Migrate Winbond W25Q16DV to FL116K AN

Migrate Winbond W25Q16DV to FL116K AN

Migration from Winbond W25Q16DV to

S25FL116K SPI Flash Family

Application Note

1.

Introduction

Spansion

®

S25FL1-K flash is a feature rich and cost-optimized serial peripheral interface (SPI) non-volatile

NOR flash family manufactured on a 90 nm 3-volt floating gate process technology node. This application note provides conversion guidelines for migrating from the Winbond

®

W25Q16DV SPI series to the Spansion

S25FL116K SPI Flash Family.

This application note is based on information available to date from data sheets and other application notes publicly available from Spansion and Winbond. Please refer also to the latest relevant specifications. The document discusses the specification differences when migrating from W25Q16DV to S25FL116K.

Publication Number Migrate_Winbond_W25Q16DV_to_FL116K_AN Revision 01 Issue Date June 9, 2014

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2.

Feature Comparison and Differences

Winbond W25Q16DV products are well suited for migration to Spansion S25FL116K products. Some of the reasons are compatible pinouts, packages, command set, and 4-kB sector structure.

Both Spansion S25FL116K and Winbond W25Q16DV devices support Single (Standard) I/O, Dual I/O, and

Quad I/O modes.

The main differences between Spansion S25FL116K and Winbond W25Q16DV are:

 Data program scheme (

See Program Method on page 4.

)

 Status register structure (

See Status Registers on page 4. )

 Block protection scheme (

See Block Protection Scheme on page 5. )

 Unique ID (

See Unique ID on page 7.

)

Feature / Parameter

Single (Standard) IO Operations

Dual IO Operations

Quad IO Operations

Standard Normal Read SCK Frequency (max)

Standard Fast Read SCK Frequency (max)

Dual Fast Read SCK Frequency (max)

Quad Fast Read SCK Frequency (max)

Wrapped Read Modes

Program Page Size

Program Suspend and Resume

Erase Suspend and Resume

Quad Page-Program

4 kB, 64 kB, and Chip Erase

32-kB Block Erase

Write Protection

Volatile Configuration

Software Reset

One Time Programmable Region(s)

Temperature Range Option

Table 2.1 High Level Feature Support Comparison

S25FL116K

50 MHz

108 MHz

108 MHz

108 MHz

256 Bytes

√ x

3 x 256 Bytes

-40°C to +85°C

-40°C to +105°C

-40°C to +125°C

W25Q16DV

50 MHz

104 MHz

104 MHz

104 MHz

256 Bytes

3 x 256 Bytes

-40°C to +85°C

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2.1

Hardware Package

The pinouts of S25FL116K and W25Q16DV are identical.

Figure 2.1

shows the SOIC packages and pinouts.

Figure 2.2

shows the TFBGA 8 x 6 mm packages and pinouts.

Refer to the data sheets for detailed package information.

HOLD#/IO3 1

VCC

NC

NC

NC

NC

CS#

SO/IO1

7

8

5

6

2

3

4

Figure 2.1 SOIC 150 / 208 / 300 mil Package and Pinout (16-Pin and 8-Pin Versions)

16

SCK

15

SI/IO0

14

13

NC

NC

12 NC

11

10

9

CS#

NC

SO/IO1

GND

W#/ACC/IO2

WP#/IO2

GND

1

2

3

4

8

VCC

7

HOLD#/IO3

6

5

CLK

SI/IO0

Figure 2.2 Ball Configuration TFBGA 8 x 6 mm Package and Pinout (Package Code TB or TC)

Top View

1 2 3 4

Top View

A

1 2 3 4 5

NC NC NC NC

A

B

NC NC NC

NC NC CLK GND VCC

B C

NC CLK GND VCC NC

NC /CS NC /WP(IO2)

C D

NC /CS NC /WP(IO2) NC

NC DO(IO1) DI(IO0) /HOLD(IO3)

D E

NC DO(IO1) DI(IO0) /HOLD(IO3)

NC NC NC NC NC

E

F

NC NC NC NC NC

NC NC NC NC

Table 2.2

summarize the available packages from Spansion and Winbond.

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SOIC8 150 mil

SOIC8 208 mil

SOIC16 300 mil

PDIP 300 mil

WSON 5x6

24-ball BGA 6 x 8 mm

(6 x 4 / 5 x 5 ball array)

KGD / KGW

Table 2.2 Spansion and Winbond Available Packages

S25FL116K

W25Q16DV

2.2

Block Structure

Both Winbond W25Q16DV and Spansion S25FL116K support 4-kB sector erase in any sector.

Winbond W25Q16DV supports both 32-kB block erase and 64-kB block erase, while Spansion S25FL116K supports 64-kB block erase only.

2.3

Program Method

Both Winbond W25Q16DV and Spansion S25FL116K support page program with program length from 1 to

256 bytes.

W25Q16DV supports Quad Page-Program, while S25FL116K does not.

2.4

Multi-I/O Operation

W25Q16DV and S25F116K support dual output read, dual I/O read, quad output read, and quad I/O.

W25Q16DV supports Word Read Quad I/O and Octal Word Read Quad I/O, while S25FL116K does not.

2.5

Status Registers

Both W25Q16DV and W25Q16DV have two status registers: SR1 and SR2.

The S25FL116K has one additional status register (SR3), which can be used to provide status on additional device features and to configure the burst wrap feature. The Write Status Register instruction allows the three status registers to be written in one command sequence. Only non-volatile status register bits SRP0, SEC,

TB, BP2, BP1, BP0 (bits 7 through 2 of Status Register-1), CMP, LB3, LB2, LB1, LB0, QE, SRP1 (bits 6 through 0 of Status Register-2), and W6, W5, W4, and LC (bits 6 through 0 of Status Register-3) can be written. All other status register bit locations are read-only and will not be affected by the Write Status

Register instruction.

4 Migrate_Winbond_W25Q16DV_to_FL116K_AN_01 June 9, 2014

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Table 2.3

illustrates the Status Register bit assignments for Winbond W25Q16DV and Spansion S25FL116K.

Bits

SR1[7]

SR1[6]

SR1[5]

SR1[4]

SR1[3]

SR1[2]

SR1[1]

SR1[0]

SR3[7]

SR3[6]

SR3[5]

SR3[4]

SR3[3]

SR3[2]

SR3[1]

SR3[0]

SR2[7]

SR2[6]

SR2[5]

SR2[4]

SR2[3]

SR2[2]

SR2[1]

SR2[0]

Table 2.3 Status Register Bit Assignments for W25Q16DV and S25FL116K

SUS

CMP

LB3

LB2

LB1

LB0

QE

SRP1

Spansion S25FL116K

Name Function

SRP0

SEC

TB

Status Register Protect0

Sector / Block Protect

Top / Bottom Protect

BP2

BP1

BP0

WEL

Block Protect Bits

BUSY

Write Enable Latch

Embedded Operation

Status

Suspend Status

Complement Protect

Security Register Lock

Bits

Quad Enable

Status Register Protect1

Reserved RFU

W6

W5

W4

Burst Wrap Length

Burst Wrap Enable

Latency Control (LC)

Variable Read Latency

Control

SUS

CMP

LB3

LB2

LB1

R

QE

SRP1

Name

Winbond W25Q16DV

Function

SRP0

SEC

TB

Status Register Protect0

Sector / Block Protect

Top / Bottom Protect

BP2

BP1

BP0

WEL

Block Protect Bits

BUSY

Write Enable Latch

Embedded Operation

Status

Suspend Status

Complement Protect

Security Register Lock

Bits

Reserved

Quad Enable

Status Register Protect1

2.6

Block Protection Scheme

Both S25FL116K and W25Q16DV have the same Block Protection Scheme. They allow all, none, or a portion of the memory array to be protected from Program and Erase instructions by way of the status register.

The Block Protect Bits (BP2-0) provide Write Protection control and status. The factory default setting for the

Block Protect Bits is 0 (none of the array is protected). The non-volatile Top/Bottom bit (TB) controls whether the Block Protect Bits (BP2-0) protect from the Top (TB=0) or the Bottom (TB=1) of the array. The non-volatile

Sector/Block Protect bit (SEC) selects whether the Block Protect Bits (BP2-0) protect 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array.

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register. It is used in conjunction with SEC, TB, and BP2-0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1, and BP0 will be reversed.

Refer to the data sheet for the valid combinations. Table 2.4

and Table 2.5

show Block Protection.

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0

0

0

0

0

0

SEC

x

0

0

0

1

1

1

1

1

1

1

0 x

1

0

0

0

1

1

1

1

1 x

0

0

0

1

0

0

0

1

1

1

TB

Status Register

BP2 BP1

x 0 0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

1

1

1

0

0

0

1

0

0

0

1

1

1

0

1

1

0

0

1

1

0

0

1

0

Table 2.4 Block Protection (CMP = 0)

0

1

1

0

1

0

BP0

0

1

0

1

0

1 x

1

0

1 x

1 x

1

Protected Portion

None

Upper 1/32

Upper 1/16

Upper 1/8

Upper 1/4

Upper 1/2

Lower 1/32

Lower 1/16

Lower 1/8

Lower 1/4

Lower 1/2

All

Upper 1/512

Upper 1/256

Upper 1/128

Upper 1/64

Lower 1/512

Lower 1/256

Lower 1/128

Lower 1/64

Protected Addresses

None

1F0000h - 1FFFFFH

1E0000h - 1FFFFFH

1C0000h - 1FFFFFH

180000h - 1FFFFFH

100000h - 1FFFFFH

000000h - 00FFFFH

000000h - 01FFFFH

000000h - 03FFFFH

000000h - 07FFFFH

000000h - 0FFFFFH

000000h - 1FFFFFH

1FF000h - 1FFFFFH

1FE000h - 1FFFFFH

1FC000h - 1FFFFFH

1F8000h - 1FFFFFH

000000h - 000FFFH

000000h - 001FFFH

000000h - 003FFFH

000000h - 007FFFH x

1

1

1

1

1

1

1

1

0

0

0

0

0

0

SEC

x

0

0

0

0 x

0

0

0

0

1

1

1

1

0

1

1

1

1

1

0

0

0

TB

x

0

Status Register

BP2

0

0

BP1

0

0

0

0

1

1

1

0

1

0

0

0

1

1

0

0

1

1

0

0

1

0

0

0

1

0

0

0

1

1

0

1

1

0

0

1

1

0 x

1

0

1 x

1

0

1 x

1

1

0

1

0

1

BP0

0

1

0

1

0

Table 2.5 Block Protection (CMP = 1)

Protected Portion

All

Lower 31/32

Lower 15/16

Lower 7/8

Lower 3/4

Lower 1/2

Upper 31/32

Upper 15/16

Upper 7/8

Upper 3/4

Lower 1/2

None

Lower 511/512

Lower 255/156

Lower 127/128

Lower 63/64

Upper 511/512

Upper 255/256

Upper 127/128

Upper 63/64

Protected Addresses

000000h - 1FFFFFH

000000h - 1EFFFFH

000000h - 1DFFFFH

000000h - 1BFFFFH

000000h - 17FFFFH

000000h - 0FFFFFH

010000h - 1FFFFFH

020000h - 1FFFFFH

040000h - 1FFFFFH

080000h - 1FFFFFH

100000h - 1FFFFFH

None

000000h - 1FEFFFH

000000h - 1FDFFFH

000000h - 1FBFFFH

000000h - 1F7FFFH

001000h - 1FFFFFH

002000h - 1FFFFFH

004000h - 1FFFFFH

008000h - 1FFFFFH

Migrate_Winbond_W25Q16DV_to_FL116K_AN_01 June 9, 2014

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2.7

Variable Latency

Spansion S25FL116K adds support for variable latency read timing. You can use the default latency code value when migrating from Winbond products to S25FL116K without any change in read timing. Or you can set latency code (SR3[3-0]) and change read timing to enable faster initial access time or higher clock rate read commands. See full feature details in the S25FL116K data sheet .

2.8

Burst Read Mode

Both W25Q16DV and S25FL116K support Set Burst with Wrap command (77H) preceding the Fast Read

Quad I/O command. See full feature details in data sheet.

Spansion S25FL116K supports Fast Read Quad I/O (EBh) in Burst with Wrap mode. Status Register-3 provides a bit (SR3[4]) to enable a read with wrap option for the Read Quad I/O command. To set burst length, Status Register-3 provides bits (SR3[6:5]) to select the alignment boundary. Burst wrap length can be aligned on 8-, 16-, 32-, or 64-byte boundaries.

2.9

OTP (One-Time Program) Area

Both S25FL116K and W25Q16DV provide three 256-byte Security Registers. Each security register can be read (opcode 48h), programmed (opcode 42h), erased (opcode 44h), and permanently locked by setting

Status Register bits LB1, LB2, and LB3 to 1.

2.10

Reset Operations

W25Q16DV supports software reset operation. It is used to put the device in normal operating ready mode.

This operation consists of two commands: Enable Reset (66h) and Reset (99h).

S25FL116K does not have a hardware Reset pin. If the host system memory controller resets without a complete power down and power up sequence, while S25FL116K is set to Continuous Mode Read,

S25FL116K will not recognize any initial standard SPI commands from the controller. To address this possibility, it is recommended to issue a Continuous Read Mode Reset (FFFFh) command as the first command after a system Reset. Doing so will release the device from the Continuous Read Mode and allow

Standard SPI commands to be recognized.

If Burst Wrap Mode is used, it is also recommended to issue a Set Burst with Wrap (77h) command that sets the W4 bit to one as the second command after a system Reset. Doing so will release the device from the

Burst Wrap Mode and allow standard sequential read SPI command operation.

Issuing these commands immediately after a non-power-cycle (warm) system reset ensures the device operation is consistent with the power-on default device operation.

2.11

Unique ID

Both S25FL116K and W25Q16DV provide 8-byte unique ID. This is a factory-set read-only number that is unique to each device. The S25FL116K uses command 5Ah to access Read Unique ID Number, and access flow is: opcode 5A -> offset F8h to FFh -> 1 dummy byte -> 64bit unique ID.

W25Q16DV uses command 4Bh to access Unique ID Number, and access flow is: opcode 4B -> 4 dummy bytes -> 64-bit unique ID.

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3.

Command Set Comparison

W25Q16DV and S25FL116K share similar instructions (op-codes) in their command-set, which determine a compatible set of internal algorithms. Nevertheless, not all commands are supported when comparing one product family with the other.

Table 3.1

shows a comparison summary of the command set of a Spansion S25FL116K and Winbond

W25Q16DV.

Table 3.1 Command Set of S25FL116K and W25Q16DV

Command Description

Read Status Register-1

Read Status Register-2

Read Status Register-3

Write Enable

Write Enable for Volatile Status Register

Write Disable

Write Status Registers

Set Burst with Wrap

Page Program

Quad Page Program

Sector Erase (4 kB)

Block Erase (32 kB)

Block Erase (64 kB)

Chip Erase

Suspends Program / Erase

Resumes Program / Erase

Read Data

Fast Read

Fast Read Dual Output

Fast Read Quad Output

Fast Read Dual I/O

Fast Read Quad I/O

Continuous Read Mode Reset

Word Read Quad I/O

Octal Word Read Quad I/O

S25FL116 Opcode

Configuration, Status, Erase, and Program Commands

05h

35h

33h

06h

50h

04h

01h

77h

02h

20h

D8h

C7h / 60h

75h

7Ah

03h

0Bh

3Bh

6Bh

BBh

EBh

FFh

ID, Security, and Other Commands

Deep Power-Down

Release Power-Down / Device ID

Manufacturer / Device ID

JEDEC ID Read

Dual I/O JEDEC ID Read

Quad I/O JEDEC ID Read

Read SFDP Register

Read Security Registers

Erase Security Registers

Program Security Registers

Read Unique ID

Enable Reset

Reset

5Ah

48h

B9h

ABh

90h

9Fh

44h

42h

5Ah

W25Q16DV Opcode

02h

32h

20h

52h

D8h

C7h / 60h

75h

7Ah

50h

04h

01h

77h

05h

35h

06h

BBh

EBh

FFh

E7h

E3h

03h

0Bh

3Bh

6Bh

B9h

ABh

90h

9Fh

92h

94h

5Ah

48h

44h

42h

4Bh

66h

99h

Migrate_Winbond_W25Q16DV_to_FL116K_AN_01 June 9, 2014

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4.

Timing Considerations

4.1

Power-Up Timing

One of the most sensitive electrical specifications is the power-up timing needed to correctly initialize the

device. Table 4.1

and Figure 4.1

show the power-up characteristics of S25FL116K and W25Q16DV.

Figure 4.2

show the power-down characteristics of S25FL116K.

Parameter

V

CC(min)

to CS# Low

Time Delay Before Write Command

Write Inhibit Threshold Voltage

Power-Down Time

V

CC

Power-Down Reset Threshold Voltage

Table 4.1 Power-Up Timing Requirement

Symbol

t

VSL t

PUW

V

WI t

PD

V

CC

Low

S25FL116K

Min Max

10

10

2.4

10

1.0

W25Q16DV

Min Max

20

5

1.0

x x

2.0

x x

Unit

µs ms

V

µs

V

Figure 4.1 Power-Up Timing and Voltage Levels

VCC

VCC (max)

VCC (min)

Reset

State

Program, Erase, and Write instructions are ignored

CS# must track VCC t

VSL

Read instructions allowed

Device is fully accessible

VWI t

PUW

Time

Figure 4.2 Power-Down and Voltage Drop

Vcc

(Max)

Vcc

(Min)

Vcc

Vcc

(Low)

No Device Access Allowed tVSL Device Read

Allowed tPD

Time

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4.2

Data In Setup/Hold Time

Two AC timing parameters that are critical in SPI designs are Data-In Setup Time and Data-In Hold Time.

They specify how long data needs to be valid before and after the rising edge of the clock signal, respectively.

The minor different requirement should not be an issue in the design but may just need to be verified.

Table 4.2

shows the Data-In Setup / Hold timing characteristics for both S25FL116K and Winbond devices.

Parameter

Data-In Setup Time

Data-In Hold Time

Table 4.2 Data-In Setup / Hold Timing Characteristics Comparison

S25FL116K W25Q16DV

Min

2

5

2

3

Unit

ns ns

4.3

Further Timing Comparison

In general, the timing characteristics of both Winbond and Spansion flash families are almost identical with just a little deviation.

One difference is that the S25FL116K family has a faster CS# deselect time than W25Q16DV. There is no need to do any changes but it's important to note that read performance of the application can be increased easily here.

When SPI clock frequency is 80 MHz, CS# deselect time for read after writes of W25Q16DV is 12.5 ns minimum. The minor different requirement should not be an issue in the design but may just need to be verified when migrating from W25Q16DV to S25FL116K.

Table 4.3

shows a comparison between S25FL116K and W25Q16DV with regards to the various CS# deselect times.

Table 4.3 CS# Deselect Timing Characteristics Comparison

S25FL116K

Parameter

W25Q16DV

Min

CS# deselect time between Reads

CS# deselect time for Read after Writes

7

40

10

50

Unit

ns ns

5.

Conclusion

Migrating from Winbond W25Q16DV to the Spansion S25FL116K is straightforward and requires minimal accommodation in regards to either system software or hardware.

Additionally, once accommodations are made, if required, S25FL116K flash will enable access to a wider range of SPI flash features and superior read throughput up to 54 Mbytes/s using Quad bit data path.

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6.

Revision History

Section

Revision 01 (June 9, 2014)

Initial release

Description

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Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document.

Copyright © 2014 Spansion LLC. All rights reserved. Spansion

®

, the Spansion logo, MirrorBit

®

, MirrorBit

®

Eclipse

, ORNAND

, HyperBus

,

HyperFlash

and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.

Other names used are for informational purposes only and may be trademarks of their respective owners.

12 Migrate_Winbond_W25Q16DV_to_FL116K_AN_01 June 9, 2014

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