Datasheet RL78/G13 RENESAS MCU

Datasheet  RL78/G13 RENESAS MCU
Datasheet
RL78/G13
R01DS0131EJ0200
Rev.2.00
Oct 12, 2012
RENESAS MCU
True Low Power Platform (as low as 66 µA/MHz, and 0.57 µA for RTC + LVD), 1.6 V to 5.5 V
operation, 16 to 512 Kbyte Flash, 41 DMIPS at 32 MHz, for General Purpose Applications
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
• 1.6 V to 5.5 V operation from a single supply
• Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31
µA
• Halt (RTC + LVD): 0.57 µA
• Snooze: 0.70 mA (UART), 1.20 mA (ADC)
• Operating: 66 µA/MHz
16-bit RL78 CPU Core
• Delivers 41 DMIPS at maximum operating frequency
of 32 MHz
• Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Main Flash Memory
• Density: 16 KB to 512 KB
• Block size: 1 KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with secure boot swap function
and flash shield window function
Data Flash Memory
• Data Flash with background operation
• Data flash size: 4 KB to 8 KB size options
• Erase Cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 5.5 V
RAM
• 2 KB to 32 KB size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed On-chip Oscillator
• 32 MHz with +/− 1% accuracy over voltage (1.8 V to
5.5 V) and temperature (−20 °C to 85 °C)
• Pre-configured settings: 32 MHz, 24 MHz, 16 MHz,
12 MHz, 8 MHz, 4 MHz & 1 MHz
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 14 setting options
(Interrupt and/or reset function)
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Data Memory Access (DMA) Controller
• Up to 4 fully programmable channels
• Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
• Up to 8 x I2C master
2
• Up to 2 x I C multi-master
• Up to 8 x CSI/SPI (7-, 8-bit)
• Up to 4 x UART (7-, 8-, 9-bit)
• Up to 1 x LIN
Extended-Function Timers
• Multi-function 16-bit timers: Up to 16 channels
• Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• Interval Timer: 12-bit, 1 channel
• 15 kHz watchdog timer : 1 channel (window function)
Rich Analog
• ADC: Up to 26 channels, 10-bit resolution, 2.1 µs
conversion time
• Supports 1.6 V
• Internal voltage reference (1.45 V)
• On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock stop/ frequency detection
• ADC self-test
General Purpose I/O
• 5V tolerant, high-current (up to 20 mA per pin)
• Open-Drain, Internal Pull-up support
Operating Ambient Temperature
• Standard: −40 °C to +85 °C
• Extended: −40 °C to +105 °C
Package Type and Pin Count
From 3mm x 3mm to 14mm x 20mm
QFP: 44, 48, 52, 64, 80, 100, 128
QFN: 24, 32, 40, 48
SSOP: 20, 30
LGA: 25, 36
BGA: 64
Page 1 of 124
RL78/G13
CHAPTER 1 OUTLINE
 ROM, RAM capacities
Flash
Data
ROM
flash
128
8 KB
KB
RAM
RL78/G13
20 pins
24 pins
25 pins
30 pins
32 pins
36 pins
12
−
−
−
R5F100AG
R5F100BG
R5F100CG
−
KB
−
−
−
R5F101AG
R5F101BG
R5F101CG
96
8 KB
8 KB
−
−
−
R5F100AF
R5F100BF
R5F100CF
KB
−
−
−
−
R5F101AF
R5F101BF
R5F101CF
64
4 KB
4 KB
R5F1006E
R5F1007E
R5F1008E
R5F100AE
R5F100BE
R5F100CE
KB
−
Note 1
R5F1016E
R5F1017E
R5F1018E
R5F101AE
R5F101BE
R5F101CE
48
4 KB
3 KB
R5F1006D
R5F1007D
R5F1008D
R5F100AD
R5F100BD
R5F100CD
KB
−
R5F1016D
R5F1017D
R5F1018D
R5F101AD
R5F101BD
R5F101CD
32
4 KB
R5F1006C
R5F1007C
R5F1008C
R5F100AC
R5F100BC
R5F100CC
KB
−
R5F1016C
R5F1017C
R5F1018C
R5F101AC
R5F101BC
R5F101CC
16
4 KB
R5F1006A
R5F1007A
R5F1008A
R5F100AA
R5F100BA
R5F100CA
KB
−
R5F1016A
R5F1017A
R5F1018A
R5F101AA
R5F101BA
R5F101CA
Flash
Data
ROM
flash
512
8 KB
KB
2 KB
2 KB
RAM
RL78/G13
40 pins
44 pins
48 pins
52 pins
64 pins
80 pins
100 pins
128 pins
32 KB
−
R5F100FL
R5F100GL
R5F100JL
R5F100LL
R5F100ML
R5F100PL
R5F100SL
−
Note 3
−
R5F101FL
R5F101GL
R5F101JL
R5F101LL
R5F101ML
R5F101PL
R5F101SL
384
8 KB
24 KB
−
R5F100FK
R5F100GK
R5F100JK
R5F100LK
R5F100MK R5F100PK
R5F100SK
KB
−
−
R5F101FK
R5F101GK
R5F101JK
R5F101LK
R5F101MK R5F101PK
R5F101SK
256
8 KB
20 KB
−
R5F100FJ
R5F100GJ
R5F100JJ
R5F100LJ
R5F100MJ
R5F100PJ
R5F100SJ
KB
−
Note 2
−
R5F101FJ
R5F101GJ
R5F101JJ
R5F101LJ
R5F101MJ
R5F101PJ
R5F101SJ
192
8 KB
16 KB
R5F100EH
R5F100FH R5F100GH
R5F100JH
R5F100LH R5F100MH R5F100PH
R5F100SH
KB
−
R5F101EH
R5F101FH R5F101GH
R5F101JH
R5F101LH R5F101MH R5F101PH
R5F101SH
128
8 KB
R5F100EG R5F100FG R5F100GG R5F100JG
R5F100LG R5F100MG R5F100PG
−
KB
−
R5F101EG R5F101FG R5F101GG R5F101JG
R5F101LG R5F101MG R5F101PG
−
96
8 KB
R5F100EF
R5F100FF
R5F100GF
R5F100JF
R5F100LF
R5F100MF
R5F100PF
−
KB
−
R5F101EF
R5F101FF
R5F101GF
R5F101JF
R5F101LF
R5F101MF
R5F101PF
−
64
4 KB
4 KB
R5F100EE
R5F100FE
R5F100GE
R5F100JE
R5F100LE
−
−
−
KB
−
Note 1
R5F101EE
R5F101FE
R5F101GE
R5F101JE
R5F101LE
−
−
−
48
4 KB
3 KB
R5F100ED
R5F100FD R5F100GD
R5F100JD
R5F100LD
−
−
−
KB
−
R5F101ED
R5F101FD R5F101GD
R5F101JD
R5F101LD
−
−
−
32
4 KB
R5F100EC
R5F100FC R5F100GC
R5F100JC
R5F100LC
−
−
−
KB
−
R5F101EC
R5F101FC R5F101GC
R5F101JC
R5F101LC
−
−
−
16
4 KB
R5F100EA
R5F100FA
R5F100GA
−
−
−
−
−
KB
−
R5F101EA
R5F101FA
R5F101GA
−
−
−
−
−
12 KB
8 KB
2 KB
2 KB
Notes 1. This is about 3 KB when the self-programming function and data flash function are used.
2. This is about 19 KB when the self-programming function and data flash function are used.
3. This is about 31 KB when the self-programming function and data flash function are used.
R01DS0131EJ0200 Rev.2.00
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Page 2 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.2 Ordering Information
• Flash memory version (lead-free product)
(1/4)
Pin count
20 pins
Package
20-pin plastic SSOP
Data flash
Mounted
(7.62 mm (300))
Part Number
R5F1006AASP, R5F1006CASP, R5F1006DASP, R5F1006EASP
R5F1006ADSP, R5F1006CDSP, R5F1006DDSP, R5F1006EDSP
Not mounted
R5F1016AASP, R5F1016CASP, R5F1016DASP, R5F1016EASP
R5F1016ADSP, R5F1016CDSP, R5F1016DDSP, R5F1016EDSP
24 pins
24-pin plastic WQFN
Mounted
(fine pitch) (4 × 4)
R5F1007AANA, R5F1007CANA, R5F1007DANA, R5F1007EANA
R5F1007ADNA, R5F1007CDNA, R5F1007DDNA, R5F1007EDNA
Not mounted
R5F1017AANA, R5F1017CANA, R5F1017DANA, R5F1017EANA
R5F1017ADNA, R5F1017CDNA, R5F1017DDNA, R5F1017EDNA
25 pins
25-pin plastic FLGA
Mounted
(3 × 3)
R5F1008AALA, R5F1008CALA, R5F1008DALA, R5F1008EALA
R5F1008ADLA, R5F1008CDLA, R5F1008DDLA, R5F1008EDLA
Not mounted
R5F1018AALA, R5F1018CALA, R5F1018DALA, R5F1018EALA
R5F1018ADLA, R5F1018CDLA, R5F1018DDLA, R5F1018EDLA
30 pins
30-pin plastic SSOP
Mounted
R5F100AAASP, R5F100ACASP, R5F100ADASP,
R5F100AEASP, R5F100AFASP, R5F100AGASP
(7.62 mm (300))
R5F100AADSP, R5F100ACDSP, R5F100ADDSP, R5F100AEDSP,
R5F100AFDSP, R5F100AGDSP
Not mounted
R5F101AAASP, R5F101ACASP, R5F101ADASP,
R5F101AEASP, R5F101AFASP, R5F101AGASP
R5F101AADSP, R5F101ACDSP, R5F101ADDSP, R5F101AEDSP,
R5F101AFDSP, R5F101AGDSP
32 pins
32-pin plastic WQFN
Mounted
(fine pitch)(5 × 5)
R5F100BAANA, R5F100BCANA, R5F100BDANA, R5F100BEANA,
R5F100BFANA, R5F100BGANA
R5F100BADNA, R5F100BCDNA, R5F100BDDNA,
R5F100BEDNA, R5F100BFDNA, R5F100BGDNA
Not mounted
R5F101BAANA, R5F101BCANA, R5F101BDANA, R5F101BEANA,
R5F101BFANA, R5F101BGANA
R5F101BADNA, R5F101BCDNA, R5F101BDDNA,
R5F101BEDNA, R5F101BFDNA, R5F101BGDNA
36 pins
36-pin plastic FLGA
Mounted
(4 × 4)
R5F100CAALA, R5F100CCALA, R5F100CDALA, R5F100CEALA,
R5F100CFALA, R5F100CGALA
R5F100CADLA, R5F100CCDLA, R5F100CDDLA, R5F100CEDLA,
R5F100CFDLA, R5F100CGDLA
Not mounted
R5F101CAALA, R5F101CCALA, R5F101CDALA, R5F101CEALA,
R5F101CFALA, R5F101CGALA
R5F101CADLA, R5F101CCDLA, R5F101CDDLA, R5F101CEDLA,
R5F101CFDLA, R5F101CGDLA
R01DS0131EJ0200 Rev.2.00
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Page 3 of 124
RL78/G13
CHAPTER 1 OUTLINE
(2/4)
Pin count
40 pins
Package
40-pin plastic WQFN
Data flash
Mounted
(fine pitch)(6 × 6)
Part Number
R5F100EAANA, R5F100ECANA, R5F100EDANA, R5F100EEANA,
R5F100EFANA, R5F100EGANA, R5F100EHANA
R5F100EADNA, R5F100ECDNA, R5F100EDDNA, R5F100EEDNA,
R5F100EFDNA, R5F100EGDNA, R5F100EHDNA
Not mounted
R5F101EAANA, R5F101ECANA, R5F101EDANA, R5F101EEANA,
R5F101EFANA, R5F101EGANA, R5F101EHANA
R5F101EADNA, R5F101ECDNA, R5F101EDDNA, R5F101EEDNA,
R5F101EFDNA, R5F101EGDNA, R5F101EHDNA
44 pins
44-pin plastic LQFP
Mounted
(10 × 10)
R5F100FAAFP, R5F100FCAFP, R5F100FDAFP, R5F100FEAFP,
R5F100FFAFP, R5F100FGAFP, R5F100FHAFP, R5F100FJAFP,
R5F100FKAFP, R5F100FLAFP
R5F100FADFP, R5F100FCDFP, R5F100FDDFP, R5F100FEDFP,
R5F100FFDFP, R5F100FGDFP, R5F100FHDFP, R5F100FJDFP,
R5F100FKDFP, R5F100FLDFP
Not mounted
R5F101FAAFP, R5F101FCAFP, R5F101FDAFP, R5F101FEAFP,
R5F101FFAFP, R5F101FGAFP, R5F101FHAFP, R5F101FJAFP,
R5F101FKAFP, R5F101FLAFP
R5F101FADFP, R5F101FCDFP, R5F101FDDFP, R5F101FEDFP,
R5F101FFDFP, R5F101FGDFP, R5F101FHDFP, R5F101FJDFP,
R5F101FKDFP, R5F101FLDFP
48 pins
48-pin plastic LQFP
Mounted
(fine pitch) (7 × 7)
R5F100GAAFB, R5F100GCAFB, R5F100GDAFB, R5F100GEAFB,
R5F100GFAFB, R5F100GGAFB, R5F100GHAFB, R5F100GJAFB,
R5F100GKAFB, R5F100GLAFB
R5F100GADFB, R5F100GCDFB, R5F100GDDFB, R5F100GEDFB,
R5F100GFDFB, R5F100GGDFB, R5F100GHDFB, R5F100GJDFB,
R5F100GKDFB, R5F100GLDFB
Not mounted
R5F101GAAFB, R5F101GCAFB, R5F101GDAFB, R5F101GEAFB,
R5F101GFAFB, R5F101GGAFB, R5F101GHAFB, R5F101GJAFB,
R5F101GKAFB, R5F101GLAFB
R5F101GADFB, R5F101GCDFB, R5F101GDDFB, R5F101GEDFB,
R5F101GFDFB, R5F101GGDFB, R5F101GHDFB, R5F101GJDFB,
R5F101GKDFB, R5F101GLDFB
48-pin plastic WQFN
Mounted
(7 × 7)
R5F100GAANA, R5F100GCANA, R5F100GDANA, R5F100GEANA,
R5F100GFANA, R5F100GGANA, R5F100GHANA, R5F100GJANA,
R5F100GKANA, R5F100GLANA
R5F100GADNA, R5F100GCDNA, R5F100GDDNA, R5F100GEDNA,
R5F100GFDNA, R5F100GGDNA, R5F100GHDNA, R5F100GJDNA,
R5F100GKDNA, R5F100GLDNA
Not mounted
R5F101GAANA, R5F101GCANA, R5F101GDANA, R5F101GEANA,
R5F101GFANA, R5F101GGANA, R5F101GHANA, R5F101GJANA,
R5F101GKANA, R5F101GLANA
R5F101GADNA, R5F101GCDNA, R5F101GDDNA, R5F101GEDNA,
R5F101GFDNA, R5F101GGDNA, R5F101GHDNA, R5F101GJDNA,
R5F101GKDNA, R5F101GLDNA
R01DS0131EJ0200 Rev.2.00
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Page 4 of 124
RL78/G13
CHAPTER 1 OUTLINE
(3/4)
Pin count
52 pins
Package
52-pin plastic LQFP
Data flash
Mounted
(10 × 10)
Part Number
R5F100JCAFA, R5F100JDAFA, R5F100JEAFA, R5F100JFAFA,
R5F100JGAFA, R5F100JHAFA, R5F100JJAFA, R5F100JKAFA,
R5F100JLAFA
R5F100JCDFA, R5F100JDDFA, R5F100JEDFA, R5F100JFDFA,
R5F100JGDFA, R5F100JHDFA, R5F100JJDFA, R5F100JKDFA,
R5F100JLDFA
Not mounted
R5F101JCAFA, R5F101JDAFA, R5F101JEAFA, R5F101JFAFA,
R5F101JGAFA, R5F101JHAFA, R5F101JJAFA, R5F101JKAFA,
R5F101JLAFA
R5F101JCDFA, R5F101JDDFA, R5F101JEDFA, R5F101JFDFA,
R5F101JGDFA, R5F101JHDFA, R5F101JJDFA, R5F101JKDFA,
R5F101JLDFA
64 pins
64-pin plastic LQFP
Mounted
(12 × 12)
R5F100LCAFA, R5F100LDAFA, R5F100LEAFA, R5F100LFAFA,
R5F100LGAFA, R5F100LHAFA, R5F100LJAFA, R5F100LKAFA,
R5F100LLAFA
R5F100LCDFA, R5F100LDDFA, R5F100LEDFA, R5F100LFDFA,
R5F100LGDFA, R5F100LHDFA, R5F100LJDFA, R5F100LKDFA,
R5F100LLDFA
Not mounted
R5F101LCAFA, R5F101LDAFA, R5F101LEAFA, R5F101LFAFA,
R5F101LGAFA, R5F101LHAFA, R5F101LJAFA, R5F101LKAFA,
R5F101LLAFA
R5F101LCDFA, R5F101LDDFA, R5F101LEDFA, R5F101LFDFA,
R5F101LGDFA, R5F101LHDFA, R5F101LJDFA, R5F101LKDFA,
R5F101LLDFA
64-pin plastic LQFP
Mounted
(fine pitch) (10 × 10)
R5F100LCAFB, R5F100LDAFB, R5F100LEAFB, R5F100LFAFB,
R5F100LGAFB, R5F100LHAFB, R5F100LJAFB, R5F100LKAFB,
R5F100LLAFB
R5F100LCDFB, R5F100LDDFB, R5F100LEDFB, R5F100LFDFB,
R5F100LGDFB, R5F100LHDFB, R5F100LJDFB, R5F100LKDFB,
R5F100LLDFB
Not mounted
R5F101LCAFB, R5F101LDAFB, R5F101LEAFB, R5F101LFAFB,
R5F101LGAFB, R5F101LHAFB, R5F101LJAFB, R5F101LKAFB,
R5F101LLAFB
R5F101LCDFB, R5F101LDDFB, R5F101LEDFB, R5F101LFDFB,
R5F101LGDFB, R5F101LHDFB, R5F101LJDFB, R5F101LKDFB,
R5F101LLDFB
64-pin plastic FBGA
Mounted
(4 × 4)
R5F100LCABG, R5F100LDABG, R5F100LEABG, R5F100LFABG,
R5F100LGABG, R5F100LHABG, R5F100LJABG
R5F100LCDBG, R5F100LDDBG, R5F100LEDBG, R5F100LFDBG,
R5F100LGDBG, R5F100LHDBG, R5F100LJDBG
Not mounted
R5F101LCABG, R5F101LDABG, R5F101LEABG, R5F101LFABG,
R5F101LGABG, R5F101LHABG, R5F101LJABG
R5F101LCDBG, R5F101LDDBG, R5F101LEDBG, R5F101LFDBG,
R5F101LGDBG, R5F101LHDBG, R5F101LJDBG
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Page 5 of 124
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CHAPTER 1 OUTLINE
(4/4)
Pin count
80 pins
Package
80-pin plastic LQFP
Data flash
Mounted
(14 × 14)
Part Number
R5F100MFAFA, R5F100MGAFA, R5F100MHAFA, R5F100MJAFA,
R5F100MKAFA, R5F100MLAFA
R5F100MFDFA, R5F100MGDFA, R5F100MHDFA,
R5F100MJDFA, R5F100MKDFA, R5F100MLDFA
Not mounted
R5F101MFAFA, R5F101MGAFA, R5F101MHAFA, R5F101MJAFA,
R5F101MKAFA, R5F101MLAFA
R5F101MFDFA, R5F101MGDFA, R5F101MHDFA,
R5F101MJDFA, R5F101MKDFA, R5F101MLDFA
80-pin plastic LQFP
Mounted
(fine pitch) (12 × 12)
R5F100MFAFB, R5F100MGAFB, R5F100MHAFB, R5F100MJAFB,
R5F100MKAFB, R5F100MLAFB
R5F100MFDFB, R5F100MGDFB, R5F100MHDFB,
R5F100MJDFB, R5F100MKDFB, R5F100MLDFB
Not mounted
R5F101MFAFB, R5F101MGAFB, R5F101MHAFB, R5F101MJAFB,
R5F101MKAFB, R5F101MLAFB
R5F101MFDFB, R5F101MGDFB, R5F101MHDFB,
R5F101MJDFB, R5F101MKDFB, R5F101MLDFB
100 pins
100-pin plastic LQFP
Mounted
(fine pitch) (14 × 14)
R5F100PFAFB, R5F100PGAFB, R5F100PHAFB, R5F100PJAFB,
R5F100PKAFB, R5F100PLAFB
R5F100PFDFB, R5F100PGDFB, R5F100PHDFB, R5F100PJDFB,
R5F100PKDFB, R5F100PLDFB
Not mounted
R5F101PFAFB, R5F101PGAFB, R5F101PHAFB, R5F101PJAFB,
R5F101PKAFB, R5F101PLAFB
R5F101PFDFB, R5F101PGDFB, R5F101PHDFB, R5F101PJDFB,
R5F101PKDFB, R5F101PLDFB
100-pin plastic LQFP
Mounted
(14 × 20)
R5F100PFAFA, R5F100PGAFA, R5F100PHAFA, R5F100PJAFA,
R5F100PKAFA, R5F100PLAFA
R5F100PFDFA, R5F100PGDFA, R5F100PHDFA, R5F100PJDFA,
R5F100PKDFA, R5F100PLDFA
Not mounted
R5F101PFAFA, R5F101PGAFA, R5F101PHAFA, R5F101PJAFA,
R5F101PKAFA, R5F101PLAFA
R5F101PFDFA, R5F101PGDFA, R5F101PHDFA, R5F101PJDFA,
R5F101PKDFA, R5F101PLDFA
128 pins
128-pin plastic LQFP
Mounted
(fine pitch) (14 × 20)
R5F100SHAFB, R5F100SJAFB, R5F100SKAFB, R5F100SLAFB
R5F100SHDFB, R5F100SJDFB, R5F100SKDFB, R5F100SLDFB
Not mounted
R5F101SHAFB, R5F101SJAFB, R5F101SKAFB, R5F101SLAFB
R5F101SHDFB, R5F101SJDFB, R5F101SKDFB, R5F101SLDFB
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Page 6 of 124
RL78/G13
CHAPTER 1 OUTLINE
Figure 1-1. Part Number, Memory Size, and Package of RL78/G13
Part No. R 5 F 1 0 0 L E A x x x F B
Package type:
SP : SSOP, 0.65 mm pitch
FP : LQFP, 0.80 mm pitch
FA : LQFP, 0.65 mm pitch
FB : LQFP, 0.50 mm pitch
NA : WQFN, 0.50 mm pitch
LA : LGA, 0.50 mm pitch
BG : FBGA, 0.40 mm pitch
ROM number (Omitted with blank products)
Classification:
A : Consumer applications, operating ambient temperature : -40˚C to 85˚C
D : Industrial applications, operating ambient temperature : -40˚C to 85˚C
ROM capacity:
A : 16 KB
C : 32 KB
D : 48 KB
E : 64 KB
F : 96 KB
G : 128 KB
H : 192 KB
J : 256 KB
K : 384 KB
L : 512 KB
Pin count:
<R>
6 :
7 :
8 :
A :
B :
C :
E :
F :
G:
J :
L :
M:
P :
S :
20-pin
24-pin
25-pin
30-pin
32-pin
36-pin
40-pin
44-pin
48-pin
52-pin
64-pin
80-pin
100-pin
128-pin
RL78/G13 group
100 : Data flash is provided
101 : Data flash is not provided
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
Remark
For details about extended-temperature products (operating ambient temperature: −40°C to 105°C),
contact a Renesas Electronics Corporation or an authorized Renesas Electronics Corporation
distributor.
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1.3 Pin Configuration (Top View)
1.3.1 20-pin products
• 20-pin plastic SSOP (7.62 mm (300))
P01/ANI16/TO00/RxD1
P00/ANI17/TI00/TxD1
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2
P147/ANI18
P10/SCK00/SCL00
P11/SI00/RxD0/TOOLRxD/SDA00
P12/SO00/TxD0/TOOLTxD
P16/TI01/TO01/INTP5/SO11
P17/TI02/TO02/SI11/SDA11
P30/INTP3/SCK11/SCL11
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remark
For pin identification, see 1.4 Pin Identification.
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1.3.2 24-pin products
P22/ANI2
P147/ANI18
P10/SCK00/SCL00
P11/SI00/RxD0/TOOLRxD/SDA00
P12/SO00/TxD0/TOOLTxD
P16/TI01/TO01/INTP5
• 24-pin plastic WQFN (fine pitch) (4 × 4)
exposed die pad
18 17 16 15 14 13
19
12
20
11
21
10
22
9
23
8
24
7
1 2 3 4 5 6
P17/TI02/TO02/SO11
P50/INTP1/SI11/SDA11
P30/INTP3/SCK11/SCL11
P31/TI03/TO03/INTP4/PCLBUZ0
P61/SDAA0
P60/SCLA0
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1
P00/ANI17/TI00/TxD1
P40/TOOL0
RESET
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remark
For pin identification, see 1.4 Pin Identification.
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CHAPTER 1 OUTLINE
1.3.3 25-pin products
• 25-pin plastic FLGA (3 × 3)
Bottom View
Top View
5
4
3
2
1
A
B
C
D
E
E
A
B
RESET
5
4
P122/X2/
EXCLK
P137/INTP0
P121/X1
VDD
3
REGC
VSS
2
P60/SCLA0
P61/SDAA0
1
A
B
C
B
A
INDEX MARK
INDEX MARK
P40/TOOL0
D
C
D
E
P01/ANI16/
TO00/RxD1
P22/ANI2
P00/ANI17/
TI00/TxD1
P21/ANI1/
AVREFM
P10/SCK00/
SCL00
P20/ANI0/
AVREFP
P12/SO00/
TxD0/
TOOLTxD
P30/INTP3/
SCK11/SCL11
P17/TI02/
TO02/SO11
P11/SI00/
RxD0/
TOOLRxD/
SDA00
P50/INTP1/
SI11/SDA11
P31/TI03/
TO03/INTP4/
PCLBUZ0
P16/TI01/
TO01/INTP5
C
P147/ANI18
5
D
4
3
2
P130
1
E
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remark
For pin identification, see 1.4 Pin Identification.
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1.3.4 30-pin products
• 30-pin plastic SSOP (7.62 mm (300))
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1
P00/ANI17/TI00/TxD1
P120/ANI19
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P60/SCLA0
P61/SDAA0
P31/TI03/TO03/INTP4/PCLBUZ0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P147/ANI18
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RXD0)
P17/TI02/TO02/(TXD0)
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
P30/INTP3/SCK11/SCL11
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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1.3.5 32-pin products
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RXD0)
P17/TI02/TO02/(TXD0)
• 32-pin plastic WQFN (5 × 5)
exposed die pad
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1 2 3 4 5 6 7 8
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
P30/INTP3/SCK11/SCL11
P70
P31/TI03/TO03/INTP4/PCLBUZ0
P62
P61/SDAA0
P60/SCLA0
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P147/ANI18
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1
P00/ANI17/TI00/TxD1
P120/ANI19
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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CHAPTER 1 OUTLINE
1.3.6 36-pin products
• 36-pin plastic FLGA (4 × 4)
Top View
Bottom View
6
5
4
3
2
1
A
B
C
D
E
F
F
E
D
C
B
A
INDEX MARK
A
B
P60/SCLA0
C
P121/X1
VDD
D
P122/X2/EXCLK
E
P137/INTP0
F
P40/TOOL0
6
6
P62
P61/SDAA0
VSS
REGC
RESET
P120/ANI19
5
5
P72/SO21
P71/SI21/
SDA21
P14/RxD2/SI20/
SDA20/(SCLA0)
/(TI03)/(TO03)
P31/TI03/TO03/
INTP4/
PCLBUZ0
P00/TI00/TxD1
P50/INTP1/
SI11/SDA11
P70/SCK21/
SCL21
P15/PCLBUZ1/
SCK20/SCL20/
(TI02)/(TO02)
P22/ANI2
P20/ANI0/
AVREFP
P21/ANI1/
AVREFM
P30/INTP3/
SCK11/SCL11
P16/TI01/TO01/
INTP5/(RxD0)
P12/SO00/
TxD0/TOOLTxD
/(TI05)/(TO05)
P11/SI00/RxD0/
TOOLRxD/
SDA00/(TI06)/
(TO06)
P24/ANI4
P23/ANI3
P51/INTP2/
SO11
P17/TI02/TO02/
(TxD0)
P13/TxD2/
SO20/(SDAA0)/
(TI04)/(TO04)
P10/SCK00/
SCL00/(TI07)/
(TO07)
P147/ANI18
B
C
4
3
2
1
A
D
P01/TO00/RxD1
4
3
2
P25/ANI5
1
E
F
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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1.3.7 40-pin products
P147/ANI18
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RXD0)
P17/TI02/TO02/(TXD0)
P51/INTP2/SO11
• 40-pin plastic WQFN (6 × 6)
30 29 28 27 26 25 24 23 22 21
31
20
exposed die pad
32
19
33
18
34
17
35
16
36
15
37
14
38
13
39
12
40
11
1 2 3 4 5 6 7 8 9 10
P50/INTP1/SI11/SDA11
P30/INTP3/RTC1HZ/SCK11/SCL11
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0
P62
P61/SDAA0
P60/SCLA0
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1
P00/TI00/TxD1
P120/ANI19
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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1.3.8 44-pin products
P147/ANI18
P146
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RXD0)
P17/TI02/TO02/(TXD0)
P51/INTP2/SO11
• 44-pin plastic LQFP (10 × 10)
33 32 31 30 29 28 27 26 25 24 23
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1 2 3 4 5 6 7 8 9 10 11
P50/INTP1/SI11/SDA11
P30/INTP3/RTC1HZ/SCK11/SCL11
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0
P63
P62
P61/SDAA0
P60/SCLA0
P41/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1
P00/TI00/TxD1
P120/ANI19
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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1.3.9 48-pin products
P140/PCLBUZ0/INTP6
P00/TI00/TxD1
P01/TO00/RxD1
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
• 48-pin plastic LQFP (fine pitch) (7 × 7)
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P147/ANI18
P146
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RXD0)
P17/TI02/TO02/(TXD0)
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
P60/SCLA0
P61/SDAA0
P62
P63
P31/TI03/TO03/INTP4/(PCLBUZ0)
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P30/INTP3/RTC1HZ/SCK11/SCL11
P120/ANI19
P41/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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CHAPTER 1 OUTLINE
P140/PCLBUZ0/INTP6
P00/TI00/TxD1
P01/TO00/RxD1
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
• 48-pin plastic WQFN (7 × 7)
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
exposed die pad
39
22
40
21
20
41
42
19
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
P147/ANI18
P146
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RXD0)
P17/TI02/TO02/(TXD0)
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
P60/SCLA0
P61/SDAA0
P62
P63
P31/TI03/TO03/INTP4/(PCLBUZ0)
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P30/INTP3/RTC1HZ/SCK11/SCL11
P120/ANI19
P41/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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1.3.10 52-pin products
P30/INTP3/RTC1HZ/SCK11/SCL11
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P17/TI02/TO02/(TXD0)
P16/TI01/TO01/INTP5/(RXD0)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P10/SCK00/SCL00/(TI07)/(TO07)
P146
P147/ANI18
• 52-pin plastic LQFP (10 × 10)
39 38 37 36 35 34 33 32 31 30 29 28 27
P25/ANI5
24
P72/KR2/SO21
P24/ANI4
43
23
P73/KR3/SO01
P23/ANI3
44
22
P74/KR4/INTP8/SI01/SDA01
P22/ANI2
45
21
P75/KR5/INTP9/SCK01/SCL01
P21/ANI1/AVREFM
46
20
P76/KR6/INTP10/(RXD2)
P20/ANI0/AVREFP
47
19
P77/KR7/INTP11/(TXD2)
P130
48
18
P31/TI03/TO03/INTP4/(PCLBUZ0)
P03/ANI16/RxD1
49
17
P63
P02/ANI17/TxD1
50
16
P62
P01/TO00
51
15
P61/SDAA0
P00/TI00
52
14
P60/SCLA0
VDD
VSS
8 9 10 11 12 13
REGC
6 7
P121/X1
5
P122/X2/EXCLK
3 4
P123/XT1
2
P40/TOOL0
1
P137/INTP0
P71/KR1/SI21/SDA21
42
RESET
P26/ANI6
P124/XT2/EXCLKS
P70/KR0/SCK21/SCL21
25
P41/TI07/TO07
26
41
P120/ANI19
40
P140/PCLBUZ0/INTP6
P27/ANI7
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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1.3.11 64-pin products
• 64-pin plastic LQFP (12 × 12)
P147/ANI18
P146
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(SI00)/(RXD0)
P17/TI02/TO02/(SO00)/(TXD0)
P55/(PCLBUZ1)/(SCK00)
P54
P53/(INTP11)
P52/(INTP10)
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
• 64-pin plastic LQFP (fine pitch) (10 × 10)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6 7 8 9 10 11 12 13 14 15 16
P120/ANI19
P43
P42/TI04/TO04
P41/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
1 2 3 4 5
P30/INTP3/RTC1HZ/SCK11/SCL11
P05/TI05/TO05
P06/TI06/TO06
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3/SO01
P74/KR4/INTP8/SI01/SDA01
P75/KR5/INTP9/SCK01/SCL01
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63
P62
P61/SDAA0
P60/SCLA0
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0 pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 19 of 124
RL78/G13
CHAPTER 1 OUTLINE
• 64-pin plastic FBGA (4 × 4)
Top View
Bottom View
8
7
6
5
4
3
2
1
A
B
C D E
F
G H
H
G
F
E D
C
B A
Index mark
Pin No.
Name
Pin No.
Name
Pin No.
Name
Pin No.
Name
A1
P05/TI05/TO05
C1
P51/INTP2/SO11
E1
P13/TxD2/SO20/
G1
(SDAA0)/(TI04)/(TO04)
P146
A2
P30/INTP3/RTC1HZ
/SCK11/SCL11
C2
P71/KR1/SI21/SDA21
E2
P14/RxD2/SI20/SDA20 G2
/(SCLA0)/(TI03)/(TO03)
P25/ANI5
A3
P70/KR0/SCK21
/SCL21
C3
P74/KR4/INTP8/SI01
/SDA01
E3
P15/SCK20/SCL20/
(TI02)/(TO02)
G3
P24/ANI4
A4
P75/KR5/INTP9
/SCK01/SCL01
C4
P52/(INTP10)
E4
P16/TI01/TO01/INTP5 G4
/(SI00)/(RxD0)
P22/ANI2
A5
P77/KR7/INTP11/
(TxD2)
C5
P53/(INTP11)
E5
P03/ANI16/SI10/RxD1 G5
/SDA10
P130
A6
P61/SDAA0
C6
P63
E6
P41/TI07/TO07
G6
P02/ANI17/SO10/TxD1
A7
P60/SCLA0
C7
VSS
E7
RESET
G7
P00/TI00
A8
EVDD0
C8
P121/X1
E8
P137/INTP0
G8
P124/XT2/EXCLKS
B1
P50/INTP1/SI11
/SDA11
D1
P55/(PCLBUZ1)/
(SCK00)
F1
P10/SCK00/SCL00/
(TI07)/(TO07)
H1
P147/ANI18
B2
P72/KR2/SO21
D2
P06/TI06/TO06
F2
P11/SI00/RxD0
/TOOLRxD/SDA00/
(TI06)/(TO06)
H2
P27/ANI7
B3
P73/KR3/SO01
D3
P17/TI02/TO02/
(SO00)/(TxD0)
F3
P12/SO00/TxD0
/TOOLTxD/(INTP5)/
H3
P26/ANI6
(TI05)/(TO05)
B4
P76/KR6/INTP10/
(RxD2)
D4
P54
F4
P21/ANI1/AVREFM
H4
P23/ANI3
B5
P31/TI03/TO03
/INTP4/(PCLBUZ0)
D5
P42/TI04/TO04
F5
P04/SCK10/SCL10
H5
P20/ANI0/AVREFP
B6
P62
D6
P40/TOOL0
F6
P43
H6
P141/PCLBUZ1/INTP7
B7
VDD
D7
REGC
F7
P01/TO00
H7
P140/PCLBUZ0/INTP6
B8
EVSS0
D8
P122/X2/EXCLK
F8
P123/XT1
H8
P120/ANI19
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0 pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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Oct 12, 2012
Page 20 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.3.12 80-pin products
• 80-pin plastic LQFP (14 × 14)
P153/ANI11
P100/ANI20
P147/ANI18
P146
P111/(INTP11)
P110/(INTP10)
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(SI00)/(RXD0)
P17/TI02/TO02/(SO00)/(TXD0)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
• 80-pin plastic LQFP (fine pitch) (12 × 12)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
P142/SCK30/SCL30
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P30/INTP3/RTC1HZ/SCK11/SCL11
P05/TI05/TO05
P06/TI06/TO06
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63/SDAA1
P62/SCLA1
P61/SDAA0
P60/SCLA0
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42/TI04/TO04
P41/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0 pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 21 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.3.13 100-pin products
P100/ANI20
P147/ANI18
P146/(INTP4)
P111/(INTP11)
P110/(INTP10)
P101
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(SI00)/(RXD0)
P17/TI02/TO02/(SO00)/(TXD0)
P57/(INTP3)
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
P51/SO11
P50/SI11/SDA11
EVDD1
P30/INTP3/RTC1HZ/SCK11/SCL11
P87/(INTP9)
• 100-pin plastic LQFP (fine pitch) (14 × 14)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
48
78
47
79
46
80
45
81
44
82
43
83
42
84
41
85
40
86
39
87
38
88
37
89
36
90
35
91
34
92
33
93
32
94
31
95
30
96
29
97
28
98
27
99
26
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P86/(INTP8)
P85/(INTP7)
P84/(INTP6)
P83
P82/(SO10)/(TXD1)
P81/(SI10)/(RXD1)/(SDA10)
P80/(SCK10)/(SCL10)
EVSS1
P05
P06
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63/SDAA1
P62/SCLA1
P142/SCK30/SCL30
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19
P47/INTP2
P46/INTP1/TI05/TO05
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42/TI04/TO04
P41
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
P60/SCLA0
P61/SDAA0
P156/ANI14
P155/ANI13
P154/ANI12
P153/ANI11
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P102/TI06/TO06
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P145/TI07/TO07
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1).
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0
and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 22 of 124
RL78/G13
CHAPTER 1 OUTLINE
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
P142/SCK30/SCL30
P143/SI30/RxD3/SDA30
P144/SO30/TxD3
P145/TI07/TO07
P00/TI00
P01/TO00
P02/ANI17/SO10/TxD1
P03/ANI16/SI10/RxD1/SDA10
P04/SCK10/SCL10
P102/TI06/TO06
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
P154/ANI12
P155/ANI13
P156/ANI14
P100/ANI20
P147/ANI18
• 100-pin plastic LQFP (14 × 20)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P146/(INTP4)
P111/(INTP11)
P110/(INTP10)
P101
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(SI00)/(RXD0)
P17/TI02/TO02/(SO00)/(TXD0)
P57/(INTP3)
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
P51/SO11
P50/SI11/SDA11
P60/SCLA0
P61/SDAA0
P62/SCLA1
P63/SDAA1
P31/TI03/TO03/INTP4/(PCLBUZ0)
P64/TI10/TO10
P65/TI11/TO11
P66/TI12/TO12
P67/TI13/TO13
P77/KR7/INTP11/(TXD2)
P76/KR6/INTP10/(RXD2)
P75/KR5/INTP9
P74/KR4/INTP8
P73/KR3
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P06
P05
EVSS1
P80/(SCK10)/(SCL10)
P81/(SI10)/(RXD1)/(SDA10)
P82/(SO10)/(TXD1)
P83
P84/(INTP6)
P85/(INTP7)
P86/(INTP8)
P87/(INTP9)
P30/INTP3/RTC1HZ/SCK11/SCL11
EVDD1
P120/ANI19
P47/INTP2
P46/INTP1/TI05/TO05
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42/TI04/TO04
P41
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1).
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0
and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 23 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.3.14 128-pin products
P100/ANI20
P147/ANI18
P146/(INTP4)
P111/(INTP11)
P110/(INTP10)
P101
P117/ANI24
P116/ANI25
P115/ANI26
P114
P113
P112
P97/SO11
P96/SI11/SDA11
P95/SCK11/SCL11
P94
P93
P92
P91
P90
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(SI00)/(RXD0)
P17/TI02/TO02/(SO00)/(TXD0)
P57/(INTP3)
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
P51
P50
P30/INTP3/RTC1HZ
P87/(INTP9)
• 128-pin plastic LQFP (fine pitch) (14 × 20)
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
103
64
104
63
105
62
106
61
107
60
108
59
109
58
110
57
111
56
112
55
113
54
114
53
115
52
51
116
50
117
49
118
48
119
47
120
46
121
45
122
44
123
43
124
42
125
41
126
40
127
39
128
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
P86/(INTP8)
P85/(INTP7)
P84/(INTP6)
P83
P82/(SO10)/(TXD1)
P81/(SI10)/(RXD1)/(SDA10)
P80/(SCK10)/(SCL10)
EVDD1
EVSS1
P05
P06
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63/SDAA1
P62/SCLA1
P142/SCK30/SCL30
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19
P37/ANI21
P36/ANI22
P35/ANI23
P34
P33
P32
P106/TI17/TO17
P105/TI16/TO16
P104/TI15/TO15
P103/TI14/TO14
P47/INTP2
P46/INTP1/TI05/TO05
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42/TI04/TO04
P41
P40/TOOL0
P127
P126
P125
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
P60/SCLA0
P61/SDAA0
P156/ANI14
P155/ANI13
P154/ANI12
P153/ANI11
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P102/TI06/TO06
P07
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P145/TI07/TO07
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1).
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0
and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 24 of 124
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CHAPTER 1 OUTLINE
1.4 Pin Identification
ANI0 to ANI14,
REGC:
Regulator capacitance
ANI16 to ANI26:
Analog input
RESET:
Reset
AVREFM:
A/D converter reference
RTC1HZ:
Real-time clock correction clock
potential (− side) input
AVREFP:
A/D converter reference
RxD0 to RxD3:
potential (+ side) input
SCK00, SCK01, SCK10,
EVDD0, EVDD1:
Power supply for port
SCK11, SCK20, SCK21,
EVSS0, EVSS1:
Ground for port
SCK30, SCK31:
EXCLK:
External clock input (Main SCLA0, SCLA1, SCL00,
Receive data
Serial clock input/output
system clock)
SCL01, SCL10, SCL11,
External clock input
SCL20,SCL21, SCL30,
(Subsystem clock)
SCL31:
Interrupt request from
SDAA0, SDAA1, SDA00,
peripheral
SDA01,SDA10, SDA11,
KR0 to KR7:
Key return
SDA20,SDA21, SDA30,
P00 to P07:
Port 0
SDA31:
P10 to P17:
Port 1
SI00, SI01, SI10, SI11,
P20 to P27:
Port 2
SI20, SI21, SI30, SI31:
P30 to P37:
Port 3
SO00, SO01, SO10,
P40 to P47:
Port 4
SO11, SO20, SO21,
P50 to P57:
Port 5
SO30, SO31:
P60 to P67:
Port 6
TI00 to TI07,
P70 to P77:
Port 7
TI10 to TI17:
P80 to P87:
Port 8
TO00 to TO07,
P90 to P97:
Port 9
TO10 to TO17:
Timer output
P100 to P106:
Port 10
TOOL0:
Data input/output for tool
P110 to P117:
Port 11
TOOLRxD, TOOLTxD:
Data input/output for external device
P120 to P127:
Port 12
TxD0 to TxD3:
Transmit data
P130, P137:
Port 13
VDD:
Power supply
P140 to P147:
Port 14
VSS:
Ground
P150 to P156:
Port 15
X1, X2:
Crystal oscillator (main system clock)
XT1, XT2:
Crystal oscillator (subsystem clock)
EXCLKS:
<R>
(1 Hz) output
INTP0 to INTP11:
PCLBUZ0, PCLBUZ1: Programmable clock
Serial clock output
Serial data input/output
Serial data input
Serial data output
Timer input
output/buzzer output
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 25 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5 Block Diagram
1.5.1 20-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
5
P10 to P12, P16, P17
TI01/TO01/P16
ch1
PORT 2
3
P20 to P22
TI02/TO02/P17
ch2
PORT 3
P30
PORT 4
P40
ch3
ch4
PORT 12
ch5
P121, P122
ch6
PORT 13
P137
ch7
PORT 14
P147
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
2
RL78
CPU
CORE
CODE FLASH MEMORY
DATA FLASH MEMORY
A/D CONVERTER
3
ANI0/P20 to
ANI2/P22
3
ANI16/P01, ANI17/P00,
ANI18/P147
AVREFP/P20
AVREFM/P21
12-BIT INTERVAL
TIMER
POWER ON RESET/
VOLTAGE
DETECTOR
REAL-TIME
CLOCK
POR/LVD
CONTROL
RAM
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11
TxD0/P12
UART0
RxD1/P01
TxD1/P00
UART1
RESET CONTROL
ON-CHIP DEBUG
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK11/P30
SI11/P17
SO11/P16
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL11/P30
SDA11/P17
IIC11
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
CRC
OSCILLATOR
VOLTAGE
REGULATOR
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
TOOL0/P40
RESET
X1/P121
X2/EXCLK/P122
REGC
INTP0/P137
INTERRUPT
CONTROL
INTP3/P30
INTP5/P16
Page 26 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.2 24-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
5
P10 to P12, P16, P17
TI01/TO01/P16
ch1
PORT 2
3
P20 to P22
TI02/TO02/P17
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
ch3
PORT 4
P40
PORT 5
P50
ch4
ch5
ch6
ch7
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
RL78
CPU
CORE
PORT 6
2
P60, P61
PORT 12
2
P121, P122
PORT 13
P137
PORT 14
P147
CODE FLASH MEMORY
3
ANI0/P20 to
ANI2/P22
3
ANI16/P01, ANI17/P00,
ANI18/P147
DATA FLASH MEMORY
A/D CONVERTER
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11
TxD0/P12
UART0
RxD1/P01
TxD1/P00
UART1
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK11/P30
SI11/P50
SO11/P17
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL11/P30
SDA11/P50
IIC11
AVREFP/P20
AVREFM/P21
POWER ON RESET/
VOLTAGE
DETECTOR
RAM
POR/LVD
CONTROL
RESET CONTROL
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
SERIAL
INTERFACE IICA0
SDAA0/P61
SCLA0/P60
RESET
X1/P121
HIGH-SPEED
ON-CHIP
X2/EXCLK/P122
OSCILLATOR
BUZZER OUTPUT
PCLBUZ0/P31
CLOCK OUTPUT
CONTROL
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
VOLTAGE
REGULATOR
REGC
INTP0/P137
CRC
INTP1/P50
INTERRUPT
CONTROL
2
INTP3/P30,
INTP4/P31
INTP5/P16
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 27 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.3 25-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
5
P10 to P12, P16, P17
TI01/TO01/P16
ch1
PORT 2
3
P20 to P22
TI02/TO02/P17
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
ch3
PORT 4
P40
PORT 5
P50
ch4
ch5
ch6
ch7
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
RL78
CPU
CORE
PORT 6
2
P60, P61
PORT 12
2
P121, P122
PORT 13
P130
P137
PORT 14
P147
CODE FLASH MEMORY
3
ANI0/P20 to
ANI2/P22
3
ANI16/P01, ANI17/P00,
ANI18/P147
DATA FLASH MEMORY
A/D CONVERTER
AVREFP/P20
AVREFM/P21
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11
TxD0/P12
UART0
RxD1/P01
TxD1/P00
UART1
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK11/P30
SI11/P50
SO11/P17
CSI11
SCL00/P10
SDA00/P11
POWER ON RESET/
VOLTAGE
DETECTOR
RAM
POR/LVD
CONTROL
RESET CONTROL
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
SERIAL
INTERFACE IICA0
SDAA0/P61
SCLA0/P60
RESET
X1/P121
HIGH-SPEED
ON-CHIP
X2/EXCLK/P122
OSCILLATOR
IIC00
BUZZER OUTPUT
SCL11/P30
SDA11/P50
IIC11
PCLBUZ0/P31
CLOCK OUTPUT
CONTROL
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
VOLTAGE
REGULATOR
REGC
INTP0/P137
CRC
INTP1/P50
INTERRUPT
CONTROL
2
INTP3/P30,
INTP4/P31
INTP5/P16
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 28 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.4 30-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
4
P20 to P23
TI02/TO02/P17
(TI02/TO02/P15)
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
(TI03/TO03/P14)
ch3
(TI04/TO04/P13)
ch4
(TI05/TO05/P12)
ch5
(TI06/TO06/P11)
ch6
(TI07/TO07/P10)
RxD2/P14
ch7
PORT 4
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 5
2
P50, P51
PORT 6
2
P60, P61
PORT 12
WINDOW
WATCHDOG
TIMER
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
RxD1/P01
TxD1/P00
UART1
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
P137
PORT 14
P147
4
ANI0/P20 to
ANI3/P23
4
ANI16/P01, ANI17/P00,
ANI18/P147, ANI19/P120
CODE FLASH MEMORY
RL78
CPU
CORE
A/D CONVERTER
AVREFP/P20
AVREFM/P21
DATA FLASH MEMORY
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RAM
RESET CONTROL
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
SDAA0/P61(SDAA0/P13)
SERIAL
INTERFACE IICA0
SCLA0/P60(SCLA0/P14)
IIC11
BUZZER OUTPUT
2
SERIAL ARRAY
UNIT1 (2ch)
UART2
LINSEL
SCK20/P15
SI20/P14
SO20/P13
CSI20
SCL20/P15
SDA20/P14
IIC20
Remark
P121, P122
12-BIT INTERVAL
TIMER
SERIAL ARRAY
UNIT0 (4ch)
RxD2/P14
TxD2/P13
P120
2
PORT 13
REAL-TIME
CLOCK
SCL11/P30
SDA11/P50
P40
CLOCK OUTPUT
CONTROL
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
PCLBUZ0/P31,
PCLBUZ1/P15
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
HIGH-SPEED
ON-CHIP
OSCILLATOR
X2/EXCLK/P122
VOLTAGE
REGULATOR
REGC
CRC
RxD2/P14
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 29 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.5 32-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
4
P20 to P23
TI02/TO02/P17
(TI02/TO02/P15)
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
(TI03/TO03/P14)
ch3
(TI04/TO04/P13)
ch4
(TI05/TO05/P12)
ch5
(TI06/TO06/P11)
(TI07/TO07/P10)
RxD2/P14
PORT 4
PORT 5
2
P50, P51
ch6
PORT 6
3
P60 to P62
ch7
PORT 7
PORT 12
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
REAL-TIME
CLOCK
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
RxD1/P01
TxD1/P00
UART1
SCK00/P10
SI00/P11
SO00/P12
CSI00
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL11/P30
SDA11/P50
IIC11
PORT 14
P147
DATA FLASH MEMORY
4
ANI0/P20 to
ANI3/P23
4
ANI16/P01, ANI17/P00,
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
POWER ON RESET/
VOLTAGE
DETECTOR
RAM
POR/LVD
CONTROL
VSS TOOLRxD/P11,
TOOLTxD/P12
TOOL0/P40
ON-CHIP DEBUG
SDAA0/P61(SDAA0/P13)
SERIAL
INTERFACE IICA0
SCLA0/P60(SCLA0/P14)
BUZZER OUTPUT
2
CLOCK OUTPUT
CONTROL
SERIAL ARRAY
UNIT1 (2ch)
Remark
P137
RESET CONTROL
SCK11/P30
SI11/P50
SO11/P51
SCL20/P15
SDA20/P14
P120
P121, P122
2
PORT 13
A/D CONVERTER
VDD
SCK20/P15
SI20/P14
SO20/P13
P70
CODE FLASH MEMORY
RL78
CPU
CORE
SERIAL ARRAY
UNIT0 (4ch)
RxD2/P14
TxD2/P13
P40
LINSEL
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
CSI20
DIRECT MEMORY
ACCESS CONTROL
IIC20
BCD
ADJUSTMENT
UART2
PCLBUZ0/P31,
PCLBUZ1/P15
CRC
SYSTEM
CONTROL
RESET
X1/P121
HIGH-SPEED
ON-CHIP
OSCILLATOR
X2/EXCLK/P122
VOLTAGE
REGULATOR
REGC
RxD2/P14
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 30 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.6 36-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
6
P20 to P25
TI02/TO02/P17
(TI02/TO02/P15)
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
(TI03/TO03/P14)
ch3
(TI04/TO04/P13)
ch4
(TI05/TO05/P12)
ch5
(TI06/TO06/P11)
(TI07/TO07/P10)
RxD2/P14
PORT 4
PORT 5
2
P50, P51
ch6
PORT 6
3
P60 to P62
ch7
PORT 7
3
P70 to P72
2
P121, P122
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 12
UART0
RxD1/P01
TxD1/P00
UART1
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL11/P30
SDA11/P50
IIC11
P137
PORT 14
P147
DATA FLASH MEMORY
A/D CONVERTER
POWER ON RESET/
VOLTAGE
DETECTOR
RAM
VSS TOOLRxD/P11,
TOOLTxD/P12
SDAA0/P61(SDAA0/P13)
CSI20
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
SCL21/P70
SDA21/P71
IIC21
SCLA0/P60(SCLA0/P14)
2
CLOCK OUTPUT
CONTROL
IIC20
ANI18/P147, ANI19/P120
POR/LVD
CONTROL
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
UART2
SCL20/P15
SDA20/P14
2
BUZZER OUTPUT
LINSEL
CSI21
ANI0/P20 to
ANI5/P25
RESET CONTROL
VDD
SERIAL ARRAY
UNIT1 (2ch)
6
AVREFP/P20
AVREFM/P21
SERIAL
INTERFACE IICA0
Remark
PORT 13
CODE FLASH MEMORY
RL78
CPU
CORE
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
P120
12-BIT INTERVAL
TIMER
REAL-TIME
CLOCK
RxD2/P14
TxD2/P13
P40
DIRECT MEMORY
ACCESS CONTROL
PCLBUZ0/P31,
PCLBUZ1/P15
VOLTAGE
REGULATOR
REGC
RxD2/P14
INTP0/P137
CRC
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
BCD
ADJUSTMENT
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 31 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.7 40-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
7
P20 to P26
TI02/TO02/P17
(TI02/TO02/P15)
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
(TI03/TO03/P14)
ch3
(TI04/TO04/P13)
ch4
(TI05/TO05/P12)
ch5
(TI06/TO06/P11)
(TI07/TO07/P10)
RxD2/P14
PORT 4
PORT 5
2
P50, P51
ch6
PORT 6
3
P60 to P62
ch7
PORT 7
4
P70 to P73
4
P121 to P124
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 12
REAL-TIME
CLOCK
UART0
RxD1/P01
TxD1/P00
UART1
P137
PORT 14
P147
DATA FLASH MEMORY
A/D CONVERTER
CSI00
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL11/P30
SDA11/P50
IIC11
POWER ON RESET/
VOLTAGE
DETECTOR
VSS TOOLRxD/P11,
TOOLTxD/P12
SDAA0/P61(SDAA0/P13)
SERIAL
INTERFACE IICA0
CSI20
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
SCL21/P70
SDA21/P71
IIC21
KR0/P70 to
KR3/P73
4
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
SCLA0/P60(SCLA0/P14)
2
CLOCK OUTPUT
CONTROL
IIC20
ANI18/P147, ANI19/P120
SYSTEM
CONTROL
UART2
SCL20/P15
SDA20/P14
2
RESET
X1/P121
X2/EXCLK/P122
BUZZER OUTPUT
LINSEL
CSI21
ANI0/P20 to
ANI6/P26
RAM
VDD
SERIAL ARRAY
UNIT1 (2ch)
7
AVREFP/P20
AVREFM/P21
KEY RETURN
SCK00/P10
SI00/P11
SO00/P12
Remark
PORT 13
CODE FLASH MEMORY
RL78
CPU
CORE
SERIAL ARRAY
UNIT0 (4ch)
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
P120
12-BIT INTERVAL
TIMER
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
RxD2/P14
TxD2/P13
P40
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
PCLBUZ0/P31,
PCLBUZ1/P15
CRC
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD2/P14
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 32 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.8 44-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
TI02/TO02/P17
(TI02/TO02/P15)
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
(TI03/TO03/P14)
ch3
PORT 4
2
P40, P41
(TI04/TO04/P13)
ch4
(TI05/TO05/P12)
ch5
PORT 5
2
P50, P51
(TI06/TO06/P11)
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
ch6
PORT 6
4
P60 to P63
ch7
PORT 7
4
P70 to P73
4
P121 to P124
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 12
PORT 13
TxD0/P12(TxD0/P17)
RxD1/P01
TxD1/P00
REAL-TIME
CLOCK
CODE FLASH MEMORY
RL78
CPU
CORE
DATA FLASH MEMORY
A/D CONVERTER
P146, P147
8
ANI0/P20 to
ANI7/P27
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
KEY RETURN
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL11/P30
SDA11/P50
IIC11
KR0/P70 to
KR3/P73
4
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
SERIAL ARRAY
UNIT1 (2ch)
POR/LVD
CONTROL
VSS TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
SDAA0/P61(SDAA0/P13)
SERIAL
INTERFACE IICA0
UART2
SYSTEM
CONTROL
2
CLOCK OUTPUT
CONTROL
CSI20
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
TOOL0/P40
ON-CHIP DEBUG
SCLA0/P60(SCLA0/P14)
BUZZER OUTPUT
LINSEL
PCLBUZ0/P31,
PCLBUZ1/P15
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
CRC
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD2/P14
INTP0/P137
CSI21
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
Remark
2
UART1
CSI00
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
PORT 14
UART0
SCK00/P10
SI00/P11
SO00/P12
RxD2/P14
TxD2/P13
P137
12-BIT INTERVAL
TIMER
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11(RxD0/P16)
P120
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 33 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.9 48-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
TI02/TO02/P17
(TI02/TO02/P15)
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
(TI03/TO03/P14)
ch3
PORT 4
2
P40, P41
(TI04/TO04/P13)
ch4
(TI05/TO05/P12)
ch5
PORT 5
2
P50, P51
(TI06/TO06/P11)
ch6
PORT 6
4
P60 to P63
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
ch7
PORT 7
6
P70 to P75
4
P121 to P124
PORT 12
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 14
REAL-TIME
CLOCK
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
RxD1/P01
TxD1/P00
UART1
DATA FLASH MEMORY
8
ANI0/P20 to
ANI7/P27
A/D CONVERTER
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
CSI01
SCL00/P10
SDA00/P11
IIC00
SCL01/P75
SDA01/P74
IIC01
SCL11/P30
SDA11/P50
IIC11
VDD
KR0/P70 to
KR5/P75
6
VSS TOOLRxD/P11,
TOOLTxD/P12
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
SERIAL ARRAY
UNIT1 (2ch)
SERIAL
INTERFACE IICA0
HIGH-SPEED
SCLA0/P60(SCLA0/P14)
BUZZER OUTPUT
CSI20
CLOCK OUTPUT
CONTROL
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
CSI21
DIRECT MEMORY
ACCESS CONTROL
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
RESET
X1/P121
X2/EXCLK/P122
SDAA0/P61(SDAA0/P13)
2
UART2
LINSEL
Remark
P140,
P146, P147
CSI00
CSI11
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
3
CODE FLASH MEMORY
RL78
CPU
CORE
KEY RETURN
SCK11/P30
SI11/P50
SO11/P51
RxD2/P14
TxD2/P13
P130
P137
PORT 13
12-BIT INTERVAL
TIMER
SERIAL ARRAY
UNIT0 (4ch)
SCK00/P10
SI00/P11
SO00/P12
SCK01/P75
SI01/P74
SO01/P73
P120
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P15
ON-CHIP
XT1/P123
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD2/P14
INTP0/P137
CRC
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
INTP6/P140
BCD
ADJUSTMENT
2
INTP8/P74,
INTP9/P75
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 34 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.10 52-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
4
P00 to P03
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
2
P40, P41
PORT 5
2
P50, P51
TI01/TO01/P16
ch1
TI02/TO02/P17
(TI02/TO02/P15)
ch2
TI03/TO03/P31
(TI03/TO03/P14)
ch3
(TI04/TO04/P13)
ch4
(TI05/TO05/P12)
ch5
(TI06/TO06/P11)
ch6
PORT 6
4
P60 to P63
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
(RxD2/P76)
ch7
PORT 7
8
P70 to P77
PORT 12
WINDOW
WATCHDOG
TIMER
P120
4
P121 to P124
P130
P137
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
12-BIT INTERVAL
TIMER
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
RxD1/P03
TxD1/P02
UART1
SCK00/P10
SI00/P11
SO00/P12
SCK01/P75
SI01/P74
SO01/P73
PORT 14
IIC00
SCL01/P75
SDA01/P74
IIC01
SCL11/P30
SDA11/P50
IIC11
A/D CONVERTER
4
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR7/P77
8
POR/LVD
CONTROL
RESET CONTROL
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
SDAA0/P61(SDAA0/P13)
SERIAL
INTERFACE IICA0
SERIAL ARRAY
UNIT1 (2ch)
CSI20
CSI21
OSCILLATOR
XT2/EXCLKS/P124
SCLA0/P60(SCLA0/P14)
VOLTAGE
REGULATOR
BUZZER OUTPUT
UART2
LINSEL
2
CLOCK OUTPUT
CONTROL
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
REGC
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P15
CRC
RxD2/P14 (RxD2/P76)
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
INTP6/P140
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
Remark
ANI0/P20 to
ANI7/P27
DATA FLASH MEMORY
CSI01
SCL00/P10
SDA00/P11
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
8
CODE FLASH MEMORY
RL78
CPU
CORE
RAM
CSI11
TxD2/P13(TxD2/P77)
P140,
P146, P147
CSI00
SCK11/P30
SI11/P50
SO11/P51
RxD2/P14(RxD2/P76)
3
DIRECT MEMORY
ACCESS CONTROL
4
INTP8/P74 to
INTP11/P77
BCD
ADJUSTMENT
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 35 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.11 64-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
7
P00 to P06
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
TI02/TO02/P17
(TI02/TO02/P15)
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
(TI03/TO03/P14)
ch3
TI04/TO04/P42
(TI04/TO04/P13)
PORT 4
4
P40 to P43
ch4
TI05/TO05/P05
(TI05/TO05/P12)
ch5
PORT 5
6
P50 to P55
ch6
PORT 6
4
P60 to P63
ch7
PORT 7
8
P70 to P77
4
P121 to P124
TI06/TO06/P06
(TI06/TO06/P11)
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
(RxD2/P76)
PORT 12
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 14
UART0
RxD1/P03
TxD1/P02
UART1
A/D CONVERTER
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL01/P75
SDA01/P74
IIC01
ANI0/P20 to
ANI7/P27
4
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
DATA FLASH MEMORY
KEY RETURN
KR0/P70 to
KR7/P77
8
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD, VSS, TOOLRxD/P11,
EVDD0 EVSS0 TOOLTxD/P12
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
SCL10/P04
SDA10/P03
IIC10
SCL11/P30
SDA11/P50
SDAA0/P61(SDAA0/P13)
SERIAL
INTERFACE IICA0
2
LINSEL
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
BUZZER OUTPUT
UART2
OSCILLATOR
SCLA0/P60(SCLA0/P14)
IIC11
SERIAL ARRAY
UNIT1 (2ch)
CLOCK OUTPUT
CONTROL
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
CSI20
DIRECT MEMORY
ACCESS CONTROL
REGC
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P141
(PCLBUZ1/P55)
RxD2/P14 (RxD2/P76)
INTP0/P137
CRC
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
2
INTP6/P140,
INTP7/P141
2
INTP8/P74,
INTP9/P75
2
INTP10/P76(INTP10/P52),
INTP11/P77(INTP11/P53)
INTERRUPT
CONTROL
INTP5/P16(INTP5/P12)
CSI21
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
Remark
8
CODE FLASH MEMORY
RL78
CPU
CORE
CSI01
CSI10
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
P140, P141,
P146, P147
CSI00
SCK10/P04
SI10/P03
SO10/P02
TxD2/P13(TxD2/P77)
4
REAL-TIME
CLOCK
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
RxD2/P14(RxD2/P76)
P130
P137
PORT 13
12-BIT INTERVAL
TIMER
SERIAL ARRAY
UNIT0 (4ch)
SCK00/P10(SCK00/P55)
SI00/P11(SI00/P16)
SO00/P12(SO00/P17)
SCK01/P75
SI01/P74
SO01/P73
P120
BCD
ADJUSTMENT
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 36 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.12 80-pin products
TIMER ARRAY
UNIT0 (8ch)
TIMER ARRAY
UNIT1 (4ch)
TI00/P00
TO00/P01
ch0
ch0
TI10/TO10/P64
PORT 0
7
P00 to P06
TI01/TO01/P16
ch1
ch1
TI11/TO11/P65
PORT 1
8
P10 to P17
TI02/TO02/P17
(TI02/TO02/P15)
ch2
ch2
TI12/TO12/P66
PORT 2
8
P20 to P27
TI03/TO03/P31
(TI03/TO03/P14)
ch3
ch3
TI13/TO13/P67
PORT 3
2
P30, P31
TI04/TO04/P42
(TI04/TO04/P13)
ch4
PORT 4
6
P40 to P45
TI05/TO05/P05
(TI05/TO05/P12)
ch5
PORT 5
6
P50 to P55
PORT 6
8
P60 to P67
PORT 7
8
P70 to P77
TI06/TO06/P06
(TI06/TO06/P11)
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
(RxD2/P76)
ch6
ch7
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
RxD1/P03
TxD1/P02
UART1
SCK00/P10(SCK00/P55)
SI00/P11(SI00/P16)
SO00/P12(SO00/P17)
SCK01/P43
SI01/P44
SO01/P45
PORT 11
PORT 12
SCL00/P10
SDA00/P11
IIC00
SCL01/P43
SDA01/P44
IIC01
SCL10/P04
SDA10/P03
IIC10
SCL11/P30
SDA11/P50
IIC11
CODE FLASH MEMORY
RL78
CPU
CORE
SERIAL ARRAY
UNIT1 (4ch)
P110, P111
2
BUZZER OUTPUT
CSI21
CLOCK OUTPUT
CONTROL
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P141
(PCLBUZ1/P55)
2
IIC20
P140 to P144,
P146, P147
PORT 15
4
P150 to P153
KEY RETURN
8
KR0/P70 to
KR7/P77
POR/LVD
CONTROL
RESET CONTROL
CSI20
SCL20/P15
SDA20/P14
7
SDAA0/P61(SDAA0/P13)
SDAA1/P63
SCLA1/P62
CSI31
PORT 14
VDD, VSS, TOOLRxD/P11,
EVDD0 EVSS0 TOOLTxD/P12
UART3
SCK31/P54
SI31/P53
SO31/P52
PORT 13
POWER ON RESET/
VOLTAGE
DETECTOR
SCLA0/P60(SCLA0/P14)
CSI30
P121 to P124
P130
P137
RAM
SERIAL
INTERFACE IICA1
LINSEL
P120
4
DATA FLASH MEMORY
SERIAL
INTERFACE IICA0
UART2
SCK30/P142
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
CRC
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD2/P14 (RxD2/P76)
INTP0/P137
DIRECT MEMORY
ACCESS CONTROL
2
SCL21/P70
SDA21/P71
IIC21
SCL30/P142
SDA30/P143
IIC30
SCL31/P54
SDA31/P53
IIC31
BCD
ADJUSTMENT
2
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
Remark
P100
PORT 10
CSI01
CSI11
SI30/P143
SO30/P144
A/D CONVERTER
AVREFP/P20
AVREFM/P21
SCK11/P30
SI11/P50
SO11/P51
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
ANI8/P150 to ANI11/P153
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
CSI00
CSI10
RxD3/P143
TxD3/P144
ANI0/P20 to ANI7/P27
4
5
SCK10/P04
SI10/P03
SO10/P02
RxD2/P14(RxD2/P76)
TxD2/P13(TxD2/P77)
8
12-BIT INTERVAL
TIMER
REAL-TIME
CLOCK
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
INTP5/P16(INTP5/P12)
INTERRUPT
CONTROL
2
INTP6/P140,
INTP7/P141
2
INTP8/P74,
INTP9/P75
2
INTP10/P76(INTP10/P110),
INTP11/P77(INTP11/P111)
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 37 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.13 100-pin products
TIMER ARRAY
UNIT0 (8ch)
TIMER ARRAY
UNIT1 (4ch)
TI00/P00
TO00/P01
ch0
ch0
TI10/TO10/P64
PORT 0
7
P00 to P06
TI01/TO01/P16
ch1
ch1
TI11/TO11/P65
PORT 1
8
P10 to P17
TI02/TO02/P17
(TI02/TO02/P15)
ch2
ch2
TI12/TO12/P66
PORT 2
8
P20 to P27
TI03/TO03/P31
(TI03/TO03/P14)
ch3
ch3
TI13/TO13/P67
PORT 3
2
P30, P31
TI04/TO04/P42
(TI04/TO04/P13)
ch4
PORT 4
8
TI05/TO05/P46
(TI05/TO05/P12)
P40 to P47
ch5
PORT 5
8
P50 to P57
PORT 6
8
P60 to P67
PORT 7
8
P70 to P77
PORT 8
8
P80 to P87
PORT 10
3
P100 to P102
PORT 11
2
P110, P111
4
P121 to P124
TI06/TO06/P102
(TI06/TO06/P11)
TI07/TO07/P145
(TI07/TO07/P10)
RxD2/P14
(RxD2/P76)
ch6
ch7
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
RxD1/P03(RxD1/P81)
TxD1/P02(TxD1/P82)
UART1
SCK00/P10(SCK00/P55)
SI00/P11(SI00/P16)
SO00/P12(SO00/P17)
SCK01/P43
SI01/P44
SO01/P45
A/D CONVERTER
AVREFP/P20
AVREFM/P21
CSI01
PORT 12
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL01/P43
SDA01/P44
IIC01
SCL10/P04(SCL10/P80)
SDA10/P03(SDA10/P81)
IIC10
SCL11/P30
SDA11/P50
IIC11
CODE FLASH MEMORY
RL78
CPU
CORE
SERIAL ARRAY
UNIT1 (4ch)
LINSEL
RxD3/P143
TxD3/P144
UART3
CSI20
VDD, VSS, TOOLRxD/P11,
EVDD0, EVSS0, TOOLTxD/P12
EVDD1 EVSS1
SERIAL
INTERFACE IICA0
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
SERIAL
INTERFACE IICA1
SDAA1/P63
SCLA1/P62
BUZZER OUTPUT
CSI21
CSI30
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
SCK31/P54
SI31/P53
SO31/P52
CSI31
DIRECT MEMORY
ACCESS CONTROL
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
IIC30
IIC31
PORT 14
8
P140 to P147
PORT 15
7
P150 to P156
KEY RETURN
8
POWER ON RESET/
VOLTAGE
DETECTOR
CLOCK OUTPUT
CONTROL
SCL31/P54
SDA31/P53
P130
P137
KR0/P70 to
KR7/P77
RAM
2
SCL30/P142
SDA30/P143
P120
PORT 13
DATA FLASH MEMORY
UART2
RxD2/P14(RxD2/P76)
TxD2/P13(TxD2/P77)
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P141
(PCLBUZ1/P55)
CRC
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
2
2
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
POR/LVD
CONTROL
RxD2/P14 (RxD2/P76)
INTP0/P137
BCD
ADJUSTMENT
RTC1HZ/P30
Remark
ANI8/P150 to ANI14/P156
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
CSI00
CSI10
SCK30/P142
SI30/P143
SO30/P144
ANI0/P20 to ANI7/P27
7
5
SCK10/P04(SCK10/P80)
SI10/P03(SI10/P81)
SO10/P02(SO10/P82)
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
8
12-BIT INTERVAL
TIMER
INTERRUPT
CONTROL
INTP1/P46(INTP1/P56),
INTP2/P47
INTP3/P30(INTP3/P57),
INTP4/P31(INTP4/P146)
INTP5/P16(INTP5/P12)
2
INTP6/P140(INTP6/P84),
INTP7/P141(INTP7/P85)
2
INTP8/P74(INTP8/P86),
INTP9/P75(INTP9/P87)
2
INTP10/P76(INTP10/P110),
INTP11/P77(INTP11/P111)
REAL-TIME
CLOCK
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 38 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.5.14 128-pin products
TIMER ARRAY
UNIT0 (8ch)
TIMER ARRAY
UNIT1 (8ch)
TI00/P00
TO00/P01
ch0
ch0
TI10/TO10/P64
PORT 0
8
P00 to P07
TI01/TO01/P16
ch1
ch1
TI11/TO11/P65
PORT 1
8
P10 to P17
TI02/TO02/P17
(TI02/TO02/P15)
ch2
ch2
TI12/TO12/P66
PORT 2
8
P20 to P27
TI03/TO03/P31
(TI03/TO03/P14)
ch3
ch3
TI13/TO13/P67
PORT 3
8
P30 to P37
TI04/TO04/P42
(TI04/TO04/P13)
ch4
ch4
TI14/TO14/P103
PORT 4
8
TI05/TO05/P46
(TI05/TO05/P12)
P40 to P47
ch5
ch5
TI15/TO15/P104
PORT 5
8
P50 to P57
ch6
ch6
TI16/TO16/P105
ch7
ch7
TI17/TO17/P106
PORT 6
8
P60 to P67
PORT 7
8
P70 to P77
PORT 8
8
P80 to P87
PORT 9
8
P90 to P97
PORT 10
7
P100 to P106
PORT 11
8
P110 to P117
TI06/TO06/P102
(TI06/TO06/P11)
TI07/TO07/P145
(TI07/TO07/P10)
RxD2/P14
(RxD2/P76)
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
RxD1/P03(RxD1/P81)
TxD1/P02(TxD1/P82)
UART1
SCK00/P10(SCK00/P55)
SI00/P11(SI00/P16)
SO00/P12(SO00/P17)
SCK01/P43
SI01/P44
SO01/P45
CSI00
8
ANI0/P20 to ANI7/P27
7
ANI8/P150 to ANI14/P156
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100, ANI21/37,
ANI22/P36, ANI23/P35,
ANI24/P117, ANI25/P116,
ANI26/P115
11
A/D CONVERTER
CSI01
SCK10/P04(SCK10/P80)
SI10/P03(SI10/P81)
SO10/P02(SO10/P82)
CSI10
SCK11/P95
SI11/P96
SO11/P97
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL01/P43
SDA01/P44
IIC01
SCL10/P04(SCL10/P80)
SDA10/P03(SDA10/P81)
IIC10
SCL11/P95
SDA11/P96
IIC11
AVREFP/P20
AVREFM/P21
UART2
DATA FLASH MEMORY
P130
P137
PORT 14
8
P140 to P147
PORT 15
7
P150 to P156
KEY RETURN
8
POWER ON RESET/
VOLTAGE
DETECTOR
VDD, VSS, TOOLRxD/P11,
EVDD0, EVSS0, TOOLTxD/P12
EVDD1 EVSS1
SERIAL
INTERFACE IICA0
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
LINSEL
UART3
SERIAL
INTERFACE IICA1
SDAA1/P63
SCLA1/P62
CSI20
BUZZER OUTPUT
CSI21
CLOCK OUTPUT
CONTROL
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P141
(PCLBUZ1/P55)
2
SCK30/P142
SI30/P143
SO30/P144
CSI30
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
SCK31/P54
SI31/P53
SO31/P52
CSI31
DIRECT MEMORY
ACCESS CONTROL
SCL20/P15
SDA20/P14
IIC20
KR0/P70 to
KR7/P77
CRC
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD2/P14 (RxD2/P76)
INTP0/P137
2
SCL21/P70
SDA21/P71
IIC21
SCL30/P142
SDA30/P143
IIC30
BCD
ADJUSTMENT
2
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
IIC31
RTC1HZ/P30
Remark
P121 to P124
RAM
RxD3/P143
TxD3/P144
SCL31/P54
SDA31/P53
P120, P125 to P127
4
PORT 13
RxD2/P14(RxD2/P76)
TxD2/P13(TxD2/P77)
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
4
CODE FLASH MEMORY
RL78
CPU
CORE
SERIAL ARRAY
UNIT1 (4ch)
PORT 12
REAL-TIME
CLOCK
INTERRUPT
CONTROL
INTP1/P46 (INTP1/P56),
INTP2/P47
INTP3/P30 (INTP3/P57),
INTP4/P31 (INTP4/P146)
INTP5/P16 (INTP5/P12)
2
INTP6/P140 (INTP6/P84),
INTP7/P141 (INTP7/P85)
2
INTP8/P74 (INTP8/P86),
INTP9/P75 (INTP9/P87)
2
INTP10/P76 (INTP10/P110),
INTP11/P77 (INTP11/P111)
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 39 of 124
RL78/G13
CHAPTER 1 OUTLINE
1.6 Outline of Functions
[20-pin, 24-pin, 25-pin, 30-pin, 32-pin, 36-pin products]
Caution
This outline describes the functions at the time when Peripheral I/O redirection register (PIOR)
is set to 00H other than timer output.
(1/2)
Item
20-pin
24-pin
Note1
16 to 128
−
4 to 8
2 to 12
R5F101Cx
2 to 12
R5F100Cx
Note1
16 to 128
−
4 to 8
36-pin
R5F101Bx
16 to 128
−
2 to 4
R5F100Bx
2 to 4
Note1
16 to 64
4
32-pin
R5F101Ax
−
R5F100Ax
2 to 4
Note1
16 to 64
4
30-pin
R5F1018x
RAM (KB)
−
R5F1008x
4
R5F1017x
16 to 64
Data flash memory (KB)
R5F1007x
R5F1016x
R5F1006x
Code flash memory (KB)
25-pin
−
4 to 8
Note1
2 to 12
Note1
Memory space
1 MB
Main system High-speed system
clock
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8
V
High-speed on-chip
oscillator
HS (High-speed main) mode:
HS (High-speed main) mode:
LS (Low-speed main) mode:
LV (Low-voltage main) mode:
1 to 32 MHz (VDD = 2.7 to 5.5 V),
1 to 16 MHz (VDD = 2.4 to 5.5 V),
1 to 8 MHz (VDD = 1.8 to 5.5 V),
1 to 4 MHz (VDD = 1.6 to 5.5 V)
−
Subsystem clock
<R>
Low-speed on-chip oscillator
15 kHz (TYP.)
<R>
General-purpose register
(8-bit register × 8) × 4 banks
Minimum instruction execution
time
0.03125 μs (High-speed on-chip oscillator: fIH = 32 MHz operation)
Instruction set
•
•
•
•
I/O port
Timer
16
20
21
26
28
32
CMOS I/O
13
15
15
21
22
26
CMOS input
3
3
3
3
3
3
CMOS output
−
−
1
−
−
−
N-ch O.D I/O (6 V
tolerance)
−
2
2
2
3
3
16-bit timer
8 channels
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer
(IT)
1 channel
RTC output
2.
3.
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
Timer output
Notes 1.
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
4 channels
3 channels
Note 2
)
(PWM outputs: (PWM outputs: 3
Note 2
)
2
4 channels (PWM outputs: 3
8 channels
Note 3
Note 2
),
(PWM outputs: 7
Note 2
)
−
In the case of the 4 KB, this is about 3 KB when the self-programming function and data flash
function are used.
The number of outputs varies, depending on the setting of channels in use and the number of the
master.
When setting to PIOR = 1
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 40 of 124
RL78/G13
CHAPTER 1 OUTLINE
(2/2)
Item
20-pin
2
R5F101Cx
2
36-pin
R5F100Cx
R5F101Bx
1
32-pin
R5F100Bx
R5F101Ax
R5F100Ax
1
30-pin
R5F1018x
R5F1008x
−
25-pin
R5F1017x
R5F1007x
R5F1016x
R5F1006x
Clock output/buzzer output
24-pin
2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
<R>
8/10-bit resolution A/D converter
6 channels
6 channels
6 channels
Serial interface
[20-pin, 24-pin, 25-pin products]
8 channels
8 channels
8 channels
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
[30-pin, 32-pin products]
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 1 channel/simplified I C: 1 channel/UART (UART supporting LIN-bus): 1 channel
2
[36-pin products]
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 2 channel/simplified I C: 2 channel/UART (UART supporting LIN-bus): 1 channel
2
2
I C bus
−
1 channel
1 channel
1 channel
Multiplier and divider/multiply-
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
accumulator
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
1 channel
1 channel
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
2 channels
Vectored interrupt Internal
23
24
24
27
27
27
sources
3
5
5
6
6
6
External
−
Key interrupt
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
• Rising edge :
1.67 V to 4.06 V (14 stages)
• Falling edge :
1.63 V to 3.98 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 41 of 124
RL78/G13
CHAPTER 1 OUTLINE
[40-pin, 44-pin, 48-pin, 52-pin, 64-pin products]
Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR)
is set to 00H other than timer output.
(1/2)
Item
40-pin
−
4 to 8
2 to 32
Note1
−
4 to 8
2 to 32
Note1
R5F101Lx
Note1
32 to 512
R5F100Lx
Main system
clock
2 to 32
16 to 512
64-pin
R5F101Jx
Memory space
−
4 to 8
R5F100Jx
Note1
2 to 16
52-pin
R5F101Gx
−
4 to 8
RAM (KB)
16 to 512
R5F100Gx
Data flash memory (KB)
48-pin
R5F101Fx
16 to 192
R5F100Fx
R5F101Ex
R5F100Ex
Code flash memory (KB)
44-pin
32 to 512
−
4 to 8
2 to 32
Note1
1 MB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to
1.8 V
High-speed on-chip
oscillator
HS (High-speed main) mode:
HS (High-speed main) mode:
LS (Low-speed main) mode:
LV (Low-voltage main) mode:
1 to 32 MHz (VDD = 2.7 to 5.5 V),
1 to 16 MHz (VDD = 2.4 to 5.5 V),
1 to 8 MHz (VDD = 1.8 to 5.5 V),
1 to 4 MHz (VDD = 1.6 to 5.5 V)
<R>
Subsystem clock
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz
<R>
Low-speed on-chip oscillator
15 kHz (TYP.)
<R>
General-purpose register
(8-bit register × 8) × 4 banks
Minimum instruction execution time 0.03125 μs (High-speed on-chip oscillator: fIH = 32 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
•
•
•
•
Instruction set
I/O port
Timer
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
36
40
44
48
58
CMOS I/O
28
31
34
38
48
CMOS input
5
5
5
5
5
CMOS output
−
−
1
1
1
N-ch O.D I/O (6 V
tolerance)
3
4
4
4
4
16-bit timer
8 channels
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer (IT)
1 channel
Note 2
Timer output
4 channels (PWM
5 channels (PWM outputs: 4
),
Note 2
Note 3
Note 2
(PWM outputs: 7
)
outputs: 3 ),
8 channels
Note 3
(PWM
8 channels
Note 2
outputs: 7 )
RTC output
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
8 channels
(PWM outputs:
Note 2
)
7
Notes 1.
In the case of the 4 KB, this is about 3 KB when the self-programming function and data flash
function are used.
In the case of the 20 KB, this is about 19 KB when the self-programming function and data flash
function are used.
In the case of the 32 KB, this is about 31 KB when the self-programming function and data flash
function are used.
2. The number of outputs varies, depending on the setting of channels in use and the number of the master.
3. When setting to PIOR = 1
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 42 of 124
RL78/G13
CHAPTER 1 OUTLINE
(2/2)
Item
40-pin
44-pin
R5F101Lx
2
R5F100Lx
2
64-pin
R5F101Jx
R5F100Jx
2
52-pin
R5F101Gx
R5F100Gx
2
R5F101Fx
R5F100Fx
R5F101Ex
R5F100Ex
Clock output/buzzer output
48-pin
2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
<R>
8/10-bit resolution A/D converter
9 channels
10 channels
Serial interface
[40-pin, 44-pin products]
10 channels
12 channels
12 channels
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 2 channels/simplified I C: 2 channels/UART (UART supporting LIN-bus): 1 channel
2
[48-pin, 52-pin products]
• CSI: 2 channels/simplified I C: 2 channels/UART: 1 channel
2
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 2 channels/simplified I C: 2 channels/UART (UART supporting LIN-bus): 1 channel
2
[64-pin products]
• CSI: 2 channels/simplified I C: 2 channels/UART: 1 channel
2
• CSI: 2 channels/simplified I C: 2 channels/UART: 1 channel
2
• CSI: 2 channels/simplified I C: 2 channels/UART (UART supporting LIN-bus): 1 channel
2
2
I C bus
1 channel
1 channel
1 channel
Multiplier and divider/multiply-
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
accumulator
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
1 channel
1 channel
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
2 channels
Vectored
Internal
27
27
27
27
27
interrupt sources
External
7
7
10
12
13
4
4
6
8
8
Key interrupt
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
• Rising edge :
1.67 V to 4.06 V (14 stages)
• Falling edge :
1.63 V to 3.98 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 43 of 124
RL78/G13
CHAPTER 1 OUTLINE
[80-pin, 100-pin, 128-pin products]
Caution
This outline describes the functions at the time when Peripheral I/O redirection register (PIOR)
is set to 00H.
(1/2)
Item
80-pin
R5F100Mx
Code flash memory (KB)
100-pin
R5F101Mx
R5F100Px
96 to 512
Data flash memory (KB)
RAM (KB)
8 to 32
R5F101Px
R5F100Sx
96 to 512
−
8
128-pin
Note 1
−
8
8 to 32
R5F101Sx
192 to 512
−
8
Note 1
16 to 32
Note 1
Memory space
1 MB
Main system High-speed system
clock
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to
1.8 V
High-speed on-chip
oscillator
HS (High-speed main) mode:
HS (High-speed main) mode:
LS (Low-speed main) mode:
LV (Low-voltage main) mode:
1 to 32 MHz (VDD = 2.7 to 5.5 V),
1 to 16 MHz (VDD = 2.4 to 5.5 V),
1 to 8 MHz (VDD = 1.8 to 5.5 V),
1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz
<R>
Low-speed on-chip oscillator
15 kHz (TYP.)
<R>
General-purpose register
(8-bit register × 8) × 4 banks
Minimum instruction execution time
0.03125 μs (High-speed on-chip oscillator: fIH = 32 MHz operation)
<R>
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
•
•
•
•
Instruction set
I/O port
Timer
Total
74
92
120
CMOS I/O
64
82
110
CMOS input
5
5
5
CMOS output
1
1
1
N-ch O.D I/O (6 V
tolerance)
4
4
4
12 channels
12 channels
16 channels
1 channel
1 channel
1 channel
Real-time clock (RTC)
1 channel
1 channel
1 channel
12-bit interval timer (IT)
1 channel
1 channel
1 channel
16-bit timer
Watchdog timer
Notes 1.
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
12 channels
Note 2
(PWM outputs: 10
)
Timer output
12 channels
Note 2
)
(PWM outputs: 10
RTC output
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
16 channels
Note 2
(PWM outputs: 14
)
In the case of the 20 KB, this is about 19 KB when the self-programming function and data flash
function are used.
In the case of the 32 KB, this is about 31 KB when the self-programming function and data flash
function are used.
2.
The number of outputs varies, depending on the setting of channels in use and the number of the
master
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 44 of 124
RL78/G13
CHAPTER 1 OUTLINE
(2/2)
Item
80-pin
R5F100Mx
Clock output/buzzer output
100-pin
R5F101Mx
R5F100Px
2
R5F101Px
128-pin
R5F100Sx
2
R5F101Sx
2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
<R>
8/10-bit resolution A/D converter
17 channels
20 channels
Serial interface
[80-pin, 100-pin, 128-pin products]
26 channels
• CSI: 2 channels/simplified I C: 2 channels/UART: 1 channel
2
• CSI: 2 channels/simplified I C: 2 channels/UART: 1 channel
2
• CSI: 2 channels/simplified I C: 2 channels/UART (UART supporting LIN-bus): 1
2
channel
• CSI: 2 channels/simplified I C: 2 channels/UART: 1 channel
2
2
I C bus
2 channel
2 channel
2 channel
Multiplier and divider/multiply-
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
accumulator
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
4 channels
Vectored
Internal
37
37
41
interrupt sources
External
13
13
13
8
8
8
Key interrupt
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
• Rising edge :
1.67 V to 4.06 V (14 stages)
• Falling edge :
1.63 V to 3.98 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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RL78/G13
2. ELECTRICAL SPECIFICATIONS
2. ELECTRICAL SPECIFICATIONS
Cautions 1. The RL78/G13 microcontrollers have an on-chip debug function, which is provided for
development and evaluation. Do not use the on-chip debug function in products designated
for mass production, because the guaranteed number of rewritable times of the flash
memory may be exceeded when this function is used, and product reliability therefore
cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the
on-chip debug function is used.
2. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and
EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS.
3. The pins mounted depend on the product. Refer to 1.3.1 20-pin products to 1.3.14 128-pin
products.
R01DS0131EJ0200 Rev.2.00
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2. ELECTRICAL SPECIFICATIONS
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C) (1/2)
Parameter
Supply voltage
Symbols
Ratings
Unit
VDD
−0.5 to +6.5
V
EVDD0, EVDD1 EVDD0 = EVDD1
−0.5 to +6.5
V
VSS
−0.5 to +0.3
V
EVSS0, EVSS1
REGC pin input voltage VIREGC
Conditions
EVSS0 = EVSS1
−0.5 to +0.3
V
REGC
−0.3 to +2.8
V
and −0.3 to VDD +0.3
Input voltage
VI1
Note 1
P00 to P07, P10 to P17, P30 to P37, P40 to P47,
−0.3 to EVDD0 +0.3
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
and −0.3 to VDD +0.3
V
Note 2
P90 to P97, P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
VI2
VI3
−0.3 to +6.5
P60 to P63 (N-ch open-drain)
−0.3 to VDD +0.3
P20 to P27, P121 to P124, P137, P150 to P156,
V
Note 2
V
EXCLK, EXCLKS, RESET
Output voltage
VO1
−0.3 to EVDD0 +0.3
P00 to P07, P10 to P17, P30 to P37, P40 to P47,
P50 to P57, P60 to P67, P70 to P77, P80 to P87,
and −0.3 to VDD +0.3
V
Note 2
P90 to P97, P100 to P106, P110 to P117, P120,
P125 to P127, P130, P140 to P147
Analog input voltage
VO2
P20 to P27, P150 to P156
VAI1
ANI16 to ANI26
−0.3 to VDD +0.3
Note 2
−0.3 to EVDD0 +0.3
and −0.3 to AVREF(+) +0.3
VAI2
V
Notes 2, 3
−0.3 to VDD +0.3
ANI0 to ANI14
and −0.3 to AVREF(+) +0.3
Notes 1.
V
V
Notes 2, 3
Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2.
Must be 6.5 V or lower.
3.
Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
2.
AVREF (+) : + side reference voltage of the A/D converter.
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Oct 12, 2012
Page 47 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter
Output current, high
Symbols
IOH1
Conditions
Per pin
P00 to P07, P10 to P17,
Ratings
Unit
−40
mA
−70
mA
−100
mA
−0.5
mA
−2
mA
40
mA
70
mA
100
mA
1
mA
5
mA
−40 to +85
°C
−65 to +150
°C
P30 to P37, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P130, P140 to P147
Total of all pins
P00 to P04, P07, P32 to P37,
−170 mA
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to P145
P05, P06, P10 to P17, P30, P31,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100, P101,
P110 to P117, P146, P147
IOH2
Per pin
P20 to P27, P150 to P156
Total of all pins
Output current, low
IOL1
Per pin
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P130, P140 to P147
Total of all pins
P00 to P04, P07, P32 to P37,
170 mA
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to P145
P05, P06, P10 to P17, P30, P31,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100, P101,
P110 to P117, P146, P147
IOL2
Per pin
P20 to P27, P150 to P156
Total of all pins
Operating ambient
TA
temperature
Storage temperature
In normal operation mode
In flash memory programming mode
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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Oct 12, 2012
Page 48 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.2 Oscillator Characteristics
2.2.1 X1, XT1 oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Resonator
Recommended
Conditions
MIN.
TYP.
MAX.
Unit
Circuit
X1 clock
Ceramic
oscillation
resonator/
Note
frequency (fX)
crystal resonator
VSS X1
X2
Rd
1.0
20.0
MHz
1.8 V ≤ VDD < 2.7 V
1.0
8.0
MHz
1.6 V ≤ VDD < 1.8 V
1.0
4.0
MHz
35
kHz
C2
C1
XT1 clock
2.7 V ≤ VDD ≤ 5.5 V
Crystal resonator
32
VSS XT2
oscillation
Note
frequency (fX)
32.768
XT1
Rd
C4
C3
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1.
When using the X1 oscillator, XT1 oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2.
Since the CPU is started by the high-speed on-chip oscillator clock after a reset release,
check the X1 clock oscillation stabilization time using the oscillation stabilization time
counter status register (OSTC) by the user. Determine the oscillation stabilization time of the
OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently
evaluating the oscillation stabilization time with the resonator to be used.
3.
The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption,
and is more prone to malfunction due to noise than the X1 oscillator. Particular care is
therefore required with the wiring method when the XT1 clock is used.
R01DS0131EJ0200 Rev.2.00
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Page 49 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.2.2 On-chip oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Oscillators
Parameters
High-speed on-chip oscillator
clock frequency
Conditions
MAX.
Unit
1
32
MHz
1.8 V≤VDD≤5.5 V
−1
+1
%
1.6 V≤VDD<1.8 V
−5
+5
%
1.8 V≤VDD≤5.5 V
−1.5
+1.5
%
1.6 V≤VDD<1.8 V
−5.5
+5.5
%
fIH
MIN.
TYP.
Note 1
−20 to +85 °C
High-speed on-chip oscillator
clock frequency accuracy
Note 2
−40 to −20 °C
Low-speed on-chip oscillator
fIL
15
kHz
clock frequency
Low-speed on-chip oscillator
−15
+15
%
clock frequency accuracy
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and
bits 0 to 2 of HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution
time.
R01DS0131EJ0200 Rev.2.00
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Page 50 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Symbol
Output current,
Note 1
high
IOH1
IOH2
Notes 1.
Conditions
MIN.
TYP.
(1/5)
MAX.
Unit
−10.0
mA
Per pin for P00 to P07, P10 to P17,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120, P125 to P127,
P130, P140 to P147
1.6 V ≤ EVDD0 ≤ 5.5 V
Total of P00 to P04, P07, P32 to P37,
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to P145
Note 3
)
(When duty = 70%
4.0 V ≤ EVDD0 ≤ 5.5 V
−55.0
mA
2.7 V ≤ EVDD0 < 4.0 V
−10.0
mA
1.8 V ≤ EVDD0 < 2.7 V
−5.0
mA
1.6 V ≤ EVDD0 < 1.8 V
−2.5
mA
Total of P05, P06, P10 to P17, P30, P31,
P50 to P57, P64 to P67, P70 to P77,
P80 to P87, P90 to P97, P100, P101,
P110 to P117, P146, P147
Note 3
)
(When duty = 70%
4.0 V ≤ EVDD0 ≤ 5.5 V
−80.0
mA
2.7 V ≤ EVDD0 < 4.0 V
−19.0
mA
1.8 V ≤ EVDD0 < 2.7 V
−10.0
mA
1.6 V ≤ EVDD0 < 1.8 V
−5.0
mA
Total of all pins
Note 3
)
(When duty = 70%
1.6 V ≤ EVDD0 ≤ 5.5 V
−135.0
mA
Per pin for P20 to P27, P150 to P156
1.6 V ≤ VDD ≤ 5.5 V
Total of all pins
Note 3
)
(When duty = 70%
1.6 V ≤ VDD ≤ 5.5 V
Note 2
Note 4
−0.1
Note 2
−1.5
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from the EVDD0,
EVDD1, VDD pins to an output pin.
2.
3.
However, do not exceed the total current value.
Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOH = −10.0 mA
Total output current of pins = (−10.0 × 0.7)/(50 × 0.01) = −14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
4.
The applied current for the products for industrial application (R5F100xxDxx, R5F101xxDxx) is −100
mA.
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and
P142 to P144 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 51 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Symbol
Output current,
Note 1
low
IOL1
Conditions
MIN.
TYP.
Per pin for P00 to P07, P10 to P17,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120, P125 to P127,
P130, P140 to P147
20.0
Per pin for P60 to P63
15.0
Note 2
70.0
Unit
mA
mA
mA
15.0
mA
9.0
mA
4.5
mA
4.0 V ≤ EVDD0 ≤ 5.5 V
80.0
mA
2.7 V ≤ EVDD0 < 4.0 V
35.0
mA
1.8 V ≤ EVDD0 < 2.7 V
20.0
mA
1.6 V ≤ EVDD0 < 1.8 V
10.0
mA
Total of all pins
Note 3
(When duty = 70%
)
150.0
mA
Per pin for P20 to P27, P150 to P156
0.4
Total of P05, P06, P10 to P17, P30,
P31, P50 to P57, P64 to P67,
P70 to P77, P80 to P87, P90 to P97,
P100, P101, P110 to P117, P146,
P147
Note 3
)
(When duty = 70%
Total of all pins
Note 3
)
(When duty = 70%
Notes 1.
MAX.
Note 2
Total of P00 to P04, P07, P32 to P37, 4.0 V ≤ EVDD0 ≤ 5.5 V
P40 to P47, P102 to P106, P120,
2.7 V ≤ EVDD0 < 4.0 V
P125 to P127, P130, P140 to P145
Note 3
1.8 V ≤ EVDD0 < 2.7 V
)
(When duty = 70%
1.6 V ≤ EVDD0 < 1.8 V
IOL2
(2/5)
1.6 V ≤ VDD ≤ 5.5 V
Note 2
5.0
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the EVSS0, EVSS1 and VSS pin.
2.
3.
However, do not exceed the total current value.
Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(50 × 0.01) = 14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 52 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Input voltage,
Symbol
VIH1
Conditions
MIN.
P00 to P07, P10 to P17, P30 to P37, Normal input buffer
TYP.
(3/5)
MAX.
Unit
0.8EVDD0
EVDD0
V
2.2
EVDD0
V
2.0
EVDD0
V
1.5
EVDD0
V
0.7VDD
VDD
V
0.7EVDD0
6.0
V
0.8VDD
VDD
V
0
0.2EVDD0
V
0
0.8
V
0
0.5
V
0
0.32
V
P40 to P47, P50 to P57, P64 to P67,
high
P70 to P77, P80 to P87, P90 to P97,
P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
VIH2
P01, P03, P04, P10, P11,
TTL input buffer
P13 to P17, P43, P44, P53 to P55,
4.0 V ≤ EVDD0 ≤ 5.5 V
P80, P81, P142, P143
TTL input buffer
3.3 V ≤ EVDD0 < 4.0 V
TTL input buffer
1.6 V ≤ EVDD0 < 3.3 V
Input voltage,
VIH3
P20 to P27, P150 to P156
VIH4
P60 to P63
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
VIL1
P00 to P07, P10 to P17, P30 to P37, Normal input buffer
P40 to P47, P50 to P57, P64 to P67,
low
P70 to P77, P80 to P87, P90 to P97,
P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
VIL2
P01, P03, P04, P10, P11,
TTL input buffer
P13 to P17, P43, P44, P53 to P55,
4.0 V ≤ EVDD0 ≤ 5.5 V
P80, P81, P142, P143
TTL input buffer
3.3 V ≤ EVDD0 < 4.0 V
TTL input buffer
1.6 V ≤ EVDD0 < 3.3 V
VIL3
P20 to P27, P150 to P156
0
0.3VDD
V
VIL4
P60 to P63
0
0.3EVDD0
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2VDD
V
Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55,
P71, P74, P80 to P82, P96, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 53 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Symbol
Output voltage,
VOH1
Conditions
MIN.
MAX.
P00 to P07, P10 to P17, P30 to P37, 4.0 V ≤ EVDD0 ≤ 5.5 V, EVDD0 −
P40 to P47, P50 to P57, P64 to P67, IOH1 = −10.0 mA
high
TYP.
(4/5)
V
1.5
P70 to P77, P80 to P87, P90 to P97, 4.0 V ≤ EVDD0 ≤ 5.5 V, EVDD0 −
P100 to P106, P110 to P117, P120, IOH1 = −3.0 mA
0.7
P125 to P127, P130, P140 to P147
2.7 V ≤ EVDD0 ≤ 5.5 V, EVDD0 −
IOH1 = −2.0 mA
V
V
0.6
1.8 V ≤ EVDD0 ≤ 5.5 V, EVDD0 −
IOH1 = −1.5 mA
V
0.5
1.6 V ≤ EVDD0 < 1.8 V, EVDD0 −
IOH1 = −1.0 mA
VOH2
P20 to P27, P150 to P156
1.6 V ≤ VDD ≤ 5.5 V,
Unit
V
0.5
VDD − 0.5
V
IOH2 = −100 μ A
Output voltage,
VOL1
P00 to P07, P10 to P17, P30 to P37, 4.0 V ≤ EVDD0 ≤ 5.5 V,
1.3
V
0.7
V
0.6
V
0.4
V
0.4
V
0.4
V
0.4
V
2.0
V
0.4
V
0.4
V
0.4
V
0.4
V
P40 to P47, P50 to P57, P64 to P67, IOL1 = 20 mA
low
P70 to P77, P80 to P87, P90 to P97, 4.0 V ≤ EVDD0 ≤ 5.5 V,
P100 to P106, P110 to P117, P120, IOL1 = 8.5 mA
P125 to P127, P130, P140 to P147
4.0 V ≤ EVDD0 ≤ 5.5 V,
IOL1 = 3.0 mA
2.7 V ≤ EVDD0 ≤ 5.5 V,
IOL1 = 1.5 mA
1.8 V ≤ EVDD0 ≤ 5.5 V,
IOL1 = 0.6 mA
1.6 V ≤ EVDD0 < 5.5 V,
IOL1 = 0.3 mA
VOL2
P20 to P27, P150 to P156
1.6 V ≤ VDD ≤ 5.5 V,
IOL2 = 400 μ A
VOL3
P60 to P63
4.0 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 15.0 mA
4.0 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 5.0 mA
2.7 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 3.0 mA
1.8 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 2.0 mA
1.6 V ≤ EVDD0 < 5.5 V,
IOL3 = 1.0 mA
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and
P142 to P144 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 54 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Symbol
Input leakage
ILIH1
Conditions
P00 to P07, P10 to P17,
MIN.
TYP.
(5/5)
MAX.
Unit
VI = EVDD0
1
μA
VI = VDD
1
μA
1
μA
10
μA
VI = EVSS0
−1
μA
VI = VSS
−1
μA
−1
μA
−10
μA
100
kΩ
P30 to P37, P40 to P47,
current, high
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P140 to P147
ILIH2
P20 to P27, P137,
P150 to P156, RESET
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
current, low
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P140 to P147
ILIL2
P20 to P27, P137,
P150 to P156, RESET
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pull-up
RU
P00 to P07, P10 to P17,
VI = EVSS0, In input port
10
20
P30 to P37, P40 to P47,
resistance
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P140 to P147
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 55 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.3.2 Supply current characteristics
(1) Flash ROM: 16 to 64 KB of 20- to 64-pin products
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Supply
current
Symbol
Note 1
IDD1
Conditions
Operating
mode
HS (highspeed main)
Note 5
mode
fIH = 32 MHz
fIH = 24 MHz
fIH = 16 MHz
LS (lowspeed main)
Note 5
mode
fIH = 8 MHz
LV (lowvoltage
main) mode
fIH = 4 MHz
Note 3
MIN.
(1/2)
TYP.
MAX.
Unit
Basic
operation
VDD = 5.0 V
2.1
mA
VDD = 3.0 V
2.1
mA
Normal
operation
VDD = 5.0 V
4.6
7.0
mA
VDD = 3.0 V
4.6
7.0
mA
Normal
operation
VDD = 5.0 V
3.7
5.5
mA
VDD = 3.0 V
3.7
5.5
mA
Normal
operation
VDD = 5.0 V
2.7
4.0
mA
VDD = 3.0 V
2.7
4.0
mA
Normal
operation
VDD = 3.0 V
1.2
1.8
mA
VDD = 2.0 V
1.2
1.8
mA
Normal
operation
VDD = 3.0 V
1.2
1.7
mA
VDD = 2.0 V
1.2
1.7
mA
Note 2
Normal
operation
Square wave input
3.0
4.6
mA
Resonator connection
3.2
4.8
mA
Note 2
Normal
operation
Square wave input
3.0
4.6
mA
Resonator connection
3.2
4.8
mA
mA
Note 3
Note 3
Note 3
Note 3
Note 5
HS (highspeed main)
Note 5
mode
fMX = 20 MHz
,
VDD = 5.0 V
fMX = 20 MHz
,
VDD = 3.0 V
Note 2
fMX = 10 MHz
,
Square wave input
1.9
2.7
Resonator connection
1.9
2.7
mA
Normal
operation
Square wave input
1.9
2.7
mA
Resonator connection
1.9
2.7
mA
Note 2
Normal
operation
Square wave input
1.1
1.7
mA
Resonator connection
1.1
1.7
mA
Note 2
Normal
operation
Square wave input
1.1
1.7
mA
Resonator connection
1.1
1.7
mA
Normal
operation
Square wave input
4.1
μA
Resonator connection
4.2
μA
Normal
operation
Square wave input
4.1
4.9
μA
Resonator connection
4.2
5.0
μA
Normal
operation
Square wave input
4.2
5.5
μA
Resonator connection
4.3
5.6
μA
Normal
operation
Square wave input
4.2
6.3
μA
Resonator connection
4.3
6.4
μA
Normal
operation
Square wave input
4.8
7.7
μA
Resonator connection
4.9
7.8
μA
VDD = 5.0 V
Note 2
fMX = 10 MHz
,
VDD = 3.0 V
LS (lowspeed main)
Note 5
mode
fMX = 8 MHz
,
VDD = 3.0 V
fMX = 8 MHz
,
VDD = 2.0 V
Subsystem
clock
operation
fSUB = 32.768 kHz
Note 4
Normal
operation
TA = −40°C
fSUB = 32.768 kHz
Note 4
TA = +25°C
fSUB = 32.768 kHz
Note 4
TA = +50°C
fSUB = 32.768 kHz
Note 4
TA = +70°C
fSUB = 32.768 kHz
Note 4
TA = +85°C
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 56 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral
operation current (except for background operation (BGO)). However, not including the current flowing
into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter
and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation).
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 [email protected] MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 [email protected] MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 [email protected] MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 57 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(1) Flash ROM: 16 to 64 KB of 20- to 64-pin products
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
Supply
IDD2
HALT
current
Note 2
mode
Note 1
HS (highspeed main)
Note 7
mode
LS (lowspeed main)
Note 7
mode
LV (lowvoltage
main) mode
MIN.
fIH = 32 MHz
Note 4
fIH = 24 MHz
Note 4
fIH = 16 MHz
Note 4
fIH = 8 MHz
Note 4
fIH = 4 MHz
Note 4
(2/2)
TYP.
MAX.
Unit
VDD = 5.0 V
0.54
1.63
mA
VDD = 3.0 V
0.54
1.63
mA
VDD = 5.0 V
0.44
1.28
mA
VDD = 3.0 V
0.44
1.28
mA
VDD = 5.0 V
0.40
1.00
mA
VDD = 3.0 V
0.40
1.00
mA
VDD = 3.0 V
260
530
μA
VDD = 2.0 V
260
530
μA
VDD = 3.0 V
420
640
μA
VDD = 2.0 V
420
640
μA
Square wave input
0.28
1.00
mA
Resonator connection
0.45
1.17
mA
Square wave input
0.28
1.00
mA
Resonator connection
0.45
1.17
mA
Square wave input
0.19
0.60
mA
Resonator connection
0.26
0.67
mA
Square wave input
0.19
0.60
mA
Resonator connection
0.26
0.67
mA
Square wave input
95
330
μA
Resonator connection
145
380
μA
Square wave input
95
330
μA
Resonator connection
145
380
μA
Note 7
HS (highspeed main)
Note 7
mode
Note 3
fMX = 20 MHz
,
VDD = 5.0 V
Note 3
fMX = 20 MHz
,
VDD = 3.0 V
Note 3
fMX = 10 MHz
,
VDD = 5.0 V
Note 3
fMX = 10 MHz
,
VDD = 3.0 V
Note 3
LS (low-
fMX = 8 MHz
speed main)
VDD = 3.0 V
mode
,
Note 7
Note 3
fMX = 8 MHz
,
VDD = 2.0 V
Subsystem
fSUB = 32.768 kHz
Square wave input
0.25
μA
clock
TA = −40°C
Resonator connection
0.44
μA
fSUB = 32.768 kHz
Square wave input
0.30
0.57
μA
TA = +25°C
operation
Note 5
Note 5
Resonator connection
0.49
0.76
μA
fSUB = 32.768 kHz
Square wave input
0.33
1.17
μA
TA = +50°C
Resonator connection
0.52
1.36
μA
fSUB = 32.768 kHz
Square wave input
0.36
1.97
μA
TA = +70°C
Resonator connection
0.55
2.16
μA
fSUB = 32.768 kHz
Square wave input
0.97
3.37
μA
TA = +85°C
Resonator connection
1.16
3.56
μA
Note 5
Note 5
Note 5
Note 6
IDD3
STOP
mode
μA
TA = −40°C
0.18
TA = +25°C
0.23
0.50
μA
TA = +50°C
0.26
1.10
μA
TA = +70°C
0.29
1.90
μA
TA = +85°C
0.90
3.30
μA
Note 8
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 58 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral
operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port,
and on-chip pull-up/pull-down resistors.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When
high-speed on-chip oscillator and high-speed system clock are stopped.
When watchdog timer is
stopped. The values below the MAX. column include the leakage current.
6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When
watchdog timer is stopped. The values below the MAX. column include the leakage current.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 [email protected] MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD < 2.4 [email protected] MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 [email protected] MHz to 4 MHz
<R>
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT
mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25°C
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 59 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Supply
current
IDD1
Note 1
Conditions
Operating
mode
HS (highspeed main)
Note 5
mode
fIH = 32 MHz
Note 3
MIN.
(1/2)
TYP.
Basic
operation
VDD = 5.0 V
VDD = 3.0 V
2.3
Normal
operation
VDD = 5.0 V
5.2
MAX.
2.3
Unit
mA
mA
8.5
mA
VDD = 3.0 V
5.2
8.5
mA
fIH = 24 MHz
Note 3
Normal
operation
VDD = 5.0 V
4.1
6.6
mA
VDD = 3.0 V
4.1
6.6
mA
fIH = 16 MHz
Note 3
Normal
operation
VDD = 5.0 V
3.0
4.7
mA
VDD = 3.0 V
3.0
4.7
mA
Normal
operation
VDD = 3.0 V
1.3
2.1
mA
VDD = 2.0 V
1.3
2.1
mA
Normal
operation
VDD = 3.0 V
1.3
1.8
mA
VDD = 2.0 V
1.3
1.8
mA
LS (lowspeed main)
Note 5
mode
fIH = 8 MHz
LV (lowvoltage
main) mode
fIH = 4 MHz
Note 3
Note 3
Note 5
HS (highspeed main)
Note 5
mode
Note 2
fMX = 20 MHz
,
Square wave input
3.4
5.5
mA
Resonator connection
3.6
5.7
mA
Normal
operation
Square wave input
3.4
5.5
mA
Resonator connection
3.6
5.7
mA
Note 2
Normal
operation
Square wave input
2.1
3.2
mA
Resonator connection
2.1
3.2
mA
Note 2
Normal
operation
Square wave input
2.1
3.2
mA
Resonator connection
2.1
3.2
mA
Normal
operation
Square wave input
1.2
2.0
mA
Resonator connection
1.2
2.0
mA
Normal
operation
Square wave input
1.2
2.0
mA
Resonator connection
1.2
2.0
mA
Normal
operation
Square wave input
4.8
μA
Resonator connection
4.9
μA
Normal
operation
Square wave input
4.9
5.9
μA
Resonator connection
5.0
6.0
μA
Normal
operation
Square wave input
4.9
7.6
μA
Resonator connection
5.0
7.7
μA
Normal
operation
Square wave input
5.2
9.3
μA
Resonator connection
5.3
9.4
μA
Normal
operation
Square wave input
6.1
13.3
μA
Resonator connection
6.2
13.4
μA
VDD = 5.0 V
Note 2
fMX = 20 MHz
,
VDD = 3.0 V
fMX = 10 MHz
,
VDD = 5.0 V
fMX = 10 MHz
,
VDD = 3.0 V
LS (lowspeed main)
Note 5
mode
Note 2
fMX = 8 MHz
,
VDD = 3.0 V
Note 2
fMX = 8 MHz
,
VDD = 2.0 V
Subsystem
clock
operation
fSUB = 32.768 kHz
Note 4
Normal
operation
TA = −40°C
fSUB = 32.768 kHz
Note 4
TA = +25°C
fSUB = 32.768 kHz
Note 4
TA = +50°C
fSUB = 32.768 kHz
Note 4
TA = +70°C
fSUB = 32.768 kHz
Note 4
TA = +85°C
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 60 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
Notes 1. Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the
level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the
peripheral operation current (except for background operation (BGO)).
However, not including the
current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter
and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation).
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 [email protected] MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 [email protected] MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 [email protected] MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 61 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Supply
current
IDD2
Note 2
Conditions
HALT
mode
Note 1
HS (highspeed main)
Note 7
mode
TYP.
MAX.
Unit
fIH = 32 MHz
Note 4
VDD = 5.0 V
0.62
1.86
mA
VDD = 3.0 V
0.62
1.86
mA
fIH = 24 MHz
Note 4
VDD = 5.0 V
0.50
1.45
mA
VDD = 3.0 V
0.50
1.45
mA
fIH = 16 MHz
Note 4
VDD = 5.0 V
0.44
1.11
mA
LS (lowspeed main)
Note 7
mode
fIH = 8 MHz
LV (lowvoltage
main) mode
fIH = 4 MHz
MIN.
(2/2)
Note 4
Note 4
VDD = 3.0 V
0.44
1.11
mA
VDD = 3.0 V
290
620
μA
VDD = 2.0 V
290
620
μA
VDD = 3.0 V
440
680
μA
VDD = 2.0 V
440
680
μA
Note 7
HS (highspeed main)
Note 7
mode
Note 3
fMX = 20 MHz
,
VDD = 5.0 V
Note 3
fMX = 20 MHz
,
VDD = 3.0 V
Note 3
fMX = 10 MHz
,
VDD = 5.0 V
Note 3
fMX = 10 MHz
,
VDD = 3.0 V
LS (lowspeed main)
Note 7
mode
Note 3
fMX = 8 MHz
,
VDD = 3.0 V
fSUB = 32.768 kHz
TA = +85°C
Note 6
IDD3
STOP
Note 8
mode
0.31
1.08
mA
0.48
1.28
mA
Square wave input
0.21
0.63
mA
Resonator connection
0.28
0.71
mA
Square wave input
0.21
0.63
mA
Resonator connection
0.28
0.71
mA
Square wave input
110
360
μA
Resonator connection
160
420
μA
360
μA
μA
Note 5
Square wave input
0.28
Resonator connection
0.47
Note 5
Square wave input
0.34
0.61
μA
Resonator connection
0.53
0.80
μA
Square wave input
0.37
2.30
μA
Resonator connection
0.56
2.49
μA
Note 5
Note 5
TA = +70°C
fSUB = 32.768 kHz
Square wave input
Resonator connection
420
TA = +50°C
fSUB = 32.768 kHz
mA
110
TA = +25°C
fSUB = 32.768 kHz
mA
1.28
160
TA = −40°C
fSUB = 32.768 kHz
1.08
0.48
Square wave input
,
VDD = 2.0 V
Subsystem
clock
operation
0.31
Resonator connection
Resonator connection
Note 3
fMX = 8 MHz
Square wave input
Note 5
μA
μA
Square wave input
0.61
4.03
μA
Resonator connection
0.80
4.22
μA
Square wave input
1.55
8.04
μA
Resonator connection
1.74
8.23
μA
μA
TA = −40°C
0.19
TA = +25°C
0.25
0.52
μA
TA = +50°C
0.28
2.21
μA
TA = +70°C
0.52
3.94
μA
TA = +85°C
1.46
7.95
μA
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 62 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
Notes 1. Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the
level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the
peripheral operation current (except for background operation (BGO)).
However, not including the
current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When
high-speed on-chip oscillator and high-speed system clock are stopped.
When watchdog timer is
stopped. The values below the MAX. column include the leakage current.
6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When
watchdog timer is stopped. The values below the MAX. column include the leakage current.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 [email protected] MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 [email protected] MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 [email protected] MHz to 4 MHz
<R>
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT
mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 63 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Supply
current
IDD1
Note 1
Conditions
Operating
mode
HS (highspeed main)
Note 5
mode
fIH = 32 MHz
fIH = 24 MHz
fIH = 16 MHz
LS (lowspeed main)
Note 5
mode
fIH = 8 MHz
LV (lowvoltage
main) mode
fIH = 4 MHz
Note 3
Note 3
Note 3
Note 3
Note 3
MIN.
(1/2)
TYP.
MAX.
Unit
Basic
operation
VDD = 5.0 V
2.6
mA
VDD = 3.0 V
2.6
mA
Normal
operation
VDD = 5.0 V
6.1
9.5
mA
VDD = 3.0 V
6.1
9.5
mA
Normal
operation
VDD = 5.0 V
4.8
7.4
mA
VDD = 3.0 V
4.8
7.4
mA
Normal
operation
VDD = 5.0 V
3.5
5.3
mA
VDD = 3.0 V
3.5
5.3
mA
Normal
operation
VDD = 3.0 V
1.5
2.3
mA
VDD = 2.0 V
1.5
2.3
mA
Normal
operation
VDD = 3.0 V
1.5
2.0
mA
VDD = 2.0 V
1.5
2.0
mA
Note 5
HS (highspeed main)
Note 5
mode
Note 2
fMX = 20 MHz
,
VDD = 5.0 V
Note 2
fMX = 20 MHz
,
VDD = 3.0 V
Note 2
fMX = 10 MHz
,
VDD = 5.0 V
Note 2
fMX = 10 MHz
,
VDD = 3.0 V
LS (lowspeed main)
Note 5
mode
Note 2
fMX = 8 MHz
,
VDD = 3.0 V
Note 2
fMX = 8 MHz
,
VDD = 2.0 V
Subsystem
clock
operation
fSUB = 32.768 kHz
Note 4
Normal
operation
Normal
operation
Normal
operation
Square wave input
3.9
6.1
mA
Resonator connection
4.1
6.3
mA
Square wave input
3.9
6.1
mA
Resonator connection
4.1
6.3
mA
mA
Square wave input
2.5
3.7
Resonator connection
2.5
3.7
mA
Normal
operation
Square wave input
2.5
3.7
mA
Resonator connection
2.5
3.7
mA
Normal
operation
Square wave input
1.4
2.2
mA
Resonator connection
1.4
2.2
mA
Normal
operation
Square wave input
1.4
2.2
mA
Resonator connection
1.4
2.2
mA
Normal
operation
Square wave input
5.4
μA
Resonator connection
5.5
μA
Normal
operation
Square wave input
5.5
6.5
μA
Resonator connection
5.6
6.6
μA
Normal
operation
Square wave input
5.6
9.4
μA
Resonator connection
5.7
9.5
μA
Normal
operation
Square wave input
5.9
12.0
μA
Resonator connection
6.0
12.1
μA
Normal
operation
Square wave input
6.8
16.3
μA
Resonator connection
6.9
16.4
μA
TA = −40°C
fSUB = 32.768 kHz
Note 4
TA = +25°C
fSUB = 32.768 kHz
Note 4
TA = +50°C
fSUB = 32.768 kHz
Note 4
TA = +70°C
fSUB = 32.768 kHz
Note 4
TA = +85°C
(Notes and Remarks are listed on the next page.)
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RL78/G13
2. ELECTRICAL SPECIFICATIONS
Notes 1. Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the
level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the
peripheral operation current (except for background operation (BGO)).
However, not including the
current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter
and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation).
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 [email protected] MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 V @1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 [email protected] MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0131EJ0200 Rev.2.00
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RL78/G13
2. ELECTRICAL SPECIFICATIONS
(3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Supply
current
IDD2
Note 2
Conditions
HALT
mode
Note 1
HS (highspeed main)
Note 7
mode
TYP.
MAX.
Unit
fIH = 32 MHz
Note 4
VDD = 5.0 V
0.62
1.89
mA
VDD = 3.0 V
0.62
1.89
mA
fIH = 24 MHz
Note 4
VDD = 5.0 V
0.50
1.48
mA
VDD = 3.0 V
0.50
1.48
mA
fIH = 16 MHz
Note 4
VDD = 5.0 V
0.44
1.12
mA
LS (lowspeed main)
Note 7
mode
fIH = 8 MHz
LV (lowvoltage
main) mode
fIH = 4 MHz
MIN.
(2/2)
Note 4
Note 4
VDD = 3.0 V
0.44
1.12
mA
VDD = 3.0 V
290
620
μA
VDD = 2.0 V
290
620
μA
VDD = 3.0 V
460
700
μA
VDD = 2.0 V
460
700
μA
Note 7
HS (highspeed main)
Note 7
mode
Note 3
fMX = 20 MHz
,
VDD = 5.0 V
Note 3
fMX = 20 MHz
,
VDD = 3.0 V
Note 3
fMX = 10 MHz
,
VDD = 5.0 V
Note 3
fMX = 10 MHz
,
VDD = 3.0 V
LS (lowspeed main)
Note 7
mode
Note 3
fMX = 8 MHz
,
VDD = 3.0 V
fSUB = 32.768 kHz
TA = +85°C
Note 6
IDD3
STOP
Note 8
mode
0.31
1.14
mA
0.48
1.34
mA
Square wave input
0.21
0.68
mA
Resonator connection
0.28
0.76
mA
Square wave input
0.21
0.68
mA
Resonator connection
0.28
0.76
mA
Square wave input
110
390
μA
Resonator connection
160
450
μA
390
μA
μA
Note 5
Square wave input
0.31
Resonator connection
0.50
Note 5
Square wave input
0.38
0.66
μA
Resonator connection
0.57
0.85
μA
Square wave input
0.46
3.49
μA
Resonator connection
0.65
3.68
μA
Note 5
Note 5
TA = +70°C
fSUB = 32.768 kHz
Square wave input
Resonator connection
450
TA = +50°C
fSUB = 32.768 kHz
mA
110
TA = +25°C
fSUB = 32.768 kHz
mA
1.34
160
TA = −40°C
fSUB = 32.768 kHz
1.14
0.48
Square wave input
,
VDD = 2.0 V
Subsystem
clock
operation
0.31
Resonator connection
Resonator connection
Note 3
fMX = 8 MHz
Square wave input
Note 5
μA
μA
Square wave input
0.75
6.10
μA
Resonator connection
0.94
6.29
μA
Square wave input
1.65
10.46
μA
Resonator connection
1.84
10.65
μA
μA
TA = −40°C
0.19
TA = +25°C
0.26
0.54
μA
TA = +50°C
0.34
3.37
μA
TA = +70°C
0.63
5.98
μA
TA = +85°C
1.53
10.34
μA
(Notes and Remarks are listed on the next page.)
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RL78/G13
2. ELECTRICAL SPECIFICATIONS
Notes 1. Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the
level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the
peripheral operation current (except for background operation (BGO)).
However, not including the
current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When
high-speed on-chip oscillator and high-speed system clock are stopped.
When watchdog timer is
stopped. The values below the MAX. column include the leakage current.
6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When
watchdog timer is stopped. The values below the MAX. column include the leakage current.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 [email protected] MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 V @1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 [email protected] MHz to 4 MHz
<R>
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT
mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
R01DS0131EJ0200 Rev.2.00
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RL78/G13
2. ELECTRICAL SPECIFICATIONS
(4) Common to RL78/G13 all products
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Real-time clock operation
0.02
μA
12-bit Interval timer operation
0.02
μA
0.22
μA
IRTC
Notes 1, 2
IWDT
Notes 2, 3
fIL = 15 kHz
A/D converter
operating
current
IADC
Note 4
When conversion
at maximum
speed
A/D converter
reference
voltage current
IADREF
75.0
μA
Temperature
sensor
operating
current
ITMPS
75.0
μA
LVD operating
ILVI
0.08
μA
RTC operating
fSUB = 32.768 kHz
current
Watchdog timer
operating
current
Normal mode, AVREFP = VDD = 5.0 V
1.3
1.7
mA
Low voltage mode, AVREFP = VDD = 3.0 V
0.5
0.7
mA
Note 5
current
BGO operating
IBGO
Note 6
2.50
12.20
mA
0.50
0.60
mA
1.20
1.44
mA
0.70
0.84
mA
current
SNOOZE
ISNOZ
ADC operation
The mode is performed
Note 7
operating
The A/D conversion operations are
current
performed, Low voltage mode, AVREFP =
VDD = 3.0 V
CSI/UART operation
Notes 1. Current flowing only to the real-time clock (excluding the operating current of the XT1 oscillator). The
value of the current value of the RL78/G13 microcontrollers is the sum of the values of either IDD1 or IDD2,
and IRTC, when the real-time clock operates in operation mode or HALT mode. IDD2 subsystem clock
operation includes the operational current of the real-time clock.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
<R>
3. Current flowing only to the watchdog timer (including the operating current of the 15-kHz low-speed onchip oscillator). The current value of the RL78/G13 microcontrollers is the sum of IDD1, IDD2 or IDD3 and
IWDT when the watchdog timer is in operation.
4. Current flowing only to the A/D converter. The current value of the RL78/G13 microcontrollers is the sum
of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
<R>
5. Current flowing only to the LVD circuit. The current value of the RL78/G13 microcontrollers is the sum of
IDD1, IDD2 or IDD3 and ILVI .
6. Current flowing only to the BGO. The current value of the RL78/G13 microcontrollers is the sum of IDD1
or IDD2 and IBGO when the BGO operates in an operation mode.
<R>
7. For shift time to the SNOOZE mode, see 18.2.3 SNOOZE mode in the RL78/G13 User’s Manual.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
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RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.4 AC Characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
Main
system
clock (fMAIN)
operation
MAX.
Unit
HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.03125
main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
1
μs
1
μs
LV (low-voltage 1.6 V ≤ VDD ≤ 5.5 V
main) mode
0.25
1
μs
LS (low-speed 1.8 V ≤ VDD ≤ 5.5 V
main) mode
0.125
1
μs
1.8 V ≤ VDD ≤ 5.5 V
28.5
31.3
μs
1
μs
1
μs
1
μs
0.125
1
μs
1.0
20.0
MHz
Subsystem clock (fSUB)
MIN.
TYP.
30.5
operation
In the self
HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.03125
programming main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
mode
0.25
LV (low-voltage 1.8 V ≤ VDD ≤ 5.5 V
main) mode
LS (low-speed 1.8 V ≤ VDD ≤ 5.5 V
main) mode
External system clock frequency fEX
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
1.0
8.0
MHz
1.6 V ≤ VDD < 1.8 V
1.0
4.0
MHz
32
35
kHz
2.7 V ≤ VDD ≤ 5.5 V
24
ns
1.8 V ≤ VDD < 2.7 V
60
ns
1.6 V ≤ VDD < 1.8 V
120
ns
13.7
μs
fEXS
<R>
External system clock input
high-level width, low-level width
tEXH, tEXL
tEXHS, tEXLS
TI00 to TI07, TI10 to TI17 input
high-level width, low-level width
tTIH,
tTIL
TO00 to TO07, TO10 to TO17
output frequency
fTO
PCLBUZ0, PCLBUZ1 output
frequency
fPCL
Note
1/fMCK+10
ns
4.0 V ≤ EVDD0 ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD0 < 4.0 V
8
MHz
1.8 V ≤ EVDD0 < 2.7 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
LV (low-voltage
main) mode
1.6 V ≤ EVDD0 ≤ 5.5 V
2
MHz
LS (low-speed
main) mode
1.8 V ≤ EVDD0 ≤ 5.5 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
HS (high-speed
main) mode
4.0 V ≤ EVDD0 ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD0 < 4.0 V
8
MHz
1.8 V ≤ EVDD0 < 2.7 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
LV (low-voltage
main) mode
1.8 V ≤ EVDD0 ≤ 5.5 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
LS (low-speed
main) mode
1.8 V ≤ EVDD0 ≤ 5.5 V
4
MHz
2
MHz
HS (high-speed
main) mode
1.6 V ≤ EVDD0 < 1.8 V
1
μs
1.6 V ≤ EVDD0 ≤ 5.5 V
1
μs
1.8 V ≤ EVDD0 ≤ 5.5 V
250
ns
1
μs
10
μs
1.6 V ≤ VDD ≤ 5.5 V
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP0
INTP1 to INTP11
Key interrupt input low-level
width
tKR
KR0 to KR7
1.6 V ≤ EVDD0 < 1.8 V
RESET low-level width
tRSL
(Note and Remark are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS
Note The following conditions are required for low voltage interface when EVDD0<VDD
1.8 V ≤ EVDD0 < 2.7 V : MIN. 125 ns
1.6 V ≤ EVDD0 < 1.8 V : MIN. 250 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn).
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7))
AC Timing Test Points
VIH
VIH
Test points
VIL
VIL
External System Clock Timing
1/fEX
tEXL
tEXH
0.7VDD (MIN.)
0.3VDD (MAX.)
EXCLK
TI/TO Timing
tTIH
tTIL
TI00 to TI07, TI10 to TI17
1/fTO
TO00 to TO07, TO10 to TO17
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP11
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2. ELECTRICAL SPECIFICATIONS
Key Interrupt Input Timing
tKR
KR0 to KR7
RESET Input Timing
tRSL
RESET
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2. ELECTRICAL SPECIFICATIONS
2.5 Peripheral Functions Characteristics
2.5.1 Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
Note 1
MAX.
fMCK/6
Theoretical value of the
Unit
Note 2
5.3
bps
Mbps
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
UART mode connection diagram (during communication at same potential)
Rx
TxDq
RL78/G13
User's device
Tx
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Notes 1. Transfer rate in the SNOOZE mode is MAX. 9600 bps, MIN. 4800 bps.
2. The following conditions are required for low voltage interface when EVDD0<VDD.
2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps
1.6 V ≤ EVDD0 < 1.8 V : MAX. 0.6 Mbps
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
2.
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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2. ELECTRICAL SPECIFICATIONS
(2) During communication at same potential (CSI mode) (master mode (fMCK/2), SCKp... internal clock
output, coresponting CSI00 only)
(TA = −40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCKp cycle time
tKCY1
2.7 V ≤ EVDD0 ≤ 5.5 V
62.5
SCKp high-/low-level width
tKH1,
4.0 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 − 7
ns
tKL1
2.7 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 − 10
ns
tSIK1
4.0 V ≤ EVDD0 ≤ 5.5 V
23
ns
SIp setup time (to SCKp↑)
Note 2
2.7 V ≤ EVDD0 ≤ 5.5 V
SIp hold time (from SCKp↑)
Note 3
Delay time from SCKp↓ to
SOp output
tKSI1
2.7 V ≤ EVDD0 ≤ 5.5 V
tKSO1
C = 20 pF
33
Note 1
ns
Note 5
ns
10
Note 6
ns
10
ns
Note 4
Notes 1. The value must also be 2/fCLK or more.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. Using the fMCK within 24 MHz.
6. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
2.
This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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2. ELECTRICAL SPECIFICATIONS
(3) During communication at same potential (CSI mode) (master mode (fMCK/4), SCKp... internal clock output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
SCKp cycle time
tKCY1
Conditions
2.7 V ≤ EVDD0 ≤ 5.5 V
TYP.
MAX.
Unit
125
Note 1
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
250
Note 1
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
500
Note 1
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
SCKp high-/low-level width
MIN.
1000
Note 1
ns
tKH1,
4.0 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 − 12
ns
tKL1
2.7 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 − 18
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 − 38
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 − 50
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 −
ns
100
SIp setup time (to SCKp↑)
Note 2
SIp hold time (from SCKp↑)
Note 3
Delay time from SCKp↓ to
SOp output
tSIK1
4.0 V ≤ EVDD0 ≤ 5.5 V
44
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
44
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
75
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
110
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
220
ns
19
ns
tKSI1
tKSO1
Note 5
C = 30 pF
25
ns
Note 4
Notes 1. The value must also be 4/fCLK or more.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0
to 3),
g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
R01DS0131EJ0200 Rev.2.00
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RL78/G13
2. ELECTRICAL SPECIFICATIONS
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCKp cycle time
Note 5
SCKp high-/low-level width
Symbol
tKCY2
tKH2,
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ EVDD0 ≤ 5.5 V 20 MHz < fMCK
8/fMCK
ns
fMCK ≤ 20 MHz
6/fMCK
ns
2.7 V ≤ EVDD0 < 4.0 V 16 MHz < fMCK
8/fMCK
ns
fMCK ≤ 16 MHz
6/fMCK
ns
1.8 V ≤ EVDD0 < 2.7 V 16 MHz < fMCK
8/fMCK
ns
fMCK ≤ 16 MHz
6/fMCK
ns
1.6 V ≤ EVDD0 < 1.8 V
6/fMCK
ns
1.6 V ≤ EVDD0≤ 5.5 V
tKCY2/2
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
1/fMCK+20
ns
1.8 V ≤ EVDD0 < 2.7 V
1/fMCK+30
ns
1.6 V ≤ EVDD0 < 1.8 V
1/fMCK+40
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
1/fMCK+31
ns
1.8 V ≤ EVDD0 < 2.7 V
1/fMCK+31
ns
1.6 V ≤ EVDD0 < 1.8 V
1/fMCK+
ns
tKL2
SIp setup time
(to SCKp↑)
tSIK2
Note 1
SIp hold time
(from SCKp↑)
tKSI2
Note 2
250
Delay time from SCKp↓ to
SOp output
tKSO2
Note 3
C = 30 pF
Note 4
4.0 V ≤ EVDD0 ≤ 5.5 V
2/fMCK+44
ns
2.7 V ≤ EVDD0 < 4.0 V
2/fMCK+44
ns
2.4 V ≤ EVDD0 < 2.7 V
2/fMCK+75
ns
1.8 V ≤ EVDD0 < 2.4 V
2/fMCK+110
ns
1.6 V ≤ EVDD0 < 1.8 V
2/fMCK+220
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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RL78/G13
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at same potential)
SCK
SCKp
RL78/G13
SIp
SO
SOp
SI
User's device
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
R01DS0131EJ0200 Rev.2.00
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Page 76 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2
(5) During communication at same potential (simplified I C mode)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCLr clock frequency
Symbol
fSCL
Conditions
MIN.
2.7 V ≤ EVDD0 ≤ 5.5 V,
MAX.
Unit
1000
kHz
400
kHz
300
kHz
250
kHz
Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “L”
tLOW
2.7 V ≤ EVDD0 ≤ 5.5 V,
475
ns
1150
ns
1550
ns
1850
ns
475
ns
1150
ns
1550
ns
1850
ns
1/fMCK + 85
ns
Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “H”
tHIGH
2.7 V ≤ EVDD0 ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Data setup time (reception)
tSU:DAT
2.7 V ≤ EVDD0 ≤ 5.5 V,
Note
Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD ≤ 5.5 V,
1/fMCK + 145
ns
Note
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ EVDD0 < 2.7 V,
1/fMCK + 230
ns
Note
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ EVDD0 < 1.8 V,
1/fMCK + 290
ns
Note
Cb = 100 pF, Rb = 5 kΩ
Data hold time (transmission)
tHD:DAT
2.7 V ≤ EVDD0 ≤ 5.5 V,
0
305
ns
0
355
ns
0
405
ns
0
405
ns
Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Note Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
(Caution and Remarks are listed on the next page.)
R01DS0131EJ0200 Rev.2.00
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Page 77 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2
Simplified I C mode mode connection diagram (during communication at same potential)
VDD
Rb
SDA
SDAr
RL78/G13
User's device
SCL
SCLr
2
Simplified I C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
Caution
tSU:DAT
Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin
products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the normal
output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode
register h (POMh).
Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14),
h: POM number (g = 0, 1, 4, 5, 7 to 9, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m
= 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
R01DS0131EJ0200 Rev.2.00
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RL78/G13
2. ELECTRICAL SPECIFICATIONS
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(dedicated baud rate generator output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
Reception 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
MAX.
fMCK/6
Theoretical value of the
Note 1
5.3
Unit
bps
Mbps
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
fMCK/6
Theoretical value of the
Note 1
bps
5.3
Mbps
fMCK/6
bps
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
1.8 V ≤ EVDD0 < 3.3 V,
Notes 1 to 3
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the
1.3
Mbps
maximum transfer rate
fCLK = 8 MHz, fMCK = fCLK
Notes 1. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps
2. Use it with EVDD0≥Vb.
3. The following conditions are required for low voltage interface when EVDD0<VDD.
2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps
1.6 V ≤ EVDD0 < 1.8 V : MAX. 0.6 Mbps
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
2.
3.
Vb[V]: Communication line voltage
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
4.
UART2 cannnot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection
register (PIOR) is 1.
R01DS0131EJ0200 Rev.2.00
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Page 79 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(dedicated baud rate generator output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
Transmission 4.0 V ≤ EVDD0 ≤ 5.5 V,
MAX.
Unit
Notes
bps
1, 2
2.7 V ≤ Vb ≤ 4.0 V
Theoretical value of the
2.8
Note 3
Mbps
maximum transfer rate
Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V
2.7 V ≤ EVDD0 < 4.0 V,
Notes
bps
2, 4
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value of the
1.2
Note 5
Mbps
maximum transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
1.8 V ≤ EVDD0 < 3.3 V,
Notes
1.6 V ≤ Vb ≤ 2.0 V
2, 6, 7
Theoretical value of the
maximum transfer rate
0.43
bps
Mbps
Note 8
Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
Notes 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ EVDD0 ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.2
)} × 3
Vb
[bps]
2.2
1
− {−Cb × Rb × ln (1 −
)}
Vb
Transfer rate × 2
1
(
) × Number of transferred bits
Transfer rate
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.
3.
Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps
This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
4.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.0
)} × 3
Vb
[bps]
2.0
1
− {−Cb × Rb × ln (1 −
)}
Vb
Transfer rate × 2
1
(
) × Number of transferred bits
Transfer rate
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
5.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
R01DS0131EJ0200 Rev.2.00
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RL78/G13
Notes 6.
7.
2. ELECTRICAL SPECIFICATIONS
Use it with EVDD0 ≥ Vb.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
1.5
)} × 3
Vb
[bps]
1.5
1
− {−Cb × Rb × ln (1 −
)}
Vb
Transfer rate × 2
1
(
) × Number of transferred bits
Transfer rate
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
8.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
Rb[Ω]:Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
4.
UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection
register (PIOR) is 1.
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
RL78/G13
User's device
RxDq
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Tx
Page 81 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
UART2 cannot communicate at different potentia when bit 1 (PIOR1) of peripheral I/O redirection
register (PIOR) is 1.
2.
Rb[Ω]:Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
3.
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
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RL78/G13
2. ELECTRICAL SPECIFICATIONS
(7) Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock
output, coresponting CSI00 only)
(TA = −40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCKp cycle time
Symbol
tKCY1
Conditions
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MIN.
TYP.
MAX.
Unit
200
Note 1
ns
300
Note 1
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp high-level width
tKH1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 50
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp low-level width
tKL1
tKCY1/2 −
ns
120
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 7
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 10
ns
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
(to SCKp↑)
tSIK1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
58
ns
121
ns
10
ns
10
ns
Note 2
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↑)
tKSI1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 2
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↓ to
SOp output
tKSO1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
60
ns
130
ns
Note 2
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
(to SCKp↓)
tSIK1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
21
ns
29
ns
10
ns
10
ns
Note 3
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↓)
tKSI1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 3
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↑ to
SOp output
tKSO1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
10
ns
10
ns
Note 3
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
(Note, Caution and Remark are listed on the next page.)
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 83 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at different potential)
Vb
<Master>
Rb
Vb
Rb
SCKp
RL78/G13
SCK
SIp
SO
SOp
SI
User's device
Notes 1. The value must also be 2/fCLK or more.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
3. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
4. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
R01DS0131EJ0200 Rev.2.00
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Page 84 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCKp cycle time
Symbol
tKCY1
Conditions
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MIN.
TYP.
MAX.
Unit
300
Note
ns
500
Note
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
1150
Note
ns
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
tKH1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 75
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
tKCY1/2 −
ns
170
tKCY1/2 −
ns
458
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 12
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 18
ns
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 − 50
ns
Cb = 30 pF, Rb = 5.5 kΩ
Note
The value must also be 4/fCLK or more.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance
(When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the
SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
2. Use it with EVDD0 ≥ Vb.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10,
12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 85 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SIp setup time
Note 1
(to SCKp↑)
Symbol
tSIK1
Conditions
MIN.
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
81
TYP.
MAX.
Unit
ns
177
ns
479
ns
19
ns
19
ns
19
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
Note 1
(from SCKp↑)
tKSI1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↓ to
Note 1
SOp output
tKSO1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
100
ns
195
ns
483
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp setup time
Note 2
(to SCKp↓)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
44
ns
44
ns
110
ns
19
ns
19
ns
19
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
Note 2
(from SCKp↓)
tKSI1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↑ to
Note 2
SOp output
tKSO1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
25
ns
25
ns
25
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
(Notes, Cautions and Remarks are listed on the next page.)
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 86 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at different potential)
Vb
<Master>
Rb
Vb
Rb
SCKp
RL78/G13
SCK
SIp
SO
SOp
SI
User's device
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance
(When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the
SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
2. Use it with EVDD0 ≥ Vb.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10,
12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 87 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 00, 01, 02, 10, 12, 13), n: Channel
number (n = 0, 2), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 88 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCKp cycle time
Note 1
Symbol
tKCY2
SCKp high-/low-level
tKH2,
width
tKL2
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ EVDD0 ≤ 5.5 V, 24 MHz < fMCK
14/fMCK
ns
2.7 V ≤ Vb ≤ 4.0 V
20 MHz < fMCK ≤ 24 MHz
12/fMCK
ns
8 MHz < fMCK ≤ 20 MHz
10/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
ns
fMCK ≤ 4 MHz
6/fMCK
ns
2.7 V ≤ EVDD0 < 4.0 V, 24 MHz < fMCK
20/fMCK
ns
2.3 V ≤ Vb ≤ 2.7 V
20 MHz < fMCK ≤ 24 MHz
16/fMCK
ns
16 MHz < fMCK ≤ 20 MHz
14/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
12/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
ns
fMCK ≤ 4 MHz
6/fMCK
ns
1.8 V ≤ EVDD0 < 3.3 V, 24 MHz < fMCK
48/fMCK
ns
1.6 V ≤ Vb ≤ 2.0 V
36/fMCK
ns
16 MHz < fMCK ≤ 20 MHz
32/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
26/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
10/fMCK
ns
tKCY2/2 −
ns
Note 2
20 MHz < fMCK ≤ 24 MHz
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
12
tKCY2/2 −
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
ns
18
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note 2
tKCY2/2 −
ns
50
SIp setup time
(to SCKp↑)
tSIK2
2.7 V ≤ EVDD0 ≤ 5.5 V, 2.3 V ≤ Vb ≤ 4.0 V
Note 2
1/fMCK +
Note 3
ns
20
1.8 V ≤ EVDD0 ≤ 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note 2
1/fMCK +
ns
30
SIp hold time
(from SCKp↑)
tKSI2
Delay time from SCKp↓ to
SOp output
1/fMCK + 31
ns
Note 4
tKSO2
Note 5
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
2/fMCK +
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
2/fMCK +
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
ns
120
ns
214
Note 2
,
2/fMCK +
ns
573
(Notes, Caution and Remarks are listed on the next page.)
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 89 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at different potential)
Vb
<Slave>
Rb
SCKp
RL78/G13
SCK
SIp
SO
SOp
SI
User's device
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. Use it with EVDD0 ≥ Vb.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for
the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 00, 01,
02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13))
4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 90 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Output data
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for
the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number,
n: Channel number (mn = 00, 01, 02, 10, 12. 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 91 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCLr clock frequency
Symbol
fSCL
Conditions
MIN.
4.0 V ≤ EVDD0 ≤ 5.5 V,
MAX.
Unit
1000
kHz
1000
kHz
400
kHz
400
kHz
300
kHz
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 1
,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “L”
tLOW
4.0 V ≤ EVDD0 ≤ 5.5 V,
475
ns
475
ns
1150
ns
1150
ns
1550
ns
245
ns
200
ns
675
ns
600
ns
610
ns
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 1
,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “H”
tHIGH
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 1
,
Cb = 100 pF, Rb = 5.5 kΩ
(Notes, Caution and Remarks are listed on the next page.)
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 92 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Data setup time (reception)
Data hold time (transmission)
Symbol
tSU:DAT
tHD:DAT
Conditions
MIN.
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 135
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 135
MAX.
Unit
ns
Note 2
ns
Note 2
1/fMCK + 190
4.0 V ≤ EVDD0 ≤ 5.5 V,
Note 2
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
ns
1/fMCK + 190
2.7 V ≤ EVDD0 < 4.0 V,
Note 2
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
ns
1.8 V ≤ EVDD0 < 3.3 V,
1/fMCK + 190
Note 2
Notes 1
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 100 pF, Rb = 5.5 kΩ
ns
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
305
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
305
ns
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
0
355
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0
355
ns
1.8 V ≤ EVDD0 < 3.3 V,
Note 1
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 100 pF, Rb = 5.5 kΩ
0
405
ns
Notes 1. Use it with EVDD0 ≥ Vb.
2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin
products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the N-ch
open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output
mode register g (POMg).
(Remarks is listed on the next page.)
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Page 93 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2
Simplified I C mode connection diagram (during communication at different potential)
Vb
Rb
Vb
Rb
SDA
SDAr
RL78/G13
User's device
SCL
SCLr
2
Simplified I C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
tSU:DAT
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin
products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the N-ch
open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output
mode register g (POMg).
Remarks 1. Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr)
load capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n:
Channel number (mn = 00, 01, 02, 10, 12, 13)
R01DS0131EJ0200 Rev.2.00
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Page 94 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.5.2 Serial interface IICA
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Standard
Conditions
Fast Mode
Fast Mode
MIN.
SCLA0 clock frequency
fSCL
MAX.
MIN.
MAX.
MIN.
MAX.
0
1000
Fast mode plus: 2.7 V ≤ EVDD0 ≤ 5.5 V
fCLK ≥ 10 MHz
Fast mode:
1.8 V ≤ EVDD0 ≤ 5.5 V
Unit
Plus
Mode
0
400
kHz
kHz
fCLK ≥ 3.5 MHz
Normal mode:
1.6 V ≤ EVDD0 ≤ 5.5 V
0
100
kHz
fCLK ≥ 1 MHz
tSU:STA
4.7
0.6
0.26
μs
tHD:STA
4.0
0.6
0.26
μs
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
0.5
μs
Hold time when SCLA0 = “H”
tHIGH
4.0
0.6
0.26
μs
tSU:DAT
250
100
50
ns
Setup time of restart condition
Hold time
Note 1
Data setup time (reception)
Note 2
tHD:DAT
0
Setup time of stop condition
tSU:STO
4.0
0.6
0.26
μs
Bus-free time
tBUF
4.7
1.3
0.5
μs
Notes 1.
2.
Remark
3.45
0
0.9
0
0.45
μs
Data hold time (transmission)
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
Fast mode:
Cb = 320 pF, Rb = 1.1 kΩ
Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ
IICA serial transfer timing
tLOW
SCL0
tHD:DAT
tHD:STA
tHIGH
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDA0
tLOW
Stop
condition
Start
condition
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Restart
condition
Stop
condition
Page 95 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.5.3 On-chip debug (UART)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
Transfer rate
MIN.
TYP.
115.2 k
MAX.
Unit
1M
bps
2.6 Analog Characteristics
2.6.1 A/D converter characteristics
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), target
ANI pin : ANI2 to ANI14
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) =
AVREFP, Reference voltage (−) = AVREFM = 0 V)
Parameter
Symbol
Resolution
<R>
Conditions
RES
Note 1
Overall error
AINL
Conversion time
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
TYP.
8
MAX.
Unit
10
bit
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
1.2
±3.5
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
1.2
±7.0
LSB
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
AVREFP = VDD
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
1.6 V ≤ VDD ≤ 5.5 V
57
95
μs
EZS
10-bit resolution
AVREFP = VDD
1.8 V ≤ VDD ≤ 5.5 V
±0.25
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.50
%FSR
EFS
10-bit resolution
AVREFP = VDD
1.8 V ≤ VDD ≤ 5.5 V
±0.25
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.50
%FSR
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±2.5
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
±5.0
LSB
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±1.5
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
±2.0
LSB
1.6
VDD
V
0
AVREFP
V
1.5
V
ILE
Note 1
MIN.
DLE
Reference voltage (+)
AVREFP
Analog input voltage
VAIN
VBGR
Select interanal reference voltage output
1.38
1.45
2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0131EJ0200 Rev.2.00
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Page 96 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(2) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), target
ANI pin : ANI16 to ANI26
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) =
AVREFP, Reference voltage (−) = AVREFM)
Parameter
Symbol
Resolution
<R>
Conditions
RES
Note 1
Overall error
AINL
Conversion time
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
TYP.
8
MAX.
Unit
10
bit
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
1.2
±5.0
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
1.2
±8.5
LSB
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
AVREFP = VDD
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
1.6 V ≤ VDD ≤ 5.5 V
57
95
μs
EZS
10-bit resolution
AVREFP = VDD
1.8 V ≤ VDD ≤ 5.5 V
±0.35
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
EFS
10-bit resolution
AVREFP = VDD
1.8 V ≤ VDD ≤ 5.5 V
±0.35
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±3.5
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
±6.0
LSB
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±2.0
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
±2.5
LSB
1.6
VDD
V
0
AVREFP
V
ILE
Note 1
MIN.
DLE
Reference voltage (+)
AVREFP
Analog input voltage
VAIN
and
EVDD0
VBGR
Select interanal reference voltage output
1.38
1.45
1.5
V
2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0131EJ0200 Rev.2.00
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Page 97 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(3) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (−) = VSS (ADREFM = 0), target ANI pin : ANI0 to
ANI14, ANI16 to ANI26
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD,
Reference voltage (−) = VSS)
Parameter
Symbol
Resolution
<R>
Conditions
RES
Note 1
Overall error
AINL
Conversion time
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
Note 1
Analog input voltage
10-bit resolution
10-bit resolution
10-bit resolution
EFS
10-bit resolution
DLE
VAIN
VBGR
TYP.
8
EZS
ILE
MIN.
10-bit resolution
10-bit resolution
MAX.
Unit
10
bit
1.8 V ≤ VDD ≤ 5.5 V
1.2
±7.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
1.2
±10.5
LSB
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
1.6 V ≤ VDD ≤ 5.5 V
57
95
μs
1.8 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.85
%FSR
1.8 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.85
%FSR
1.8 V ≤ VDD ≤ 5.5 V
±4.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
±6.5
LSB
1.8 V ≤ VDD ≤ 5.5 V
±2.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
±2.5
LSB
ANI0 to ANI14
0
VDD
V
ANI16 to ANI26
0
EVDD0
V
1.5
V
Select interanal reference voltage output,
1.38
1.45
2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 98 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
(4) When AVREF
(+)
= Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF
(−)
= AVREFM/ANI1
(ADREFM = 1), target ANI pin : ANI0 to ANI14, ANI16 to ANI26
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR, Reference
voltage (−) = AVREFM = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Notes 1, 2
Zero-scale error
Integral linearity error
Note 1
Differential linearity error
Note 1
TYP.
MAX.
8
Unit
bit
tCONV
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
39
μs
EZS
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
ILE
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±2.0
LSB
DLE
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±1.0
LSB
1.5
V
VBGR
V
17
Reference voltage (+)
VBGR
1.38
Analog input voltage
VAIN
0
1.45
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 99 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.6.2 Temperature sensor characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, HS (high-speed main) mode)
Parameter
<R>
Symbol
Conditions
Temperature sensor output voltage VTMPS25
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VCONST
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
MIN.
TYP.
MAX.
1.05
1.38
1.45
Unit
V
1.5
−3.6
V
mV/°C
temperature
Operation stabilization wait time
tAMP
5
μs
2.6.3 POR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Detection voltage
Minimum pulse width
Detection delay time
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
Power supply rise time
1.48
1.51
1.54
V
VPDR
Power supply fall time
1.47
1.50
1.53
V
TPW
μs
300
350
μs
Page 100 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.6.4 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = −40 to +85°C, VPDR ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Detection
Supply voltage level
Symbol
VLVD0
voltage
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
VLVD12
VLVD13
Minimum pulse width
Detection delay time
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
tLW
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.98
4.06
4.14
V
Power supply fall time
3.90
3.98
4.06
V
Power supply rise time
3.68
3.75
3.82
V
Power supply fall time
3.60
3.67
3.74
V
Power supply rise time
3.07
3.13
3.19
V
Power supply fall time
3.00
3.06
3.12
V
Power supply rise time
2.96
3.02
3.08
V
Power supply fall time
2.90
2.96
3.02
V
Power supply rise time
2.86
2.92
2.97
V
Power supply fall time
2.80
2.86
2.91
V
Power supply rise time
2.76
2.81
2.87
V
Power supply fall time
2.70
2.75
2.81
V
Power supply rise time
2.66
2.71
2.76
V
Power supply fall time
2.60
2.65
2.70
V
Power supply rise time
2.56
2.61
2.66
V
Power supply fall time
2.50
2.55
2.60
V
Power supply rise time
2.45
2.50
2.55
V
Power supply fall time
2.40
2.45
2.50
V
Power supply rise time
2.05
2.09
2.13
V
Power supply fall time
2.00
2.04
2.08
V
Power supply rise time
1.94
1.98
2.02
V
Power supply fall time
1.90
1.94
1.98
V
Power supply rise time
1.84
1.88
1.91
V
Power supply fall time
1.80
1.84
1.87
V
Power supply rise time
1.74
1.77
1.81
V
Power supply fall time
1.70
1.73
1.77
V
Power supply rise time
1.64
1.67
1.70
V
Power supply fall time
1.60
1.63
1.66
V
μs
300
300
μs
Page 101 of 124
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2. ELECTRICAL SPECIFICATIONS
LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +85°C, VPDR ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Interrupt and reset VLVD13
mode
VLVD12
Conditions
VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage: 1.6 V
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
(+0.1 V)
VLVD11
VLVD4
VLVD11
VLVD10
VLVD9
VLVD2
VLVD8
VLVD7
VLVD6
VLVD1
VLVD5
VLVD4
VLVD3
VLVD0
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
MIN.
TYP.
MAX.
Unit
1.60
1.63
1.66
V
1.74
1.77
1.81
V
1.70
1.73
1.77
V
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
1.84
1.88
1.91
V
(+0.2 V)
1.80
1.84
1.87
V
2.86
2.92
2.97
V
2.80
2.86
2.91
V
1.80
1.84
1.87
V
Falling interrupt voltage
Falling interrupt voltage
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
(+1.2 V)
Falling interrupt voltage
VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage: 1.8 V
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
(+0.1 V)
Falling interrupt voltage
1.94
1.98
2.02
V
1.90
1.94
1.98
V
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
2.05
2.09
2.13
V
(+0.2 V)
2.00
2.04
2.08
V
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
3.07
3.13
3.19
V
(+1.2 V)
3.00
3.06
3.12
V
2.40
2.45
2.50
V
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
2.56
2.61
2.66
V
(+0.1 V)
2.50
2.55
2.60
V
2.66
2.71
2.76
V
Falling interrupt voltage
Falling interrupt voltage
VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage: 2.4 V
Falling interrupt voltage
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
(+0.2 V)
Falling interrupt voltage
2.60
2.65
2.70
V
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
3.68
3.75
3.82
V
(+1.2 V)
3.60
3.67
3.74
V
2.70
2.75
2.81
V
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
2.86
2.92
2.97
V
(+0.1 V)
2.80
2.86
2.91
V
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
2.96
3.02
3.08
V
(+0.2 V)
2.90
2.96
3.02
V
3.98
4.06
4.14
V
3.90
3.98
4.06
V
Falling interrupt voltage
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage: 2.7 V
Falling interrupt voltage
Falling interrupt voltage
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
(+1.2 V)
Falling interrupt voltage
Page 102 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
Supply Voltage Rise Time (TA = −40 to +85°C, VSS = 0 V)
Parameter
Symbol
Maximum time to rise to
tPUP1
Conditions
MIN.
When RESET input is not used
TYP.
MAX.
Unit
3.2
ms
Note
1.6 V (VDD (MIN.))
(VDD: 0 V → 1.6 V)
Note
Make sure to raise the power supply in a shorter time than this.
Supply Voltage Rise Time Timing
• When RESET pin input is not used
Supply voltage
(VDD)
1.6 V
0V
Time
POR internal
signal
tPUP1
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 103 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +85°C)
Parameter
Data retention supply voltage
Symbol
Conditions
MIN.
VDDDR
1.47
TYP.
Note
MAX.
Unit
5.5
V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a
POR reset is effected, but data is not retained when a POR reset is effected.
Operation mode
STOP mode
Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.8 Flash Memory Programming Characteristics
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
CPU/peripheral hardware clock
Symbol
Conditions
MIN.
fCLK
1.8 V ≤ VDD ≤ 5.5 V
Cerwr
Retained for 20 years
TA = 85°C
Note 3
Retained for 1 years
TA = 25°C
Note 3
Retained for 5 years
TA = 85°C
Note 3
100,000
Retained for 20 years
TA = 85°C
Note 3
10,000
TYP.
1
MAX.
Unit
32
MHz
frequency
<R>
Number of code flash rewrites
Times
1,000
Notes 1, 2, 3
<R>
Number of data flash rewrites
Notes 1, 2, 3
<R>
Notes 1.
1,000,000
1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
<R>
2.
When using flash memory programmer and Renesas Electronics self programming library
3.
These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 104 of 124
RL78/G13
2. ELECTRICAL SPECIFICATIONS
2.9 Timing Specs for Switching Flash Memory Programming Modes
Parameter
Symbol
How long from when a pin reset
tSUINIT
Conditions
MIN.
POR and LVD reset must end before the pin
TYP.
MAX.
Unit
100
ms
reset ends.
ends until the initial communication
settings are specified
How long from when the TOOL0
tSU
POR and LVD reset must end before the pin
10
μs
1
ms
reset ends.
pin is placed at the low level until a
pin reset ends
How long the TOOL0 pin must be
kept at the low level after a reset
tHD
POR and LVD reset must end before the pin
reset ends.
ends
(except soft processing time)
<1>
<2>
<4>
<3>
RESET
tHD+
soft processing
time
00H reception
(TOOLRxD, TOOLTxD mode)
TOOL0
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin.
<2> The pins reset ends (POR and LVD reset must end before the pin reset ends.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete
the baud rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings
within 100 ms from when the resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until a pin reset ends (MIN. 10 μ s)
tHD:
How long to keep the TOOL0 pin at the low level from when the external and internal resets
end (except soft processing time)
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 105 of 124
RL78/G13
3 PACKAGE DRAWINGS
3. PACKAGE DRAWINGS
3.1 20-pin products
R5F1006AASP, R5F1006CASP, R5F1006DASP, R5F1006EASP
R5F1016AASP, R5F1016CASP, R5F1016DASP, R5F1016EASP
R5F1006ADSP, R5F1006CDSP, R5F1006DDSP, R5F1006EDSP
R5F1016ADSP, R5F1016CDSP, R5F1016DDSP, R5F1016EDSP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP20-0300-0.65
PLSP0020JC-A
S20MC-65-5A4-3
0.12
20
11
detail of lead end
F
G
T
P
L
U
E
1
10
A
H
J
I
S
N
S
K
C
D
M
M
B
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
6.65±0.15
B
0.475 MAX.
C
0.65 (T.P.)
D
0.24 +0.08
−0.07
E
0.1±0.05
F
1.3±0.1
G
1.2
H
8.1±0.2
I
6.1±0.2
J
1.0±0.2
K
0.17±0.03
L
0.5
M
0.13
N
0.10
P
3° +5°
−3°
T
0.25
U
0.6±0.15
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 106 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.2 24-pin products
R5F1007AANA, R5F1007CANA, R5F1007DANA, R5F1007EANA
R5F1017AANA, R5F1017CANA, R5F1017DANA, R5F1017EANA
R5F1007ADNA, R5F1007CDNA, R5F1007DDNA, R5F1007EDNA
R5F1017ADNA, R5F1017CDNA, R5F1017DDNA, R5F1017EDNA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-HWQFN24-4x4-0.50
PWQN0024KE-A
P24K8-50-CAB-1
0.04
D
DETAIL OF A PART
E
S
A
A
S
y
S
(UNIT:mm)
ITEM
D2
A
EXPOSED DIE PAD
1
6
D
4.00 ± 0.05
E
4.00 ± 0.05
A
0.75 ± 0.05
b
+
0.25 − 0.05
0.07
e
7
24
Lp
B
DIMENSIONS
0.50
0.40 ± 0.10
x
0.05
y
0.05
E2
ITEM
19
12
18
EXPOSED
DIE PAD
VARIATIONS
13
D2
E2
MIN NOM MAX MIN NOM MAX
A 2.45 2.50 2.55 2.45 2.50 2.55
e
Lp
b
x
M
S AB
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 107 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.3 25-pin products
R5F1008AALA, R5F1008CALA, R5F1008DALA, R5F1008EALA
R5F1018AALA, R5F1018CALA, R5F1018DALA, R5F1018EALA
R5F1008ADLA, R5F1008CDLA, R5F1008DDLA, R5F1008EDLA
R5F1018ADLA, R5F1018CDLA, R5F1018DDLA, R5F1018EDLA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-WFLGA25-3x3-0.50
PWLG0025KA-A
P25FC-50-2N2-2
0.01
21x b
w S A
S AB
M
A
ZD
D
x
e
ZE
5
4
B
3 2.27
E
2
C
1
E
w S B
INDEX MARK
y1
S
D
C
B
A
D
2.27
INDEX MARK
A
S
(UNIT:mm)
y
S
DETAIL OF C PART
DETAIL OF D PART
R0.17±0.05
0.43±0.05
R0.12±0.05 0.33±0.05
0.50±0.05
0.365±0.05
b
(LAND PAD)
0.34±0.05
(APERTURE OF
SOLDER RESIST)
0.365±0.05
ITEM
D
DIMENSIONS
3.00±0.10
E
3.00±0.10
w
0.20
e
0.50
A
0.69±0.07
b
0.24±0.05
x
0.05
y
0.08
y1
0.20
ZD
0.50
ZE
0.50
R0.165±0.05
0.50±0.05
0.33±0.05
R0.215±0.05
0.43±0.05
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 108 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.4 30-pin products
R5F100AAASP, R5F100ACASP, R5F100ADASP, R5F100AEASP, R5F100AFASP, R5F100AGASP
R5F101AAASP, R5F101ACASP, R5F101ADASP, R5F101AEASP, R5F101AFASP, R5F101AGASP
R5F100AADSP, R5F100ACDSP, R5F100ADDSP, R5F100AEDSP, R5F100AFDSP, R5F100AGDSP
R5F101AADSP, R5F101ACDSP, R5F101ADDSP, R5F101AEDSP, R5F101AFDSP, R5F101AGDSP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP30-0300-0.65
PLSP0030JB-B
S30MC-65-5A4-3
0.18
30
16
detail of lead end
F
G
T
P
1
L
15
U
E
A
H
I
J
S
C
D
N
M
S
B
M
K
ITEM
A
MILLIMETERS
9.85±0.15
B
0.45 MAX.
C
0.65 (T.P.)
NOTE
D
0.24 +0.08
−0.07
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
E
0.1±0.05
F
1.3±0.1
G
1.2
H
8.1±0.2
I
6.1±0.2
J
1.0±0.2
K
0.17±0.03
L
0.5
M
0.13
N
0.10
P
3° +5°
−3°
T
0.25
U
0.6±0.15
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 109 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.5 32-pin products
R5F100BAANA, R5F100BCANA, R5F100BDANA, R5F100BEANA, R5F100BFANA, R5F100BGANA
R5F101BAANA, R5F101BCANA, R5F101BDANA, R5F101BEANA, R5F101BFANA, R5F101BGANA
R5F100BADNA, R5F100BCDNA, R5F100BDDNA, R5F100BEDNA, R5F100BFDNA, R5F100BGDNA
R5F101BADNA, R5F101BCDNA, R5F101BDDNA, R5F101BEDNA, R5F101BFDNA, R5F101BGDNA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-HWQFN32-5x5-0.50
PWQN0032KB-A
P32K8-50-3B4-3
0.06
D
DETAIL OF A PART
E
S
A
A
S
y
S
(UNIT:mm)
ITEM
D2
A
EXPOSED DIE PAD
1
9
32
D
5.00 ± 0.05
E
5.00 ± 0.05
A
e
0.75 ± 0.05
+
0.25 − 0.05
0.07
0.50
Lp
0.40 ± 0.10
b
8
B
DIMENSIONS
x
0.05
y
0.05
E2
ITEM
25
16
17
24
Lp
EXPOSED
DIE PAD
VARIATIONS
D2
E2
MIN NOM MAX MIN NOM MAX
A 3.45 3.50 3.55 3.45 3.50 3.55
e
b
x
M
S AB
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 110 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.6 36-pin products
R5F100CAALA, R5F100CCALA, R5F100CDALA, R5F100CEALA, R5F100CFALA, R5F100CGALA
R5F101CAALA, R5F101CCALA, R5F101CDALA, R5F101CEALA, R5F101CFALA, R5F101CGALA
R5F100CADLA, R5F100CCDLA, R5F100CDDLA, R5F100CEDLA, R5F100CFDLA, R5F100CGDLA
R5F101CADLA, R5F101CCDLA, R5F101CDDLA, R5F101CEDLA, R5F101CFDLA, R5F101CGDLA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-WFLGA36-4x4-0.50
PWLG0036KA-A
P36FC-50-AA4-2
0.023
32x b
S AB
e
ZE
w S A
M
A
ZD
D
x
6
5
B
4
E
3
2.90
2
C
INDEX MARK
y1
D
w S B
S
1
F
E D C B A
E
2.90
A
S
y
S
DETAIL C
DETAIL E
DETAIL D
R0.17± 0.05
0.70 ±0.05
0.55 ±0.05 R0.12 ±0.05
0.75
0.55
(UNIT:mm)
R0.17 ±0.05
0.70 ±0.05
R0.12 ±0.05 0.55 ±0.05
0.75
0.55
φb
(LAND PAD)
φ 0.34±0.05
(APERTURE OF
SOLDER RESIST)
0.55
0.75
0.55±0.05
0.70± 0.05
0.55
0.75
0.55±0.05
R0.275±0.05
R0.35±0.05
ITEM
D
DIMENSIONS
E
4.00±0.10
w
0.20
4.00±0.10
e
0.50
A
0.69±0.07
b
0.24±0.05
x
0.05
y
0.08
y1
0.20
ZD
0.75
ZE
0.75
0.70±0.05
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 111 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.7 40-pin products
R5F100EAANA, R5F100ECANA, R5F100EDANA, R5F100EEANA, R5F100EFANA, R5F100EGANA, R5F100EHANA
R5F101EAANA, R5F101ECANA, R5F101EDANA, R5F101EEANA, R5F101EFANA, R5F101EGANA, R5F101EHANA
R5F100EADNA, R5F100ECDNA, R5F100EDDNA, R5F100EEDNA, R5F100EFDNA, R5F100EGDNA, R5F100EHDNA
R5F101EADNA, R5F101ECDNA, R5F101EDDNA, R5F101EEDNA, R5F101EFDNA, R5F101EGDNA, R5F101EHDNA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-HWQFN40-6x6-0.50
PWQN0040KC-A
P40K8-50-4B4-3
0.09
D
DETAIL OF A
PART
E
S
A
A
S
y
S
(UNIT:mm)
ITEM
D2
A
1
EXPOSED DIE PAD
10
D
6.00 ± 0.05
E
6.00 ± 0.05
A
e
0.75 ± 0.05
+
0.25 − 0.05
0.07
0.50
Lp
0.40 ± 0.10
b
11
40
B
DIMENSIONS
x
0.05
y
0.05
E2
31
20
21
30
Lp
e
b
x
M
ITEM
EXPOSED
DIE PAD
VARIATIONS
D2
E2
MIN NOM MAX MIN NOM MAX
A 4.45 4.50 4.55 4.45 4.50 4.55
S AB
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 112 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.8 44-pin products
R5F100FAAFP, R5F100FCAFP, R5F100FDAFP, R5F100FEAFP, R5F100FFAFP, R5F100FGAFP,
R5F100FHAFP, R5F100FJAFP, R5F100FKAFP, R5F100FLAFP
R5F101FAAFP, R5F101FCAFP, R5F101FDAFP, R5F101FEAFP, R5F101FFAFP, R5F101FGAFP,
R5F101FHAFP, R5F101FJAFP, R5F101FKAFP, R5F101FLAFP
R5F100FADFP, R5F100FCDFP, R5F100FDDFP, R5F100FEDFP, R5F100FFDFP, R5F100FGDFP,
R5F100FHDFP, R5F100FJDFP, R5F100FKDFP, R5F100FLDFP
R5F101FADFP, R5F101FCDFP, R5F101FDDFP, R5F101FEDFP, R5F101FFDFP, R5F101FGDFP,
R5F101FHDFP, R5F101FJDFP, R5F101FKDFP, R5F101FLDFP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP44-10x10-0.80
PLQP0044GC-A
P44GB-80-UES-2
0.36
HD
D
detail of lead end
A3
23
22
33
34
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
12
11
44
1
ZE
e
ZD
b
x
M
S
A
S
S
NOTE
Each lead centerline is located within 0.20 mm of
its true position at maximum material condition.
A1
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
A2
y
ITEM
D
0.25
b
0.37 +0.08
−0.07
c
0.145 +0.055
−0.045
L
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.80
x
0.20
y
0.10
ZD
1.00
ZE
1.00
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 113 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.9 48-pin products
R5F100GAAFB, R5F100GCAFB, R5F100GDAFB, R5F100GEAFB, R5F100GFAFB, R5F100GGAFB,
R5F100GHAFB, R5F100GJAFB, R5F100GKAFB, R5F100GLAFB
R5F101GAAFB, R5F101GCAFB, R5F101GDAFB, R5F101GEAFB, R5F101GFAFB, R5F101GGAFB,
R5F101GHAFB, R5F101GJAFB, R5F101GKAFB, R5F101GLAFB
R5F100GADFB, R5F100GCDFB, R5F100GDDFB, R5F100GEDFB, R5F100GFDFB, R5F100GGDFB,
R5F100GHDFB, R5F100GJDFB, R5F100GKDFB, R5F100GLDFB
R5F101GADFB, R5F101GCDFB, R5F101GDDFB, R5F101GEDFB, R5F101GFDFB, R5F101GGDFB,
R5F101GHDFB, R5F101GJDFB, R5F101GKDFB, R5F101GLDFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP48-7x7-0.50
PLQP0048KF-A
P48GA-50-8EU-1
0.16
HD
D
detail of lead end
36
25
37
A3
24
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
13
48
12
1
ZE
e
ZD
b
x
M
S
A
ITEM
D
DIMENSIONS
7.00±0.20
E
7.00±0.20
HD
9.00±0.20
HE
9.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
A2
c
L
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
A1
0.25
0.22±0.05
0.145 +0.055
−0.045
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
0.75
ZE
0.75
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 114 of 124
RL78/G13
3 PACKAGE DRAWINGS
R5F100GAANA, R5F100GCANA, R5F100GDANA, R5F100GEANA, R5F100GFANA, R5F100GGANA,
R5F100GHANA, R5F100GJANA, R5F100GKANA, R5F100GLANA
R5F101GAANA, R5F101GCANA, R5F101GDANA, R5F101GEANA, R5F101GFANA, R5F101GGANA,
R5F101GHANA, R5F101GJANA, R5F101GKANA, R5F101GLANA
R5F100GADNA, R5F100GCDNA, R5F100GDDNA, R5F100GEDNA, R5F100GFDNA, R5F100GGDNA,
R5F100GHDNA, R5F100GJDNA, R5F100GKDNA, R5F100GLDNA
R5F101GADNA, R5F101GCDNA, R5F101GDDNA, R5F101GEDNA, R5F101GFDNA, R5F101GGDNA,
R5F101GHDNA, R5F101GJDNA, R5F101GKDNA, R5F101GLDNA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-HWQFN48-7x7-0.50
PWQN0048KB-A
P48K8-50-5B4-4
0.13
D
DETAIL OF
E
S
A
PART
A
A
S
y
(UNIT:mm )
S
ITEM
D2
A
EXPOSED DIE PAD
1
12
D
7.00 ± 0.05
E
7.00 ± 0.05
A
0.75 ± 0.05
b
+
0.25 − 0.05
0.07
e
13
48
DIMENSIONS
Lp
0.50
0.40 ± 0.10
x
0.05
y
0.05
B
E2
ITEM
37
24
36
25
Lp
EXPOSED
DIE PAD
VARIATIONS
D2
E2
MIN NOM MAX MIN NOM MAX
A 5.45 5.50 5.55 5.45 5.50 5.55
e
b
x
M
S AB
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 115 of 124
RL78/G13
<R>
3 PACKAGE DRAWINGS
3.10 52-pin products
R5F100JCAFA, R5F100JDAFA, R5F100JEAFA, R5F100JFAFA, R5F100JGAFA, R5F100JHAFA, R5F100JJAFA,
R5F100JKAFA, R5F100JLAFA
R5F101JCAFA, R5F101JDAFA, R5F101JEAFA, R5F101JFAFA, R5F101JGAFA, R5F101JHAFA, R5F101JJAFA,
R5F101JKAFA, R5F101JLAFA
R5F100JCDFA, R5F100JDDFA, R5F100JEDFA, R5F100JFDFA, R5F100JGDFA, R5F100JHDFA, R5F100JJDFA,
R5F100JKDFA, R5F100JLDFA
R5F101JCDFA, R5F101JDDFA, R5F101JEDFA, R5F101JFDFA, R5F101JGDFA, R5F101JHDFA, R5F101JJDFA,
R5F101JKDFA, R5F101JLDFA
JEITA Package Code
RENESAS Code
P-LQFP52-10x10-0.65
PLQP0052JA-A
Previous Code
MASS (TYP.) [g]
P52GB-65-GBS-1
0.3
HD
D
2
27
39
40
detail of lead end
26
c
1
E
HE
L
52
14
1
13
e
(UNIT:mm)
3
b
x
M
A
A2
y
NOTE
A1
ITEM
D
E
10.00±0.10
10.00±0.10
HD
12.00±0.20
HE
12.00±0.20
A
1.70 MAX.
A1
0.10±0.05
A2
1.40
b
0.32±0.05
c
0.145±0.055
L
0.50±0.15
e
0.65
x
0.13
y
0.10
1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
DIMENSIONS
0° to 8°
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 116 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.11 64-pin products
R5F100LCAFA, R5F100LDAFA, R5F100LEAFA, R5F100LFAFA, R5F100LGAFA, R5F100LHAFA, R5F100LJAFA,
R5F100LKAFA, R5F100LLAFA
R5F101LCAFA, R5F101LDAFA, R5F101LEAFA, R5F101LFAFA, R5F101LGAFA, R5F101LHAFA, R5F101LJAFA,
R5F101LKAFA, R5F101LLAFA
R5F100LCDFA, R5F100LDDFA, R5F100LEDFA, R5F100LFDFA, R5F100LGDFA, R5F100LHDFA, R5F100LJDFA,
R5F100LKDFA, R5F100LLDFA
R5F101LCDFA, R5F101LDDFA, R5F101LEDFA, R5F101LFDFA, R5F101LGDFA, R5F101LHDFA, R5F101LJDFA,
R5F101LKDFA, R5F101LLDFA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP64-12x12-0.65
PLQP0064JA-A
P64GK-65-UET-2
0.51
HD
D
detail of lead end
48
33
49
32
A3
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
A2
S
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
DIMENSIONS
12.00±0.20
E
12.00±0.20
HD
14.00±0.20
HE
14.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
A
y
ITEM
D
A1
0.25
b
0.32 +0.08
−0.07
c
0.145 +0.055
−0.045
L
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.65
x
0.13
y
0.10
ZD
1.125
ZE
1.125
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 117 of 124
RL78/G13
3 PACKAGE DRAWINGS
R5F100LCAFB, R5F100LDAFB, R5F100LEAFB, R5F100LFAFB, R5F100LGAFB, R5F100LHAFB, R5F100LJAFB,
R5F100LKAFB, R5F100LLAFB
R5F101LCAFB, R5F101LDAFB, R5F101LEAFB, R5F101LFAFB, R5F101LGAFB, R5F101LHAFB,
R5F101LJAFB, R5F101LKAFB, R5F101LLAFB
R5F100LCDFB, R5F100LDDFB, R5F100LEDFB, R5F100LFDFB, R5F100LGDFB, R5F100LHDFB, R5F100LJDFB,
R5F100LKDFB, R5F100LLDFB
R5F101LCDFB, R5F101LDDFB, R5F101LEDFB, R5F101LFDFB, R5F101LGDFB, R5F101LHDFB,
R5F101LJDFB, R5F101LKDFB, R5F101LLDFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP64-10x10-0.50
PLQP0064KF-A
P64GB-50-UEU-2
0.35
HD
D
detail of lead end
48
33
49
A3
32
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
ITEM
D
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
A
A2
c
L
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
A1
0.25
0.22±0.05
0.145 +0.055
−0.045
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
1.25
ZE
1.25
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 118 of 124
RL78/G13
3 PACKAGE DRAWINGS
R5F100LCABG, R5F100LDABG, R5F100LEABG, R5F100LFABG, R5F100LGABG, R5F100LHABG,
R5F100LJABG
R5F101LCABG, R5F101LDABG, R5F101LEABG, R5F101LFABG, R5F101LGABG, R5F101LHABG,
R5F101LJABG
R5F100LCDBG, R5F100LDDBG, R5F100LEDBG, R5F100LFDBG, R5F100LGDBG, R5F100LHDBG,
R5F100LJDBG
R5F101LCDBG, R5F101LDDBG, R5F101LEDBG, R5F101LFDBG, R5F101LGDBG, R5F101LHDBG,
R5F101LJDBG
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-VFBGA64-4x4-0.40
PVBG0064LA-A
P64F1-40-AA2-2
0.03
w
D
S A
ZE
ZD
A
8
7
6
B
5
4
E
3
2
1
H G F E D C B A
INDEX MARK
w
S B
(UNIT:mm)
A
y1
A2
S
S
y
e
S
b
x
M
A1
S A B
INDEX MARK
ITEM
D
DIMENSIONS
E
4.00±0.10
w
0.15
4.00±0.10
A
0.89±0.10
A1
0.20± 0.05
A2
0.69
e
0.40
b
0.25 ± 0.05
x
0.05
y
0.08
y1
0.20
ZD
0.60
ZE
0.60
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 119 of 124
RL78/G13
<R>
3 PACKAGE DRAWINGS
3.12 80-pin products
R5F100MFAFA, R5F100MGAFA, R5F100MHAFA, R5F100MJAFA, R5F100MKAFA, R5F100MLAFA
R5F101MFAFA, R5F101MGAFA, R5F101MHAFA, R5F101MJAFA, R5F101MKAFA, R5F101MLAFA
R5F100MFDFA, R5F100MGDFA, R5F100MHDFA, R5F100MJDFA, R5F100MKDFA, R5F100MLDFA
R5F101MFDFA, R5F101MGDFA, R5F101MHDFA, R5F101MJDFA, R5F101MKDFA, R5F101MLDFA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP80-14x14-0.65
PLQP0080JB-E
P80GC-65-UBT-2
0.69
HD
detail of lead end
D
L1
A
A3
c
60
61
41
40
L
Lp
B
E
HE
Referance
Symbol
D
80
1
21
20
Dimension in Millimeters
Min
Nom
Max
13.80
14.00
14.20
E
13.80
14.00
14.20
HD
17.00
17.20
17.40
HE
17.00
17.20
17.40
A1
0.05
0.125
0.20
A2
1.35
1.40
1.45
bp
0.26
0.32
0.38
c
0.10
0.145
0.20
Lp
0.736
0.886
1.036
L1
1.40
1.60
1.80
0°
3°
A
ZE
e
ZD
1.70
A3
bp
x
M
S AB
L
A
A2
S
e
y
S
A1
0.25
0.80
8°
0.65
x
0.13
y
0.10
ZD
0.825
ZE
0.825
2012 Renesas ElectronicsCorporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 120 of 124
RL78/G13
3 PACKAGE DRAWINGS
R5F100MFAFB, R5F100MGAFB, R5F100MHAFB, R5F100MJAFB, R5F100MKAFB, R5F100MLAFB
R5F101MFAFB, R5F101MGAFB, R5F101MHAFB, R5F101MJAFB, R5F101MKAFB, R5F101MLAFB
R5F100MFDFB, R5F100MGDFB, R5F100MHDFB, R5F100MJDFB, R5F100MKDFB, R5F100MLDFB
R5F101MFDFB, R5F101MGDFB, R5F101MHDFB, R5F101MJDFB, R5F101MKDFB, R5F101MLDFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP80-12x12-0.50
PLQP0080KE-A
P80GK-50-8EU-2
0.53
HD
D
detail of lead end
41
60
61
A3
40
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
21
80
1
20
ZE
e
ZD
b
x
M
S
E
12.00±0.20
HD
14.00±0.20
HE
14.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
c
L
A2
S
S
DIMENSIONS
12.00±0.20
A3
b
A
y
ITEM
D
A1
0.25
0.22±0.05
0.145 +0.055
−0.045
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
1.25
ZE
1.25
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 121 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.13 100-pin products
R5F100PFAFB, R5F100PGAFB, R5F100PHAFB, R5F100PJAFB, R5F100PKAFB, R5F100PLAFB
R5F101PFAFB, R5F101PGAFB, R5F101PHAFB, R5F101PJAFB, R5F101PKAFB, R5F101PLAFB
R5F100PFDFB, R5F100PGDFB, R5F100PHDFB, R5F100PJDFB, R5F100PKDFB, R5F100PLDFB
R5F101PFDFB, R5F101PGDFB, R5F101PHDFB, R5F101PJDFB, R5F101PKDFB, R5F101PLDFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP100-14x14-0.50
PLQP0100KE-A
P100GC-50-GBR-1
0.69
HD
D
detail of lead end
A
L1
75
76
51
50
A3
c
B
L
E
HE
Lp
(UNIT:mm)
26
25
100
1
ITEM
D
DIMENSIONS
14.00±0.20
E
14.00±0.20
HD
16.00±0.20
HE
16.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40± 0.05
A3
ZE
e
b
ZD
x
M
S AB
A
A2
0.22 ±0.05
c
0.145 + 0.055
0.045
L
0.50
Lp
0.60±0.15
L1
e
1.00±0.20
3° + 5°
3°
0.50
x
0.08
y
0.08
ZD
1.00
ZE
1.00
S
y
S
A1
0.25
b
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 122 of 124
RL78/G13
3 PACKAGE DRAWINGS
R5F100PFAFA, R5F100PGAFA, R5F100PHAFA, R5F100PJAFA, R5F100PKAFA, R5F100PLAFA
R5F101PFAFA, R5F101PGAFA, R5F101PHAFA, R5F101PJAFA, R5F101PKAFA, R5F101PLAFA
R5F100PFDFA, R5F100PGDFA, R5F100PHDFA, R5F100PJDFA, R5F100PKDFA, R5F100PLDFA
R5F101PFDFA, R5F101PGDFA, R5F101PHDFA, R5F101PJDFA, R5F101PKDFA, R5F101PLDFA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP100-14x20-0.65
PLQP0100JC-A
P100GF-65-GBN-1
0.92
HD
D
detail of lead end
A
A3
51
50
80
81
c
B
E
HE
L
Lp
100
1
L1
31
30
(UNIT:mm)
ZE
e
ZD
b
x
M
S AB
A
A2
S
ITEM
D
DIMENSIONS
20.00 0.20
E
14.00 0.20
HD
22.00 0.20
HE
16.00 0.20
A
1.60 MAX.
A1
0.10 0.05
A2
1.40 0.05
A3
0.25
b
c
y
S
A1
L
+ 0.08
0.32 0.07
0.145 + 0.055
0.045
0.50
Lp
0.60 0.15
L1
e
1.00 0.20
3 +5
3
0.65
x
0.13
y
0.10
ZD
0.575
ZE
0.825
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 123 of 124
RL78/G13
3 PACKAGE DRAWINGS
3.14 128-pin products
R5F100SHAFB, R5F100SJAFB, R5F100SKAFB, R5F100SLAFB
R5F101SHAFB, R5F101SJAFB, R5F101SKAFB, R5F101SLAFB
R5F100SHDFB, R5F100SJDFB, R5F100SKDFB, R5F100SLDFB
R5F101SHDFB, R5F101SJDFB, R5F101SKDFB, R5F101SLDFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP128-14x20-0.50
PLQP0128KD-A
P128GF-50-GBP-1
0.92
HD
detail of lead end
D
A
A3
102
103
65
64
c
B
θ
E
L
HE
Lp
L1
128
1
39
38
(UNIT:mm)
ZE
e
ZD
b
x
M
S AB
A
A2
ITEM
D
DIMENSIONS
20.00±0.20
E
14.00±0.20
HD
22.00±0.20
HE
16.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
S
y
S
A1
0.25
b
0.22 ±0.05
c
0.145 +0.055
−0.045
L
0.50
Lp
0.60±0.15
L1
e
1.00±0.20
3° +5°
−3°
0.50
x
0.08
y
0.08
ZD
0.75
ZE
0.75
θ
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0200 Rev.2.00
Oct 12, 2012
Page 124 of 124
Revision History
RL78/G13 Data Sheet
Rev.
Date
Page
1.00
2.00
Feb 29, 2012
Oct 12, 2012
7
25
40, 42, 44
41, 43, 45
59, 63, 67
68
69
96 to 98
100
104
116
120
Description
Summary
First Edition issued
Figure 1-1. Part Number, Memory Size, and Package of RL78/G13: Pin count
corrected.
1.4 Pin Identification: Description of pins INTP0 to INTP11 corrected.
1.6 Outline of Functions: Descriptions of Subsystem clock, Low-speed on-chip
oscillator, and General-purpose register corrected.
1.6 Outline of Functions: Lists of Descriptions changed.
Descriptions of Note 8 in a table corrected.
(4) Common to RL78/G13 all products: Descriptions of Notes corrected.
2.4 AC Characteristics: Symbol of external system clock frequency corrected.
2.6.1 A/D converter characteristics: Notes of overall error corrected.
2.6.2 Temperature sensor characteristics: Parameter name corrected.
2.8 Flash Memory Programming Characteristics: Incorrect descriptions
corrected.
3.10 52-pin products: Package drawings of 52-pin products corrected.
3.12 80-pin products: Package drawings of 80-pin products corrected.
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
C-1
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2012 Renesas Electronics Corporation. All rights reserved.
Colophon 2.2
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