UPD78058F(A) Data Sheet

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On April 1

st

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas

Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

st

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

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DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD78058F(A)

8-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The

µ

PD78058F(A) is an 8-bit single-chip microcontroller belonging to the

µ

PD78058F Subseries of the 78K/0

Series. A stricter quality assurance program is applied to this device, which is classified as special grade, compared to the

µ

PD78058F, which is classified as standard grade.

The Electro Magnetic Interference (EMI) noise generated inside the

µ

PD78058F(A) is reduced compared to the

µ

PD78058 Subseries.

This microcontroller includes a rich assortment of peripheral hardware, such as 8-bit resolution A/D converter, 8bit resolution D/A converter, timer, serial interface, real-time output port, and interrupt functions.

The

µ

PD78P058F, a one-time PROM version which can be operated in the same supply voltage range as the mask

ROM version, and various development tools are also available.

Details of the function descriptions are described in the following user’s manuals. Be sure to read them before designing.

µ

PD78058F, 78058FY Subseries User's Manual : U12068E

78K/0 Series User’s Manual – Instructions : U12326E

FEATURES

• EMI noise reduced version (the overall peak level is reduced by 5 to 10 dB.)

• High-capacity on-chip ROM & RAM

ROM : 60 Kbytes

High-speed RAM: 1024 bytes

Buffer RAM : 32 bytes

Expanded RAM : 1024 bytes

• Package: 80-pin plastic QFP (14

×

14 mm)

• External memory expansion space: 64 Kbytes

• Minimum instruction execution time can be varied from high-speed (0.4

µ s) to ultra-low-speed (122

µ s)

• I/O ports: 69 (N-ch open-drain: 4)

• 8-bit resolution A/D converter: 8 channels

• 8-bit resolution D/A converter: 2 channels

• Serial interface: 3 channels

• Timer: 5 channels

• Supply voltage: V

DD

= 2.7 to 6.0 V

APPLICATIONS

Automobile equipment control units, gas detector/cutoff units, safety devices, etc.

The information in this document is subject to change without notice.

Document No U12325EJ2V0DS00 (2nd edition)

Date Published October 1997 N

Printed in Japan

The mark shows major revised points.

©

2

µ

PD78058F(A)

ORDERING INFORMATION

µ

Part Number

PD78058FGC(A)-

×××

-3B9

Package

80-pin plastic QFP (14

×

14 mm)

Quality Grade

Special

(for high-reliability electronic equipment)

Remark

×××

denotes the ROM code suffix.

Please refer to "Quality grade on NEC Semiconductor Devices" (Document number C11531E) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

Differences between the

µ

PD78058F(A) and

µ

PD78058F

Product name

Item

Quality grade

Package

µ

PD78058F(A)

Special

80-pin plastic QFP

(14

×

14 mm, resin thickness 2.7 mm)

µ

PD78058F

Standard

• 80-pin plastic QFP

(14

×

14 mm, resin thickness 2.7 mm)

• 80-pin plastic QFP

(14

×

14 mm, resin thickness 1.4 mm)

• 80-pin plastic TQFP (fine pitch) (12

×

12 mm)

µ

PD78058F(A)

78K/0 SERIES PRODUCT DEVELOPMENT

These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names.

78K/0

Series

Products in mass production

Products under development

Y subseries products are compatible with the I

2

C bus.

100-pin

100-pin

100-pin

100-pin

80-pin

80-pin

80-pin

64-pin

64-pin

64-pin

64-pin

64-pin

64-pin

64-pin

42/44-pin

Control

µ

PD78075B

µ

PD78078

µ

PD78070A

µ

µ

µ

µ

µ

µ

µ

PD780058

PD78058F

µ

PD78054

µ

PD780034

PD780024

PD78014H

PD78018F

µ

PD78014

µ

PD780001

PD78002

PD78083

64-pin

64-pin

64-pin

Inverter control

µ

PD780988

µ

PD780964

µ

PD780924

µ

PD78075BY

µ

PD78078Y

µ

PD78070AY

µ

PD780018AY

µ

PD780058Y

Note

µ

PD78058FY

µ

PD78054Y

µ

PD780034Y

µ

PD780024Y

µ

PD78018FY

µ

PD78014Y

µ

PD78002Y Basic subseries for control

On-chip UART, capable of operating at low voltage (1.8 V)

The inverter control, timer, and SIO were enhanced. ROM and RAM capacites were expanded.

On-chip inverter control circuit and UART. EMI noise was reduced

100-pin

100-pin

80-pin

80-pin

FIP

TM

drive

µ

PD780208

µ

PD780228

µ

PD78044H

µ

PD78044F

Basic subseries for driving FIP. Display output total: 34

100-pin

100-pin

100-pin

LCD drive

µ

PD780308

µ

PD78064B

µ

PD78064

80-pin

80-pin

IEBus

TM

supported

µ

PD78098B

µ

PD78098

µ

PD780308Y

µ

PD78064Y

Basic subseries for driving LCDs, On-chip UART

80-pin

Meter control

µ

PD780973

64-pin

LV

µ

PD78P0914

On-chip automobile meter driving controller/driver

On-chip PWM output, LV digital code decoder, and Hsync counter

Note Under planning

3

4

µ

PD78058F(A)

The major functional differences among the subseries are shown below.

Function

ROM

Capacity

Timer

8-bit 10-bit

A/D

8-bit

D/A

Serial Interface

Subseries Name

Control

8-bit 16-bit Watch WDT

A/D

µ

PD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch — 2 ch 3 ch (UART: 1 ch)

µ

PD78078 48 K to 60 K

µ

PD78070A —

µ

PD780058 24 K to 60 K 2 ch 3 ch (Time division

UART: 1 ch)

V

DD

External

I/O MIN.

Value

Expansion

88 1.8 V

61 2.7 V

68 1.8 V

µ

PD78058F 48 K to 60 K

µ

PD78054 16 K to 60 K

µ

PD780034 8 K to 32 K

µ

PD780024

µ

PD78014H

8 ch

8 ch

3 ch (UART: 1 ch) 69 2.7 V

2.0 V

3 ch (UART: 1 ch, Time 51 1.8 V division 3-wire: 1 ch)

2 ch

µ

PD78018F 8 K to 60 K

µ

PD78014 8 K to 32 K

µ

PD780001 8 K

µ

PD78002 8 K to 16 K

— —

1ch —

1 ch

µ

PD78083 — 8 ch 1 ch (UART: 1 ch)

Inverter

µ

PD780988 32 K to 60 K 3 ch Note 1 — 1 ch — 8 ch — 3 ch (UART: 2 ch) control µ

PD780964 8 K to 32 K

Note 2

2 ch (UART: 2 ch)

53

39

53

2.7 V

33 1.8 V

47 4.0 V

2.7 V

FIP driving

LCD driving

IEBus supported

Meter control

µ

PD780924 8 ch —

µ

PD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch — — 2 ch

µ

PD780228 48 K to 60 K 3 ch — —

µ

PD78044H 32 K to 48 K 2 ch 1 ch 1 ch

µ

PD78044F 16 K to 40 K

1 ch

2 ch

µ

PD780308 48 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch — — 3 ch (Time division

UART: 1 ch)

µ

PD78064B 32 K

µ

PD78064 16 K to 32 K

2 ch (UART: 1 ch)

µ

PD78098B 40 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch — 2 ch 3 ch (UART: 1 ch)

µ

PD78098 32 K to 60 K

µ

PD780973 24 K to 32 K 3 ch 1 ch 1 ch 1 ch 5 ch — — 2 ch (UART: 1 ch)

74 2.7 V

72 4.5 V

68 2.7 V

57 2.0 V

69 2.7 V

56 4.5 V

LV

µ

PD78P0914 32 K 6 ch — — 1 ch 8 ch — — 2 ch 54 4.5 V

Notes 1. 16-bit timer: 2 channels

10-bit timer: 1 channel

2. 10-bit timer: 1 channel

µ

PD78058F(A)

FUNCTIONAL OUTLINE

Internal memory

Item

ROM

High-speed RAM

Buffer RAM

60 Kbytes

1024 bytes

32 bytes

Function

A/D converter

D/A converter

Serial interface

Expanded RAM 1024 Kbytes

Memory space

General registers

Minimum instruction execution time On-chip minimum instruction execution time cycle modification function

When main system clock selected 0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0-MHz operation)

When subsystem clock selected 122

µ s (at 32.768-kHz operation)

Instruction set

64 Kbytes

8 bits

×

32 registers (8 bits

×

8 registers

×

4 banks)

• 16-bit operation

• Multiply/divide (8 bits

×

8 bits,16 bits

÷

8 bits)

• Bit manipulate (set, reset, test, Boolean operation)

• BCD adjust, etc.

I/O ports Total

• CMOS input

• CMOS I/O

• N-ch open-drain I/O

• 8-bit resolution

×

8 channels

• 8-bit resolution

×

2 channels

: 69

: 2

: 63

: 4

• 3-wire serial I/O, SBI, or 2-wire serial I/O mode selectable: 1 channel

• 3-wire serial I/O mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel

• 3-wire serial I/O or UART mode selectable: 1 channel

Timer

Timer output

Clock output

Buzzer output

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

3 (14-bit PWM output enable

×

1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,

5.0 MHz (during 5.0-MHz operation with main system clock)

32.768 kHz (during 32.768-kHz operation with subsystem clock)

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (during 5.0-MHz operation with main system clock)

Vectored interrupt source

Maskable

Non-maskable

Software

Test input

Supply voltage

Operating ambient temperature

Package

Internal interrupts: 13, external interrupts: 7

Internal interrupt: 1

1

Internal: 1, external: 1

V

DD

= 2.7 to 6.0 V

T

A

= –40 to + 85

°

C

80-pin plastic QFP (14

×

14 mm)

5

6

µ

PD78058F(A)

CONTENTS

1.

PIN CONFIGURATION (TOP VIEW) ................................................................................................ 7

2.

BLOCK DIAGRAM ............................................................................................................................. 9

3.

PIN FUNCTIONS .............................................................................................................................. 10

3.1

Port Pins ................................................................................................................................................... 10

3.2

Non-port Pins .......................................................................................................................................... 12

3.3

Pin I/O Circuits and Recommended Connection of Unused Pins ................................................... 14

4.

MEMORY SPACE ............................................................................................................................. 18

5.

PERIPHERAL HARDWARE FUNCTION FEATURES ................................................................... 19

5.1

Ports .......................................................................................................................................................... 19

5.2

Clock Generator ...................................................................................................................................... 20

5.3

Timer/event Counter ............................................................................................................................... 20

5.4

Clock Output Control Circuit................................................................................................................. 23

5.5

Buzzer Output Control Circuit .............................................................................................................. 23

5.6

A/D Converter .......................................................................................................................................... 24

5.7

D/A Converter .......................................................................................................................................... 25

5.8

Serial Interfaces ...................................................................................................................................... 25

5.9

Real-Time Output Port Functions ......................................................................................................... 27

6 INTERRUPT FUNCTIONS AND TEST FUNCTIONS ..................................................................... 28

6.1

Interrupt Functions ................................................................................................................................. 28

6.2

Test Functions ......................................................................................................................................... 32

7.

EXTERNAL DEVICE EXPANSION FUNCTIONS ........................................................................... 33

8.

STANDBY FUNCTION ..................................................................................................................... 33

9.

RESET FUNCTION ........................................................................................................................... 33

10. INSTRUCTION SET .......................................................................................................................... 34

11. ELECTRICAL SPECIFICATIONS .................................................................................................... 37

12. PACKAGE DRAWINGS ................................................................................................................... 63

13. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 64

APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 65

APPENDIX B. RELATED DOCUMENTS ............................................................................................... 68

µ

PD78058F(A)

1.

PIN CONFIGURATION (TOP VIEW)

• 80-pin plastic QFP (14

×

14 mm)

µ

PD78058FGC(A)-

×××

-3B9

P15/ANI5

P16/ANI6

P17/ANI7

AV

SS

P130/ANO0

P131/ANO1

AV

REF1

P70/SI2/RxD

P71/SO2/TxD

P72/SCK2/ASCK

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P25/SI0/SB0

P26/SO0/SB1

P27/SCK0

P40/AD0

P41/AD1

6

7

4

5

1

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

60

2

3

59

58

57

56

55

54

8

9

10

11

12

13

14

15

16

17

18

19

49

48

47

46

45

44

43

42

20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

41

53

52

51

50

RESET

P127/RTP7

P126/RTP6

P125/RTP5

P124/RTP4

P123/RTP3

P122/RTP2

P121/RTP1

P120/RTP0

P37

P36/BUZ

P35/PCL

P34/TI2

P33/TI1

P32/TO2

P31/TO1

P30/TO0

P67/ASTB

P66/WAIT

P65/WR

Cautions 1. Connect directly the Internally Connected (IC) pin to V

SS

.

2. The AV

DD

pin functions as both an A/D converter power supply and a port power supply. When the

µ

PD78058F(A) is used in applications where the noise generated inside the microcontroller need to be reduced, connect the AV

DD

pin to another power supply that has the same potential as V

DD

.

3. The AV

SS

m

When the

µ

PD78058F(A) is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AV

SS

pin to a ground line other than V

SS

.

7

8

A8 to A15

AD0 to AD7

ANI0 to ANI7

ANO0, ANO1

: Address Bus

: Address/Data Bus

: Analog Input

: Analog Output

ASCK

ASTB

: Asynchronous Serial Clock

: Address Strobe

AV

DD

: Analog Power Supply

AV

REF0

, AV

REF1

: Analog Reference Voltage

AV

SS

BUSY

BUZ

IC

: Analog Ground

: Busy

: Buzzer Clock

: Internally Connected

INTP0 to INTP6 : Interrupt from Peripherals

P00 to P07 : Port0

P10 to P17

P20 to P27

: Port1

: Port2

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P72

P120 to P127

P130, P131

: Port3

: Port4

: Port5

: Port6

: Port7

: Port12

: Port13

µ

PD78058F(A)

PCL

RD

: Programmable Clock

: Read Strobe

RESET : Reset

RTP0 to RTP7 : Real-Time Output Port

RxD

SB0, SB1

: Receive Data

: Serial Bus

SCK0 to SCK2 : Serial Clock

SI0 to SI2 : Serial Input

SO0 to SO2

STB

TI00, TI01

TI1, TI2,

TO0 to TO2

TxD

V

DD

V

SS

WAIT

WR

X1, X2

XT1, XT2

: Serial Output

: Strobe

: Timer Input

: Timer Input

: Timer Output

: Transmit Data

: Power Supply

: Ground

: Wait

: Write Strobe

: Crystal (Main System Clock)

: Crystal (Subsystem Clock)

µ

PD78058F(A)

2.

BLOCK DIAGRAM

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/

EVENT COUNTER 1

8-bit TIMER/

EVENT COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/RxD/P70

SO2/TxD/P71

SCK2/ASCK/P72

ANI0/P10 to

ANI7/P17

AV

REF0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

ANO0/P130,

ANO1/P131

AV

REF1

INTP0/P00 to

INTP6/P06

BUZ/P36

PCL/P35

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

60 Kbytes

RAM

2080 bytes

V

DD

V

SS

AV

DD

AV

SS

IC

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

P00

P01 to P06

T07

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P72

P120 to P127

P130, P131

RTP0/P120 to

RTP7/P127

AD0/P40 to

AD7/P47

A8/P50 to

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

9

µ

PD78058F(A)

3.

PIN FUNCTIONS

3.1

Port Pins (1/2)

Pin Name I/O

P00

P01

P02

P03

P04

P05

P06

P07

Note 1

P10 to P17

Input

Input/ output

Input

Input/ output

Function

After

Reset

Alternate

Function

Port 0

8-bit I/O port

Input only

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input INTP0/TI00

Input INTP1/TI01

INTP2

INTP3

INTP4

INTP5

INTP6

Input only

Input XT1

Port 1

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Note 2

Input ANI0 to ANI7

P24

P25

P26

P27

P20

P21

P22

P23

Input/ output

Port 2

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input SI1

SO1

SCK1

STB

BUSY

SI0/SB0

SO0/SB1

SCK0

Notes

1. When using the P07/XT1 pins as an input port, set 1 in bit 6 (FRC) of the processor clock control register

(PCC). The on-chip feedback resistor of the subsystem clock oscillator should not be used.

2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input pins, set port 1 to input mode.

The on-chip pull-up resistor is cancelled automatically.

Caution For pins that also function as port pins, do not perform the following operations during A/D conversion. If these operations are performed, the total error ratings cannot be kept.

(1) Rewrite the output latch of the output for pins used as a port pin.

(2) Change the output level of pins used as an output pin, even if they are not used as a port pin.

10

µ

PD78058F(A)

3.1

Port Pins (2/2)

Pin Name I/O

P30

P31

P32

P33

P34

P35

P36

P37

P40 to P47

Input/ output

Input/ output

P50 to P57

Input/ output

P130, P131 Input/ output

Function

After

Reset

Alternate

Function

Port 3

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input

Port 4

8-bit input/output port.

Input/output can be specified in 8-bit units.

When used as an input port, on-chip pull-up resistor can be used by software.

Test input flag (KRIF) is set to 1 by falling edge detection.

Input AD0 to AD7

Port 5

8-bit input/output port.

LED can be driven directly.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input A8 to A15

Input —

Port 6

8-bit input/outport port.

Input/output can be specified bit-wise.

N-ch open-drain input/output port.

On-chip pull-up resistor can be specified by mask option. LED can be driven directly.

TI2

PCL

BUZ

TO0

TO1

TO2

TI1

P60

P61

P62

P63

Input/ output

P64

P65

P66

P67

P70

P71

Input/ output

P72

P120 to P127 Input/ output

When used as an input port, on-chip pull-up resistor can be used by software.

Port 7

3-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Port 12

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Port 13

2-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input

Input

RD

WR

WAIT

ASTB

SI2/R

SO2/T

X

X

D

D

SCK2/ASCK

Input RTP0 to RTP7

Input ANO0, ANO1

Caution For pins that also function as port pins, do not perform the following operations during A/D conversion. If these operations are performed, the total error ratings cannot be kept.

(1) Rewrite the output latch of the output for pins used as a port pin.

(2) Change the output level of pins used as an output pin, even if they are not used as a port pin.

11

µ

PD78058F(A)

Pin Name I/O

SI1

SI2

SO0

SO1

SO2

SB0

SB1

SCK0

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTP6

SI0

SCK1

SCK2

STB

BUSY

R

X

D

T

X

D

ASCK

TI00

TI01

TI1

Input

Input

Output

Input/ output

Input/ output

TI2

TO0

TO1

TO2

Output

PCL

BUZ

Output

Output

RTP0 to RTP7 Output

AD0 to AD7

Input/ output

Output

Input

Input

Output

Input

Input

A8 to A15 Output

RD Output

WR

3.2

Non-port Pins (1/2)

Function

After

Reset

Alternate

Function

External interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edges) can be specified.

Serial interface serial data input.

Serial interface serial data output.

Serial interface serial data input/output.

Serial interface serial clock input/output.

Serial interface automatic transmit/receive strobe output.

Serial interface automatic transmit/receive busy input.

Asynchronous serial interface serial data input.

Asynchronous serial interface serial data output.

Asynchronous serial interface serial clock input.

External count clock input to the 16-bit timer (TM0)

Capture trigger signal input to the capture register (CR00)

External count clock input to the 8-bit timer (TM1)

Input

Input

P00/TI00

P01/TI01

P02

P03

P04

P05

P06

P25/SB0

Input

Input

P20

P70/R

X

D

P26/SB1

P21

P71/T

X

D

P25/SI0

P26/SO0

P27 Input

Input

Input

Input

Input

P22

P72/ASCK

P23

P24

P70/SI2

P71/SO2

Input P72/SCK2

Input P00/INTP0

P01/INTP1

P33

External count clock input to the 8-bit timer (TM2)

16-bit timer (TM0) output (dual-function as 14-bit PWM output)

8-bit timer (TM1) output

8-bit timer (TM2)

Input

P34

P30

P31

P32

Clock output (for main system clock, subsystem clock trimming).

Buzzer output.

Input

Input

P35

P36

Real-time output port by which data is output in synchronization with a trigger.

Input P120 to P127

Low-order address/data bus at external memory expansion.

Input P40 to P47

High-order address bus at external memory expansion.

External memory read operation strobe signal output.

External memory write operation strobe signal output.

Input P50 to P57

Input P64

P65

12

µ

PD78058F(A)

3.2

Non-port Pins (2/2)

Pin Name

WAIT

ASTB

I/O

Input

Output

ANI0 to ANI7 Input

ANO0, ANO1 Output

AV

REF0

AV

REF1

Input

Input

AV

DD

AV

SS

RESET

X1

X2

XT1

XT2

V

DD

V

SS

IC

Input

Input

Input

Function

After

Reset

Wait insertion at external memory access.

Strobe output which latches the address information output at port 4 to access external memory.

Input

Input

Alternate

Function

P66

P67

A/D converter analog input.

D/A converter analog output.

A/D converter reference voltage input.

D/A converter reference voltage input.

A/D converter analog power supply (shared with the port power supply)

A/D and D/A converter ground potential (shared with the port ground potential)

Input P10 to P17

Input P130, P131

System reset input.

Main system clock oscillation crystal connection.

Subsystem clock oscillation crystal connection.

Positive power supply (except for port).

Ground potential (except for port).

Internally connected. Connect to V

SS

directly.

Input

P07

Cautions 1. The AV

DD

pin functions as both an A/D converter power supply and a port power supply. When

the

µ

PD78058F(A) is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AV

DD

pin to another power supply that has the same potential as V

DD

.

2. The AV

SS

pin functions as both a ground potential of A/D and D/A converters and a ground potential of a port section. When the

µ

PD78058F(A) is used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AV

SS

pin to a ground line other than V

SS

.

13

µ

PD78058F(A)

3.3

Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and the recommended connection of unused pins are shown in Table 3-

1.

For the input/output circuit configuration of each type, see Figure 3-1.

Pin Name

P00/INTP0/TI00

P01/INTP1/TI01

P02/INTP2

P03/INTP3

P04/INTP4

P05/INTP5

P06/INTP6

P07/XT1

P10/ANI0 to P17/ANI7

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P25/SI0/SB0

P26/SO0/SB1

P27/SCK0

P30/TO0

P31/TO1

P32/TO2

P33/TI1

P34/TI2

P35/PCL

P36/BUZ

P37

P40/AD0 to P47/AD7

P50/A8 to P57/A15

P60 to P63

P64/RD

P65/WR

P66/WAIT

P67/ASTB

Table 3-1. Input/Output Circuit Type of Each Pin (1/2)

Input/output

Circuit Type

2

8-D

I/O

Input

Input/output

Recommended Connection when Not Used

Connect to V

SS

.

Independently connect to V

SS

via a resistor.

16

11-C

8-D

5-J

8-D

5-J

8-D

10-C

5-J

8-D

5-J

5-O

5-J

13-I

5-J

Input

Input/output

Connect to V

DD

.

Independently connect to V

DD

or V

SS

via a resistor.

Independently connect to V

DD

via a resistor.

Independently connect to V

DD

or V

SS

via a resistor.

Independently connect to V

DD

via a resistor.

Independently connect to V

DD

or V

SS

via a resistor.

14

Pin Name

P70/SI2/R

X

D

P71/SO2/T

X

D

P72/SCK2/ASCK

P120/RTP0 to

P127/RTP7

P130/ANO0,

P131/ANO1

RESET

XT2

AV

REF0

AV

REF1

AV

DD

AV

SS

IC

µ

PD78058F(A)

Table 3-1. Input/Output Circuit Type of Each Pin (2/2)

Input/output

Circuit Type

8-D

5-J

8-D

5-J

12-B

2

16

I/O

Input/output

Recommended Connection when Not Used

Independently connect to V

DD

or V

SS

via a resistor.

Input/output Independently connect to V

SS

via a resistor.

Input

Leave open.

Connect to V

SS

.

Connect to V

DD

.

Connect to another power supply that has the same potential as V

DD

.

Connect to another ground line that has the same potential as V

SS

.

Connect to V

SS directly.

15

16

µ

PD78058F(A)

Type 2

IN

Schmitt-Triggered Input with Hysteresis Characteristic

Type 5-J pull-up enable data output disable input enable

Type 5-O pull-up enable data output disable

Figure 3-1. Pin Input/Output Circuits (1/2)

AV

DD

Type 8-D pull-up enable data output disable

Type 10-C pull-up enable

AV

DD

P-ch

P-ch

IN/OUT

N-ch

AV

SS data open drain output disable

AV

DD

AV

DD

P-ch

P-ch

IN/OUT

N-ch

AV

SS

AV

DD

AV

DD

P-ch

P-ch

IN/OUT

N-ch

AV

SS

AV

DD

AV

DD

P-ch

P-ch

IN/OUT

N-ch

AV

SS

Type 11-C pull-up enable data

AV

DD

AV

DD

P-ch

P-ch

IN/OUT output disable

Comparator

+

-

P-ch

N-ch

AV

SS

V

REF

AV

SS

N-ch

(Threshold Voltage) input enable

Figure 3-1. Pin Input/Output Circuits (2/2)

Type 12-B

AV

DD pull-up enable

P-ch

AV

DD data

P-ch

IN/OUT output disable input enable

AV

SS

N-ch

Analog Output

Voltage

P-ch

N-ch

AV

SS

Type 13-I data output disable

Mask

Option

AV

DD

IN/OUT

N-ch

AV

SS

AV

DD

RD

P-ch

Type 16

XT1 feed back cut-off

P-ch

XT2

Medium Voltage Withstand Input Buffer

µ

PD78058F(A)

17

µ

PD78058F(A)

4.

MEMORY SPACE

Figure 4-1 shows the memory map of the

µ

PD78058F(A).

Figure 4-1. Memory Map

FFFFH

Special Function Registers

(SFR) 256

×

8 bits

FF00H

FEFFH

FEE0H

FEDFH

General Registers

32

×

8 bits

Data Memory

Space

Program

Memory

Space

Internal High-Speed

RAM

1024

×

8 bits

FB00H

FAFFH

Use Prohibited

FAE0H

FADFH

Internal Buffer RAM 32

×

8 bits

FAC0H

FABFH

Use Prohibited

F800H

F7FFH

Internal Expanded RAM

1024

×

8 bits

F400H

F3FFH

Use Prohibited

Note

F000H

EFFFH

Internal ROM

61440

×

8 bits

0000H

EFFFH

1000H

0FFFH

0800H

07FFH

0080H

007FH

0040H

003FH

Program Area

CALLF Entry Area

Program Area

CALLT Table Area

Vector Table Area

0000H

Note When the external device expansion function is used, set the internal ROM capacity to 56 Kbytes or less using the memory size switching register (IMS).

18

µ

PD78058F(A)

5.

PERIPHERAL HARDWARE FUNCTION FEATURES

5.1

Ports

The following 3 types of I/O ports are available.

• CMOS input (P00, P07)

• CMOS input/output (P01 to P06, ports 1 to 5, P64 to P67, port 7, port 12, port 13)

• N-channel open-drain input/output (P60 to P63)

Total

Table 5-1. Port Functions

Name

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 12

Port 13

Pin Name Function

P00, P07

P01 to P06

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P63

Dedicated input port pins

Input/output port pins. Input/output specifiable bit-wise.

When used as input/output port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable in 8-bit units.

When used as input port pins, on-chip pull-up resistor can be used by software.

Test input flag (KRIF) is set to 1 by falling edge detection.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

LED direct drive capability.

N-channel open-drain input/output port pins. Input/output specifiable bit-wise.

On-chip pull-up resistor can be used by mask option.

LED direct drive capability.

P64 to P67

P70 to P72

Input/output port pins. Input/output specifiable bit-wise.

When used as input/output port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input/output port pins, on-chip pull-up resistor can be used by software.

P120 to P127 Input/output port pins. Input/output specifiable bit-wise.

When used as input/output port pins, on-chip pull-up resistor can be used by software.

P130, P131 Input/output port pins. Input/output specifiable bit-wise.

When used as input/output port pins, on-chip pull-up resistor can be used by software.

: 2

: 63

: 4

: 69

19

µ

PD78058F(A)

5.2

Clock Generator

Two types of generators, a main system clock generator and a subsystem clock generator, are avaibable.

The minimum instruction execution time can also be changed.

• 0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (main system clock: at 5.0-MHz operation)

• 122

µ s (subsystem clock: at 32.768-kHz operation)

XT1/P07

XT2

X1

X2

Figure 5-1. Clock Generator Block Diagram

Subsystem

Clock

Oscillator f

XT

1

2

Main System

Clock

Oscillator f

X

STOP

Divider f

X

2

Selector f

XX f

XX

2

Prescaler f

XX

2

2 f

XX

2

3 f

XX f

XT

2

4

2

Selector

Prescaler

Standby

Control

Circuit

Circuit

To INTP0

Sampling Clock

Watch Timer, Clock

Output Function

Clock to Peripheral

Hardware

Wait Control

CPU Clock

(f

CPU

)

5.3

Timer/event Counter

The

µ

PD78058F(A) incorporates 5 channels of the timer/event counter.

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter

• Watch timer

• Watchdog timer

: 2 channel

: 1 channel

: 1 channel

Table 5-2. Operations of Timer/Event Counter

16-Bit Timer/Event Counter 8-Bit Timer/Event Counter Watch Timer Watchdog Timer

Operation mode

Interval timer

External event counter

Function

Timer

PWM output

Pulse width measurement

Square wave output

One-shot pulse output

Interrupt request

Test input

1 channel

1 channel

1 output

1 output

2 inputs

1 output

1 output

2

2 channels

2 channels

2 outputs

2 outputs

2

1 channel

1 channel

1

1 input

1

20

µ

PD78058F(A)

Figure 5-2. 16-Bit Timer/Event Counter Block Diagram

Internal Bus

TI01/P01/INTP1

Selector

16-Bit Capture/

Compare Register

(CR00)

Watch Timer

Output

2f

XX f

XX f

XX

/2 f

XX

/2

2

TI00/P00/INTP0

Match

PWM pulse

Output

Control

Circuit

Edge

Detection

Circuit

Selector

16-Bit Timer Register

(TM0)

Clear

Match

Selector

16-Bit Capture/

Compare Register

(CR01)

INTP1

INTTM00

Output Control

Circuit

TO0/P30

INTTM01

INTP0

Internal Bus

Figure 5-3. 8-Bit Timer/Event Counter Block Diagram

Internal Bus f xx

/2 to f xx

/2

9 f xx

/2

11

TI1/P33 f xx

/2 to f xx

/2

9 f xx

/2

11

TI2/P34

8-Bit Compare

Register (CR10)

Match

8-Bit Compare

Register (CR20)

Match

Selector

8-Bit Timer

Register 1 (TM1)

Clear

Selector

8-Bit Timer

Register 2 (TM2)

Clear

Selector

Selector

Internal Bus

INTTM1

Selector

Output

Control

Circuit

TO2/P32

INTTM2

Output

Control

Circuit

TO1/P31

21

µ

PD78058F(A)

f

XX

/2

7 f

XT

Selector f

W

Figure 5-4. Watch Timer Block Diagram

Prescaler

Selector

5-Bit Counter f

W

2

13 f

W

2

14

Selector INTWT f

W

2

4 f

W

2

5 f

W

2

6 f

W

2

7 f

W

2

8 f

W

2

9

Selector INTTM3

To 16-Bit Timer/

Event Counter

Figure 5-5. Watchdog Timer Block Diagram

f xx

2

3 f xx

2

4

Prescaler f xx

2

5 f xx

2

6 f xx

2

7 f xx

2

8 f xx

2

9 f xx

2

11

Selector 8-Bit Counter

INTWDT

Maskable

Interrupt Request

Control

Circuit

RESET

INTWDT

Non-Maskable

Interrupt Request

22

µ

PD78058F(A)

5.4

Clock Output Control Circuit

Clocks with the following frequencies can be output as the clock output.

• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (main system clock: at 5.0-

MHz operation)

• 32.768 kHz (subsystem clock: at 32.768-kHz operation)

Figure 5-6. Clock Output Control Circuit Configuration

f

XX f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XT

Selector

Synchronization

Circuit

Output Control

Circuit

PCL/P35

5.5

Buzzer Output Control Circuit

Clocks with the following frequencies can be output as the buzzer output.

• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (main system clock: at 5.0-MHz operation)

Figure 5-7. Buzzer Output Control Circuit Block Diagram

f

XX

/2

9 f

XX

/2

10 f

XX

/2

11

Selector

Output Control

Circuit

BUZ/P36

23

µ

PD78058F(A)

5.6

A/D Converter

An A/D converter of 8-bit resolution

×

8 channels is incorporated.

The following two types of the A/D conversion operation start-up methods are available.

• Hardware start

• Software start

Figure 5-8. A/D Converter Block Diagram

Series Resistor String

Sample & Hold Circuit

ANI0/P10

ANI1/P11

ANI2/P12

ANI3/P13

ANI4/P14

ANI5/P15

ANI6/P16

ANI7/P17

Selector

AV

SS

Voltage Comparator

Succesive Approximation

Register (SAR)

Tap

Selector

INTP3/P03

Edge

Detection

Circuit

Control

Circuit

A/D Conversion

Result Register (ADCR)

Internal Bus

AV

DD

AV

REF0

AV

SS

INTAD

INTP3

24

µ

PD78058F(A)

5.7

D/A Converter

A D/A converter of 8-bit resolution

×

2 channels is available.

Conversion method is R-2R resistor ladder method.

Figure 5-9. D/A Converter Block Diagram

AV

REF1

ANOn

Selector

AV

SS

DACSn

Write

INTTM

X

D/A Conversion Value Set Register n

(DACSn)

DAMm

D/A Converter

Mode Register

Internal Bus n = 0, 1 m = 4, 5 x = 1, 2

5.8

Serial Interfaces

3 channels of the clocked serial interface are incorporated.

• Serial interface channel 0

• Serial interface channel 1

• Serial interface channel 2

Table 5-3. Types and Functions of Serial Interface

Function

3-wire serial I/O mode

Serial Interface Channel 0 Serial Interface Channel 1 Serial Interface Channel 2

(MSB/LSB first switchable)

(MSB/LSB first switchable)

(MSB/LSB first switchable)

(MSB/LSB first switchable) — 3-wire serial I/O mode with automatic transmission/reception function

SBI (serial bus interface) mode

(MSB first)

2-wire serial I/O mode

(MSB first)

Asynchronous serial interface

(UART) mode

— —

(Dedicated baud rate generator incorporated)

25

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

µ

PD78058F(A)

Figure 5-10. Serial Interface Channel 0 Block Diagram

Internal Bus

Selector

Selector

Serial I/O Shift

Register 0 (SIO0)

Output

Latch

Bus Release/Command/

Acknowledge Detection

Circuit

Serial Clock Counter

Serial Clock

Control Circuit

Busy/Acknowledge

Output Circuit

Interrupt

Request

Signal

Generator

Selector

INTCSI0 f

XX

/2 to f

XX

/2

8

TO2

SI1/P20

SO1/P21

STB/P23

BUSY/P24

SCK1/P22

Figure 5-11. Serial Interface Channel 1 Block Diagram

Internal Bus

Automatic Data Transmit/

Receive Address Pointer

(ADTP)

Buffer RAM

Automatic Data

Transmit/Receive

Interval Specification

Register (ADTI)

Match

Handshake

Control

Circuit

Serial I/O Shift Register 1 (SIO1)

5-Bit Counter

Serial Counter

Serial Clock Control Circuit

Interrupt Request

Signal Generator

Selector

INTCSI1 f

XX

/2 to f

XX

/2

8

TO2

26

µ

PD78058F(A)

Figure 5-12. Serial Interface Channel 2 Block Diagram

Internal Bus

Receive Buffer Register

(RXB/SIO2)

Direction Control Circuit

Direction Control Circuit

Transmit Shift Register

(TXS/SIO2)

RxD/SI2/P70

TxD/SO2/P71

Receive Shift Register

(RXS)

Transmit Control Circuit

INTST

ASCK/SCK2/P72

Receive Control Circuit

INTSER

INTSR/INTCSI2

SCK Output

Control Circuit

Baud Rate

Generator f

XX

to f

XX

/2

10

5.9

Real-Time Output Port Functions

The real-time output function consists in transferring data set previously in the real-time output buffer register to the output latch by hardware concurrently with a timer interrupt request or external interrupt request generation in order to output to off-chip. Pins used to output to off-chip are called real-time output ports.

By using a real-time output port, a signal which has no jitter can be output. This is most applicable to control of stepping motors, etc.

Figure 5-13. Real-Time Output Port Block Diagram

Internal Bus

INTP2

INTTM1

INTTM2

Output Trigger

Control Circuit

Real-Time Output

Buffer Register

Higher 4 Bits

(RTBH)

Real-Time Output

Buffer Register

Higher 4 Bits

(RTBL)

Output Latch

P127

P120

Real-Time Output Port Mode

Register (RTPM)

27

µ

PD78058F(A)

6.

INTERRUPT FUNCTIONS AND TEST FUNCTIONS

6.1

Interrupt Functions

There are 22 interrupt functions of three different types, as shown below.

• Non-maskable : 1

• Maskable

• Software :

: 20

1

Table 6-1. Interrupt Source List (1/2)

Interrupt Type

Non-maskable

Maskable

7

8

9

10

4

5

6

1

2

3

Default

Priority

Note 1

0

11

12

Interrupt Source

Internal/

External

Name Trigger

INTWDT Watchdog timer overflow

(watchdog timer mode 1 selected)

INTWDT Watchdog timer overflow

(interval timer mode selected)

INTP0 Pin input edge detection

INTP1

INTP2

INTP3

INTP4

INTP5

Internal

External

INTP6

INTCSI0 End of serial interface channel 0 transfer Internal

INTCSI1 End of serial interface channel 1 transfer

INTSER Generation of serial interface channel 2 UART receive error

INTSR End of serial interface channel 2

UART reception

INTCSI2 End of serial interface channel 2

3-wire transfer

INTST End of serial interface channel 2

UART transmission

Vector

Table

Address

0004H

Basic

Configuration

Type

Note 2

(A)

0006H

0008H

000AH

000CH

000EH

0010H

0012H

0014H

0016H

0018H

001AH

001CH

(B)

(C)

(D)

(B)

Notes

1. The default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 18, the lowest.

2. Basic configuration types (A) to (E) correspond to (A) to (E) in Fig. 6-1, respectively.

28

µ

PD78058F(A)

Table 6-1. Interrupt Source List (2/2)

Interrupt Type

Maskable

Software

Default

Priority

Note 1

13

14

Interrupt Source

Name Trigger

INTTM3 Reference time interval signal from watch timer

INTTM00 Generation of match signal of 16-bit timer register and capture/compare register (CR00)

15

16

17

18

INTTM01 Generation of match signal of 16-bit timer register and capture/compare register (CR01)

INTTM1 Generation of match signal of 8-bit timer/event counter 1

INTTM2 Generation of match signal of 8-bit timer/event counter 2

INTAD End of conversion by A/D converter

BRK BRK instruction execution

Internal/

External

Internal

Vector

Table

Address

001EH

Basic

Configuration

Type

Note 2

(B)

0020H

0022H

0024H

0026H

0028H

003EH (E)

Notes

1. The default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 18, the lowest.

2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.

29

Figure 6-1. Interrupt Function Basic Configuration (1/2)

(A) Internal non-maskable interrupt

Interrupt

Request

Priority Control

Circuit

Internal Bus

Vector Table

Address

Generator

Standby Release

Signal

µ

PD78058F(A)

(B) Internal maskable interrupt

Interrupt

Request

IF

MK

Internal Bus

IE

PR ISP

Priority Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

(C) External maskable interrupt (INTP0)

Internal Bus

Interrupt

Request

Sampling Clock

Select Register

(SCS)

External Interrupt

Mode Register

(INTM0)

Sampling

Clock

Edge

Detection

Circuit

IF

MK IE PR ISP

Priority Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

30

µ

PD78058F(A)

Figure 6-1. Interrupt Function Basic Configuration(2/2)

(D) External maskable interrupt (except INTP0)

Interrupt

Request

External Interrupt

Mode Register

(INTM0)

Edge Detection

Circuit

IF

Internal Bus

MK IE PR ISP

Priority Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

(E) Software interrupt

Internal Bus

Interrupt

Request

IF : Interrupt request flag

IE : Interrupt enable flag

ISP : In-service priority flag

MK : Interrupt mask flag

PR : Priority specification flag

Priority Control

Circuit

Vector Table

Address

Generator

31

µ

PD78058F(A)

6.2

Test Functions

There are two sources of test function as shown in Table 6-2.

Table 6-2. Test Input Source List

Name

INTWT

INTPT4

Test Input Source

Trigger

Watch timer overflow

Port 4 falling edge detection

Figure 6-2. Test Function Basic Configuration

Internal/external

Internal

External

Internal Bus

MK

Standby Release

Signal

Test Input

IF : Test input flag

MK : Test mask flag

IF

32

µ

PD78058F(A)

7.

EXTERNAL DEVICE EXPANSION FUNCTIONS

The external device expansion functions connect external devices to areas other than the internal ROM, RAM and

SFR. Ports 4 to 6 are used for external device connection.

8.

STANDBY FUNCTION

There are the following two standby functions to reduce the system power consumption.

• HALT mode : The CPU operating clock is stopped.

The average consumption current can be reduced by intermittent operation in combination with the normal operating mode.

• STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock is stopped, so that the system operates with ultra-low power consumption using only the subsystem clock.

Figure 8-1. Stand-by Function

Main System

Clock Operation

Interrupt

Request

STOP

Instruction

Interrupt

Request

STOP Mode

(Main system clock oscillation stopped)

CSS=1

CSS=0

HALT

Instruction

HALT Mode

(Clock supply to CPU is stopped, oscillation)

Subsystem Clock

Operation

Note

HALT

Instruction

Interrupt

Request

HALT Mode

Note

(Clock supply to CPU is stopped, oscillation)

Note The power consumption is reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set bit 7 (MCC) in the processor clock control register (PCC) to stop the main system clock.

The STOP instruction cannot be used.

Caution When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program.

Remark CSS : Bit 4 in the PCC

9.

RESET FUNCTION

There are the following two reset methods.

External reset input by RESET pin

Internal reset by watchdog time runaway time detection

33

µ

PD78058F(A)

10. INSTRUCTION SET

(1) 8-bit instructions

MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,

ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ

Second

Operand

First

Operand

A

#byte

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

A r

Note

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP sfr

MOV

XCH saddr !addr16

PSW

MOV MOV

XCH XCH

ADD ADD

ADDC ADDC

SUB SUB

SUBC SUBC

AND AND

OR OR

XOR XOR

CMP CMP

[DE] [HL]

[HL + byte]

[HL + B]

$addr16

[HL + C]

MOV MOV MOV

XCH XCH

MOV

XCH

ADD ADD

ADDC ADDC

SUB SUB

SUBC SUBC

AND AND

OR OR

XOR XOR

CMP CMP

1

ROR

ROL

RORC

ROLC

None r MOV MOV

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

INC

DEC

B, C sfr saddr

MOV

MOV

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

!addr16

PSW

MOV

MOV

MOV

MOV

MOV

DBNZ

DBNZ INC

DEC

PUSH

POP

[DE]

[HL]

MOV

MOV ROR4

ROL4

[HL + byte]

[HL + B]

[HL + C]

X

C

MOV

MULU

DIVUW

Note Except r = A

34

µ

PD78058F(A)

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

Second instruction

First instruction

AX rp

#word

ADDW

SUBW

CMPW

MOVW

AX

MOVW

Note

sfrp saddrp

!addr16

SP

MOVW

MOVW

MOVW

MOVW

MOVW

MOVW

MOVW

Note Only when rp = BC, DE or HL rp

Note

MOVW

XCHW sfrp

MOVW saddrp

MOVW

!addr16

MOVW

(3) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

Second instruction

First instruction

A.bit

A.bit

sfr.bit

saddr.bit

PSW.bit

[HL].bit

CY

MOV1 sfr.bit

saddr.bit

PSW.bit

[HL].bit

CY

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

MOV1

MOV1

MOV1

SP

MOVW

None

INCW, DECW

PUSH, POP

$addr16

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

None

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

(4) Call instruction/branch instructions

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ

Second instruction

First instruction

Basic instruction

BR

AX

Compound instruction

!addr16

CALL

BR

!addr11

CALLF

[addr5]

CALLT

$addr16

BR, BC, BNC

BZ, BNZ

BT, BF

BTCLR

DBNZ

35

36

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

µ

PD78058F(A)

µ

PD78058F(A)

11. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (T

A

= 25

°

C)

Parameter

Supply voltage

Symbol

V

DD

AV

DD

AV

REF0

Test Conditions

Input voltage

High-level output current

V

I2

Output voltage V

O

Analog input voltage V

AN

I

OH

Low-level output current

I

AV

REF1

AV

SS

V

I1

P00 to P07, P10 to P17, P20 to P27, P30 to P37,

P40 to P47, P50 to P57, P64 to P67, P70 to P72,

P120 to P127, P130, P131, X1, X2, XT2, RESET

P60 to P63 N-ch Open-drain

OL

Note

P10 to P17

1 pin

P01 to P06, P30 to P37, P56, P57, P60 to P67, P120 to P127 total

P10 to P17, P20 to P27, P40 to P47, P50 to P55,

P70 to P72, P130, P131 total

1 pin

Analog input pin

Peak value

Effective value

P50 to P55 total

P56, P57, P60 to P63 total

P10 to P17, P20 to P27, P40 to P47,

P70 to P72, P130, P131 total

P01 to P06, P30 to P37, P64 to P67,

P120 to P127 total

Peak value

Effective value

Peak value

Effective value

Peak value

Effective value

Peak value

Effective value

Operating ambient T

A temperature

Storage temperature

T stg

Rating

–0.3 to +7.0

–0.3 to V

DD

+ 0.3

–0.3 to V

DD

+ 0.3

–0.3 to V

DD

+ 0.3

–0.3 to +0.3

–0.3 to V

–0.3 to +16 V

–0.3 to V

DD

+ 0.3

V

AV

SS

– 0.3 to AV

REF0

+ 0.3

V

–10

–15

–15 mA mA mA

30

15

DD

100

70

100

70

50

20

50

20

+ 0.3

–40 to +85

–65 to +150

Unit

V

V

V

V

V

V mA mA mA mA mA mA mA mA mA mA

°

C

°

C

Note Effective value should be calculated as follows: [Effective value] = [Peak value]

× √ duty

Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, alternate pin characteristics are the same as port pin characteristics.

37

µ

PD78058F(A)

Main System Clock Oscillation Circuit Characteristics (T

A

= –40 to 85

°

C, V

DD

= 2.7 to 6.0 V)

Resonator

Ceramic resonator

Crystal resonator

External clock

Recommended

Circuit

X2 X1 IC

Parameter

Oscillator frequency (f

X

)

Note 1

C2 C1

Oscillation stabilization time

Note 2

X2 X1 IC

Oscillator frequency (f

X

)

Note 1

C2 C1

Oscillation stabilization time

Note 2

X2 X1

X1 input frequency (f

X

)

Note 1

µ

PD74HCU04

X1 input high/low level width

(t

XH

, t

XL

)

Test Conditions MIN.

V

DD

= Oscillator voltage range

After V

DD

reaches oscillator voltage range MIN.

1.0

TYP.

MAX.

5.0

4

Unit

MHz ms

V

DD

= 4.5 to 6.0 V

1.0

1.0

85

5.0

MHz

10

30

5.0

ms

MHz

500 ns

Notes

1. Indicates only oscillation circuit characteristics. Refer to “AC CHARACTERISTICS” for instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release.

Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.

• Wiring should not be placed close to a varying high current.

• The potential of the oscillator capacitor ground should be the same as V

SS

.

• Do not ground wiring to a ground pattern in which a high current flows.

• Do not fetch a signal from the oscillator.

2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program.

38

µ

PD78058F(A)

Subsystem Clock Oscillation Circuit Characteristics (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

Resonator

Ceramic resonator

Recommended

Circuit

IC XT2 XT1

R1

C4 C3

Parameter

Oscillator frequency (f

XT

)

Note 1

Oscillation stabilization time

Note 2

External clock

XT2 XT1

XT1 input frequency (f

XT

)

Note 1

XT1 input high/low level width

(t

XTH

, t

XTL

)

Test Conditions

V

DD

= 4.5 to 6.0 V

MIN.

TYP.

MAX.

Unit

32 32.768

35

1.2

32 kHz

2

10 s

100 kHz

5 15

µ s

Notes

1. Indicates only oscillation circuit characteristics. Refer to “AC CHARACTERISTICS” for instruction execution time.

2. Time required to stabilize oscillation after V

DD

reaches MIN. oscillating voltage frequency.

Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.

• Wiring should not be placed close to a varying high current.

• The potential of the oscillator capacitor ground should be the same as V

SS

.

• Do not ground wiring to a ground pattern in which a high current flows.

• Do not fetch a signal from the oscillator.

2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to mulfunction due to noise than the main system clock oscillator.

Particular care is therefore required with the wiring method when the subsystem clock is used.

39

µ

PD78058F(A)

CAPACITANCE (T

A

= 25

°

C, V

DD

= V

SS

= 0 V)

Parameter

Input capacitance

Input/Output

Symbol

C

IN

C

IO

Test Conditions f = 1 MHz

Unmeasured pins returned to 0 V.

f = 1 MHz

Unmeasured pins returned to 0 V.

P01 to P06, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P50 to P57,

P64 to P67, P70 to P72,

P120 to P127,

P130, P131

P60 to P63

MIN.

TYP.

MAX.

15

15

20

Unit pF pF pF

Remark Unless otherwise specified, alternate pin characteristics are the same as port pin characteristics.

40

µ

PD78058F(A)

DC CHARACTERISTICS (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

Parameter

Input voltage, high

Input voltage, low

Output voltage, high

Output voltage, low

Input leakage current, high

Symbol

V

IH1

V

IH2

V

IH3

V

IH4

V

IH5

V

IL1

V

IL2

V

IL3

V

IL4

V

IL5

V

OH

V

OL1

V

OL2

V

OL3

I

LIH1

I

LIH2

I

LIH3

Test Conditions MIN.

P10 to P17, P21, P23, P30 to P32, P35 to P37,

P40 to P47, P50 to P57, P64 to P67, P71,

P120 to P127, P130, P131

0.7 V

DD

P00 to P06, P20, P22, P24 to P27, P33, P34, P70, P72, 0.8 V

DD

RESET

P60 to P63 (N-ch Open-drain)

X1, X2

XT1/P07, XT2 V

DD

= 4.5 to 6.0 V

V

0.7 V

DD

0.8 V

DD

– 0.5

DD

0.9 V

DD

P10 to P17, P21, P23, P30 to P32, P35 to P37,

P40 to P47, P50 to P57, P64 to P67, P71,

P120 to P127, P130, P131

P00 to P06, P20, P22, P24 to P27, P33, P34, P70, P72,

RESET

P60 to P63 V

DD

= 4.5 to 6.0 V

0

0

X1, X2

XT1/P07, XT2 V

DD

= 4.5 to 6.0 V

0

0

0

0

0

V

DD

– 1.0

V

DD

– 0.5

V

DD

= 4.5 to 6.0 V, I

OH

= –1 mA

I

OH

= –100

µ

A

P50 to P57, P60 to P63 V

DD

= 4.5 to 6.0 V,

I

OL

= 15 mA

P01 to P06, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P64 to P67,

P70 to P72, P120 to P127,

P130, P131

V

DD

= 4.5 to 6.0 V,

I

OL

= 1.6 mA

SB0, SB1, SCK0 V

DD

= 4.5 to 6.0 V,

N-ch open-drain at pull-up time (R = 1 K

)

I

OL

= 400

µ

A

V

IN

= V

DD

V

IN

= 15 V

P00 to P06, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P50 to P57,

P60 to P67, P70 to P72,

P120 to P127, P130,

P131, RESET

X1, X2, XT1/P07, XT2

P60 to P63

TYP.

MAX.

V

DD

0.4

V

DD

15

V

DD

V

DD

V

DD

0.3 V

0.2 V

0.3 V

0.2 V

0.4

2.0

0.4

0.2 V

0.5

3

20

80

DD

DD

DD

DD

0.2 V

DD

0.1 V

DD

DD

Remark Unless specified otherwise, alternate pin characteristics are the same as port pin characteristics.

Unit

V

V

V

V

V

V

µ

A

µ

A

µ

A

V

V

V

V

V

V

V

V

V

V

V

V

V

41

µ

PD78058F(A)

DC CHARACTERISTICS (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

Parameter

Input leakage current, low

Symbol

I

LIL1

V

IN

= 0 V

Test Conditions

P00 to P06, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P50 to P57,

P64 to P67, P70 to P72,

P120 to P127,

P130, P131, RESET

X1, X2, XT1/P07, XT2

P60 to P63

MIN.

TYP.

MAX.

–3

Unit

µ

A

I

LIL2

I

LIL3

Output leakage I

LOH current, high

Output leakage I

LOL current, low

Mask option pull-up resistor

R

1

Software pull-up R

2 resistor

V

OUT

= V

DD

V

OUT

= 0 V

V

IN

= 0 V, P60 to P63 20 40

–20

–3

Note

3

–3

90

µ

A

µ

A

µ

A

µ

A k

V

IN

= 0 V, P01 to P06,

P10 to P17, P20 to P27,

P30 to P37, P40 to P47,

P50 to P57, P64 to P67,

P70 to P72, P120 to P127,

P130, P131

V

DD

= 4.5 V to 6.0 V 15

20

40 90

500 k

Ω k

Note When the pull-up resistor is not included in P60 to P63 (specified by a mask option), the –200

µ

A (MAX.) lowlevel input leakage current is passed only at the 1.5 clock interval (no wait) when the read instruction to port

6 (PM6) and port mode register (PM6) is executed. At other than the 1.5 interval, –3

µ

A (MAX.) is passed.

Remark Unless specified otherwise, alternate pin characteristics are the same as port pin characteristics.

42

µ

PD78058F(A)

DC CHARACTERISTICS (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

Parameter

Power supply current

Note 1

I

I

I

I

I

Symbol

I

DD1

DD2

DD3

DD4

DD5

DD6

Test Conditions

5.0-MHz Crystal oscillation operating mode

(f

XX

= 2.5 MHz)

Note 2

V

V

DD

DD

= 5.0 V

= 3.0 V

±

±

10 %

10 %

Note 5

Note 6

5.0-MHz Crystal oscillation operating mode

(f

XX

= 5.0 MHz)

Note 3

5.0-MHz Crystal oscillation

HALT mode

(f

XX

= 2.5 MHz)

Note 2

V

V

V

V

DD

DD

DD

DD

= 5.0 V

= 3.0 V

= 5.0 V

= 3.0 V

±

±

±

±

10 %

10 %

10 %

10 %

5.0-MHz Crystal oscillation

HALT mode

(f

XX

= 5.0 MHz)

Note 3

V

V

DD

DD

= 5.0 V

= 3.0 V

±

±

10 %

10 %

32.768-kHz Crystal oscillation operating mode

Note 4

32.768-kHz Crystal oscillation

HALT mode

XT1 = V

DD

Note 4

STOP mode

When feedback resistor is used

V

DD

= 5.0 V

±

10 %

V

DD

= 3.0 V

±

10 %

V

DD

= 5.0 V

±

10 %

V

DD

= 3.0 V

±

10 %

V

DD

= 5.0 V

±

10 %

V

DD

= 3.0 V

±

10 %

XT1 = V

DD

STOP mode V

DD

= 5.0 V

±

10 %

When feedback resistor is not used V

DD

= 3.0 V

±

10 %

Note 5

Note 6

MIN.

TYP.

MAX.

4

0.6

6.5

0.8

1.4

0.5

1.6

0.65

60

32

25

5

1

0.5

0.1

0.05

12

1.8

19.5

2.4

4.2

1.5

4.8

1.95

120

64

55

15

30

10

30

10 mA mA mA mA mA mA

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

Unit mA mA

Notes

1. Passed through the V

DD

and AV

DD

pins. Does not include the current which is passed through the A/D converter, D/A converter, and on-chip pull-up resistor.

2. Main system clock f

XX

= f

X

/2 operation (when an oscillation mode selection register (OSMS) is set to 00H)

3. Main system clock f

XX

= f

X

operation (when the OSMS is set to 01H)

4. When the operation of the main system clock is stopped

5. High-speed mode operation (when a processor clock control register (PCC) is set to 00H)

6. Low-speed mode operation (when the PCC is set to 04H)

43

µ

PD78058F(A)

AC CHARACTERISTICS

(1) Basic Operation (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

Parameter

Cycle time

(Min. instruction execution time)

Symbol

T

CY

Test Conditions

Operating on main f

XX

= f

X

/2

Note 1

system clock f

XX

= f

X

Note 2

V

DD

= 4.5 to 6.0 V

Operating on subsystem clock

V

DD

= 4.5 to 6.0 V TI00 input high/ t

TIH00

, low-level width t

TIL00

TI01 input high/ t

TIH01

, low-level width t

TIL01

TI1, TI2 input frequency f

TI1

TI1, TI2 input high/low-level width t t

TIH1

TIL1

,

Interrupt request t

INTH

, input high/lowt

INTL level width

RESET low level width t

RSL

V

DD

= 4.5 to 6.0 V

V

DD

= 4.5 to 6.0 V

INTP0

INTP1 to INTP6, KR0 to KR7

MIN.

0.8

0.4

0.8

40

Note 3

2/f sam

+ 0.1

Note 4

2/f sam

+ 0.2

Note 4

10

TYP.

MAX.

Unit

122

64

32

32

125

µ s

µ s

µ s

µ s

µ s

µ s

µ s

0

0

100

1.8

V

DD

= 4.5 to 6.0 V 2/f sam

+ 0.1

Note 4

2/f sam

+ 0.2

Note 4

10

10

4 MHz

275 kHz ns

µ s

µ s

µ s

µ s

µ s

Notes

1. When the operation of the main system clock f

XX

= f

X

/2 (When oscillation mode selection register is set to 00H)

2. When the operation of the main system clock f

XX

= f

X

(When oscillation mode selection register is set to

01H)

3. Value when the external clock is used. 114

µ s (MIN.) when a crystal resonator is used.

4. Selection of f sam

is possible between f

XX

/2 N , f

XX

/32, f

XX

/64 and f

XX

/128 (when N = 0 to 4) using bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS).

44

µ

PD78058F(A)

T

CY

vs V

DD

(at f

XX

= f

X

/2 main system clock operation) T

CY

vs V

DD

(at f

XX

= f

X

main system clock operation)

60 60

10

Operation Guaranteed

Range

2.0

1.0

0.5

0.4

0

1 2 3 4 5

Supply Voltage V

DD

[V]

6

10

Operation Guaranteed

Range

2.0

1.0

0.5

0.4

0

1 2 3 4 5

Supply Voltage V

DD

[V]

6

45

µ

PD78058F(A)

(2) Read/Write Operation

(a) When MCS = 1, PCC2 to PCC0 = 000B (T

A

= –40 to +85

°

C, V

DD

= 4.5 to 6.0 V)

Parameter Symbol Test Conditions

ASTB high-level width

Address setup time

Address hold time

Data input time from address

Data input time from RD

Read data hold time

RD low-level width

WAIT

input time from RD

WAIT

input time from WR

WAIT low-level width

Write data setup time

Write data hold time t t t t

WRWT

WTL

WDS

WDH

WR low-level width

RD

delay time from ASTB

WR

delay time from ASTB

ASTB

delay time from

RD

in external fetch t t t t

WRL

ASTRD

ASTWR

RDAST

Address hold time from

RD

in external fetch

Write data output time from RD

Write data output time from WR

↓ t

RDWD

Address hold time from WR

↑ t

WRADH

RD

delay time from WAIT

↑ t

WTRD

WR

delay time from WAIT

↑ t t t

RDADH

RDWD

WTWR t

RDD2 t

RDH t

RDL1 t

RDL2 t

RDWT1 t

RDWT2 t

ASTH t

ADS t

ADH t

ADD1 t

ADD2 t

RDD1

MIN.

0.85t

CY

– 50

0.85t

CY

– 50

50

0

(2 + 2n)t

CY

– 60

(2.85 + 2n)t

CY

– 60

(1.15 + 2n)t

CY

(2.85 + 2n)t

CY

– 100

20

(2.85 + 2n)t

CY

– 60

25

0.85t

CY

+ 20

0.85t

CY

– 10

0.85t

CY

– 50

40

0

0.85t

CY

1.15t

CY

+ 40

1.15t

CY

+ 30

Remarks 1. MCS: Oscillation mode selection register bit 0

2. PCC2 to PCC0: Processor clock control register (PCC) bits 2 to 0

3. t

CY

= T

CY

/4

4. n indicates the number of waits.

MAX.

(2.85 + 2n)t

CY

– 80

(4 + 2n)t

CY

– 100

(2 + 2n)t

CY

– 100

(2.85 + 2n)t

CY

– 100

0.85t

CY

– 50

2t

CY

– 60

2t

CY

– 60

(2 + 2n)t

CY

1.15t

CY

+ 20

1.15t

CY

+ 50

50

1.15t

CY

+ 40

3.15t

CY

+ 40

3.15t

CY

+ 30 ns ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

46

µ

PD78058F(A)

(b) When except MCS = 1, PCC2 to PCC0 = 000B (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

MAX.

Parameter Symbol Test Conditions

ASTB high-level width

Address setup time

Address hold time

Data input time from address

Data input time from RD

Read data hold time

RD low-level width

WAIT

input time from RD

WAIT

input time from WR

WAIT low-level width

Write data setup time

Write data hold time t t

WDS

WDH

WR low-level width

RD

delay time from ASTB

WR

delay time from ASTB

ASTB

delay time from

RD

in external fetch t t t t

WRL

ASTRD

ASTWR

RDAST

Address hold time from

RD

in external fetch t

RDADH

Write data output time from RD

↑ t

RDWD

Write data output time from WR

↓ t

RDWD

Address hold time from WR

RD

delay time from WAIT

WR

delay time from WAIT

↑ t t t

WRADH

WTRD

WTWR t

RDD2 t

RDH t

RDL1 t

RDL2 t

RDWT1 t

RDWT2 t

WRWT t

WTL t

ASTH t

ADS t

ADH t

ADD1 t

ADD2 t

RDD1

MIN.

t

CY

– 80 t

CY

– 80

0.4t

CY

– 10

0

(1.4 + 2n)t

CY

– 20

(2.4 + 2n)t

CY

– 20

(1 + 2n)t

CY

(2.4 + 2n)t

CY

– 60

20

(2.4 + 2n)t

CY

– 60

0.4t

CY

– 30

1.4t

CY

– 30 t

CY

– 10 t

CY

– 50

0.4t

CY

– 20

0

t

CY

0.6t

CY

+ 180

0.6t

CY

+ 120

Remarks 1. MCS: Oscillation mode selection register (OSMS) bit 0

2. PCC2 to PCC0: Processor clock control register (PCC) bits 2 to 0

3. t

CY

= T

CY

/4

4. n indicates the number of waits.

(3 + 2n)t

CY

– 160

(4 + 2n)t

CY

– 200

(1.4 + 2n)t

CY

– 70

(2.4 + 2n)t

CY

– 70 t

CY

– 100

2t

CY

– 100

2t

CY

– 100

(2 + 2n)t

CY t

CY

+ 20 t

CY

+ 50

60 t

CY

+ 60

2.6t

CY

+ 180

2.6t

CY

+ 120

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

47

µ

PD78058F(A)

(3) Serial Interface (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

(a) Serial interface channel 0

(i) 3-wire serial I/O mode (SCK0... Internal clock output)

Parameter

SCK0 cycle time

Symbol t

KCY1

Test Conditions

V

DD

= 4.5 to 6.0 V

SCK0 high/low-level t

KH1

, t

KL1

V

DD

= 4.5 to 6.0 V width

V

DD

= 4.5 to 6.0 V SI0 setup time (to

SCK0

) t

SIK1

SI0 hold time (from t

KSI1

SCK0

)

SO0 output delay time from SCK0

↓ t

KSO1

C = 100 pF Note

Note C is the load capacitance of the SCK0 and SO0 output lines.

MIN.

800

1600 t

KCY1

/2 – 50 t

KCY1

/2 – 100

100

150

400

TYP.

(ii) 3-wire serial I/O mode (SCK0... Internal clock input)

MAX.

300

Unit ns ns ns ns ns ns ns ns

Parameter

SCK0 cycle time

Symbol t

KCY2

Test Conditions

V

DD

= 4.5 to 6.0 V

SCK0 high/low-level t

KH2

, t

KL2

V

DD

= 4.5 to 6.0 V width

SI0 setup time (to

SCK0

) t

SIK2

SI0 hold time (from t

KSI2

SCK0

)

SO0 output delay time from SCK0

↓ t

KSO2

SCK0 rise, fall time t

R2

, t

F2

C = 100 pF Note

When using external device expansion function

When not using external device expansion function

Note C is the load capacitance of the SO0 output line.

MIN.

800

1600

400

800

100

400

TYP.

MAX.

300

160

1000

Unit ns ns ns ns ns ns ns ns ns

48

µ

PD78058F(A)

(iii) SBI mode (SCK0... Internal clock output)

Parameter

SCK0 cycle time

Symbol t

KCY3

Test Conditions

V

DD

= 4.5 to 6.0 V

SCK0 high/low-level t

KH3

, t

KL3

V

DD

= 4.5 to 6.0 V width

V

DD

= 4.5 to 6.0 V SB0, SB1 setup time t

SIK3

(to SCK0

)

SB0, SB1 hold time t

KSI3

(from SCK0

)

SB0, SB1 output delay time from SCK0

↓ t

KSO3

SB0, SB1

from SCK0

↑ t

KSB

SCK0

from SB0, SB1

↓ t

SBK

SB0, SB1 high-level t

SBH width

SB0, SB1 low-level t

SBL width

R = 1 k

,

C = 100 pF

Note

V

DD

= 4.5 to 6.0 V

MIN.

800

3200 t

KCY3

/2 – 50 t

KCY3

/2 – 150

100

300 t

KCY3

/2

0

0 t

KCY3 t

KCY3 t

KCY3 t

KCY3

TYP.

MAX.

250

1000

Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns

49

µ

PD78058F(A)

(iv) SBI mode (SCK0... External clock input)

Parameter

SCK0 cycle time

Symbol t

KCY4

Test Conditions

V

DD

= 4.5 to 6.0 V

SCK0 high/low-level t

KH4

, t

KL4

V

DD

= 4.5 to 6.0 V width

V

DD

= 4.5 to 6.0 V SB0, SB1 setup time t

SIK4

(to SCK0

)

SB0, SB1 hold time t

KSI4

(from SCK0

)

SB0, SB1 output delay time from SCK0

↓ t

KSO4

SB0, SB1

from SCK0

↑ t

KSB

SCK0

from SB0, SB1

↓ t

SBK

SB0, SB1 high-level t

SBH width

SB0, SB1 low-level t

SBL width

SCK0 rise, fall time t

R4

, t

F4

R = 1 k

,

C = 100 pF

Note

V

DD

= 4.5 to 6.0 V

When using external device expansion function

When not using external device expansion function

MIN.

800

3200

400

1600

100

300 t

KCY4

/2

0

0 t

KCY4 t

KCY4 t

KCY4 t

KCY4

TYP.

Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.

MAX.

300

1000

160

1000 ns ns ns

Unit ns ns ns ns ns ns ns ns ns ns ns ns

50

µ

PD78058F(A)

(v) 2-wire serial I/O mode (SCK0... Internal clock output)

Parameter Symbol

SCK0 cycle time t

KCY5

SCK0 high-level width t

KH5

SCK0 low-level width t

KL5

SB0, SB1 setup time t

SIK5

(to SCK0

)

SB0, SB1 hold time t

KSI5

(from SCK0

)

SB0, SB1 output delay time from SCK0

↓ t

KSO5

Test Conditions

R = 1 k

,

C = 100 pF

Note

V

DD

= 4.5 to 6.0 V

V

DD

= 4.5 to 6.0 V

MIN.

800 t

KCY5

/2 – 160 t

KCY5

/2 – 50 t

KCY5

/2 – 150

300

350

600

0

TYP.

MAX.

300

Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.

Unit ns ns ns ns ns ns ns ns

(vi) 2-wire serial I/O mode (SCK0... External clock input)

Parameter Symbol

SCK0 cycle time t

KCY6

SCK0 high-level width t

KH6

SCK0 low-level width t

KL6

SB0, SB1 setup time t

SIK6

(to SCK0

)

SB0, SB1 hold time t

KSI6

(from SCK0

)

SB0, SB1 output delay time from SCK0

↓ t

KSO6

SCK0 rise, fall time t

R6

, t

F6

Test Conditions

R = 1 k

,

C = 100 pF

Note

V

DD

= 4.5 to 6.0 V

When using external device expansion function

When not using external device expansion function t

KCY6

/2

0

0

MIN.

1600

650

800

100

TYP.

Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.

MAX.

300

500

160

1000

Unit ns ns ns ns ns ns ns ns ns

51

µ

PD78058F(A)

(b) Serial interface channel 1

(i) 3-wire serial I/O mode (SCK1...Internal clock output)

Parameter

SCK1 cycle time

SCK1 high/low-level width

SI1 setup time (to SCK1

)

Symbol t

KCY7

Test Conditions

V

DD

= 4.5 to 6.0 V t

KH7

, t

KL7

V

DD

= 4.5 to 6.0 V t

SIK7

V

DD

= 4.5 to 6.0 V

SI1 hold time (from SCK1

) t

KSI7

SO1 output delay time from SCK1

↓ t

KSO7

C = 100 pF Note

Note C is the load capacitance of the SCK1 and SO1 output line.

MIN.

800

1600 t

KCY7

/2 – 50 t

KCY7

/2 – 100

100

150

400

TYP.

(ii) 3-wire serial I/O mode (SCK1...External clock output)

Parameter

SCK1 cycle time

Symbol t

KCY8

Test Conditions

V

DD

= 4.5 to 6.0 V

TYP.

SCK1 high/low-level width t

KH8

, t

KL8

V

DD

= 4.5 to 6.0 V

SI1 setup time (to SCK1

) t

SIK8

SI1 hold time (from SCK1

) t

KSI8

SO1 output delay time from SCK1

SCK1 rise, fall time t t

KSO8

R8

, t

F8

C = 100 pF Note

When using external device expansion function

When not using external device expansion function

Note C is the load capacitance of the SO1 output line.

MIN.

800

1600

400

800

100

400

MAX.

300

MAX.

300

160

1000

Unit ns ns ns ns ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns

52

µ

PD78058F(A)

(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... Internal clock output)

Parameter

SCK1 cycle time

SCK1 high/low-level width

SI1 setup time (to SCK1

)

Symbol t

KCY9

Test Conditions

V

DD

= 4.5 to 6.0 V t

KH9

, t

KL9

V

DD

= 4.5 to 6.0 V t

SIK9

V

DD

= 4.5 to 6.0 V

SI1 hold time (from SCK1

) t

KSI9

SO1 output delay time from t

KSO9

SCK1

STB

from SCK1

↑ t

SBD

Strobe signal high-level width t

SBW

Busy signal setup time (to busy signal detection timing) t

BYS

Busy signal hold time (from t

BYH busy signal detection timing)

SCK1

↓ from busy inactive t

SPS

C = 100 pF

Note

V

DD

= 4.5 to 6.0 V

Note C is the load capacitance of the SCK1 and SO1 output lines.

MIN.

800

1600 t

KCY9

/2 – 50 t

KCY9

/2 – 100

100

150

400 t

KCY9

/2 – 100 t

KCY9

/2 – 30

100

100

150

TYP.

MAX.

300 t

KCY9

/2 + 100 t

KCY9

/2 + 30

2t

KCY9

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns

(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... External clock output)

TYP.

MAX.

Parameter

SCK1 cycle time

Symbol t

KCY10

Test Conditions

V

DD

= 4.5 to 6.0 V

SCK1 high/low-level width t

KH10

, t

KL10

V

DD

= 4.5 to 6.0 V

SI1 setup time (to SCK1

) t

SIK10

SI1 hold time (from SCK1

) t

KSI10

SO1 output delay time from t

KSO10

SCK1

SCK1 rise, fall time t

R10

, t

F10

C = 100 pF Note

When using external device expansion function

When not using external device expansion function

Note C is the load capacitance of the SO1 output line.

MIN.

800

1600

400

800

100

400

300

160

1000

Unit ns ns ns ns ns ns ns ns ns

53

µ

PD78058F(A)

(c) Serial interface channel 2

(i) 3-wire serial I/O mode (SCK2...Internal clock output)

Parameter

SCK2 cycle time

SCK2 high/low-level width

SI2 setup time (to SCK2

)

Symbol t

KCY11

Test Conditions

V

DD

= 4.5 to 6.0 V t

KH11

, t

KL11

V

DD

= 4.5 to 6.0 V t

SIK11

V

DD

= 4.5 to 6.0 V

SI2 hold time (from SCK2

) t

KSI11

SO2 output delay time from SCK1

↓ t

KSO11

C = 100 pF Note

Note C is the load capacitance of the SCK2 and SO2 output lines.

MIN.

800

1600 t

KCY11

/2 – 50 t

KCY11

/2 – 100

100

150

400

TYP.

(ii) UART mode (Dedicated baud rate generator output)

Parameter

Transfer rate

Symbol Test Conditions

V

DD

= 4.5 to 6.0 V

MIN.

TYP.

MAX.

300

MAX.

78125

39063

(iii) UART mode (External clock input)

Parameter

ASCK cycle time

Symbol t

KCY12

Test Conditions

V

DD

= 4.5 to 6.0 V

MIN.

800

1600

400

800

TYP.

MAX.

ASCK high-/low-level width t

KH12

, t

KL12

V

DD

= 4.5 to 6.0 V

Transfer rate V

DD

= 4.5 to 6.0 V

ASCK rise, fall time t

R12

, t

F12

V

DD

= 4.5 to 6.0 V

When not using external device expansion function

39063

19531

1000

160

Unit ns ns ns ns ns ns ns ns

Unit bps bps

Unit ns ns ns ns bps bps ns ns

54

µ

PD78058F(A)

AC Timing Test Point (Excluding X1, XT1 Input)

0.8 V

DD

0.2 V

DD

Test Points

0.8 V

DD

0.2 V

DD

Clock Timing

t

XL

1/f

X t

XH

X1 Input

V

DD

– 0.5 V

0.4 V t

XTL

1/f

XT t

XTH

XT1 Input

V

IH5

(MIN.)

V

IL5

(MAX.)

TI Timing

t

TIL00

, t

TIL01 t

TIH00

, t

TIH01

TI00, TI01 t

TIL1

1/f

TI t

TIH1

TI1, TI2

55

Read/Write Operation

External Fetch (No Wait) :

A8 to A15

AD0 to AD7

Higher 8-Bit Address

Lower 8-Bit

Address t

ADS t

ASTH t

ADH t

ADD1

Hi-z

Operation

Code t

RDD1 t

RDADH t

RDAST

ASTB

RD t

ASTRD t

RDL1 t

RDH

External Fetch (Wait Insertion) :

A8 to A15

AD0 to AD7

Lower 8-Bit

Address t

ADS t

ASTH t

ADH

ASTB

Higher 8-Bit Address t

ADD1

Hi-z t

RDD1

Operation

Code t

RDADH t

RDAST

RD

WAIT t

RDWT1 t

ASTRD t

RDL1 t

WTL t

WTRD t

RDH

µ

PD78058F(A)

56

µ

PD78058F(A)

External Data Access (No Wait) :

A8 to A15

AD0 to AD7

Lower

8-Bit

Address t

ADS t

ASTH

ASTB t

ADH t

ADD2

Hi-z t

RDD2

Higher 8-Bit Address

Read Data t

RDH

Hi-z

Write Data

Hi-z

RD

WR t

ASTRD t

RDL2 t

RDWD t

WDWR t

WDS t

WRL t

WDH t

ASTWR t

WRADH

External Data Access (Wait Insertion) :

A8 to A15

AD0 to AD7

Lower

8-Bit

Address t

ADS t

ASTH

ASTB t

ADH t

ADD2

Hi-z t

RDD2 t

ASTRD

RD t

RDL2

Higher 8-Bit Address

Read Data t

RDH

Hi-z

WR t

ASTWR

Write Data t

RDWD t

WRWD t

WDS t

WRL t

WDH t

WRADH

Hi-z

WAIT t

RDWT2 t

WTRD t

WTL t

WRWT t

WTL t

WTWR

57

µ

PD78058F(A)

Serial Transfer Timing

3-wire Serial I/O Mode :

t

KLm t

Rn t

KCYm t

KHm t

Fn

SCK0 to SCK2

SI0 to SI2 t

KSOm

SO0 to SO2 m = 1, 2, 7, 8, 11 n = 2, 8

SBI Mode (Bus Release Signal Transfer) :

t

SIKm t

KSIm

Input Data

Output Data t

KL3,4 t

R4 t

KCY3,4 t

KH3,4 t

F4

SCK0 t

KSB t

SBL t

SBH t

SBK t

SIK3,4 t

KSI3, 4

SB0, SB1 t

KSO3,4

SBI Mode (Command Signal Transfer) :

t

KL3,4 t

R4 t

KCY3,4 t

KH3,4 t

F4

SCK0 t

KSB t

SBK t

SIK3,4 t

KSI3,4

SB0, SB1 t

KSO3,4

58

µ

PD78058F(A)

2-wire Serial I/O Mode :

SCK0

SB0, SB1 t

KSO5,6 t

KL5,6 t

R6 t

KCY5,6 t

KH5,6 t

F6 t

SIK5,6 t

KSI5,6

3-wire Serial I/O Mode with Automatic Transmit/Receive Function :

SO1

D2 D1 D0

SI1

D2 t

SIK9,10 t

KSO9, 10

SCK1

STB

D1 D0 t

KH9,10 t

KSI9,10 t

F10 t

KL9,10 t

KCY9,10 t

R10 t

SBD t

SBW

3-wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy processing) :

SCK1

7 8 9

Note

10

Note

t

BYS t

BYH

10+n

Note

t

SPS

BUSY

(Active high)

Note The signal is not actually driven low here; it is shown as such to indicate the timing.

1

D7

D7

59

µ

PD78058F(A)

UART Mode (External Clock Input) :

t

KL12 t

R12 t

KCY12 t

KH12 t

F12

ASCK

A/D Converter Characteristics (T

A

= –40 to +85

°

C, AV

DD

= V

DD

= 2.7 to 6.0 V, AV

SS

= V

SS

= 0 V)

Parameter

Resolution

Overall error

Note

Conversion time

Symbol t

CONV

Sampling time

Analog input voltage t

SAMP

V

IAN

Reference voltage AV

REF0

Resistance between AV

REF0 and AV

SS

R

AIREF0

Test Conditions

2.7 V

AV

REF0

AV

DD

MIN.

8

19.1

12/f

XX

AV

SS

2.7

4

TYP.

MAX.

8 8

±

0.6

200

14

AV

REF0

AV

DD

Note Overroll error excluding quantization error (

±

1/2 LSB). It is indicated as a ratio to the full-scale value.

Unit bit

%

µ s

µ s

V

V k

Caution For pins that also function as port pins (refer to 3.1 Port Pins), do not perform the following operations during A/D conversion. If these operations are performed, the total error ratings cannot be kept (except for LCD segment output alternate-function pin).

(1) Rewrite the output latch while the pin is used as a port pin.

(2) Change the output level of the pin used as an output pin, even if it is not used as a port pin.

Remarks 1. f

XX

: Main system clock frequency (f

X

or f

X

/2)

2. f

X

: Main system clock oscillation frequency

D/A Converter Characteristics (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V, AV

SS

= V

SS

= 0 V)

Parameter Symbol Test Conditions

Resolution

Overall error

Settling time

R

O

AV

REF1

R = 2 M

Note 1

R = 4 M

Note 1

R = 10 M

Note 1

C = 30 pF

Note 1

4.5 V

AV

REF1

6.0 V

2.7 V

AV

REF1

< 4.5 V

Note 2

Output resistance

Analog reference voltage

Resistance between AV

REF1 and AV

SS

R

AIREF1

DACS0, DACS1 = 55H

Note 2

MIN.

2.0

4

TYP.

MAX.

8

1.2

10

8

0.8

0.6

10

15

V

DD

Notes

1. R and C denote the D/A converter output pin load resistance and load capacitance, respectively.

2. Value for 1 D/A converter channel

Unit bit

%

%

%

µ s

µ s k

V k

Remark DACS0, DACS1: D/A conversion value setting register 0, 1

60

µ

PD78058F(A)

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T

A

= –40 to +85

°

C)

Parameter

Data retention power supply voltage

Data retention power supply current

Release signal set time

Oscillation stabilization wait time

Symbol

V

DDDR

I

DDDR

Test Conditions

V

DDDR

= 1.8 V

Subsystem clock stop and feed-back resister disconnected t

SREL t

WAIT

Release by RESET

Release by interrupt request

MIN.

1.8

0

TYP.

MAX.

6.0

0.1

10

2 17 /f

X

Note

Unit

V

µ

A

µ s ms ms

Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of

2 12 /f

XX

and 2 14 /f

XX

to 2 17 /f

XX

is possible.

Remark f

XX

: Main system clock frequency (f

X

or f

X

/2) f

X

: Main system clock oscillatior frequency

Data Retention Timing (STOP Mode Release by RESET)

Internal Reset Operation

HALT Mode

STOP Mode

Operating Mode

Data Retention Mode

V

DD V

DDDR t

SREL

STOP Instruction Execution

RESET t

WAIT

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)

HALT Mode

Operating Mode

STOP Mode

Data Retention Mode

V

DD

STOP Instruction Execution

Standby Release Signal

(Interrupt Request)

V

DDDR t

SREL t

WAIT

61

Interrupt Request Input Timing

INTP0 to INTP6

RESET Input Timing

t

INTL t

INTH t

RSL

RESET

µ

PD78058F(A)

62

µ

PD78058F(A)

12. PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14x14)

A

B

60

61

41

40

80

1

21

20

F

G

J

H I

M

P

K

M

N

L

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.

C D

S detail of lead end

Q

R

C

D

F

G

H

I

J

K

L

M

N

P

Q

R

S

ITEM MILLIMETERS

A 17.2±0.4

B 14.0±0.2

INCHES

0.677±0.016

14.0±0.2

17.2±0.4

0.825

0.825

0.30±0.10

0.13

0.65 (T.P.)

1.6±0.2

0.8±0.2

0.15

+0.10

–0.05

0.10

2.7±0.1

0.1±0.1

5

°

±5

°

3.0 MAX.

0.677±0.016

0.032

0.032

0.005

0.026 (T.P.)

0.063±0.008

0.006

0.004

+0.004

–0.003

0.004±0.004

5

°

±5

°

0.119 MAX.

S80GC-65-3B9-5

Remark Dimensions and materials of ES product are the same as those of mass-production products.

63

µ

PD78058F(A)

13. RECOMMENDED SOLDERING CONDITIONS

This product should be soldered and mounted under the conditions recommended in the table below.

For detail of recommended soldering conditions, refer to the information document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC sales representative.

Table 13-1. Surface Mounting Type Soldering Conditions

µ

PD78058FGC(A)-

×××

-3B9 : 80-pin Plastic QFP (14

×

14 mm)

Soldering

Method

Infrared reflow

Soldering Conditions

Package peak temperature: 235

°

C, Duration: 30 sec. max. (at 210

°

C or above),

Number of times: Three times max.

VPS Package peak temperature: 215

°

C, Duration: 40 sec. max. (at 200

°

C or above),

Number of times: Three times max.

Wave soldering Solder bath temperature : 260

°

C max., Duration : 10 sec. max., Number of times: once, Preheating temperature : 120

°

C max. (package surface temperature)

Partial heating Pin temperature: 300

°

C max. Duration: 3 sec. max. (per pin row)

Recommended

Condition Symbol

IR35-00-3

VP15-00-3

WS60-00-1

Caution Use of more than one soldering method should be avoided (except in the case of partial heating).

64

µ

PD78058F(A)

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the

µ

PD78058F(A).

Language Processing Software

RA78K/0

Notes 1, 2, 3, 4

CC78K/0

Notes 1, 2, 3, 4

DF78054

Notes 1, 2, 3, 4

CC78K/0-L

Notes 1, 2, 3, 4

Assembler package common to the 78K/0 Series

C compiler package common to the 78K/0 Series

Device file common to the

µ

PD78054 Subseries

C compiler library source file common to the 78K/0 Series

PROM Writing Tools

PG-1500 PROM programmer

PA-78P054GC Programmer adapters connected to PG-1500

PG-1500 controller

Notes 1, 2

PG-1500 control program

Notes

1. PC-9800 series based

2. IBM PC/AT TM and compatibles based

3. HP9000 series 700

TM

based, SPARCstation

TM based

4. NEWS TM based

Remark The RA78K/0 and CC78K/0 are used in combination with the DF78054.

65

µ

PD78058F(A)

Debugging Tools

(1) In-circuit Emulators (when IE-78K0-NS is used)

IE-78K0-NS

Note 5

IE-70000-MC-PS-B

IE-70000-98-IF-C

Note 5

In-circuit emulator common to 78K/0 Series

Power supply unit for IE-78K0-NS

Interface adapter when PC-9800 series (except for notebooks) is used as host machine.

IE-70000-CD-IF

Note 5

Interface adapter and cable when PC-9800 series notebook is used as host machine.

IE-70000-PC-IF-O

Note 5

Interface adapter when IBM PC/AT or compatibles is used as host machine.

IE-780308-NS-EM1

Note 5

Emulation board to emulate

µ

PD780308 Subseries

NP-80GC Emulation probe for 80-pin plastic QFP (GC-3B9 type)

EV-9200GC-64

ID78K0-NS

Notes 2, 3, 5

SM78K0

Notes 2, 3

DF78054

Notes 1, 2, 3, 4

Socket for mounting on target system board created for 80-pin plastic QFP (GC-3B9 type)

Integrated debugger for IE-78K0-NS

System simulator common to 78K/0 Series

Device file for

µ

PD78054 Subseries

(2) In-circuit Emulators (when IE-78001-R-A is used)

IE-78001-R-A

Note 5

IE-70000-98-IF-B

IE-70000-98-IF-C

Note 5

IE-70000-PC-IF-B

IE-70000-PC-IF-C

Note 5

In-circuit emulator common to 78K/0 Series

Interface adapter when PC-9800 series (except for notebooks) is used as host machine.

Interface adapter when IBM PC/AT or its compatibles is used as host machine.

IE-78000-R-SV3 Interface adapter and cable when EWS is used as host machine.

IE-780308-NS-EM1

Note 5

Emulation board common to

µ

PD780308 Subseries

IE-78K0-R-EX1

Note 5

Emulation probe conversion board that is necessary when using IE-780308-NS-EM1 on IE-78001-R-A

EP-78230GC-R

EV-9200GC-80

ID78K0

Notes 1, 2, 3, 4

SM78K0

Notes 2, 3

DF78054

Notes 1, 2, 3, 4

Emulation probe for 80-pin plastic QFP (GC-3B9 type)

Socket for mounting on target system board created for 80-pin plastic QFP (GC-3B9 type)

Integrated debugger for IE-78001-R-A

System simulator common to 78K/0 Series

Device file for

µ

PD78054 Subseries

Notes

1. HP9000 series 700 based, SPARCstation based

2. PC-9800 series based

3. IBM PC/AT and compatibles based

4. NEWS TM based

5. Under development

Remarks 1. The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF78054.

2. The NP-80GC is a product of Naito Densei Machida Seisakusho Co., Ltd. (044-822-3813). Contact an

NEC sales representative about purchasing.

66

µ

PD78058F(A)

Real-Time OS

RX78K/0

Notes 1, 2, 3, 4

MX78K/0

Notes 1, 2, 3, 4

Real-time OS for the 78K/0 Series

Real-time OS for the 78K/0 Series

Notes

1. PC-9800 series based

2. IBM PC/AT

TM

and its compatibles based

3. NEWS based

4. HP9000 series 700

TM

based, SPARCstation

TM

based

Remarks 1. For third party development tools, see the 78K/0 Series Selection Guide (U11126E).

2. The RX78K/0 is used in combination with the DF78054.

67

µ

PD78058F(A)

APPENDIX B. RELATED DOCUMENTS

Device Related Documents

Document Name

µ

PD78058F, 78058FY Subseries User’s Manual

µ

PD78058F(A) Data Sheet

µ

PD78P058F Data Sheet

78K/0 Series User’s Manual – Instructions

78K/0 Series Instruction Set

78K/0 Series Instruction Table

78K/0 Series Application Note Basics (III)

Document No.

(English)

U12068E

This document

U11796E

U12326E

U10182E

Document No.

(Japanese)

U12068J

U12325J

U11796J

U12326J

U10904J

U10903J

U10182J

Caution The above related documents are subject to change without notice. For design purposes, etc., be sure to use the latest documents.

68

µ

PD78058F(A)

Development Tool Related Documents (User’s Manual)

Document Name

RA78K Series Assembler Package

ID78K0-NS Integrated Debugger

ID78K0 Integrated Debugger, EWS based

ID78K0 Integrated Debugger, PC based

ID78K0 Integrated Debugger, Windows based

Operation

Language

RA78K Series Structured Assembler Preprocessor

RA78K0 Assembler Package

CC78K Series C Compiler

IE-78K0-NS

IE-78001-R-A

IE-780308-NS-EM1

EP-78230

SM78K0 System Simulator, Windows™ based

SM78K Series System Simulator

Operation

Assembly language

Structured assembly language

Operation

CC78K/0 C Compiler

CC78K/0 C Compiler Application Note

CC78K Series Library Source File

PG-1500 PROM Programmer

PG-1500 Controller PC-9800 Series (MS-DOS) based

PG-1500 Controller IBM PC series (PC DOS) based

Language

Operation

Language

Programming know-how

Reference

External parts user open interface specification

Reference

Reference

Guide

Document No.

(English)

EEU-1399

EEU-1404

EEU-1402

U11802E

U11801E

U11789E

EEU-1280

EEU-1284

U11517E

U11518E

EEA-1208

EEU-1335

EEU-1291

U10540E

Document No.

(Japanese)

EEU-809

EEU-815

U12323J

U11802J

U11801J

U11789J

EEU-656

EEU-655

U11517J

U11518J

EEA-618

U12322J

U11940J

EEU-704

EEU-5008

To be prepared To be prepared

To be prepared To be prepared

To be prepared To be prepared

EEU-1515 EEU-985

U10181E

U10092E

U10181J

U10092J

Under preparation To be prepared

U11539E

U11649E

U11151J

U11539J

U11649J

Caution The above related documents are subject to change without notice. For design purposes, etc., be sure to use the latest documents.

69

µ

PD78058F(A)

Embedded Software Documents (User’s Manual)

Document Name

78K/0 Series Real-time OS

78K/0 Series OS MX78K0

Basics

Installation

Basics

Document No.

(English)

U11537E

U11536E

U12257E

Document No.

(Japanese)

U11537J

U11536J

U12257J

Other Documents

Document Name

IC Package Manual

Semiconductor Device Mounting Technology Manual

Quality Grades on NEC Semiconductor Devices

NEC Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

Guide to Quality Assurance for Semiconductor Devices

Microcontroller Related Product Guide — Third Party

Document No.

(English)

C10943X

C10535E

C11531E

C10983E

C11892E

MEI-1202

Document No.

(Japanese)

C10535J

C11531J

C10983J

C11892J

C11893J

C11416J

Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents.

70

[MEMO]

µ

PD78058F(A)

71

72

µ

PD78058F(A)

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

µ

PD78058F(A)

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

Fax: 2886-9022/9044

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 01-30-67 58 99

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

Tel: 01-504-2787

Fax: 01-504-2860

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 253-8311

Fax: 250-3583

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

Fax: 02-719-5951

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil

Tel: 011-6465-6810

Fax: 011-6465-6829

J97. 8

73

µ

PD78058F(A)

FIP and IEBus are trademarks of NEC Corporation.

MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.

PC/AT, and PC DOS are trademarks of International Business Machines Corporation.

HP9000 series is a trademark of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

NEWS is a trademark of Sony Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M4 96.5

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