DS820

DS820
LogiCORE IP AXI EP Bridge for
PCI Express (v1.01.a)
DS820 October 19, 2011
Product Specification
Introduction
t
LogiCORE IP Facts Table
The Advanced eXtensible Interface (AXI) Endpoint
(EP) Bridge for PCI Express® is an interface between
the AXI4 bus and PCI Express. Definitions and
references are provided in this document for all of the
functional modules, registers, and interfaces that are
implemented in the AXI Bridge for PCI Express.
Definitions are also provided for the hardware
implementation and software interfaces to the AXI
Bridge for PCI Express in the Field Programmable Gate
Array (FPGA).
Features
Core Specifics
Supported
Device
Family (1)
Supported User
Interfaces
LUTs
FFs
DSP
Slices
Block
RAMs
Max. Freq.
Virtex-6 EP
64-bit
9300
6900
0
20
125 MHz
Spartan-6 EP
32-bit/
5600
4000
0
24
62.5 MHz
Provided with Core
•
Virtex-6 FPGA x1, x2, x4 Gen 1 and x1, x2 Gen 2
Design Files
•
Spartan-6 FPGA x1 Gen 1
Example Design
•
Maximum Payload Size (MPS) up to 256 Bytes
Test Bench
•
Messaged Signaled Interrupt (MSI)
Constraints File
•
Legacy interrupt supported
Simulation
Model
•
Memory mapped AXI4 access to PCIe® space
•
PCIe access to memory mapped AXI4 space
•
Tracks and manages Transaction Layer Packets
(TLP) completion processing
•
Optimal AXI4 pipeline support for enhanced
performance
Frequency
Configuration
Virtex®-6 and Spartan®-6 FPGA Integrated Blocks
for PCI Express
Detects and indicates error conditions with
interrupts
AXI4
Resources
•
•
Virtex-6, Spartan-6
Documentation
Product Specification
VHSIC Hardware Description Language (VHDL)
Available Online (3)
System Verilog
User Constraints File
Not Provided
Tested Design Tools
Design Entry
Tools
Xilinx® Platform Studio (XPS) 13.3
Simulation (2)
Mentor Graphics ModelSim
Synthesis Tools
(2)
Xilinx Synthesis Technology (XST)
Support
Provided by Xilinx, Inc. @www.xilinx.com/support
•
Compliant to Advanced RISC Machine (ARM®)
AMBA®4 AXI4 spec
•
Supports up to three PCIe 32-bit or 64-bit PCIe
Base Address Registers (BARs) as Endpoint
1. For a complete list of supported derivative devices, see IDS
Embedded Edition Derivative Device Support.
2. For the supported version of the tool, see the ISE Design Suite 13:
Release Notes Guide.
3. See Answer Record on www.xilinx.com.
© Copyright 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in
the United States and other countries. ARM and AMBA are registered trademarks of ARM in the EU and other countries. PCI, PCIe and PCI Express are trademarks
of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Product Specification
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Functional Description
The AXI PCIe Intellectual Property (IP) core provides the translation level between the AXI4 memory-mapped
embedded system to the PCI Express system. The AXI PCIe bridge translates the AXI4 memory read or writes to
PCIe Transaction Layer Packets (TLP) packets, and translates PCIe memory read and write request TLP packets to
AXI4 interface commands.
The architecture of the AXI Bridge for PCI Express is shown in Figure 1. The AXI Bridge for PCI Express contains
two sections: the memory-mapped AXI4 to AXI4-Stream Bridge and the AXI4-Stream Enhanced Interface Block for
PCIe. The memory-mapped AXI4 to AXI4-Stream Bridge contains a register block and two functional half bridges,
referred to here as the Slave Bridge and Master Bridge. The Slave Bridge connects to the AXI4 Interconnect as a slave
device to handle any issued AXI4 master read or write requests. The Master Bridge connects to the AXI4
Interconnect as a master to process the PCIe generated read or write TLPs.
The Register Block contains registers used in the AXI Bridge for PCI Express for dynamically mapping the AXI4
MM address range provided using AXIBAR parameters to an address for PCIe range.
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Figure 1: AXI Bridge for PCI Express Architecture
The Slave Bridge provides termination of memory-mapped AXI4 transactions from an AXI master device (such as
a processor). The Slave Bridge provides a way to translate addresses that are mapped within the AXI Memory
Mapped address domain to the domain addresses for PCIe. When a remote AXI master initiates a write transaction
to the Slave Bridge, the write address and qualifiers are captured and write data is queued in a First In First Out
(FIFO). These are then converted into one or more MemWr TLPs, depending on the configured Max Payload Size
setting, which are passed to the integrated block for PCI Express.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
A second remote AXI master initiated write request write address and qualifiers can then be captured and the
associated write data queued, pending the completion of the previous write TLP transfer to the integrated block for
PCI Express. The resulting AXI PCIe Slave Bridge write pipeline is two-deep.
When a remote AXI master initiates a read transaction to the Slave Bridge, the read address and qualifiers are
captured and a MemRd request TLP is passed to the integrated block for PCI Express and a completion timeout
timer is started. Completions received via the integrated block for PCI Express are correlated with pending read
requests and read data is returned to the AXI master. The Slave bridge is capable of handling up to eight memory
mapped AXI4 read requests with pending completions.
The Master Bridge processes both PCIe MemWr and MemRd request TLPs received from the integrated block for
PCI Express. It also provides a means to translate addresses that are mapped within the address for the PCIe
domain to the memory-mapped AXI4 address domain. Each PCIe MemWr request TLP header is used to create an
address and qualifiers for the memory-mapped AXI4 bus and the associated write data is passed to the addressed
memory mapped AXI4 Slave. The Master bridge is capable of supporting up to four active PCIe MemWr request
TLPs.
Each PCIe MemRd request TLP header is used to create an address and qualifiers for the memory-mapped AXI4
bus. Then read data that is collected from the addressed memory-mapped AXI4 Slave is used to generate
completion TLPs which are then passed to the integrated block for PCI Express. The Master bridge is capable of
handling up to four read requests with pending completions for improved AXI4 pipelining performance.
The instantiated AXI4-Stream Enhanced PCIe block contains submodules including the Requester/Completer
interfaces to the AXI bridge and the register block. The Register block contains the status, control and interrupt
registers, and the AXI4-Lite interface.
Bridge Parameters
Because many features in the AXI Bridge for PCI Express design can be parameterized, the user is able to uniquely
tailor the implementation of the AXI PCIe using only the resources required for the desired functionality. This
approach also achieves the best possible performance with the lowest resource usage.
The parameters defined for the AXI Bridge for PCI Express are shown in Table 1.
Table 1: Top Level Parameters
Generic
Parameter Name
Description
Allowable Values
Default Value VHDL Type
Bridge Parameters
G1
C_FAMILY
Target FPGA Family
virtex-6, spartan6
virtex6
String
G2
C_INCLUDE_RC
Configures the Bridge
to be a Root Complex
or an Endpoint
0 = Endpoint
1 = Root Complex
(supported in future release)
0
Integer
G3
C_COMP_TIMEOUT
Selects the Slave
Bridge completion
timeout counter value
0 = 50 uS
1 = 50 mS
0
Integer
G4
C_INCLUDE_
BAROFFSET_REG
0 = exclude
Include the registers
for high-order bits to be 1 = include
substituted in
translation in Slave
Bridge
0
Integer
G5
C_SUPPORTS_
NARROW_BURST
0 = not supported
Instantiates internal
logic to support narrow 1 = supported
burst transfers.
0
Integer
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 1: Top Level Parameters (Cont’d)
Generic
Parameter Name
Description
Allowable Values
G6
C_AXIBAR_NUM
Number of AXI
1- 6;
address apertures that 1 = BAR_0 enabled
can be accessed
2 = BAR_0, BAR_1 enabled
3 = BAR_0, BAR_1, BAR_2
enabled
4 = BAR_0 through BAR_3
enabled
5 = BAR_0 through BAR_4
enabled
6 = BAR_0 through BAR_5
enabled
G7
C_AXIBAR_0
AXI BAR_0 aperture
low address
G8
C_AXIBAR_
HIGHADDR_0
G9
C_AXIBAR_AS_0
G10
G11
C_AXIBAR_1
G12
Default Value VHDL Type
6
Integer
Valid AXI address(1)(3)(4)
0xFFFF_FFFF
std_logic_
vector
AXI BAR_0 aperture
high address
Valid AXI address(1)(3)(4)
0x0000_0000
std_logic_
vector
AXI BAR_0 address
size
0 = 32 bit
1 = 64 bit
0
Integer
C_AXIBAR2PCIEBAR PCIe BAR to which
Valid address for PCIe(2)
_0
AXI BAR_0 is mapped
0xFFFF_FFFF
std_logic_
vector
AXI BAR_1 aperture
low address
Valid AXI address(1)(3)(4)
0xFFFF_FFFF
std_logic_
vector
C_AXIBAR_
HIGHADDR_1
AXI BAR_1 aperture
high address
Valid AXI address(1)(3)(4)
0x0000_0000
std_logic_
vector
G13
C_AXIBAR_AS_1
AXI BAR_1 address
size
0 = 32 bit
1 = 64 bit
0
Integer
G14
C_AXIBAR2PCIEBAR PCIe BAR to which
Valid address for PCIe(2)
_1
AXI BAR_1 is mapped
0xFFFF_FFFF
std_logic_
vector
G15
C_AXIBAR_2
AXI BAR_2 aperture
low address
Valid AXI address(1)(3)(4)
0xFFFF_FFFF
std_logic_
vector
G16
C_AXIBAR_
HIGHADDR_2
AXI BAR_2 aperture
high address
Valid AXI address(1)(3)(4)
0x0000_0000
std_logic_
vector
G17
C_AXIBAR_AS_2
AXI BAR_2 address
size
0 = 32 bit
1 = 64 bit
0
Integer
G18
C_AXIBAR2PCIEBAR PCIe BAR to which
Valid address for PCIe(2)
_2
AXI BAR_2 is mapped
0xFFFF_FFFF
std_logic_
vector
G19
C_AXIBAR_3
AXI BAR_3 aperture
low address
Valid AXI address(1)(3)(4)
0xFFFF_FFFF
std_logic_
vector
G20
C_AXIBAR_
HIGHADDR_3
AXI BAR_3 aperture
high address
Valid AXI address(1)(3)(4)
0x0000_0000
std_logic_
vector
G21
C_AXIBAR_AS_3
AXI BAR_3 address
size
0 = 32 bit
1 = 64 bit
0
Integer
G22
C_AXIBAR2PCIEBAR PCIe BAR to which
Valid address for PCIe(2)
_3
AXI BAR_3 is mapped
0xFFFF_FFFF
std_logic_
vector
G23
C_AXIBAR_4
AXI BAR_4 aperture
low address
Valid AXI address(1)(3)(4)
0xFFFF_FFFF
std_logic_
vector
G24
C_AXIBAR_
HIGHADDR_4
AXI BAR_4 aperture
high address
Valid AXI address(1)(3)(4)
0x0000_0000
std_logic_
vector
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 1: Top Level Parameters (Cont’d)
Generic
Parameter Name
Description
Allowable Values
Default Value VHDL Type
G25
C_AXIBAR_AS_4
AXI BAR_4 address
size
0 = 32 bit
1 = 64 bit
0
Integer
G26
C_AXIBAR2PCIEBAR PCIe BAR to which
Valid address for PCIe(2)
_4
AXI BAR_4 is mapped
0xFFFF_FFFF
std_logic_
vector
G27
C_AXIBAR_5
AXI BAR_5 aperture
low address
Valid AXI address(1)(3)(4)
0xFFFF_FFFF
std_logic_
vector
G28
C_AXIBAR_
HIGHADDR_5
AXI BAR_5 aperture
high address
Valid AXI address(1)(3)(4)
0x0000_0000
std_logic_
vector
G29
C_AXIBAR_AS_5
AXI BAR_5 address
size
0 = 32 bit
1 = 64 bit
0
Integer
G30
C_AXIBAR2PCIEBAR PCIe BAR to which
Valid address for PCIe(2)
_5
AXI BAR_5 is mapped
0xFFFF_FFFF
std_logic_
vector
G31
C_PCIEBAR_NUM
Number of address for
PCIe apertures that
can be accessed
1- 3;
1 = BAR_0 enabled
2 = BAR_0, BAR_1 enabled
3 = BAR_0, BAR_1, BAR_2
enabled
3
Integer
G32
C_PCIEBAR_AS
Configures PCIEBAR
aperture width to be 32
bits wide or 64 bits
wide
1
0 = Generates three 32 bit
PCIEBAR address apertures.
32 bit BAR example:
PCIEBAR_0 is 32 bits
PCIEBAR_1 is 32 bits
PCIEBAR_2 is 32 bits
Integer
1 = Generates three 64 bit
PCIEBAR address apertures.
64 bit BAR example:
PCIEBAR_0 and
PCIEBAR_1 concatenate to
comprise 64 bit PCIEBAR_0.
PCIEBAR_2 and
PCIEBAR_3 concatenate to
comprise 64 bit PCIEBAR_1.
PCIEBAR_4 and
PCIEBAR_5 concatenate to
comprise 64 bit PCIEBAR_2
G33
C_PCIEBAR_LEN_0
G34
13-31
16
Integer
C_PCIEBAR2AXIBAR AXI BAR to which
_0
PCIE BAR_0 is
mapped
Valid AXI address
0x0000_0000
std_logic_
vector
G35
C_PCIEBAR_LEN_1
13-31
16
Integer
G36
C_PCIEBAR2AXIBAR AXI BAR to which
_1
PCIE BAR_1 is
mapped
Valid AXI address
0x0000_0000
std_logic_
vector
DS820 October 19, 2011
Product Specification
Power of 2 in the size
of bytes of PCIE
BAR_0 space
Power of 2 in the size
of bytes of PCIE
BAR_1 space
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 1: Top Level Parameters (Cont’d)
Generic
Parameter Name
Description
Allowable Values
Default Value VHDL Type
G37
C_PCIEBAR_LEN_2
Power of 2 in the size
of bytes of PCIE
BAR_2 space
13-31
16
Integer
G38
C_PCIEBAR2AXIBAR AXI BAR to which
_2
PCIE BAR_2 is
mapped
Valid AXI address
0x0000_0000
std_logic_
vector
AXI4-Lite Parameters
G39
C_BASEADDR
Device base address
Valid AXI address
0xFFFF_FFFF
std_logic_
vector
G40
C_HIGHADDR
Device high address
Valid AXI address
0x0000_0000
std_logic_
vector
Core for PCIe Configuration Parameters
G41
C_NO_OF_LANES
Number of PCIe Lanes 1 - Spartan-6
1, 2, 4 - Virtex-6
1
integer
G42
C_DEVICE_ID
Device ID
16-bit vector
0x0000
std_logic_
vector
G43
C_VENDOR_ID
Vendor ID
16-bit vector
0x0000
std_logic_
vector
G44
C_CLASS_CODE
Class Code
24-bit vector
0x00_0000
std_logic_
vector
G45
C_REV_ID
Rev ID
8-bit vector
0x00
std_logic_
vector
G46
C_SUBSYSTEM_ID
Subsystem ID
16-bit vector
0x0000
std_logic_
vector
G47
C_SUBSYSTEM_
VENDOR_ID
Subsystem Vendor ID
16-bit vector
0x0000
std_logic_
vector
G48
C_PCIE_CAP_SLOT_ PCIE Capabilities
IMPLEMENTED
Register Slot
Implemented
0 = Not add-in card slot
1 = Downstream port is
connected to add-in card
slot
(valid only for Root
Complex)
0
integer
G49
C_REF_CLK_FREQ
0
0 = 100 MHz
1 = 125 MHz - Spartan-6 only
2 = 250 MHz - Virtex-6 only
integer
REFCLK input
Frequency
Memory Mapped AXI4 Parameters
G50
C_M_AXI_DATA_
WIDTH
AXI Master Bus Data
width
32 - Spartan-6 only
64 - Virtex-6 only
64
integer
G51
C_M_AXI_ADDR_
WIDTH
AXI Master Bus
Address width
32
32
integer
G52
C_S_AXI_ID_WIDTH
AXI Slave Bus ID width 4
4
integer
G53
C_S_AXI_DATA_
WIDTH
AXI Slave Bus Data
width
32 - Spartan-6 only
64 - Virtex-6 only
64
integer
G54
C_S_AXI_ADDR_
WIDTH
AXI Slave Bus
Address width
32
32
integer
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 1: Top Level Parameters (Cont’d)
Generic
Parameter Name
Description
Allowable Values
Default Value VHDL Type
G55
C_MAX_LINK_
SPEED
Maximum PCIe link
speed supported
0 = 2.5 GT/s - Spartan-6,
Virtex-6
1 = 5.0 GT/s - Virtex-6
0
integer
G56
C_INTERRUPT_PIN
Legacy INTX pin
support/select
0 = no INTX support
1 = INTA selected
0
integer
AXI4 Interconnect Parameters
G57
C_INTERCONNECT_
S_AXI_WRITE_
ACCEPTANCE (5)
AXI Interconnect Slave 1 = Only one active AXI
Port Write Pipeline
AWADDR can be accepted in
Depth
AXI PCIe slave bridge,
2 = Maximum of two active
AXI AWADDR values can be
stored in AXI PCIe slave
bridge.
2
integer
G58
C_INTERCONNECT_
S_AXI_READ_
ACCEPTANCE (5)
8
AXI Interconnect Slave 1 = Only one active AXI
Port Read Pipeline
ARADDR can be accepted in
Depth
AXI PCIe slave bridge,
2, 4, 8 = Size of pipeline for
active AXI ARADDR values to
be stored in AXI PCIe slave
bridge.
integer
G59
C_INTERCONNECT_
M_AXI_WRITE_
ISSUING (5)
AXI Interconnect
Master Bridge write
address issue depth
1, 2, 4 = Number of actively
4
issued AXI AWADDR values
on the AXI Interconnect to the
target slave device(s).
integer
G60
C_INTERCONNECT_
M_AXI_READ_
ISSUING (5)
AXI Interconnect
Master Bridge read
address issue depth
1, 2, 4 = Number of actively
4
issued AXI ARADDR values
on the AXI Interconnect to the
target slave device(s).
integer
1.
2.
3.
4.
5.
This is a 32-bit address.
The width of this should match the address size (C_AXIBAR_AS) for this BAR.
The range specified must comprise a complete, contiguous power of two range, such that the range = 2n and the n least significant
bits of the Base Address are zero. The address value is a 32-bit AXI address.
The difference between C_AXIBAR_n and C_AXIBAR_HIGHADDR_n must be less than or equal to 0X1FFF_FFFF and greater
than or equal to 0X0001_FFFF.
It is not recommended to edit these default values on the AXI PCIe IP unless resource utilization needs to be reduced which will
impact the AXI bridge performance.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Parameter Dependencies
Table 2: Parameter Dependencies
Generic
Parameter
Affects
Depends
Description
Bridge Parameters
G1
C_FAMILY
G2
C_INCLUDE_RC
G3
C_COMP_TIMEOUT
G4
C_INCLUDE_BAROFFSET_REG G10,
G14,
G18,
G22,
G26, G30
G5
C_SUPPORTS_NARROW_
BURST
G6
C_AXIBAR_NUM
G7 - G30
G7
C_AXIBAR_0
G8
G8
G7 and G8 define the range in AXI
memory space that is responded to by
this device (AXI BAR)
G8
C_AXIBAR_HIGHADDR_0
G7
G7
G7 and G8 define the range in AXI
memory space that is responded to by
this device (AXI BAR)
G9
C_AXIBAR_AS_0
G10
C_AXIBAR2PCIBAR_0
G4
Meaningful if G4 = 1
G11
C_AXIBAR_1
G12
G12
G11 and G12 define the range in AXImemory space that is responded to by
this device (AXIBAR)
G12
C_AXIBAR_HIGHADDR_1
G11
G11
G11 and G12 define the range in AXImemory space that is responded to by
this device (AXIBAR)
G13
C_AXIBAR_AS_1
G14
C_AXIBAR2PCIBAR_1
G4
Meaningful if G4 = 1
G15
C_AXIBAR_2
G16
G16
G15 and G16 define the range in AXImemory space that is responded to by
this device (AXIBAR)
G16
C_AXIBAR_HIGHADDR_2
G15
G15
G15 and G16 define the range in AXImemory space that is responded to by
this device (AXIBAR)
G17
C_AXIBAR_AS_2
G18
C_AXIBAR2PCIBAR_2
G4
Meaningful if G4 = 1
G19
C_AXIBAR_3
G20
G19 and G20 define the range in AXImemory space that is responded to by
this device (AXIBAR)
DS820 October 19, 2011
Product Specification
G2
G20
G1
Meaningful only if G1 = Virtex-6
G6
If G4 = 1 then G10, G14, G18, G22, G26
and G30 have no meaning. The number
of registers included is set by G6.
If G6 = 1, then G7 - G10 are enabled
If G6 = 2, then G7 - G14 are enabled
If G6 = 3, then G7 - G18 are enabled
If G6 = 4, then G7 - G22 are enabled
If G6 = 5, then G7 - G26 are enabled
If G6 = 6, then G7 - G30 are enabled
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 2: Parameter Dependencies
Generic
Parameter
Affects
Depends
Description
G20
C_AXIBAR_HIGHADDR_3
G19
G19
G19 and G20 define the range in AXImemory space that is responded to by
this device (AXIBAR)
G21
C_AXIBAR_AS_3
G22
C_AXIBAR2PCIBAR_3
G4
Meaningful if G4 = 1
G23
C_AXIBAR_4
G24
G24
G23 and G24 define the range in AXImemory space that is responded to by
this device (AXIBAR)
G24
C_AXIBAR_HIGHADDR_4
G23
G23
G23 and G24 define the range in AXImemory space that is responded to by
this device (AXIBAR)
G25
C_AXIBAR_AS_4
G26
C_AXIBAR2PCIBAR_4
G4
Meaningful if G4 = 1
G27
C_AXIBAR_5
G28
G28
G27 and G28 define the range in AXImemory space that is responded to by
this device (AXIBAR)
G28
C_AXIBAR_HIGHADDR_5
G27
G27
G27 and G28 define the range in AXImemory space that is responded to by
this device (AXIBAR)
G29
C_AXIBAR_AS_5
G30
C_AXIBAR2PCIBAR_5
G4
Meaningful if G4 = 1
G31
C_PCIBAR_NUM
G32
C_PCIBAR_AS
G33
C_PCIBAR_LEN_0
G34
C_PCIBAR2AXIBAR_0
G35
C_PCIBAR_LEN_1
G36
C_PCIBAR2AXIBAR_1
G37
C_PCIBAR_LEN_2
G38
C_PCIBAR2AXIBAR_2
G33-G88
If G31 = 1, then G32, G33 are enabled
If G31 = 2, then G32 - G36 are enabled
If G31 = 3, then G32 - G38 are enabled
G34
G33
Only the high-order bits above the length
defined by G33 are meaningful.
G35
Only the high-order bits above the length
defined by G35 are meaningful.
G37
Only the high-order bits above the length
defined by G37 are meaningful.
G36
G38
AXI4-Lite Parameters
G39
C_BASEADDR
G40
C_HIGHADDR
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 2: Parameter Dependencies
Generic
Parameter
Affects
Depends
Description
Core for PCIe Configuration Parameters
G41
C_NO_OF_LANES
G1
If G1 = Spartan-6 then
G41 = 1 only
if G1 = Virtex-6 then
G41 = 1, 2 or 4.
Note: Spartan-6 is a fixed x1 lane
Endpoint
G42
C_DEVICE_ID
G43
C_VENDOR_ID
G44
C_CLASS_CODE
G45
C_REV_ID
G46
C_SUBSYSTEM_ID
G47
C_SUBSYSTEM_VENDOR_ID
G48
C_PCIE_CAP_SLOT_
IMPLEMENTED
G2
if G2 = 0 G48 is not meaningful
G49
C_REF_CLK_FREQ
G1
if G1 = Spartan-6, G49 must be = 0 or 1
if G1 = Virtex-6, G49 must be = 0 or 2
Memory Mapped AXI4 Bus Parameters
G50
C_M_AXI_DATA_WIDTH
G53
G53
G50 must be equal to G53
G51
C_M_AXI_ADDR_WIDTH
G54
G54
G51 must be equal to G54
G52
C_S_AXI_ID_WIDTH
G53
C_S_AXI_DATA_WIDTH
G50
G50
G53 must be equal to G50
G54
C_S_AXI_ADDR_WIDTH
G51
G51
G54 must be equal to G51
G55
C_MAX_LINK_SPEED
G1
if G1 = Spartan-6, G55 must be = 0
G56
C_INTERRUPT_PIN
Top-level Interface Signals
The interface signals for the AXI Bridge for PCI Express are described in Table 3.
Table 3: Top Level Interface Signals
Signal Name
I/O
Description
Global Signals
AXI_ACLK
I
Global clock signal for AXI Interfaces
AXI_ARESETN
I
Global reset signal for AXI Interfaces
AXI_ACLK_OUT
O
PCIe derived clock output for AXI_ACLK
AXI_CTL_ACLK
I
Global clock signal for AXI CTL Interface
AXI_CTL_ACLK_OUT
O
PCIe derived clock output for AXI_CTL_ACLK
MMCM_LOCK
O
AXI_ACLK_OUT from axi_enhanced_core for PCIe is stable
INTERRUPT_OUT
O
Interrupt signal
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 3: Top Level Interface Signals (Cont’d)
Signal Name
I/O
Description
AXI Slave Interface
S_AXI_AWID[C_S_AXI_ID_WIDTH-1:0]
I
Slave write address ID
S_AXI_AWADDR[C_S_AXI_ADDR_WIDTH-1:0]
I
Slave write address
S_AXI_AWREGION[3:0]
I
Slave write region decode
S_AXI_AWLEN[7:0]
I
Slave write burst length
S_AXI_AWSIZE[2:0]
I
Slave write burst size
S_AXI_AWBURST[1:0]
I
Slave write burst type
S_AXI_AWVALID
I
Slave write address valid
S_AXI_AWREADY
O
Slave write address ready
S_AXI_WDATA[C_S_AXI_DATA_WIDTH-1:0]
I
Slave write data
S_AXI_WSTRB[C_S_AXI_DATA_WIDTH/8-1:0]
I
Slave write strobe
S_AXI_WLAST
I
Slave write last
S_AXI_WVALID
I
Slave write valid
S_AXI_WREADY
O
Slave write ready
S_AXI_BID[C_S_AXI_ID_WIDTH-1:0]
O
Slave response ID
S_AXI_BRESP[1:0]
O
Slave write response
S_AXI_BVALID
O
Slave write response valid
S_AXI_BREADY
I
Slave response ready
S_AXI_ARID[C_S_AXI_ID_WIDTH-1:0]
I
Slave read address ID
S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH-1:0]
I
Slave read address
S_AXI_ARREGION[3:0]
I
Slave read region decode
S_AXI_ARLEN[7:0]
I
Slave read burst length
S_AXI_ARSIZE[2:0]
I
Slave read burst size
S_AXI_ARBURST[1:0]
I
Slave read burst type
S_AXI_ARVALID
I
Slave read address valid
S_AXI_ARREADY
O
Slave read address ready
S_AXI_RID[C_S_AXI_ID_WIDTH-1:0]
O
Slave read ID tag
S_AXI_RDATA[C_S_AXI_DATA_WIDTH-1:0]
O
Slave read data
S_AXI_RRESP[1:0]
O
Slave read response
S_AXI_RLAST
O
Slave read last
S_AXI_RVALID
O
Slave read valid
S_AXI_RREADY
I
Slave read ready
AXI Master Interface
M_AXI_AWADDR[C_M_AXI_ADDR_WIDTH-1:0]
O
Master write address
M_AXI_AWLEN[7:0]
O
Master write burst length
M_AXI_AWSIZE[2:0]
O
Master write burst size
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 3: Top Level Interface Signals (Cont’d)
Signal Name
I/O
Description
M_AXI_AWBURST[1:0]
O
Master write burst type
M_AXI_AWPROT[2:0]
O
Master write protection type
M_AXI_AWVALID
O
Master write address valid
M_AXI_AWREADY
I
Master write address ready
M_AXI_WDATA[C_M_AXI_DATA_WIDTH-1:0]
O
Master write data
M_AXI_WSTRB[C_M_AXI_DATA_WIDTH/8-1:0]
O
Master write strobe
M_AXI_WLAST
O
Master write last
M_AXI_WVALID
O
Master write valid
M_AXI_WREADY
I
Master write ready
M_AXI_BID
I
Master response ID
M_AXI_BRESP[1:0]
I
Master write response
M_AXI_BVALID
I
Master write response valid
M_AXI_BREADY
O
Master response ready
M_AXI_ARADDR[C_M_AXI_ADDR_WIDTH-1:0]
O
Master read address
M_AXI_ARLEN[7:0]
O
Master read burst length
M_AXI_ARSIZE[2:0]
O
Master read burst size
M_AXI_ARBURST[1:0]
O
Master read burst type
M_AXI_ARPROT[2:0]
O
Master read protection type
M_AXI_ARVALID
O
Master read address valid
M_AXI_ARREADY
I
Master read address ready
M_AXI_RID[3:0]
I
Master read ID tag
M_AXI_RDATA[C_M_AXI_DATA_WIDTH-1:0]
I
Master read data
M_AXI_RRESP[1:0]
I
Master read response
M_AXI_RLAST
I
Master read last
M_AXI_RVALID
I
Master read valid
M_AXI_RREADY
O
Master read ready
AXI4-Lite Control Interface
S_AXI_CTL_AWADDR[31:0]
I
Slave write address
S_AXI_CTL_AWVALID
I
Slave write address valid
S_AXI_CTL_AWREADY
O
Slave write address ready
S_AXI_CTL_WDATA[31:0]
I
Slave write data
S_AX_CTL_WSTRB[3:0]
I
Slave write strobe
S_AXI_CTL_WVALID
I
Slave write valid
S_AXI_CTL_WREADY
O
Slave write ready
S_AXI_CTL_BRESP[1:0]
O
Slave write response
S_AXI_CTL_BVALID
O
Slave write response valid
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 3: Top Level Interface Signals (Cont’d)
Signal Name
I/O
Description
S_AXI_CTL_BREADY
I
Slave response ready
S_AXI_CTL_ARADDR[31:0]
I
Slave read address
S_AXI_CTL_ARVALID
I
Slave read address valid
S_AXI_CTL_ARREADY
O
Slave read address ready
S_AXI_CTL_RDATA[31:0]
O
Slave read data
S_AXI_CTL_RRESP[1:0]
O
Slave read response
S_AXI_CTL_RVALID
O
Slave read valid
S_AXI_CTL_RREADY
I
Slave read ready
PCIe Interface
REFCLK
I
PCIe Reference Clock
INTX_MSI_Request
I
Legacy Interrupt Input (see C_INTERRUPT_PIN) when
MSI_enable = ‘0’
Initiates a MSI write request when MSI_enable = ‘1’
MSI_enable
O
Indicates when MSI is enabled
PCI_EXP_RXP[C_NO_OF_LANES-1 : 0]
I
PCIe RX serial interface
PCI_EXP_RXN[C_NO_OF_LANES-1 : 0]
I
PCIe RX serial interface
PCI_EXP_TXP[C_NO_OF_LANES-1 : 0]
O
PCIe TX serial interface
PCI_EXP_TXN[C_NO_OF_LANES-1 :0]
O
PCIe TX serial interface
Memory Map
The memory map shown in Table 4 shows the address mapping for the AXI Bridge for PCI Express. These registers
are described in more detail in the following section. All registers are accessed via the AXI4-Lite Control Interface
and are offset from C_BASEADDR. During a reset, all registers return to default values.
Note: RC mode supported in future release.
Table 4: Memory Map
Offset
Contents
RO - EP, R/W - RC
0x000 - 0x124
PCIe Core Configuration Space Header
RO
0x128
Vendor-Specific Enhanced Capability (VSEC) Capability
RO
0x12C
VSEC Header
RO
0x130
Bridge Info
RO - EP, R/W - RC
0x134
Bridge Status and Control
R/W
0x138
Interrupt Decode
R/W
0x13C
Interrupt Mask
RO - EP, R/W - RC
0x140
Bus Location
RO
0x144
Physical-Side Interface (PHY) Status/Control
RO
0x148 - 0x1FF
Reserved (zeros returned on read)
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 4: Memory Map (Cont’d)
Offset
Contents
RO
0x200
VSEC Capability 2
RO
0x204
VSEC Header 2
R/W
0x208 - 0x234
AXI Base Address Translation Configuration Registers
RO
0x238 - 0xFFF
Reserved (zeros returned on read)
PCIe Core Configuration Space Header
The PCIe Core Configuration Space Header is a memory aperture for accessing the core for PCIe configuration
space. For a Spartan-6 device configurations, this area is read-only. For a Virtex-6 device configurations, this area is
read-only when configured as an endpoint. Writes are permitted for some registers when a Virtex-6 device is
configured as a root complex. Special access modes can be enabled using the PHY Status/Control register. Address
bits 12:2 map to the DWAddr core input. All reserved or undefined memory-mapped addresses must return zero
and writes have no effect.
VSEC Capability Register (Offset 0x128)
The VSEC structure allows the memory space of the core to appear as though it is a part of the underlying
Integrated Block for the PCIe configuration space. The VSEC is inserted immediately following the last enhanced
capability structure in the underlying block. VSEC is defined in §7.18 of the PCI Express Base Specification, v1.1 (§7.19
of v2.0).
Table 5: VSEC Capability Register
Bit(s)
Name
Core
Access
Reset Value
Description
15:0
VSEC Capability ID
RO
0x000B
PCI-SIG® defined ID identifying this Enhanced Capability as a
Vendor-Specific capability. Hard-coded to 0x000B.
19:16
Capability Version
RO
0x1
Version of this capability structure. Hard-coded to 0x1.
31:20
Next Capability
Offset
RO
0x200
Offset to next capability. Hard-coded to 0x0200.
VSEC Header Register (Offset 0x12C)
The VSEC header provides a unique (within a given vendor) identifier for the layout and contents of the VSEC
structure, as well as its revision and length.
Table 6: VSEC Header Register
Bit(s)
Name
Core
Access
Reset Value
Description
15:0
VSEC ID
RO
0x0001
ID value uniquely identifying the nature and format of this VSEC
structure.
19:16
VSEC REV
RO
0
Version of this capability structure. Hard-coded to 0h.
31:20
VSEC Length
RO
0x038
Length of the entire VSEC Capability structure, in bytes,
including the VSEC Capability register. Hard-coded to 0x038
(56 decimal).
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Bridge Info Register (Offset 0x130)
The Bridge Info register provides general configuration information about the AXI4-Stream Bridge. Information in
this register is static and does not change during operation.
Table 7: Bridge Info Register
Bit(s)
Name
Core
Access
Reset
Value
0
Gen2 Present
RO
0
Indicates underlying Integrated Block is running at Gen2 speeds for
PCIe when this bit is set. When set to ‘0’, there may be no link, or the
link is set to GEN1. If set, indicates the link is running at GEN2 (and can
transition back to ‘0’ if the link speed changes from GEN2).
If set, GEN2 PHY Register is present in this interface.
1
Reserved
RO
0
Reserved
2
Up Config Capable
RO
18:3
Reserved
RO
0
Reserved
31:19
Reserved
RO
0
Reserved
Description
Indicates underlying Integrated Block is upconfig capable when this bit
is set.
Bridge Status and Control Register (Offset 0x134)
The Bridge Status and Control register provides information about the current state of the AXI4-Stream Bridge. It
also provides control over how reads and writes to the Core Configuration Access aperture are handled. For
Spartan-6 devices, this register is not used and the contents are hard-wired to 0.
Table 8: Bridge Status and Control Register
Bit(s)
Name
Core
Access
Reset
Value
Description
7:0
Reserved
RO
0
Reserved
8
Global Interrupt
Disable
RW
0
When set, it disables the interrupt line from being asserted. Does not
prevent bits in Interrupt Decode register from being set.
15:9
Reserved
RO
0
Reserved
16
RW1C as RW
RW
0
When set, allows writing to core registers that are normally RW1C.
Hard-wired to zero for Spartan-6 device cores.
31:17
Reserved
RO
0
Reserved
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Interrupt Decode Register (Offset 0x138)
The Interrupt Decode register provides a single location where the host processor interrupt service routine can
determine what is causing the interrupt to be asserted and how to clear the interrupt. Writing a 1 to any bit of the
Interrupt Decode register clears that bit.
Note: An asserted bit in the Interrupt Decode register does not cause the interrupt line to assert unless the corresponding bit
in the Interrupt Mask register is also set.
Table 9: Interrupt Decode Register
Bit(s)
Name
Core
Access
Reset
Value
0
Link Down
RW1C
0
Indicates that Link-Up on the PCI Express link was lost. Not asserted
unless link-up had previously been seen.
1
Reserved
RO
0
Reserved
2
Streaming Error
RW1C
0
Indicates a gap was encountered in a streamed packet on the Tx
interface (RW, RR, or CC).
3
Hot Reset
RW1C
0
Indicates a Hot Reset was detected.
4
Reserved
RO
0
Reserved
7:5
Cfg Completion
Status
RW1C
0
Indicates config completion status.
19:8
Reserved
0
Reserved
20
Slave Unsupported
Request
RW1C
0
Indicates that a completion TLP was received with a status of 0b001 Unsupported Request.
21
Slave Unexpected
Completion
RW1C
0
Indicates that a completion TLP was received that was unexpected.
22
Slave Completion
Timeout
RW1C
0
Indicates that the expected completion TLP(s) for a read request for PCIe
was not returned within the time period selected by the
C_COMP_TIMEOUT parameter.
23
Slave Error Poison
RW1C
0
Indicates the EP bit was set in a completion TLP.
24
Slave Completer
Abort
RW1C
0
Indicates that a completion TLP was received with a status of 0b100 Completer Abort.
25
Slave Illegal Burst
RW1C
0
Indicates that a burst type other than INCR was requested by the AXI
Master.
26
Master DECERR
RW1C
0
Indicates a DECERR response was received.
27
Master SLVERR
RW1C
0
Indicates a SLVERR response was received.
28
Master Error Poison
RW1C
0
Indicates an EP bit was set in a MemWR TLP for PCIe.
31:29
Reserved
RO
0
Reserved
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Interrupt Mask Register (Offset 0x13C)
The Interrupt Mask register controls whether each individual interrupt source can cause the interrupt line to be
asserted. A ‘1’ in any location allows the interrupt source to assert the interrupt line. The Interrupt Mask register
initializes to all zeros. Therefore, by default no interrupt is generated for any event. Table 10 describes the Interrupt
Mask register bits and values.
Table 10: Interrupt Mask Register
Bit(s)
Name
Core
Access
Reset
Value
Description
0
Link Down
RW
0
Enables interrupts for Link Down events when bit is set.
1
Reserved
RO
0
Reserved
2
Streaming Error
RW
0
Enables interrupts for Streaming Error events when bit is set.
3
Hot Reset
RW
0
Enables interrupts for Hot Reset events when bit is set.
4
Reserved
RO
0
Reserved
7:5
Cfg Completion
Status
RO
0
Enables interrupts for config completion status.
8
Cfg Timeout
RO
0
Enables interrupts for Config (Cfg) Timeout events when bit is set.
9
Correctable
RO
0
Enables interrupts for Correctable Error events when bit is set.
10
Non-Fatal
RO
0
Enables interrupts for Non-Fatal Error events when bit is set.
11
Fatal
RO
0
Enables interrupts for Fatal Error events when bit is set.
16:12
Reserved
RO
0
Reserved
17
MSI Interrupt
Received
RO
0
Enables interrupts for MSI Interrupt events when bit is set.
19:18
Reserved
RO
0
Reserved
20
Slave Unsupported
Request
RW
0
Enables the Slave Unsupported Request interrupt when bit is set.
21
Slave Unexpected
Completion
RW
0
Enables the Slave Unexpected Completion interrupt when bit is set.
22
Slave Completion
Timeout
RW
0
Enables the Slave Completion Timeout interrupt when bit is set.
23
Slave Error Poison
RW
0
Enables the Slave Error Poison interrupt when bit is set.
24
Slave Completer
Abort
RW
0
Enables the Slave Completer Abort interrupt when bit is set.
25
Slave Illegal Burst
RW
0
Enables the Slave Illegal Burst interrupt when bit is set.
26
Master DECERR
RW
0
Enables the Master DECERR interrupt when bit is set.
27
Master SLVERR
RW
0
Enables the Master SLVERR interrupt when bit is set.
28
Master Error Poison
RW
0
Enables the Master Error Poison interrupt when bit is set.
31:29
Reserved
RO
0
Reserved
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Bus Location Register (Offset 0x140)
The Bus Location register reports the Bus, Device, and Function number, and the Port number for the PCIe port
(Table 11).
Table 11: Bus Location Register
Bit(s)
Name
Core
Access
Reset
Value
Description
2:0
Function Number
RO
0
Function number of the port for PCIe. Hard-wired to 0.
7:3
Device Number
RO
0
Device number of port for PCIe. For Endpoint, this register is RO and is
set by the Root Complex.
15:8
Bus Number
RO
0
Bus number of port for PCIe. For Endpoint, this register is RO and is set
by the Root Complex.
23:16
Port Number
RW
0
Sets the Port number field of the Link Capabilities register. Not supported
for Spartan-6 devices.
31:24
Reserved
RO
0
Reserved
PHY Status/Control Register (Offset 0x144)
The PHY Status/Control register (described in Table 12) provides the status of the current PHY state, as well as the
control of speed and rate switching for Gen2-capable cores.
Table 12: PHY Status/Control Register
Bit(s)
Name
Core
Access
Reset
Value
Description
0
Link Rate
RO
0
Reports the current link rate. 0b = 2.5 GT/s, 1b = 5.0 GT/s.
2:1
Link Width
RO
0
Reports the current link width. 00b = x1, 01b = x2, 10b = x4, 11b = x8.
8:3
LTSSM State
RO
0
Reports the current LTSSM state. Encoding is specific to the underlying
Integrated Block.
10:9
Lane Reversal
RO
0
Reports the current lane reversal mode.
00b = No reversal,
01b = Lanes 1:0 reversed,
10b = Lanes 3:0 reversed,
11b = Lanes 7:0 reversed.
11
Link Up
RO
0
Reports the current PHY Link-up state.
1b = Link up,
0b = Link down.
15:12
Reserved
RO
0
Reserved
17:16
Directed Link Width
RW
0
Specifies completer link width for a directed link change operation. Only
acted on when Directed Link Change specifies a width change.
00b = x1,
01b = x2,
10b = x4,
11b = x8.
Hardwired to 0.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 12: PHY Status/Control Register (Cont’d)
Core
Access
Reset
Value
Directed Link Width
Speed
RW
0
Specifies completer link speed for a directed link change operation. Only
acted on when Directed Link Change specifies a speed change.
0b = 2.5 GT/s,
1b = 5.0 GT/s.
Hard-wired to 0.
19
Directed Link
Autonomous
RW
0
Specifies link reliability or autonomous for a directed link change
operation.
0b = link reliability,
1b = autonomous.
Hard-wired to 0.
21:20
Directed Link
Change
RW
0
Directs LTSSM to initiate a link width and/or speed change.
00b = no change,
01b = force link width,
10b = force link speed,
11b = force link width & speed.
Register is write only: a write triggers a link change, but a read always
returns 00b.
31:22
Reserved
RO
0
Reserved
Bit(s)
Name
18
Description
VSEC Capability Register 2 (Offset 0x200)
The VSEC structure allows the memory space for the core to appear as though it is a part of the underlying
integrated block PCIe configuration space. The VSEC is inserted immediately following the last enhanced
capability structure in the underlying block. VSEC is defined in §7.18 of the PCI Express Base Specification, v1.1 (§7.19
of v2.0)
This Register is only included if C_INCLUDE_BAR_OFFSET_REG = 1.
Table 13: VSEC Capability Register2
Bit(s)
Name
Core
Access
Reset
Value
15:0
VSEC Capability ID
RO
0x000B
PCI-SIG defined ID identifying this Enhanced Capability as a VendorSpecific capability. Hard-coded to 0x000B.
19:16
Capability Version
RO
0x1
Version of this capability structure. Hardcoded to 0x1.
31:20
Next Capability
Offset
RO
0x000
Offset to next capability
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
VSEC Header Register 2 (Offset 0x204)
The VSEC Header Register 2 (described in Table 14) provides a unique (within a given vendor) identifier for the
layout and contents of the VSEC structure, as well as its revision and length.
This Register is only included if C_INCLUDE_BAR_OFFSET_REG = 1.
Table 14: VSEC Header Register 2
Bit(s)
Name
Core
Access
Reset Value
Description
15:0
VSEC ID
RO
0x0002
ID value uniquely identifying the nature and format of this VSEC
structure.
19:16
VSEC REV
RO
0x0
Version of this capability structure. Hard-coded to 0x0.
31:20
VSEC Length
RO
0x038
Length of the entire VSEC Capability structure, in bytes,
including the VSEC Capability register. Hard-coded to 0x038
(56 decimal).
AXI Base Address Translation Configuration Registers (Offset 0x208 - 0x234)
The AXI Base Address Translation Configuration Registers and their offsets are shown in Table 15 and the register
bits are described in Table 16. This set of registers can be used in two configurations based on the top level
parameter C_AXIBAR_AS_n. When the BAR is set to a 32-bit address space, the translation vector should be placed
into the AXIBAR2PCIEBAR_nL register where n is the BAR number. When the BAR is set to a 64-bit address space,
the translation’s most significant 32 bits are written into the AXIBAR2PCIEBAR_nU and the least significant 32 bits
are written into AXIBAR2PCIEBAR_nL. These Registers are only included if C_INCLUDE_BAR_OFFSET_REG = 1.
Table 15: AXI Base Address Translation Configuration Registers
Offset
Bits
Register Mnemonic
0x208
31-0
AXIBAR2PCIEBAR_0U
0x20C
31-0
AXIBAR2PCIEBAR_0L
0x210
31-0
AXIBAR2PCIEBAR_1U
0x214
31-0
AXIBAR2PCIEBAR_1L
0x218
31-0
AXIBAR2PCIEBAR_2U
0x21C
31-0
AXIBAR2PCIEBAR_2L
0x220
31-0
AXIBAR2PCIEBAR_3U
0x224
31-0
AXIBAR2PCIEBAR_3L
0x228
31-0
AXIBAR2PCIEBAR_4U
0x22C
31-0
AXIBAR2PCIEBAR_4L
0x230
31-0
AXIBAR2PCIEBAR_5U
0x234
31-0
AXIBAR2PCIEBAR_5L
DS820 October 19, 2011
Product Specification
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20
LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 16: AXI Base Address Translation Configuration Register Bit Definitions
Core
Access
Reset Value
Description
Lower
Address
R/W
C_AXIBAR2PCIEBAR_0(31 to 0)
Lower Address: To create the address for
PCIe–this is the value substituted for the least
significant 32 bits of the AXI address.
Upper
Address
R/W
if (C_AXIBAR2PCIEBAR_0 = 64 bits) then Upper Address: To create the address for
reset value = C_AXIBAR2PCIEBAR_0(63 PCIe–this is the value substituted for the most
significant 32 bits of the AXI address.
to 32)
Bits
Name
31-0
31-0
if(C_AXIBAR2PCIEBAR_0 = 32 bits) then
reset value = 0x00000000
31-0
Lower
Address
R/W
C_AXIBAR2PCIEBAR_1(31 to 0)
Lower Address: To create the address for
PCIe–this is the value substituted for the least
significant 32 bits of the AXI address.
31-0
Upper
Address
R/W
if (C_AXIBAR2PCIEBAR_1 = 64 bits) then Upper Address: To create the address for
reset value = C_AXIBAR2PCIEBAR_1(63 PCIe– this is the value substituted for the most
significant 32 bits of the AXI address.
to 32)
if (C_AXIBAR2PCIEBAR_1 = 32 bits) then
reset value = 0x00000000
31-0
Lower
Address
R/W
C_AXIBAR2PCIEBAR_2(31 to 0)
Lower Address: To create the address for
PCIe–this is the value substituted for the least
significant 32 bits of the AXI address.
31-0
Upper
Address
R/W
if (C_AXIBAR2PCIEBAR_2 = 64 bits) then Upper Address: To create the address for
reset value = C_AXIBAR2PCIEBAR_2(63 PCIe–this is the value substituted for the most
significant 32 bits of the AXI address.
to 32)
if(C_AXIBAR2PCIEBAR_2 = 32 bits) then
reset value = 0x00000000
31-0
Lower
Address
R/W
C_AXIBAR2PCIEBAR_3(31 to 0)
Lower Address: To create the address for
PCIe–this is the value substituted for the least
significant 32 bits of the AXI address.
31-0
Upper
Address
R/W
if (C_AXIBAR2PCIEBAR_3 = 64 bits) then Upper Address: To create the address for
reset value = C_AXIBAR2PCIEBAR_3(63 PCIe–this is the value substituted for the most
significant 32 bits of the AXI address.
to 32)
if(C_AXIBAR2PCIEBAR_3 = 32 bits) then
reset value = 0x00000000
31-0
Lower
Address
R/W
DS820 October 19, 2011
Product Specification
C_AXIBAR2PCIEBAR_4(31 to 0)
www.xilinx.com
Lower Address: To create the address for
PCIe–this is the value substituted for the least
significant 32 bits of the AXI address.
21
LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 16: AXI Base Address Translation Configuration Register Bit Definitions (Cont’d)
Bits
Name
31-0
Upper
Address
Core
Access
R/W
Reset Value
Description
if (C_AXIBAR2PCIEBAR_4 = 64 bits) then Upper Address: To create the address for
reset value = C_AXIBAR2PCIEBAR_4(63 PCIe–this is the value substituted for the most
significant 32 bits of the AXI address.
to 32)
if(C_AXIBAR2PCIEBAR_4 = 32 bits) then
reset value = 0x00000000
31-0
Lower
Address
R/W
C_AXIBAR2PCIEBAR_5(31 to 0)
Lower Address: To create the address for
PCIe–this is the value substituted for the least
significant 32 bits of the AXI address.
31-0
Upper
Address
R/W
if (C_AXIBAR2PCIEBAR_5 = 64 bits) then Upper Address: To create the address for
reset value = C_AXIBAR2PCIEBAR_5(63 PCIe–this is the value substituted for the most
significant 32 bits of the AXI address.
to 32)
if (C_AXIBAR2PCIEBAR_5 = 32 bits) then
reset value = 0x00000000
Clock and Reset Interface
Clock Interface
The AXI_ACLK_OUT output must be fed back and used for the input of AXI_ACLK. This is the main memory
mapped AXI4 bus clock.
The REFCLK input must be provided at the frequency selected by the value of C_REF_CLK_FREQ. This clock is
used to generate the two output clocks and is also the clock used to drive the AXI4 bus.
The AXI_CTL_ACLK_OUT output must be fed back and used for the input AXI_CTL_ACLK. This is the AXI4-Lite
interconnect clock. The AXI_CTL_ACLK_OUT clock is rising-edge aligned and an integer division of the
AXI_ACLK_OUT clock.
X-Ref Target - Figure 2
!8)?!#,+
0#)E2EFERENCE#LOCK
!8)?!#,+?/54
!8)
0#)E
)0
2%&#,+
--#-?,/#+
!8)?#4,?!#,+?/54
!8)?#4,?!#,+
X
Figure 2: Clocking Diagram
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Product Specification
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22
LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Reset Interface
The bridge is designed to be used with the Proc_Sys_Reset module for generation of the AXI_ARESET input. When
using the EDK tools to build a system, it is best to connect the PERSTN pin of the host connector for PCIe to the
Peripheral_Reset port of the Proc_Sys_Reset module. The bridge does not use PERSTN directly. Also, the
MMCS_LOCK output must be connected to the DCM_Locked input of the Proc_Sys_Reset module to make sure that
AXI_ARESET is held active for 16 clocks after MMCM_LOCK becomes active. See Figure 3.
X-Ref Target - Figure 3
PROC?SYS?RESET
)0
0%234N
!UX?2ESET?)N
)NTERCONNECT?ARESETN
--#-?,/#+
!8)!2%3%4N
$#-?,/#+%$
!8)
0#)E
)0
!8)?!2%3%4.
8
Figure 3: System Reset Connection
AXI Transactions for PCIe
Table 17 and Table 18 are the translations tables for AXI4-Stream and memory mapped transactions.
Table 17: AXI4 Memory-Mapped Transactions to AXI4-Stream PCIe TLPs
AXI4 Memory-Mapped Transaction
AXI4-Stream PCIe TLPs
INCR Burst Read of 32-bit address AXIBAR
MemRd 32 (3DW)
INCR Burst Write to 32-bit address AXIBAR
MemWr 32 (3DW)
INCR Burst Read of 32-bit address AXIBAR
MemRd 64 (4DW)
INCR Burst Write to 32-bit address AXIBAR
MemWr 64 (4DW)
Table 18: AXI4-Stream PCIe TLPs to AXI4 Memory Mapped Transactions
AXI4-Stream PCIe TLPs
AXI4 Memory-Mapped Transaction
MemRd 32 (3DW) of PCIEBAR
INCR Burst Read with 32-bit address
MemWr 32 (3DW) to PCIEBAR
INCR Burst Write with 32-bit address
MemRd 64 (4DW) of PCIEBAR
INCR Burst Read with 32-bit address
MemWr 64 (4DW) to PCIEBAR
INCR Burst Write with 32-bit address
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Transaction Ordering for PCIe
The AXI PCIe Bridge conforms to strict PCIe transaction ordering rules. See the PCIe v2.1 Specification for the
complete rule set. The following behaviors are implemented in the AXI PCIE bridge to enforce the PCIe transaction
ordering rules on the highly-parallel AXI bus of the bridge. The rules are enforced without regard to the Relaxed
Ordering attribute bit within the TLP header:
1.
The BRESP to the remote (requesting) AXI4 master device for a write to a remote PCIe device is not issued until
the MemWr TLP transmission is guaranteed to be sent on the PCIe link before any subsequent tx-transfers.
2.
A remote AXI master read of a remote PCIe device is not permitted to pass any previous or simultaneous AXI
master writes to a remote PCIe device that occurs previously or at the same time. Timing is based on the AXI
ARVALID signal timing relative to the AXI AWVALID. Any AXI write transaction in which AWVALID was
asserted before or at the same time as the ARVALID for a read from PCIe is asserted causes the MemRd TLP(s)
to be held until the pipelined or simultaneous MemWr TLP(s) have been sent.
3.
A remote PCIe device read of a remote AXI slave is not permitted to pass any previous remote PCIe device
writes to a remote AXI slave received by the AXI PCIe bridge. The AXI read address phase is held until the
previous AXI write transactions have completed and BRESP has been received for the AXI write transactions.
4.
Read completion data received from a remote PCIe device are not permitted to pass any remote PCIe device
writes to a remote AXI slave received by the AXI PCIe bridge prior to the read completion data. The BRESP for
the AXI write(s) must be received before the completion data is presented on the AXI read data channel.
5.
Read data from a remote AXI slave is not permitted to pass any remote AXI master writes to a remote PCIe
device initiated on the AXI bus prior to or simultaneously with the read data being returned on the AXI bus.
Timing is based on the AXI AWVALID signal timing relative to the AXI RVALID assertion. Any AXI write
transaction in which AWVALID was asserted before or simultaneously with the RVALID being asserted up to
and including the last data beat, causes the Completion TLP(s) to be held until the pipelined or simultaneous
MemWr TLP(s) have been sent.
Note: The transaction ordering rules for PCIe have an impact on data throughput in heavy bidirectional traffic.
Address Translation
The address space for PCIe is different than the AXI address space. To access one address space from another
address space requires an address translation process. On the AXI side, the bridge supports mapping to PCIe of up
to six 32-bit or 64-bit AXI base address registers (BARs). The generics used to configure the BARs follow.
C_AXIBAR_NUM, C_AXIBAR_n, C_AXIBAR_HIGHADDR_n, C_AXIBAR2PCIEBAR_n and C_AXIBAR_AS_n,
where "n" represents an AXI BAR number from 0 to 5. The bridge for PCIe supports mapping of up to three 64-bit
BARs for PCIe. The generics used to configure the BARs are:
C_PCIEBAR_NUM, C_PCIE2AXIBAR_n and C_PCIEBAR_LEN_n,
where "n" represents a particular BAR number for PCIe from 0 to 2.
The C_INCLUDE_BAROFFSET_REG generic allows for dynamic address translation. When this parameter is set to
one, the AXIBAR2PCIEBAR_n translation vectors can be changed by using the software.
In the four following examples:
•
Example 1 (32-bit PCIe Address Mapping) demonstrates how to set up four 32-bit AXI BARs and translate the
AXI address to an address for PCIe.
•
Example 2 (64-bit PCIe Address Mapping) demonstrates how to set up three 64-bit AXI BARs and translate the
AXI address to an address for PCIe.
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Product Specification
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
•
Example 3 demonstrates how to set up two 64-bit PCIe BARs and translate the address for PCIe to an AXI
address.
•
Example 4 demonstrates how set up a combination of two 32-bit AXI BARs and two 64 bit AXI BARs, and
translate the AXI address to an address for PCIe.
Example 1 (32-bit PCIe Address Mapping)
This example shows the generic settings to set up four independent 32-bit AXI BARs and address translation of AXI
addresses to a remote address space for PCIe. This setting of AXI BARs does not depend on the BARs for PCIe
within the AXI Bridge for PCIe.
In this example, where C_AXIBAR_NUM=4, the following assignments for each range are made:
C_AXIBAR_AS_0=0
C_AXIBAR_0=0x12340000
C_AXI_HIGHADDR_0=0x1234FFFF
C_AXIBAR2PCIEBAR_0=0x5671XXXX (Bits 15-0 are don’t cares as the lower 16-bits will hold the
actual lower 16-bits of the PCIe address)
C_AXIBAR_AS_1=0
C_AXIBAR_1=0xABCDE000
C_AXI_HIGHADDR_1=0xABCDFFFF
C_AXIBAR2PCIEBAR_1=0xFEDC0XXX (Bits 12-0 are don’t cares as the lower 13-bits will hold the
actual lower 13-bits of the PCIe address)
C_AXIBAR_AS_2=0
C_AXIBAR_2=0xFE000000
C_AXI_HIGHADDR_2=0xFFFFFFFF
C_AXIBAR2PCIEBAR_2=0x40XXXXXX (Bits 24-0 are don’t cares)
•
Accessing the Bridge AXIBAR_0 with address 0x12340ABC on the AXI bus yields 0x56710ABC on the bus for
PCIe. See Figure 4.
X-Ref Target - Figure 4
!8)!7!$$2 X!"#
#?!8)"!20#)%"!2?XXXXX
#?!8)"!2?
X
)NTERMEDIATE !DDRESS X!"#
#?!8)?()'(!$$2?
X&&&&
!"# &INAL 0#)E !DDRESS X!"#
!8)TO0#)E!DDRESS4RANSLATION
8
Figure 4: AXI to PCIe Address Translation
•
Accessing the Bridge AXIBAR_1 with address 0xABCDF123 on the AXI bus yields 0xFEDC1123 on the bus for
PCIe.
•
Accessing the Bridge AXIBAR_2 with address 0xFFFEDCBA on the AXI bus yields 0x41FEDCBA on the bus for
PCIe.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Example 2 (64-bit PCIe Address Mapping)
This example shows the generic settings to set up to three independent 64-bit AXI BARs and address translation of
AXI addresses to a remote address space for PCIe. This setting of AXI BARs does not depend on the BARs for PCIe
within the Bridge.
In this example, where C_AXIBAR_NUM=3, the following assignments for each range are made:
C_AXIBAR_AS_0=1
C_AXIBAR_0=0x12340000
C_AXI_HIGHADDR_0=0x1234FFFF
C_AXIBAR2PCIEBAR_0=0x500000005671XXXX (Bits 15-0 are don’t cares)
C_AXIBAR_AS_1=1
C_AXIBAR_1=0xABCDE000
C_AXI_HIGHADDR_1=0xABCDFFFF
C_AXIBAR2PCIEBAR_1=0x60000000FEDC0XXX (Bits 12-0 are don’t cares)
C_AXIBAR_AS_2=1
C_AXIBAR_2=0xFE000000
C_AXI_HIGHADDR_2=0xFFFFFFFF
C_AXIBAR2PCIEBAR_2=0x7000000040XXXXXX (Bits 24-0 are don’t cares)
•
Accessing the Bridge AXIBAR_0 with address 0x12340ABC on the AXI bus yields 0x5000000056710ABC on
the bus for PCIe.
•
Accessing the Bridge AXIBAR_1 with address 0xABCDF123 on the AXI bus yields 0x60000000FEDC1123 on
the bus for PCIe.
•
Accessing the Bridge AXIBAR_2 with address 0xFFFEDCBA on the AXI bus yields 0x7000000041FEDCBA on
the bus for PCIe.
Example 3
This example shows the generic settings to set up two independent BARs for PCIe and address translation of
addresses for PCIe to a remote AXI address space. This setting of BARs for PCIe does not depend on the AXI BARs
within the bridge.
In this example, where C_PCIEBAR_NUM=2, the following range assignments are made:
BAR 0 is set to 0x20000000ABCDE800 by the Root Complex
C_PCIEBAR_LEN_0=11
C_PCIEBAR2AXIBAR_0=0x123450XX (Bits 10-0 are don’t cares)
BAR 1 is set to 0xA000000012000000 by Root Complex
C_PCIEBAR_LEN_1=25
C_PCIEBAR2AXIBAR_1=0xFEXXXXXX (Bits 24-0 are don’t cares)
•
Accessing the Bridge PCIEBAR_0 with address 0x20000000ABCDEFF4 on the bus for PCIe yields
0x123457F4 on the AXI bus.
DS820 October 19, 2011
Product Specification
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
X-Ref Target - Figure 5
#?0#)%"!2!8)"!2?XXX
#?0#)%"!2?,%.?
LEASTSIGNIFICANTBITS
PROVIDEWINDOW
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Y'
0#)ETO!8)!DDRESS4RANSLATION
8
Figure 5: PCIe to AXI Translation
•
Accessing Bridge PCIEBAR_1 with address 0xA00000001235FEDC on the bus for PCIe yields 0xFE35FEDC
on the AXI bus.
Example 4
This example shows the generic settings to set up a combination of two independent 32-bit AXI BARs and two
independent 64-bit BARs and address translation of AXI addresses to a remote address space for PCIe. This setting
of AXI BARs does not depend on the BARs for PCIe within the Bridge.
In this example, where C_AXIBAR_NUM=4, the following assignments for each range are made:
C_AXIBAR_AS_0=0
C_AXIBAR_0=0x12340000
C_AXI_HIGHADDR_0=0x1234FFFF
C_AXIBAR2PCIEBAR_0=0x5671XXXX (Bits 15-0 are don’t cares)
C_AXIBAR_AS_1=1
C_AXIBAR_1=0xABCDE000
C_AXI_HIGHADDR_1=0xABCDFFFF
C_AXIBAR2PCIEBAR_1=0x50000000FEDC0XXX (Bits 12-0 are don’t cares)
C_AXIBAR_AS_2=0
C_AXIBAR_2=0xFE000000
C_AXI_HIGHADDR_2=0xFFFFFFFF
C_AXIBAR2PCIEBAR_2=0x40XXXXXX (Bits 24-0 are don’t cares)
C_AXIBAR_AS_3=1
C_AXIBAR_3=0x00000000
C_AXI_HIGHADDR_3=0x0000007F
C_AXIBAR2PCIEBAR_3=0x600000008765438X (Bits 6-0 are don’t cares)
•
Accessing the Bridge AXIBAR_0 with address 0x12340ABC on the AXI bus yields 0x56710ABC on the bus for
PCIe.
•
Accessing the Bridge AXIBAR_1 with address 0xABCDF123 on the AXI bus yields 0x50000000FEDC1123 on
the bus for PCIe.
DS820 October 19, 2011
Product Specification
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27
LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
•
Accessing the Bridge AXIBAR_2 with address 0xFFFEDCBA on the AXI bus yields 0x41FEDCBA on the bus for
PCIe.
•
Accessing the AXI M S PCIe Bridge AXIBAR_3 with address 0x00000071 on the AXI bus yields
0x60000000876543F1 on the bus for PCIe.
Interrupts
This section describes the interrupt pins which include Local, MSI and Legacy Interrupts.
Local Interrupts
The INTERRUPT_OUT pin can be configured to send interrupts based on the settings of the Interrupt Mask register.
The INTERRUPT_OUT pin signals interrupts to devices attached to the memory mapped AXI4 side of the Bridge.
The MSI interrupt defined in the Interrupt Mask & Interrupt Decode registers is used to indicate the receipt of a
Message Signaled Interrupt only when the bridge is operating in Root Complex mode (C_INCLUDE_RC=1).
MSI Interrupt
When the MSI_enable output pin indicates that the bridge has Endpoint MSI functionality enabled (MSI_enable
= ‘1’), the INTX_MSI_Request input pin is defined as MSI_Request and can be used to trigger a Message
Signaled Interrupt via a special MemWr TLP to an external Root Complex for PCIe on the PCIe side of the Bridge.
The INTX_MSI_Request input pin is positive-edge detected and synchronous to AXI_ACLK. The address and data
contained in this MemWr TLP are determined by an external Root Complex for PCIe configuration of registers
within the integrated block for PCI Express. The INTX_MSI_Request pin input is valid only when the bridge is
operating in Endpoint mode (C_INCLUDE_RC=0).
Legacy Interrupts
The bridge supports legacy interrupts for PCI if selected by the C_INTERRUPT_PIN parameter. A value of 1 selects
INTA, as defined in Table 1. If a legacy interrupt for PCI support is selected and the MSI_enable output pin
indicates that the bridge has end point MSI functionality disabled (MSI_enable = ‘0’), the INTX_MSI_Request
pin is defined as INTX. When the INTX pin goes high, an assert INTA message is sent. When the INTX pin goes low,
a deassert INTA message is sent. These messages are defined in the PCI 2.1 specification. The INTX_MSI_Request
pin input is valid only when the bridge is operating in Endpoint mode (C_INCLUDE_RC=0).
Malformed TLP
Because the Bridge is designed to work with the Enhanced Interface for PCIe, any malformed TLP is not seen by the
Bridge and is blocked by the Enhanced Interface for PCIe.
Abnormal Conditions
This section describes how the Slave side (Table 19) and Master side (Table 20) of the AXI Bridge for PCI Express
handle abnormal conditions.
Slave Bridge Abnormal Conditions
Slave Bridge abnormal conditions are classified as: Illegal Burst Type and Completion TLP Errors. The following
sections describe the manner in which the Bridge handles these errors.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Illegal Burst Type
The Slave Bridge monitors AXI read and write burst type inputs to ensure that only the INCR (incrementing burst)
type is requested. Any other value on these inputs is treated as an error condition and the Slave Illegal Burst (SIB)
interrupt is asserted. In the case of a read request, the Bridge asserts SLVERR for all data beats and arbitrary data is
placed on the S_AXI_RDATA bus. In the case of a write request, the Bridge asserts SLVERR for the write response
and all write data is discarded.
Completion TLP Errors
Any request to the bus for PCIe (except for posted Memory write) requires a completion TLP to complete the
associated AXI request. The Slave side of the Bridge checks the received completion TLPs for errors and checks for
completion TLPs that are never returned (Completion Timeout). Each of the completion TLP error types are
discussed in the subsequent sections.
Unexpected Completion
When the Slave Bridge receives a completion TLP, it matches the header RequesterID and Tag to the outstanding
RequesterID and Tag. A match failure indicates the TLP is an Unexpected Completion which results in the
completion TLP being discarded and a Slave Unexpected Completion (SUC) interrupt strobe being asserted.
Normal operation then continues.
Unsupported Request
A device for PCIe may not be capable of satisfying a specific read request. For example, the read request targets an
unsupported address for PCIe causing the completer to return a completion TLP with a completion status of "0b001
- Unsupported Request". The completer can also return a completion TLP with a completion status that is
“reserved” according to the 2.1 PCIe Specification, which must be treated as an unsupported request status. When
the slave bridge receives an unsupported request response, the Slave Unsupported Request (SUR) interrupt is
asserted and the SLVERR response is asserted with arbitrary data on the memory mapped AXI4 bus.
Completion Timeout
A Completion Timeout occurs when a completion (Cpl) or completion with data (CplD) TLP is not returned after
an AXI to PCIe read request. Completions must complete within the C_COMP_TIMEOUT parameter selected value
from the time the MemRd for PCIe request is issued. When a completion timeout occurs, a Slave Completion
Timeout (SCT) interrupt is asserted and the SLVERR response is asserted with arbitrary data on the memory
mapped AXI4 bus.
Poison Bit Received on Completion Packet
An Error Poison occurs when the completion TLP "EP" bit is set, indicating that there is poisoned data in the
payload. When the slave bridge detects the poisoned packet, the Slave Error Poison (SEP) interrupt is asserted and
the SLVERR response is asserted with arbitrary data on the memory mapped AXI4 bus.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Completer Abort
A Completer Abort occurs when the completion TLP completion status is "0b100 - Completer Abort". This indicates
that the completer has encountered a state in which it was unable to complete the transaction. When the slave
bridge receives a completer abort response, the Slave Completer Abort (SCA) interrupt is asserted and the SLVERR
response is asserted with arbitrary data on the memory mapped AXI4 bus.
Table 19: Slave Bridge Response to Abnormal Conditions
Transfer Type
Abnormal Condition
Bridge Response
Read
Illegal burst type
SIB interrupt is asserted.
SLVERR response given with arbitrary read data.
Write
Illegal burst type
SIB interrupt is asserted.
Write data is discarded.
SLVERR response given.
Read
Unexpected completion
SUC interrupt is asserted.
Completion is discarded.
Read
Unsupported Request status
returned
SUR interrupt is asserted.
SLVERR response given with arbitrary read data.
Read
Completion timeout
SCT interrupt is asserted.
SLVERR response given with arbitrary read data.
Read
Poison bit in completion
Completion data is discarded.
SEP interrupt is asserted.
SLVERR response given with arbitrary read data.
Read
Completer Abort status returned
SCA interrupt is asserted.
SLVERR response given with arbitrary read data.
Master Bridge Abnormal Conditions
The following sections describe the manner in which the Master Bridge handles abnormal conditions.
AXI DECERR Response
When the Master Bridge receives a DECERR response from the AXI bus, the request is discarded and the Master
DECERR (MDE) interrupt is asserted. If the request was non-posted, a completion packet with the Completion Status
= Unsupported Request (UR) is returned on the bus for PCIe.
AXI SLVERR Response
When the Master Bridge receives a SLVERR response from the addressed AXI slave, the request is discarded and the
Master SLVERR (MSE) interrupt is asserted. If the request was non-posted, a completion packet with the
Completion Status = Completer Abort (CA) is returned on the bus for PCIe.
Max Payload Size for PCIe, Max Read Request Size or 4K Page Violated
It is the responsibility of the requester to ensure that the outbound request adhere to the Max Payload Size, Max
Read Request Size, and 4k Page Violation rules. If the master bridge receives a request that violates one of these
rules, the bridge processes the invalid request as a valid request, which can result in the return of a completion that
violates one of these conditions or the loss of data. The Master Bridge does not return a malformed TLP completion
to signal this violation.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Completion Packets
A situation can exist where the read request for PCIe can ask for more data than the Master Bridge can insert into a
single completion packet. This situation can exist when the MAX_READ_REQUEST_SIZE is greater than the
MAX_PAYLOAD_SIZE. When this situation occurs, multiple completion packets are generated up to
MAX_PAYLOAD_SIZE, with the Read Completion Boundary (RCB) observed.
Poison Bit
When the poison bit is set in a transaction layer packet (TLP) header, the payload following the header is corrupt.
When the Master Bridge receives a memory request TLP with the poison bit set, it discards the TLP and asserts the
Master Error Poison (MEP) interrupt strobe.
Zero Length Requests
When the Master Bridge receives a read request with the Length = 0x1, FirstBE = 0x00, and LastBE = 0x00, it
responds by sending a completion with Status = Successful Completion. When the Master Bridge receives a write
request with the Length = 0x1, FirstBE = 0x00, and LastBE = 0x00 there is no effect.
Table 20: Master Bridge Response to Abnormal Conditions
Transfer Type
Abnormal Condition
Bridge Response
Read
DECERR response
MDE interrupt strobe asserted.
Completion returned with Unsupported Request status.
Write
DECERR response
MDE interrupt strobe asserted.
Read
SLVERR response
MSE interrupt strobe asserted.
Completion returned with Completer Abort status.
Write
SLVERR response
MSE interrupt strobe asserted.
Write
Poison bit set in request
MEP interrupt strobe asserted.
Data is discarded.
Read
DECERR response
MDE interrupt strobe asserted.
Completion returned with Unsupported Request status.
Write
DECERR response
MDE interrupt strobe asserted.
Link Down Behavior
The normal operation of the AXI Bridge for PCI Express is dependent on the Integrated Block for PCIe establishing
and maintaining the point-to-point link with an external device for PCIe. If the link has been lost, it must be reestablished to return to normal operation.
When a Hot Reset is received by the AXI PCIE, the link goes down and the PCI Config Space must be reconfigured.
Initiated AXI4 write transactions that have not yet completed on the AXI4 bus when the link goes down have a
SLVERR response given and the write data is discarded. Initiated AXI4 read transactions that have not yet
completed on the AXI4 bus when the link goes down have a SLVERR response given, with arbitrary read data
returned.
Any MemWr TLPs for PCIe that have been received, but the associated AXI4 write transaction has not started when
the link goes down, are discarded. If the associated AXI4 write transaction is in the process of being transferred, it
completes as normal. Any MemRd TLPs for PCIe that have been received, but have not returned completion TLPs
by the time the link goes down, complete on the AXI4 bus, but do not return completion TLPs on the PCIe bus.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Line Rate Support for PCIe Gen1/Gen2
The link speed, number of lanes supported, and support of line rate for PCIe are defined in Table 21. Achieving line
rate for PCIe is dependent on the device family, the AXI clock frequency, the AXI data width, the number of lanes,
and Gen 1 or Gen 2 link speed.
Table 21: Line Rate for PCIe Support for Gen1/Gen2
C_FAMILY
AXI_ACLK
Frequency
C_X_AXI_DATA_WIDTH
C_NO_OF_LANES
Gen 1
(2.5 GT/s)
Gen 2
(5.0 GT/s)
Spartan-6
62.5 MHz
32
x1
Yes
No
Virtex-6
125 MHz
64
x1
Yes
Yes
Virtex-6
125 MHz
64
x2
Yes
Yes
Virtex-6
125 MHz
64
x4
Yes
No
Virtex-6
125 MHz
64
x8
No
No
Limitations
Reference Clock for PCIe Frequency Value
The REFCLK input used by the serial transceiver for PCIe must be 100 MHz or 125 MHz for Spartan-6 device
configurations, and 100 MHz or 250 MHz for Virtex-6 device configurations. The C_REF_CLK_FREQ parameter is
used to set this value, as defined in Table 1.
AXI Clock Frequency Values
•
62.5 MHz for Spartan-6 FPGA devices
•
125 MHz for Virtex-6 FPGA devices
Constraints
The AXI PCIe core requires a clock period constraint for the REFCLK input that agrees with the C_REF_CLK_FREQ
parameter setting. Also, pin-placement constraints are needed that are board/part/package specific. More
information on the constraints needed in the UCF for an EDK system can be found in the Answer Record support
on www.xilinx.com.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Device Utilization and Performance Benchmarks
System Performance
X-Ref Target - Figure 6
AXI4
MicroBlaze
Domain
(IC)
(DC)
MicroBlaze
Controller
AXI4
Memory
Controller
MemoryMap
Interconnect
(AXI4)
Memory
AXI Block Ram
AXI PCIE
AXI CDMA
D_LMB
(DP)
I_LMB
Control
Interface
Subset
Interconnect
(AXI4-Lite)
Block RAM
Controller
AXI INTC
AXI GPIO
LEDs
AXI UARTLite
RS232
MDM
AXI4-Lite
Figure 6: Virtex-6 and Spartan-6 FPGA System Configuration Diagram
The target FPGA was filled with logic to drive the LUT and block RAM utilization to approximately 70% and the
I/O utilization to approximately 80%. The data shown in Table 22 was obtained using the default tool options and
the slowest speed grade for the target FPGA.
Table 22: System Performance
Target FPGA
XC6SLX45T (1)
XC6VLX240T
(2)
Target FMAX (MHz)
AXI4
AXI4-Lite
MicroBlaze
90 MHz
120 MHz
80 MHz
135 MHz
180 MHz
135 MHz
Notes:
1.
2.
Spartan-6 FPGA LUT utilization: 70%; block RAM utilization: 70%; I/O utilization: 80%; MicroBlaze™ processor not AXI4
interconnect; AXI4 interconnect configured with a single clock of 120 MHz.
Virtex-6 FPGA LUT utilization: 70%; block RAM utilization: 70%; I/O utilization: 80%.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
System Integration
A typical AXI PCIe system is shown in Figure 6. Some additional components to this system in the EDK
environment can include the need to connect the MicroBlaze processor peripheral ports to communicate with the
AXI PCIe bridge (in addition to the AXI4-Lite register port on the PCIe bridge). The EDK provides a helper core to
achieve this functionality and bridges transactions from the AXI4-Lite MicroBlaze processor peripheral ports (DP
and IP) to the AXI4 Interconnect (connected to the AXI PCIe bridge). The axi2axi_connector IP core provides this
support and the user can connect this in the EDK environment.
Specification Exceptions
N/A
Reference Documents
To search for Xilinx documentation, go to www.xilinx.com/support
1.
AMBA AXI Protocol Specification
2.
Xilinx AXI4 Memory-Mapped Protocol Specification Version 1.7
3.
AXI4-Stream PCIe Bridge Design Specification
4.
PCI Express Base Specification, v1.1 (§7.19 of v2.0)
5.
PCI Express Base Specification (v1.1 and v2.0), §7.2.2
6.
PCI Express Base Specification Revision 2.1
Support
Xilinx provides technical support for this LogiCORE™ IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering and Licensing Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE® Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE modules and software, please contact your
local Xilinx sales representative.
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
List of Acronyms
Table 23: List of Acronyms
Acronym
Spelled Out
AMBA
Advanced Microcontroller Bus Architecture
ARM
Advanced RISC Machine
AXI
Advanced eXtensible Interface
BAR
Base Address Register
CA
Completer Abort
Cfg
Config
Cpl
Completion
CplD
Completion with data
DECERR
Decoder Error status in AXI4
DSP
Digital Signal Processing
ECAM
Enhanced Configuration Access Mechanism
EDK
Embedded Development Kit
EP
Error Poison or EndPoint
FF
Flip-Flop
FIFO
First In First Out
FPGA
Field Programmable Gate Array
GT/s
Giga Transfers per second
I/O
Input/Output
IP
Intellectual Property
LTSSM
Link Training and Status State Machine
LUT
Lookup Table
MDE
Master DECERR
MEP
Master Error Poison
MHz
Mega Hertz
MPS
Maximum Payload Size
MSE
Master SLVERR
MSI
Messaged Signaled Interrupt
PCI
Peripheral Component Interconnect
PHY
physical-side interface
RAM
Random Access Memory
RC
Root Complex
RC/EP
Root Complex/Error Poison
RCB
Read Completion Boundary
RO
Read Only
R/W
Read/Write
SCA
Slave Completer Abort
SCT
Slave Completion Timeout
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
Table 23: List of Acronyms
Acronym
Spelled Out
SEP
Slave Error Poison
SIB
Slave Illegal Burst
SLVERR
Slave Error status in AXI4
SUC
Slave Unexpected Completion
SUR
Slave Unsupported Request
SW
Software
TLP
Transaction Layer Packets
UR
Unsupported Request
VHDL
VHSIC Hardware Description Language (VHSIC an acronym for Very High-Speed Integrated Circuits)
VSEC
Vendor-Specific Enhanced Capability
Revision History
Date
Version
Revision
6/22/11
1.0
Initial Xilinx Release.
9/13/11
1.1
Release with EDK 13.3.
10/19/11
1.2
Summary of Core Changes
• Updated Gen2 Present register in RTL
Summary of Documentation Changes
• Updated Bridge information and PHY status/control register per AXI-Enhanced
Architecture Specification v0.9.
• Added all C_INTERCONNECT_* parameters to the end of Table 1
• Added description about use of axi2axi_connector IP core in AXI PCIe systems.
Added a note that inclusion of this helper core is for MicroBlaze and XMD access
to the AXI PCIe IP
• Added Figures 4 and to pages 25 and 27
• Updated resource numbers and other information in IP Facts table
• Added System Integration section on page 33
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LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a)
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