MAX1960, MAX1961, MAX1962

MAX1960, MAX1961, MAX1962

19-2740; Rev 0; 1/03

EVALUATION KIT

AVAILABLE

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

General Description

The MAX1960/MAX1961/MAX1962 high-current, highefficiency voltage-mode step-down DC-DC controllers operate from a 2.35V to 5.5V input and generate output voltages down to 0.8V at up to 20A. An on-chip charge pump generates a regulated 5V for MOSFET drive.

Additionally, adaptive dead-time drivers allow a wide variety of MOSFETs to be used without risking shoot-through.

Fixed-frequency PWM operation and external synchronization make these controllers suitable for telecom and datacom applications. The operating frequency is programmable to either 500kHz or 1MHz, or from

450kHz to 1.2MHz with an external clock. A clock output is provided to synchronize another converter for 180° out-of-phase operation. A high closed-loop bandwidth provides excellent transient response for applications with dynamic loads.

Lossless current sensing in the MAX1960 and

MAX1961 is achieved by monitoring the drain-to-source voltage of the low-side external FET. The current limit is scalable to accommodate a wide variety of MOSFETs and load currents. The MAX1962 has 10% accurate sense-resistor-based current limiting.

The MAX1960 and MAX1962 have an adjustable output voltage from 0.8V to 4.95V. The MAX1961 and

MAX1962 have four preset output voltages (1.5V, 1.8V,

2.5V, and 3.3V) and feature 0.5% voltage accuracy over temperature, line, and load variations. The

MAX1960 and MAX1961 also feature voltage-margining control inputs that shift the output voltage up or down by 4% for system testing.

Features

0.5% Accurate Output

Operates from 2.35V to 5.5V Supply

Generates Low Output Voltage Down to 0.8V

On-Chip Charge Pump Provides 5V Gate Drive

Ceramic or Electrolytic Capacitors

94% Efficiency

External Synchronization from 450kHz to 1.2MHz

500kHz/1MHz Fixed-Frequency PWM Operation

Fast Transient Response

Two Converters Can Operate 180° Out-of-Phase

±4% Voltage Margining for System Test

10% Accurate Current Sensing (MAX1962)

Adaptive Dead Time Prevents Shoot-Through

Ordering Information

PART

MAX1960EEP

MAX1961EEP

MAX1962EEP

TEMP RANGE

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

PIN-PACKAGE

20 QSOP

20 QSOP

20 QSOP

INPUT

2.35V TO 5.5V

Typical Operating Circuit

V

CC

C+ C-

AV

DD

Applications

ASIC, FPGA, DSP, and CPU Core and I/O Voltages

Cellular Base Stations

Telecom and Network Equipment

Server and Storage Systems

Pin Configurations and Selector Guide appear at the end of the data sheet.

VOLTAGE

MARGINING

AND ON/OFF

CTL1

CTL2

COMP

MAX1960

V

DD

BST

DH

REF

GND

LX

DL

PGND

ILIM

OPTIONAL

SYNCHRONIZATION

CLKOUT

180

° OUT-OF-PHASE

FSET/SYNC

CLKOUT

FB

OUTPUT

0.8 TO 0.87

V

IN

UP TO 20A

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

ABSOLUTE MAXIMUM RATINGS

V

CC

, CTL_, CS, FSET/SYNC, SEL, EN,

OUT to GND ..........................................................-0.3V to +6V

ILIM, COMP, REF, FB, CLKOUT,

C- to GND ..............................................-0.3V to V

AVDD

+ 0.3V

C+ to GND.............-0.3V to higher of V

VCC

+ 1V or V

VDD

+ 0.3V

V

DD

, AV

DD to GND ..............-0.3V to higher of V

VCC

- 0.3V or 6V

DL to PGND ................................................-0.3V to V

VDD

+ 0.3V

BST to GND ............................................................-0.3V to +12V

DH to LX ...................................................................-0.3V to +6V

LX to BST..................................................................-6V to +0.3V

PGND to GND, or V

DD to AV

DD

............................-0.3V to +0.3V

Continuous Power Dissipation (T

A

= +70°C)

20-Pin QSOP (derate up to +70°C)..............................727mW

20-Pin QSOP (derate above +70°C) ........................9.1mW/°C

Operating Temperature Range (Extended).........-40°C to +85°C

Junction Temperature ......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

VCC

= 3.3V, Circuits of Figures 9–12, T

A

= 0°C to +85°C. Typical values are at T

A

= +25°C, unless otherwise noted.)

CONDITIONS TYP PARAMETER

V

CC

Input Voltage Range

V

CC

Input Voltage UVLO

V

DD

Input Voltage UVLO

Output Voltage

DC Output Accuracy

Positive Voltage-Margining Shift

Negative Voltage-Margining Shift

Load Regulation Error

Line Regulation Error

FB Input Bias Current

Feedback Transconductance

COMP Discharge Resistance

DC-DC Soft-Start Time

Switching Frequency

SYNC Frequency Range

Maximum Duty Cycle

Maximum Duty Cycle

Quiescent Supply Current

Shutdown Supply Current

Rising or falling, hysteresis = 33mV (typ)

Rising or falling, hysteresis = 44mV (typ)

MAX1960/MAX1962 (measured at FB)

SEL = GND

MAX1961/

MAX1962 (FB = V

DD

), measured at output

SEL = REF

SEL not connected

SEL = V

DD

MAX1960/MAX1961

MAX1960/MAX1961

0V to full load

V

VCC

= 2.7V to 5.5V

In shutdown

FSET/SYNC = GND

FSET/SYNC = V

CC f = 1MHz f = 500kHz

MIN

2.35

1.95

3.9

0.8

0.796

1.492

1.791

2.487

3.272

+3.8

-3.8

-0.2

1

450

880

450

80

90

0.800

1.500

1.800

2.500

3.300

+4

-4

0.08

0.1

2

10

1280

500

1000

83

92

11

MAX

5.5

2.3

4.45

0.804

1.508

1.809

2.514

3.336

+4.2

-4.2

+0.2

3

100

550

1120

1200

15

15

UNITS

V

V

V

V

V kHz kHz

%

% mA

µA

%

%

%

%

µA mS

Ω cycles

2 _______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

ELECTRICAL CHARACTERISTICS (continued)

(V

VCC

= 3.3V, Circuits of Figures 9–12, T

A

= 0°C to +85°C. Typical values are at T

A

= +25°C, unless otherwise noted.)

V

DD

PARAMETER

Output Voltage

CONDITIONS

2.7V

≤ V

VCC

≤ 5.5V, I

LOAD

= 1mA to 50mA

2.35V

≤ V

VCC

≤ 2.7V, I

LOAD

= 1mA to 35mA, C1

= 4.7

µF, C6 = 22µF (Note 1)

2.35V

≤ V

VCC

≤ 3.6V with tripler, I

LOAD

= 1 to

50mA (circuit of Figure 12) (Note 1)

Reference Voltage (No Load)

Reference Load Regulation -50

µA to +50µA

Positive Current-Limit Threshold

(V

PGND

- V

LX

)

MAX1962

V

OUT

= 0.8V

V

OUT

= 2.0V

V

OUT

= 3.3V

Negative Current-Limit Threshold

(V

LX

- V

PGND

)

CS Bias Current

OUT Bias Current

MAX1962, V

OUT

= 0.8V to 3.3V

MAX1962, V

CS

= 3.3V

MAX1961/MAX1962, V

OUT

= 3.3V

Current-Limit Threshold (Positive

Direction, Fixed, V

PGND

- V

LX

)

MAX1960/MAX1961, ILIM = V

DD

Current-Limit Threshold (Negative

Direction, Fixed, V

LX

- V

PGND

)

MAX1960/MAX1961, ILIM = V

DD

Current-Limit Threshold (Positive

Direction, Adjustable, V

PGND

- V

LX

Current-Limit Threshold (Negative

Direction, Adjustable, V

LX

- V

PGND

Thermal-Shutdown Threshold

DH Gate-Driver On-Resistance

)

)

DL Gate-Driver On-Resistance (Pullup)

MAX1960/MAX1961, R

ILIM

= 160k

R

ILIM

= 400k

MAX1960/MAX1961, R

ILIM

= 160k

R

ILIM

= 400k

15

°C hysteresis

V

BST

- V

LX

= 5V, pulling up or down

DL high state

DL Gate-Driver On-Resistance (Pulldown) DL low state

DH falling to DL rising

Minimum Adaptive Dead Time

DH rising to DL falling

FSET/SYNC Pulse Width

Minimum high time (Note 1)

Minimum low time (Note 1)

FSET/SYNC Rise/Fall Time

CLKOUT V

OL

(Note 1)

CTL_, FSET/SYNC, EN Input High Voltage V

VCC

= 2.35V to 5.5V

CTL_, FSET/SYNC, EN Input Low Voltage V

VCC

= 2.35V to 5.5V

CTL_, FSET/SYNC, EN Input Current

Sinking 1mA

CLKOUT V

OH

Sourcing 1mA

MIN

4.75

4.45

4.75

1.269

44

45

38

38

58

50

100

250

90

245

200

200

2.0

-1

V

VCC

-

0.2V

CLKOUT Rise/Fall Time C

LOAD

= 100pF (Note 1)

TYP

1.280

3

53

50

48

50

20

30

74

67

114

279

107

271

+160

1.8

1.8

0.5

35

26

0.01

V

VCC

-

0.01V

MAX

5.25

5.25

5.25

1.291

0.8

+1

0.1

62

55

58

68

50

50

90

85

135

306

125

296

3.5

3.5

1.6

100

40

UNITS

V

V

V

V mV mV mV

°C

Ω ns mV

µA

µA mV mV mV ns ns

V

V

µA

V

V ns

_______________________________________________________________________________________ 3

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

ELECTRICAL CHARACTERISTICS

(V

VCC

= 3.3V, Circuits of Figures 9–12, T

A

= -40°C to +85°C, unless otherwise noted.) (Note 2)

CONDITIONS PARAMETER

V

CC

Input Voltage Range

V

CC

Input Voltage UVLO

V

DD

Input Voltage UVLO

Output Voltage

Rising or falling

Rising or falling

DC Output Accuracy

Positive Voltage-Margining Shift

Negative Voltage-Margining Shift

FB Input Bias Current

Feedback Transconductance

COMP Discharge Resistance

MAX1960/MAX1962 (measured at FB)

SEL = GND

MAX1961/MAX1962

(FB = V

DD

), measured at output

SEL = REF

SEL not connected

SEL = V

DD

MAX1960/MAX1961

MAX1960/MAX1961

Switching Frequency

In shutdown

FSET/SYNC = GND

FSET/SYNC = V

CC

SYNC Frequency Range

Maximum Duty Cycle

Maximum Duty Cycle

Quiescent Supply Current

Shutdown Supply Current f = 1MHz f = 500kHz

V

DD

Output Voltage

2.7V

≤ V

VCC

≤ 5.5V, I

LOAD

= 1mA to 50mA

2.35V

≤ V

VCC

≤ 2.7V, I

LOAD

= 1mA to 35mA,

C1 = 4.7µF, C6 = 22µF

2.35V

≤ V

VCC

≤ 3.6V with tripler, I

LOAD

= 1mA to 50mA (circuit of Figure 12)

1.789

2.482

3.272

3.8

-3.8

-0.2

1

MIN

2.35

1.95

3.90

0.8

0.795

1.492

4.75

4.45

4.75

450

880

450

80

90

Reference Voltage (No Load)

Positive Current-Limit Threshold

(V

CS

- V

OUT

)

Negative Current-Limit Threshold

(V

OUT

- V

CS

)

CS Bias Current

OUT Bias Current

Current-Limit Threshold (Positive

Direction, Fixed, V

PGND

- V

LX

)

Current-Limit Threshold (Negative

Direction, Fixed, V

LX

- V

PGND

)

Current-Limit Threshold (Positive

Direction, Adjustable, V

PGND

- V

LX

)

MAX1962, V

OUT

= 2V

MAX1962, V

OUT

= 2V

MAX1962, V

CS

= 3.3V

MAX1961/MAX1962, V

OUT

= 3.3V

MAX1960/MAX1961, ILIM = V

DD

MAX1960/MAX1961, ILIM = V

DD

MAX1960/MAX1961, R

ILIM

= 160k

R

ILIM

= 400k

1.267

45

42

58

50

100

250

TYP

85

135

306

64

50

50

90 mV

µA

µA mV mV mV

MAX

5.50

2.3

4.45

UNITS

V

V

V

V

-4.2

+0.2

3

100

550

1120

1200

0.805

1.508

1.809

2.517

3.339

4.2

V

15

15

5.25

5.25

%

%

µA

µS

Ω kHz kHz

%

% mA

µA

V

5.25

1.291

56

V mV

4 _______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

ELECTRICAL CHARACTERISTICS (continued)

(V

VCC

= 3.3V, Circuits of Figures 9–12, T

A

= -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER

Current-Limit Threshold (Negative

Direction, Adjustable, V

LX

- V

PGND

)

DH Gate-Driver On-Resistance

DL Gate-Driver On-Resistance (Pullup)

CONDITIONS

MAX1960/MAX1961, R

ILIM

= 160k

R

ILIM

= 400k

V

BST

- V

LX

= 5V, pulling up or down

DL high state

DL Gate-Driver On-Resistance (Pulldown) DL low state

Minimum high time

FSET/SYNC Pulse Width

Minimum low time

FSET/SYNC Rise/Fall Time

CTL_, FSET/SYNC, EN Input High Voltage V

VCC

= 2.35V to 5.5V

CTL_, FSET/SYNC, EN Input Low Voltage V

VCC

= 2.35V to 5.5V

CTL_, FSET/SYNC, EN Input Current

CLKOUT V

OL

Sinking 1mA

MIN

90

245

200

200

2.0

-1

CLKOUT V

OH

Sourcing 1mA

V

VCC

-

0.2V

CLKOUT Rise/Fall Time C

LOAD

= 100pF

Note 1: Guaranteed by design.

Note 2: Specifications at -40°C are guaranteed by design, and not production tested.

TYP MAX

125

296

3.5

3.5

1.6

100

0.8

+1

0.1

40

UNITS

ns

V

V

µA

V

V mV

Ω ns ns

_______________________________________________________________________________________ 5

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Typical Operating Characteristics

(Circuit of Figure 9, T

A

= +25°C, unless otherwise noted.)

80

70

60

100

EFFICIENCY vs. LOAD CURRENT WITH

15A 1MHz CIRCUIT, 3.3V INPUT

V

OUT

= 2.5V

90

V

OUT

= 1.5V

V

OUT

= 1.8V

80

70

60

100

EFFICIENCY vs. LOAD CURRENT WITH

15A 1MHz CIRCUIT, 5V INPUT

V

OUT

= 3.3V

90

V

OUT

= 2.5V

V

OUT

= 1.8V

V

OUT

= 1.5V

80

70

60

100

EFFICIENCY vs. LOAD CURRENT WITH

15A 500kHz CIRCUIT, 3.3V INPUT

V

OUT

= 2.5V

90

V

OUT

= 1.5V

V

OUT

= 1.8V

50

0.1

80

70

60

50

0.1

1 10

LOAD CURRENT (A)

100

100

EFFICIENCY vs. LOAD CURRENT WITH

15A 500kHz CIRCUIT, 5V INPUT

V

OUT

= 3.3V

90

V

OUT

= 2.5V

V

OUT

= 1.8V

V

OUT

= 1.5V

1 10

LOAD CURRENT (A)

100

FB REGULATION VOLTAGE vs. LOAD CURRENT

50

0.1

1 10

LOAD CURRENT (A)

100

OUTPUT VOLTAGE vs. INPUT VOLTAGE, 1MHz

3.5

3.3V OUTPUT

3.0

2.5

DROPOUT

2.5V OUTPUT

2.0

1.5

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

1.0

0.5

0

2.7

15A LOAD

3.1

3.5

3.9

4.3

INPUT VOLTAGE (V)

4.7

5.1

5.5

0.803

0.802

0.801

0.800

0.799

0.798

0.797

0 5 10

LOAD CURRENT (A)

15 20

1200

1100

1000

900

800

700

600

500

400

3.0

50

0.1

1 10

LOAD CURRENT (A)

100

OUTPUT VOLTAGE vs. INPUT VOLTAGE, 500kHz

3.5

3.3V OUTPUT

3.0

2.5

2.0

DROPOUT

2.5V OUTPUT

1.5

1.0

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

0.5

15A LOAD

0

2.7

3.1

3.5

3.9

4.3

INPUT VOLTAGE (V)

4.7

5.1

5.5

FREQUENCY vs. INPUT VOLTAGE

FSET/SYNC = V

CC

FSET/SYNC = GND

3.5

4.0

4.5

INPUT VOLTAGE (V)

5.0

6 _______________________________________________________________________________________

5.5

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Typical Operating Characteristics (continued)

(Circuit of Figure 9, T

A

= +25°C, unless otherwise noted.)

1100

1000

900

800

700

600

500

400

300

200

100

0

-40

FREQUENCY vs. TEMPERATURE

FSET/SYNC = V

CC

FSET/SYNC = GND

-15 10 35

TEMPERATURE (

°C)

60 85

5.0

4.9

4.8

4.7

5.2

TRIPLER CHARGE-PUMP OUTPUT VOLTAGE

vs. CHARGE-PUMP LOAD CURRENT, 1MHz

5.1

C10, C11, C12 = 0.47

µF

C6 = 2.2

µF

V

IN

= 2.5V

5.2

CHARGE-PUMP OUTPUT VOLTAGE vs. CHARGE-PUMP LOAD CURRENT, 1MHz

5.1

C1 = 0.47

µF

C6 = 2.2

µF

5.0

4.9

4.8

4.7

4.6

4.5

0

V

IN

= 3.3V

V

IN

= 2.5V

50 100 150

CHARGE-PUMP LOAD CURRENT (mA)

200

5.0

4.9

4.8

4.7

5.2

CHARGE-PUMP OUTPUT VOLTAGE vs. CHARGE-PUMP LOAD CURRENT, 500kHz

5.1

5.0

4.9

4.8

4.7

4.6

4.5

0

V

IN

= 2.5V

C1 = 1

µF

C6 = 4.7

µF

V

IN

= 3.3V

50 100 150

CHARGE-PUMP LOAD CURRENT (mA)

200

TRIPLER CHARGE-PUMP OUTPUT VOLTAGE

vs. CHARGE-PUMP LOAD CURRENT, 500kHz

5.2

5.1

C10, C11, C12 = 1

µF

C6 = 4.7

µF

V

IN

= 2.5V

4.6

4.5

0

CIRCUIT OF FIGURE 12

10 20 30 40

CHARGE-PUMP LOAD CURRENT (mA)

50

4.6

4.5

0

CIRCUIT OF FIGURE 12

10 20 30 40

CHARGE-PUMP LOAD CURRENT (mA)

50

MAX1960/MAX1961

CURRENT-LIMIT THRESHOLD

VOLTAGE vs. TEMPERATURE

MAX1962

CURRENT-LIMIT THRESHOLD

VOLTAGE vs. TEMPERATURE

350

300

250

200

150

100

50

0

-40

R

ILIM

= 390k

ILIM = V

DD

-15 10 35

TEMPERATURE (

°C)

60

52.0

51.5

51.0

50.5

50.0

49.5

49.0

48.5

48.0

47.5

47.0

-40

85

-15 10 35

TEMPERATURE (

°C)

60 85

_______________________________________________________________________________________

7

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Typical Operating Characteristics (continued)

(Circuit of Figure 9, T

A

= +25°C, unless otherwise noted.)

7.5A TO 15A TO 7.5A LOAD TRANSIENT

MAX1960 toc16

CTL1

CTL2

VOLTAGE-MARGINING STEP RESPONSE

MAX1960 toc17

5V/div

5V/div

50mV/div

V

OUT

I

IN

200mA/div

I

LOAD

20

µs/div

5A/div

V

OUT

CIRCUIT OF FIGURE 13

50

µs/div

200mV/div

STARTUP/SHUTDOWN WAVEFORMS

MAX1960 toc18

10A/div

10A/div

V

OUT

MAX1960/MAX1961

SHORT-CIRCUIT WAVEFORMS

MAX1960 toc19

CIRCUIT OF FIGURE 13

2V/div

I

IN

I

L

I

L

20A/div

V

OUT

1ms/div

MAX1962

SHORT-CIRCUIT WAVEFORMS

MAX1960 toc20

1V/div

I

IN

10A/div

10A/div

I

L

V

OUT

V

IN

= 5V

V

OUT

= 3.3V

2V/div

50

µs/div

I

IN

DH

MASTER

DL

MASTER

CLKOUT

MASTER/

SYNC

SLAVE

DH

SLAVE

DL

SLAVE

50

µs/div

SYNC TIMING WAVEFORMS

MAX1960 toc21

200ns/div

8 _______________________________________________________________________________________

5A/div

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Pin Description

PIN

MAX1960 MAX1961 MAX1962

NAME

1

2

3

4

5

6

7

8

9

10

11

12

13

14

1

2

3

4

8

5

6

7

9

10

11

12

13

14

1

2

3

4

5

6

7

8

9

10

11

12

13

14

FUNCTION

CLKOUT

Clock Output. Connect to FSET/SYNC of a second converter to operate 180° out-ofphase. CLKOUT swings from V

CC

to GND. CLKOUT is low in shutdown (see the

Operating Frequency and Synchronization section).

FSET/SYNC

Frequency Set and Synchronization. Connect to GND for 500kHz operation, connect to V

CC

for 1MHz operation, or drive with clock signal to synchronize

(between 450kHz and 1200kHz).

ILIM

EN

SEL

N.C.

OUT

Current Limit. Connect a resistor from ILIM to GND to set the current-sense threshold voltage. Connect ILIM to V

DD

to select the default threshold of 75mV.

E nab l e. D r i ve hi g h for nor m al op er ati on. D r i ve l ow or connect to GN D for shutd ow n m od e.

Preset Output Voltage Select. Allows the output to be set to one of four preset voltages (1.5V, 1.8V, 2.5V, and 3.3V). For the MAX1962, FB must be connected to

V

DD

if SEL is to be used (see the Setting the Output Voltage section).

No Connection. Not internally connected.

Output. Connect to the output. Used to sense the output voltage for internal feedback and current sense.

CTL1

CTL2

CS

AV

COMP

REF

GND

V

DD

FB

DD

DL

PGND

Control Pins. Controls voltage margining and shutdown. Connect both CTL1 and

CTL2 high for normal operation. Connect both CTL1 and CTL2 low for shutdown.

Connect CTL1 high and CTL2 low for +4% voltage margining. Connect CTL1 low and CTL2 high for -4% voltage margining. If voltage margining is not to be used, connect CTL1 and CTL2 together and use to enable/shutdown the device.

C ur r ent- S ense Inp ut. C onnect to the j uncti on of the cur r ent- sense r esi stor and the i nd uctor . The M AX 1962 cur r ent- sense thr eshol d i s 50m V m easur ed fr om C S to O U T.

Filtered Supply from V

DD

. Connect a 1µF bypass capacitor. AV

DD

is forced to V

CC in shutdown. Do not apply an external load to AV

DD

.

Feed b ack Inp ut. The feed b ack thr eshol d i s 0.8V . C onnect to the center of a r esi sti ve vol tag e- d i vi d er fr om the outp ut to GN D to set the outp ut vol tag e to 0.8V or g r eater . On the M AX 1962, connect FB to V

DD

to sel ect p r eset outp ut vol tag es ( see S E L) .

Compensation Pin. COMP is forced to GND in shutdown, UVLO, or thermal fault.

Reference Output. V

REF

= 1.28V. Bypass with a 0.22µF capacitor to GND.

Analog Ground. Connect to the PC board analog ground plane. Connect the PC board analog ground plane and power ground planes with a single connection.

C har g e- P um p O utp ut. P r ovi d es r eg ul ated 5V to p ow er the IC and g ate d r i ver s.

Byp ass w i th a 4.7µF cer am i c cap aci tor for op er ati ng fr eq uenci es b etw een 450kH z and 950kH z. Byp ass w i th a 2.2µF cer am i c cap aci tor for 1M H z op er ati on. V

DD

i s i nter nal l y for ced to V

CC

i n shutd ow n. D o not ap p l y an exter nal l oad to V

DD

.

Low-Side MOSFET Synchronous Rectifier Gate-Driver Output. DL is high in shutdown.

Power Ground. Connect to the PC board power ground plane.

_______________________________________________________________________________________ 9

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Pin Description (continued)

PIN

MAX1960 MAX1961 MAX1962

15 15 15

NAME

C-

FUNCTION

16

17

18

19

20

16

17

18

19

20

16

17

18

19

20

C+

V

CC

BST

DH

LX

Charge-Pump Flying Capacitor Negative Connection. Use a 0.47µF ceramic capacitor at 1MHz, and 1µF between 450kHz and 950kHz.

Charge-Pump Flying Capacitor Positive Connection. Use a 0.47µF ceramic capacitor at 1MHz and 1µF between 450kHz and 950kHz.

Input Supply to Charge Pump

Boost Capacitor Connection. Connect a 0.1µF ceramic capacitor from BST to LX.

High-Side MOSFET Gate-Driver Output. DH is low in shutdown.

Inductor Connection

Detailed Description

The MAX1960/MAX1961/MAX1962 are high-current, high-efficiency voltage-mode step-down DC-DC controllers that operate from 2.35V to 5.5V input and generate adjustable voltages down to 0.8V at up to 20A. An on-chip charge pump generates a regulated 5V for driving a variety of external N-channel MOSFETs.

Constant frequency PWM operation and external synchronization make these controllers suitable for telecom and datacom applications. The operating frequency is programmed externally to either 500kHz or 1MHz, or from 450kHz to 1.2MHz with an external clock. A clock output is provided to synchronize another converter for

180° out-of-phase operation.

A high closed-loop bandwidth provides excellent transient response for applications with dynamic loads.

Internal Charge Pump

An on-chip regulated charge pump develops 5V at

50mA (max) with input voltages as low as 2.35V. The output of this charge pump provides power for the internal circuitry, bias for the low-side driver (DL), and the bias for the boost diode, which supplies the highside MOSFET gate driver (DH). The charge pump is synchronized with the DL driver signal and operates at

1/2 the PWM frequency.

The external MOSFET gate charge is the dominant load for the charge pump and is proportional to the PWM switching frequency. The charge pump must supply chip-operating current plus adequate gate current for both MOSFETs at the selected operating frequency.

The required charge-pump output current is given by the formula:

I

TOTAL

= I

AVDD

+ f

OSC

(Q

G1

+ Q

G2

) where I

AVDD is the current supplied to the IC through

AV

DD

(typically 2mA), f

OSC is the PWM switching frequency, Q

G1 is the gate charge of the high-side

MOSFET, and Q

G2 is the gate charge of the low-side

MOSFET. The MOSFETs must be chosen such that

I

TOTAL does not exceed 50mA. For example, with 1MHz operation, Q

G1

+ Q

G2 should be less than 48nC.

Voltage Margining and Shutdown

The voltage-margining feature on the MAX1960/

MAX1961 shifts the output voltage up or down by 4%.

This is useful for the automatic testing of systems at high and low supply conditions to find potential hardware failures. CTL1 and CTL2 control voltage margining as outlined in Table 1.

A shutdown feature is included on all three parts, which stops switching the output drivers and the charge pump, reducing the supply current to less than 15µA.

For the MAX1962, drive EN high for normal operation, or low for shutdown. For the MAX1960/MAX1961, drive both CTL1 and CTL2 high for normal operation, or drive

CTL1 and CTL2 low for shutdown. For a simple enable/shutdown function with no voltage margining, connect CTL1 and CTL2 together and drive as one input.

Table 1. Voltage Margining Truth Table

CTL1

High

High

Low

Low

CTL2

High

Low

High

Low

FUNCTION

Normal operation

+4% output-voltage shift

-4% output-voltage shift

Shutdown

10 ______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

ILIM

(MAX1960/MAX1961)

CLKOUT

FSET/SYNC

OSC

OUT

CURRENT

SENSE

UVLO

LX

PGND

S

Q DH

LX

CS

(MAX1962)

BST

OSC

V

DD

COMP R

Q

COMP

OUT

(MAX1961/MAX1962)

DL

PGND

FB

(MAX1960/MAX1962)

VSEL

(MAX1961/MAX1962)

CTL1

(MAX1960/MAX1961)

CTL2

(MAX1960/MAX1961)

EN

(MAX1962)

FEEDBACK

SELECT

SHUTDOWN

AND VOLTAGE

MARGINING

ERROR

AMP

MAX1960/

MAX1961/

MAX1962

SOFT-START

DAC

OSC

CHARGE

PUMP

REF

AV

DD

REF

V

DD

C+

C-

V

CC

GND

Figure 1. Functional Diagram

MOSFET Gate Drivers

The DH and DL drivers are designed to drive logic-level

N-channel MOSFETs to optimize system cost and efficiency. MOSFETs with R

DSON rated at V

GS

4.5V are recommended. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the

MOSFET gate for the adaptive dead-time circuit to work properly. Otherwise, the internal sense circuitry could interpret the MOSFET gate as “off” while there is actually still charge left on the gate. Use very short, wide traces measuring no more than 20 squares (50mils to 100mils wide if the MOSFET is 1in from the IC).

Undervoltage Lockout and Soft-Start

There are two undervoltage lockout (UVLO) circuits on the MAX1960/MAX1961/MAX1962. The first UVLO circuit monitors V

CC

, which must be above 2.15V (typ) in order for the charge pump to operate. The second

UVLO circuit monitors the output of the charge pump.

The charge-pump output, V

DD

, must be above 4.2V

(typ) in order for the PWM converter to operate. Both

UVLO circuits inhibit switching and force DL high and DH low when either V

CC or V

DD are below their threshold.

When the monitored voltages are above their thresholds, an internal soft-start timer ramps up the erroramplifier reference voltage. The ramp occurs in eighty

10mV steps. Full output voltage is reached 1.28ms after activation with a 1MHz operating frequency.

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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Operating Frequency and Synchronization

The MAX1960/MAX1961/MAX1962 operating frequency is set externally to either 500kHz or 1MHz. For 500kHz operation, connect FSET/SYNC to GND, or for 1MHz operation, connect FSET/SYNC to V

DD

. Alternately, an external clock from 450kHz to 1.2MHz can be applied to SYNC.

A clock output (CLKOUT) that is 180° out-of-phase with the internal clock is also provided. This allows a second converter to be synchronized, and operate 180° out-ofphase with the first. To do this, simply connect CLKOUT of the first converter to FSET/SYNC of the second converter. The first converter can be set internally to 500kHz or 1MHz for this mode of operation. When the first converter is synchronized to an external clock, CLKOUT is the inverse of external clock. See the SYNC Timing

Waveform in the Typical Operating Characteristics.

Lossless Current Limit

(MAX1960/MAX1961)

To prevent damage in the case of excessive load current or a short circuit, the MAX1960/MAX1961 use the low-side MOSFET’s on-resistance (R

DS(ON)

) for current sensing. The current is monitored during the on-time of the low-side MOSFET. If the current-sense voltage

(V

PGND

- V

LX

) rises above the current-limit threshold for more than 128 clock cycles, the controller turns off. The controller remains off until the input voltage is removed or the device is re-enabled with CTL1 and CTL2 (see the Setting the Current Limit section).

Current-Sense Resistor (MAX1962)

The MAX1962 uses a standard current-sense resistor in series with the inductor for a 10% accurate current-limit measurement. The current-sense threshold is 50mV. This provides accurate current sensing at all duty cycles without relying on MOSFET on-resistance. CS connects to the high-side (inductor side) of the current-sense resistor and OUT connects to the low-side (output side) of the current-sense resistor.

The current-sense resistor for the MAX1962 may also be replaced with a series RC network across the inductor.

This method uses the parasitic resistance of the inductor for current sensing. This method is less accurate than using a current-sense resistor, but is lower cost and provides slightly higher efficiency. See the Design

Procedure section for instructions on using this method.

Dropout Performance

The MAX1960/MAX1961/MAX1962 enter dropout when the input voltage is not sufficiently high to maintain output regulation. As input voltage is lowered, the duty cycle increases until it reaches its maximum value, where the part enters dropout. With a switching frequency of

1MHz, the maximum duty cycle is about 83%. At

500kHz, the duty cycle can increase to about 92%, resulting in a lower dropout voltage. The duty cycle is dependent on the input voltage (V

IN

), the output voltage (V

OUT

), and the parasitic voltage drops in the

MOSFETs and the inductor (V

DROP(N1)

, V

DROP(N2)

,

V

DROP(L)

). Note that V

DROP(L) includes the voltage drop due to the inductor’s resistance, the drop across the current-sense resistor (if used), and any other resistive voltage drop from the LX switching node to the point where the output voltage is sensed. The duty cycle is found from:

D

=

V

OUT

+

V

V

IN

V

DROP N 1 )

V

DROP N 2 )

Adaptive Dead Time

The MAX1960/MAX1961/MAX1962 DL and DH MOSFET drivers have an adaptive dead-time circuit to prevent shoot-through current caused by high- and low-side

MOSFET overlap. This allows a wide variety of MOSFETs to be used without matching FET dynamic characteristics. The DL driver will not go high until DH drives the high-side MOSFET gate to within 1V of its source (LX).

The DH output will not go high until DL drives the low-side

MOSFET gate to within 1V of ground.

Design Procedure

Component selection is primarily dictated by the following criteria:

Input voltage range. The maximum value

(V

IN(MAX)

) must accommodate the worst-case high input voltage. The minimum value (V

IN(MIN)

) must account for the lowest input voltage after drops due to connectors, fuses, and selector switches are considered.

Maximum load current. There are two values to consider: The peak load current (I

LOAD(MAX)

) determines the instantaneous component stresses and filtering requirements and is key in determining output capacitor requirements. I

LOAD(MAX) also determines the inductor saturation rating and the design of the current-limit circuit. The continuous load current (I

LOAD

) determines the thermal stresses and is key in determining input capacitor requirements, MOSFET requirements, as well as those of other critical heatcontributing components.

12 ______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Inductor operating point. This choice provides tradeoffs between size, transient response, and efficiency. Choosing higher inductance values results in lower inductor ripple current, lower peak current, lower switching losses, and, therefore, higher efficiency at the cost of slower transient response and larger size. Choosing lower inductance values results in large ripple currents, smaller size, and poorer efficiency, but have faster transient response.

Setting the Output Voltage

The MAX1961 has four output voltage presets selected by SEL. Table 2 shows how each of the preset voltages are selected. The MAX1962 also has four preset output voltages, but also is adjustable down to 0.8V. To use the preset voltages on the MAX1962, FB must be connected to V

DD

. SEL then selects the output voltage as shown in

Table 2.

Both the MAX1960/MAX1962 feature an adjustable output that can be set down to 0.8V. To set voltages greater than 0.8V, Connect FB to a resistor-divider from the output (Figures 9 and 11). Use a resistor up to 10k

Ω for R2 and select R1 according to the following equation:

R 1

=

R 2

×



V

OUT

V

FB

1

 where the feedback threshold, V

FB

= 0.8V, and V

OUT is the output voltage.

Input Voltage Range

The MAX1960/MAX1961/MAX1962 have an input voltage range of 2.35V to 5.5V but cannot operate at both extremes with one application circuit. The standard charge-pump doubler application circuit operates with an input range of 2.7V to 5.5V (Figures 9, 10, and 11).

In order to operate down to 2.35V, the charge pump must be configured as a tripler. This circuit, however, limits the maximum input voltage to 3.6V. The schematic for the tripler charge pump is shown in Figure 2. Note that the flying capacitor between C+ and C- has been removed and C+ is not connected.

Inductor Selection

Determine an appropriate inductor value with the following equation:

L

=

V

OUT

×

V

IN

× f

OSC

V

IN

×

V

OUT

LIR

×

I

LOAD MAX )

The inductor current ripple, LIR, is the ratio of peak-topeak inductor ripple current to the average continuous inductor current. An LIR between 20% and 40% pro-

Table 2. Preset Voltages—

MAX1961/MAX1962

PRESET OUTPUT VOLTAGE

1.5V

1.8V

2.5V

3.3V

SEL

GND

REF

No connection

V

DD

D2

V

CC

MAX1960/

MAX1961/

MAX1962

C-

C+

V

DD

C10

AV

DD

C10, C11, C12

C6

500kHz

1

µF

4.7

µF

D3

C11

R5

10

C4

1

µF

D4

C12

1MHz

0.47

µF

2.2

µF

Figure 2. Tripler Charge-Pump Configuration.

C6

D5 vides a good compromise between efficiency and economy. Choose a low-loss inductor having the lowest possible DC resistance. Ferrite core type inductors are often the best choice for performance. The inductor saturation current rating must exceed I

PEAK

:

I

PEAK

=

I

LOAD MAX )



LIR

2



×

I

LOAD MAX )

Setting the Current Limit

Lossless Current Limit (MAX1960/MAX1961)

The MAX1960/MAX1961 use the low-side MOSFET’s onresistance (R

DS(ON)

) for current sensing. This method of current limit sets the maximum value of the inductor’s

“valley” current (Figure 3). If the inductor current is higher than the valley current-limit setting at the end of the clock period, the controller skips the DH pulse. When the first current-limit event is detected, the controller initi-

______________________________________________________________________________________ 13

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

I

PEAK

I

LOAD

I

VALLEY

DH

LX

MAX1962

DL

R

L

0.22

µH, 2.8mW,

I

LIMIT

= 18A

L

R

R = 33

C

C = 4.7

µF

CS

OUT

TIME

Figure 3. Inductor Current Waveform

ates a 128 clock cycle counter. If the current limit is present at the end of this count, the controller remains off until the input voltage is removed and re-applied, or the device is re-enabled with CTL1 and CTL2. The 128-cycle counter is reset when four successive DH pulses are observed, without activating the current limit.

At maximum load, the low excursion of inductor current,

I

VALLEY(MAX)

, is:

I

VALLEY MAX )

=

I

LOAD MAX )

-



LIR

2



×

I

LOAD MAX )

The current-limit threshold (V

CLT

) is set by connecting a resistor (R

ILIM

) from ILIM to GND. The range for this resistor is 100k

Ω to 400kΩ. Set current-limit threshold as follows:

V

CLT

= R

ILIM

× 0.714µA

Connecting ILIM to V

DD sets the threshold to a default value of 75mV.

To prevent the current limit from falsely triggering, V

CLT divided by the low-side MOSFET R

DS(ON) must exceed the maximum value of I

VALLEY

. The maximum value of low-side MOSFET R

DS(ON) should be used:

V

CLT

> R

DS(ON)MAX x I

VALLEY(MAX)

A limitation of sensing current across MOSFET on-resistance is that the MOSFET on-resistance varies significantly from MOSFET to MOSFET and over temperature.

Consequently, this current-sensing method may not be suitable if a precise current limit is required. If better

Figure 4. Using the Inductor Resistance as a Current-Sense

Resistor with the MAX1962

accuracy is needed, use the MAX1962 with a currentsense resistor.

Current-Sense Resistor (MAX1962)

The MAX1962 uses a current-sense resistor connected from the inductor to the output with Kelvin sense connections. The current-sense voltage is measured from CS to

OUT, and has a fixed threshold of 50mV. The MAX1962 current limit is triggered when the peak voltage across the current-sense resistor, I

PEAK

× R

SENSE

, exceeds

50mV. Once current sense is triggered, the controller does not turn off, but continues to operate at the current limit. This method of current sensing is more precise due to the accuracy of the current-sense resistor. The cost of this precision is that it requires an extra component and is slightly less efficient due to the loss in the currentsense resistance.

Inductor Resistance Current Sense (MAX1962)

Alternately, the inductor resistance can be used to sense current in place of a current-sense resistor. To do this, connect a series RC network in parallel with the inductor (Figure 4). Choose a resistor value less than

40

Ω to avoid offsets due to CS input current. Calculate the capacitor value from the formula C = 2L / (R

L

× R).

The effective current-sense resistance (R

SENSE

) equals

R

L

. Current-sense accuracy then depends on the accuracy of the inductor resistance. Note that the currentsense signal is delayed due to the RC filter time constant. Consequently, inductor current may overshoot (by as much as 2x) when a fast short occurs.

14 ______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Output Capacitor Selection

The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load transient requirements. In addition, the capacitance value must be high enough to absorb the inductor energy during load steps.

In applications where the output is subject to large load transients, low ESR is needed to prevent the output from dipping too low (V

DIP

) during a load step:

R

ESR

V

DIP

I

LOADSTEP MAX )

In applications with less severe load steps, maximum

ESR may be governed by what is needed to maintain acceptable output voltage ripple:

R

ESR

V

( )

LIR

×

I

LOAD MAX )

To satisfy both load step and ripple requirements, select the lowest value from the above two equations.

The capacitor is usually selected by physical size, ESR, and voltage rating, rather than by capacitance value.

With current tantalum, electrolytic, and polymer capacitor technology, the bulk capacitance will also be sufficient once the ESR requirement is satisfied.

When using low-capacity filter capacitors such as ceramic, capacitor size is usually determined by the capacitance needed to prevent voltage undershoot and overshoot during load transients. The overshoot voltage (V

SOAR

) is given by:

V

SOAR

=

2

×

L

×

(

I

PEAK

V

OUT

×

)

2

C

OUT

Generally, once enough capacitance is in place to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem.

Input Capacitor Selection

The input capacitor (C

IN

) reduces the current peaks drawn from the input supply and reduces noise injection. The source impedance to the input supply largely determines the value of C

IN

. High source impedance requires high input capacitance. The input capacitor must meet the ripple current requirement (I

RMS

) imposed by the switching currents.

The RMS input ripple current is given by:

I

RMS

=

I

LOAD

×

V

OUT

× (

V

IN

V

OUT

)

V

IN

For optimal circuit reliability, choose a capacitor that has less than 10°C temperature rise at the peak ripple current.

Compensation and Stability

Compensation with Ceramic Output Capacitors

The high switching frequency range of the

MAX1960/MAX1961/MAX1962 allows the use of ceramic output capacitors. Since the ESR of ceramic capacitors is very low typically, the frequency of the associated transfer function zero is higher than the unity-gain crossover frequency and the zero cannot be used to compensate for the double pole created by the output inductor and capacitor. The solution is Type 3 compensation (Figure 5), which takes advantage of local feedback to create two zeros and three poles (Figure 6). The frequency of the poles and zeros are described below:

f

P1

=

0 f

P2

=

1

2

×

R 2

×

C 3 f

P3

=

2

×

R 1

×

1

C 1

C 1

×

+

C 2

C 2 f

LC

=

2

π

L

0

1

×

C

0 f

Z1

=

1

2

×

R 1

×

C 1 f

Z2

=

1

2

π ×

( R 2

+

R 3 )

×

C 3 f

ZESR

=

2

1

R

ESR

Unity-gain crossover frequency:

×

C

0 f

0

=

R 1

×

C 3

×

V

IN MAX )

V

RAMP

×

2

π

1

×

L

0

×

C

0

______________________________________________________________________________________ 15

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

V

IN

L

O

V

OUT

GAIN (dB)

DH

LX

DL

MAX1960

FB

C

0

R3

R2

C3

R4

R1

COMP fz1 fz2 fp2 fp3

FREQUENCY fp1

C2 C1

Figure 5. Type 3 Compensation Network

where:

V

IN(MAX)

= Maximum input voltage

V

RAMP

= Oscillator ramp voltage = 0.85 x 10

6

/f

S

, where f

S

= switching frequency

L

O

= Output inductance

C

O

= Output capacitance

The goal is to place the two zeros below crossover and the two poles above crossover so that crossover occurs with a single-pole slope. The compensation procedure is as follows:

Select the crossover frequency such that: f

0

< f

ZESR and f

0

<1/5

✕ f

S

Select R1 such that:

R 1

>>

2 g mEA where g mEA

= 2mS.

Place the first zero before the double pole:

C 1

2

×

0 75

1

× f

LC

×

R 1

Place the third pole at half the switching frequency:

C 2

2

×

0 5

1

× f

S

×

R 1

Figure 6. Transfer Function for Type 3 Compensation

If C2 < 10pF, it can be omitted.

C 3

2

× f

0

×

L

R

0

1

×

×

V

C

IN

0

×

V

RAMP

Place the second pole after the ESR zero:

R 2

1

2

× f

ZESR

×

C 3

If:

R 2

<

1 g

M

(

=

550

), increase R1 and recalculate C1, C2, and C3.

Place the second zero at the double-pole frequency:

R 3

1

2

× f

LC

×

C 3

R 2

Set the output voltage:

R 4

=

V

FB

V

OUT

V

FB

×

R 3 , V

FB

=

16 ______________________________________________________________________________________

.

V

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Compensation with Electrolytic Output Capacitors

The MAX1960/MAX1961/MAX1962 use a voltage-mode control scheme that regulates the output voltage by comparing the error-amplifier output (COMP) with a fixed internal ramp to produce the required duty cycle.

The inductor and output capacitor create a double pole at the resonant frequency, which has gain drop of 40dB per decade, and phase shift of 180

°. The error amplifier must compensate for this gain drop and phase shift in order to achieve a stable high-bandwidth, closed-loop system.

The basic regulator loop consists of a power modulator, an output feedback divider and an error amplifier. The power modulator has DC gain set by V

IN

/V

RAMP

, with a double pole set by the inductor and output capacitor, and a single zero set by the output capacitor (C

O

) and its equivalent series resistance (ESR). Below are equations that define the power modulator:

The DC gain of the power modulator is:

G

MOD DC )

=

V

IN

V

RAMP where V

RAMP

= 0.85

× 10

6

/ f

S

. The pole frequency due to the inductor and output capacitor is: f

PMOD

=

2

π

1

L C

O

The zero frequency due to the output capacitor’s ESR is: f

ZESR

=

2

×

1

R

ESR

×

C

O

The output capacitor is usually comprised of several same value capacitors connected in parallel. With n capacitors in parallel, the output capacitance is:

C

O

= ×

C

EACH

The total ESR is:

R

ESR

=

R

ESR EACH ) n

The ESR zero (f

ZESR

) for a parallel combination of capacitors is the same as for an individual capacitor.

The feedback divider has a gain of G

FB

= V

FB

/V

OUT

, where V

FB is 0.8V.

The transconductance error amplifier has DC gain

GEA(dc) of 80dB. A dominant pole is set by the compensation capacitor (C

C

), the amplifier output resistance (R

O

), and the compensation resistor (R

C

): f

PEA

=

2

1

×

C

C

×

R

0

+

R

C

)

A zero is set by the compensation resistor and the compensation capacitor: f

ZEA

=

1

2

×

C

C

×

R

C

The total closed-loop gain must equal to unity at the crossover frequency, where the crossover frequency should be higher than f

ZESR

, so that the -1 slope is used to cross over at unity gain. Also, the crossover frequency should be less than or equal to 1/5 the switching frequency.

f

ZESR

< f

C

≤ f

S

5

The loop-gain equation at the crossover frequency is:

V

FB

V

OUT

×

G

×

G

=1 where:

G

= g mEA

×

R

C and:

G

=

G

MOD DC )

× f

( f

PMOD

ESR

×

) 2 f

C

The compensation resistor, R

C

, is calculated from:

R

C

= g mEA

×

V

V

OUT

FB

×

G where g mEA

= 2mS.

Due to the under-damped (Q > 1) nature of the output

LC double pole, the error-amplifier compensation zero should be approximately 0.2f

PMOD phase boost. C

C is calculated from: to provide good

C

C

=

2

π

5

×

R

C

× f

PMOD

______________________________________________________________________________________ 17

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

A small capacitor C

F

, can also be added from COMP to

GND to provide high-frequency decoupling. C

F will add another high-frequency pole (f

PHF

) to the error-amplifier response. This pole should be greater than 100 times the error-amplifier zero frequency to have negligible impact on the phase margin. This pole should also be less than half the switching frequency for effective decoupling:

100f

ZEA

< f

PHF

< 0.5f

S

Select a value for f

PHF in the range given above, then solve for C

F using the following equation:

C

F

=

1

2

×

R

C

× f

PHF

Below is a numerical example to calculate compensation values:

V

IN

= 3.3V

V

RAMP

= 0.85V

V

OUT

= 1.8V

V

FB

= 0.8V

I

OUT(max)

= 15A

C

O

= 2 x 680µF = 1360µF

ESR = 0.008

Ω / 2 = 0.004Ω

L

O

= 0.22µH g mEA

= 2mS f

S

= 1MHz f

PMOD

=

2

π ×

1

L

O

×

C

O

=

2

π ×

=

9 201 kHz

.

10

1

6

×

1360

×

10

6 f

ZESR

=

=

=

2

π ×

C

1

O

×

R

ESR

2

π ×

.

kHz

1

1360

×

10

6

0 004

Choose the crossover frequency (f

C

) in the range f

ZESR

< f

C

< f

S

/5:

29.3kHz < f

C

< 200kHz

Select f

C

= 100kHz, this meets the criteria above, and the bandwidth is high enough for good transient response.

The power modulator gain at f

C is:

G

=

V

IN

V

RAMP

=

3

×

× f

( f

PMOD

ZESR

×

)

2 f

C

.

k

( 9201 )

2

Ω ×

100 k

=

Choose R

1

= 8.06k

Ω, then R

2

= 10k

Ω (see the Setting

the Output Voltage section):

C

= g mEA

=

11 k

×

V

V

OUT

FB

×

G

=

.

×

.

×

.

C

C

=

2

π

5

×

R

C

× f

PMOD

=

5

2

π ×

11 k

Ω ×

9201

=

7863 pF

Select C

C

= 8200pF (nearest standard capacitor value).

Select f

PHF in the range 100f

ZEA

< f

PHF

< 0.5f

S

.

184kHz < f

PHF

< 500kHz

Select f

PHF

= 250kHz, then solve for C

F

:

C

F

=

2

π

1

×

R

C

× f

PHF

=

2

π ×

11 k

1

×

250 kHz

=

58 pF

Select the nearest standard capacitor value C

F

= 56pF.

Summary of feedback divider and compensation components:

R

1

= 8.06k

R

2

= 10k

R

C

= 11k

C

C

= 8200pF

C

F

= 56pF include:

Power MOSFET Selection

When selecting a MOSFET, essential parameters

(1) Total gate charge (Q

G

)

(2) Reverse transfer capacitance (C

RSS

)

(3) On-resistance (R

DS(ON)

)

(4) Gate threshold voltage (V

TH(MIN)

)

(5) Turn-on/turn-off times

(6) Turn-on/turn-off delays

18 ______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

ERROR AMPLIFIER MODULATOR OUTPUT FILTER FEEDBACK DIVIDER

V

1

R1

0.8V

V

IN

/V

RAMP

Gm

R2 R3

C9

R

S

L1

R

ESR

C

OUT

V

2

R

LOAD

Figure 7. Open-Loop Transfer Model

At high switching rates, dynamic characteristics (parameters 1, 2, 5, and 6) that predict switching losses may have more impact on efficiency than R

DS(ON)

, which predicts DC losses. Q

G includes all capacitance associated with charging the gate, and best performance is achieved with a low total gate charge. Q

G also helps predict the current needed to drive the gate at the selected operating frequency. This is very important because the output current from the charge pump is finite (50mA, max) and is used to drive the gates of the

MOSFETs as well as provide bias for the IC. R

DS(ON) is important as well, as it is used for current sensing in the

MAX1960/MAX1961. R

DS(ON) also causes power dissipation during the on-time of the MOSFET.

Choose Q

G to be as low as possible. Ensure that:

Q

G 1

+

Q

G 2

50 mA f

S

Choose R

DS(ON) to provide the desired I

LOAD(MAX) at the desired current-limit threshold voltage (see the

Setting the Current Limit section).

MOSFET RC Snubber Circuit

Fast-switching transitions can cause ringing due to resonating circuit parasitic inductance and capacitance at the switching nodes. This high-frequency ringing occurs at LX rising and falling transitions, and may introduce current-sensing errors and generate EMI. To dampen this ringing, a series RC snubber circuit can be added across each MOSFET switch (Figure 8).

Typical values for the snubber components are C

SNUB

= 4700pF and R

SNUB

= 1

Ω, however, the ideal values for snubber components will depend on circuit parasitics. Below is the procedure for selecting the component values of the series RC snubber circuit:

1) Connect a scope probe to measure V

LX to GND, and observe the ringing frequency, f

R

.

2) Find the capacitor value (connected from LX to

GND) that reduces the ringing frequency by half.

3) The circuit parasitic capacitance, C

PAR

, at LX is then equal to 1/3 of the value of the added capacitance above.

______________________________________________________________________________________ 19

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

DH

MAX1960

LX

DL

PGND

INPUT

N1

N2

R

SNUB

C

SNUB

L1

R

SNUB

C

SNUB

Figure 8. RC Snubber Circuit

4) The circuit parasitic inductance, L

PAR

, is calculated by:

L

PAR

=

1

( 2

π × f

R

)

×

C

PAR

5) The resistor for critical dampening, R

SNUB

= 2

π x f

R x L

PAR

. The resistor value can be adjusted up or down to tailor the desired damping and the peak voltage excursion.

6) The capacitor, C

SNUB

, should be at least 2 to 4 times the value of the C

PAR to be effective.

7) The snubber circuit power loss is dissipated in the resistor, P

RSNUB

, and can be calculated as:

P RSNUB

=

C

SNUB

×

( V

IN

)

× f

S where V

IN is the input voltage, and f

S is the switching frequency. Choose R

SNUB power rating that exceeds the calculated power dissipation.

MOSFET Power Dissipation

Worst-case power dissipation occurs at duty factor extremes. For the high-side MOSFET, the worst-case power dissipation due to resistance occurs at minimum input voltage (V

IN(MIN)

):

PD

( 1 )

=

V

OUT

V

IN MIN )

×

I

LOAD

2

×

R

DS ON )

The following formula calculates switching losses for the high-side MOSFET, but is only an approximation and not a substitute for evaluation:

P

1 )

=

(

I

L PEAK )

× t

FALL

+

I

L VALLEY )

× t

RISE

)

×

V

IN MAX )

2

× f

S where V

IN(MAX) is the maximum value of the input voltage, t

FALL and t

RISE are the fall and rise time of the

MOSFET, I

L(PEAK) and I

L(VALLEY) are the maximum peak and valley inductor current, and f

S is the PWM switching frequency:

I

L(PEAK)

= I

OUT(MAX)

× (1 + 0.5 × LIR) and I

L(VALLEY)

=

I

OUT(MAX)

× (1 - 0.5 × LIR) where LIR is the peak-to-peak inductor ripple current divided by the load current.

The total power dissipation in the high-side MOSFET is the sum of these two power losses:

P

D(N1)

= P

D(N1RESISTIVE)

+ P

D(N1SWITCHING)

For the low-side MOSFET, the worst-case power dissipation occurs at maximum input voltage:

P

2 )

=

1 -

V

OUT

V

IN MAX )

 × I

LOAD

2

×

R

DS ON )

Applications Information

PC Board Layout Guidelines

A properly designed PC board layout is important in any switching DC-DC converter circuit. If possible, mount the MOSFETs, inductor, input/output capacitors, and current-sense resistor on the top side. Connect the ground for these devices close together on a powerground trace. Make all other ground connections to a separate analog ground plane. Connect the analog ground plane to power ground at a single point.

To help dissipate heat, place high-power components

(MOSFETs, inductor, and current-sense resistor) on a large PC board area. Keep high-current traces short and wide to reduce the resistance in these traces. Also make the gate drive connections (DH and DL) short and wide, measuring 10 to 20 squares (50mils to 100mils wide if the

MOSFET is 1in from the controller IC).

For the MAX1960/MAX1961, connect LX and PGND to the low-side MOSFET using Kelvin sense connections.

For the MAX1962, connect CS and OUT to the currentsense resistor using Kelvin sense connections.

Place the REF capacitor, the BST diode and capacitor, and the charge-pump components as close as possible to the IC. If the IC is far from the input capacitors, bypass

V

CC to GND with a 0.1

µF or greater ceramic capacitor close to the V

CC pin.

For an example PC board layout, see the MAX1960 evaluation kit.

20 ______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Table 3. Component List for Application Circuits

PART

C1

C2

C3

C4

C5

C6

C8

C9

C10, C11, C12

C13, C14

D1

D2–D5

L1

N1

N2

R1

R2

R3

R4

R5

R6

R7, R8

APP. CIRCUIT

1, 2, 3

1, 2, 3, 4

1, 2, 3, 4

1, 2, 3, 4

1, 2, 3, 4

1, 2, 3, 4

1, 2, 3, 4

1, 2, 3, 4

4

1, 2, 3, 4

1, 2, 3, 4

15A OUTPUT 1MHz

0.47µF ceramic capacitor

5

× 10µF ceramic capacitors

2 x 680µF POSCAPs Sanyo 2R5TPD680M8

1µF ceramic capacitor

0.1µF ceramic capacitor

2.2µF ceramic capacitor

0.22µF ceramic capacitor

(Table 4)

0.47µF ceramic capacitors

4700pF ceramic capacitors

Schottky diode

Central CMSSH-3

4

1, 2, 3, 4

1, 2, 3, 4

1, 2, 3, 4

1, 3

1, 3

1, 2, 3, 4

1, 2

1, 2, 3, 4

3, 4

1, 2, 3, 4

Schottky diodes

Central CMHSH5-2L

0.22µH, 1.7m

Ω inductor

Sumida CDEP1040R2NC-50

N-channel MOSFET

International Rectifier IRLR7821

N-channel MOSFET

International Rectifier IRLR7833

Sets output voltage

10k

Ω ±1% resistor

(Table 4)

390k

Ω ±5% resistor

10

Ω ±5% resistor

1.5m

Ω ±5%, 1W resistor

Panasonic ERJM1WTJ1M5U

1

Ω ±5% resistors

15A OUTPUT 500kHz

1µF ceramic capacitor

5

× 10µF ceramic capacitors

2 x 680

µF POSCAPs Sanyo 2R5TPD680M8

1µF ceramic capacitor

0.1µF ceramic capacitor

4.7µF ceramic capacitor

0.22µF ceramic capacitor

(Table 5)

1µF ceramic capacitors

4700pF ceramic capacitors

Schottky diode

Central CMSSH-3

Schottky diodes

Central CMHSH5-2L

0.45µH inductor

Sumida CDEP1040R4MC-50

N-channel MOSFET

International Rectifier IRLR7821

N-channel MOSFET

International Rectifier IRLR7833

Sets output voltage

10k

Ω ±1% resistor

(Table 5)

390k

Ω ±5% resistor

10

Ω ±5% resistor

1.5m

Ω ±5%, 1W resistor

Panasonic ERJM1WTJ1M5U

1

Ω ±5% resistors

______________________________________________________________________________________ 21

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Table 4. R1, R3, and C9 Component Values for 1MHz Operation

V

IN

5V

3.3V

2.5V

V

OUT

= 3.3V

V

OUT

= 2.5V

V

OUT

= 1.8V

V

OUT

= 1.5V

R1 (k

) R3 (k) C9 (µF) R1 (k) R3 (k) C9 (µF) R1 (k) R3 (k) C9 (µF)

R1 (

)

R3 (k

) C9 (µF)

3.12

1.2

0.0068

2.13

9.1

0.01

1.24

6.8

0.01

876 5.5

0.01

1.24

1.24

2.7

3.9

0.01

0.01

876

876

2.4

3.3

0.01

0.01

Table 5. R1, R3, and C9 Component Values for 500kHz Operation

V

IN

5V

3.3V

2.5V

V

OUT

= 3.3V

V

OUT

= 2.5V

V

OUT

= 1.8V

V

OUT

= 1.5V

R1 (k

) R3 (k) C9 (µF) R1 (k) R3 (k) C9 (µF) R1 (k) R3 (k) C9 (µF)

R1 (

)

R3 (k

) C9 (µF)

3.12

36 0.0033

2.13

27 0.0047

1.24

20 0.0068

876 16 0.0068

2.13

47

0.0033

1.24

1.24

30

39

0.0047

0.0033

876

876

27

33

0.0047

0.0033

Table 6. Component Suppliers

SUPPLIER PHONE WEBSITE

C entr al S em i cond uctor 631- w w w .centr al sem i .com

International Rectifier

Kamaya

Murata

Panasonic

310-322-3331

260-489-1533

814-237-1431

714-373-7939 www.irf.com

www.kamaya.com

www.murata.com

www.panasonic.com

Sanyo

Sumida

Taiyo Yuden

619-661-6835 www.sanyo.com

847-956-0666 www.sumida.com

408-573-4150 www.t-yuden.com

PART

MAX1960

MAX1961

MAX1962

VOLTAGE

MARGINING

±4%

No

Selector Guide

CURRENT

LIMIT

FET V

DS

Sensing

±10% with

R

SENSE

OUTPUT

VOLTAGE

Adjustable

4 Presets

4 Presets or

Adjustable

22 ______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

INPUT

2.7V TO 5.5V

C1

V

CC

C+ C-

AV

DD

C2

C9

R3

CTL1 V

DD

C8

CTL2

COMP

MAX1960

BST

DH

REF

LX

DL

GND

FSET/SYNC

CLKOUT

CLKOUT

N.C.

PGND

ILIM

FB

R5

R4

C4

D1

C6

C5

N1

R7

C13 L1

N2

R8

C14

R1

OUTPUT

DOWN TO 0.8V

C3

R2

Figure 9. Application Circuit 1—MAX1960 Adjustable Output Voltage

______________________________________________________________________________________ 23

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

INPUT

2.7V TO 5.5V

C9

R3

C2

C1

V

CC

C+ C-

AV

DD

CTL1 V

DD

C8

CTL2

COMP

MAX1961

BST

DH

REF

LX

DL

R5

C4

D1

C6

C5

N1

R7

C13 L1

N2

R8

C14

GND

FSET/SYNC

CLKOUT

CLKOUT

VSEL

PGND

ILIM

OUT

R4

OUTPUT 2.5V

C3

Figure 10. Application Circuit 2—MAX1961 Preset Output Voltage

24 ______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

INPUT

2.7V TO 5.5V

C9

R3

C2

C1

V

CC

C+ C-

AV

DD

C8

V

DD

EN

COMP

MAX1962

BST

DH

REF

LX

DL

R5

C4

D1

C6

C5

N1

R7

C13

L1

N2

R8

C14

GND

FSET/SYNC

CLKOUT

CLKOUT

PGND

CS

OUT

VSEL

FB

R6

OUTPUT

DOWN TO 0.8V

C3

R1

R2

Figure 11. Application Circuit 3—MAX1962 Adjustable Output Voltage

______________________________________________________________________________________ 25

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

D2 D3

C10

D4

C11

D5

C12

INPUT

2.35V TO 3.6V

C9

R3

C2

V

CC

C+ C-

AV

DD

V

DD

C8

EN

COMP

MAX1962

BST

DH

REF

LX

DL

R5

C4

D1

C6

C5

N1

R7

C13 L1

N2

R8

C14

R6

GND

FSET/SYNC

CLKOUT

CLKOUT

PGND

CS

OUT

VSEL

FB V

DD

OUTPUT 1.5V

C3

Figure 12. Application Circuit 4—MAX1962 Tripler Configuration, Preset Output

26 ______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

C10

33pF

INPUT

2.7V TO 5.5V

C2

5 x 10

µF

V

CC

C+

C1

0.47

µF

C-

AV

DD

CTL1 V

DD

CTL2

COMP

MAX1960

BST

DH

REF

LX

C9

820pF

R3

10k

C8

0.22

µF

GND

FSET/SYNC

CLKOUT

CLKOUT

DL

PGND

ILIM

N.C.

FB

C4

1

µF

R5

10

D1

C6

2.2

µF

C5

0.1

µF

N1

R7

1

C13

4700pF

L1

N2

R8

1

C14

4700pF

R9

680

R4

390k

C7

560pF

OUTPUT 2.5V, 15A

C3

4 x 47

µF

TAIYO-YUDEN

JMK325BJ476MN

R1

6.84k

R2

3.22k

N1 – IRLR7821

N2 – IRLR7833

Figure 13. Application Circuit—Ceramic Output Capacitors with Type 3 Compensation

______________________________________________________________________________________ 27

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Pin Configurations

TOP VIEW

CLKOUT 1

FSET/SYNC 2

ILIM 3

N.C. (SEL) 4

CTL1 5

CTL2 6

AV

DD

7

FB (OUT) 8

COMP 9

REF 10

MAX1960

MAX1961

( ) ARE FOR MAX1961.

QSOP

20 LX

19 DH

18 BST

17 V

CC

16 C+

15 C-

14

PGND

13 DL

12 V

DD

11 GND

TOP VIEW

CLKOUT 1

FSET/SYNC 2

EN 3

SEL 4

OUT 5

CS 6

AV

DD

7

FB 8

COMP 9

REF 10

MAX1962

QSOP

20 LX

19 DH

18 BST

17 V

CC

16 C+

15 C-

14

PGND

13 DL

12 V

DD

11 GND

TRANSISTOR COUNT: 4476

Chip Information

PROCESS: BiCMOS

28 ______________________________________________________________________________________

2.35V to 5.5V, 0.5% Accurate, 1MHz PWM

Step-Down Controllers with Voltage Margining

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to

www.maxim-ic.com/packages

.)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29

© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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