datasheet for Am29SL800D by Spansion

datasheet for Am29SL800D by Spansion
Am29SL800D
Data Sheet (Retired Product)
Am29SL800D Cover Sheet
This product has been retired and is not recommended for designs. For new and current designs, S29AS008J supercedes
Am29SL800D. This is the factory-recommended migration path. Please refer to the S29AS008J data sheet for specifications
and ordering information. Availability of this document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 27546
Revision A
Amendment 7
Issue Date February 23, 2009
Da ta
Shee t
(Retire d
Pro duct)
This page left intentionally blank.
2
Am29SL800D
27546_A7 February 23, 2009
DATA SHEET
Am29SL800D
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 1.8 Volt-only Super Low Voltage Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29AS008J supercedes Am29SL800D. This is the factory-recommended migration path. Please refer to the S29AS008J data sheet
for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
̈ Single Power Supply Operation
— 1.65 to 2.2 V for read, program, and erase
operations
— Ideal for battery-powered applications
̈ Manufactured on 0.23 µm Process Technology
— Compatible with 0.32 µm Am29SL800C device
̈ High Performance
— Access times as fast as 90 ns
̈ Ultra Low Power Consumption (Typical Values at
5 MHz)
̈ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
̈ Minimum 1,000,000 Erase Cycle Guarantee Per
Sector
̈ 20-Year Data Retention at 125°C
̈ Package Option
— 0.2 µA Automatic Sleep Mode current
— 48-pin TSOP
— 0.2 µA standby mode current
— 48-ball FBGA
— 5 mA read current
— 15 mA program/erase current
̈ Flexible Sector Architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection Features:
A hardware method of locking a sector to prevent any
program or erase operations within that sector
Sectors can be locked in-system or via programming
equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
̈ Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
̈ Compatibility with JEDEC Standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
̈ Data# Polling and Toggle Bits
— Provides a software method of detecting program
or erase operation completion
̈ Ready/Busy# Pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
̈ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
̈ Hardware Reset Pin (RESET#)
— Hardware method to reset the device to reading
array data
̈ Top or Bottom Boot Block Configurations
Available
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 27546 Rev: A Amendment/7
Issue Date: February 23, 2009
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29SL800D is an 8 Mbit, 1.8 V volt-only Flashmemory organized as 1,048,576 bytes or 524,288
words. The device is offered in 48-pin TSOP and 48ball FBGA packages. The word-wide data (x16)
appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed and erased in-system with a single 1.8
volt VCC supply. No VPP is for write or erase operations.
The device can also be programmed in standard
EPROM programmers.
The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 1.8 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already
programmed) before executing the erase operation.
2
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Packages .................. 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Standard Products .................................................................... 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Write Operation Status ..................................................... 23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24
Figure 7. Maximum Negative Overshoot Waveform ...................... 24
Figure 8. Maximum Positive Overshoot Waveform........................ 24
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. CMOS Compatible ........................................................... 25
Zero Power Flash ................................................................... 26
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 26
Figure 10. Typical ICC1 vs. Frequency ........................................... 26
Table 1. Am29SL800D Device Bus Operations ................................8
Word/Byte Configuration .......................................................... 8
Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 8
Program and Erase Operation Status ...................................... 9
Standby Mode .......................................................................... 9
Automatic Sleep Mode ............................................................. 9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode .............................................................. 10
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Test Setup..................................................................... 27
Table 8. Test Specifications ........................................................... 27
Table 9. Key to Switching Waveforms ........................................... 27
Figure 12. Input Waveforms and Measurement Levels ................. 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. Read Operations ............................................................ 28
Figure 13. Read Operations Timings ............................................. 28
Table 11. Hardware Reset (RESET#) ............................................ 29
Figure 14. RESET# Timings .......................................................... 29
Table 12. Word/Byte Configuration (BYTE#) ................................. 30
Figure 15. BYTE# Timings for Read Operations............................ 30
Figure 16. BYTE# Timings for Write Operations............................ 30
Table 13. Erase/Program Operations ............................................ 31
Figure 17. Program Operation Timings.......................................... 32
Figure 18. Chip/Sector Erase Operation Timings .......................... 33
Figure 19. Data# Polling Timings (During Embedded Algorithms). 34
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 34
Figure 21. DQ2 vs. DQ6................................................................. 35
Table 14. Temporary Sector Unprotect .......................................... 35
Figure 22. Temporary Sector Unprotect Timing Diagram .............. 35
Figure 23. Sector Protect/Unprotect Timing Diagram .................... 36
Table 15. Alternate CE# Controlled Erase/Program Operations .... 37
Figure 24. Alternate CE# Controlled Write Operation Timings ...... 38
Table 2. Am29SL800DT Top Boot Block Sector Address Table .....10
Table 3. Am29SL800DB Bottom Boot Block Sector Address Table 11
Autoselect Mode ..................................................................... 12
Table 4. Am29SL800D Autoselect Code (High Voltage Method) ...12
Sector Protection/Unprotection ............................................... 12
Temporary Sector Unprotect .................................................. 12
Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 13
Figure 2. Temporary Sector Unprotect Operation........................... 14
Hardware Data Protection ...................................................... 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . 14
Reading Array Data ................................................................ 14
Reset Command ..................................................................... 14
Autoselect Command Sequence ............................................ 15
Word/Byte Program Command Sequence ............................. 15
Figure 3. Program Operation .......................................................... 16
Chip Erase Command Sequence ........................................... 16
Sector Erase Command Sequence ........................................ 16
Erase Suspend/Erase Resume Commands ........................... 17
Erase and Programming Performance . . . . . . . 39
Table 16. Erase and Programming Performance ........................... 39
Table 17. Latchup Characteristics .................................................. 39
Table 18. TSOP Pin Capacitance .................................................. 39
Table 19. Data Retention ............................................................... 39
Figure 4. Erase Operation............................................................... 18
Table 5. Am29SL800D Command Definitions ................................19
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 20
DQ7: Data# Polling ................................................................. 20
Figure 5. Data# Polling Algorithm ................................................... 20
RY/BY#: Ready/Busy# ........................................................... 21
DQ6: Toggle Bit I .................................................................... 21
DQ2: Toggle Bit II ................................................................... 21
Reading Toggle Bits DQ6/DQ2 .............................................. 21
Figure 6. Toggle Bit Algorithm......................................................... 22
DQ5: Exceeded Timing Limits ................................................ 22
DQ3: Sector Erase Timer ....................................................... 22
February 23, 2009 27546A7
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TS 048—48-Pin Standard TSOP ............................................ 40
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 X 6.15 mm Package ....................................................... 41
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
9 x 8 mm Package .................................................................. 42
VBK048—48 Ball Fine-Pitch Ball Grid Array (FBGA) ............. 43
8.15 x 6.15 mm ....................................................................... 43
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44
Am29SL800D
3
D A T A
S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Am29SL800D
90
(Note 2)
100
120
150
Max access time, ns (tACC)
90 (Note 2)
100
120
150
Max CE# access time, ns (tCE)
90 (Note 2)
100
120
150
Max OE# access time, ns (tOE)
30
35
50
65
Speed Options
Notes:
1. See “AC Characteristics” for full specifications.
2. VCC min. = 1.7 V
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A18
4
Am29SL800D
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
27546A7 February 23, 2009
D A T A
S H E E T
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Standard TSOP
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48-Ball FBGA
(Top View, Balls Facing Down)
A6
B6
C6
D6
E6
A13
A12
A14
A15
A16
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
G6
BYTE# DQ15/A-1
H6
VSS
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
NC
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
A18
NC
DQ2
DQ10
DQ11
DQ3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
A3
A4
A2
A1
A0
CE#
OE#
VSS
Special Handling Instructions for FBGA
Packages
Special handling is required for Flash Memory products
in molded packages (TSOP and BGA). The package
February 23, 2009 27546A7
F6
and/or data integrity may be compromised if the
package body is exposed to temperatures about 150°C
for prolonged periods of time.
Am29SL800D
5
D A T A
PIN CONFIGURATION
A0–A18
S H E E T
LOGIC SYMBOL
= 19 addresses
19
DQ0–DQ14 = 15 data inputs/outputs
A0–A18
DQ15/A-1
= DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE#
= Selects 8-bit or 16-bit mode
CE#
= Chip enable
OE#
= Output enable
WE#
= Write enable
RESET#
RESET#
= Hardware reset pin, active low
BYTE#
RY/BY#
= Ready/Busy# output
VCC
= 1.65–2.2 V single power supply
VSS
= Device ground
NC
= Pin not connected internally
6
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
Am29SL800D
RY/BY#
27546A7 February 23, 2009
D A T A
S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29SL800D
T
-100
E
C
TEMPERATURE RANGE
C
= Commercial (0°C to +70°C)
D
= Commercial (0°C to +70°C) with Pb-free package
I
=
Industrial (–40°C to +85°C)
F
=
Industrial (–40°C to +85°C) with Pb-free package
PACKAGE TYPE
E
= 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
VU
= 48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80mm pitch, 8.15 x 6.15 mm package (VBK048)
WA
= 48-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 8.15 x 6.15 mm package (FBA048)
WC = 48-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 9 x 8 mm package (FBC048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
=
Top Sector
B
=
Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29SL800D
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
1.8 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations for FBGA Packages
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Valid Combinations for TSOP Packages
Order Number
AM29SL800DT90,
AM29SL800DB90
AM29SL800DT90,
AM29SL800DB90
AM29SL800DT100,
AM29SL800DB100
AM29SL800DT100,
AM29SL800DB100
EC, EI, ED, EF
AM29SL800DT120,
AM29SL800DB120
AM29SL800DT150,
AM29SL800DB150
AM29SL800DT120,
AM29SL800DB120
AM29SL800DT150,
AM29SL800DB150
Am29SL800DT120
February 23, 2009 27546A7
Am29SL800D
Package Marking
WAC, WAD
WAI, WAF
A800DT90U,
A800DB90U
WCC, WCD, A800DT90P,
WCI, WCF A800DB90P
WAC, WAD
WAI, WAF
A800DT10U,
A800DB10U
WCC, WCD, A800DT10P,
WCI, WCF A800DB10P
WAC, WAD
WAI, WAF
A800DT12U,
A800DB12U
C, I,
D, F
WCC, WCD, A800DT12P,
WCI, WCF A800DB12P
WAC, WAD
WAI, WAF
A800DT15U,
A800DB15U
WCC, WCD, A800DT15P,
WCI, WCF A800DB15P
VUF
A800DT12V
A800DB12V
7
D A T A
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory location. The register is composed of latches that store the
commands, along with the address and data informaTable 1.
S H E E T
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
Am29SL800D Device Bus Operations
DQ8–DQ15
CE#
OE#
WE#
RESET#
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
BYTE#
= VIL
Read
L
L
H
H
AIN
DOUT
DOUT
Write
L
H
L
H
AIN
DIN
DIN
DQ8–DQ14 = High-Z,
DQ15 = A-1
VCC ±
0.2 V
X
X
VCC ±
0.2 V
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
High-Z
High-Z
High-Z
Sector Protect (Note)
L
H
L
VID
Sector Address, A6 =
L, A1 = H,
A0 = L
DIN
X
X
Sector Unprotect (Note)
L
H
L
VID
Sector Address, A6 =
H, A1 = H,
A0 = L
DIN
X
X
Temporary Sector Unprotect
X
X
X
VID
AIN
DIN
DIN
High-Z
Operation
Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at V IH . The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
8
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See Reading Array Data‚ on page 14 for more information. Refer to the AC Read Operations table for timing
specifications and to Figure 13, on page 28 for the
timing diagram. ICC1 in the DC Characteristics table
represents the active current specification for reading
array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
Am29SL800D
27546A7 February 23, 2009
D A T A
words. Refer to Word/Byte Configuration‚ on page 8
for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
Word/Byte Program Command Sequence‚ on page 15
has details on programming data to the device using
b o t h s t a n d a r d a n d U n l o ck B y p a s s c o m m a n d
sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The Command Definitions‚ on
page 14 has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode‚ on page 12
and Autoselect Command Sequence‚ on page 15 sections for more information.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. AC
Characteristics‚ on page 28 contains timing specification tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to Write Operation
Status‚ on page 20 for more information, and to “AC
Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.2 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.2 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
February 23, 2009 27546A7
S H E E T
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
RESET#: Hardware Reset Pin.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
ICC3 in Table 7 on page 25 represents the standby
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 50
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in Table 7 on
page 25 represents the automatic sleep mode current
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.2 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.2 V, the standby current is
greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algorithms). The system can read data t RH after the
RESET# pin returns to VIH.
Am29SL800D
9
D A T A
S H E E T
Output Disable Mode
Refer to the Table 10 on page 28 for RESET# parameters and to Figure 14, on page 29 for the timing
diagram.
Table 2.
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
Am29SL800DT Top Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
0
0
0
0
X
X
X
64/32
00000h–0FFFFh
00000h–07FFFh
SA1
0
0
0
1
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA2
0
0
1
0
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA3
0
0
1
1
X
X
X
64/32
30000h–3FFFFh
18000h–1FFFFh
SA4
0
1
0
0
X
X
X
64/32
40000h–4FFFFh
20000h–27FFFh
SA5
0
1
0
1
X
X
X
64/32
50000h–5FFFFh
28000h–2FFFFh
SA6
0
1
1
0
X
X
X
64/32
60000h–6FFFFh
30000h–37FFFh
SA7
0
1
1
1
X
X
X
64/32
70000h–7FFFFh
38000h–3FFFFh
SA8
1
0
0
0
X
X
X
64/32
80000h–8FFFFh
40000h–47FFFh
SA9
1
0
0
1
X
X
X
64/32
90000h–9FFFFh
48000h–4FFFFh
SA10
1
0
1
0
X
X
X
64/32
A0000h–AFFFFh
50000h–57FFFh
SA11
1
0
1
1
X
X
X
64/32
B0000h–BFFFFh
58000h–5FFFFh
SA12
1
1
0
0
X
X
X
64/32
C0000h–CFFFFh
60000h–67FFFh
SA13
1
1
0
1
X
X
X
64/32
D0000h–DFFFFh
68000h–6FFFFh
SA14
1
1
1
0
X
X
X
64/32
E0000h–EFFFFh
70000h–77FFFh
SA15
1
1
1
1
0
X
X
32/16
F0000h–F7FFFh
78000h–7BFFFh
SA16
1
1
1
1
1
0
0
8/4
F8000h–F9FFFh
7C000h–7CFFFh
SA17
1
1
1
1
1
0
1
8/4
FA000h–FBFFFh
7D000h–7DFFFh
SA18
1
1
1
1
1
1
X
16/8
FC000h–FFFFFh
7E000h–7FFFFh
10
Am29SL800D
(x8)
Address Range
(x16)
Address Range
27546A7 February 23, 2009
D A T A
Table 3.
S H E E T
Am29SL800DB Bottom Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
0
0
0
0
0
0
X
16/8
00000h–03FFFh
00000h–01FFFh
SA1
0
0
0
0
0
1
0
8/4
04000h–05FFFh
02000h–02FFFh
SA2
0
0
0
0
0
1
1
8/4
06000h–07FFFh
03000h–03FFFh
SA3
0
0
0
0
1
X
X
32/16
08000h–0FFFFh
04000h–07FFFh
SA4
0
0
0
1
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA5
0
0
1
0
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA6
0
0
1
1
X
X
X
64/32
30000h–3FFFFh
18000h–1FFFFh
SA7
0
1
0
0
X
X
X
64/32
40000h–4FFFFh
20000h–27FFFh
SA8
0
1
0
1
X
X
X
64/32
50000h–5FFFFh
28000h–2FFFFh
SA9
0
1
1
0
X
X
X
64/32
60000h–6FFFFh
30000h–37FFFh
SA10
0
1
1
1
X
X
X
64/32
70000h–7FFFFh
38000h–3FFFFh
SA11
1
0
0
0
X
X
X
64/32
80000h–8FFFFh
40000h–47FFFh
SA12
1
0
0
1
X
X
X
64/32
90000h–9FFFFh
48000h–4FFFFh
SA13
1
0
1
0
X
X
X
64/32
A0000h–AFFFFh
50000h–57FFFh
SA14
1
0
1
1
X
X
X
64/32
B0000h–BFFFFh
58000h–5FFFFh
SA15
1
1
0
0
X
X
X
64/32
C0000h–CFFFFh
60000h–67FFFh
SA16
1
1
0
1
X
X
X
64/32
D0000h–DFFFFh
68000h–6FFFFh
SA17
1
1
1
0
X
X
X
64/32
E0000h–EFFFFh
70000h–77FFFh
SA18
1
1
1
1
X
X
X
64/32
F0000h–FFFFFh
78000h–7FFFFh
(x8)
Address Range
(x16)
Address Range
Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more
information.
February 23, 2009 27546A7
Am29SL800D
11
D A T A
S H E E T
Autoselect Mode
address must appear on the appropriate highest order
address bits (see Table 2 on page 10 and Table 3 on
page 11). Table 4 shows the remaining address bits
that are don’t care. When all necessary bits have been
set as required, the programming equipment may then
read the corresponding identifier code on DQ7–DQ0.
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5 on page 19.
This method does not require VID. See Command
Definitions‚ on page 14 for details on using the autoselect mode.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector
Table 4.
Description
Mode
Manufacturer ID: AMD
Am29SL800D Autoselect Code (High Voltage Method)
A11
to
A10
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
X
01h
22h
EAh
X
EAh
22h
6Bh
X
6Bh
X
01h (protected)
X
00h
(unprotected)
OE#
WE#
L
L
H
X
X
VID
X
L
X
L
L
L
L
H
X
X
VID
X
L
X
L
H
VID
X
Word
Byte
L
L
H
Device ID:
Am29SL800D
(Bottom Boot Block)
Word
L
L
H
X
Sector Protection Verification
A6
A5
to
A2
CE#
Device ID:
Am29SL800D
(Top Boot Block)
Byte
A9
A8
to
A7
A18
to
A12
L
L
L
L
X
H
H
SA
X
VID
X
L
L
X
X
L
H
H
L
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. Sector protection/unprotection can be implemented via two methods.
Sector Protection/ Unprotection requires VID on the
RESET# pin only, and can be implemented either insystem or via programming equipment. Figure 1, on
page 13 shows the algorithms and Figure 23, on page
36 shows the timing diagram. For sector unprotect, all
unprotected sectors must first be protected prior to the
first sector unprotect write cycle.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
12
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See Autoselect Mode‚ on page 12 for
details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by
selecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 2, on page 14
shows the algorithm, and Figure 22, on page 35 shows
the timing diagrams, for this feature.
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 ms
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 ms
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
All sectors
protected?
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
Reset
PLSCNT = 1
Wait 15 ms
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
No
Yes
Yes
Device failed
PLSCNT
= 1000?
Protect another
sector?
No
Set up
next sector
address
No
Data = 00h?
Yes
Yes
Remove VID
from RESET#
Device failed
Last sector
verified?
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Figure 1.
February 23, 2009 27546A7
In-System Sector Protect/Unprotect Algorithms
Am29SL800D
13
D A T A
S H E E T
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
START
RESET# = VID
(Note 1)
Low VCC Write Inhibit
When V CC is less than V LKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Notes:
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 2. Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 on page 19
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 on page 19 defines the valid register command sequences. Writing incorrect address
and data values or writing them in the improper
sequence may place the device in an unknown state. A
reset command is then required to return the device to
reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
AC Characteristics‚ on page 28 section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
14
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See Erase
Suspend/Erase Resume Commands‚ on page 17 for
more information on this mode.
The system must issue the reset command to reenable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See Reset Command‚ on page 14.
See also Requirements for Reading Array Data‚ on
page 8 for more information. Table 10 on page 28 provides the read parameters, and Figure 12, on page 27
shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
Am29SL800D
27546A7 February 23, 2009
D A T A
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies dur ing Erase
Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 on page 19 shows the address and data
requirements. This method is an alternative to that
shown in Table 4 on page 12, which is intended for
PROM programmers and requires VID on address bit
A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address 01h in
word mode (or 02h in byte mode) returns the device
code. A read cycle containing a sector address (SA)
and the address 02h in word mode (or 04h in byte
mode) returns 01h if that sector is protected, or 00h if it
is unprotected. Refer to Table 2 on page 10 and Table 3
on page 11 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command.
February 23, 2009 27546A7
S H E E T
The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or timings. The device automatically generates the program
pulses and verifies the programmed cell margin.
Table 5 on page 19 shows the address and data
r e q u i r e m e n t s fo r t h e byt e p r o gra m c o m m a n d
sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See Table on page 20 for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes or words to the device faster than using
the standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A twocycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 5 on page 19 shows the requirements
for the command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses
are don’t cares. The device then returns to reading
array data.
Am29SL800D
15
D A T A
Figure 3 illustrates the algorithm for the program operation. See Table 13 on page 31 for parameters, and to
Figure 17, on page 32 for timing diagrams.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
1. See Table 5 for program command sequence.
Figure 3.
Program Operation
No
S H E E T
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 5 on
page 19 shows the address and data requirements for
the chip erase command sequence.
Any commands wr itten to the chip dur ing the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
Figure 4, on page 18 illustrates the algorithm for the
erase operation. See Table 13 on page 28 for parameters, and to Figure 10, on page 26 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for the sector erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during
16
Am29SL800D
27546A7 February 23, 2009
D A T A
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See DQ3: Sector Erase
Timer‚ on page 22.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. (Refer to Write Operation Status‚ on
page 20 for information on these status bits.)
Figure 4, on page 18 illustrates the algorithm for the
erase operation. Refer to the Table 16 on page 39for
parameters, and to Figure 18, on page 33 for timing
diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
February 23, 2009 27546A7
S H E E T
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-suspended. See Write Operation Status‚ on page 20 for
information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program operation. See Write Operation Status‚ on page 20 for
more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See Autoselect Command Sequence‚
on page 15 for more information.
The system must write the Erase Resume command
(address bits are don’t care) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
Am29SL800D
17
D A T A
S H E E T
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
18
Am29SL800D
27546A7 February 23, 2009
D A T A
Cycles
Table 5.
Command
Sequence
(Note 1)
Read (Note 6)
Reset (Note 7)
Autoselect (Note 8)
Manufacturer ID
Word
Byte
Device ID,
Top Boot Block
Word
Device ID,
Bottom Boot Block
Word
Sector Protect Verify
(Note 9)
Byte
Byte
Unlock Bypass
First
Second
1
RA
RD
1
XXX
F0
4
4
555
AAA
555
AAA
555
AAA
AA
AA
AA
555
4
Byte
Addr
2AA
555
2AA
555
2AA
555
AA
555
AAA
555
55
AAA
55
AAA
Word
555
2AA
555
Word
Byte
3
555
AAA
AA
AA
555
2AA
555
55
XXX
A0
PA
PD
2
XXX
90
XXX
00
Byte
Word
Byte
6
6
555
AAA
555
AAA
AA
AA
Erase Suspend (Note 12)
1
XXX
B0
Erase Resume (Note 13)
1
XXX
30
2AA
555
2AA
555
Legend:
X = Don’t care
AAA
555
55
2
Word
X00
01
X01
22EA
X02
EA
X01
226B
90
90
X02
6B
(SA)
X02
XX00
(SA)
X04
00
X03
90
555
AAA
90
555
55
AAA
4
Data
AAA
Byte
Byte
Addr
90
2AA
AA
Fourth
Data
555
Unlock Bypass Reset (Note 11)
Sector Erase
AAA
55
Unlock Bypass Program (Note 10)
Chip Erase
Addr
555
55
555
555
4
Third
Data
2AA
AAA
Word
Program
Bus Cycles (Notes 2-5)
Data
Word
Extension
Am29SL800D Command Definitions
Addr
4
S H E E T
AAA
555
55
AAA
555
55
AAA
X04
A0
PA
Fifth
Addr
Sixth
Data
Addr
Data
XX01
01
TBD
TBD
TBD
TBD
PD
20
80
80
555
AAA
555
AAA
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are
write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
cycles.
5. Address bits A18–A11 are don’t cares for unlock and command
cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data,
unless SA or PA required.
7. The Reset command is required to return to reading array data
when device is in the autoselect mode, or if DQ5 goes high (while
the device is providing status data).
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A12 uniquely select any sector.
9. The data is 00h for an unprotected sector and 01h for a protected
sector. See “Autoselect Command Sequence” for more
information.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
11. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the
autoselect mode, when in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
13. The Erase Resume command is valid only during the Erase Suspend
mode.
8. The fourth cycle of the autoselect command sequence is a read
cycle.
February 23, 2009 27546A7
Am29SL800D
19
D A T A
S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6,
DQ7, and RY/BY#. Table 6 and the following subsections describe the functions of these bits. DQ7,
RY/BY#, and DQ6 each offer a method for determining
whether a program or erase operation is complete or in
progress. These three bits are discussed first.
page 34, Data# Polling Timings (During Embedded
Algorithms), illustrates this.
Table 6 on page 23 shows the outputs for Data# Polling
on DQ7. Figure 5 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
DQ7 = Data?
No
No
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 19, on
20
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a 0 on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a 1 on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to 1; prior
to this, the device outputs the complement, or 0. The
system must provide an address within any of the
sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector erase
operation, a valid address is an address within any sector
selected for erasure. During chip erase, a valid address is any
non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may
change simultaneously with DQ5.
Am29SL800D
Figure 5. Data# Polling Algorithm
27546A7 February 23, 2009
D A T A
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel
with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 on page 23 shows the outputs for RY/BY#.
Figure 14, on page 29, Figure 17, on page 32, and
Figure 18, on page 33 shows RY/BY# for reset, program, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle (The system may use either OE#
or CE# to control the read cycles). When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
February 23, 2009 27546A7
S H E E T
Table 6 on page 23 shows the outputs for Toggle Bit I
on DQ6. Figure 6, on page 22 shows the toggle bit
algorithm. Figure 20, on page 34 shows the toggle bit
timing diagrams. Figure 21, on page 35 shows the differences between DQ2 and DQ6 in graphical form. See
also the subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE# or CE# read cycle.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer to Table 6 on page 23 to compare outputs
for DQ2 and DQ6.
Figure 6, on page 22 shows the toggle bit algorithm in
flowchart form, and the section DQ2: Toggle Bit II
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 20, on page 34 shows the toggle bit
timing diagram. Figure 21, on page 35 shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 22 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice
in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of
the toggle bit after the first read. After the second read,
the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation.
The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to return
to reading array data.
Am29SL800D
21
D A T A
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 6).
START
S H E E T
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a 1. This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a 1 to a location that is previously programmed to 0. Only an erase operation can change
a 0 back to a 1. Under this condition, the device halts
the operation, and when the operation has exceeded
the timing limits, DQ5 produces a 1.
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
Read DQ7–DQ0
Read DQ7–DQ0
DQ3: Sector Erase Timer
Toggle Bit
= Toggle?
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches
from 0 to 1. If the time between additional sector erase
commands from the system can be assumed to be less
than 50 µs, the system need not monitor DQ3. See also
Sector Erase Command Sequence‚ on page 16.
No
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes
to “1”. See text
Figure 6. Toggle Bit Algorithm
22
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is 1, the internally controlled erase cycle has
begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete.
If DQ3 is 0, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Figure 6 shows the outputs for DQ3.
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
Table 6. Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Operation
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5:
Exceeded Timing Limits for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
February 23, 2009 27546A7
Am29SL800D
23
D A T A
S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages ...............................–65°C to +150°C
Ambient Temperature
with Power Applied............................–65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) ................................ –0.5 V to +2.5 V
A9, OE#,
and RESET# (Note 2)................ –0.5 V to +11.0 V
20 ns
0.0 V
–0.5 V
–2.0 V
20 ns
All other pins (Note 1)........... –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3) ............. 100 mA
20 ns
Figure 7. Maximum Negative Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage
transitions, input or I/O pins may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 7. Maximum DC voltage on
input or I/O pins is VCC +0.5 V. During voltage transitions, input
or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns.
See Figure 8.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5
V. During voltage transitions, A9, OE#, and RESET# may
overshoot VSS to –2.0 V for periods of up to 20 ns. See Maximum
DC input voltage on pin A9 is +11.0 V which may overshoot to
12.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time.
Duration of the short circuit should not be greater than one
second.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 8. Maximum Positive Overshoot Waveform
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA).......................0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA)...................–40°C to +85°C
VCC Supply Voltages
VCC, 90ns speed option ...................+1.70 V to +2.2 V
VCC, All other speed options ............+1.65 V to +2.2 V
Operating ranges define those limits between which the functionality
of the device is guaranteed.
24
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
DC CHARACTERISTICS
Table 7.
Parameter
Description
CMOS Compatible
Test Conditions
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 11.0 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
ICC1
VCC Active Read Current
(Notes 1, 2)
Min
Typ
Max
Unit
±1.0
µA
35
µA
±1.0
µA
CE# = VIL, OE# = VIH,
Byte Mode
5 MHz
5
10
1 MHz
1
3
CE# = VIL, OE# = VIH,
Word Mode
5 MHz
5
10
1 MHz
1
3
mA
ICC2
VCC Active Write Current
(Notes 2, 3, 5)
CE# = VIL, OE# = VIH
15
30
mA
ICC3
VCC Standby Current (Note 2)
CE#, RESET# = VCC ± 0.2 V
0.2
5
µA
ICC4
VCC Reset Current (Note 2)
RESET# = VSS ± 0.2 V
0.2
5
µA
ICC5
Automatic Sleep Mode
(Notes 2, 3)
VIH = VCC ± 0.2 V;
VIL = VSS ± 0.2 V
0.2
5
µA
VIL
Input Low Voltage
–0.5
0.3 x VCC
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
9.0
11.0
V
IOL = 2.0 mA, VCC = VCC min
0.25
V
IOL = 100 μA, VCC = VCC min
0.1
V
VOL1
Output Low Voltage
VOL2
VOH1
Output High Voltage
VOH2
VLKO
VCC = 2.0 V
IOH = –2.0 mA, VCC = VCC min
0.85 x VCC
V
IOH = –100 μA, VCC = VCC min
VCC–0.1
V
Low VCC Lock-Out Voltage (Note 4)
1.2
1.5
V
Notes:
1. The ICC current listed is typically less than 1 mA/MHz, with OE# at VIH. Typical VCC is 2.0 V.
2. The maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 50 ns.
5. Not 100% tested.
February 23, 2009 27546A7
Am29SL800D
25
D A T A
S H E E T
DC CHARACTERISTICS (Continued)
Zero Power Flash
Supply Current in mA
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
Supply Current in mA
8
6
2.2 V
4
1.8 V
2
0
1
2
3
Frequency in MHz
4
5
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
26
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
TEST CONDITIONS
Table 8.
Test Specifications
Test Condition
-90,
-100
Output Load
Device
Under
Test
30
Input Rise and Fall Times
100
pF
5
ns
0.0–2.0
V
Input timing measurement
reference levels
1.0
V
Output timing measurement
reference levels
1.0
V
Input Pulse Levels
Figure 11.
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
CL
-120,
-150
Test Setup
Table 9.
WAVEFORM
Key to Switching Waveforms
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
2.0 V
Input
1.0 V
Measurement Level
1.0 V
Output
0.0 V
Figure 12. Input Waveforms and Measurement Levels
February 23, 2009 27546A7
Am29SL800D
27
D A T A
S H E E T
AC CHARACTERISTICS
Table 10.
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
-90
-100
-120
-150
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
90
(Note 3)
100
120
150
ns
tAVQV
tACC
Address to Output Delay
CE# = VIL
OE# = VIL
Max
90
(Note 3)
100
120
150
ns
tELQV
tCE
Chip Enable to Output Delay
OE# = VIL
Max
90
(Note 3)
100
120
150
ns
tGLQV
tOE
Output Enable to Output Delay
Max
30
35
50
65
ns
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
Read
Min
0
ns
Toggle and
Data# Polling
Min
30
ns
Min
0
ns
tOEH
tAXQX
tOH
Output Enable
Hold Time (Note 1)
Test Setup
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Figure 11, on page 27 and Table 8 on page 27 for test specifications
3. VCC min. = 1.7V
.
tRC
Addresses Stable
Addresses
tACC
CE#
tD
tOE
OE#
tOEH
WE#
tCE
tO
HIGH Z
Output Valid
Outputs
HIGH Z
RESET#
RY/BY#
0V
Figure 13. Read Operations Timings
28
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
AC CHARACTERISTICS
Table 11.
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tREADY
RESET# Pin Low (During Embedded Algorithms) to Read or Write
(see Note)
Max
20
µs
tREADY
RESET# Pin Low (NOT During Embedded Algorithms) to Read or
Write (see Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
RESET# High Time Before Read (see Note)
Min
200
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14.
February 23, 2009 27546A7
RESET# Timings
Am29SL800D
29
D A T A
S H E E T
AC CHARACTERISTICS
Table 12.
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Speed Options
Std
Description
-90
-100
-120
-150
Unit
tELFL/tELFH
CE# to BYTE# Switching Low or High
Max
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
50
50
60
60
ns
tFHQV
BYTE# Switching High to Output Active
Min
90
100
120
150
ns
10
ns
CE#
OE#
BYTE#
BYTE#
Switching
from word
to byte
mode
tELFL
Data Output
(DQ0–DQ14)
DQ0–DQ14
Address
Input
DQ15
Output
DQ15/A-1
Data
Output
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte to
word mode
DQ0–DQ14
Data
Output
DQ15/A-1
Address
Input
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
Figure 15.
BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16. BYTE# Timings for Write Operations
30
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
AC CHARACTERISTICS
Table 13.
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-90
-100
-120
-150
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
90
100
120
150
ns
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
50
60
70
ns
tDVWH
tDS
Data Setup Time
Min
45
50
60
70
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
0
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
30
Byte
Typ
5
tWHWH1
tWHWH1
Programming Operation (Notes 1, 2)
Word
Typ
7
tWHWH2
tWHWH2
Sector Erase Operation (Notes 1, 2)
Typ
0.7
sec
tVCS
VCC Setup Time
Min
50
µs
tRB
Recovery Time from RY/BY#
Min
0
ns
Program/Erase Valid to RY/BY# Delay
Max
200
ns
tBUSY
45
50
60
70
ns
ns
µs
Notes:
1. Not 100% tested.
2. See the Table 16 on page 39 for more information.
February 23, 2009 27546A7
Am29SL800D
31
D A T A
S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tD
PD
A0h
Data
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17.
32
Program Operation Timings
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
555h for chip erase
VA
tAH
CE#
tCH
OE#
tW
WE#
tWP
tCS
tWHWH
tD
tD
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 18.
February 23, 2009 27546A7
Chip/Sector Erase Operation Timings
Am29SL800D
33
D A T A
S H E E T
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
High Z
Valid Data
True
High Z
Valid Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUS
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
34
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Erase Suspend
Read
Erase
WE#
Enter Erase
Suspend Program
Erase
Resume
Erase
Suspend
Program
Erase
Complete
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Figure 21. DQ2 vs. DQ6
Table 14.
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time
Min
500
ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
µs
10 V
RESET#
0 or 1.8 V
0 or 1.8 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 22. Temporary Sector Unprotect Timing Diagram
February 23, 2009 27546A7
Am29SL800D
35
D A T A
S H E E T
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Protect/Unprotect
Data
60h
1 µs
Valid*
Verify
60h
40h
Status
Sector Protect: 150 µs
Sector Unprotect: 15 ms
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector Protect/Unprotect Timing Diagram
36
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
AC CHARACTERISTICS
Table 15.
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-90
-100
-120
-150
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
90
100
120
150
ns
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
50
60
70
ns
tDVEH
tDS
Data Setup Time
Min
45
50
60
70
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
30
Typ
5
tWHWH1
Programming Operation
(Notes 1, 2)
Byte
tWHWH1
Word
Typ
7
tWHWH2
tWHWH2
Sector Erase Operation (Notes 1, 2)
Typ
0.7
0
45
50
ns
60
70
ns
ns
µs
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
February 23, 2009 27546A7
Am29SL800D
37
D A T A
S H E E T
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUS
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written, DOUT = data written
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.
Figure 24.
38
Alternate CE# Controlled Write Operation Timings
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Table 16.
Parameter
Erase and Programming Performance
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.7
15
s
Chip Erase Time
14
Excludes 00h programming prior
to erasure (Note 4)
Byte Programming Time
5
150
µs
Word Programming Time
7
210
µs
Chip Programming Time
Byte Mode
5.3
16
s
(Note 3)
Word Mode
3.7
11
s
s
Excludes system level overhead
(Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals
assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 for further
information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
Table 17.
Latchup Characteristics
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
11.0 V
Input voltage with respect to VSS on all I/O pins
–0.5 V
VCC + 0.5 V
VCC Current
–100 mA
+100 mA
Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.
Table 18.
TSOP Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Table 19.
Parameter
Data Retention
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
February 23, 2009 27546A7
Am29SL800D
39
D A T A
S H E E T
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99
40
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
PHYSICAL DIMENSIONS
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 X 6.15 mm Package
Dwg rev AF; 10/99
February 23, 2009 27546A7
Am29SL800D
41
D A T A
S H E E T
PHYSICAL DIMENSIONS
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
9 x 8 mm Package
Dwg rev AF; 10/99
42
Am29SL800D
27546A7 February 23, 2009
D A T A
S H E E T
PHYSICAL DIMENSIONS
VBK048—48 Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 x 6.15 mm
0.10 ( 4X)
D
D1
A
6
5
7
e
4
SE
E
E1
3
2
1
H
PI N A1
I NDEX MARK
CORNER
B
G
F
E
D
C
B
A
6
fb
10
SD
A1 CORNER
7
f 0.08M C
TOP VI EW
f 0.15M C A B
BOTTOM VI EW
0.10 C
A2
A
SEATING PLAN E
A1
C
0.08 C
SI DE VI EW
NOTES :
PACKAGE
VBK 048
JEDEC
1. DI MENSI ONI NG AND TOLERANCI NG PER ASME Y14.5M- 1994.
N/A
2. ALL DI MENSI ONS ARE I N MI LLI METERS.
8.15 mm x 6.15 mm NOM
PACKAG E
SYMBOL
MIN
NOM
3. BALL POSI TI ON DESI GNATI ON PER JESD 95- 1, SPP- 010 ( EXCEPT
AS NOTED).
MAX
A
---
---
1.00
A1
0.18
---
---
A2
0.62
---
0.76
NOT E
4. e
OVERALL THICKNESS
BALL HEIGHT
SYMBOL "ME" IS THE BALL NCOLUM
MATRIX SIZE IN THE
" E" DI RECTI ON.
BODY THICKNESS
D
8.15 BSC.
BODY SIZE
E
6.15 BSC.
BODY SIZE
N I S THE TOTAL NUMBER OF SOLDER BALLS.
6 DI MENSI ON " b" I S MEASURED AT THE MAXI MUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
5.60 BSC.
E1
4.00 BSC.
MD
8
ROW MATRIX SIZE D DIRECTION
ME
6
ROW MATRIX SIZE E DIRECTION
N
48
fb
0.35
---
BALL FOOTPRINT
BALL FOOTPRINT
WHEN THERE I S AN ODD NUMBER OF SOLDER BALLS I N
THE OUTER ROW PARALLEL TO THE ED DIMENSION,
OR
RESPECTI VELY, SD OR SE = 0.000.
BALL DIAMETER
e
0.80 BSC.
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMEN T
---
7 SD AND SE ARE MEASURED WITH RESPECT
TO DATUMS
A AND B AND DEFINE THE POSITION
OF THE CENTER
SOLDER BALL I N THE OUTER ROW.
TOTAL BALL COUNT
0.43
REPRESENTS THE SOLDER BALL GRI D PI TCH.
5. SYMBOL "MD" IS THE BALL ATRIX
ROW M SIZE IN THE
" D" DI RECTI ON.
DEPOPULATED SOLDER BALLS
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/ 2
8. NOT USED.
9. " + " I NDI CATES THE THEORETI CAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE I DENTI FI ED BY CHAMFER, LASER OR I NK
MARK, METALLI ZED MARK I NDENTATI ON OR OTHER MEANS.
3338 \ 16- 038.25b
February 23, 2009 27546A7
Am29SL800D
43
D A T A
S H E E T
REVISION SUMMARY
Revision A (February 4, 2003)
Revision A+4 (April 27, 2005)
Initial release.
Added Colophon.
Revision A+1 (March 17, 2003)
Updated Trademark.
Ordering Information
Revision A+5 (February 17, 2006)
Corrected typo in table.
Global
Corrected typo to OPNs.
Removed Reverse TSOP throughout.
Revision A+2 (June 10, 2004)
Revision A6 (January 23, 2007)
Ordering Information
Erase and Program Operations table
Added Pb-free package OPNs.
Changed tBUSY to a maximum specification.
Revision A+3 (October 27, 2004)
Revision A7 (February 23, 2009)
Updated VCC values
Global
Added VBK048 package.
Added obsolescence information.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2003–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are
for identification purposes only and may be trademarks of their respective companies.
Copyright © 2006–2009 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
ORNAND2™, HD-SIM™, EcoRAM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names
used are for informational purposes only and may be trademarks of their respective owners.
44
Am29SL800D
27546A7 February 23, 2009
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