datasheet for SYS88000RKX by Apta Group

datasheet for SYS88000RKX by Apta Group
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
8M x 8 SRAM MODULE
SYS88000RKX - 70/85/10/12
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax.+44 (0191)
Issue 1.4 : January 1999
2590997
Description
Features
The SYS88000RKX is a plastic 64Mbit Static RAM
Module housed in a standard 38 pin Single In-Line
package organised as 8M x 8 with access times of 70,
85,100, or 120 ns.
The module is constructed using sixteen 512Kx8 SRAMs
in TSOPII packages mounted onto both sides of an FR4
epoxy substrate. This offers an extremely high PCB
packing density.
The device is offered in standard and low power versions,
with the -L module having a low voltage data retention
mode for battery backed applications. On board buffering
is provided to reduce output capacitance.
Note: CS and OE on the module, should be used
with care to avoid on and off board bus contention.
Block Diagram
A19
A20
A21
A22
Access Times of 70/85/100/120 ns.
•
Low Power Disapation:
Operating
935 mW (Max.)
Standby
-L Version
11 mW (Max.)
•
5 Volt Supply ± 10%.
•
Completely Static Operation.
•
Equal Access and Cycle Times.
•
Low Voltage VCC Data Retention.
•
On-board Decoding & Capacitors.
•
38 Pin Single-In-Line package.
•
Upgrade from SYS84000RKX (32Mbit).
Pin Definition
OE
WE
A0 - A18
•
512K X 8
SRAM
T/R
BI-DIRECTIONAL
DRIVERS
4 TO 16
DECODER
D0 - D7
A0~7
B0~7
74FCT245
OE
512K X 8
SRAM
CS
Pin Functions
Address Inputs
Data Input/Output
A0 ~ A22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
D0 ~ D7
Chip Select
CS
Write Enable
WE
Output Enable
OE
No Connect
NC
Power (+5V)
VCC
Ground
D0 - D7
A22
A20
Vcc
WE
D2
D3
D0
A1
A2
A3
A4
GND
D5
A10
A11
A5
A13
A14
A19
CS
A15
A16
A12
A18
A6
D1
GND
A0
A7
A8
A9
D7
D4
D6
A17
Vcc
OE
A21
GND
Package Details
Plastic 38 pin Single-In-Line (SIP)
ISSUE 1.4 : January 1999
SYS88000RKX - 70/85/10/12
Absolute Maximum Ratings
(1)
Parameter
Symbol
(2)
T
Voltage on any pin relative to VSS
Power Dissipation
Storage Temperature
V
PT
TSTG
Min
Typ
Max
Unit
-0.3
-55
1.0
-
7.0
125
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) VT can be -3.0V pulse of less than 30ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
(Commercial)
(Industrial)
Symbol
Min
Typ
Max
Unit
VCC
VIH
VIL
TA
TAI
4.5
2.2
-0.3
0
-40
5.0
-
5.5
VCC+0.3
0.8
70
85
V
V
V
o
C
o
C
TA 0 to 70 oC
DC Electrical Characteristics (VCC=5V±10%)
Parameter
I/P Leakage Current
Symbol Test Condition
Min Typ
max
Unit
ILI
0V < VIN < VCC
-16
-
16
µA
Output Leakage Current
ILO
CS = VIH, VI/O = GND to VCC
-16
-
16
µA
Operating Current
ICC1
Min. Cycle, CS = VIL,VIL<VIN<VIH
-
-
170
mA
TTL levels
ISB1
CS = VIH
-
-
48
mA
CMOS levels
ISB2
CS > VCC-0.2V, 0.2<VIN<VCC-0.2V
-
-
32
mA
-L Version (CMOS)
ISB3
CS > VCC-0.2V, 0.2<VIN<VCC-0.2V
-
-
2
mA
VOL
IOL = 8.0mA
-
-
0.4
V
VOH
IOH = -4.0mA
2.4
-
-
V
Address,OE,WE
Standby Supply Current
Output Voltage
Typical values are at VCC=5.0V,TA=25oC and specified loading.
Add 800mA to -L CMOS standby currents to obtain industrial temp range parameters.
Capacitance (VCC=5V±10%,TA=25oC)
Parameter
Input Capacitance (Address,OE,WE)
I/P Capacitance (other)
I/O Capacitance
Note: Capacitance calculated, not measured.
Symbol Test Condition
CIN1
CIN2
CI/O
VIN = 0V
VIN = 0V
VI/O = 0V
2
max
Unit
128
10
160
pF
pF
pF
SYS88000RKX - 70/85/10/12
ISSUE 1.4 : January 1999
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
I/O Pin
645Ω
* Input rise and fall times: 5ns
1.76V
* Input and Output timing reference levels: 1.5V
100pF
* Output load: see diagram
* VCC=5V±10%
Operation Truth Table
CS
OE
WE
DATA PINS
SUPPLY CURRENT
MODE
H
X
X
High Impedance
ISB1 , ISB2 , ISB3, ISB4
Standby
L
L
L
Invalid State
~
Invalid
L
L
H
Data Out
ICC1
Read
L
H
L
Data In
ICC1
Write
L
H
H
High-Impedance
ICC1
High-Z
Notes : H = VIH : L =VIL : X = VIH or VIL
OE must not be tied low permanently.
Low Vcc Data Retention Characteristics - L Version Only
Parameter
Symbol
VCC for Data Retention
VDR
Data Retention Current
ICCDR1 (2)
Chip Deselect to Data Retention Time tCDR
Operation Recovery Time
tR
Notes
Test Condition
min
typ(1)
max
CS > VCC-0.2V
VCC = 3.0V, CS > VCC-0.2V
See Retention Waveform
See Retention Waveform
2.0
0
5.0
-
1.2
-
(1)
Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
(3) Add 840mA to -L CMOS standby currents to obtain industrial temp range parameters.
3
Unit
V
mA
ns
ms
ISSUE 1.4 : January 1999
SYS88000RKX - 70/85/10/12
AC OPERATING CONDITIONS
Read Cycle
-70
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
-85
-10
-12
Symbol
min
max
min
max
min
max
min
max
Unit
tRC
tAA
tACS
tOE
tOH
tCLZ
tOLZ
tCHZ
tOHZ
70
11.5
1.5
1.5
0
0
70
70
40
5
5
85
11.5
1.5
1.5
0
0
85
85
50
5
5
100
11.5
1.5
1.5
0
0
100
100
55
5
5
120
11.5
1.5
1.5
0
0
120
120
60
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-70
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
***
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write ***
-85
-10
-12
Symbol
min
max
min
max
min
max
min
max
Unit
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
tDW
tDH
tOW
70
60
60
0
50
5
0
35
0
5
30
-
85
75
75
0
60
5
0
40
0
5
35
-
100
80
80
0
70
5
0
45
0
5
40
-
120
100
100
0
70
5
0
45
0
5
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*** Theses signals are the internal Ram signals on the module and are included to assist control signal
timing.
4
SYS88000RKX - 70/85/10/12
ISSUE 1.4 : January 1999
Read Cycle Timing Waveform (1,2)
t RC
Address
t AA
OE
t OE
t OH
t OLZ
CS
t ACS
Don't
care.
t OHZ (3)
t CLZ (4,5)
Dout
Data Valid
t CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
tWC
Address
t WR(7)
OE
t AS(6)
t AW
t CW
CS
Don't
Care
WE
t OHZ(3,9)
t OW
t WP(2)
High-Z
Dout
t DW
Din
High-Z
t DH
Data Valid
5
(8)
ISSUE 1.4 : January 1999
SYS88000RKX - 70/85/10/12
Write Cycle No.2 Timing Waveform
(1,5)
tWC
Address
t AS(6)
t WR(7)
t CW
CS
t AW
t WP(2)
WE
tOH
t WHZ(3,9)
t OW
High-Z
Dout
t DW
(8)
(4)
Don't
Care
t DH
High-Z
Din
Data Valid
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS and WE low.
(3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state.
Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes.
(7) CS or WE must be high during address transitions.
(8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the
output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
tCDR
tR
2.2V
2.2V
V DR
CS
CS > Vcc -0.2V
0V
6
SYS88000RKX - 70/85/10/12
Package Information
ISSUE 1.4 : January 1999
Dimensions in mm
97.25 max
30.25 max
4.40 max
3.50 +/- 0.50
0.50 typ.
2.54 typ
Ordering Information
SYS88000RKXLI - 70
Speed
70
85
10
12
=
=
=
=
70ns
85ns
100ns
120ns
Temperature Range
Blank = Commercial Temperature
I = Industrial Temperature
Power Consumption
Blank = Standard
L = Low Power
Package
RKX = Plastic 38 pin SIP
Organization
88000 = 8M x 8
Memory Type
SYS = Static RAM
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our Products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval
of a company director
7
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