datasheet for VL33B2K63A

Product Specifications

PART NO.:

VL33B2K63A-K0/K9/F8S REV: 1.0

General Information

16GB 2Gx72 DDR3 SDRAM ECC REGISTERED DIMM 240-PIN

Description

The VL33B2K63A is a 2Gx72 DDR3 SDRAM high density RDIMM. This memory module is four rank, consists of thirty-six CMOS 512Mx8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages, a 28-bit registered buffer/PLL clock in BGA package, and a 2K EEPROM in an 8-pin MLF package. This module is a 240-pin registered dual in-line memory module and is intended for mounting into an edge connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM.

240-pin, registered dual in-line memory module (RDIMM)

Supports ECC error detection and correction

Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500

VDD = VDDQ = 1.5V +/-0.075V

JEDEC standard 1.5V +/-0.075V I/O (SSTL_15 )

VDDSPD = 3.0V to 3.6V

Eight internal component banks for concurrent operation

8-bit

Bi-directional differential data-strobe

Nominal and dynamic on-die termination (ODT)

ZQ calibration support

Programmable CAS# latency:

11(DDR3-1600), 9 (DDR3-1333), 7 (DDR3-1066)

Programmable burst; length (8)

Average refresh period 7.8 us

• reset

Fly-by

On board terminated command, address, and control bus

Serial presence detect (SPD) with EEPROM

Gold edge contacts

Lead-free, RoHS compliant

PCB:

Operating temperature (T

OPER

): - Commercial (0 o

- Industrial (-40 o

C <= Tc <= 95

C <= Tc <= 95 o o

C)

C)

Notes: Double refresh rate is required when 85 o

C < T

OPER

< =95 o

C.

T

OPER

is DRAM case temperature (Tc)

Order Information:

VL33B2K63A K0 S X -

X

OPERATING TEMPERATURE

None: Commercial

S1: Industrial screening

DRAM DIE (Option)

DRAM MANUFACTURER

S - SAMSUNG

MODULE SPEED

K0: PC3-12800 @ CL11

K9: PC3-10600 @ CL9

F8: PC3-8500 @ CL7

VL: Lead-free/RoHS

Pin Name

A12/BC#

DQS0#~DQS8#

CB0~CB7

ERR_OUT#

CK0, CK0#

ODT0, ODT1

CKE0, CKE1

CS0# ~ CS3#

RAS#

CAS#

RESET#

Parity Error Output

Clock Input

On-die Termination Control

Clock Enables

Chip Selects

Row Address Strobes

Column Address Strobes

VSS Ground

SDA

SCL

VREFCA

VREFDQ

VDDSPD

Function

Address Input/ Burst Chop

Data Strobes Complement

Data Check Bits I/O

Register and SDRAM Control

SPD Data Input/Output

SPD Clock Input

Reference Voltage for CA

Reference Voltage for DQ

SPD Voltage Supply

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Product Specifications

PART NO.:

VL33B2K63A-K0/K9/F8S REV: 1.0

240-PIN DDR3 RDIMM FRONT SIDE

Pin Configuration

240-PIN DDR3 RDIMM BACK SIDE

Pin Name Pin Name Pin Name Pin Name

2 VSS 32 VSS 62 VDD 92 VSS

3

VREFDQ 121 VSS 151 VSS 181 A1 211 VSS

DQ0 33 DQS3# 63 CK1 * 93 DQS5# 123 DQ5 153 NC 183 VDD 213 NC

* 124 VSS 154 VSS

5 VSS 35 VSS 65 VDD 95 VSS

7 DQS0 37 DQ27

96 126 NC 156

67 VREFCA 97 DQ43 127 VSS 157 VSS 187 EVENT#* 217 VSS

128 DQ6 158 CB4 188 A0 218 DQ52

9 DQ2 39 CB0 69 VDD 99 DQ48 129 DQ7 159 CB5 189

100 BA1 220 VSS

11 VSS 41 VSS 71 BA0 VDD 221 DM6

102 132 DQ13 162 NC 192

103 133 VSS 163 VSS 193

CAS# 134 DM1 164 CB6 194

15 DQS1# 45 CB2 75 VDD 105 DQ50 135 NC 165 CB7 195 ODT0 225 DQ55

136 VSS 166 VSS 196 A13 226 VSS

ODT1 137 TEST 197

18 DQ10 48 VTT 78 VDD 108 DQ56

19 DQ11 49 VTT 79 CS2# 109 DQ57 139 VSS 169 CKE1 199 VSS 229 VSS

20 VSS 50 CKE0 80 VSS 140 DQ20 170 VDD 200

111 A15 201 DQ37 231 NC

22 DQ17 52 BA2 82 DQ33 142 VSS 172 202 VSS 232 VSS

114 144 NC 174

145 VSS 175 A9 205 VSS 235 VSS

26 VSS 56 A7 86 VSS 146 DQ22 176 VDD 206

148 VSS 178 A6 208 VSS 238 SDA

*: These pins are not used in this module.

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PART NO.:

Function Block Diagram

Product Specifications

VL33B2K63A-K0/K9/F8S REV: 1.0

RCS3#

RCS2#

RCS1#

RCS0#

DQS0

DQS0#

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Vss

DQS1

DQS1#

DM1

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D0

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D9

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D18

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D27

ZQ

Vss

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

Vss

DQS2

DQS2#

DM2

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D1

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D10

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D19

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D28

ZQ

Vss

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

Vss

DQS3

DQS3#

DM3

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D2

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D11

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D20

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D29

ZQ

Vss

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

Vss

DQS8

DQS8#

DM8

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D3

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D12

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D21

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D30

ZQ

Vss

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D8

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D17

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D26

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D35

ZQ

Vss

CS3#

CS2#

CS1#

CS0#

A0-A15

BA0-BA2

RAS#

CAS#

WE#

CKE0

ODT0

CKE1

ODT1

CK0

CK0#

22 ohm +/-5%

120 ohm

+/-1%

R

/

P

L

L

1:2

R

E

G

I

S

T

E

PAR_IN

RESET#

22 ohm +/-5%

QERR#

RST #

Err_Out#

RCS3# -> CS3#: SDRAMs D27-D35

RCS2# -> CS2#: SDRAMs D18-D26

RCS1# -> CS1#: SDRAMs D9-D17

RCS0# -> CS0#: SDRAMs D0-D8

RA0-RA15 -> A0-A15: SDRAMs D0-D35

RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D35

RRAS# -> RAS#: SDRAMs D0-D35

RCAS# -> CAS#: SDRAMs D0-D35

RWE# -> WE#: SDRAMs D0-D35

RCKE0 -> CKE0: SDRAMs D0-D17

RODT0 -> ODT0: SDRAMs D0-D17

RCKE1 -> CKE1: SDRAMs D18-D35

RODT1 -> ODT1: SDRAMs D18-D35

PCK0

PCK0#

RESET#: SDRAMs D0-D35

DQS4

DQS4#

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

Vss

DQS5

DQS5#

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

Vss

DQS6

DQS6#

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

Vss

DQS7

DQS7#

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D4

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D13

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D22

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D31

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D5

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D14

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D23

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D32

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D6

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D15

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D24

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D33

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D7

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D16

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D25

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D34

ZQ

Vss

Command, address, control, and clock line terminations

RA0-RA15, RBA0-RBA2

RRAS#, RCAS#, RWE#,

RCKE0, RODT0, RCKE1, RODT1

RCS0#, RCS1#, RCS2#, RCS3#

DDR3

SDRAM

39 ohm +/-5%

VTT

PCK0

PCK0#

DDR3

SDRAM

36 ohm +/-5%

0.1uF

VDD

Serial PD

SCL

Vss

WP

A0 A1 A2

SA0 SA1 SA2

SDA

VDDSPD

VDD

VTT

VREFCA

VREFDQ

VSS

Serial PD

D0-D35

D0-D35

D0-D35

D0-D35

D0-D35

Notes:

1. Unless otherw ise noted, resistor values are 15 ohms +/-5%

2. ZQ resistors are 240 ohms +/-1%

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Product Specifications

PART NO.:

VL33B2K63A-K0/K9/F8S

Absolute Maximum Ratings

Symbol Parameter

VDD Voltage on VDD pin relative to VSS

VDDQ Voltage on VDDQ pin relative to VSS

VIN, VOUT Voltage on any pin relative to VSS

-0.4

-0.4

-0.4

-55

Address, BA,

RAS#, CAS#,WE#,

CS#, CKE, ODT

IL

Input leakage current; Any input 0V<VIN<VDD;

VREF input 0V<VIN<0.95V;

Other pins not under test = 0V

CK, CK# -5

REV: 1.0

1.975

1.975

1.975

100

150 uA

V

V

V

0

C

IOZ

IVREF

Output leakage current;

0V<VOUT<VDDQ; DQs and ODT are disabled

DQ, DQS, DQS#

VREF supply leakage current; VREF = Valid VREF level

-20

-36

20

36 uA uA

DC Operating Conditions

Symbol Parameter Min Max

1.425 1.5 1.575 V 1,2

VDDQ I/O Supply Voltage

VREFDQ (DC) I/O reference voltage DQ bus

VREFCA (DC) Input reference voltage CMD/ADD bus

1.425

0.49 x VDD

0.49 x VDD

1.5

0.5 x VDD

0.5 x VDD

1.575

0.51 x VDD

0.51 x VDD

V

V

V

1,2

3,4

3,4

VTT Termination Reference Voltage -0.483 x VDDQ 0.5 x VDDQ +0.517 x VDDQ V

Notes:

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD

4. For reference: approximate VDD/2 +/-15mV.

5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce timing margins.

5

Operating Temperature Condition

Symbol Parameter

T

OPER

Operating

Commercial

Industrial

Rating Units Notes

0 to 95

-40 to +95

0

C 1,2

Notes:

1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51-2.

2. At -40 to +85

85 o o

C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when

C < TOPER <= 95 o

C.

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Product Specifications

PART NO.:

VL33B2K63A-K0/K9/F8S REV: 1.0

Input DC Logic Level

All voltages referenced to VSS

Symbol Parameter Min Unit

Command and Address

VIHCA(DC)

Input High (Logic 1) Voltage

(DDR3-1066/1333/1600)

VILCA(DC) Input Low (Logic 0) Voltage

(DDR3-1066/1333/1600)

VREF + 0.100

VSS

VDD

VREF - 0.100

V

V

DQ and DM

VIHDQ(DC)

VILDQ(DC)

Input High (Logic 1) Voltage (DDR3-1066/1333/1600)

Input Low (Logic 0) Voltage (DDR3-1066/1333/1600)

VREF + 0.100

VSS

VDD

VREF - 0.100

V

V

Input AC Logic Level

All voltages referenced to VSS

Symbol Parameter Min Unit

Command and Address

VIHCA(AC)

VILCA(AC)

Input High (Logic 1) Voltage

(DDR3-1066/1333/1600)

Input Low (Logic 0) Voltage

(DDR3-1066/1333/1600)

DQ and DM

VIHDQ(AC)

VILDQ(AC)

VIHDQ(AC)

VILDQ(AC)

Input High (Logic 1) Voltage

(DDR3-1066)

Input Low (Logic 0) Voltage (DDR3-1066)

Input High (Logic 1) Voltage (DDR3-1333/1600)

Input Low (Logic 0) Voltage

(DDR3-1333/1600)

VREF + 0.175

-

VREF + 0.175

-

VREF + 0.150

-

Input/Output Capacitance

TA=25

0

C, f=100MHz

-

VREF - 0.175

-

VREF - 0.175

-

VREF - 0.150

V

V

V

V

V

V

Input capacitance (A0~A15, BA0~BA2, RAS#, CAS#, WE#)

Input capacitance (CKE0, CKE1), (ODT0, ODT1), (CS0# ~CS3#)

Input capacitance (CK0, CK0#)

Input/Output capacitance

(DQ, DQS, DQS#, DM, CB)

K0 (DDR3-1600)

K9 (DDR3-1333)

F8 (DDR3-1066)

CIN1

CIN2

CIN3

CIO

5.5

5.5

5.5

10

10

6.5

6.5

6.5

14

14.8 pF pF pF pF pF

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Product Specifications

PART NO.:

VL33B2K63A-K0/K9/F8S REV: 1.0

IDD Specification

(DDR3-1333)

(DDR3-1066)

E7

(DDR3-800)

Unit

Operating one bank active-precharge current;

tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,

CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD); CKE is HIGH,

CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as IDD4W.

Precharge power-down current;

All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge standby current;

All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING.

Precharge quiet standby current;

All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

Active power-down current;

All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING.

Active standby current;

All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS

MAX(IDD)); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING.

Operating burst read current;

All device banks open; Continuous burst reads; IOUT = 0mA; BL = 8; CL

= CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data pattern is same as IDD4W.

Operating burst write current;

All device banks open; Continuous burst writes; BL = 8; CL = CL(IDD);

AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data bus inputs are SWITCHING.

Burst refresh current;

tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is

HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Self refresh current;

CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING.

Operating bank interleave read current;

All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs;

Data pattern is same as IDD4R.

IDD0* 1045 1000 955 mA

IDD1* 1180 1135 1090 mA

IDD2P-F** 820 820 820 mA

IDD2P-S** 640 640 640 mA

IDD2N** 1180 1180 1000 mA

IDD2Q** 1180 1000 1000 mA

IDD3P** 1180 1000 1000 mA

IDD3N** 1900 1720 1540 mA

IDD4R* 1630 1495 1360 mA

IDD4W* 1765 1675 1450 mA

IDD5** 6580 6220 5680 mA

IDD6** 540 540 540 mA

IDD7* 2395 2350 1990 mA

Note: IDD specification is based on Samsung A-die components.

*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.

**: Value calculated reflects all module ranks in this operating condition.

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Product Specifications

PART NO.:

VL33B2K63A-K0/K9/F8S REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9 F8

(DDR3-1066)

Unit

MIN MAX MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - 8 - ns

Average Clock Period tCK(avg)

Clock Period

Average high pulse width

Average low pulse width

Clock Period Jitter tCK(abs) tCH(avg) tCL(avg) tJIT(per)

1.25 <1.50 1.5 <1.875 1.875 <2.5 tCK(avg)min

+

tJIT(per)min tCK(avg)max

+ tJIT(per)max tCK(avg)min

+ tJIT(per)min tCK(avg)max

+ tJIT(per)max tCK(avg)min

+ tJIT(per)min tCK(avg)max

+

tJIT(per)max

0.47 0.53 0.47 0.53 0.47 0.53 ns ns tCK(avg)

0.47

-70

0.53

70

0.47

-80

0.53

80

0.47

-90

0.53

90 tCK(avg) ps

Clock Period Jitter during DLL locking period

Cycle to Cycle Period Jitter

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

Cumulative error across n = 13, 14 ... 49, 50 cycles

Absolute clock HIGH pulse width

Absolute clock Low pulse width

Data Timing

DQS,DQS# to DQ skew, per group, per access

DQ output hold time from DQS, DQS#

DQ low-impedance time from CK, CK#

DQ high-impedance time from CK, CK#

Data setup time to DQS, DQS# referenced to Vih(ac)Vil(ac) levels

Data hold time to DQS, DQS# referenced to Vih(ac)Vil(ac) levels

DQ and DM Input pulse width for each input tJIT(per, lck) tJIT(cc) tJIT(cc, lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) tERR(nper) tCH(abs) tCL(abs) tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) tDH(base) tDIPW

-

0.38

-450

-

10

45

360

-60 60 -70 70 -80 80

-155

-163

-169

-175

-103

-122

-136

-147

-180

-184

-188

0.43

0.43

140

120

160

140

155

163

169

175

103

122

136

147

-118

-140

-155

-168

-177

-186

-193

-200

118

140

155

168

177

186

193

200

180

184

-205

-210

205

210

-231

-237

188 -215 215 -242 tERR(nper)min =(1+ 0.68ln(n))*tJIT(per)min

tERR(nper)max=(1+ 0.68ln(n))*tJIT(per)max

- 0.43 - 0.43

- 0.43 - 0.43

-200

-209

-217

-224

-132

-157

-175

-188

180

160

200

209

217

224

132

157

175

188

231

237

242

-

-

-

-

-

100

-

225

225

-

0.38

-500

-

30

65

400

-

-

-

125

-

250

250

-

0.38

-600

-

25

100

490

-

-

-

150

-

300

300 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK(avg) tCK(avg) ps tCK(avg) ps ps ps ps ps

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Product Specifications

PART NO.:

VL33B2K63A-K0/K9/F8S REV: 1.0

Data Strobe Timing

DQS, DQS# READ Preamble

DQS, DQS# differential READ Postamble

DQS, DQS# output high time

DQS, DQS# output low time

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9 F8

(DDR3-1066)

Unit

MIN MAX MIN MAX MIN MAX

tRPRE tRPST tQSH tQSL

0.9

0.3

0.4

0.4

-

-

-

-

0.9

0.3

0.4

0.4

-

-

-

-

0.9

0.3

0.38

0.38

-

-

-

- tCK tCK tCK(avg) tCK(avg)

DQS, DQS# rising edge output access time from rising CK, CK#

DQS, DQS# low-impedance time (Referenced from

RL-1)

DQS, DQS# high-impedance time (Referenced from RL+BL/ 2)

DQS, DQS# differential input low pulse width

DQS, DQS# differential input high pulse width

DQS, DQS# rising edge to CK, CK# rising edge

DQS,DQS# failing edge setup time to CK, CK# rising edge

DQS,DQS# failing edge hold time to CK, CK# rising edge

Command and Address Timing

tDQSCK -225 tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH

-

0.45

0.45

-0.27

0.18

0.18

225 -255

225

0.55

0.55

0.27

-

-

-

0.45

0.45

-0.25

0.2

0.2

255

250

0.55

0.55

0.25

-

-

-300

-

0.45

0.45

-0.25

0.2

0.2

300 ps

300

0.55

0.55

0.25

-

- ps tCK tCK tCK(avg) tCK(avg) tCK(avg)

Internal READ Command to PRECHARGE Command delay

Delay from start of internal write transaction to internal read command

Mode Register Set command cycle time

Mode Register Set command update delay

CAS# to CAS# command delay

Auto precharge write recovery + precharge time

Multi-Purpose Register Recovery Time

ACTIVE to PRECHARGE command period

ACTIVE to ACTIVE command period for 1KB page size

ACTIVE to ACTIVE command period for 2KB page size

Four activate window for 1KB page size

Four activate window for 2KB page size

Command and Address setup time to CK, CK# referenced to Vih(ac) /

Vil(ac) levels

Command and Address hold time from CK, CK# referenced to Vih(ac) /

Vil(ac) levels

Control & Address Input pulse width for each input tRTP tWTR max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- tMRD tMOD tCCD tDAL(min) tMPRR tRAS tRRD tRRD tFAW tFAW

4 max

(12tCK,15ns)

4

1

35 max

(4tCK,6ns) max

(4tCK,7.5ns)

30

40

-

-

-

4 max

(12tCK,15ns)

4

-

-

-

4 max

(12tCK,15ns)

4

-

9*tREFI

WR + roundup (tRP / tCK(AVG))

1 -

9*tREFI

-

-

-

36 max

(4tCK,6ns) max

(4tCK,7.5ns)

30

-

-

-

1

37.5 max

(4tCK,7.5ns) max

(4tCK,10ns)

37.5

- 45 - 50

- nCK

-

- nCK nCK nCK -

9*tREFI ns

-

-

- ns

- ns tIPW 560 - 620 - 780 - ps

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Product Specifications

PART NO.:

VL33B2K63A-K0/K9/F8S REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9 F8

(DDR3-1066)

Unit

MIN MAX MIN MAX MIN MAX

Refresh Timing

4Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval

Average periodic refresh interval

(0°C<= TCASE <= 85 °C)

Average periodic refresh interval

(85°C<= TCASE <= 95 °C)

Calibration Timing

Power-up and RESET calibration time tRFC 300 - 300 - 300 - ns

Normal operation Full calibration time

Normal operation Short calibration time

Reset Timing

tZQinitI tZQoper tZQCS

512

256

64

-

-

-

512

256

64

-

-

-

512

256

64

-

-

- tCK tCK tCK

Exit Reset from CKE HIGH to a valid command tXPR max

(5tCK, tRFC

+ 10ns)

- max

(5tCK, tRFC

+ 10ns)

- max

(5tCK, tRFC

+ 10ns)

-

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL tXS - - -

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

Valid Clock Requirement after Self Refresh Entry (SRE) tXSDLL tCKESR tCKSRE tCKSRX max(5tC, tRFC+10ns) tDLLK(min) tCKE(min) +

1tCK max(5tC,

10ns) max(5tC,

10ns)

-

-

-

- max(5tC, tRFC+10ns) tDLLK(min) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

-

- max(5tC, tRFC +10ns) tDLLK(min) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

-

- nCK

Valid Clock Requirement before Self Refresh Exit (SRX)

Power Down Timing

Exit Power Down with DLL to any valid command; Exit Precharge Power

Down with DLL frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL

CKE minimum pulse width

Command pass disable delay tXP tXPDLL tCKE tCPDED max

(3tCK,6ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1

-

-

-

- max

(3tCK,6ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1

-

-

-

- max

(3tCK,7.5ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1

-

-

-

- nCK

Power Down Entry to Exit Timing

Timing of ACT command to Power Down entry tPD tACTPDEN tCKE(min) 9*tREFI

1 - tCKE(min)

1

9*tREFI

- tCKE(min)

1

9*tREFI

- tCK nCK

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power Down entry

Timing of WR command to Power Down entry BL8 (OTF, MRS), BL4OTF

Timing of WRA command to Power Down entry BL8 (OTF, MRS), BL4OTF

Timing of WR command to Power Down entry (BL4MRS)

Timing of WRA command to Power Down entry (BL4MRS)

Timing of REF command to Power Down entry tPRPDEN 1 tRDPDEN tWRPDEN tWRAPDEN tWRPDEN tWRAPDEN tREFPDEN

RL + 4 +1

WL + 4

+(tWR/ tCK)

WL+4+WR+

1

WL + 2

+(tWR/ tCK)

WL+2+WR+

1

1 tMRSPDEN tMOD(min) Timing of MRS command to Power Down entry

- 1 - 1 - nCK

-

-

RL + 4 +1

WL + 4

+(tWR/ tCK)

-

-

RL + 4 +1

WL + 4

+(tWR/ tCK)

-

- nCK

- WL+4+WR+1 - WL+4+WR+1 - nCK

-

WL + 2

+(tWR/ tCK)

-

WL + 2

+(tWR/ tCK)

- nCK

- WL+2+WR+1 - WL+2+WR+1 - nCK

- 1 - 1 -

- tMOD(min) - tMOD(min) -

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Product Specifications

PART NO.:

VL33B2K63A-K0/K9/F8S REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9 F8

(DDR3-1066)

Unit

MIN MAX MIN MAX MIN MAX

ODT Timing

ODT high time without write command or with write command and BC4 ODTH4 4 - 4 - 4 - nCK

ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - nCK tAONPD tAOFPD tAON

2

2

-225

8.5

8.5

225

2

2

-250

8.5

8.5

250

2

2

-300

8.5

8.5

300 ns ns ps

Asynchronous RTT turn-on delay (Power-Down with DLL frozen)

Asynchronous RTT turn-off delay (Power-Down with DLL frozen)

ODT turn-on

RTT_NOM and RTT_WR turn-off time from ODTL off reference

RTT dynamic change skew

Write Leveling Timing

First DQS pulse rising edge after tDQSS margining mode is programmed

DQS/DQS delay after tDQS margining mode is programmed

Setup time for tDQSS latch

Hold time for tDQSS latch

Write leveling output delay

Write leveling output error tADC tWLMRD tWLDQSEN tWLS tWLH tWLO tWLOE

0.3

40

25

165

165

0

0

0.7

-

-

-

-

7.5

2

0.3

40

25

195

195

0

0

0.7

9

2

-

-

-

-

0.3

40

25

245

245

0

0

0.7

9

2

-

-

-

- tCK(avg) tCK tCK ps ps ns ns

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PART NO.:

Package Dimensions

Product Specifications

VL33B2K63A-K0/K9/F8S REV: 1.0

FRONT VIEW

133.35

3.0 TYP (4X)

2.50 D (2X)

2.30 TYP

2.20 TYP

1.45 TYP

0.75 R

PIN 1

1.50 +/- 0.10

54.68 TYP

123.00 TYP

BACK VIEW

1.00 TYP 0.80 TYP

0.70 R MAX (8X)

3.05 TYP

PIN 240

5.00 TYP

71.00 TYP 47.00 TYP

PIN 121

3.67

MAX

9.50

PIN 120

17.30

30.00

1.27 +/- 0.10

Note: 1. All dimensions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.

2. The dimensional diagram is for reference only.

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Revision History:

PART NO.:

Product Specifications

VL33B2K63A-K0/K9/F8S REV: 1.0

03/29/2011 1.0 All Spec

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