Compaq Evo D500 - Convertible Minitower Reference Guide

Technical Reference Guide

For

Compaq Evo D300/D500 Personal Computers and

W4000 Workstations

Covers Small Form Factor, Desktop, and Configurable Minitower Models

Featuring the

Intel Pentium 4 Processor and the 845 Chipset

This document is designed to fit into a standard 3-ring binder. Provided below is a title block that can be copied and/or cut out and placed into a slip or taped onto the binder.

Evo D300/D500 Personal Computers and

W4000 Workstations

Featuring the Intel Pentium 4 Processor

TRG

Technical Reference Guide

NOTICE

© 2002 Compaq Information Technologies Group, L.P.

Compaq, the Compaq logo, Deskpro, and Evo are trademarks of the Compaq Information

Technologies Group, L.P. iPAQ is a trademark of Compaq Information Technologies

Group, L.P. in the United States and other countries. Microsoft, MS-DOS, Windows,

Windows NT are trademarks of Microsoft Corporation in the United States and other countries. Intel, Pentium, Intel Inside, and Celeron are trademarks of Intel Corporation in the U. S. and/or other countries. The Open Group, Motif, OSF/1, UNIX, the "X" device, and IT DialTone are trademarks of The Open Group in the U. S. and other countries.

All other product names mentioned herein may be trademarks of their respective companies.

Compaq shall not be liable for technical or editorial errors or omissions contained herein.

The information in this document is provided “as is” without warranty of any kind and is subject to change without notice. The warranties for Compaq products are set forth in the express limited warranty statements accompanying such products. Nothing herein should be construed as constituting an additional warranty.

For more information regarding specifications and Compaq-specific parts please contact Compaq

Computer Corporation.

For more information regarding specifications and Compaq-specific parts please contact Compaq

Computer Corporation.

Technical Reference Guide for

Compaq Evo D300/D500 Personal Computers and W4000 Workstations

First Edition - April 2002

Second Edition – January 2003

Document Part Number 329001-001

Compaq Evo and Workstation Personal Computers i

Featuring the Intel Pentium 4 Processor

Second Edition - January 2003

Technical Reference Guide ii Compaq Evo and Workstation Personal Computers


Second Edition –- January 2003


TABLE OF CONTENTS

CHAPTER 1 INTRODUCTION ..................................................................................................................

1.1 ABOUT THIS GUIDE ................................................................................................................ 1-1

VIEWING............................................................................................................ 1-1

1.1.2 HARDCOPY ....................................................................................................................... 1-1

1.2 ADDITIONAL INFORMATION SOURCES............................................................................. 1-2

1.3 MODEL NUMBERING CONVENTION ................................................................................... 1-2

1.4 SERIAL NUMBER ..................................................................................................................... 1-2

1.5 NOTATIONAL CONVENTIONS.............................................................................................. 1-3

1.5.1 VALUES ............................................................................................................................. 1-3

1.5.2 RANGES ............................................................................................................................. 1-3

1.5.3 REGISTER NOTATION AND USAGE ............................................................................ 1-3

1.5.4 BIT NOTATION AND BYTE VALUES ........................................................................... 1-3

1.6 COMMON ACRONYMS AND ABBREVIATIONS ................................................................. 1-4

CHAPTER 2 SYSTEM OVERVIEW ..........................................................................................................

2.1 INTRODUCTION....................................................................................................................... 2-1

2.2 FEATURES AND OPTIONS...................................................................................................... 2-2

FEATURES .................................................................................................. 2-2

2.2.2 OPTIONS ............................................................................................................................ 2-3

2.3 MECHANICAL DESIGN ........................................................................................................... 2-4

LAYOUTS ........................................................................................................ 2-5

LAYOUTS ......................................................................................................... 2-7

2.4 SYSTEM ARCHITECTURE .................................................................................................... 2-12

2.4.1 INTEL PENTIUM 4 PROCESSOR .................................................................................. 2-14

2.4.2 CHIPSET........................................................................................................................... 2-15

COMPONENTS.............................................................................................. 2-15

MEMORY ........................................................................................................ 2-16

STORAGE............................................................................................................. 2-16

2.4.6 SERIAL AND PARALLEL INTERFACES ..................................................................... 2-16

2.4.7 UNIVERSAL SERIAL BUS INTERFACE...................................................................... 2-16

2.4.8 NETWORK INTERFACE CONTROLLER..................................................................... 2-16

2.4.9 GRAPHICS

SUBSYSTEM...................................................................................................... 2-18

2.5 SPECIFICATIONS ................................................................................................................... 2-18

CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM.............................................................................

3.1 INTRODUCTION....................................................................................................................... 3-1

3.2 PENTIUM 4 PROCESSOR......................................................................................................... 3-2

OVERVIEW ................................................................................................ 3-2

UPGRADING.............................................................................................. 3-4

3.3 MEMORY SUBSYSTEM........................................................................................................... 3-5

3.4 SUBSYSTEM CONFIGURATION............................................................................................ 3-8

Compaq Evo and Workstation Personal Computers iii




CHAPTER 4 SYSTEM SUPPORT ..............................................................................................................

4.1 INTRODUCTION....................................................................................................................... 4-1

4.2 PCI BUS OVERVIEW ................................................................................................................ 4-2

4.2.1 PCI BUS TRANSACTIONS............................................................................................... 4-3

4.2.2 PCI BUS MASTER ARBITRATION ................................................................................. 4-6

4.2.3 OPTION ROM MAPPING ................................................................................................. 4-7

INTERRUPTS.............................................................................................................. 4-7

4.2.5 PCI POWER MANAGEMENT SUPPORT........................................................................ 4-7

SUB-BUSSES .............................................................................................................. 4-7

CONFIGURATION ..................................................................................................... 4-8

CONNECTOR ............................................................................................................. 4-9

4.3 AGP BUS OVERVIEW ............................................................................................................ 4-10

TRANSACTIONS.................................................................................................... 4-10

CONNECTOR.......................................................................................................... 4-14

4.4 SYSTEM RESOURCES ........................................................................................................... 4-15

4.4.1 INTERRUPTS................................................................................................................... 4-15

4.4.2 DIRECT MEMORY ACCESS.......................................................................................... 4-19

4.5 SYSTEM CLOCK DISTRIBUTION ........................................................................................ 4-22

4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY.................................................. 4-23

CMOS........................................................................................................... 4-23

4.6.2 CMOS ARCHIVE AND RESTORE................................................................................. 4-24

4.6.3 STANDARD CMOS LOCATIONS ................................................................................. 4-24

4.7 SYSTEM MANAGEMENT...................................................................................................... 4-25

MANAGEMENT ............................................................................................... 4-27

STATUS ........................................................................................................... 4-27

4.7.4 THERMAL SENSING AND COOLING ......................................................................... 4-28

4.8 REGISTER MAP AND MISCELLANEOUS FUNCTIONS .................................................... 4-30

4.8.1 SYSTEM I/O MAP ........................................................................................................... 4-30

4.8.2 LPC47B367 I/O CONTROLLER FUNCTIONS .............................................................. 4-31

CHAPTER 5 INPUT/OUTPUT INTERFACES.......................................................................................... iv

5.1 INTRODUCTION....................................................................................................................... 5-1

5.2 ENHANCED IDE INTERFACE................................................................................................. 5-1

PROGRAMMING ....................................................................................................... 5-1

CONNECTOR ............................................................................................................. 5-3

5.3 DISKETTE DRIVE INTERFACE .............................................................................................. 5-4

5.3.1 DISKETTE DRIVE PROGRAMMING.............................................................................. 5-5

5.3.2 DISKETTE DRIVE CONNECTOR ................................................................................... 5-7

5.4 SERIAL INTERFACE ................................................................................................................ 5-8

INTERFACE.......................................................................................................... 5-8

5.4.2 COM1 PORT HEADER...................................................................................................... 5-9

5.4.3 SERIAL INTERFACE PROGRAMMING......................................................................... 5-9

5.5 PARALLEL INTERFACE........................................................................................................ 5-11

5.5.1 STANDARD PARALLEL PORT MODE ........................................................................ 5-11

5.5.2 ENHANCED PARALLEL PORT MODE........................................................................ 5-12

5.5.3 EXTENDED CAPABILITIES PORT MODE .................................................................. 5-12

5.5.4 PARALLEL INTERFACE PROGRAMMING ................................................................ 5-13

5.5.5 PARALLEL INTERFACE CONNECTOR ...................................................................... 5-15

Compaq Evo and Workstation Personal Computers




5.6 KEYBOARD/POINTING DEVICE INTERFACE................................................................... 5-16

5.6.1 KEYBOARD INTERFACE OPERATION ...................................................................... 5-16

5.6.2 POINTING DEVICE INTERFACE OPERATION .......................................................... 5-18

5.6.3 KEYBOARD/POINTING

DEVICE INTERFACE CONNECTOR ................................. 5-21

5.7 UNIVERSAL SERIAL BUS INTERFACE .............................................................................. 5-22

5.7.1 USB DATA FORMATS ................................................................................................... 5-22

PROGRAMMING .................................................................................................... 5-24

CONNECTOR.......................................................................................................... 5-25

5.7.4 USB CABLE DATA ......................................................................................................... 5-25

5.8 AUDIO SUBSYSTEM.............................................................................................................. 5-26

ANALYSIS............................................................................................. 5-26

5.8.2 AC97 AUDIO CONTROLLER ........................................................................................ 5-28

5.8.3 AC97 LINK BUS .............................................................................................................. 5-28

CODEC................................................................................................................ 5-29

SPECIFICATIONS ............................................................................................. 5-31

5.9 NETWORK INTERFACE CONTROLLER ............................................................................. 5-32

5.9.1 WAKE ON LAN SUPPORT............................................................................................. 5-33

5.9.2 ALERT ON LAN SUPPORT............................................................................................ 5-33

5.9.3 POWER MANAGEMENT SUPPORT............................................................................. 5-34

PROGRAMMING..................................................................................................... 5-35

CONNECTOR........................................................................................................... 5-36

SPECIFICATIONS ................................................................................................... 5-36

CHAPTER 6 POWER SUPPLY AND DISTRIBUTION...........................................................................

6.1 INTRODUCTION....................................................................................................................... 6-1

6.2 POWER SUPPLY ASSEMBLY/CONTROL ............................................................................. 6-1

6.2.1 POWER SUPPLY ASSEMBLY ......................................................................................... 6-2

CONTROL ........................................................................................................... 6-3

6.3 POWER DISTRIBUTION .......................................................................................................... 6-5

6.3.1 3.3/5/12 VDC DISTRIBUTION.......................................................................................... 6-5

6.3.2 LOW VOLTAGE PRODUCTION/DISTRIBUTION ........................................................ 6-7

6.4 SIGNAL DISTRIBUTION.......................................................................................................... 6-8

CHAPTER 7 BIOS ROM ..............................................................................................................................

7.1 INTRODUCTION....................................................................................................................... 7-1

7.2 ROM FLASHING ....................................................................................................................... 7-2

7.2.1 UPGRADING...................................................................................................................... 7-2

7.2.2 CHANGEABLE SPLASH SCREEN.................................................................................. 7-3

7.3 BOOT FUNCTIONS................................................................................................................... 7-4

7.3.1 BOOT DEVICE ORDER .................................................................................................... 7-4

7.3.2 NETWORK BOOT (F12) SUPPORT................................................................................. 7-4

7.3.3 MEMORY DETECTION AND CONFIGURATION ........................................................ 7-5

7.3.4 BOOT ERROR CODES...................................................................................................... 7-5

7.4 SETUP UTILITY ........................................................................................................................ 7-4

Compaq Evo and Workstation Personal Computers v




7.5 CLIENT MANAGEMENT FUNCTIONS ................................................................................ 7-12

7.5.1 SYSTEM ID AND ROM TYPE ....................................................................................... 7-14

RETRIEVE ............................................................................................................. 7-14

STATUS .............................................................................................. 7-15

7.5.4 DRIVE FAULT PREDICTION ........................................................................................ 7-15

7.6 PNP SUPPORT ......................................................................................................................... 7-15

7.6.1 SMBIOS ............................................................................................................................ 7-16

7.7 POWER MANAGEMENT FUNCTIONS ................................................................................ 7-17

7.7.1 INDEPENDENT PM SUPPORT ...................................................................................... 7-17

SUPPORT ............................................................................................................... 7-19

7.7.3 APM 1.2 SUPPORT.......................................................................................................... 7-19

7.8 USB LEGACY SUPPORT ........................................................................................................ 7-23

APPENDIX A ERROR MESSAGES AND CODES...................................................................................

A.1 INTRODUCTION...................................................................................................................... A-1

A.2 BEEP/KEYBOARD LED CODES............................................................................................. A-1

A.3 POWER-ON SELF TEST (POST) MESSAGES........................................................................ A-2

A.4 SYSTEM ERROR MESSAGES (1 XX XX )................................................................................. A-3

MEMORY ERROR MESSAGES (2 XX XX ) .......................................................................................... A-4

A.6 KEYBOARD ERROR MESSAGES (30 X XX )........................................................................... A-4

A.7 PRINTER ERROR MESSAGES (4 XX XX )................................................................................ A-5

A.8 VIDEO (GRAPHICS) ERROR MESSAGES (5 XX XX )............................................................. A-5

A.9 DISKETTE DRIVE ERROR MESSAGES (6 XX XX ) ................................................................ A-6

A.10 SERIAL INTERFACE ERROR MESSAGES (11 XX XX ).......................................................... A-6

A.11 MODEM COMMUNICATIONS ERROR MESSAGES (12 XX XX ) ......................................... A-7

A.12 SYSTEM STATUS ERROR MESSAGES (16 XX XX )............................................................... A-8

A.13 HARD DRIVE ERROR MESSAGES (17 XX XX ) ...................................................................... A-8

A.14 HARD DRIVE ERROR MESSAGES (19 XX XX ) ...................................................................... A-9

A.15 VIDEO (GRAPHICS) ERROR MESSAGES (24 XX XX )........................................................... A-9

A.16 AUDIO ERROR MESSAGES (3206XX ) ................................................................................ A-10

A.17 DVD/CD-ROM ERROR MESSAGES (33 XX XX )................................................................... A-10

A.18 NETWORK INTERFACE ERROR MESSAGES (60 XX XX ).................................................. A-10

A.19 SCSI INTERFACE ERROR MESSAGES (65 XX XX , 66 XX XX , 67 XX XX )............................. A-11

A.20 POINTING DEVICE INTERFACE ERROR MESSAGES (8601XX ) .................................... A-11

APPENDIX B ASCII CHARACTER SET ..................................................................................................

B.1 INTRODUCTION.......................................................................................................................B-1

APPENDIX C KEYBOARD .........................................................................................................................

C.1 INTRODUCTION.......................................................................................................................C-1

C.2 KEYSTROKE PROCESSING ....................................................................................................C-2

C.2.1 PS/2-TYPE KEYBOARD TRANSMISSIONS ..................................................................C-3

C.2.2 USB-TYPE KEYBOARD TRANSMISSIONS ..................................................................C-4

LAYOUTS ...................................................................................................C-5

C.2.4 KEYS...................................................................................................................................C-8

COMMANDS ............................................................................................C-11 vi

C.3 CONNECTORS ........................................................................................................................C-16





APPENDIX D COMPAQ/NVIDIA VANTA LT AGP GRAPHICS CARD .............................................

D.1 INTRODUCTION...................................................................................................................... D-1

D.2 FUNCTIONAL DESCRIPTION................................................................................................ D-2

D.3 DISPLAY MODES .................................................................................................................... D-3

D.4 SOFTWARE SUPPORT INFORMATION................................................................................ D-4

D.5 POWER MANAGEMENT AND CONSUMPTION ................................................................. D-4

D.6 CONNECTORS ......................................................................................................................... D-5

CONNECTOR ................................................................................................ D-5

APPENDIX E COMPAQ/NVIDIA QUADRO2 EX/MXR AGP GRAPHICS CARDS...........................

E.1 INTRODUCTION.......................................................................................................................E-1

E.2 FUNCTIONAL DESCRIPTION.................................................................................................E-2

E.3 DISPLAY MODES .....................................................................................................................E-3

E.4 SOFTWARE SUPPORT INFORMATION.................................................................................E-4

E.5 POWER MANAGEMENT AND CONSUMPTION ..................................................................E-4

E.6 CONNECTORS ..........................................................................................................................E-5

CONNECTOR .................................................................................................E-5

APPENDIX F COMPAQ/MATROX MILLENNIUM G450 AGP GRAPHICS CARD .........................

F.1 INTRODUCTION....................................................................................................................... F-1

F.2 FUNCTIONAL DESCRIPTION................................................................................................. F-2

F.3 DISPLAY MODES ..................................................................................................................... F-3

F.4 SOFTWARE SUPPORT INFORMATION................................................................................. F-4

F.5 POWER MANAGEMENT AND CONSUMPTION .................................................................. F-4

F.6 CONNECTORS .......................................................................................................................... F-5

CONNECTOR ................................................................................................. F-5

F.6.2 VIDEO FEATURE CONNECTOR .................................................................................... F-6

APPENDIX G COMPAQ/ADAPTEC SCSI HOST ADAPTER ...............................................................

G.1 INTRODUCTION...................................................................................................................... G-1

G.2 FUNCTIONAL DESCRIPTION................................................................................................ G-2

G.3 SCSI ADAPTER PROGRAMMING ......................................................................................... G-3

G.3.1 SCSI ADAPTER CONFIGURATION .............................................................................. G-3

G.3.2 SCSI ADAPTER CONTROL ............................................................................................ G-3

G.4 SPECIFICATIONS .................................................................................................................... G-3

G.5 SCSI CONNECTORS ................................................................................................................ G-4

G.5.1 EXTERNAL 50-PIN ULTRA SCSI CONNECTOR ......................................................... G-4

G.5.2 INTERNAL 50-PIN ULTRA SCSI CONNECTOR .......................................................... G-5

G.5.3 INTERNAL 68-PIN ULTRA160 SCSI CONNECTOR .................................................... G-6

Compaq Evo and Workstation Personal Computers vii




APPENDIX H COMPAQ/MATROX G200 MMS QUAD-HEAD PCI GRAPHICS CARD..................

H.1 INTRODUCTION...................................................................................................................... H-1

H.2 FUNCTIONAL DESCRIPTION................................................................................................ H-2

H.3 DISPLAY MODES .................................................................................................................... H-4

H.4 DISPLAY CONFIGURATION.................................................................................................. H-5

CONFIGURATION................................................................................ H-5

CONFIGURATION

H.5 SOFTWARE SUPPORT INFORMATION................................................................................ H-5

H.6 POWER MANAGEMENT AND CONSUMPTION ................................................................. H-6

H.7 CONNECTORS ......................................................................................................................... H-7

H.7.1 ADAPTER CABLE CONNECTOR .................................................................................. H-7

H.7.2 ANALOG MONITOR CONNECTOR .............................................................................. H-8

H.7.3 DIGITAL MONITOR CONNECTOR............................................................................... H-9 viii Compaq Evo and Workstation Personal Computers




LIST OF FIGURES

F IGURE 2–1.

C OMPAQ E VO P ERSONAL C OMPUTERS AND W ORKSTATIONS ................................................. 2-1

F IGURE 2–2.

C OMPAQ E VO AND W ORKSTATIONS , F RONT V IEWS ............................................................... 2-5

F IGURE 2–3.

C OMPAQ D ESKPROS , R EAR V IEWS ......................................................................................... 2-6

F IGURE 2–4.

S MALL F ORM F ACTOR C HASSIS L AYOUT , T OP V IEW ............................................................. 2-7

F IGURE 2–5.

D ESKTOP C HASSIS L AYOUT , T OP V IEW ................................................................................. 2-8

F IGURE 2–6.

C ONFIGURABLE M INITOWER C HASSIS L AYOUT , L EFT S IDE V IEW (M INITOWER

CONFIGURATION ).................................................................................................................................. 2-9

F IGURE 2–7.

S MALL F ORM F ACTOR B OARD L AYOUTS ............................................................................ 2-10

F IGURE 2–8.

D ESKTOP OR C ONFIGURABLE M INITOWER M AIN B OARD L AYOUTS .................................... 2-11

F IGURE 2–9.

S YSTEM A RCHITECTURE , B LOCK DIAGRAM .......................................................................... 2-13

F IGURE 2–10.

P ROCESSOR A SSEMBLY A ND M OUNTING ........................................................................... 2-14

F IGURE 3–1.

P ROCESSOR /M EMORY S UBSYSTEM A RCHITECTURE ............................................................... 3-1

F IGURE 3–2.

P ENTIUM 4 P ROCESSOR I NTERNAL A RCHITECTURE ................................................................ 3-3

F IGURE 3–3.

S YSTEM M EMORY M AP .......................................................................................................... 3-7

F IGURE 4-1.

PCI B US D EVICES AND F UNCTIONS ......................................................................................... 4-2

F IGURE 4-2.

C ONFIGURATION C YCLE ......................................................................................................... 4-4

F IGURE 4-3.

PCI C ONFIGURATION S PACE M APPING ................................................................................... 4-5

F IGURE 4-4.

PCI B US C ONNECTOR (32-B IT T YPE )...................................................................................... 4-9

F IGURE 4-5.

AGP 1X D ATA T RANSFER (P EAK T RANSFER R ATE : 266 MB/ S ) ........................................... 4-11

F IGURE 4-6.

AGP 2X D ATA T RANSFER (P EAK T RANSFER R ATE : 532 MB/ S ) ........................................... 4-12

F IGURE 4-7.

AGP 4X D ATA T RANSFER (P EAK T RANSFER R ATE : 1064 MB/ S ) ......................................... 4-12

F IGURE 4-8.

U NIVERSAL AGP B US C ONNECTOR ...................................................................................... 4-14

F IGURE 4-9.

M ASKABLE I NTERRUPT P ROCESSING , B LOCK D IAGRAM ....................................................... 4-15

F IGURE 4-10.

C ONFIGURATION M EMORY M AP ......................................................................................... 4-23

F IGURE 4-11.

S MALL F ORM F ACTOR F AN C ONTROL B LOCK D IAGRAM ..................................................... 4-29

F IGURE 4-12.

D ESKTOP /C ONFIGURABLE M INITOWER F AN C ONTROL B LOCK D IAGRAM ........................... 4-29

F IGURE 5-1.

40-P IN P RIMARY IDE C ONNECTOR ( ON SYSTEM BOARD )........................................................ 5-3

F IGURE 5-2.

34-P IN D ISKETTE D RIVE C ONNECTOR . ................................................................................... 5-7

F IGURE 5-3.

S ERIAL I NTERFACE C ONNECTOR (M ALE DB-9 AS VIEWED FROM REAR OF CHASSIS ) .............. 5-8

F IGURE 5-4.

COM1 S ERIAL I NTERFACE H EADER (S MALL F ORM F ACTOR SYSTEM BOARD ONLY ) .............. 5-9

F IGURE 5-5.

P ARALLEL I NTERFACE C ONNECTOR (F EMALE DB-25 AS VIEWED FROM REAR OF CHASSIS ).. 5-15

F IGURE 5-6.

8042-T O -K EYBOARD T RANSMISSION OF C ODE ED H , T IMING D IAGRAM .............................. 5-16

F IGURE 5-7.

K EYBOARD OR P OINTING D EVICE I NTERFACE C ONNECTOR .................................................. 5-21

F IGURE 5-8.

USB I/F, B LOCK D IAGRAM ................................................................................................... 5-22

F IGURE 5-9.

USB P ACKET F ORMATS ........................................................................................................ 5-23

F IGURE 5-10.

U NIVERSAL S ERIAL B US C ONNECTOR ................................................................................ 5-25

F IGURE 5-11.

A UDIO S UBSYSTEM F UNCTIONAL B LOCK D IAGRAM ........................................................... 5-27

F IGURE 5-12.

AC’97 L INK B US P ROTOCOL .............................................................................................. 5-28

F IGURE 5-13.

AD1885 A UDIO C ODEC F UNCTIONAL B LOCK D IAGRAM .................................................... 5-29

F IGURE 5-14.

N ETWORK I NTERFACE C ONTROLLER B LOCK D IAGRAM ...................................................... 5-32

F IGURE 5-15.

E THERNET TPE C ONNECTOR (RJ-45, VIEWED FROM CARD EDGE ) ...................................... 5-36

Compaq Evo and Workstation Personal Computers ix




F IGURE 6–1.

P OWER D ISTRIBUTION AND C ONTROL , B LOCK D IAGRAM ...................................................... 6-1

F IGURE 6–2.

S MALL F ORM F ACTOR P OWER C ABLE D IAGRAM .................................................................... 6-5

F IGURE 6–3.

D ESKTOP AND C ONFIGURABLE M INITOWER P OWER C ABLE D IAGRAM .................................. 6-6

F IGURE 6–4.

L OW V OLTAGE S UPPLY AND D ISTRIBUTION D IAGRAM .......................................................... 6-7

F IGURE 6–5.

S MALL F ORM F ACTOR S IGNAL D ISTRIBUTION D IAGRAM ....................................................... 6-8

F IGURE 6–6.

D ESKTOP /M INITOWER S IGNAL D ISTRIBUTION D IAGRAM ....................................................... 6-9

F IGURE 6–7.

H EADER P INOUTS ................................................................................................................. 6-10

F IGURE B–1.

ASCII C HARACTER S ET ........................................................................................................B-1

F IGURE C–1.

K EYSTROKE P ROCESSING E LEMENTS , B LOCK D IAGRAM .......................................................C-2

F IGURE C–2.

PS/2 K EYBOARD -T O -S YSTEM T RANSMISSION , T IMING D IAGRAM ........................................C-3

F IGURE C–3.

U.S.

E NGLISH (101-K EY ) K EYBOARD K EY P OSITIONS ..........................................................C-5

F IGURE C–4.

N ATIONAL (102-K EY ) K EYBOARD K EY P OSITIONS ...............................................................C-5

F IGURE C–5.

U.S.

E NGLISH W INDOWS (101W-K EY ) K EYBOARD K EY P OSITIONS .....................................C-6

F IGURE C–6.

N ATIONAL W INDOWS (102W-K EY ) K EYBOARD K EY P OSITIONS ..........................................C-6

F IGURE C–7.

7-B UTTON E ASY A CCESS K EYBOARD L AYOUT .....................................................................C-7

F IGURE C–8.

8-B UTTON E ASY A CCESS K EYBOARD L AYOUT .....................................................................C-7

F IGURE C–9.

PS/2 K EYBOARD C ABLE C ONNECTOR (M ALE ) ....................................................................C-16

F IGURE C–10.

USB K EYBOARD C ABLE C ONNECTOR (M ALE )..................................................................C-16

F IGURE D-1.

C OMPAQ /NVIDIA V ANTA LT AGP G RAPHICS C ARD (P/N 192174-002) L AYOUT .............. D-1

F IGURE D-2.

C OMPAQ /NVIDIA V ANTA LT G RAPHICS C ARD B LOCK DIAGRAM ......................................... D-2

F IGURE D-3.

VGA M ONITOR C ONNECTOR , (F EMALE DB-15, AS VIEWED FROM REAR ). ............................. D-5

F IGURE E-1.

C OMPAQ /NVIDIA Q UADRO 2 EX OR MXR AGP G RAPHICS C ARD L AYOUT .........................E-1

F IGURE E-2.

NVIDIA Q UADRO 2 EX/MXR G RAPHICS C ARD B LOCK DIAGRAM ..........................................E-2

F IGURE E-3.

VGA M ONITOR C ONNECTOR , (F EMALE DB-15, AS VIEWED FROM REAR )................................E-5

F IGURE F-1.

C OMPAQ /M ATROX M ILLENNIUM G450 AGP G RAPHICS C ARD L AYOUT (PCA# 202901-001)F-1

F IGURE F-2.

M ATROX M ILLENNIUM G450 G RAPHICS C ARD B LOCK DIAGRAM ............................................ F-2

F IGURE F-3.

VGA M ONITOR C ONNECTOR , (O NE OF TWO FEMALE DB-15, AS VIEWED FROM REAR )............ F-5

F IGURE F-4.

F EATURE C ONNECTOR (26-P IN H EADER )................................................................................. F-6

F IGURE G–1.

C OMPAQ /A DAPTEC 29160N SCSI H OST A DAPTER C ARD L AYOUT (PCA# 157342-001) .... G-1

F IGURE G–2.

C OMPAQ /A DAPTEC U LTRA SCSI A DAPTER C ARD B LOCK D IAGRAM ................................... G-2

F IGURE G–3.

E XTERNAL U LTRA SCSI C ONNECTOR (50PIN )...................................................................... G-4

F IGURE G–4.

I NTERNAL 50-P IN U LTRA SCSI C ONNECTOR ......................................................................... G-5

F IGURE G–5.

U LTRA 160 SCSI C ONNECTOR (68PIN HEADER TYPE ) .......................................................... G-6

F IGURE H-1.

C OMPAQ /M ATROX G200 MMS Q UAD -H EAD PCI G RAPHICS C ARD L AYOUT ....................... H-1

F IGURE H-2.

M ATROX G200 MMS Q UAD -H EAD PCI G RAPHICS C ARD B LOCK DIAGRAM .......................... H-2

F IGURE H-3.

MGA G200 G RAPHICS C ONTROLLER A RCHITECTURE ........................................................... H-3

F IGURE H-4.

A DAPTER C ABLE C ONNECTOR , (O NE OF TWO AS VIEWED FROM REAR ). ................................. H-7

F IGURE H-5.

A NALOG (VGA) M ONITOR C ONNECTOR (O NE OF TWO FEMALE DB-15 CONNECTORS ). ........ H-8

F IGURE H-6.

DVI-D M ONITOR C ONNECTOR (24-P IN C ONNECTOR )............................................................ H-9 x Compaq Evo and Workstation Personal Computers




LIST OF TABLES

T ABLE 1–1.

A CRONYMS AND A BBREVIATIONS ........................................................................................... 1-4

T ABLE 2-1.

F EATURE D IFFERENCE M ATRIX ............................................................................................... 2-2

T ABLE 2-2.

C HIPSET C OMPARISON ........................................................................................................... 2-15

T ABLE 2-3.

S UPPORT C OMPONENT F UNCTIONS ........................................................................................ 2-15

T ABLE 2-4.

S TANDARD G RAPHICS S UBSYSTEM C OMPARISON .................................................................. 2-17

T ABLE 2-5.

E NVIRONMENTAL S PECIFICATIONS ........................................................................................ 2-18

T ABLE 2-6.

E LECTRICAL S PECIFICATIONS ................................................................................................ 2-18

T ABLE 2-7.

P HYSICAL S PECIFICATIONS .................................................................................................... 2-19

T ABLE 2-8.

D ISKETTE D RIVE S PECIFICATIONS .......................................................................................... 2-19

T ABLE 2-9.

48 X CD-ROM D RIVE S PECIFICATIONS .................................................................................. 2-20

T ABLE 2-10.

H ARD D RIVE S PECIFICATIONS .............................................................................................. 2-20

T ABLE 3–1.

SPD A DDRESS M AP (SDRAM DIMM) .................................................................................... 3-6

T ABLE 3–2.

H OST /PCI B RIDGE C ONFIGURATION R EGISTERS (GMCH, F UNCTION 0).................................. 3-8

T ABLE 4-1.

PCI D EVICE C ONFIGURATION A CCESS ..................................................................................... 4-4

T ABLE 4-2.

S YSTEM B OARD PCI D EVICE I DENTIFICATION ......................................................................... 4-5

T ABLE 4-3.

PCI B US M ASTERING D EVICES ................................................................................................ 4-6

T ABLE 4-4.

LPC B RIDGE C ONFIGURATION R EGISTERS (ICH2, F UNCTION 0) .............................................. 4-8

T ABLE 4-5.

PCI B US C ONNECTOR P INOUT ................................................................................................. 4-9

T ABLE 4-6.

PCI/AGP B RIDGE C ONFIGURATION R EGISTERS (MCH, F UNCTION 1) .................................... 4-13

T ABLE 4-7.

AGP B US C ONNECTOR P INOUT .............................................................................................. 4-14

T ABLE 4-8.

M ASKABLE I NTERRUPT P RIORITIES AND A SSIGNMENTS ......................................................... 4-16

T ABLE 4-9.

M ASKABLE I NTERRUPT C ONTROL R EGISTERS ........................................................................ 4-17

T ABLE 4-10.

D EFAULT DMA C HANNEL A SSIGNMENTS ............................................................................ 4-19

T ABLE 4-11.

DMA P AGE R EGISTER A DDRESSES ...................................................................................... 4-20

T ABLE 4-12.

DMA C ONTROLLER R EGISTERS ........................................................................................... 4-21

T ABLE 4-13.

C LOCK G ENERATION AND D ISTRIBUTION ............................................................................ 4-22

T ABLE 4-14.

C ONFIGURATION M EMORY (CMOS) M AP ........................................................................... 4-24

T ABLE 4-15.

S YSTEM B OOT /ROM F LASH S TATUS LED I NDICATIONS ...................................................... 4-27

T ABLE 4-16.

S YSTEM O PERATIONAL S TATUS LED I NDICATIONS .............................................................. 4-28

T ABLE 4-17.

S YSTEM I/O M AP ................................................................................................................. 4-30

T ABLE 4-18 LPC47B367 I/O C ONTROLLER R EGISTERS ............................................................................ 4-31

T ABLE 5–1.

IDE PCI C ONFIGURATION R EGISTERS ..................................................................................... 5-2

T ABLE 5–2.

IDE B US M ASTER C ONTROL R EGISTERS ................................................................................. 5-2

T ABLE 5–3.

40-P IN P RIMARY IDE C ONNECTOR P INOUT ............................................................................ 5-3

T ABLE 5–4.

D ISKETTE D RIVE C ONTROLLER C ONFIGURATION R EGISTERS ................................................. 5-5

T ABLE 5–5.

D ISKETTE D RIVE I NTERFACE C ONTROL R EGISTERS ................................................................ 5-5

T ABLE 5–6.

34-P IN D ISKETTE D RIVE C ONNECTOR P INOUT ........................................................................ 5-7

T ABLE 5–7.

DB-9 S ERIAL C ONNECTOR P INOUT ......................................................................................... 5-8

T ABLE 5–8.

S ERIAL I NTERFACE C ONFIGURATION R EGISTERS .................................................................... 5-9

T ABLE 5–9.

S ERIAL I NTERFACE C ONTROL R EGISTERS .............................................................................. 5-10

T ABLE 5–10.

P ARALLEL I NTERFACE C ONFIGURATION R EGISTERS ........................................................... 5-13

T ABLE 5–11.

P ARALLEL I NTERFACE C ONTROL R EGISTERS ...................................................................... 5-14

T ABLE 5–12.

DB-25 P ARALLEL C ONNECTOR P INOUT .............................................................................. 5-15

T ABLE 5–13.

8042-T O -K EYBOARD C OMMANDS ...................................................................................... 5-17

T ABLE 5–14.

K EYBOARD I NTERFACE C ONFIGURATION R EGISTERS .......................................................... 5-18

T ABLE 5–15.

CPU C OMMANDS T O T HE 8042........................................................................................... 5-20

T ABLE 5–16.

K EYBOARD /P OINTING D EVICE C ONNECTOR P INOUT ........................................................... 5-21

Compaq Evo and Workstation Personal Computers xi




T ABLE 5–17.

USB I NTERFACE C ONFIGURATION R EGISTERS .................................................................... 5-24

T ABLE 5–18.

USB C ONTROL R EGISTERS .................................................................................................. 5-24

T ABLE 5–19.

USB C ONNECTOR P INOUT ................................................................................................... 5-25

T ABLE 5–20.

USB C ABLE L ENGTH D ATA ................................................................................................ 5-25

T ABLE 5–21.

AC’97 A UDIO C ONTROLLER PCI C ONFIGURATION R EGISTERS ........................................... 5-30

T ABLE 5–22.

AC’97 A UDIO C ODEC C ONTROL R EGISTERS ....................................................................... 5-30

T ABLE 5–23.

A UDIO S UBSYSTEM S PECIFICATIONS ................................................................................... 5-31

T ABLE 5–24.

AOL E VENTS ...................................................................................................................... 5-33

T ABLE 5–25.

NIC C ONTROLLER PCI C ONFIGURATION R EGISTERS .......................................................... 5-35

T ABLE 5–26.

NIC C ONTROL R EGISTERS ................................................................................................... 5-35

T ABLE 5–27.

82559 NIC O PERATING S PECIFICATIONS ............................................................................. 5-36

T ABLE 7–1.

B OOT B LOCK C ODES ............................................................................................................... 7-2

T ABLE 7–2.

B OOT E RROR C ODES ............................................................................................................... 7-5

T ABLE 7–3.

S ETUP U TILITY F UNCTIONS ..................................................................................................... 7-6

T ABLE 7–4.

C LIENT M ANANGEMENT F UNCTIONS (INT15) ...................................................................... 7-12

T ABLE 7–5.

P N P BIOS F UNCTIONS .......................................................................................................... 7-15

T ABLE 7–6.

APM BIOS F UNCTIONS ........................................................................................................ 7-20

T ABLE A–1.

B EEP /K EYBOARD LED C ODES .............................................................................................. A-1

T ABLE A–2.

P OWER -O N S ELF T EST (POST) M ESSAGES ........................................................................... A-2

T ABLE A–3.

S YSTEM E RROR M ESSAGES ................................................................................................... A-3

T ABLE A–4.

M EMORY E RROR M ESSAGES ................................................................................................. A-4

T ABLE A–5.

K EYBOARD E RROR M ESSAGES .............................................................................................. A-4

T ABLE A–6.

P RINTER E RROR M ESSAGES ................................................................................................... A-5

T ABLE A–7.

V IDEO (G RAPHICS ) E RROR M ESSAGES .................................................................................. A-5

T ABLE A–8.

D ISKETTE D RIVE E RROR M ESSAGES ..................................................................................... A-6

T ABLE A–9.

S ERIAL I NTERFACE E RROR M ESSAGES .................................................................................. A-6

T ABLE A–10.

S ERIAL I NTERFACE E RROR M ESSAGES ................................................................................ A-7

T ABLE A–11.

S YSTEM S TATUS E RROR M ESSAGES .................................................................................... A-8

T ABLE A–12.

H ARD D RIVE E RROR M ESSAGES .......................................................................................... A-8

T ABLE A–13.

H ARD D RIVE E RROR M ESSAGES .......................................................................................... A-9

T ABLE A–14.

V IDEO (G RAPHICS ) E RROR M ESSAGES ................................................................................ A-9

T ABLE A–15.

A UDIO E RROR M ESSAGES ................................................................................................. A-10

T ABLE A–16.

DVD/CD-ROM D RIVE E RROR M ESSAGES ........................................................................ A-10

T ABLE A–17.

N ETWORK I NTERFACE E RROR M ESSAGES ......................................................................... A-10

T ABLE A–18.

SCSI I NTERFACE E RROR M ESSAGES ................................................................................. A-11

T ABLE A–19.

P OINTING D EVICE I NTERFACE E RROR M ESSAGES ............................................................. A-11

T ABLE C–1.

K EYBOARD TO -S YSTEM C OMMANDS ...................................................................................C-11

T ABLE C–2.

K EYBOARD S CAN C ODES ......................................................................................................C-12

T ABLE D-1.

NVIDIA V ANTA LT 2D G RAPHICS D ISPLAY M ODES .............................................................. D-3

T ABLE D-2.

M ONITOR P OWER M ANAGEMENT C ONDITIONS ...................................................................... D-4

T ABLE D-3.

DB-15 M ONITOR C ONNECTOR P INOUT .................................................................................. D-5

T ABLE E-1.

NVIDIA Q UADRO 2 MXR G RAPHICS D ISPLAY M ODES ............................................................E-3

T ABLE E-2.

M ONITOR P OWER M ANAGEMENT C ONDITIONS .......................................................................E-4

T ABLE E-3.

DB-15 M ONITOR C ONNECTOR P INOUT ....................................................................................E-5 xii Compaq Evo and Workstation Personal Computers




T ABLE F-1.

M ATROX M ILLENNIUM G450 G RAPHICS D ISPLAY M ODES ........................................................ F-3

T ABLE F-2.

M ONITOR P OWER M ANAGEMENT C ONDITIONS ........................................................................ F-4

T ABLE F-3.

DB-15 M ONITOR C ONNECTOR P INOUT .................................................................................... F-5

T ABLE F-4.

V IDEO I N C ONNECTOR P INOUT ................................................................................................ F-6

T ABLE G-1.

SCSI H OST A DAPTER C ARD C ONTROL R EGISTER M APPING ................................................... G-3

T ABLE G-2.

U LTRA SCSI H OST A DAPTER C ARD S PECIFICATIONS .............................................................. G-3

T ABLE G-3.

E XTERNAL 50-P IN U LTRA SCSI C ONNECTOR P INOUT ............................................................. G-4

T ABLE G-4.

I NTERNAL 50-P IN U LTRA SCSI C ONNECTOR P INOUT .............................................................. G-5

T ABLE G-5.

U LTRA 160 SCSI C ONNECTOR P INOUT .................................................................................... G-6

T ABLE H-1.

M ATROX G200 MMS G RAPHICS D ISPLAY M ODES .................................................................. H-4

T ABLE H-2.

M ONITOR P OWER M ANAGEMENT C ONDITIONS ...................................................................... H-6

T ABLE H-3.

A DAPTER C ABLE C ONNECTOR P INOUT .................................................................................. H-7

T ABLE H-4.

DB-15 M ONITOR C ONNECTOR P INOUT .................................................................................. H-8

T ABLE H-5.

V IDEO I N C ONNECTOR P INOUT .............................................................................................. H-9

Compaq Evo and Workstation Personal Computers xiii




This page is intentionally blank. xiv Compaq Evo and Workstation Personal Computers




Chapter 1

INTRODUCTION

1.

Chapter 1 INTRODUCTION

1.1 ABOUT THIS GUIDE

This guide provides technical information about Compaq Evo D300/D500 small form factor, desktop, and configurable minitower personal computers and W4000 workstations that feature the

Intel Pentium 4 processor. This document describes in detail the system’s design and operation for programmers, engineers, technicians, and system administrators, as well as end-users wanting detailed information.

The chapters of this guide primarily describe the hardware and firmware elements and primarily deal with the system board and the power supply assembly. The appendices contain general data such as error codes and information about standard peripheral devices such as keyboards, graphics cards, and communications adapters.

This guide can be used either as an online document or in hardcopy form.

1.1.1 ONLINE VIEWING

Online viewing allows for quick navigating and convenient searching through the document. A color monitor will also allow the user to view the color shading used to highlight differential data.

A softcopy of the latest edition of this guide is available for downloading in .pdf file format at the

URL listed below: http://www.compaq.com/support/techpubs/technical_reference_guides/index.html

Viewing the file requires a copy of Adobe Acrobat Reader available at no charge from Adobe

Systems, Inc. at the following URL: http://www.adobe.com

When viewing with Adobe Acrobat Reader, click on the ( ) icon or "Bookmarks" tab to display the navigation pane for quick access to particular places in the guide.

1.1.2 HARDCOPY

A hardcopy of this guide may be obtained by printing from the .pdf file. The document is designed for printing in an 8 ½ x 11-inch format. Note that printing in black and white will lose color shading properties.



Second Edition – January 2003

1-1

Chapter 1 Introduction

1.2 ADDITIONAL INFORMATION SOURCES

For more information on components mentioned in this guide refer to the indicated manufacturers’ documentation, which may be available at the following online sources:

♦ Compaq Computer Corporation: http://www.compaq.com

♦ Intel Corporation: http://www.intel.com

♦ Standard Microsystems Corporation: http://www.smsc.com

♦ Texas Instruments Inc.: http://www.ti.com

♦ USB user group: http://www.usb.org

1.3 MODEL NUMBERING CONVENTION

The model numbering convention for Compaq systems is as follows:

XXX/XNN/NN/N/NNNx

Removable storage: b = CD/CDRW, c = CD, d = DVD, r = CDRW, z = ZIP

Memory (in MB)

OS type: 2 = Windows 2000, 6 = Dual install, Windows NT 4.0 or 2000,

8 = Windows 98SE, P = Dual install Windows XP Pro/2000

Hard drive size (in GB)

Processor speed (2 digits in GHz)

Processor type: P = Pentium 4

Form factor: S = Small form factor, D = desktop, C = Convertible minitower

Model: D3 = Evo D300, D5 = Evo D500; W4 = Workstation 4000

The unit’s serial number is located on a sticker placed on the exterior cabinet. The serial number may also be read with the Compaq Diagnostics or Compaq Insight Manager utilities.

1-2 Compaq Evo and Workstation Personal Computers




The notational guidelines used in this guide are described in the following subsections.

1.5.1 VALUES

Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter

“h.” Binary values are indicated by a value of ones and zeros followed by the letter “b.”

Numerical values that have no succeeding letter can be assumed to be decimal unless otherwise stated.

1.5.2 RANGES

Ranges or limits for a parameter are shown using the following methods:

Bits <7..4> = bits 7, 6, 5, and 4.

IRQ3-7, 9 = IRQ signals 3 through 7, and IRQ signal 9

Example A:

Example B:

1.5.3 REGISTER NOTATION AND USAGE

This guide uses standard Intel naming conventions in discussing the microprocessor’s (CPU) internal registers. Registers that are accessed through programmable I/O using an indexing scheme are indicated using the following format:

03C5.17h

Index port

Data port

In the example above, register 03C5.17h is accessed by writing the index port value 17h to the index address (03C4h), followed by a write to or a read from port 03C5h.

1.5.4 BIT NOTATION AND BYTE VALUES

Bit designations are labeled between brackets (i.e., “bit <0 >”). Binary values are shown with the most significant bit (MSb) on the far left, least significant bit (LSb) at the far right. Byte values in hexadecimal are also shown with the MSB on the left, LSB on the right.




1-3


1.6 COMMON ACRONYMS AND ABBREVIATIONS

Table 1-1 lists the acronyms and abbreviations used in this guide.

Table 1–1. Acronyms and Abbreviations

Table 1-1.

Acronyms and Abbreviations

Acronym/Abbreviation Description

A ampere

ACPI Advanced Configuration and Power Interface

A/D analog-to-digital

AGP

API

APIC

APM

Accelerated graphics port application programming interface

Advanced Programmable Interrupt Controller advanced power management

AOL Alert-On-LAN™

ASIC application-specific integrated circuit

AT

ATA

ATAPI

1) attention (modem commands) 2) 286-based PC architecture

AT attachment (IDE protocol)

AT attachment w/packet interface extensions

AWG

BAT

BIOS

BNC bps or b/s

BTO

CAS

American Wire Gauge (specification)

Basic assurance test basic input/output system

Bayonet Neill-Concelman (connector type) bits per second

Built to order column address strobe

CD-ROM

CDS

CGA compact disk read-only memory compact disk system color graphics adapter cm centimeter

CMOS complimentary metal-oxide semiconductor (configuration memory)

Cntlr controller

Cntrl control codec 1. coder/decoder; 2. compressor/decompressor

CPQ Compaq

CPU central processing unit

CRIMM

CRT

CSM

Continuity (blank) RIMM cathode ray tube

Compaq system management / Compaq server management

Continued




Table 1-1. Acronyms and Abbreviations Continued


DCH

DDC

DDR

DIMM

DIN

DIP

DMA

DMI dpi

DRAM

DVI

EDID

EDO

EEPROM

EGA

EIA

EPP

ESCD

EV

ExCA

FIFO

DOS compatibility hole

Display Data Channel

Double data rate (memory) dual inline memory module

Deutche IndustriNorm (connector type) dual inline package direct memory access

Desktop management interface dots per inch dynamic random access memory

Digital video interface extended display identification data extended data out (RAM type) electrically eraseable PROM enhanced graphics adapter

Electronic Industry Association enhanced parallel port

Extended System Configuration Data (format)

Environmental Variable (data)

Exchangeable Card Architecture first in / first out

FPM fast page mode (RAM type)

FPU

FPS

Floating point unit (numeric or math coprocessor)

Frames per second ft Foot/feet

GB gigabyte

GMCH Graphics/memory controller hub

GND ground

GPIO general purpose I/O

GPOC

GART general purpose open-collector

Graphics address re-mapping table

GUI graphic user interface h hexadecimal

HW hardware hex hexadecimal

Hz

ICH

Hertz (cycles-per-second)

I/O controller hub

IDE

IEEE integrated drive element

Institute of Electrical and Electronic Engineers

I/F interface


Continued




1-5



Acronym/Abbreviation Description in inch

INT interrupt

I/O input/output

IPL initial program loader

IrDA InfraRed Data Association

ISA

Kb / KB industry standard architecture kilobits / kilobytes (x 1024 bits / x 1024 bytes)

Kb/s kilobits per second kg kilogram

KHz kilohertz kV kilovolt lb pound

LAN local area network

LCD liquid crystal display

LPC

LSI

Low pin count large scale integration

LSb / LSB

LUN least significant bit / least significant byte logical unit (SCSI) m Meter

MCH Memory controller hub

MPEG Motion Picture Experts Group ms millisecond

MSb / MSB most significant bit / most significant byte mux multiplex

MVA

MVW motion video acceleration motion video window

NIC network interface card/controller ns nanosecond

NT nested task flag

NTSC National Television Standards Committee

NVRAM non-volatile random access memory

PAL 1. programmable array logic 2. phase alternating line

PCA

PCI

PCM

PCMCIA

Printed circuit assembly peripheral component interconnect pulse code modulation

Personal Computer Memory Card International Association

Continued







PFC

PIN

Power factor correction personal identification number

POST

PROM power-on self test programmable read-only memory

PTR pointer

RAM random access memory

RAS row address strobe rcvr receiver

RDRAM

RGB

(Direct) Rambus DRAM red/green/blue (monitor input)

RMS root mean square

RPM revolutions per minute

RTC real time clock

R/W Read/Write

SCSI

SDR

SDRAM small computer system interface

Singles data rate (memory)

Synchronous Dynamic RAM

SECAM sequential colour avec memoire (sequential color with memory)

SGRAM

SIMD

SIMM

SMART

SMI

SMM

SMRAM

SPD

SPDIF

SPN

SPP

SSE

STN

Synchronous Graphics RAM

Single instruction multiple data single in-line memory module

Self Monitor Analysis Report Technology system management interrupt system management mode system management RAM serial presence detect

Sony/Philips Digital Interface (IEC-958 specification)

Spare part number standard parallel port

Streaming SIMD extensions super twist pneumatic

SW software

Continued




1-7




TAD telephone answering device

TCP tape carrier package

TIA

TPE

TPI

Telecommunications Information Administration twisted pair ethernet track per inch

TV television

TX transmit

URL us / µs

USB

Uniform resource locator microsecond

Universal Serial Bus

UTP unshielded twisted pair

V volt

VAC

VDC

VESA

VGA

VLSI

Volts alternating current

Volts direct current

Video Electronic Standards Association video graphics adapter very large scale integration

W watt

WOL Wake-On-LAN

ZIF zero insertion force (socket)





Chapter 2

SYSTEM OVERVIEW

2. Chapter 2 SYSTEM OVERVIEW

2.1 INTRODUCTION

Compaq Evo Personal Computers and Compaq Workstations (Figure 2-1) deliver an outstanding combination of manageability, serviceability, and consistency for enterprise environments. Based on the Intel Pentium 4 processor with the Intel 845 Chipset, these systems emphasize performance along with industry compatibility. These models feature architectures incorporating the PCI bus.

All models are easily upgradable and expandable to keep pace with the needs of the office enterprise.

Compaq Evo D500 or Workstation W4000

Small Form Factor

Compaq Evo D500

Desktop

Compaq Evo D300/D500

Configurable Minitower

Figure 2–1. Compaq Evo Personal Computers and Workstations

This chapter includes the following topics:

♦ Features and options (2.2) page 2-2

♦ Mechanical design (2.3) page 2-4

♦ System architecture (2.4) page 2-8

♦ Specifications (2.5) page 2-13

Compaq Workstation W4000





2-1

Chapter 2 System Overview

2.2 FEATURES AND OPTIONS

This section describes the standard features and available options.

2.2.1 STANDARD FEATURES

The following standard features are included on all models:

♦ Intel Pentium 4 processor in PPGA478 (Socket N) package

♦ Intel 845 Chipset

♦ Support for three PC133 DIMMs (2 DDR DIMMs on select W4000 systems)

♦ 3.5 inch, 1.44-MB diskette drive

♦ 48x Max CD-ROM drive

♦ IDE controller w/UATA/100 mode support

♦ Hard drive fault prediction

♦ Two serial, two USB, one parallel, and one network interface

♦ APM 1.2 power management support

♦ Plug ’n Play compatible (with ESCD support)

♦ Intelligent Manageability support

♦ Energy Star compliant

♦ Security features including:

• Flash ROM Boot Block

• Diskette drive disable, boot disable, write protect

• Power-on password

• Administrator password

• Serial/parallel port disable

♦ PS/2 Compaq Easy-Access keyboard w/Windows support

♦ PS/2 Compaq Scroll Mouse

Table 2-1 shows the differences in features between the Deskpro series’ based on form factor:

Table 2-1. Feature Difference Matrix

Table 2-1.

Feature Difference Matrix (by Form Factor)

Small Form Factor Desktop

Configurable

Minitower

Series

Chassis type

Drive bays

Memory

Audio

Front panel audio/USB access

# of PCI slots

Smart Cover Sensor/Lock

Power Supply

NOTES:

Evo / Workstation

Compaq Proprietary

3

PC133 SDRAM

Premier Sound

Standard

2

Evo

ATX

5

PC133 SDRAM

Business Audio

Optional

3

Evo / Workstation

ATX

5

PC133 / PC2100 (DDR) SDRAM

Business Audio

[1]

5

Yes/Optional Yes/Optional No/Optional

175 watt 235 watt 250 watt

[1] Optional for Evo systems, standard on Workstation systems





2.2.2 OPTIONS

The following items are available as options for all models and may be included in the standard configuration of some models:

♦ System Memory: PC133 or PC266 64-MB DIMM (non-ECC)

PC133 128-MB (non-ECC)

256-MB (non-ECC)

512-MB (non-ECC)

♦ Hard drives/controllers: 20-, 40-, or 60-GB UATA/100 hard drive

32-GB Wide Ultra3 SCSI hard drive

♦ Removeable media drives: 16x/10x/40x CD-RW drive

10x/40x Max DVD-ROM drive

LS-120 Super Disk drive

PCI DXR DVD Decoder kit

♦ Graphics Monitors: Compaq P700 17” CRT

P1100

Compaq

Compaq

♦ Other: Hood (cover) lock assembly




2-3


These systems are available in three form factors:

♦ Small Form Factor – a small-footprint desktop designed for environments where both performance and space are critical issues.

♦

♦

Desktop – a low-profile ATX-type desktop that satisfies standard expandability needs.

Configurable Minitower – an ATX-type unit providing the most expandability and being adaptable to desktop (horizontal) or floor-standing (vertical) placement.

The following subsections describe the mechanical (physical) aspects of the Compaq Evo models.

CAUTION: Voltages are present within the system unit whenever the unit is plugged

!

disconnect the power cable from the power outlet and/or from the system unit

before handling the system unit in any way.

NOTE: The following information is intended primarily for identification purposes

only. Before servicing these systems refer to the applicable Maintenance And

Service Guide. Service personnel should review training materials also available on

these products.




2.3.1 CABINET LAYOUTS


1 2 3 4

5 6 7 8 9 10 11 12

Evo or Workstation Small Form Factor

1

2

3

5

10

8

4

6

7

9

11

12

1

8

2

3

5

10

5

10 8

6

9

1

11

2 3

7 12

Evo D300/D500 Desktop

4

Evo D300/D500


(as a Minitower)

Item Description

1

2

CD-ROM drive headphone jack

CD-ROM drive volume control

3

4

5

6

CD-ROM drive activity LED

CD-ROM drive open/close button

1.44-MB diskette drive activity LED

1.44-MB diskette drive eject button

7

8

9

Microphone In Jack

Headphone Out Jack

Universal Serial Bus Connector

Workstation W4000


(as a Minitower)

12 Hard Drive Activity LED

Figure 2–2. Compaq Evos and Workstations, Front Views

4

6

11

12

7

9




2-5


11 12 12 6 5 11

1 2 6 4 5 3 7

Small Form Factor

10

12

8

9

7

2

3

4

13

8 9 10 10 1


(as a Minitower)

2 3

1

6

5

11

4 13

Desktop

8 9 7


1

2

Mouse connector

Keyboard connector

3

4

5

6

Serial port A connector

Parallel connector

Network interface connector

Serial port B connector

Item Description

8

9

Audio line input jack

Microphone input jack

10

11

12

AC power connector

VGA monitor connector

AC line voltage selector switch

13 Audio headphone/line output in jack

— —

Figure 2–3. Compaq Evos and Workstation, Rear Views





2.3.2 CHASSIS LAYOUTS

This section describes the internal layouts of the chassis. For detailed information on servicing the chassis refer to the multimedia training CD-ROM and/or the maintenance and service guide for these systems.

The chassis layout for the Small Form Factor is shown in Figure 2-4. Service features include:

♦ Easily-removable card cage assembly.

♦ Tilting drive bay assembly (for easy access to processor and memory sockets).

PCI Conn. 2 (Slot 2)

PCI Conn. 1 (Slot 1)

Slots On Backplane,

Rear View

Hood Lock Solenoid

(Optional)

Power Supply

Speaker Assembly [1]

Lower Drive Bay

Upper Drive Bays

(Tilting Assembly)

Back

Front

Card Cage

Assembly

System Board

Processor Fan

Figure 2–4. Small Form Factor Chassis Layout, Top View




2-7


Figure 2-5 shows the layout for the Slim Desktop. Service features include:

♦ Tilting upper drive bay assembly (for easy access to all drive bays).

♦ Easy access to expansion slots and all socketed system board components.

PCI Slot 1

PCI Slot 2

PCI Slot 3

AGP Slot

Speaker

Back

Auxiliary Chassis Fan

Hood Lock Solenoid

(Optional)

Smart Cover

Sensor Switch

Front

Figure 2–5. Desktop Chassis Layout, Top View

Lower Drive Bays

Power Supply

Air Baffle

Assembly

Upper Drive Bays

(Tilting Assembly)





Figure 2-5 shows the layout for the Configurable Minitower in the minitower configuration.

Features include:

♦ Externally accessible drive bay assembly may be configured for minitower (vertical) or desktop (horizontal) position.

♦ Easy access to expansion slots and all socketed system board components.

Power Supply

Drive Lock

Processor/Heat Sink/Fan

Assembly

Chassis Fan

Back

AGP Slot

Hood Lock

Solenoid

(Optional)

PCI Slot 1

PCI Slot 2

PCI Slot 3

PCI Slot 4

PCI Slot 5

Externally Accessible

Drive Bays

Internal

Drive Bays

Front

Speaker

Figure 2–6. Configurable Minitower Chassis Layout, Left Side View (Minitower configuration)




2-9


2.3.3 BOARD LAYOUTS

Figure 2-7 shows the system and riser boards for the small form factor unit.

32

31

30

29

28

27

26

25

24

1 2

23

3 4 5

22 21

6 7

20 19

8

18

9 10

17

11 12 13

16

14

15

System Board PCA# 011466-101 or 011351-001 Riser Board SP# 252298-001

8

9

10

11

12

13

14

15

16

NOTE:


1 System board

2

3

Audio line in jack

Audio line out jack

4

5

6

7

USB connectors (2)

Serial port A

Network interface connector

Battery

Parallel port

Serial port B

Top: Mouse conn.; Bottom: keyboard conn.

Riser board slot

Riser board

PCI slot connectors (2)

Hood (cover) sensor switch

Processor power connector

Processor socket (mPGA478)


17 Processor fan connector

18

19

Hard drive activity LED

Power button

20

21

22

23

Power LED

USB ports (2)

Audio headphones output jack

Audio microphone input jack

24

25

26

27

28

29

30

31

32

Third DIMM socket present on PC133-based boards.

CD-ROM audio input connector

Diskette drive connector

Secondary IDE connector

Primary IDE connector

Power supply connector

Internal speaker connector

CMOS clear button

Hood (cover) lock solenoid connector

DIMM sockets

Figure 2–7. Small Form Factor Board Layouts





Figure 2-7 shows the system and PCI slot expansion boards. The system board (with three PCI slots) is common to both the desktop and the configurable minitower units. The PCI slot expansion board is attached to the system board in the configurable minitower unit to provide a total of 5 PCI slots.

1 2 3 4 5 6 7 8 9 10 11 12 13

14

34

33

32

31

30

15

16

17

18

19

29 28 27

PCI Slot Expansion Board [1]

SP# 252609-001

26 25 24 23 22 21 20

System Board

PCA# 011345-101 or 011348-101

7

8

9

10

11

12

13

14

15

16


1

2

PCI slot expansion board [1]

PCI slots

3

4

5

6

System board

Front panel headphone/microphone conn.

AGP connector

Top: NIC port; Bottom: USB ports (2)

Microphone Input jack

Serial port (B)

Audio line input jack

Audio line output jack

Parallel port

Serial port (A)

Top: Mouse port; bottom: keyboard port

Processor power connector

Processor socket

Chassis fan connector

Hood (cover) lock solenoid connector 17

NOTE:

24

25

26

27

28

29

30

31


18

19

Processor fan connector

DIMM sockets

20

21

22

23

Power supply connector

Diskette drive connector

SCSI hard drive LED connector

Power button/Pwr & HD LED connector

32

33

34

Primary IDE hard drive connector

Secondary IDE hard drive connector

CMOS clear button

Hood (cover) sense connector

Front panel USB port connector

Password clear jumper

Chassis speaker connector

CMOS battery

Auxiliary audio connector

CD-ROM audio connector

PCI slot expansion connector

[1] Third DIMM socket present on PC133-type board (PCA# 011345) only.

[1] Used in configurable minitower units only.

Figure 2–8. Desktop or Configurable Minitower Main Board Layouts

Compaq Evo and Workstation Personal Computers 2-11




The Compaq Evo and Workstation systems covered in this guide feature an architecture based on the Intel Pentium 4 processor and the Intel 845 chipset (Figure 2-9). These models use either

PC133 or DDR (PC266) SDRAM for system memory, provide AGP 4X graphics support, and include PCI bus expansion capability.

The Intel 845 chipset includes the 82845 MCH designed to support the Pentium 4 processor with an FSB speed of 400 MHz. The 82845 MCH also includes an SDRAM controller supporting up to three PC133 DIMMs or two DDR DIMMs, depending on model configuration.

All systems feature AC’97-compatible audio subsystems and include a microphone input, a line input and headphone and/or line output. The Small Form Factor system features Compaq Premier

Sound components while Desktop and Configurable Minitower systems provide a business audio solution.

The 845 chipset also includes the 82801BA I/O Controller Hub (ICH2) that integrates two IDE controllers with ATA100 support, two USB interfaces, and a PCI bus controller. Also integrated into the 82801BA is an 82562 network interface controller. An SMC LPC47B367 Super I/O

Controller provides serial, parallel, keyboard, mouse, and diskette drive interface functions.

All models covered in this guide support ATA100-type hard drives. Select Compaq Workstation

W4000 models feature a SCSI PCI adapter controlling a Wide Ultra3 SCSI hard drive.

Below is a matrix defining the architectural differences based on form factor and series.

Series Type

SDRAM Memory Speed

Audio subsystem type

Front panel audio ports

Front panel USB ports

Evo/Workstation

SDR

Premier Sound

Standard

Standard

Evo

SDR

Business

Optional

Optional

Evo

SDR

Business

Optional

Optional

Workstation

SDR/DDR

Business

Standard

Standard

Hard Drive Type

SDR = Single data rate

DDR = Double data rate

ATA100 ATA100 ATA100 ATA100 or SCSI





Monitor

RGB AGP 4X

Graphics

Controller

Pentium 4

Processor

AGP

4X

I/F

400-MHz FSB

845 Chipset

82845

GMCH

SDRAM

Cntlr.

Memory

Bus

System

Memory

Hub Link

Bus

SCSI

Hard Drive

IDE

Hard Drive

CD

Audio

Audio

Subsystem

Adaptec

29160N

SCSI

Adapter Card

Pri. IDE

Cntlr.

Sec. IDE

Cntlr.

82801BA

ICH2

NIC

USB

Cntlr.

82802

FWH

LPC

Bus

Serial

I/F (2)

Parallel

I/F

LPC47B367 I/O Controller

Keyboard/

Mouse I/F

Diskette

I/F

Beep

Audio

AC’97

Link Bus

33-MHz

32-Bit PCI Bus

Power

Supply

PCI Slots

NOTES:

Select Workstation models only.

Figure 2–9. System Architecture, Block diagram





2.4.1 INTEL PENTIUM 4 PROCESSOR

The models covered in this guide feature the Intel Pentium 4 processor. This processor is backward-compatible with software written for the Pentium III, Pentium II, Pentium MMX,

Pentium Pro, Pentium, and x86 microprocessors. The processor architecture includes a floatingpoint unit, 32-KB first and 512-KB secondary caches, and enhanced performance for multimedia applications through the use of multimedia extension (MMX) instructions. Also included are streaming SIMD extensions (SSE and SSE2) for enhancing 3D graphics and speech processing performance. The Pentium 4 processor features Net-Burst Architecture that uses hyper-pipelined technology and a rapid-execution engine that runs at twice the processor's core speed.

These systems employ an mPGA478B zero-insertion-force (ZIF) socket designed for mounting a

“Flip-Chip” (FC-PGA2) processor package (Figure 2-10). Small form factor units use a passive heat sink held in place over the FC-PGA package with two retaining clips. Desktop and configurable minitower units use an active assembly (which integrates the heat sink and fan) that clips on to the processor socket over the FC-PGA package.

Heat Sink

Retaining Clips

Heat Sink / Fan Assembly for

Desktop and

Configurable Minitower Units

Small Form Factor Units

Heat Sink for

Lock/Unlock

Handle

(Shown in unlock position) mPGA478B

Socket

Figure 2–10. Processor Assembly And Mounting

FC-PGA2 Package

(w/ Integrated Heat

Spreader)

These systems support processors fitted with passive heat sinks or processors fitted with heat sink/fan assembly with a power cable that attaches to a fan-power header provided on the system board. There are three types of passive heat sinks.

NOTE: The two types of heat sinks are not interchangeable. Also, these systems support processors using the FC-PGA2 package only.





2.4.2 CHIPSET

The Intel 845 chipset consists of a Memory Controller Hub (MCH), an enhanced I/O controller hub (ICH2), and a firmware hub (FWH). Table 2-2 lists the integrated functions provided by the chipset.

Table 2-2. Chipset Comparison

Component Type

82845 MCH

82801BA ICH2

82802 FWH

Table 2-2.

845 Chipset Functions

Function

AGP 4X interface

SDRAM controller supporting PC133 DIMMs or 266-MHz DDR DIMMs [1]

400-MHz FSB

PCI bus I/F

LPC bus I/F

SMBus I/F

IDE I/F with UATA/100 support

AC ’97 controller

RTC/CMOS

IRQ controller

Power management logic

USB controllers #1 and #2 (supporting up to 4 ports)

Network interface controller

Loaded with Compaq BIOS

Random number generator

NOTE:

[1] Dependent on system board type. System supports one or the other.

2.4.3 SUPPORT COMPONENTS

Input/output functions not provided by the chipset are handled by other support components.

Some of these components also provide “housekeeping” and various other functions as well.

Table 2-3 shows the functions provided by the support components.

Table 2-3. Support Component Functions

Component Name

LPC47B367 I/O Controller

AD1885 Audio Codec

Table 2-3.

Support Component Functions

Function

Keyboard and pointing device I/F

Diskette I/F

Serial I/F (COM1and COM2)

Parallel I/F (LPT1, LPT2, or LPT3)

AGP, PCI reset generation

Interrupt (IRQ) serializer

Power button logic

GPIO ports

Audio mixer

Digital-to-analog converter

Analog-to-digital converter

Analog I/O





2.4.4 SYSTEM MEMORY

Two memory types are used in these systems:

♦ PC133-based with three DIMM sockets supporting up to 3 gigabytes of SDRAM memory

♦ 266-MHz DDR-based with two DIMM sockets supporting up to 2 gigabytes of DDR memory.

NOTE: The maximum memory amounts stated above are with 1-GB memory modules using 512 Mb technology DIMMs.

Industry-standard SDRAM DIMMs and DDR266 DIMMs are not interchangable in these systems.

2.4.5 MASS STORAGE

All models include a 3.5 inch 1.44-MB diskette drive installed as drive A. Most models also include a CD-ROM and either a 10-, 15-, or 20-GB hard drive. Standard hard drives feature Drive

Protection System (DPS) support. All systems provide two (one primary, one secondary) PCI bus-mastering Enhanced IDE (EIDE) controllers integrated into the chipset. Each controller provides UATA/100 support for two drives for a total of four IDE devices, although the form factor will determine the actual number of drive spaces available.

2.4.6 SERIAL AND PARALLEL INTERFACES

All models include two serial ports and a parallel port accessible at the rear of the chassis. Each serial port is RS-232-C/16550-compatible and supports standard baud rates up to 115,200 as well as two high-speed baud rates of 230K and 460K, and utilize DB-9 connectors. The parallel interface is Enhanced Parallel Port (EPP1.9) and Enhanced Capability Port (ECP) compatible, and supports bi-directional data transfers through a DB-25 connector.

2.4.7 UNIVERSAL SERIAL BUS INTERFACE

All models feature a minimum of two Universal Serial Bus (USB) v1.1 ports that provide a

12Mb/s interface for peripherals. The Compaq Evo desktop and configurable minitower models may be upgraded to include two additional USB ports on the front panel. All small form factor and Workstation models include front panel USB ports in the standard configuration. The USB provides hot plugging/unplugging (Plug ’n Play) functionality.

2.4.8 NETWORK INTERFACE CONTROLLER

All models feature a Network Interface Controller (NIC) integrated on the system board.

Equivalent to the Intel 82562 10/100 NIC, the controller provides automatic selection of 10BASE-

T or 100BASE-TX operation with a local area network and includes power-down, wake-up, and

Alert-On-LAN features. An RJ-45 connector is provided on the rear panel.





2.4.9 GRAPHICS SUBSYSTEM

The 82845 MCH component includes an AGP 4X interface that supports an AGP graphics controller installed in the AGP slot. The AGP slot includes both Type 1 and Type 2 retention mechanisms. Dual-monitor support is possible by adding a PCI graphics card to the standard configuration. Table 2-4 lists the key features of the standard graphics subsystems employed in these systems:

Table 2-4. Standard Graphics Subsystem Comparison

Std. Config. In

Recommended for:

Bus Type

Mem. Amount

Mem. Type

DAC Speed

Max. 2D Res.

Table 2-4.

Standard AGP Graphics Comparison nVIDIA

Vanta

Evo

Entry 3D

AGP 4X

16 MB

SGRAM

300 MHz nVIDIA

Quadro2 EX/MXR

Wkstn. W4000

Hi 2D,

Entry 3D

AGP 4X

32 MB

SDRAM

350 MHz

1920x1200 1920x1200

Matrox

Millennium

G450 Dual-Head

Evo

Hi 2D,

Entry 3D

AGP 4X

16 / 32 MB

SDRAM

360 MHz (Pri)

200 MHz (Sec)

2048x768

Software

Compatibility

Aux. I/O

Outputs

NOTES:

Quick

DCI/DirectX,

Direct Draw,

Direct Show,

MPEG 1/2,

Indeo

VESA I/F

1 RGB

[1] DVI connector on MXR card only.

[2] Supports up to four monitors.

Quick Draw,

DCI/DirectX,

Direct Draw,

Direct Show,

MPEG 1/2,

Indeo

VESA I/F

1 RGB, 1 DVI [1]

Quick Draw,

DCI/DirectX,

Direct Draw,

Direct Show,

MPEG 1/2,

Indeo

VESA I/F

2 RGB

Matrox

G200 MMS

Wkstn. W4000

Multi-monitor

Hi 2D

PCI

8 MB x 4

SGRAM

250 MHz

1920x1200

(analog mon.)

Quick Draw,

DCI/DirectX,

Direct Draw,

MPEG 1/2,

OpenGL,

Direct 3D

VESA I/F

4 RGB/4DVI [2]





2.4.10 AUDIO SUBSYSTEM

These systems use the integrated AC97 audio controller of the 845 chipset and an AC’97compliant audio codec. These systems include microphone and line inputs and headphone and line outputs. The Desktop and Configurable Minitower models include a 3-watt output amplifier driving an internal speaker. The Small Form Factor models feature Compaq Premier Sound consisting of a five-level equalizer designed to compensate for chassis acoustics and a lowdistortion 5-watt amplifier driving a speaker for optimum sound. Small form factor and all

Workstation models front panel-accessible audio jacks as standard while Evo desktop and configurable minitower models may be upgraded to include front panel audio jacks.

2.5 SPECIFICATIONS

This section includes the environmental, electrical, and physical specifications for the Compaq

Evo and Worksstation Personal Computers. Where provided, metric statistics are given in parenthesis. All specifications subject to change without notice.

Table 2-5. Environmental Specifications

Table 2-5.

Environmental Specifications (Factory Configuration)

Ambient Air Temperature

Shock (w/o damage)

Vibration

Humidity

50 o to 95 o F (10 o to 35 o C, max. rate of change < 10 °C/Hr)

5 Gs [1]

0.000215 G 2 /Hz, 10-300 Hz

10-90% Rh @ 28 o C max. wet bulb temperature

10,000 ft (3048 m) [2]

-24 o to 140 o F (-30 o to 60 o C, max. rate of change < 20 °C/Hr )

20 Gs [1]

0.0005 G 2 /Hz, 10-500 Hz o 5-95% Rh @ 38.7

C max. wet bulb temperature

30,000 ft (9,144 m) [2] Maximum Altitude

NOTE:

[1] Peak input acceleration during an 11 ms half-sine shock pulse.

[2] Maximum rate of change: 1500 ft/min.

Table 2-6. Electrical Specifications

Table 2-6.

Electrical Specifications

Input Line Voltage:

Nominal:

Maximum:

Input Line Frequency Range:

Nominal:

Maximum:

Power Supply:

Maximum Continuous Power

Small Form Factor

Desktop


Maximum Line Current Draw

Small Form Factor

Desktop


100 - 127 VAC

90 - 132 VAC

50 - 60 Hz

47 - 63 Hz

175 watts

235 watts

250 watts

2.7 A @ 100 VAC

3.6 A @ 100 VAC

3.6 A @ 100 VAC

200 - 240 VAC

180 - 264 VAC

50 - 60 Hz

47 - 63 Hz

175 watts

235 watts

250 watts

2.7 A @ 100 VAC

3.6 A @ 100 VAC

3.6 A @ 100 VAC





Table 2-7. Physical Specifications

Parameter

Height

Width

Depth

Weight (nom.) [1]

Maximum Supported Weight [2]

Table 2-7.

Physical Specifications

Small

Form Factor

3.9 in (9.90 cm)

13.1 in (33.3 cm)

14.4 in (36.6 cm)

20 lb (9.1 kg)

100 lb (45.5 kg)

Desktop

5.72 in (14.5 cm)

15.25 in (38.7 cm)

17.90 in (45.5 cm)

26 lb (12 kg)

100 lb (45.5 kg)

Configurable

Minitower [3]

17.65 in (44.8 cm)

6.60 in (16.8 cm)

16.80 in (42.7 cm)

26 lb (12 kg)

100 lb (45.5 kg)

NOTES:

[1] System weight may vary depending on installed drives/peripherals.

[2] Assumes reasonable article(s) such as a display monitor and/or another system unit.

[3] Minitower configuration. For desktop configuration, swap Height and Width dimensions.

Table 2-8. Diskette Drive Specifications

Table 2-8.

Diskette Drive Specifications

(Compaq SP# 179161-001)

Parameter Measurement

Media Type

Height

Bytes per Sector

Sectors per Track:

High Density

Low Density

Tracks per Side:

High Density

Low Density

Read/Write Heads

Average Access Time:

Track-to-Track (high/low)

Average (high/low)

Settling Time

Latency Average

3.5 in 1.44 MB/720 KB diskette

1/3 bay (1 in)

512

18

9

80

80

2

3 ms/6 ms

94 ms/173ms

15 ms

100 ms





Table 2-9. Optical Drive Specifications

Parameter

Interface Type

Media Type (reading)

Media Type (writing)

Transfer Rate (Reads)

Table 2-9.

Optical Drive Specifications

48x CD-ROM

IDE

Mode 1,2, Mixed Mode, CD-DA,

Photo CD, Cdi, CD-XA

N/a

4.8 Kb/s (max sustained)

Transfer Rate (Writes): N/a

16/10/40x CD-RW Drive

IDE

Mode 1,2, Mixed Mode, CD-DA,

Photo CD, Cdi, CD-XA

CD-R, CD-RW

CD-ROM, 4.8 Kb/s;

CD-ROM/CD-R, 1.5-6 Kb/s

CD-R, 2.4 Kbps (sustained);

CD-RW, 1.5 Kbps (sustained);

650 MB @ 12 cm Capacity:

Mode 1, 12 cm

Mode 2, 12 cm

8 cm

Center Hole Diameter

Disc Diameter

Disc Thickness

Track Pitch

Laser

Beam Divergence

Output Power

Type

Wave Length

Average Access Time:

Random

Full Stroke

Audio Output Level

Cache Buffer

550 MB

640 MB

180 MB

15 mm

8/12 cm

1.2 mm

1.6 um

53.5 +/- 1.5 °

53.6 0.14 mW

GaAs

790 +/- 25 nm

<100 ms

<150 ms

0.7 Vrms

128 KB

15 mm

8/12 cm

1.2 mm

1.6 um

53.5 + 1.5°

53.6 0.14 mW

GaAs

790 +/- 25 nm

<120 ms

<200 ms

0.7 Vrms

128 KB

Table 2-10. Hard Drive Specifications

Parameter

Table 2-10.

Hard Drive Specifications

20.0 GB 32.0 GB 40.0 GB 60.0 GB

3.5” 3.5" 3.5” 3.5”

Interface

Transfer Rate

Drive Protection System Support?

Typical Seek Time (w/settling) [1]

Single Track

Average

Full Stroke

Disk Format (logical blocks)

Rotation Speed

Drive Fault Prediction

NOTE:

100 MBps

Yes

1.2 ms

8.0 ms

18 ms

39,102,336

160 MBps

Yes

0.6 ms

4.7 ms

12 ms

71,132,000

100 MBps

Yes

1.2 ms

8.0 ms

18 ms

78,165,360

7200 RPM 10,000 RPM 7200 RPM

SMART III N/a SMART III

Actual times may vary depending on specific drive installed.

All ATA drives are Quiet Drives.

100 MBps

Yes

1.0 ms

9.0 ms

20 ms

78,165,360

7200 RPM

SMART III





Chapter 3

PROCESSOR/

MEMORY SUBSYSTEM

3. Chapter 3 PROCESSOR/MEMORY SUBSYSTEM


This chapter describes the processor/memory subsystem of Compaq Deskpro Personal Computers featuring the Pentium 4 processor. These systems feature the Pentium 4 processor and the 845 chipset (Figure 3-1). The 82845 MCH component of the 845 chipset supports SDRAM memory of either the standard PC133 or the DDR type, depending on model.

400-MHz

64-Bit FSB

AGP

I/F

Pentium 4

Processor

FSB I/F

82845

MCH

Hub I/F

Covered in Chapter 4

Cntl

Memory

Cntlr .

Present in PC133 systems only.

Mem. Bus

XMM1

DIMM

In

Socket

System Memory

XMM2 XMM3

DIMM

Socket

DIMM

Socket

Figure 3–1. Processor/Memory Subsystem Architecture


♦ Pentium 4 processor [3.2]

♦ Memory subsystem [3.3]

♦ Subsystem configuration {3.4] page 3-2 page 3-5 page 3-8

Compaq Evo and Workstation Personal Computer


3-1


Chapter 3 Processor/Memory Subsystem

3.2 PENTIUM 4 PROCESSOR

These systems each feature an Intel Pentium 4 processor in a FC-PGA478 package mounted with a passive heat sink in a mPGA478B zero-insertion force socket. The mounting socket allows the processor to be easily changed for servicing and/or upgrading.

3.2.1 PROCESSOR OVERVIEW

The Intel Pentium 4 processor represents the latest generation of Intel’s IA32-class of processors.

Featuring Intel’s NetBurst  architecture, the Pentium 4 processor is designed for intensive multimedia and internet applications of today and the future while maintaining compatibility with software written for earlier (Pentium III, Pentium II, Pentium, Celeron, and x86) microprocessors.

Key features of the Pentium 4 processor include:

♦ Hyper-Pipelined Technology – The main processing loop has twice the depth (20 stages) of the Pentium III allowing for increased processing frequencies.

♦ Execution Trace Cache – A new feature supporting the branch prediction mechanism, the trace cache stores translated sequences of branching micro-operations ( µops) and is checked when suspected re-occurring branches are detected in the main processing loop. This feature allows instruction decoding to be removed from the main processing loop.

♦ Rapid Execution Engine – Arithmetic Logic Units (ALUs) run at twice (2x) processing frequency for higher throughput and reduced latency.

♦ 256-KB Advanced transfer L2 cache – Using 32-byte-wide interface at processing speed, the

L2 cache can provide 48 GB/s performance (3x over the Pentium III)

♦ Advanced dynamic execution – Using a larger (4K) branch target buffer and improved prediction algorithm, branch mis-predictions are reduced by an average of 33 % over the

Pentium III.

♦ Enhanced Floating Point Processor - With 128-bit integer processing and deeper pipelining the Pentium 4’s FPU provides a 2x performance boost over the Pentium III.

♦ Additional Streaming SIMD extensions (SSE2) – In addition to the SSE support provided by previous Pentium processors, the Pentium 4 processor includes an additional 144 MMX instructions, further enhancing:

• Streaming video/audio processing

• Photo/video editing

• Speech recognition

• 3D processing

• Encryption processing

♦ Quad-pumped Front Side Bus (FSB) – The FSB uses a 100-MHz clock for qualifying the buses’ control signals. However, address information is transferred using a 200-MHz strobe while data is transferred with a 400-MHz strobe, providing a maximum data transfer rate of

3.2 GB/s. This is a boost of over three times that of a Pentium III with a 133-MHz FSB.




Figure 3-1 illustrates the internal architecture of the Pentium 4 processor.

Pentium 4 Processor

Branch

Prediction

Rapid Exe. Eng.

ALUs

CPU

Execution

Trace Cache

Out-of-

Order Core

128-bit

Integer

FPU

FSB

I/F

L1

Data

Cache

256-KB

8-Way

L2

Adv.

Transfer

Cache

ALU Speed: Core speed x2

Core Speed: 1.4, 1.5, 2.0, 2.2 GHz

FSB Speed: 400 MHz (effective data transfer rate)

Figure 3–2. Pentium 4 Processor Internal Architecture

The Pentium 4 increases processing speed with higher clock speeds made possible with hyperpipelined technology that can handle significantly more instructions at a time. Since branch mispredicts would result in serious performance hits with such a long pipeline, the Pentium 4 features a branch prediction mechanism improved with the addition of an execution trace cache and a refined prediction algorithm. The execution trace cache can store 12k micro-ops (decoded instructions dealing with branching sequences) that are checked when re-occurring branches are processed. Code that is not executed (bypassed) is no longer stored in the L1 cache as was the case in the Pentium III.

The out-of-order core features Advanced Dynamic Execution, which provides a large window

(126 instructions) for execution units to work with. A more accurate branch prediction algorithm, along with a larger (4-KB) branch target buffer that stores more details on branch history results in a 33% reduction in branch mis-predictions over the Pentium III.

The L1 data cache features a low-latency design for minimum response to cache hits. The 256-KB advanced transfer L2 cache features a 256-bit (32-byte) interface operating at processing speed.

The L2 cache of the 1.5 GHz Pentium 4 can therefore provide a transfer rate of 48 GB/s.

The combined improvements of the Pentium 4’s CPU core the rapid execution engine’s ALUs to operate at twice the processing frequency to handle the steady stream of instructions.

The front side bus (FSB) of the Pentium 4 uses a 100-MHz clock but provides bi- and quadpumped transfers through the use of 200- and 400-MHz strobes. The Pentium 4 can transfer a complete 64-byte cache line in two 100-MHz bus cycles for a throughput rate of 3.2 GB/s.

Address information is transferred at a 200-MHz rate.



3-3



The Pentium 4 processor is software-compatible with Celeron, Pentium II, Pentium MMX,

Pentium, and x86 processors, but will require the latest versions of operating system software to take advantage of the Streaming SIMD extensions (SSE2).

3.2.2 PROCESSOR UPGRADING

All units use mPGA478B ZIF mounting socket and ship with the Pentium 4 processor in a Flip-

Chip (FC-PGA478) package installed with a passive heat sink. The FC-PGA478 package consists of the processor die mounted “upside down” on a PC board. This arrangement allows the heat sink to come in direct contact with the processor die. The heat sink and attachment clip are specially designed provide maximum heat transfer from the processor component.

!

CAUTION: Attachment of the heat sink to the processor is critical on these systems.

Improper attachment of the heat sink will likely result in a thermal condition.

Although the system is designed to detect thermal conditions and automatically shut down, such a condition could still result in damage to the processor component. Refer to the applicable Maintenance and Service Guide for processor installation instructions.




3.3 MEMORY SUBSYSTEM

These systems support one of two types of memory: single data rate (SDR) SDRAM or double data rate (DDR) SDRAM. The system board determines the type of memory supported:

♦ SDR SDRAM-based system board: Three 168-pin DIMM sockets that accept PC100 or

PC133 (PC133 supplied) DIMMs.

♦ DDR SDRAM-based system board: Two 184-pin DIMM sockets that accept PC1600 or

PC2100 (PC2100 supplied) DIMMs.

NOTE: The two memory types are not interchangeable within a system. The system board determines memory type.

NOTE: The SDR SDRAM "PCxxx" reference designates bus speed (i.e, a PC133

DIMM is designed for 133 MHz operation). The DDR SDRAM "PCxxxx" reference designates bus bandwidth (i.e., a PC2100 DIMM can, operating at a 266-MHz effective speed, provide a throughput of 2100 MBps (8 bytes × 266 MHz)).

These systems accept DIMMs with the following parameters:

♦ Unbuffered, compatible with SPD rev. 1.0

♦ 32-, 64-, 128-, 256-, and 512-Mb memory technology

♦ Single or double-sided

NOTE: Systems that support DDR SDRAM accept either ECC or non-ECC DIMMs,

but not both.

The SPD format supported by these systems complies with the JEDEC specification for 128-byte

EEPROMs. This system also provides support for 256-byte EEPROMs to include additional

Compaq-added features such as part number and serial number. The SPD format as supported in this system (SPD rev. 1) is shown in Table 3-3.

The key SPD bytes that BIOS checks for compatibility are 2, 9, 10, 18, 23, 24, and 126. If BIOS detects EDO or ECC DIMMs a “memory incompatible” message will be displayed and the system will halt. This system is designed for using non-ECC DIMMs only. Refer to chapter 8 for a description of the BIOS procedure of interrogating DIMMs.

An installed mix of DIMM types (PC100 and PC133, CL 2 and CL 3) is acceptable but operation will be constrained to the level of the DIMM with the lowest performance specification.

If an incompatible DIMM is detected the NUM LOCK will blink for a short period of time during

POST and an error message may or may not be displayed before the system hangs.



3-5



The SPD address map is shown below.

Table 3–1. SPD Address Map (SDRAM DIMM)

Table 3-3.

SPD Address Map (SDRAM DIMM)

Byte

0

1

10

11

12

13

14

15

16

17

2

3

4

5

6, 7

8

9

18

19

20

21

22

23

24

NOTES:

No. of Bytes Written Into EEPROM

Total Bytes (#) In EEPROM

Memory Type

No. of Row Addresses On DIMM

No. of Column Addresses On DIMM

No. of Module Banks On DIMM

Data Width of Module

Voltage Interface Standard of DIMM

Cycletime @ Max CAS Latency (CL)

Access From Clock

Config. Type (Parity, Nonparity, etc.)

Refresh Rate/Type

Width, Primary DRAM

Error Checking Data Width

Min. Clock Delay

Burst Lengths Supported

No. of Banks For Each Mem. Device

CAS Latencies Supported

CS# Latency

Write Latency

DIMM Attributes

Memory Device Attributes

Min. CLK Cycle Time at CL X-1

Max. Acc. Time From CLK @ CL X-1

[1]

[2]

[3]

[4]

[4]

[4] [5]

[6]

[4]

[4]

[4]

[4]

[7]

[7]

25

26

27

28

29

30, 31

32..61

62

63

64-71

72

73-90

91, 92

93, 94

95-98

99-125 OEM Specific Data

126 Intel frequency check

127

128-131

132

133-145

146

147

Min. CLK Cycle Time at

CL X-2

Max. Acc. Time From

CLK @ CL X-2

Min. Row Prechge. Time

Min. Row Active to Delay

Min. RAS to CAS Delay

Reserved

Superset Data

SPD Revision

Checksum Bytes 0-62

JEP-106E ID Code

DIMM OEM Location

OEM’s Part Number

OEM’s Rev. Code

Manufacture Date

OEM’s Assembly S/N

Reserved

Compaq header “CPQ1”

Header checksum

Unit serial number

DIMM ID

Checksum

Reserved

[7]

[7]

[1] Programmed as 128 bytes by the DIMM OEM

[2] Must be programmed to 256 bytes.

[3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be

re-sent as highest order CAS# address.

[4] Refer to memory manufacturer’s datasheet

[5] MSb is Self Refresh flag. If set (1), assembly supports self refresh.

[6] Back-to-back random column addresses.

[7] Field format proposed to JEDEC but not defined as standard at publication time.

[8] Field specified as optional by JEDEC but required by this system.

[9] Compaq usage. This system requires that the DIMM EEPROM have this

space available for reads/writes.

[10] Serial # in ASCII format (MSB is 133). Intended as backup identifier in case vender data is

invalid.

Can also be used to indicate s/n mismatch and flag system adminstrator of possible system

Tampering.

[11] Contains the socket # of the module (first module is “1”). Intended as backup identifier (refer to

note [10]).

[8]

[8]

[8]

[8]

[8]

[8]

[8]

[7]

[7]

[7]

[7]

[7]

[9]

[9]

[9] [10]

[9] [11]

[9]

[9]




Figure 3-4 shows the system memory map.

FFFF FFFFh

FFE0 0000h

FFDF FFFFh

FEC1 0000h

FEC0 FFFFh

FEC0 0000h

FEBF FFFFh

Host,

PCI, AGP Area

High BIOS Area

(2 MB)

PCI Memory

(18 MB)

APIC Config. Space

(64 KB)

PCI Memory

Expansion

(3060 MB)

4 GB

2000 0000h

1FFF FFFFh

Host/PCI Memory

Expansion

(496 MB)

512 MB

Host, PCI,

ISA Area

DOS Compatibility

Area

0100 0000h

00FF FFFFh

0010 0000h

000F FFFFh

Extended Memory

(15 MB)

Option ROM

(128 KB)

Graphics/SMRAM

RAM (128 KB)

16 MB

1 MB

000F 0000h

000E FFFFh

000E 0000h

000D FFFFh

000C 0000h

000B FFFFh

000A 0000h

0009 FFFFh

System BIOS Area

(64 KB)

Extended BIOS

Area

640 KB

Fixed Mem. Area

(128 KB)

0008 0000h

0007 FFFFh

512 KB

Base Memory

(512 KB)

0000 0000h

NOTE: All locations in memory are cacheable. Base memory is always mapped to DRAM. The next 128 KB fixed memory area can, through the north bridge, be mapped to DRAM or to PCI space. Graphics RAM area is mapped to PCI or AGP locations.

Figure 3–3. System Memory Map



3-7



3.4 SUBSYSTEM CONFIGURATION

The 82815 GMCH component provides the configuration function for the processor/memory subsystem. Table 3-4 lists the configuration registers used for setting and checking such parameters as memory control and PCI bus operation. These registers reside in the PCI

Configuration Space and accessed using the methods described in Chapter 4, section 4.2.

Table 3–2. Host/PCI Bridge Configuration Registers (GMCH, Function 0)

PCI Config.

Addr.

00, 01h

02, 03h

04, 05h

06, 07h

Table 3-4.

Host/PCI Bridge Configuration Registers (GMCH, Device 0)

Register

Reset

Value

PCI Config.

Addr. Register

Vender ID

Device ID

Command

Status

8086h 6A, 6Bh

1130h 6C..6Fh

0006h 70h

[1] 71h

DRAM Control Reg.

Memory Buffer Strength

Multi-Transaction Timer

CPU Latency Timer

0A..0Bh

0Dh

0Eh

10..13h

50, 51h

53h

55..56h

57h

58h

59..5Fh

60..67h

68h

Class Code

Latency Timer

Header Type

Aperture Base Config.

PAC Config. Reg.

Data Buffer Control

DRAM Row Type

DRAM Control

DRAM Timing

PAM 0..6 Registers

DRAM Row Boundary

Fixed DRAM Hole

--

00h

00h

[2]

00h

83h

00h

01h

00h

00h

01h

00h

90h

91h

92h

93h

A0..A3h

A4..A7h

A8..ABh

B0..B3h

B4h

B8..BBh

BCh

BDh

Error Command

Error Status Register 0

Error Status Register 1

Reset Control

AGP Capability Identifier

AGP Status

AGP Command

AGP Control

Aperture Size

Aperture Translation Table

Aperture I/F Timer

Low Priority Timer

NOTES:

Refer to Intel Inc. documentation for detailed description of registers.

Assume unmarked locations/gaps as reserved.

[1] = 0090h for AGP (external graphics) implementation; = 0080h for GFX (internal i740)

implementation.

[2] = 8 for AGP; = 0 for GFX.

Reset

Value

00h

00h

N/A

N/A

00h

00h

0000h

0000h

00h

00h

00h

55h

00h

10h

02h

00h

00h




Chapter 4

SYSTEM SUPPORT

4. Chapter 4 SYSTEM SUPPORT


This chapter covers subjects dealing with basic system architecture and covers the following topics:

♦ PCI bus overview (4.2)

♦ AGP bus overview (4.3)

♦ System resources (4.4)

♦ System clock distribution (4.5) page 4-2 page 4-10 page 4-15 page 4-22

♦ Real-time clock and configuration memory (4.6) page 4-23

♦ System management (4.7) page 4-33

♦ Register map and miscellaneous functions (4.8) page 4-38

This chapter covers functions provided by off-the-shelf chipsets and therefore describes only basic aspects of these functions as well as information unique to the systems covered in this guide. For detailed information on specific components, refer to the applicable manufacturer’s documentation.



4-1


Chapter 4 System Support

4.2 PCI BUS OVERVIEW

NOTE: This section describes the PCI bus in general and highlights bus implementation in this particular system. For detailed information regarding PCI bus operation, refer to the PCI Local Bus Specification Revision 2.2.

These systems implement a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2) operating at 33 MHz. The PCI bus handles address/data transfers through the identification of devices and functions on the bus. A device is typically defined as a component or slot that resides on the PCI bus (although some components such as the MCH and ICH2 are organized as multip devices). A function is defined a s the end source or target of the bus transaction. A device may le c ontain one or more functions.

In the standard configuration these systems use a hierarchy of three PCI buses (Figure 4-1). The

PCI bus #0 is internal to the 815E chipset components and is not physically accessible. T he AGP bus that services the AGP slot (or resident AGP controller on the Small Form Factor) is designated as

P CI bus #2.

PCI bus #1. All PCI slots and the NIC function internal to the 82801BA reside on omponent

Mem. Cntlr.

Function

Hub Link

Hub Link I/F

PCI Br

Func

I/F

Hub idge tion

PCI

Bus #2

PCI

Bus #0

Link Bus

NIC

I/F

Function

AGP

Bridge

Function

PCI Bus #1

(AGP Bus)

82801BA ICH2 Component

PCI Bus #0

EIDE

Controller

Function

PCI

Bus #2

PCI Connector 1

PCI Connector 2

PCI Connector 3 [1]

PCI Connector 4 [2]

PCI Connector 5 [2]

NOTES:

[1] Desktop and Configurable minitower models only .

[2] Configurable minitower models only




USB

I/F

Function

AGP Connector

SMBus

Controller

Function

LPC

Bridge

Function

AC97

Audio

Function

Figure 4-1. PCI Bus Devices and Functions




4-3



4.2.1 PCI BUS TRANSACTIONS

The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for handling both address and data transfers. A bus transaction consists of an address cycle and one or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is realized during burst modes in which a transaction with contiguous memory locations requires th at only one address cycle be conducted and subsequent data cycles are completed using autoin c cremented addressi onf iguration, and s p n Four types of d ss ecial. A ddress dec ad re cycl odin es ca take pl g is distri but ed (left u ace on the P p to each de

CI bus; I/ vic

O, memory, e on th e PC I bus).

4.2.1.1

I/O and Memory Cycles

For I/O and memory cycles, a standard 32-bit address d ecode (AD31..0) for byte-level addressing is handled by the appropriate PCI device. For memory addressing, PCI devices decode the

AD31..2 lines for dword-level addr essing and check the AD1,0 lines for burst (linearincrementing) mode. In burst mode, subsequent data phases are conducted a dword at a time with addressing assumed to increment accordingly (four bytes at a time).

D s evices on the PC oftware. In th

I bus must com ply wi PCI protoc is system, configurat n m th echani ol th at allows con figurati h on of that dev sm #1 (as described in t e PCI Local Bus ice by specification Rev. 2.1) is employed. This method uses two 32-bit registers for initiating a configuration cycle for accessing the configura n space o f a PCI device . Th e configuration a ddress reg S cc

8h e c onfigura alue that specifies the PCI bus, PCI tion data r ( _D ATA) at

0 CFCh contain s the configuration data.

P CI Configuration Ad dress Register

I/O Port 0CF8h, R/W, (32-bit access only)

PCI Configuration Data Register

I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)

B ction

Bit

31 Configuration

0 = Disabled

1 = Enable

30..24 Reserved - rea d/write 0s

23..16 Bus Number. S elects PC I bus

15..11 PCI Device Nu mber. Sel ects PC I

10..8

7..2

1,0

device for acc ess

Function Number. Selects function of

selected PCI devic e.

Register Index. Specifies config. reg.

Configuration Cycle Type ID.

00 = Type 0

01 = Type 1





Two types of configuration cycles are used. A Type 0 (zero) cycle is targeted to a device on the

PCI bus on which the cycle is running. A Type 1 cycle is targeted to a device on a downstream

PCI bus as identified by bus number bits <23..16>. With three or more PCI buses, a PC may convert a Type 1 to a Type 0 if it’s de stined fo r a

I bridge

device being serviced by that bridge or it m d ay forward the Type 1 cycle unmodified ow nstream bri

if it is

c

dest dge. Figure 4-2 shows the onfigurat i ined for a device being serviced by a on cycle format a nd how th e loa din of

0 CF8h res ults in a Type 0 conf iguration cycle on th e PCI bus. The D evice Number (bits <15..11> d etermines which one of the AD31..11 line a ct n I s is to be asserted high for the IDSEL signal, which o be con figured. The f unctio b its <10..8>) i s used to s elect a particular f uncti on wi thin a PC I component.

Register 0C F8h

R esults in:

AD31..0

(w/Type 00

C onfig. Cycle)

3

Reserved

2 2 1 1

Bu s

Num ber

Devic e

Numb er

1 1 8 7 2 1 0 [1]

Function Register

Number Index

IDSEL (only one signal li ne asser ted)

Func

Numb tion er

R egister

Index

NOTES:

[1] Bits <1,0> : 00 = Typ e e 1 cycle

Type 01 c ycle only. Reserved on Ty pe 00 cy cle.

F igure 4-2. Configuration Cycle

Table 4-1 shows the standard configur c ation of device numb omponents and slots residing on a PCI bus. ers and IDSEL connections for

Table 4-1. PCI Device Configu ration Access

PCI Component

Table 4-1.

PCI Component Confi guration Acc ess

Notes Function # Device #

82845 MCH:

Memory Controller

AGP Bridge

AGP slot

82801BA ICH2:

PCI Bridge

LPC Bridge

EIDE Controller

USB I/F #1

SMBus Co ntroller

USB I/F #2

AC97 Audio Controller

AC97 Modem Contr oller

Network Inter face Controller

PCI Connector 1 (slot 1)





[1]

[2]

[2]

[2, 3]

[2, 4]

[2, 4]

0

0

0

0

0

0

0

0

2

3

4

5

6

0

0

0

1

0 (00h)

1 (01h)

0 (00h)

30 (1Eh)

31 (1Fh)

31 (1Fh)

31 (1Fh)

31 (1Fh)

31 (1Fh)

31 (1Fh)

31 (1Fh)

8 (08h)

4 (04h)

9 (09h)

10 (0Ah )

11 (0Bh)

13 (0Dh )

N OTES: ed.

[2] PCI bus number giv en is for standard configuration.

[3] Desktop and Configurable Minitow er models only.

[4] Configu rable minitower models only.

PCI

Bus #

2

2

2

2

2

0

0

1

0

0

0

0

0

2

0

0

0

IDSEL

Wired to:

--

--

--

AD20

AD25

AD26

AD27

AD29



4-5



T he register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space header.

Configuration

Space

Header

31 24 23

M in. Lat.

16 15

Device-Specific Area

Min. GNT Int. Pin

8 7

Int. Line

0

Reserved

Reserved

Expansion ROM Base Address

Subsystem ID Subsystem Vendor ID

Card Bus CIS Pointer

B IST Hdr. T ype Lat. Timer Line Size

Class Code Revision ID

Status

Devi ce ID

Command

Vendor ID

PCI Configuration Space Type 0

Data required by PCI protocol

Not required

Register

Index

FCh

40h

3Ch

38h

34h

30h

2Ch

28h

10h

0Ch

08h

04h

00h

31 24 23 16 15 8 7

Device-Specific Area

Bridge Control Int. Pin Int. Line

Expansion ROM Base Address

Reserved

I /O Limit Upper 16 Bits I/O Base Upper 16 Bits

Prefetchable Limit Upper 32 Bits

Prefetchable Base Upper 32 Bits

Prefetch. Mem. Limit Prefetch. Mem. Base

Memory Base Memory Limit

Sec ondary Status

2 nd Lat.Tmr Sub. Bus #

I/O Limit

Sec. Bus #

I/O Base

Pri. Bus #

Bas e Address Registers

BIST Hd r. Type

Cla ss Code

Status

Device ID

Lat. Timer Line Size

Revision ID

Command

Vendor ID

PCI Configuration Space Type 1

Figure 4-3. PCI Configuration Space Mapping

E ach PCI device is identified with a vendor ID (assigned to the vendor by the PCI Special Interest

Group) and a device ID (assigned by the vendor). The device and vendor IDs for the devices on the system board are listed in Table 4-2.

Table 4-2. System Board PCI Device Identification

Table 4-2.

System Board PCI Device Identification

PCI Device

82845 MCH:

Memory Controller

AGP Bridge

82801 ICH2:

PCI Bridge

LPC Bridge

EIDE Controller

USB I/F #2

SMBus Controller

AC97 Audio Controller

Network Interface Controller

Vendor ID

8086h

8086h

8086h

8086h

8086h

8086h

8086h

8086h

8086h

Device ID

1A30h

1A31h

244Eh

2440h

244Bh

2444h

(Hidden)

2445h

2449h




0

Register

Index

FCh

40h

3Ch

38h

34h

30h

2Ch

28h

24h

20h

1Ch

18h

10h

0Ch

08h

04h

00h


4.2.2 PCI BUS MASTER ARBIT RATION

The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has been granted control of the bus for the purpose of initiating a transaction. A target is a device th at is the recipient of a transaction. The Request (REQ), Grant (G NT), and FRAME signals are used by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI bus (and does not already own it), the PCI device asserts it’s REQn signal to the PCI bus arbiter (a function of the system control ler component). If the bus is available, the arbiter asserts the GNTn signal to the requesting device, which then asserts FRAME and conducts the address phase of the transaction with a target. If the PCI device already owns the bus, a request is not needed and the device can simply assert FRAME and conduct the transaction. Table 4-3 shows the grant and request signals assignments for the devices on the PCI bus.

Tabl e 4-3. PCI Bus Mastering Devices

Table 4-3.

PCI Bus Mastering Devices

REQ/GNT Line

REQ0/GNT0

REQ1/GNT1

REQ2/GNT2

REQ3/GNT3

REQ4/GNT4

GREQ/GGNT

NOTE:

[1] Desktop and Config

[2] Configurable minito wer models only

Device

PCI Connector Slot 1

PCI Connector Slot 2

PCI Connector Slot 3 [1]

PCI Connector Slot 4 [2]

PCI Connector Slot 5 [2] urable Minitower models only.

AGP Slot

P CI bus arbitration is based on a round-robin scheme that complies with the fairness algorith m sp ecified by the PCI specification. The bus parking policy allows for the current PCI bus owner

(excepting the PCI/ISA br idge) to maintain ownership of the bus as long as no request is asserted by nother agent. Note tha c

a t most CPU-to-DRAM and AGP-to-DRAM accesses can occur oncurrently with PCI traffic, therefore reducing the need for the Host/PCI bridge to compete for

PCI bus ownership.



4-7



4.2.3 OPTION ROM MAPPING

During POST, the PCI bus is scanned for devices that contain their own specific firmware in

ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility area (refer to the system memory map shown in chapter 3).

4.2.4 PCI INTERRUPTS

E m ight interrupt signals (INTA- thru INTH-) are available for use by PCI devices. These signals ay be generated by on-board PCI devices or by devices installed in the PCI slots. For more information on interrupts incl uding PCI inte rrupt mappi ng refer to the “System Resources” section

4.4.

4.2.5 PCI POWER MANAGEMENT SUPPORT

T m lies with the PCI Power Ma nagement Interface Specifica tion (rev 1.0). The PCI

Power Man a agement En able (PME-) itiate the p signa ower l is

m supported by the chipset an an agem ent ro utine. d allows complia nt PCI

4.2.6 P B

T he chip set implements two dat a bu s ses t h at a e I bu s:

4.2.6.1

Hub Link Bus

T to he chip set implements a Hub Link bus between th e MCH and the ICH2. This bus is transparent

software and is not accessible for expansion purposes.

The 82801 ICH2 implements a Low Pin Count (LPC) bus for handling transactions to and from the 47B367 Super I/O Controller as well as the 82802 Firmware Hub (FWH). The LPC bus transfers data a nibble (4 bits) at a time at a 33-MHz rate. Generally transparent in operation, the only consideration required of the LPC bus is during the configuration of DMA channel modes

(see section 4.4.3 “DMA”).





4.2.7 PCI CONFIGURATION

PCI bus operations requi c hannel configuration, R re the co nfigu ration of certain parameters such as PCI IRQ routing, DM

TC control, port decode ranges, and power management opt ions. These

A parameters are handl c om ed by the LPC I/F bridge function (PCI function #0, device 31) of t he ICH2 ponent and configured through the PCI configuration space registers listed in Table 4-4.

C onfiguration is provi ded by BIOS at power-up but re-configurable by software.

T able 4-4. LPC Bridge Configuration Registers (ICH2, Function 0)

Tabl e 4-4.

LPC Bridge Configuration Registers

(ICH2, Function 0, Device 31)

PCI

Config.

Addr. Register

00, 01h Vendor ID

02, 03h Device ID

04, 05h an

06, 07h Status

08h Revisi on ID

0A-0Bh Cl ass Co de

0Eh

40-43h

He ader T

ACPI Bas ype e Address

44h ACPI Con

4E, 4Fh BIOS Con trol trol

54h TCO Con trol

58-5Bh as

5Ch

60-63h

64h

68-6B

88h

.

Serial I RQ Control

INT E-F R outing Cntrl.

Dev . 31 E rror Config.

NOTE:

Reset

Value

8086h

2440h

00 h

010 6h

80 h

1

00 h

000 0h

00 h

1

00 h

10

00

[1] Va lue for each b yte.

Assum e unm arked l ocation ps h h

PCI

Config.

Addr.

8Ah

90, 91h

A0 -CF h

D4-D7 h

D8h

E0h

E1h

E2h

E3h

E 4, E 5h

E 6, E 7h

E8EB h

F0h

F2h rved.

Register

Device 31 Error Status

PCI D MA Configuration

Po we r Mana gem ent

Ge ne ra l Con trol

General Status

RTC onfig urati on

LP C C OM P ort Dec. Ran ge

LPC FDD & LPT Dec. Rge

LPC Audio Dec. Range

FWH D eco de E nable

LPC I /F De code Range 1

LPC I /F Ena bles

FW H Select 1

LPC I/F Decode Range 2

FW H Select 2

FW H Decode Enable 2

Fun ct io n Di sable Regis ter

Reset

Value

00h

0000h

0’s

F00 h

00h

00h

00h

80h

FFh

0000 h

0000 h

001122 33

0000 h

5678 h

0Fh

00h



4-9



4.2.8 PCI CONNECTOR

B94

A94

B62 B52 B49

A62 A52 A49

F igure 4-4. PCI Bus Connector (32-Bit Type)

B1

A1

Table 4-5. PCI Bus Connector P inout

Table 4-5.

PCI Bus Connector Pinout

Pin B Signal A Signal Pin B Signal A Signal

01 -12 AD16

Pin B Signal A Signal

02 TCK

03 GND

04 TDO

05

06 +5

07 INTB-

08

09

11

+5 VDC

INTD-

PRSNT2- Reserved 42 SERR- GND

12

TMS

TDI

+5 VDC

INTC-

+5 VDC

34 GND

35 IRDY- GND

36 +3.3 VDC TRDY-

37 DEVSEL- GND

38 GND

39 LOCK- +3.3 VDC

10 RSVD +5 VDC SBO-

63 Reserved GND

C/BE7-

FRAME- 65 C/BE6-

66 C/BE4-

67

70

GND

68 AD63

STOP- 69 AD61

+5 VDC

59

72 AD57

73 GND

C/BE5-

PAR64

AD62

GND

AD60

AD58

GND

AD56

13

14

15

17

18

RSVD

GND

16 CLK

GND

REQ-

+3.3

RST- 46 GND AD13

+5 AD11

GNT-

GND

48 AD10

49 GND

VDC 76 GND

GND

AD09

77 AD51

78 AD49

AD52

AD50

GND

79 +5 AD48

80 AD47 AD46

19

20

+5 50 K

21 AD29

22 GND

+3.3

AD28 53 ey Key

C/BE0-

81 AD45

83 AD43

AD07 +3.3

GND ey Key 82 AD44

AD42

AD06 85 AD40

24 AD25 GND 55 AD05 AD04 86 AD39 AD38

25 +3.3 56 AD03

26 C/BE3- IDSEL 57 GND

GND

AD02

27 AD23 +3.3 AD00

28 GND AD22 59 +5

87 AD37 GND

88 +5 AD36

89 AD35

VDC 90 AD33

AD34

GND

REQ64- 91 AD32

30 AD19 GND 61 +5 VDC 92 Reserved Reserved

31 +3.3 VDC AD18 62 +5 VDC +5 VDC 93 Reserved GND





4.3 AGP BUS OVERVIEW

NOTE: For a detailed description of AGP bus operations refer to the AGP Interface

Specification Rev. 2.0 available at the following AGP forum web site: http://www.agpforum.org/index.htm

The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet highperformance interface for graphics adapters, especially those designed for 3D operations. The

AGP interface is designed to give graphics adapters dedicated pipelined access to system memory for the purpose of off-loading texturing, z-buffering, and alpha blending used in 3D graphics operations. By off-loading a large portion of 3D data to system memory the AGP graphics adapte o nly requires enough memory for frame buffer (display image ) refreshing. r

4.3.1 BUS TRANSACTIONS

The operation of the AGP bus is based on the 66-MHz PCI specification but includes additional mechanisms to increase bandwidth. During the configuration phase the AGP bus acts in accordance with PCI protocol. Once graphics data handling operation is initiated, AGP-defined protocols take ef b fect. The AGP graphics adapter acts generally as the AGP master, but can also ehave as a “PCI” target during fast writes from the MCH.

Key differences between the AGP interface and the PCI interface are as follows:

♦ Address phase and associated data transfer phase are disconnected transactions. Addressing and data transferring occur as contiguous actions on the PCI bus. On the AGP bus a reques t for data and the transfer of data may be separated by other operations.

♦ Commands on the AGP bus specify system memory accesses only. Unlike the PCI bus, commands involving I/O and configuration are not required or allowed. The system memory address space used in AGP operations is the same linear space used by PCI memory space commands, but is further specified by the graphics address re-mapping table (GART) of the north bridge component.

♦ Data trans acti ons on the A GP bu s in volve e ight bytes o r m ultiples of eight bytes. The AGP m emo ry addressing protocol uses 8-byte boundaries as opposed to PCI’s 4-byte boundaries.

If a transfer of less than eight bytes is needed, the remaining bytes are filled with arbitrary d ata th at is discarded by th e targ et.

♦ Pipelined requests are defined by length or size on the AGP bus. The PCI bus defines transfer length s with the FRAME- signal. h an two basic types of transactions on the AGP bus: data requests (addressing) and data hese actions are separate from each other.





4.3.1.1

Request

Requesting data is accomplished in one of two ways; either multiplexed addressing (using the A D lines for addressing/data) or demultiplexed (“sideband”) addressing (using the SBA lines for addressing only and the AD lines for data only). Even though there are only eight SBA lines (as opposed to the 32 AD lines) sideband addressing maximizes efficiency and throughput by allowing the AD lines to be exclusively used for data transfers. Sideband addressing occurs at the same rate (1X, 2X, or 4X) as data transfers. The differences in rates will be discussed in the next se b ction describing data transfers. Note also that sideband addressing is limited to 48 bits (address its 48-63 are assumed zero). The MCH component supports both SBA and AD addressing , but the method and rate is sel ecte d by the AG P grap hics adapte r.

D tr ata transfers use the AD lines and occur as the result of data requests described previously. Each ans action resulting from a request involves at least eight bytes, requiring the 32 AD lines to h andle at least two transfers per request. The 82845 MCH supports three transfer rates: 1X, 2X, nd gardless of the rate used, the speed of the bus clock is constant at 66 MHz. The fo llowing subsections describe how the use of additional strobe signals makes possible higher es.

AGP 1X Transfers

During a AGP 1X transf

Each 4-byte data transfer er the 66-MHz CLK signal is used to qualify the control and data signals.

is synchronous with one CLK cycle so it takes two CLK cycles for a m inimum 8-byte transfer (Figure 4-5 shows two 8-byte transfers). The GNT- and TRDY- signals retain their traditional PCI functions. The ST0..3 signals are used for priority encoding, with

“000” for low priority and “001” indicating high priority. The signal level for AGP 1X transf ers may be 3.3 or 1.5 VDC.

CLK

AD

GNT -

TRDY

-

ST0..2

T1 T2 T3 T4 T5 T6 T7

00x

D1A xxx

D1B xxx

D2A xxx

D2B xxx xxx

Figure 4-5. AGP 1X Data Transfer (Peak Transfer Rate: 266 MB/s)





AGP 2X Transfers

During AGP 2X transfers, clocking is basically the same as in 1X transfers except that the 66-

MHz CLK signal is used to qualify only the control signals. The data bytes are latched by an additional strobe (AD_STBx) signal so that an 8-byte transfer occurs in one CLK cycle (Fig ure 4-

6). The first four bytes (DnA) are latched by the receiving agent on the falling edge of AD_STB and the second four bytes (DnB) are latched on the rising edge of AD_STBx. The signal l x evel for

AGP 2X transfers may be 3.3 or 1.5 VDC.

CLK

AD

AD_STBx

GNT-

TRDY-

ST0..2

T1 T2 T3 T4 T5 T6 T7

00x xxx xxx

D2B D3B D4B xxx xxx xxx

F igure 46. AGP 2X Data Transfer (Pe te: 532 M B/s)

A GP 4X Tra nsfers

The AGP 4X t ransfer rate allows s ixteen b of e tran

2 s

X transfers t e 66-MHz CLK signal ignal h s are use

is used only d to latch each 4-byte tr ansf th

for qual er on e AD lin ifying es. A

control signals while s shown in

strobe

Figure 4-7, 4-byt e block D nA is latched by the falling edge of AD_STBx while DnB is latched by the falling edge of

AD_STB x-. The signal level for AGP 4X transfers is 1.5 VDC.

CLK

AD

AD_STBx

AD_STBx-

ST0..2 xxx 00x xxx xxx





Figure 4-7. AGP 4X Data Transfer (Peak Transfer Rate: 1064 MB/s)

4.3.2 AGP CONFIGURATION

AGP bus operations re qu ire the configuration of certain parameters involvin g syst em memory a ccess by the AGP grap hi integrated within the nort s h bridge (MCH, device 1) component. The AGP function i s, from the

P c

CI bus perspective, tr onfiguration registers eated essentially as a PCI/PCI bridge and configured through PC I

(Table 4-6). Configuration is accomplished by BIOS during POST.

NOTE: Configuration of the AGP bus interface involves functions 0 and 1 of the

MCH. Function 0 registers (listed in Table 3-4) include functions that affect basic control (GART) of the AGP.

Table 4-6. PCI/AGP Bridge Configuration Registers (MCH, Funct ion 1)

Table 4-6.

PCI/AGP ge onfigura tion gi

(MCH n C

, Fun ction 1)

PCI

Con fig .

Add r.

00, 01h

02, 03h

04, 05h

06, 07h

08h

0A, 0B h

0Eh

18h

19h

1Ah

NOTE:

Regis

Vend

D evic ter or ID e ID

Comm

Statu s and

Revision ID

Class Code

Head er Type

Prima ry Bus Numbe r

Secon dary Bus Number

Subordinate Bus Number

Assum e unm arked l ocation ps register d esc riptions.

Reset

Value

P CI

C onfig.

A ddr.

8086 h 1 Bh

1131h 1 Ch

0000h 1 Dh

0020 h 1E, 1Fh

00h 2 0, 21h

0406h 2 2, 23h

01h 2 4, 25h

00h

00h

00h

2

3

6, 27h

Eh

3F-FFh

R egi ste r

Reset

Value

Sec. Master Latency T

I/O Base Address

I/O Limit Address

Sec. PCI/PCI Status

Memory Base Ad dress imer 00h

F0h

00h

02A0h

FFF0h

Memory Limit A ddress 0000h

P refe tch Mem. Ba se A ddr. FFF0h

P refe tch Mem. Li mit A ddr.

P CI ontro l

R ese rve d

0000h

00h

00 h ved. Refer to Intel do en r detail ed

The AGP graphics a u its resident con on re anda rd PCI device.





4 .3.3 AGP CONNECTOR

A1

B94

A94

B1

Figure 4-8. Universal AGP Bus Con nector

A66

B66

T able 4-7. AGP Bus Connector Pinout

Table 4-7.

AGP Bus Connector Pinout

Pin A Signal B Signal Pin A Signal B Signal

GND

Pin A Signal B Signal

45 VDD3 VDD3

03 NC VDD

24 NC

25 VDD3 VDD3 47 STOP- VDDQ

04 USBN USBP 26 PAD30 PAD31 48 PME- PERR-

05 GND GND 27 PAD28 PAD29 49 GND GND

06 INTA- INTB- 28 VDD3 VDD3

07 RESET CLK 29 PA D

50 PAR SERR-

26 PAD27 51 PAD15 CBE1-

08 GNT-

09 VDD3

10 ST1

1 1 NC

REQ -

VDD 3

ST0

ST2

12 PIPE- RBF-

30 P

31 G

AD 24 PAD25 52 VDDQ VDDQ

ND

32 A D_ STB1- _STB1 54 PAD11 PAD12

33 CBE3-

34 VDDQ

GND

PAD23

VDDQ

53 PAD13 PAD14

55 GN

56 PA

D GND

D09 PAD10

13 GND

14 WBF-

GND

NC

35 PAD22 PAD21

36 PAD20 PAD19

7 E 0-

58 VD DQ

PAD08

VDDQ

15 SBA1 SBA0 37 GND

16 VDD3

19 GND

VDD3

GND

GND

38 PAD18 PAD17

41 FRAME- IRDY-

20 SBA5 SBA4 42 NC

59 A D

60 PAD06 PAD07

17 SBA3 SBA2 39 PAD16 CBE2- 61 G ND GND

18 SB_STB- SB_STB 40 VDDQ VDDQ 62 PAD04 PAD05

63 PAD02 PAD03

21 SBA7 DBA6 43 GND GND 65 PAD00 PAD01

NOTES;

NC = Not connected

VDDQ = 3.3 VDC when TYPE DET- is left open by AGP 1X/2X card.

VDDQ = 1.5 VDC when TYPE DET- is grounded by AGP 4X card.





4.4 RESOURCES

This section describes the availability and basic control of major subsystems, otherwise known a s resource allocation or simply “system resources.” System resources are provi ded on a priority basis through hardware interrupts and DMA requests and gra nts.

4.4.1 I U

The microprocessor uses tw as upt can be e o types of hard nabled or ware interrupts; maskable and nonmaskable. A

disabled within the microprocessor by the use of the STI and a

LI ltho ugh it may be inh ibited skable interrupt c

by hardware annot be masked off within the microprocessor,

or software means external to the microprocessor.

4.4.1.1 askab le erru pts

The maskable i nterrup t is a hardware-generated signa l used by peripheral functions within the

( s ystem to get th

PCI) or IR e attent ion o

Q0-15 (ISA) sig f the microprocessor. P eripheral functions produce a unique INTA-H nal that is routed to interrupt processing logic that asserts the interrupt

(INTR-) input to th of the in e microprocessor. The microprocessor halts execution to determine the source terrupt and then ser vices the peripheral as appropriate.

F igure 4-9 shows the routing of PCI and ISA interrupts. Most IRQs are routed through the I/O controller, which contains a serializing function. A serialized interrupt stream is applied to the

82801 ICH2.

I/O &

SM Functions

IDE

Hard Drives

PCI Peripherals

IRQ3..7,

9..12,

14,15

IRQ14,15

INTA-..H-

LPC47B367

I/O Cntlr.

Interrup t

Serializer

Serial IRQ

82801

ICH2

Interrupt

Processing

INTR-

APIC bus

Processor

Figure 4-9. M aska ble In terrupt ia

Interrupts may be roce sse in o ne tw o m es ( ec bl r

♦ 825

♦ API

9 mode

C mode gh th e F 10 Se tup uti lity):





8259 Mode

T he 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using 8259t e quivalent logic. Table 4-8 lists the standard source configuration for maskable interrupts and heir pr i orities in 8259 mode. If more than one interrupt is pending, the highest priority (lowest

T able 4-8. Maskable Interrupt Priorities and Assignments

Table 4-8.

Maskable Interrupt Priorities and Assignments

Priority Signal Label Source (Typical)

6

7

8

9

10

1

2

3

4

5

11

12

13

14

15

--

IRQ0

IRQ1

IRQ8-

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ2

Interval timer 1, counter 0

Keyboard

Real-time clock

Unused

PCI devices/slots

Audio codec

Mouse

Coprocessor (math)

Primary IDE controller

Secondary IDE I/F controller

Serial port (COM2)

Serial port (COM1)

Network interface controller

Diskette drive controller

Parallel port (LPT1)

NOT AVAILABLE (Cascade from interrupt controller 2)

APIC Mode

The Advanced Programmable Interrupt Controller (APIC) mode provides enhanced interrupt processing with the following advantages:

♦ Eliminates the processor’s interrupt acknowledge cycle by using a separate (APIC ) bus

♦ Programmable inte rrupt priority

♦ Additional interrupt s (total of 24)

T d he APIC mode accommodates eight PCI interrupt signals (INTA-..INTH-) for use by PCI evices. The PCI interrupts are evenly distributed to minimize latency and wired as follows:

ICH2 PCI PCI PCI PCI PCI AGP NIC USB

Int. Cntlr. Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot I/F [1] I/F #2

INTD-

-- --

INTB-

--

-- -- --

-- -- -- --

Wired to

INTA-

INTE- -- -- --

INTC-

--

--

INTA- INTA- -- --

-- INTB- -- --

INTB- INTD- -- -- --

INTC- INTA- -- -- --

INTH- -- -- -- --

NOTES:

[1] Connection internal to the ICH2. Will be reported by BIOS as using INTA but is NOT shared with

other functions using INTA.

Desktop and configurable minitower systems only.

Configurable minitower systems only.





The PCI interrupts can be configured by PCI Configuration Registers 60h..63h to share the st andard ISA interrupts (IRQn).

NOTE: The APIC mode is supported by the Wi ndows NT and Windows 2000 operating systems. Systems running the Windows 95 or 98 operating system will need to run in

8259 mode.

Ma abl reg ers e Interrupt processing is controlled and m

. These registers are listed in Table 4-9. onitored t hrough standard AT-type I/O-mapped

Table 49. Maskable Interrupt Contro l Registers

I/O Port

020h

021h

0A0h

0A 1h

Table 4 -9.

Maskable Interrupt Control Registers

Register

Base Address, Int. Cn tlr. 1

Initialization Command Word 2-4, Int. Cntlr. 1

Base Address, Int. Cntlr. 2

Initialization Command Word 2-4, Int. Cntlr. 2

The initialization and operation of the interrupt control registers follows standard AT-type protocol.

4.4.1.2

Interrupts

Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself b e by ut may be maskabl software using logic external to the microprocessor. There are two non-maskable in terrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable s,

N MI- Generation

The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:

♦ Parity errors detected on a PCI bus (activating SERR- or PERR-).

♦ Microprocessor internal error (activating IERRA or IERRB)

T he SERR- and PERR- signals are routed through the ICH2 component, which in turn activates the NMI to the microprocessor.





The NMI Status Register at I/O port 061h contains NMI source and status data as follows:

N MI Status Register 61h

Bit Function

0 = No NMI from system board parity error.

1 = NMI requested, read only

5

4

3

2

1

0

0 = No NMI from IOCHK-

1 = IOCHK- is active (low), NMI requested, read only

Interval Timer 1, Counter 2 (Speaker) Status

Refresh Indicator (toggles with every refresh)

IOCHK- NMI Enable/Disable:

0 = NMI from IOCHK- enabled

1 = NMI from IOCHK- disabled and cleared (R/W)

System Board Parity Error (PERR/SERR) NMI Enable:

0 = Parity error NMI enabled

1 = Parity error NMI disabled and cleared (R/W)

Speaker Data (R/W)

Inteval Timer 1, Counter 2 Gate Signal (R/W)

0 = Counter 2 disabled

1 = Counter 2 enabled

Functions not related to NMI activity.

After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2> or

<3> respectively.

T he N MI Enable Register (0 70h, <7>) is used to en able/disable the NMI signal. Writing 80h to t his r egister masks generatio affect RTC operation and sho n of the uld be

NMI-. Note that the lower six bits of register at I/O port 70h considered when changing NMI- generation status.

SMI- Generation

T he SMI- (System Management Interrupt) is typically used for power management functions.

When power management is enabled, inactivity timers are monitored. When a timer times out,

SMI- is asserted and invokes the microprocesso

A r’s SMI handler. The SMI- handler works with the

PM BIOS to service the SMI- according to the cause of the timeout.

Alth ough the SMI- i s primarily used for power managment the interrupt is also employed for the

Q uickLock/QuickBlank functions as well.





4.4.2 D IRECT MEMORY ACCESS

Direct Memory Access (DMA) is a in

method by which a device accesses system memory without volving the microprocessor. Although the DMA method has been traditionally used to transfer blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well.

The DMA method reduces the amount of CPU interactions with memory, freeing the CPU fo r other processing tasks.

NOTE: This section describes DMA in general. For d etailed information regarding

DMA operation, refer to the data manual for the Intel 82801BA I/O Controller Hub.

T he 82801 ICH 2 component i ncludes the equivalen t of two 8237 DMA controllers cascaded t d ogether to provide eight D A evice. Table 4-10 lists the d efault configuration of the DMA channels.

T able 410. Default DMA Channel Assignments

Tab le 4-10.

Default DMA Channel Assignments

DMA Ch annel

Controlle r 1 (byte transfers)

0

1

2

3

Controller 2 (word transfers)

4

5

6

7

Device ID

Spare

Audio subsystem

Diskette drive

Parallel port

Cascade for con

Spare troller 1

Spare

Spare

All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note that channel 4 is not available for use other than its ca scading function for controller 1. The DMA controller 2 can tran sfer wo rds only on an even addr register define a 24-bit address that allows data t ran ess boundary. The DMA controller and page sfers within the address space of the CPU.

In addition to device configuration, each channel can be configured (through PCI Configu ration

Registers) for one of two modes of operation:

♦ LPC DMA

♦ PC/PCI DMA

The LPC DMA mode uses the LPC bus to communicate DMA channel control and is impl emented for devices using DMA through t he LPC47B367 I/O controller such as the diskette drive controller.

The PC/PCI DMA mode uses the REQ#/GNT# signals to communicate DMA channel control and is used by PCI expansion devices.





The DMA logic is accessed through two types of I/O mapped registers; page registers and controller registers.

4.4.2.1

DMA Page Registers

The DMA page register contains the eight most significant bits of the 24-bit address and work s in c onjunction with the DMA controllers to define the com plete (24-bit)address for the DMA channels. Table 4-11 lists the page register port addresses.

Table 4-11. DMA Page Register Addresses

Table 4-11.

DMA Page Register Addresses

Page Register I/O Port

C ntroller 1 (byte transfers)

Ch 0 087h

Ch 1

Ch 2

083h

081h

Ch 3

Controller 2 (word transfers)

Ch 4

Ch 5

Ch 6

Ch 7

082h n/a

08Bh

089h

08Ah

Refresh 08Fh [see note]

N OTE:

The DMA memory page register for the refresh channel must be

programmed with 00h for proper operation.

T he memory address is derived as follows:

2 4-Bit Address - Contro ller 1 (Byte Transfers)

8 -Bit Page Register 8-Bit DMA Controller

A 23..A16 A15..A0

0

2 4-Bit Address - Controller 2 (W ord Transfers)

8 -Bit Page Register

A 23..A17

16-Bit D MA Controller

A16..A01, (A00 = 0)

N ote that address line A16 from the DM A memory page regi ster is di sabled when DMA c ontroller 2 is selected. Address line A00 is not connected to when word-length transfers are selected.

DMA controller 2 and is always 0

B y not connecting A00, th e following applies:

♦ The size of the the bl ock of data that can be moved or addressed is measur ed in 1 6-bits

(words) rather than 8-bits (b ytes).

♦ The words must always be addressed on an even boundary.





DMA controller 1 can move up to 64 Kbytes of data per DMA transfer. DMA controller 2 can move up to 64 Kwords (128 Kbytes) of data per DMA transfer. Word DMA operations are only possible between 16-bit memory and 16-bit per ipherals.

The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit memory bus and the ISA bus. The refresh address is provided on lines SA00 through SA08.

A ddress lines LA23..17, S A18,19 are driven low.

The remaining address lines are in an undefined st ate during the refresh cycl e. The refresh op erations are driven by a 69.799-KHz clock generated by Interval Timer 1, C refresh rate is 128 refresh cycles in 2.038 ms. ounter 1. The

4.4.2.2 DMA Con trolle r Re sters

T able 4-1 2 lists the DMA Con tro ller Registers and their I/O of registers for each DMA controller.

port addresses. Note that there is a set

Table 4-12. DMA Controller Registers

Register

Table 4-12.

DMA Controller Registers

Controller 1 Controller 2 R/W

Write Single Mask Bit

Write All Mask Bits

Software DRQx Request

Base and Current Address - Ch 0

Current Address - Ch 0

Base and Current Word Count - Ch 0

Current Word Count - Ch 0













Temporary (Command)

Reset Pointer Flip-Flop (Command)

Master Reset (Command)

Reset Mask Register (Command)




00Ah

00Fh

009h

000h

000h

001h

001h

002h

002h

003h

003h

004h

004h

005h

005h

006h

006h

007h

007h

00Dh

00Ch

00Dh

00Eh

0D4h

0DEh

0D2h

0C0h

0C0h

0C2h

0C2h

0C4h

0C4h

0C6h

0C6h

0C8h

0C8h

0CAh

0CAh

0CCh

0CCh

0CEh

0CEh

0DAh

0D8h

0DAh

0DCh

W

R

W

R

W

R

W

R

W

W

W

W

R

W

R

R

W

W

W

W

R

W

R


4.5 SYSTEM CLOCK DISTRIBUTION

These systems use an Intel CK-type clock generator and crystal for generating the clock signals required by the system board components. Table 4-13 lists the system board clock signals and how they are distributed.

Table 4-13. Clock Generation and Distribution

Table 4-13.

Clock Generation and Distribution

Frequncy on

66, 100, or 133 MHz

100 or 133 MHz

66 MHz

48 MHz

33 MHz

14.31818 MHz

C K

CK

CK

Proce

DIM

ICH sso

M so

2, AG r, MCH ckets

P Graphic s Cntlr. [1]

CK

C K

ICH2, I/

Proces r CK

O Cntlr. so r, ICH2, P CI Slots

NOTES:

[1] Routed to on-board controller on Deslpro EN SFF.

Routed to AGP slot on Desktop and Configurable Minitow er.

C ertain clock out put power modes to conserve energy. Clock output control is handled through the SMBus interface by BIOS.





4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY

The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions are provided by the 82801 ICH2 component and is MC146818-compatible. As shown in the following figure, the 82801 ICH2 component provides 256 bytes of battery-backed RAM divide into two 128-byte configuration memory areas. Th e RTC uses the first 14 bytes (00-0Dh) of the d st andard memory area. All locations of the standard memory area (00-7Fh) can be directly accessed using conventional OUT and IN assembly language instructio ns through I/O ports

70h/71h, although the suggested method is to use the INT15 AX=E823h BIOS call.

0Dh

0Ch

0Bh

Register D

Register C

Register B

82801

FFh

0Ah

09h

08h

07h

Register A

Year

Month

Date of Month

Extended Config.

Memory Area

(128 bytes)

80h

06h

05h

04h

03h

02h

01h

00h

Day of Week

Hours (A larm)

Hours (Timer)

Minutes (Alarm)

Minutes (Timer)

Seconds (Alarm)

Seconds (Timer)

Standard Config.

Memory Area

(114 bytes)

RTC Area

(14 bytes)

7Fh

0Eh

0Dh

00h

CMOS

Figure 4-10. Configuration Memory Map

A lithium 3-VDC battery is used for maintaining the RTC and configuration memory while the system is powered down. During system o peration a wire -Ored circuit allows the RTC and configuration memory to dra h w power from the power supply. The batt oard and has a life expe ctancy of fou r to eight y ery is located in a battery ears. When the battery has expired it is replaced with a Renata CR2032 or equivalent 3VDC lithium ba ttery.

4.6.1 CLE ARI NG CMOS

The content s of configuration m emory (includ ing t he Power-On Password) can be cleared by the f ollow ing pr ocedure:

1 . T urn of f the unit.

2 . D isconn ect the AC power cord from t he o utlet and /or sy stem unit.

3 . R emove the chassis hood (cover) and ins ure th at no LE Ds on the system board are il lumina ted.

4 . Pr ess an e system board.

5 . R eplace the chassis hood (cover).

6 . R econn ect the AC power cord to th e outl et and/or syste m unit.

7. Turn the unit on.

To clear only the Power-On Password refer to section 4.7.1.1.





4.6.2 CMOS ARCHIVE AND RESTORE

D uring the boot sequence the BIOS saves a copy of NVRAM (CMOS contents, password(s) and other system variables) in a portion of the flash ROM. Should the system become un-usable, the last good copy of NVRAM data can be restored with the Power Button Override function. Th function is invoked with the following procedure: is

1. With the unit powered down, press and release the power button.

2. Immediately after releasing the power button in step 1, press and hold the power button until the unit powers down. This action will be recorded as a Power Button Override event.

With the next startup sequence the BIOS will detect the occurrence of the Power Button Overrid e event and will load the backup copy of NVRAM from the ROM to the CMOS.

NOTE: The Power Button Override feature does not allow quick cycling of the system

(turning on then off). If the power cord is disconnected during the POST routine, the splash screen image may beco me corrupted, requiring a re-flashing of the ROM (refer to chapter 8, BIOS ROM).

4.6.3 STANDARD CMOS LOCATIONS

Table 4-14 and the following paragraphs describe standard configuration me mory locations 0Ah-

3Fh. These locations are accessible through using OU T/IN assembly language instructions using p ort 70/71h or BIOS function INT15, AX=E823h.

Table 4-14. Configuration Memory (CMOS) Map

Table 4-14.

Configuration Memory (CMOS) Map

Location Function Location Function

00-0Dh

0Eh

0Fh

Real-time clock

Diagnostic status

System reset code

24h

25h

26h

10h

11 h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

Diskette drive type

Reser ved

Hard drive type

Security functions

Equipment installed

Base memory size, low byte/KB

Base memory size, high byte/KB

Extended memory, low byte/KB

Extended memory, high byte/KB

Hard drive 1, primary controller

Hard drive 2, primary controller

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh-2Fh

30h-31h

32h

33h

Hard drive 1, secondary controller 34h

Hard drive 2, secondary controller 35h

Enhanced hard drive support 36h

1Eh Reserved

1Fh Power management functions 40-FFh

NOTES:

System board ID

System architecture data

Auxiliary peripheral configuration

Speed control external drive

Expanded/base mem. size, IRQ12

Miscellaneous configuration

Hard drive timeout

System inactivity timeout

Monitor timeout, Num Lock Cntrl

Additional flags

Checksum of locations 10h-2Dh

Total extended memory tested

Century

Miscellaneous flags set by BIOS

APM status flags

ECC POST test single bit

Feature Control/Status

Assume unmarked gaps are reserved.

Higher locations (>3Fh) contain information that should be accessed using the INT15, AX=E845h





BIOS function (refer to Chapter 8 for BIOS function descriptions).

4.7 MANAGEMENT

T his section describes functions having to do with security, power management, temperature, and overall status. These functions are handled by hardware and firmware (BIOS) and generally nf .

4.7.1 SECURITY FUNCTIONS

These systems include various features that provide different levels of security. Note that this subsection describes only the hardware functionality (including that supported by S etup) and does not describe security features that may be provided by the operating system and application software.

These systems include a power-on password, which may be enabled or disabled a

(cleared) through

jumper on the system board. The jumper controls a GPIO input to the 82801 ICH2 that is c hecked during POST. The password is stored in configuration memory (CMOS) and if enabled and then forgotten by the us er will require that either the password be cleared (preferable solution a nd described below) or the entire CMOS be cleared (refer to section 4.6).

To clear the password, use the following procedure:

1. Turn off the system and disconnect the AC power cord from the outlet and/or system unit.

2. Remove the cover (hood) as described in the appropriate User Guide or Maintainance And

Service Guide. Insure that all system board LEDs are off (not illuminated).

3. Locate the password clear jumper (header is labeled E49 on these systems) and move the jumper from pins 1 and 2 and place on (just) pin 2 (for safekeeping).

4. Replace the cover.

5. Re-connect the AC power cord to the AC outlet and/or system unit.

6. Turn on the system. The POST routine will clear and disable the password.

7. To re-enable the password feature, repeat steps 1-6, replacing the jumper on pins 1 and 2 of header E49.

T he Setup utility may be configured to be always changeable or changeable only by entering a password. The password is held on CMOS and, if forgotten, will require that CMOS be cleared

(refer to section 4.6).





4.7.1.3 Cable Lock Provision

These systems include a chassis cutout (on the rear panel) for the attachment of a cable lock mechanism.

4.7.1.4

I/O Interface Security

The serial , parallel, USB, and d iskette interfaces may be disa bled individually through the Setup utility to g from a rem uard against ovable me unauthorized ac dia drive (such as cess to a system. In

the diskette drive)

addition, the ability to write to or boot

may be enabled through the Setup utility. Th e disabling of the seri al, para llel, and diskette in terfaces are a function of the

LPC47B3 67 I/O controlle r. The USB p orts are controlled through the 82801 ICH2.

4 .7.1.5 Chassis

T he Small Form Factor and Desktop systems feature Smart Cover (hood) Sensor and Smart Cover

(hood) Lock mechanisms to inhibit unauthorized tampering of the system unit.

S mart Cover Sensor

The Sm a ll Form Factor and Desktop systems include a plunger switch that, when the cover (hood) v this “intr usion” event by setting a specific bit. T

2801 ICH2. The battery-backed logic will record his bit will remain set (even if the cover is replaced) until the system is powered up and the user completes the boot sequence successfully, at which time the bit will be cleared. Through Setup, the user can set this function to be used by

A lert-On-LAN and or one of three levels of support for a “cover removed” condition:

Level 0 - Cover remov al indication is essentially disabled at this level. During POST, status bit is c leared and no ot her action is taken by BIOS.

L s

evel 1 - Duri ng POST the message “The computer’s c ystem start up” is displayed and t ime stamp in CMOS over h

is up dat as been rem ed. oved since the last

L evel 2 - During POST the “The computer’s cov er has b een removed sin ce th e last syst em start u a p” message is displayed, time stamp in CMOS i dministrator pass word. s updat ed, a nd the user i s pro mpted for t he

Smart Cover Lock

T a he Sma ctivated ll Form Factor and Desktop systems includ e a solenoid-operated locking bar that, when

, prevents the cover (hood) from being removed. The GPIO ports 44 and 45 of the

L m

PC47B ay be b

367 I/O controller provide the lock and unlock signals to the solenoid.

ypassed by removing special screw

A locked hood s that hold the locking mechanism in place. The sp ecial screws are removed with the Compaq Smart Cover Lock Failsafe Key.





4.7.2 POWER MANAGEMENT

bas eline hardware support of ACPI- and APM-comp software. Key power-consuming components (pro pset, I/O controll er, and fan) placed into a reduced power mode either automatically or by user control. The sy stem can then be

ACPI Wake-Up Event

Power Button

RTC Alarm

Wake On LAN (w/NIC)

PME

Serial Port Ring

Suspend or soft-off

Suspend or so ft-o ff

Suspend or soft-off

Suspend or soft-off

Suspend or soft-off

4.7.3 SYSTEM STATUS

These systems provide a visual indication of system boot and ROM flash status through the keyboard LEDs and operational status using bi-colored power and hard drive activity LEDs as indicated in Tables 4-15 and 4-16 respectively.

NOTE: The LED indications listed in Table 4-15 are valid only for PS/2-type keyboards. A USB keyboard will not provide LED status for the listed events, although audible (beep) indications will occur.

Table 4-15. System Boot/ROM Flash Status LED Indications

Table 4-15.

System Boot/ROM Flash Status LED Indications

Ev ent

Sy stem memory failure [1]

Gr aphics controller failure [2]

System failure prior to graphics cntlr. initialization [3]

RO MPAQ diskette not present, faulty, or drive prob.

Pa ssword prompt

Invalid ROM detected - flash failed

Keyboard locked in network mode

Successful boot block ROM flash

NOTES:

NUM Lock

LED

Blinking

Off

Off

On

Off

Blinking [4]

Blinking [5]

On [6]

CAPs Lock

LED

Off

Blinking

Off

Off

On

Blinking [4]

Blinking [5]

On [6]

[1] Accompanied by 1 sho rt, 2 long audio beeps

[2] Accompanied by 1 long, 2 short audio beeps

[3] Accompanied by 2 long, 1 short audio beeps

[4] All LEDs will blink in sync twice, accompanied by 1 long and three short audio beeps

[5] LEDs will blink in sequence (NUM Lock, then CAPs Lock, then Scroll Lock)

[6] Accompanied by rising audio tone.

Scroll Lock

LED

Off

Off

Blinking

Off

Off

Blinking [4]

Blinking [5]

On [6]





Table 4-16. System Operational Status LED Indications

Table 4-16.

System Operationa l Status LED Indications

Sy stem Status

S0: System on (normal operation)

S1: Suspend

S3: Suspend to RAM

S4: Suspend to disk

S5: Soft off

Processor not seated

CPU thermal shutdown

ROM er ror

Pow er supply rowbar activated

Sy stem off

Power

LED

Steady green

Blinks green @ 1 Hz

Blinks green @ 1 Hz

Blinks green @ 0.5 Hz

Off - clear

Stead y red

Off (system p owers dow n)

Blinks red @ 1 Hz

.5

Off

Hard Drive

LED

Green w/HD activity

Off

Off

Off

Off

Off

Off (system powers down)

Off

Off

Off

T RM AL S EN SING AND COOLING

A p ll sy rovi stems feature a v ariable-speed fan as part of the power supply ass de a system board connection for a processor fan, which is prese emb ly. All systems also nt in all units. Desktop and

C onfi gurable Minitower systems provide an auxiliary chassis fan. All fans are controlled through temperature sensing logic both on the system board and in the power supply. Electrically, there are slight differences between the Small Form Factor (Figure 4-11) and the desktop and configurable minitower (Figure 4-12), although functionally op eration is the same.

An ASIC monitors a thermal diode internal to the processor and provides a Fan CMD signal that th e Speed Control logic uses to vary the speed of the fan(s) through the negative terminal of the fa c n(s). The turning off of the fan(s) as the result from the system bein g placed into a Sleep ondition is initiated by the control ASIC asserting the Fan Off- signal, which results in the

O n/Off Control logic shutting off the +12 volts to the fan(s).

T he main differences between the system types are as follow s:

♦ In the Small Form ci rcui t, is mounte

Factor system the processor fan, controlled by a separate speed control d in the fro nt of the chassis (separate from the heat sink assembly) and air is

the processor's heat sink by an air ba ffle .

♦ fans speed-controlled by the ASIC through the power supply so that a thermal condition of the processor or power supply will affect all fans simultaneously.

T ypical cooling conditions include t he fol lowing:

1. Normal – Low fan speed.

2. Hot processor – ASIC directs Speed Control logic to increase speed of fa n(s).

3. Hot power supply – Power supply increases speed of fan(s).

4. Sleep state – Fan(s) turned off. Hot processor or power supply will result in starting fan(s).





High and low thermal parameters are programmed into the ASIC by BIOS during POST. If the high thermal parameter is reached then the fan(s) will be turned on full speed and the Therm- signal will be asserted. The asserted Therm- signal can, with the proper software setup, be used by the 82801 ICH2 to initiate an AOL message for transmission over a network (refer to Network

Interface Controller subsection in Chapter 5).

NOTE: These systems do not support thermister-based fans used on earlier products.

Processor

Control

ASI C

Fan

Sense

Fan CMD

Therm-

Interrupt

SMBus

Speed

Control

82801

ICH2

Fan Header

P70

(-)

+5 VDC (+)

1

2

3

P1

10

13

Fan

Sink

Fan

SPD

Power Supply Assembly

Speed

Control

(-)

PS Fan

+5 VDC (+)

PS

Circuits

F a Control Block Diagram

Processor

Cont rol

AS IC

Chassis

Fan Sense

CPU Fan Sense

Fan CMD

Therm-

SMBus

82 801

ICH2

+5 VDC

Chassis Fan

Header P8

(-)

(+)

1

2

3

CPU Fan Header

P70

+5 VDC

(-)

(+)

1

2

3

P1

24

12

Fan

Sink

Fan

SPD

Power Supply Assembly

PS Fan

Speed

Control

(-)

+5 VDC

(+)

PS

Circuits

Figure 4 -12. Desktop/Configurable Minitower Fan Control Block D iagram





4.8 REGISTER MAP AND MISCELLANEOUS FUNCTIONS

This section contains the system I/O map and information on general-purpose functions of the

ICH2 and I/O controller.

4.8.1 SYSTEM I/O MAP

Table 4-17 lists the fixed addresses of the input/output (I/O) ports.

Table 4-17. System I/O Map

I/O Port

0000..001F

h

0020..002D

h

002E, 002F h

0030..003D

0040..0042

004E, 004F h

0050..0052

h

0060..0067

h

0070..0077

Table 4-17.

System I/O Map

Fu nction

DMA Controlle r 1

In terrupt Controller 1

Index, Data Ports to LPC4 7B367 I/O Controlle r (prim ary) r

Index, Dat a Ports to LPC47B367 I/O Controller (secondary)

Timer / Cou nter

Microcontroller, NMI Contro ller (alternating addresses)

0092h

00A0..00B

1h

00B2h, 00B 3h

Cont roller

Port A, Fast A 20/Reset Generator

Cont roller

Interrupt Controller 2

APM Control/Status P orts

00C0..00DFh

00F0h

0170..0177

h

01F0..01F7

h

0278..027F

h

02E8..02EFh

02F8..02FFh

0370..0377

h

0376h

0378..037Fh

DMA Controller 2

Coprocessor error reg ister

IDE Controller 2 (active only if standard I/O space is enabled for primary drive)

IDE Controller 1 (active only if standard I/O space is enabled for secondary drive)

Pa rallel Port (LPT2)

Serial Port (COM4)

Serial Port (COM2)

Di skette Drive Controller Secondary Address

IDE Controller 2 (active only if standard I/O space is enabled for primary drive)

Parallel Port (LPT1)

03BC..03BEh

03E8..03EFh

03F0..03F5h

03F6h

03F8..03FFh

04D0, 04D1h

0678..067Fh

0778..077Fh

07BC..07BEh

0CF8h

0CF9h

0CFCh

NOTE:


Serial Port (COM3)

Diskette Drive Controller Primary Addresses

IDE Controller 1 (active only if standard I/O space is enabled for sec. drive)

Serial Port (COM1)

Interrupt Controller




PCI Configuration Address (dword access only )

Reset Control Register

PCI Configuration Data (byte, word, or dword access)

Assume unmarked gaps are unused, reserved, or used by functions that employ variable I/O address mapping. Some ranges may include reserved addresses.





4.8.2 LPC47B367 I/O CONTROLLER FUNCTIONS

T he LPC47B367 I/O controller contains various functions such as the keyboard/mouse interfaces, disk ette interface, serial interfaces, and parallel interface. While the control of these interfaces uses fu

standard AT-type I/O addressing (as described in chapter 5) the conf iguration of these nctions uses indexed ports unique to the LPC47B367. In these systems, hardware strapping selec devic ts I/O addresses 02Eh and 02Fh es within the

at reset as

LPC47B367. Table 4-18

the Index/Da ta ports for accessing the logical

lists the PnP standa rd control registers for the

LPC4 7B367.

Tabl e 4-18 LPC 47B367 I/O Controller Register s

Table 4-18.

LPC47B367 I/O Contro ller Con trol Re gis ters

Index Function

03h Reserved

07h

20h

Logical Device (Interface) Select:

00h = Diskette Drive I/F

01h = Reserved

02h = Res erved

03h = Para llel I/F

04h = Serial I/F (UART 1/Port A)

05h = Serial I/F (UART 2/Port B)

06h = Reserved

07h = Keyboard I/F

08h = Reserved

09h = Reserved

0Ah = Runtime Registers (GPIO Config.)

0Bh = SMBus Configuration

Super I/O ID Register (SID)

21h Revision

22h Logical Device Power Control

23h

24h

Logical Device Power Management

PLL / Oscillator Control

25h Reserved

26h Configuration Address (Low Byte)

27h Configuration Address (High Byte)

28 -2Fh Reserved

NOTE:

00h

00h

56h

--

00h

00h

04h

For a detailed description of registers refer to appropriate SMC documentation.

The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) afte r the configuration phase has been activated by writing 55h to I/O port 2Eh. The desired interface

(l ogical device) is initiated by firmware selecting logical device number of the 47B347 using the following sequence:

1. Write 07h to I/O register 2Eh.

2. Write value of logical device to I/O register 2Fh.

3 . Write 30h to I/O register 2Eh.

4. Write 01h to I/O register 2Fh (this activates the interface).

Writing AAh to 2Eh deactivates the configuration phase.





The systems covered in this guide utilize the following specialized functions built into the LPC

47B367 I/O Controller:

♦ Power/Hard drive LED control – The I/O controller provides color and blink control for the front panel LEDs used for indicating system events as listed below:

System Status Power LED HD LED

S0: System on (normal operation)

S1: Suspend

S3: Suspend to RAM

S4: Suspend to disk

S5: Soft off


CPU thermal shutdown

ROM error

Power supply crowbar activated

System off

Steady green

Blinks green @ 1 Hz

Blinks green @ 1 Hz

Blinks green @ 0.5 Hz

Off - clear

Steady red


Blinks red @ 1 Hz

Blinks red @ 0.5 Hz

Off

Green w/HD activity

Off

Off

Off

Off

Off


Off

Off

Off

NOTE:

[1] Later systems using PCA#s 011305, 011308, or 011311 will power down for this condition.

♦ Intruder sensing – Used on Small Form Factor and Desktop models, battery-backed D-latch logic internal to the LPC47B367 is connected to the hood sensor switch to record hood

(cover) removal.

♦ Hood lock/unlock – Used on Small Form Factor and Desktop models, logic internal to the

LPC47B34x controls the lock bar mechanism.

♦ I/O security – The parallel, serial, and diskette interfaces may be disabled individually by software and the LPC47B367’s disabling register locked. If the disabling register is locked, a system reset through a cold boot is required to gain access to the disabling (Device Disable) register.

♦ Processor present/speed detection – One of the battery-back general-purpose inputs (GPI26) of the LPC47B367 detects if the processor has been removed. The occurrence of this event is passed to the ICH2 that will, during the next boot sequence, initiate the speed selection routine for the processor. The speed selection function replaces the manual DIP switch configuration procedure required on previous systems.

♦ Legacy/ACPI power button mode control – The LPC47B367 receives the pulse signal from the system’s power button and produces the PS On signal according to the mode (legacy or

ACPI) selected. Refer to chapter 7 for more information regarding power management.





Chapter 5

INPUT/OUTPUT INTERFACES

5. Chapter 5 INPUT/OUTPUT INTERFACES


This chapter describes the standard (i.e., system board) interfaces that provide input and output

(I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped registers. The following I/O interfaces are covered in this chapter:

♦ Enhanced IDE interface (5.2)

♦ Diskette drive interface (5.3)

♦ Serial (5.4)

♦ Parallel interface (5.5)

♦ Universal serial bus interface (5.7)

♦ Keyboard/pointing device interface (5.6)

♦ Audio subsystem (5.8)

♦ Network interface controller (5.9) page 5-1 page 5-4 page 5-11 page 5-16 page 5-22 page 5-26 page 5-32

5.2 ENHANCED IDE INTERFACE

The enhanced IDE (EIDE) interface consists of primary and secondary controllers integrated into the 82801 ICH2 component of the chipset. Two 40-pin IDE connectors (one for each controller) are included on the system board. Each controller can be configured independently for the following modes of operation:

♦ Programmed I/O (PIO) mode – CPU controls drive transactions through standard I/O mapped registers of the IDE drive.

♦ 8237 DMA mode – CPU offloads drive transactions using DMA protocol with transfer rates up to 16 MB/s.

♦ Ultra ATA/100 mode – Preferred bus mastering source-synchronous protocol providing transfer rates of 100 MB/s.

NOTE: These systems include 80-conductor data cables required for UATA/66 and /100 modes.

5.2.1 IDE PROGRAMMING

The IDE interface is configured as a PCI device during POST and controlled through I/O-mapped registers at runtime.



5-1


Chapter 5 Input/Output Interfaces

Hard drives types not found in the ROM’s parameter table are automatically configured as to

(soft)type by DOS as follows:

Primary controller: drive 0, type 65; drive 1, type 66

Secondary controller: drive 0, type 68; drive 1, type 15

Non-DOS (non-Windows) operating systems may require using Setup (F10) for drive configuration.

The IDE controller is configured as a PCI device with bus mastering capability. The PCI configuration registers for the IDE controller function (PCI device #31, function #1) are listed in

Table 5-1.

Table 5–1. IDE PCI Configuration Registers

PCI Conf.

Addr.

Table 5-1.

EIDE PCI Configuration Registers (82801, Device 31/Function 1)

Register

Reset

Value

PCI Conf.

Addr. Register

02-03h

04-05h

06-07h

09h

0Ah

0Bh

0Dh

0Eh

NOTE:

Device ID

PCI Command

PCI Status

Programming

Sub-Class

Base Class Code

Master Latency Timer

Header Type

244Bh 20-23h

0000h 2C, 2Dh

0280h 2E, 2Fh

80h

01h

01h

00h

00h

40-43h

44h

48h

4A-4Bh

54h

BMIDE Base Address

Subsystem Vender ID

Subsystem ID

Pri./Sec. IDE Timing

Slave IDE Timing

Sync. DMA Control

Sync. DMA Timing

EIDE I/O Config.Register

Reset

Value

0’s

1

0000h

0000h

0’s

0’s

00h

00h

0000h

00h

Assume unmarked gaps are reserved and/or not used.

5.2.1.2 IDE Bus Master Control Registers

The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2.

These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI configuration register 20h in the previous table.

Table 5–2. IDE Bus Master Control Registers

Table 5-2.

IDE Bus Master Control Registers

I/O Addr.

Offset

Size

(Bytes) Register

Default

Value

00h

02h

04h

08h

0Ah

0Ch

1

2

4

1

1

4

Bus Master IDE Command (Primary)

Bus Master IDE Status (Primary)

Bus Master IDE Descriptor Pointer (Pri.)

00h

00h

0000 0000h

Bus Master IDE Command (Secondary)

Bus Master IDE Status (Secondary)

00h

00h

Bus Master IDE Descriptor Pointer (Sec.) 0000 0000h

NOTE:

Unspecified gaps are reserved, will return indeterminate data, and should not be written to.

5-2 Compaq Evo and Workstation Personal Computers




5.2.2 IDE CONNECTOR

This system uses a standard 40-pin connector for the primary IDE device and connects (via a cable) to the hard drive installed in the right side drive bay. Note that some signals are re-defined for UATA/33 and higher modes, which require a special 80-conductor cable (supplied) designed to reduce cross-talk. Device power is supplied through a separate connector.

Figure 5-1. 40-Pin Primary IDE Connector (on system board).

Table 5–3. 40-Pin Primary IDE Connector Pinout

Table 5-3.

40-Pin Primary IDE Connector Pinout

Pin Signal Description Pin

10

11

12

13

14

15

16

17

6

7

8

9

2 GND Ground

3 DD7 Data Bit <7>

4

5

DD8

DD6

Data Bit <8>

Data Bit <6>

DD9

DD5

DD10

DD4

Data Bit <9>

Data Bit <5>

Data Bit <10>

Data Bit <4>

DD11

DD3

DD12

DD2

DD13

DD1

DD14

DD0

18

19

DD15

GND

20 --

Data Bit <11>

Data Bit <3>

Data Bit <12>

Data Bit <2>

Data Bit <13>

Data Bit <1>

Data Bit <14>

Data Bit <0>

Data Bit <15>

Ground

Key

28

29

30

31

32

33

34

35

21 DRQ

22 GND

23 IOW-

24

25

26

27

GND

IOR-

GND

IORDY

CSEL

DAK-

GND

IRQn

IO16-

DA1

DSKPDIAG

DA0

36

37

38

39

DA2

CS0-

CS1-

HDACTIVE-

40 GND

Ground

I/O Write [1]

Ground

I/O Read [2]

Ground

I/O Channel Ready [3]

Cable Select

DMA Acknowledge

Ground

Interrupt Request [4]

16-bit I/O

Address 1

Pass Diagnostics

Address 0

Address 2

Chip Select

Chip Select

Drive Active (front panel LED) [5]

Ground

NOTES:

[1] On UATA/33 and higher modes, re-defined as STOP.

[2] On UATA/33 and higher mode reads, re-defined as DMARDY-.

On UATA/33 and higher mode writes, re-defined as STROBE.

[3] On UATA/33 and higher mode reads, re-defined as STROBE-.

On UATA/33 and higher mode writes, re-defined as DMARDY-.

[4] Primary connector wired to IRQ14, secondary connector wired to IRQ15.

[5] Pin 39 is used for spindle sync and drive activity (becomes SPSYNC/DACT-)

when synchronous drives are connected.



5-3



5.3 DISKETTE DRIVE INTERFACE

The diskette drive interface supports up to two diskette drives, each of which use a common cable connected to a standard 34-pin diskette drive connector. All models come standard with a 3.5-inch

1.44-MB diskette drive installed as drive A. The drive designation is determined by which connector is used on the diskette drive cable. The drive attached to the end connector is drive A while the drive attached to the second (next to the end) connector) is drive B.

On all models, the diskette drive interface function is integrated into the LPC47B357 super I/O component. The internal logic of the I/O controller is software-compatible with standard 82077type logic. The diskette drive controller has three operational phases in the following order:

♦ Command phase - The controller receives the command from the system.

♦ Execution phase - The controller carries out the command.

♦ Results phase - Status and results data is read back from the controller to the system.

The Command phase consists of several bytes written in series from the CPU to the data register

(3F5h/375h). The first byte identifies the command and the remaining bytes define the parameters of the command. The Main Status register (3F4h/374h) provides data flow control for the diskette drive controller and must be polled between each byte transfer during the Command phase.

The Execution phase starts as soon as the last byte of the Command phase is received. An

Execution phase may involve the transfer of data to and from the diskette drive, a mechnical control function of the drive, or an operation that remains internal to the diskette drive controller.

Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2 and DACK2- signals for control.

The Results phase consists of the CPU reading a series of status bytes (from the data register

(3F5h/375h)) that indicate the results of the command. Note that some commands do not have a

Result phase, in which case the Execution phase can be followed by a Command phase.

During periods of inactivity, the diskette drive controller is in a non-operation mode known as the

Idle phase.





5.3.1 DISKETTE DRIVE PROGRAMMING

Programming the diskette drive interface consists of configuration, which occurs typically during

POST, and control, which occurs at runtime.

The diskette drive controller must be configured for a specific address and also must be enabled before it can be used. Address selection and enabling of the diskette drive interface are affected by firmware through the PnP configuration registers of the 47B357 I/O controller during POST.

The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the configuration phase has been activated by writing 55h to I/O port 2Eh. The diskette drive I/F is initiated by firmware selecting logical device 0 of the 47B357 using the following sequence:


2. Write 00h to I/O register 2Fh (this selects the diskette drive I/F).


4. Write 01h to I/O register 2Fh (this activates the interface).

Writing AAh to 2Eh deactivates the configuration phase. The diskette drive I/F configuration registers are listed in the following table:

Table 5–4. Diskette Drive Controller Configuration Registers

Table 5-4.

Diskette Drive Interface Configuration Registers

Index

Address Function R/W

Reset

Value

30h Activate

60-61h Base Address

70h

74h

Interrupt Select

DMA Channel Select

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

01h

03F0h

06h

02h

02h

00h

FFh

00h

00h

For detailed configuration register information refer to the SMSC data sheet for the LPC47B357

I/O component.

5.3.1.2 Diskette Drive Interface Control

The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette drive interface can be controlled by software through the LPC47B357’s I/O-mapped registers listed in Table 5-5. The diskette drive controller of the LPC47B357 operates in the PC/AT mode in these systems.



5-5



Table 5–5. Diskette Drive Interface Control Registers

Pri.

Addr.

3F0h

3F1h

3F2h

3F3h

3F4h

Table 5-5.

Diskette Drive Interface Control Registers

Sec.

Addr.

Register

370h Status Register A:

<7> Interrupt pending

<6> Reserved (always 1)

<5> STEP pin status (active high)

<4> TRK 0 status (active high)

<3> HDSEL status (0 = side 0, 1 = side 1)

<2> INDEX status (active high)

<1> WR PRTK status (0 = disk is write protected)

<0> Direction (0 = outward, 1 = inward)

371h Status Register B:

<7,6> Reserved (always 1’s)

<5> DOR bit 0 status

<4> Write data toggle

<3> Read data toggle

<2> WGATE status (active high)

<1,0> MTR 2, 1 ON- status (active high)

372h Digital Output Register (DOR):

<7,6> Reserved

<5,4> Motor 1, 0 enable (active high)

<3> DMA enable (active high)

<2> Reset (active low)

<1,0> Drive select (00 = Drive 1, 01 = Drive 2, 10 = Reserved, 11 = Tape drive)

373h Tape Drive Register (available for compatibility)

374h Main Status Register (MSR):

<7> Request for master (host can transfer data) (active high)

<6> Transfer direction (0 – write, 1 = read)

<5> non-DMA execution (active high)

<4> Command busy (active high)

<3,2> Reserved

<1,0> Drive 1, 2 busy (active high)

Data Rate Select Register (DRSR):

<7> Software reset (active high)

<6> Low power mode enable (active high)

<5> Reserved (0)

<4..2> Precompensation select (default = 000)

<1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250 Kb/s, 11 = 2/1

Mb/s)

<7..0> Data

3F6h 376h Reserved

3F7h 377h Digital Input Register (DIR):

<7> DSK CHG status (records opposite value of pin)

<6..0> Reserved (0’s)

Configuration Control Register (CCR):

<7..2> Reserved

<1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250 Kb/s, 11 = 2/1

Mb/s)

NOTE: The most recently written data rate value to either DRSR or CCR will be in effect.

R/W

R

R

R/W

R/W

R

W

R/W

--

R

W





5.3.2 DISKETTE DRIVE CONNECTOR

This system uses a standard 34-pin connector (refer to Figure 5-2 and Table 5-6 for the pinout) for diskette drives. Drive power is supplied through a separate connector.

2

1

4 6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

34

33

Figure 5-2. 34-Pin Diskette Drive Connector.

Table 5–6. 34-Pin Diskette Drive Connector Pinout

Table 5-6.

34-Pin Diskette Drive Connector Pinout

Pin Signal

1

2

3

GND Ground

LOW DEN- Low density select

--- (KEY)

18

19

20

DIR-

GND

STEP-

21

22

23

GND

WR DATA-

GND

Drive head direction control

Ground

Drive head track step control

Ground

Write data

Ground

4

5

MEDIA ID- Media identification

GND Ground

Drive 4 select

SEL-

GND Ground 7

8

9

10

11

INDEX-

GND

MTR 1 ON- Activates drive motor

GND Ground

12 DRV

13

SEL-

GND

2

Media index is detected

Ground

Drive 2 select

Ground

Drive 1 select

SEL-

15

16

17

GND

MTR 2 ON-

GND

Ground

Activates drive motor

Ground

24

25

26

27

28

29

30

31

32

33

34

WR ENABLE-

GND

TRK 00-

GND

WR PRTK-

GND

RD DATA-

GND

SIDE SEL-

GND

DSK CHG-

Enable for WR DATA-

Ground

Heads at track 00 indicator

Ground

Media write protect status

Ground

Data and clock read off disk

Ground

Head select (side 0 or 1)

Ground

Drive door opened indicator



5-7



All models include two RS-232-C type serial interfaces to transmit and receive asynchronous serial data with external devices. The serial interface function is provided by the LPC47B357 I/O controller component that includes two NS16C550-compatible UARTs.

Each UART supports the standard baud rates up through 115200, and also special high speed rates of 239400 and 460800 baud. The baud rate of the UART is typically set to match the capability of the connected device. While most baud rates may be set at runtime, baud rates

230400 and 460800 must be set during the configuration phase.

5.4.1 SERIAL CONNECTOR

The serial port uses a DB-9 connector as shown in the following figure with the pinout listed in

Table 5-5.

Figure 5-3. Serial Interface Connector (Male DB-9 as viewed from rear of chassis)

Table 5–7. DB-9 Serial Connector Pinout

Pin Signal

1 CD

2

3

RX Data

TX Data

4 DTR

5 GND

Table 5-7.

DB-9 Serial Connector Pinout

Carrier Detect

Receive Data

Transmit Data

Data Terminal Ready

Ground

6

7

8

DSR

RTS

CTS

9 RI

-- --

Data Set Ready

Request To Send

Clear To Send

Ring Indicator

--

The standard RS-232-C limitation of 50 feet (or less) of cable between the DTE (computer) and

DCE (modem) should be followed to minimize transmission errors. Higher baud rates may require shorter cables.





5.4.2 SERIAL INTERFACE PROGRAMMING

Programming the serial interfaces consists of configuration, which occurs during POST, and control, which occurs during runtime.

The serial interface must be configured for a specific address range (COM1, COM2, etc.) and also must be activated before it can be used. Address selection and activation of the serial interface are affected through the PnP configuration registers of the LPC47B357 I/O controller.

The serial interface configuration registers are listed in the following table:

Table 5–8. Serial Interface Configuration Registers

Table 5-8.

Serial Interface Configuration Registers

Index

Address Function R/W

30h Activate

60h Base Address MSB

61h Base Address LSB

R/W

R/W

R/W

R/W

R/W

NOTE:

Refer to LPC47B357 data sheet for detailed register information.



5-9



5.4.2.2 Serial Interface Control

The BIOS function INT 14 provides basic control of the serial interface. The serial interface can be directly controlled by software through the I/O-mapped registers listed in Table 5-9.

Table 5–9. Serial Interface Control Registers

COM1

Addr.

3F8h

3F9h

3FAh

3FBh

3FCh

3FDh

Table 5-9.

Serial Interface Control Registers

COM2

Addr.

Register

2F8h Receive Data Buffer

Transmit Data Buffer

Baud Rate Divisor Register 0 (when bit 7 of Line Control Reg. Is set)

2F9h Baud Rate Divisor Register 1 (when bit 7 of Line Control Reg. Is set)

Interrupt Enable Register

2FAh Interrupt ID Register

FIFO Control Register

2FBh Line Control Register

2FCh Modem Control Register

2FDh Line Status Register

R/W

R

W

W

W

R/W

R

W

R/W

R/W

R

R





The legacy-light models include a parallel interface for connection to a peripheral device that has a compatible interface, the most common being a printer. The parallel interface function is integrated into theLPC47B277 I/O controller component and provides bi-directional 8-bit parallel data transfers with a peripheral device. The parallel interface supports three main modes of operation:

♦ Standard Parallel Port (SPP) mode

♦ Enhanced Parallel Port (EPP) mode

♦ Extended Capabilities Port (ECP) mode

These three modes (and their submodes) provide complete support as specified for an IEEE 1284 parallel port.

5.5.1 STANDARD PARALLEL PORT MODE

The Standard Parallel Port (SPP) mode uses software-based protocol and includes two sub-modes of operation, compatible and extended, both of which can provide data transfers up to 150 KB/s.

In the compatible mode, CPU write data is simply presented on the eight data lines. A CPU read of the parallel port yields the last data byte that was written.

The following steps define the standard procedure for communicating with a printing device:

1. The system checks the Printer Status register. If the Busy, Paper Out, or Printer Fault signals are indicated as being active, the system either waits for a status change or generates an error message.

2. The system sends a byte of data to the Printer Data register, then pulses the printer STROBE signal (through the Printer Control register) for at least 500 ns.

3. The system then monitors the Printer Status register for acknowledgment of the data byte before sending the next byte.

In extended mode, a direction control bit (CTR 37Ah, bit <5>) controls the latching of output data while allowing a CPU read to fetch data present on the data lines, thereby providing bi-directional parallel transfers to occur.

The SPP mode uses three registers for operation: the Data register (DTR), the Status register

(STR) and the Control register (CTR). Address decoding in SPP mode includes address lines A0 and A1.





5.5.2 ENHANCED PARALLEL PORT MODE

In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7 and

1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation phase is entered to detect whether or not the connected peripheral is compatible with EPP mode. If compatible, then EPP mode can be used. In EPP mode, system timing is closely coupled to EPP timing. A watchdog timer is used to prevent system lockup.

Five additional registers are available in EPP mode to handle 16- and 32-bit CPU accesses with the parallel interface. Address decoding includes address lines A0, A1, and A2.

5.5.3 EXTENDED CAPABILITIES PORT MODE

The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as well as Run Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode includes a bi-directional FIFO buffer that can be accessed by the CPU using DMA or programmed

I/O. For the parallel interface to be initialized for ECP mode, a negotiation phase is entered to detect whether or not the connected peripheral is compatible with ECP mode. If compatible, then

ECP mode can be used.

Ten control registers are available in ECP mode to handle transfer operations. In accessing the control registers, the base address is determined by address lines A2-A9, with lines A0, A1, and

A10 defining the offset address of the control register. Registers used for FIFO operations are accessed at their base address + 400h (i.e., if configured for LPT1, then 378h + 400h = 778h).

The ECP mode includes several sub-modes as determined by the Extended Control register. Two submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO is cleared and not used, and DMA and RLE are inhibited.





5.5.4 PARALLEL INTERFACE PROGRAMMING

Programming the parallel interface consists of configuration, which typically occurs during POST, and control, which occurs during runtime.

5.5.4.1 Parallel Interface Configuration

The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and also must be enabled before it can be used. When configured for EPP or ECP mode, additional considerations must be taken into account. Address selection, enabling, and EPP/ECP mode parameters of the parallel interface are affected through the PnP configuration registers of the

LPC47B357 I/O controller. Address selection and enabling are automatically done by the BIOS during POST but can also be accomplished with the Setup utility and other software.

The parallel interface configuration registers are listed in the following table:

Table 5–10. Parallel Interface Configuration Registers

Table 5-10.

Parallel Interface Configuration Registers

Index

Address Function

30h Activate

60h

61h

Base Address MSB

Base Address LSB

74h

F1h

DMA Channel Select

Mode Register 2

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

Value

00h

00h

00h

00h

04h

00h

00h





5.5.4.2 Parallel Interface Control

The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions such as initialization, character printing, and printer status are provide by subfunctions of INT 17.

The parallel interface is controllable by software through a set of I/O mapped registers. The number and type of registers available depends on the mode used (SPP, EPP, or ECP). Table 5-11 lists the parallel registers and associated functions based on mode.

Table 5–11. Parallel Interface Control Registers

Table 5-11.

Parallel Interface Control Registers

I/O

Address Register

Base Data

Base + 1h Printer

Base + 2h Control

SPP

Mode

Ports

Base + 3h

Base + 4h

Base + 5h

Base + 6h

Base + 7h

Base + 400h

Base + 400h

Base + 400h

Base + 400h

Base + 401h

Base + 402h

Address

Data Port 0

Data Port 1

Data Port 2

Data Port 3

Parallel Data FIFO

ECP Data FIFO

Test FIFO

Configuration Register A

Configuration Register B

Extended Control Register

EPP

Mode

Ports

ECP

Mode

Ports

LPT1,2,3 LPT1,2 LPT1,2,3

LPT1,2,3 LPT1,2 LPT1,2,3

--

--

LPT1,2

LPT1,2

--

--

--

--

--

--

--

--

--

--

--

LPT1,2

LPT1,2

LPT1,2

--

--

--

--

--

--

--

--

--

LPT1,2,3

LPT1,2,3

LPT1,2,3

LPT1,2,3

LPT1,2,3

LPT1,2,3

Base Address:

LPT1 = 378h

LPT2 = 278h

LPT3 = 3BCh





5.5.5 PARALLEL INTERFACE CONNECTOR

Figure 5-5 and Table 5-12 show the connector and pinout of the parallel interface connector. Note that some signals are redefined depending on the port’s operational mode.

Figure 5-4. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis)

Table 5–12. DB-25 Parallel Connector Pinout

1

2

3

Table 5-12.

DB-25 Parallel Connector Pinout

Pin Signal Function Pin

STB-

D0

D1

Strobe / Write [1]

Data 0

Data 1

14

15

16

LF-

ERR-

INIT-

Line Feed [2]

Error [3]

Initialize Paper [4]

4

10

11

D2

ACK-

BSY

Data 2

Acknowledge / Interrupt [1]

Busy / Wait [1]

17 SLCTIN- Select In / Address. Strobe [1]

18 GND Ground

19 GND Ground

20 GND Ground

21 GND Ground

22 GND Ground

23

24

GND

GND

Ground

Ground

Ground

--

12

13

NOTES:

PE

SLCT

Paper End / User defined [1]

Select / User defined [1]

25

--

GND

--

[1] Standard and ECP mode function / EPP mode function

[2] EPP mode function: Data Strobe

ECP modes: Auto Feed or Host Acknowledge

[3] EPP mode: user defined

ECP modes:Fault or Peripheral Req.

[4] EPP mode: Reset

ECP modes: Initialize or Reverse Req.





5.6 KEYBOARD/POINTING DEVICE INTERFACE

The keyboard/pointing device interface function is provided by the LPC47B357 I/O controller component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as simply the “8042”) to communicate with the keyboard and pointing device using bi-directional serial data transfers. The 8042 handles scan code translation and password lock protection for the keyboard as well as communications with the pointing device. This section describes the interface itself. The keyboard is discussed in the Appendix C.

5.6.1 KEYBOARD INTERFACE OPERATION

The data/clock link between the 8042 and the keyboard is uni-directional for Keyboard Mode 1 and bi-directional for Keyboard Modes 2 and 3. (These modes are discussed in detail in Appendix

C). This section describes Mode 2 (the default) mode of operation.

Communication between the keyboard and the 8042 consists of commands (originated by either the keyboard or the 8042) and scan codes from the keyboard. A command can request an action or indicate status. The keyboard interface uses IRQ1 to get the attention of the CPU.

The 8042 can send a command to the keyboard at any time. When the 8042 wants to send a command, the 8042 clamps the clock signal from the keyboard for a minimum of 60 us. If the keyboard is transmitting data at that time, the transmission is allowed to finish. When the 8042 is ready to transmit to the keyboard, the 8042 pulls the data line low, causing the keyboard to respond by pulling the clock line low as well, allowing the start bit to be clocked out of the 8042.

The data is then transferred serially, LSb first, to the keyboard (Figure 5-6). An odd parity bit is sent following the eighth data bit. After the parity bit is received, the keyboard pulls the data line low and clocks this condition to the 8042. When the keyboard receives the stop bit, the clock line is pulled low to inhibit the keyboard and allow it to process the data.

Start

Bit

0

D0

(LSb)

1

D1

0

D2

1

D3

1

D4

0

D5

1

D6

1

D7

(MSb)

1

Parity

1

Stop

Bit

0

Data

Clock

Th Tcy Tcl Tch

Parameter Minimum Maximum

Tcy (Cycle Time) 0 us 80 us

Tcl (Clock Low) 25 us 35 us

Tch (Clock High) 25 us 45 us

Th (Data Hold) 0 us 25 us

Tss (Stop Bit Setup) 8 us 20 us

Tsh (Stop Bit Hold) 15 us 25 us

Figure 5-5. 8042-To-Keyboard Transmission of Code EDh, Timing Diagram

Tss Tsh





Control of the data and clock signals is shared by the 8042and the keyboard depending on the originator of the transferred data. Note that the clock signal is always generated by the keyboard.

After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a parity error or timeout occurs, a Resend command is sent to the 8042.

Table 5-13 lists and describes commands that can be issued by the 8042 to the keyboard.

Table 5–13. 8042-To-Keyboard Commands

Table 5-13.

Command

Set/Reset Status Indicators

8042-To-Keyboard Commands

Value Description

EDh Enables LED indicators. Value EDh is followed by an option byte that specifies the indicator as follows:

Bits <7..3> not used

Bit <2>, Caps Lock (0 = off, 1 = on)

Bit <1>, NUM Lock (0 = off, 1 = on)

Bit <0>, Scroll Lock (0 = off, 1 = on)

Echo

Invalid Command

Select Alternate Scan Codes

Read ID

Set Typematic Rate/Display

Enable

Default Disable

Set Default

Set Keys - Typematic

Set Keys - Make/Brake

Set Keys - Make

Set Keys - Typematic/Make/Brake

Set Type Key - Typematic

Set Type Key - Make/Brake

Set Type Key - Make

Resend

Reset

Note:

[1] Used in Mode 3 only.

F7h

F8h

F9h

FAh

FBh

FCh

FDh

FEh

FFh

EEh Keyboard returns EEh when previously enabled.

EFh/F1h These commands are not acknowledged.

F0h

F2h

F3h

Instructs the keyboard to select another set of scan codes and sends an option byte after ACK is received:

01h = Mode 1

02h = Mode 2

03h = Mode 3

Instructs the keyboard to stop scanning and return two keyboard ID bytes.

Instructs the keyboard to change typematic rate and delay to specified values:

Bit <7>, Reserved - 0

Bits <6,5>, Delay Time

00 = 250 ms

01 = 500 ms

10 = 750 ms

11 = 1000 ms

Bits <4..0>, Transmission Rate:

00000 = 30.0 ms

00001 = 26.6 ms

00010 = 24.0 ms

00011 = 21.8 ms

:

11111 = 2.0 ms

F4h

F5h

F6h

Instructs keyboard to clear output buffer and last typematic key and begin key scanning.

Resets keyboard to power-on default state and halts scanning pending next 8042 command.

Resets keyboard to power-on default state and enable scanning.

Clears keyboard buffer and sets default scan code set. [1]




Clears keyboard buffer and prepares to receive key ID. [1]



8042 detected error in keyboard transmission.

Resets program, runs keyboard BAT, defaults to Mode 2.





5.6.2 POINTING DEVICE INTERFACE OPERATION

The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical to the keyboard connector both physically and electrically. The operation of the interface (clock and data signal control) is the same as for the keyboard. The pointing device interface uses the

IRQ12 interrupt.

5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING

Programming the keyboard interface consists of configuration, which occurs during POST, and control, which occurs during runtime.

The keyboard/pointing device interface must be enabled and configured for a particular speed before it can be used. Enabling and speed parameters of the 8042 logic are affected through the

PnP configuration registers of the LPC47B357 I/O controller. Enabling and speed control are automatically set by the BIOS during POST but can also be accomplished with the Setup utility and other software.

The keyboard interface configuration registers are listed in the following table:

Table 5–14. Keyboard Interface Configuration Registers

Table 5-14.

Keyboard Interface Configuration Registers

Index

Address Function

30h Activate

70h Primary Interrupt Select

72h

F0h

Secondary Interrupt Select

Reset and A20 Select

R/W

R/W

R/W

R/W

R/W





The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Subfunctions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the keyboard’s scan codes into ASCII codes). The keyboard/pointing device interface is accessed by the CPU through I/O mapped ports 60h and 64h, which provide the following functions:

♦ Output buffer reads

♦ Input buffer writes

♦ Status reads

♦ Command writes

Ports 60h and 64h can be accessed using the IN instruction for a read and the OUT instruction for a write. Prior to reading data from port 60h, the “Output Buffer Full” status bit (64h, bit <0>) should be checked to ensure data is available. Likewise, before writing a command or data, the

“Input Buffer Empty” status bit (64h, bit <1>) should also be checked to ensure space is available.

I/O Port 60h

I/O port 60h is used for accessing the input and output buffers. This register is used to send and receive data from the keyboard and the pointing device. This register is also used to send the second byte of multi-byte commands to the 8042 and to receive responses from the 8042 for commands that require a response.

A read of 60h by the CPU yields the byte held in the output buffer. The output buffer holds data that has been received from the keyboard and is to be transferred to the system.

A CPU write to 60h places a data byte in the input byte buffer and sets the CMD/ DATA bit of the

Status register to DATA. The input buffer is used for transferring data from the system to the keyboard. All data written to this port by the CPU will be transferred to the keyboard except bytes that follow a multibyte command that was written to 64h

I/O Port 64h

I/O port 64h is used for reading the status register and for writing commands. A read of 64h by the CPU will yield the status byte defined as follows:

Bit Function

7..4 General Purpose Flags.

3 CMD/DATA Flag (reflects the state of A2 during a CPU write).

0 = Data

1 = Command

2

1

0

General Purpose Flag.

Input Buffer Full. Set (to 1) upon a CPU write. Cleared by

IN A, DBB instruction.

Output Buffer Full (if set). Cleared by a CPU read of the buffer.

A CPU write to I/O port 64h places a command value into the input buffer and sets the

CMD/DATA bit of the status register (bit <3>) to CMD.





Table 5-15 lists the commands that can be sent to the 8042 by the CPU. The 8042 uses IRQ1 for gaining the attention of the CPU.

Table 5–15. CPU Commands To The 8042

Table 5-15.

CPU Commands To The 8042

Value Command Description

20h

60h

A4h

A5h

A6h

A7h

A8h

A9h

AAh

ABh

ADh

AEh

C0h

C2h

C3h

D0h

D1h

D2h

D3h

D4h

E0h

F0h-

FFh

Put current command byte in port 60h.

Load new command byte.

Test password installed. Tests whether or not a password is installed in the 8042:

If FAh is returned, password is installed.

If F1h is returned, no password is installed.

Load password. This multi-byte operation places a password in the 8042 using the following manner:

1. Write A5h to port 64h.

2.

Write each character of the password in 9-bit scan code (translated) format to port 60h.

3.

Write 00h to port 60h.

Enable security. This command places the 8042 in password lock mode following the A5h command.

The correct password must then be entered before further communication with the 8042 is allowed.

Disable pointing device. This command sets bit <5> of the 8042 command byte, pulling the clock line of the pointing device interface low.

Enable pointing device. This command clears bit <5> of the 8042 command byte, activating the clock line of the pointing device interface.

Test the clock and data lines of the pointing device interface and place test results in the output buffer.

00h = No error detected

01h = Clock line stuck low

02h = Clock line stuck high

03h = Data line stuck low

04h = Data line stuck high

Initialization. This command causes the 8042 to inhibit the keyboard and pointing device and places

55h into the output buffer.

Test the clock and data lines of the keyboard interface and place test results in the output buffer.

00h = No error detected

01h = Clock line stuck low

02h = Clock line stuck high

03h = Data line stuck low

04h = Data line stuck high

Disable keyboard command (sets bit <4> of the 8042 command byte).

Enable keyboard command (clears bit <4> of the 8042 command byte).

Read input port of the 8042. This command directs the 8042 to transfer the contents of the input port to the output buffer so that they can be read at port 60h.

Poll Input Port High. This command directs the 8042 to place bits <7..4> of the input port into the upper half of the status byte on a continous basis until another command is received.

Poll Input Port Low. This command directs the 8042 to place bits <3..0> of the input port into the lower half of the status byte on a continous basis until another command is received.

Read output port. This command directs the 8042 to transfer the contents of the output port to the output buffer so that they can be read at port 60h.

Write output port. This command directs the 8042 to place the next byte written to port 60h into the output port (only bit <1> can be changed).

Echo keyboard data. Directs the 8042 to send back to the CPU the next byte written to port 60h as if it originated from the keyboard. No 11-to-9 bit translation takes place but an interrupt (IRQ1) is generated if enabled.

Echo pointing device data. Directs the 8042 to send back to the CPU the next byte written to port

60h as if it originated from the pointing device. An interrupt (IRQ12) is generated if enabled.

Write to pointing device. Directs the 8042 to send the next byte written to 60h to the pointing device.

Read test inputs. Directs the 8042 to transfer the test bits 1 and 0 into bits <1,0> of the output buffer.

Pulse output port. Controls the pulsing of bits <3..0> of the output port (0 = pulse, 1 = don’t pulse).

Note that pulsing bit <0> will reset the system.





5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR

The legacy-light model provides separate PS/2 connectors for the keyboard and pointing device.

Both connectors are identical both physically and electrically. Figure 5-7 and Table 5-16 show the connector and pinout of the keyboard/pointing device interface connectors.

Figure 5-6. Keyboard or Pointing Device Interface Connector

(as viewed from rear of chassis)

Table 5–16. Keyboard/Pointing Device Connector Pinout

Pin Signal

1 DATA

2 NC

3 GND

Table 5-16.

Keyboard/Pointing Device Connector Pinout

Data

Ground

4 + 5 VDC

5 CLK

6 NC

Power

Clock





5.7 UNIVERSAL SERIAL BUS INTERFACE

The Universal Serial Bus (USB) interface provides asynchronous/isochronous data transfers of up to 12 Mb/s with compatible peripherals such as keyboards, printers, or modems. This high-speed interface supports hot-plugging of compatible devices, making possible system configuration changes without powering down or even rebooting systems.

NOTE: It is recommended to run the Windows 98 (or later) operating system when using USB peripherals, especially a USB keyboard and USB mouse. Problems may be encountered when using USB devices with a system running Windows 95, although some peripherals may operate satisfactorily. More information on USB compatibility and functionality may be found at the following web site: http://www.usb.org

.

As shown in Figure 5-8, the USB interface is provided by the 82801 ICH2 component. All models provide two rear-panel accessible type-A USB ports. Front panel USB ports are standard on small forma factor and all Workstation units. The Evo desktop and configurable minitower units may be upgraded to include two front panel USB ports. For more information on the USB interface refer to the following web site:

82801 ICH2

Rear Panel

Tx/Rx Data

USB

I/F #1 Tx/Rx Data

USB Port 1

USB Port 2

P24

USB

I/F #2

Tx/Rx Data

Tx/Rx Data

Front Panel

USB Port 3

USB Port 4

Standard on small form factor and all Workstation units.

Optional on Evo desktop and configurable minitower units.

Desktop and configurable minitower systems only.

Figure 5-7. USB I/F, Block Diagram

5.7.1 USB DATA FORMATS

The USB I/F uses non-return-to-zero inverted (NRZI) encoding for data transmissions, in which a

1 is represented by no change (between bit times) in signal level and a 0 is represented by a change in signal level. Bit stuffing is employed prior to NRZ1 encoding so that in the event a string of 1’s is transmitted (normally resulting in a steady signal level) a 0 is inserted after every six consecutive 1’s to ensure adequate signal transitions in the data stream.





The USB transmissions consist of packets using one of four types of formats (Figure 5-9) that include two or more of seven field types.

♦ Sync Field – 8-bit field that starts every packet and is used by the receiver to align the incoming signal with the local clock.

♦ Packet Identifier (PID) Field – 8-bit field sent with every packet to identify the attributes (in. out, start-of-frame (SOF), setup, data, acknowledge, stall, preamble) and the degree of error correction to be applied.

♦ Address Field – 7-bit field that provides source information required in token packets.

♦ Endpoint Field – 4-bit field that provides destination information required in token packets.

♦ Frame Field – 11-bit field sent in Start-of-Frame (SOF) packets that are incremented by the host and sent only at the start of each frame.

♦ Data Field – 0-1023-byte field of data.

♦ Cyclic Redundancy Check (CRC) Field – 5- or 16-bit field used to check transmission integrity.

Token Packet

SOF Packet

Sync Field

(8 bits)

Sync Field

(8 bits)

Data Packet

Handshake Packet

Sync Field

(8 bits)

Sync Field

(8 bits)

PID Field

(8 bits)

PID Field

(8 bits)

PID Field

(8 bits)

PID Field

(8 bits)

Addr. Field

(7 bits)

ENDP. Field

(4 bits)

Frame Field

(11 bits)

Data Field

(0-1023 bytes)

CRC Field

(5 bits)

CRC Field

(5 bits)

CRC Field

(16 bits)

Figure 5-8. USB Packet Formats

Data is transferred LSb first. A cyclic redundancy check (CRC) is applied to all packets (except a handshake packet). A packet causing a CRC error is generally completely ignored by the receiver.





5.7.2 USB PROGRAMMING

Programming the USB interface consists of configuration, which typically occurs during POST, and control, which occurs at runtime.

PCI

Config.

Addr.

00, 01h

02, 03h

04, 05h

06, 07h

08h

09h

0Ah

0Bh

The USB interface functions as a PCI device (31) within the 82801 component (function 2) and is configured using PCI Configuration Registers as listed in Table 5-17.

Table 5–17. USB Interface Configuration Registers

Table 5-17.

USB Interface Configuration Registers

Register

Vender ID

Device ID

PCI Command

PCI Status

Revision ID

Programming I/F

Sub Class Code

Base Class Code

Reset

Value

PCI

Config.

Addr.

8086h 0Eh

2444h 20-23h

0000h 2C, 2Dh

0280h 3Ch

00h 3Dh

00h

03h

0Ch

60h

C0, C1h

C4h

Register

Header Type

I/O Space Base Address

Sub. Vender ID

Interrupt Line

Interrupt Pin

Serial Bus Release No.

USB Leg. Kybd./Ms. Cntrl.

USB Resume Enable

Reset

Value

00h

1

00h

00h

03h

10h

2000h

00h

The USB is controlled through I/O registers as listed in table 5-18.

Table 5–18. USB Control Registers

I/O Addr.

00, 01h

02, 03h

04, 05h

06, 07

08, 0B

0Ch

10, 11h

12, 13h

Table 5-18.

USB Control Registers

Register

Command

Status

Interupt Enable

Frame Number

Frame List Base Address

Start of Frame Modify

Port 1 Status/Control

Port 2 Status/Control

Default Value

0000h

0000h

0000h

0000h

0000h

40h

0080h

0080h

00h





5.7.3 USB CONNECTOR

The USB interface provides two series-A connectors on the front panel and, on legacy-free models, three series-A USB connectors on the rear panel.

1 2 3 4

Figure 5-9. Universal Serial Bus Connector

Table 5–19. USB Connector Pinout

Table 5-19.

USB Connector Pinout

Pin Signal Description Pin

1 Vcc +5 VDC 3 USB+

4 GND

Data (plus)

Ground

5.7.4 USB CABLE DATA

The recommended cable length between the host and the USB device should be no longer than sixteen feet for full-channel (12 MB/s) operation, depending on cable specification (see following table).

Table 5–20. USB Cable Length Data

Table 5-20.

USB Cable Length Data

Conductor Size Resistance Maximum Length

20 AWG

22 AWG

24 AWG

26 AWG

28 AWG

0.036 Ω

0.057 Ω

0.091 Ω

0.145 Ω

0.232 Ω

16.4 ft (5.00 m)

9.94 ft (3.03 m)

6.82 ft (2.08 m)

4.30 ft (1.31 m)

2.66 ft (0.81 m)

NOTE:

For sub-channel (1.5 MB/s) operation and/or when using sub-standard cable shorter lengths may be allowable and/or necessary.

The shield, chassis ground, and power ground should be tied together at the host end but left unconnected at the device end to avoid ground loops.

Color code:

Data + Green

Red

Black





The systems covered in this guide come configured with one of two types of audio support:

♦

♦

Desktop/configurable minitower audio subsystem

Small form factor audio subsystem

5.8.1 FUNCTIONAL ANALYSIS

A block diagram of the audio subsystem is shown in Figure 5-11. These systems use the AC’97

Audio Controller of the 82801 ICH2 component to access and control an Analog Devices

AD1885 Audio Codec, which provides the analog-to-digital (ADC) and digital-to-analog (DAC) conversions as well as the mixing functions. All control functions such as volume, audio source selection, and sampling rate are controlled through software over the PCI bus through the AC97

Audio Controller of the 82801 ICH2. Control data and digital audio streams (record and playback) are transferred between the Audio Controller and the Audio Codec over the AC97 Link Bus.

Desktop and Configurable Minitower systems implement Business Audio, which has the codec stereo analog output applied through a headphone jack(s) and switch logic to a mono 3-watt amplifier that drives a 16-ohm speaker. The switch logic allows a system with two headphone jacks equal functionality between jacks.

Small Form Factor systems feature Premier Sound, which includes a 6-level equalizer that compensates for chassis acoustics and a low-distortion 8-watt amplifier driving a speaker.

The analog interfaces allowing connection to external audio devices include:

Mic In - This input uses a three-conductor (stereo) mini-jack that is specifically designed for connection of a condenser microphone with an impedance of 10-K ohms. This is the default recording input after a system reset. On desktops and CMTs, if the front panel assembly is installed then either microphone jack is available for use (but not simultaneously).

Line In - This input uses a three-conductor (stereo) mini-jack that is specifically designed for connection of a high-impedance (10k-ohm) audio source such as a tape deck.

Headphones Out - This input uses a three-conductor (stereo) mini-jack that is designed for connecting a set of 16-ohm (nom.) stereo headphones or powered speakers. Plugging into the

Headphones jack mutes the signal to the internal speaker and, on SFF systems, the Line Out jack as well. On desktops and CMTs, if the front panel assembly is installed then either headphone jack is available for use (but not simultaneously).

Line Out (SFF only) - This output uses a three-conductor (stereo) mini-jack for connecting left and right channel line-level signals (20-K ohm impedance). A typical connection would be to a tape recorder’s Line In (Record In) jacks, an amplifier’s Line In jacks, or to powered speakers that contain amplifiers. Plugging into the Line Out mutes the internal speaker.





82801 ICH2

Line In

PCI

Bus AC’97

Audio

Cntlr.

(L)

(R)

PC Beep Audio

AC97

Link Bus

HP Out

Audio (L/R)

L+R (Mono)

Audio

P23

CD ROM

Mic In

Headphones/

Line Out

82801 ICH2

PCI

Bus AC’97

Audio

Mic In

Line In

CD ROM

CD Audio (L)

CD Audio (R)

Cntlr.

Audio

Bias

Audio

Bias

(L)

(R)

CD Audio (L)

CD Audio (R)

(L)

(R)

AD1885

Audio

Codec

L+R Audio

PC Beep Audio

AC97

Link Bus

Internal

Speaker

+

-

Internal

Speaker

+

-

Desktop/Configurable Minitower Audio Subsystem

Small Form Factor Audio Subsystem

AD1885

Audio

Codec

Switch

Logic

Mono

Audio

Line

Sense

Line Out Audio (L/R)

HP

Sense

HP Out Audio (L/R)

Optional on Evo units, standard on workstation units.

Panel En

Equalizer

TDA

7056

LA

4301

Front Panel Assembly

(L)

(R)

(L)

(R)

(L)

(R)

Audio

Bias

Headphones/

Line Out

Mic In

Line

Out

Headphones

Out

Figure 5-10. Audio Subsystem Functional Block Diagram





5.8.2 AC97 AUDIO CONTROLLER

The AC97 Audio Controller is a PCI device (device 31/function 5) that is integrated into the

82801 ICH component and supports the following functions:

♦

♦

♦

♦

♦

♦

Read/write access to audio codec registers

16-bit stereo PCM output @ up to 48 KHz sampling

16-bit stereo PCM input @ up to 48 KHz sampling

Acoustic echo correction for microphone

AC’97 Link Bus

ACPI power management

5.8.3 AC97 LINK BUS

The audio controller and the audio codec communicate over a five-signal AC97 Link Bus (Figure

5-12). The AC97 Link Bus includes two serial data lines (SD OUT/SD IN) that transfer control and PCM audio data serially to and from the audio codec using a time-division multiplexed

(TDM) protocol. The data lines are qualified by a 12.288 MHz BIT_CLK signal driven by the audio codec. Data is transferred in frames synchronized by the 48-KHz SYNC signal, which is derived from the clock signal and driven by the audio controller. The SYNC signal is high during the frame’s tag phase then falls during T17 and remains low during the data phase. A frame consists of one 16-bit tag slot followed by twelve 20-bit data slots. When asserted (typically during a power cycle), the RESET- signal (not shown) will reset all audio registers to their default values.

T1 T2 T18 T19 T38 T39 T58

BIT_CLK

(12.288 MHz)

SYNC

(48 KHz)

SD OUT or SD IN

Codec

Ready

Bit 15 Bit 14

Slot 0

(Tag)

Bit 0 Bit 19 Bit 18

Slot 1

(Data)

Bit 0 Bit 19 Bit 18

Slot 2

(Data)

Bit 0 Bit 19

Slot Description

0 Bit 15: Frame valid bit

1

Bits 14-3: Slots 1-12 valid bits

Bits 2-0: Codec ID

Command address: Bit 19, R/W; Bits 18..12, reg. Index; Bits 11..0, reserved.

3

4

Bits 19-4: PCM audio data, left channel (SD OUT, playback; SD IN, record)

Bits 3-0 all zeros

Bits 19-4: PCM audio data, right channel (SD OUT, playback; SD IN, record)

Bits 3-0 all zeros

5 Modem codec data (not used in this system)

6-11 Reserved

Figure 5-11. AC’97 Link Bus Protocol





5.8.4 AUDIO CODEC

The audio codec provides pulse code modulation (PCM) coding and decoding of audio information as well as the selection and/or mixing of analog channels. As shown in Figure 5-13, analog audio from a microphone, tape, or CD can be selected and, if to be recorded (saved) onto a disk drive, routed through an analog-to-digital converter (ADC). The resulting left and right PCM record data are muxed into a time-division-multiplexed (TDM) data stream (SD IN signal) that is routed to the audio controller. Playback (PB) audio takes the reverse path from the audio controller to the audio codec as SD OUT data and is decoded and processed by the digital-toanalog converter (DAC). The codec supports simultaneous record and playback of stereo (left and right) audio. The Sample Rate Generator may be set for sampling frequencies up to 48 KHz.

Analog audio may then be routed through 3D stereo enhancement processor or bypassed to the output selector (SEL). The integrated analog mixer provides the computer control-console functionality handling multiple audio inputs.

Audio

Format

Mic In

Line In (L)

S e l e c t o r

Left

Audio

Right

Audio

Rec

Gain

ADC

Rec

Data (L)

Line In (R)

CD In (L)

CD In (R)

Rec

Gain

ADC

Rec

Data (R)

Analog

Output

Circuits

(L)

(R)

S

E

L

3D Proc.

Σ/Mixer

(L)

(L)

(R)

SW

PB

Gain

DAC

3D Proc.

(R)

PB

Gain

DAC

Figure 5-12. AD1885 Audio Codec Functional Block Diagram

Sample

Rate

Gen.

PB

Data (L)

PB

Data (R)

AC97

Link

I/F

SD IN

SD Out

Audio

Controller

All inputs and outputs are two-channel stereo except for the microphone input, which is inputted as a single-channel but mixed internally onto both left and right channels. The microphone input is the default active input. All block functions are controlled through index-addressed registers of the codec.





5.8.5 AUDIO PROGRAMMING

Audio subsystem programming consists configuration, typically accomplished during POST, and control, which occurs during runtime.

The audio subsystem is configured according to PCI protocol through the AC’97 audio controller function of the 82801 ICH2. Table 5-21 lists the PCI configuration registers of the audio subsystem.

Table 5–21. AC’97 Audio Controller PCI Configuration Registers

Table 5-21.

AC’97 Audio Controller

PCI Configuration Registers (82801 Device 31/Function 5)

PCI

Conf.

Addr.

Register

00-01h Vender ID

06-07h PCI Status

08h Revision ID

09h Programming

0Ah Sub-Class

0Bh Base Class Code

Value on

Reset

PCI

Conf.

Addr. Register

8086h 14-17h Native Audio Bus Mstr. Addr.

2445h 18-1Bh Reserved

0000h 1C-2Bh Reserved

0280h 2C-2Dh Subsystem Vender ID

XXh 2E-2Fh Subsystem ID

04h 3Dh Interrupt Pin

10-13h Native Audio Mixer Base Addr. 1 -- --

Value on

Reset

1

1h

1h

0000h

0000h

--

00h

02h

0’s

--

The audio subsystem is controlled through a set of indexed registers that physically reside in the audio codec . The register addresses are decoded by the audio controller and forwarded to the audio codec over the AC97 Link Bus previously described. The audio codec’s control registers

(Table 5-22) are mapped into 64 kilobytes of variable I/O space.

Table 5–22. AC’97 Audio Codec Control Registers

Offset

Addr. / Register

00h Reset

02h Master Vol.

04h Reserved

06h Mono Mstr. Vol.

08h Reserved

0Ah PC Beep Vol.

0Ch Phone In Vol.

0Eh Mic Vol.

10h Line In Vol.

12h CD Vol.

Table 5-22.

AC’97 Audio Codec Control Registers

Value

On

Reset

Offset


0100h 14h Video Vol.

8000h 16h Aux Vol.

-- 18h PCM Out Vol.

8000h 1Ah Record Sel.

-- 1Ch Record Gain

8000h 1Eh Reserved

8008h 20h Gen. Purpose

8008h 22h 3D Control

8808h 24h Reserved

8808h 26h Pwr Mgnt.

Value

On

Reset

Offset


8808h 28h Ext. Audio ID.

8808h 2Ah Ext. Audio Ctrl/Sts

8808h 2Ch PCM DAC SRate

0000h 32h PCM ADC SRate

8000h 34h Reserved

-- 72h Reserved

0000h 74h Serial Config.

0000h 76h Misc. Control Bits

-- 7Ch Vender ID1

000xh 7Eh Vender ID2

Value

On

Reset

0001h

0000h

BB80h

BB80h

--

--

7x0xh

0404h

4144h

5340h





5.8.6 AUDIO SPECIFICATIONS

The specifications for the integrated AC97 audio subsystem are listed in Table 5-23.

Table 5–23. Audio Subsystem Specifications

Table 5-23.

AC97 Audio Subsystem Specifications

Paramemter Measurement

Sampling Rate 5.51 KHz to 44 KHz

Nominal Input Voltage:

Mic In (w/+20 db gain)

Line In

Impedance:

Mic In

Line In

Line Out

Signal-to-Noise Ratio (input to Line Out)

Max. Power Output (with 10% THD):

Small Form Factor

Slim Desktop/Configurable Minitower

Input Gain Attenuation Range

Master Volume Range

Frequency Response:

Codec

Speaker (Small Form Factor)

.283 Vp-p

2.83 Vp-p

1 K ohms (nom)

10 K ohms (min)

800 ohms

90 db (nom)

8 watts (into 8 ohms)

3 watts (into 16 ohms)

46.5 db

-94.5 db

20-20 KHz

450 - 4000 Hz





5.9 NETWORK INTERFACE CONTROLLER

These systems include a 10/100 Mbps network interface controller (NIC) consisting of a 82562equivalent controller integrated into the 82801BA ICH2 component coupled with a physical interface (PHY) component and an RJ-45 jack with integral status LEDs (Figure 5-14). The support firmware is contained in the system (BIOS) ROM. The NIC can operate in half- or fullduplex modes, and provides auto-negotiation of both mode and speed. Half-duplex operation features an Intel-proprietary collision reduction mechanism while full-duplex operation follows the IEEE 802.3x flow control specification. Transmit and receive FIFOs of 3 kilobytes each reduce the chance of overrun while waiting for bus access.

Active/

Link

(Green)

82801 ICH2

RJ-45

Connector

Network

Interface

Function

TX/RX

LAN

PHY

I/F

TX/RX

Speed

(Yellow)

LED Function

Green Activity/Link: reception.

Yellow Speed: Indicates link detection in 100 MB/s mode

(always on if 100Base-Tx is forced).

Figure 5-13. Network Interface Controller Block Diagram

The Network Interface Controller includes the following features:

♦ Fast Ethernet controller with 32-bit architecture and 3-KB TX/RX buffers.

♦ Dual-mode support with auto-switching between 10BASE-T and 100BASE-TX.

♦ Power down and Wake up support in both APM and ACPI environments (PME- and WOL).

♦ Alert-on-LAN (AOL v1.0) support.

♦ Link and Activity LED indicator drivers

♦ AOL support for upgrade card

The controller features high and low priority queues and provides priority-packet processing for networks that can support that feature. The controller’s micro-machine processes transmit and receive frames independently and concurrently. Receive runt (under-sized) frames are not passed on as faulty data but discarded by the controller, which also directly handles such errors as collision detection or data under-run.

The NIC uses 3.3 VDC auxiliary power, which allows the controller to support Wake-On-LAN

(WOL) and Alert-On-LAN (AOL) functions while the main system is powered down.





NOTE: For the WOL and AOL features to function as described in the following paragraphs, the system unit must be plugged into a live AC outlet. Controlling unit power through a switchable power strip will, with the strip turned off, disable WOL and

AOL functionality.

5.9.1 WAKE ON LAN SUPPORT

The NIC supports the Wired-for-Management (WfM) standard of Wake-On-LAN (WOL) that allows the system to be booted up from a powered-down or low-power condition upon the detection of special packets received over a network. The NIC receives 3.3 VDC auxiliary power while the system unit is powered down in order to process special packets. The detection of a

Magic Packet by the NIC results in the PME- signal on the PCI bus to be asserted, initiating system wake-up from an ACPI S1 or S3 state.

5.9.2 ALERT ON LAN SUPPORT

Alert-On-LAN (AOL) support allows the NIC to communicate the occurrence of certain events over a network even while the system unit is powered off. In a system-off (powered down) condition the network function of the 82801 ICH2 component receives auxiliary +3.3 VDC power

(derived from the +5 VDC auxiliary power from the power supply assembly). Certain events

(listed in Table 5-24) will result in the network function of the ICH2 to transmit an appropriate pre-constructed message over the network to a system management console.

Reportable AOL events are listed in the following table:

Table 5–24. AOL Events

Table 5-24.

AOL Events

Event Description

BIOS Failure

OS Problem

System fails to boot successfully.

System fails to load operating system after POST.

Missing/Faulty Processor Processor fails to fetch first instruction.

Thermal Condition

Heartbeat

Thermal ASIC reports high temperature.

Indication of system’s network presence (sent approximately every 30 seconds in normal operation).

The AOL implementation requirements are as follows:

1. Intel PRO/100 VM Network Connection drivers 3.80 or later (available from Compaq).

2. Intel Alert-On-LAN Utilities, version 2.5 (available from Compaq).

3. Management console running one of the following: a. HP OpenView Network Node Manager 6.x b. Intel LANDesk Client Manager c. Sample Application Console from the Intel AOL Utilities (item #2 above)





5.9.3 POWER MANAGEMENT SUPPORT

The NIC features Wired-for-Management (WfM) support providing system wake up from network events (WOL) as well as generating system status messages (AOL) and supports both

APM and ACPI power management environments. The controller receives 3.3 VDC (auxiliary) power as long as the system is plugged into a live AC receptacle, allowing support of wake-up events occuring over a network while the system is powered down or in a low-power state.

The Advanced Power Management (APM) functionality of system wake up is implemented through the system’s APM-compliant BIOS and the controller’s Magic Packet-compliant hardware. This environment bypasses operating system (OS) intervention allowing a plugged in unit to be turned on remotely over the network (i.e., “remote wake up”). In APM mode the controller will respond upon receiving a Magic Packet, which is a packet where the node’s address is repeated 16 times. Upon Magic packet detection, the controller initiates the boot sequence.

The Advanced Configuration and Power Interface (ACPI) functionality of system wake up is implemented through an ACPI-compliant OS and is the default power management mode. The following wakeup events may be individually enabled/disabled through the supplied software driver:

♦ Magic Packet – Packet with node address repeated 16 times in data portion

NOTE: The following functions are supported in NDIS5 drivers but implemented through remote management software applications (such as LanDesk).

♦ Individual address match – Packet with matching user-defined byte mask

♦ Multicast address match – Packet with matching user-defined sample frame

♦ ARP (address resolution protocol) packet

♦ Flexible packet filtering – Packets that match defined CRC signature

The PROSet Application software (pre-installed and accessed through the System Tray or

Windows Control Panel) allows configuration of operational parameters such as WOL and duplex mode.





5.9.4 NIC PROGRAMMING

Programming the NIC consists of configuration, which occurs during POST, and control, which occurs at runtime.

5.9.4.1 Configuration

The network interface function is a PCI device and configured though PCI configuration space registers using PCI protocol described in chapter 4. The PCI configuration registers are listed in the following table:

Table 5–25. NIC Controller PCI Configuration Registers

PCI

Conf.

Addr.

Table 5-25.

NIC Controller PCI Configuration Registers (ICH2 Device 8/Function 0)

Register

00-01h Vender ID

02-03h Device ID

04-05h PCI Command

06-07h PCI Status

08h Revision ID

09-0Bh Class Code

0Dh Latency Timer

0Eh Header Type

10-13h Cntrl. Reg. Base Addr. (Mem)

14-17h Cntrl. Reg. Base Addr. (I/O)

2C, 2Dh Subsystem Vender ID

Value on

Reset

8086h

2449h

0000h

0290h

Xxh

0002h

00h

00h

8

1

0000h

PCI

Conf.

Addr. Register

2E, 2Fh

34h

3Ch

3Dh

3Eh

3E, 3Fh

DCh

DDh

Subsystem ID

Capabilities Pointer

Interrupt Line

Interrupt Pin

Min. Grant

Max. Latency

Capability ID

Next Item Pointer

DE, DFh Pwr. Mgmt. Functions

E0, E1h Pwr. Mgmt. Cntrl./Sts

E3h Data

NOTE:

Assume unmarked gaps are reserved and/or not used .

Value on

Reset

0000h

DCh

00h

01h

08h

38h

01h

00h

FE21h

0000h

--

5.9.4.2 Control

The 82562 controller is controlled though registers that may be mapped in system memory space or variable I/O space. The registers are listed in the following table:

Table 5–26. NIC Control Registers

Offset


00h SCB Status

02h SCB Command

04h SCB General Pointer

08h PORT

0Ch Flash Control Reg.

0Eh EEPROM Control Reg.

10h Mgmt. Data I/F Cntrl. Reg.

14h Rx Direct Mem. Access Byte Cnt.

Table 5-26.

NIC Control Registers

No. of

Bytes

2

2

4

4

2

2

4

4

Offset


19h Flow Control Register

1Bh PMDR

1Ch General Control

1Dh General Status

1E-2Fh Reserved

30h Function Event Register

34h Function Event Mask Register

38h Function Present State Register

18h Early Receive Interrupt 1 20h Force Event Register

Not implemented in these systems (CardBus registers).

No. of

Bytes

10

4

4

4

4

2

1

1

1





5.9.5 NIC CONNECTOR

Figure 5-15 shows the RJ-45 connector used for the NIC interface. This connector includes the two status LEDs as part of the connector assembly.

Speed LED Activity LED

8 7 6 5 4 3 2 1

Pin Description

1 Transmit+

2 Transmit-

3 Receive+

6 Receive-

Figure 5-14. Ethernet TPE Connector (RJ-45, viewed from card edge)

5.9.6 NIC SPECIFICATIONS

Table 5–27. 82559 NIC Operating Specifications

Table 5-27.

NIC Specifications

Parameter

Modes Supported

Standards Compliance

OS Driver Support

Boot ROM Support

F12 BIOS Support

Bus Inteface

Power Management Support

10BASE-T half duplex @ 10 MB/s

10Base-T full duplex @ 20 MB/s

100BASE-TX half duplex @ 100 MB/s

100Base-TX full duplex @ 200 MB/s

IEEE 802.2

IEEE 802.3 & 802.3u

IEEE Intel priority packet (801.1p)

MS-DOS

MS Windows 3.1

MS Windows 95 (pre-OSR2), 98, and 2000

Professional

MS Windows NT 3.51 & 4.0

Novell Netware 3.x, 4.x, 5x

Novell Netware/IntraNetWare

SCO UnixWare 7

OpenServer

Intel PRO/100 Boot Agent (PXE 3.0, RPL)

Yes

PCI 2.2

APM, ACPI, PCI Power Management Spec.





5.9.7 NIC UPGRADING/CHANGING

The integrated NIC may be used in conjunction with another NIC card in a PCI slot. These systems provide AOL support for NIC cards that are AOL-compliant to the extent described previously in section 5.9.2. These systems also provide Remote System Alert (RSA) support for such NIC cards as the 3Com 3C905C-TX NIC card. The RSA function is similar to AOL in that the unit provides, even while powered off, system status alert messages to a network console.

Note that NIC cards implementing the RSA method do not use the PCI/SMBus for receiving alert information and therefore require, in addition to the PCI connection, an auxiliary cable connection with the system as shown in Figure 5-16.

Network

Cable

System or

Backplane board

NIC Card in PCI Slot

AOL/SOS Cable

Figure 5-15. Remote System Alert Implementation (Generic Representation)

AOL/SOS

Header P12

In the Remote System Alert implementation, the NIC card receives event notification directly from the system’s thermal and hood sensors and the LPC47B357 I/O controller over an AOL/SOS cable connection (Figure 5-17). During system-off conditions the NIC card receives auxiliary power from the 3.3 VDC auxiliary power rail on the PCI bus.

Hood Sensor

System or Backplane Board

47B37x

I/O Cntlr.

BIOS Fail

O

Intrusion

AOL/SOS

Header

1

Optional NIC Card

SOS

Thermal

ASIC

NC

NC

Fan

Fan Alert

Fan Therm.

7

PCI

Connector

PCI

Bus

PCI

Bus

Not connected on Configurable Minitower models.

Figure 5-16. RSA Logic, Block Diagram





Reportable RSA events are listed in the following table:

Table 5–28. Remote System Alert Events

Event

BIOS Failure

Thermal Condition

Chassis Intrusion [1]

Heartbeat

Table 5-28.

Remote System Alert Events

Description

System fails to boot successfully.

Thermal ASIC reports high temperature. Some systems may generate an alert message when increasing fan speed.

Smart Cover (hood) Sensor detected cover removal. This event is battery backed, meaning that should the unit be unplugged (from AC power) during cover removal, notification will occur after AC power is restored.

Indication of system’s network presence (sent approximately every 30 seconds in normal operation).

NOTE:

[1] Not supported on Configurable Minitower models.

The current Remote System Alert implementation requirements are as follows:

1. 3Com Etherlink 3C905C-TX NIC.

2. 7-pin AOL/SOS cable.

3. 3Com EtherDisk Driver 5.x or later (available from Compaq).

4. Client-side utility software (included with driver).

5. Server-side utility software (called 3Com Remote System Alert Manager on the compaq.com web site ).

6. Management console running one of the following: a. HP OpenView Network Node Manager 6.x b. Microsoft Systems Management Server (SMS), version 1.2





Chapter 6

POWER and SIGNAL

DISTRIBUTION

6.

Chapter 6 POWER SUPPLY AND DISTRIBUTION


This chapter describes the power supply and method of general power and signal distribution.

Topics covered in this chapter include:

♦ Power supply assembly/control (6.2) page 6-1

♦ Power distribution (6.3) page 6-5

♦ Signal distribution (6.4) page 6-8

6.2 POWER SUPPLY ASSEMBLY/CONTROL

This system features a power supply assembly that is controlled through programmable logic

( Figure 6-1).

Front Bezel System Board

Power On/Off

Power On

CPU, Slots, Chipsets, Logic

& Voltage Regulators

Mains

110/230 VAC

PS

On

Fan

Off

Fan

Spd

+5

AUX

P ower Supply

Assembly

+3.3

AUX

+12.8 VDC

F igure 6–1. Power Distribution and Control, Block Diagram

+5 VDC

-5 VDC

+12 VDC

-12 VDC

+5 VDC

+12 VDC

Drives



6-1


Chapter 6 Power and Signal Distribution

6.2.1 POWER SUPPLY ASSEMBLY

These systems feature auto-ranging power supplies with power factor-correction logic. The SFF systems use a 175-watt supply while the desktop and configurable minitower systems employ a

250-watt supply. Tables 6-1 and 6-2 list the specifications of the power supplies.

Table 6–1. 175-Watt Power Supply Assembly Specifications

Table 6-1.

175-Watt Power Supply Assembly Specifications (PN 243891)

Input Line Voltage:

115 - 230 VAC (auto-ranging)

Line Frequency

Constant Input (AC) Current

+3.33 VDC Output

+5 VDC Output

+3.30 AUX Output

+5.05 AUX Output

+12 VDC Output

+12.8 VDC Output (Vcpu)

-12 VDC Output

Range/

Tolerance

Min. Current

Loading [1]

Max.

Current

Surge

Current [2]

90 - 264 VAC -- -- --

47 - 63 Hz -- -- --

-- -- A

+/- 6 %

+/- 5 %

+/- 5 %

+/- 4 %

0.6 A

0.5 A

1.0 A

0.1 A

12.0 A

8.0 A

1.0 A

2.4 A

--

--

--

--

+/- 3 %

+/- 12 %

+/- 10 %

0.0 A

0.1 A

0.0 A

3.0 A

7.5 A

0.3 A

4.5 A

--

--

N OTES:

[1] Minimum loading requirements must be met at all times to ensure normal operation

and specification compliance.

[2] Surge duration no longer than 10 seconds with 12-volt tolerance +/- 10%.

Table 6–2. 250-Watt Power Supply Assembly Specifications

Max.

Ripple

--

--

50 mV

50 mV

50 mV

50 mV

120 mV

120 mv

200 mV

Table 6-2.

250-Watt Power Supply Assembly Specifications (PN 243890)

Input Line Voltage:

115 - 230 VAC Setting

Line Frequency

Constant Input (AC) Current

+3.3 VDC Output

+5 VDC Output

+3 AUX Output

+5 AUX Output

+12 VDC Output

+12.8 VDC Output (Vcpu)

-12 VDC Output

NOTES:

Range/

Tolerance

90 - 264 VAC

47 - 63 Hz

+/- 5%

+/- 5 %

+/- 5 %

+/- 4 %

+/- 5 %

+/- 5 %

+/- 10 %

[1] Minimum loading requirements

Min. Current

Loading [1]

--

--

1.0 A

1.0 A

0.0 A

0.0 A

0.1 A

0.0 A

0.0 A

Max.

Current

--

--

17.0 A

11.0 A

2.20 A

1.70 A

5.00 A

7.50 A

0.15 A

Surge

Current [2]

--

--

17.0 A

11.0 A

2.20 A

1.70 A

7.50 A

10.5 A

0.15 A

must be met at all times to ensure normal operation

and specification compliance.

[2] Surge duration no longer than 10 seconds with 12-volt tolerance +/- 10%.

Max.

Ripple

--

--

50 mV

50 mV

50 mV

50 mV

120 mV

200 mv

200 mV



Second Edition- January 2003


6.2.2 POWER CONTROL

The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On is asserted, the Power Supply Assembly is activated and all voltage outputs are produced. When

PS On is de-asserted, the Power Supply Assembly is off and all voltages (except +3.3 AUX and

+5 AUX) are not generated. Note that the +3.3 AUX and +5 AUX voltages are always

produced as long as the system is connected to a live AC source.

6.2.2.1 Power Button

The PS On signal is typically controlled through the Power Button which, when pressed and released, applies a negative (grounding) pulse to the power control logic. The resultant action of pressing the power button depends on the state and mode of the system at that time and is described as follows:

System State

Off

On, ACPI Disabled

On, ACPI Enabled

Pressed Power Button Results In:

Negative pulse, of which the falling edge results in power control logic asserting PS

On signal to Power Supply Assembly, which then initializes. ACPI four-second counter is not active.

Negative pulse, of which the falling edge causes power control logic to de-assert the

PS On signal. ACPI four-second counter is not active.

Pressed and Released Under Four Seconds:

Negative pulse, of which the falling edge causes power control logic to

generate SMI-, set a bit in the SMI source register, set a bit for button stat us,

and start four-second counter. Software should clear the button status bit

within four seconds and the Suspend state is entered. If the status bit i s

not cleared by software in four seconds PS On is de-asserted and the

power supply asse mbly shuts down (this operation is meant as a guard if

the OS is hung).

Pressed and Held At least Four Seconds Before Release:

If the button is held in for at least four seco nds and then released, PS On is

negated, de-activating the power supply.



6-3



6.2.2.2 Power LED Indications

A dual-color LED located on the front panel (bezel) is used to indicate system power status. The front panel (bezel) power LED provides a visual indication of key system conditions listed as follows:

Power LED

Steady green

Blinks green @ 1 Hz

Blinks green @ 2 Hz

Blinks green @ 4 Hz

Steady red

Blinks red @ 0.5 Hz

Blinks red @ 1 Hz

Blinks red @ 4 Hz

Condition

Normal full-on operation

Suspend state (S1)

Sleep (suspend to RAM) state (S3)

Sleep (suspend to disk) state (S4)


Power supply crowbar activated

BIOS ROM error

Thermal condition: processor has overheated and shut down

6.2.2.3 Wake Up Events

The PS On signal can be activated with a power “wake-up” of the system due to the occurrence of a magic packet, serial port ring, or PCI power management (PME) event. These events can be individually enabled through the Setup utility to wake up the system from a sleep (low power) state.

NOTE: Wake-up functionality requires that certain circuits receive auxiliary power while the system is turned off. The system unit must be plugged into a live AC outlet for wake up events to function. Using an A C power strip to control system unit power will disable wake-up event functionality.

The wake up sequence for each event occurs as follows:

W ake-On-LAN

The network interface controller (NIC) can be configured for detection of a “Magic Packet” and wake the system up from sleep mode through the assertion of the PME- signal on the PCI bus.

R efer to Chapter 5, “Network Support” for more information.

M odem Ring

A ring condition on serial port A (COM1) or serial port B (COM2) can be d etected by the power c ontrol logic and, if so configured, cause the PS On signal to be asserted.

P ower Management Event

A power management event that asserts the PME- signal on the PCI bus can be enabled to c ause the power control logic to generate t compliant to support this function. he PS On. Note that the PCI card must be PCI ver. 2.2





6.2.3 POWER MANAGEMENT

These systems include power management functions designed to conserve energy. These functions are provided by a combination of hardware, firmware (BIOS) and software. The system provides the following power management features:

J

Intel Pentium III processor with SpeedStep technology

J

J

ACPI v1.0b compliant (ACPI modes C1, C2, S1, and S3, )

API 1.2 compliant

J

U.S. EPA Energy Star compliant

Table 6-1 shows the comparison in power states.

Table 6-1. System Power States

Power

State

G0, S0, D0 System fully on. OS and application is running, all components.

G1, S1, C1, D1 System on, CPU is executing and data is held in memory. Some peripheral subsystems may be on low power. Monitor is blanked.

G1, S2/3, C2,

D2 (Stand by/ suspend)

G1, S4, D3

(Hibernation)

System Condition

Table 6-1.

System Power States

Power

Consumption

Transition

To S 0 by [2]

OS Restart

Required

Maximum N/A No

System on, CPU not executing, cache data lost. Memory is holding data, display and I/O subsystems on low power.

Low

Low

Low

< 2 sec after keyboard or pointing device action

< 5 sec. after keyboard, pointing device, or power button action

<25 sec. after pow er butt on action

No

No

Yes

G2, S5, D3 cold

G3

System off. CPU, memory, and most subsystems shut down.

Memory image save d to disk for recall on power up.

System off. All components either completely shut down or receiving minimum po wer to perform system wake-up.

System off (mechanical). No power to any internal c

RTC circuit. [1] omponents except

Minimum <35 sec. after pow er butt on action

Yes

None — —

NOTES:

Gn = Global state.

Sn = Sleep state.

Cn = ACPI state.

Dn = PCI state.

[1] Power cord is disconnected for this condition.

[2 ] Actual transition time dependent on OS and/or application software.



6-5



6.3.1 3.3/5/12 VDC DISTRIBUTION

The power supply assembly includes a multi-connector cable assembly that routes +3.3 VDC, +5

VDC, -5 VDC, +12 VC, and -12 VDC to the system board as well as to the individual drive assemblies. Figure 6-2 shows the power supply cabling for small form factor series units.

P ower Suppl y

Assembly

(PN 243891)

P4 P3

P2

P5

P1

To

Drive

Assemblies

To

System

Board

4 3 2 1

2

1

P2

4

3

P1

6 10

5

8

7

P3-P4

12

11

14

9 13

1 2 3 4

P5

2 1

4 3

Con n. Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7

FC +12 P1 [1]

P2, 4-7

+3.3

+5

-12

GND

FS

GND

PS On

+12

+5 Aux

NOTES:

Connectors not shown to sca le.

All + and - values are VDC

RTN = Return (signal g

GND = Power ground

RS = Remote sense

. round)

FC = Fan com mand

FO = Fan off

FSpd = Fan spe ed

FS = Fan Sink

[1] This row represents pins 8 - 14 of connector P1.

F igure 6–2. Small Form Factor Power Cable Diagram





Figure 6-3 shows the cabling for the desktop and configurable minitower systems.

Power Supply

Assembly

(PN 243890)

P2

P6

P4

P8

P7

P5

P3

P1

To

Drive

Assemblies

To

System

Board

1 2 3 4

P2, P4-6

13

1

14

2

15

3

16

4

P7, P8

4 3 2 1

17

5

P1

18 19

6 7

2 1

4 3

20

8

P3

21

9

22

10

23

11

24

12

Conn. Pin 1 Pin 2 Pin 3 Pin 4

PS On

Pin 5

RTN

Pin 6

RTN

Pin 7

RTN

Pin 8 Pin 9 Pin 10 Pin 11

P1 +3.3 +3.3 RTN +5 RTN +5 RTN FO Au +12 Au

P1 [1] +3.3 -12 RTN -5 +5 +5 +3.3

Pin 12

FC

FS

NOTES:

Connectors not shown to sca le.

All + and - values are VDC

RTN = Return (signal g

GND = Power ground

RS = Remote sense

. round)

FO = Fan off

FSpd = Fan spe ed

FS = Fan Sink

FC = Fan Command

[1] This row represents pins 13 - 24 of connector P1.

F igure 6–3. Desktop and Configurable Minitower Power Cable Diagram



6-7



6.3.2 LOW VOLTAGE PRODUCTION/DISTRIBUTION

Voltages less than 3.3 VDC including processor core (VccP) voltage are produced through regulator circuitry (Figure 6-4) on the system board.

+5 AUX

+5 VDC

3.3

DIMM

Circuit

3.3 VDC

DIMMs

+3.3 VDC

+12 VDC

AGP

PWR

VDDQ (1.5 VDC)

AGP Bus

Power Supply +3.3 VDC

+3 AUX

DDR

Power

Circuitry

2.5 S3 VDC

+1.8 VDC

+1.4 Ref

DDR

DIMMs

+5 VDC

+12 VDC

+12.8 Vcpu

Processor

VID0

VID1

VID2

VID3

VID4

Regulator

Circuit

VccP (see text)

Processor

F igure 6–4. Low Voltage Supply and Distribution Diagram

The VccP regulator produces the VccP (processor core) voltage according to the strappi ng of si gnals VID4..0 by the processor. The possible voltages available are listed as follows:

VID 4..0

VccP VID

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

2.05 VDC 01011

2.00 VDC 01100

1.95 VDC 01101

1.90 VDC 01110

1.85 VDC 01111

1.80 VDC 10000

1.75 VDC 10001

1.70 VDC 10010

1.65 VDC 10011

1.60 VDC 10100

1.55 VDC 10101

1.50 VDC 10110

1.45 VDC 10111

1.40 VDC 11000

1.35 VDC 11001

1.30 VDC 11010

3.50 VDC 11011

3.40 VDC 11100

3.30 VDC 11101

3.20 VDC 11110

3.10 VDC 111 11

3.00 VDC --

VccP

2.90 VDC

2.80 VDC

2.70 VDC

2.60 VDC

2.50 VDC

2.40 VDC

2.30 VDC

2.20 VDC

2.10 VDC

No CPU

--





Figures 6-5 and 6-6 shows general signal distribution between the main subassemblies of the system units.

Graphics

Controller

Chassis

Fan

Audio

AGP

Bus

Fan

PWR

AGP

Conn. J40

Conn.

P70

System

Board

(PCA #011466

or 011351)

Conn.

P6 Riser

Conn.

J30

Conn.

P124

Conn.

J4002

Conn.

P1

Pri. IDE

Conn. P20

Sec. IDE

Conn. P21

Cover Sensor

PCI Bus

Cover Sensor

Riser

Card

(SPN 252298)

12.8 Vcpu

3/5/12 VDC, 3/5AUX

IDE

IDE I/F

Fan Cntrl., PS On

Data, Cntl

IDE

Hard Drive

CD-ROM

Cover Lock

Power

Solenoid

(Optional)

Supply

Assembly

5, 12 VDC

5, 12 VDC

Audio

Conn. P7

Dsk.

Conn. P10

Mouse

Kybd.

Conn. J68

L/R Audio

Dskt.

Data, Cntl Diskette Drive

Mouse

Keyboard

5, 12 VDC

N OTES:

[1] See Figure 6-7 for header pinout.

F igure 6–5. Small Form Factor Signal Distribution Diagram



6-9



Chassis

Fan

Graphics

Controller

AGP

Bus

Fan

PWR

AGP

Connector

Conn.

P8

System

Board

(PCA #011345 or

011348)

Audio

Conn.

P6

Conn.

P125

Conn.

P124

Conn.

P5 [1]

Conn.

P3

Conn.

P1

Pri. IDE

Conn. P20

Cover Sensor [3]

Pwr Btn, Pwr/HD LED

12.8 Vcpu

3/5/12 VDC, 3/5AUX

IDE

Data, Cntl

Cover Lock

Solenoid

(Optional)

Power On

Fan Cntrl., PS On

IDE

Hard Drive

Sec. IDE

Conn. P21

IDE I/F CD-ROM

Audio

Conn. P7

Dsk.

Conn. P10

L/R Audio

Dskt.

Data, Cntl Diskette Drive

Mouse

Mouse

Kybd.

Conn. J68

Keyboard

Headphones Out

Audio

Conn. P23 Microphone In

PCI Slot Exp.

Edge Connector

USB Conn.

Conn. P24

USB Data 3, USB Data 4

PCI Bus

N OTES:

PCI Slot Exp.

Card

[1] Configurable minitower only.

[1] Header pinout shown in Figure 6-7.

[2] Optional on Evo systems. Standard on W

[3] Sensor switch installed on desktop only. orkstation systems.

F igure 6–6. Desktop/Minitower Signal Distribution Diagram




Power On/Off

Power

Supply

Assembly

5, 12 VDC

5, 12 VDC

5, 12 VDC

A udio/USB

I/O Board

Assembly [2]

HD Activity


Power Button/LED Header P5

HD LED Cathode 1

HD LED Anode 3

GND 5

M Reset 7

+5 VDC 9

NC 11

GND 13

NC 15

Chassis ID1 17

CD ROM Audio Header P7

1 Audio (Left Channel)

2 Ground

3 Ground

4 Audio (right channel)

2 PS LED cathode

4 PS LED anode

6 PWR Btn

8 GND

10 Chassis ID0

12 GND

16 +5 VDC

18 GND

AOL/SOS Header P12

BIOS Fail 1

Not Connected 3

Not Connected 5

Ground 7

2 Not Connected

4 Not Connected

6 Thermal

NOTE:

No polarity consideration required for connection to speaker header P6 or SCSI HD LED heade r P29.

[1] Separate cable connection for these two pins (equivalent of header P29 on other systems).

Figure 6–7. Header Pinouts





This page is intentionally blank.





Chapter 7

BIOS ROM

7.

Chapter 8 BIOS ROM


The Basic Input/Output System (BIOS) of the computer is a collection of machine language programs stored as firmware in read-only memory (ROM). The BIOS ROM includes such functions as Power-On Self Test (POST), PCI device initialization, Plug ‘n Play support, power management activities, and the Setup utility. The firmware contained in the BIOS ROM supports the following operating systems and specifications:

♦ DOS 6.2

♦ Windows 3.1 (and Windows for Workgroups 3.11)

♦ Windows 95, 98SE, 2000, XP Professional, and XP Home

♦ Windows NT 4.0 (SP6 required for PnP support)

♦ OS/2 ver 2.1 and OS/2 Warp

♦ SCO Unix

♦ DMI 2.1

♦ Intel Wired for Management (WfM) ver. 2.2

♦ Alert-On-LAN (AOL) and Wake-On-LAN (WOL)

♦ ACPI and OnNow

♦ APM 1.2

♦ SMBIOS 2.3.1

♦ PC98/99/00 and NetPC

♦ Boot Integrity Services (BIS)

♦ Intel PXE boot ROM for the integrated LAN controller

♦ BIOS Boot Specification 1.01

♦ Enhanced Disk Drive Specification 3.0

♦ “El Torito” Bootable CD-ROM Format Specification 1.0

♦ ATAPI Removeable Media Device BIOS Specification 1.0

The BIOS ROM is a 512KB Intel Firmware Hub (or Firmware Hub-compatible) part. The runtime portion of the BIOS resides in a 128KB block from E0000h to FFFFFh.


♦ ROM flashing (7.2) page 7-2 functions

♦ Setup

♦ Client management functions (7.5)

♦ PnP (7.6)

♦ Power management functions (7.7)

♦ USB legacy support (7.8) page 7-13 page 7-17 page 7-24




7-1

Chapter 7 BIOS ROM

7.2 ROM FLASHING

The system BIOS firmware is contained in a flash ROM device that can be re-written with BIOS code (using the ROMPAQ utility or a remote flash program) allowing easy upgrading, including changing the splash screen displayed during the POST routine.

7.2.1 UPGRADING

Upgrading the BIOS is not normally required but may be necessary if changes are made to the unit’s operating system, hard drive, or processor. All BIOS ROM upgrades are available directly from Compaq. Flashing is done either locally with the CPQFLASH Windows program, a

ROMPaq diskette or remotely using the network boot function (described in the section 7.3.2).

This system includes 64 KB of write-protected boot block ROM that provides a way to recover from a failed flashing of the system BIOS ROM. If the BIOS ROM fails the flash check, the boot block code provides the minimum amount of support necessary to allow booting the system from the diskette drive and re-flashing the system ROM with a ROMPAQ diskette. Note that if an administrator password has been set in the system the boot block will prompt for this password by illuminating the caps lock keyboard LED and displaying a message if video support is available.

A PS/2 keyboard must be used during bootblock operation.

Since video may not be available during the initial boot sequence the boot block routine uses the

Num Lock, Caps Lock, and Scroll Lock LEDs of the PS/2 keyboard to communicate the status of the ROM flash as follows:

Table 7-1. Boot Block Codes

Table 7-1.

Boot Block Codes

Num Lock

LED

Off

On

Cap Lock

LED

On

Off

Scroll Lock

LED

Off

Off

Meaning

Administrator password required.

Boot failed. Reset required for retry.





7.2.2 CHANGEABLE SPLASH SCREEN

NOTE: A corrupted splash screen may be restored by the user with the ROMPAQ software. Depending on system, changing (customizing) the splash screen is a function may only be available though Compaq PC Customization Services.

The splash screen (image displayed during POST) is stored in the BIOS ROM and may be replaced with another image of choice by using the Image Flash utility (Flashi.exe). The Image

Flash utility allows the user to browse directories for image searching and pre-viewing.

Background and foreground colors can be chosen from the selected image’s palette.

The splash screen image requirements are as follows:

♦ Format: Windows bitmap with 4-bit RLE encoding

♦

♦

♦

Size:

Colors:

424 (width) x 320 (height) pixels

16 (4 bits per pixel)

File Size: < 64 KB

The Image Flash utility can be invoked at a command line for quickly flashing a known image as follows:

>\Flashi.exe [Image_Filename] [Background_Color] [Foreground_Color]

The utility checks to insure that the specified image meets the splash screen requirements listed above or it will not be loaded into the ROM.




7-3


The BIOS supports various functions related to the boot process, including those that occur during the Power On Self-Test (POST) routine.

7.3.1 BOOT DEVICE ORDER

The default boot device order is as follows:

1. CD-ROM drive (EL Torito CD images)

2. Diskette drive (A)

3. Hard drive (C)

4. Network boot

The order can be changed in the ROM-based Setup utility (accessed by pressing F10 when so prompted during POST).

7.3.2 NETWORK BOOT (F12) SUPPORT

The BIOS supports booting the system to a network server. The function is accessed by pressing the F12 key when prompted at the lower right hand corner of the display during POST. Booting to a network server allows for such functions as:

♦ Flashing a ROM on a system without a functional operating system (OS).

♦

♦

Installing an OS.

Installing an application.

These systems include, as standard, an integrated Intel 82562-equivalent NIC with Preboot

Execution Environment (PXE) ROM and can boot with a NetPC-compliant server.





7.3.3 MEMORY DETECTION AND CONFIGURATION

This system uses the Serial Presence Detect (SPD) method of determining the installed DIMM configuration. The BIOS communicates with an EEPROM on each DIMM through the SMBus to obtain data on the following DIMM parameters:

♦ Presence

♦ Size

♦ Type

♦ Timing/CAS latency

♦ PC133 capability

NOTE: Refer to Chapter 3, “Processor/Memory Subsystem” for the SPD format and

DIMM data specific to this system.

The BIOS performs memory detection and configuration with the following steps:

1. Program the buffer strength control registers based on SPD data and the DIMM slots that are populated.

2. Determine the common CAS latency that can be supported by the DIMMs.

3. Determine the memory size for each DIMM and program the GMCH accordingly.

4. Enable refresh

5. Determine if the memory configuration will allow for 133MHz memory operation and program the memory clock and MCH (see note below)

NOTE: The presence of PC133-compliant DIMMS will be indicated by BIOS reading

75h from byte 9 and 64h or 85h from byte 126. For PC133 operation to occur the FSB of the processor must be running at 133 MHz and all installed DIMMs must be

PC133-compliant and total no more than four “sides.” Refer to Chapter 3 for more details on PC133 operation.

7.3.4 BOOT ERROR CODES

The BIOS provides visual and audible indications of a failed system boot by using the keyboard

LEDs and the system speaker. The error conditions are listed in the following table.

Table 7-2. Boot Error Codes

Table 7-2. Boot Error Codes

Visual [1]

Num Lock LED blinks

Scroll Lock LED blinks

Caps Lock LED blinks

Audible Meaning

1 short, 2 long beeps System memory not present or incompatible.

2 long, 1 short beeps Hardware failure before graphics initialization.

1 long, 2 short beeps Graphics controller not present or failed to initialize.

1 long, 3 short beeps ROM failure. Num, Caps, Scroll Lock LEDs blink

Num, Caps, Scroll Lock LEDs blink in sequence none Network service mode

NOTE:

[1] Provided with PS/2 keyboard only.




7-5


Storage

The Setup utility (stored in ROM) allows the user to configure system functions involving security, power management, and system resources. The Setup utility is ROM-based and invoked when the F10 key is pressed during the time the F10 prompt is displayed in the lower right-hand corner of the screen during the POST routine. Highlights of the Setup utility are described in the following table.

NOTE: Support for Computer Setup options may vary depending on your specific hardware configuration.

Table 7-3. Setup Utility Functions

Table 7-3.

Setup Utility Functions

Heading Option Description

About

Set Time and Date

Save to Diskette

Restore from Diskette

Set Defaults and Exit

Ignore Changes and Exit

Save Changes and Exit

Device Configuration

Product name

Processor type/speed/stepping

Cache size (L1/L2)

Installed memory size and frequency

System ROM (includes family name and version)

System board revision

Chassis serial number

Asset tracking number

Integrated MAC for embedded, enabled NIC (if applicable)

Displays copyright notice.

Allows you to set system time and date.

Saves system configuration, including CMOS, to a blank, formatted 1.44-MB diskette.

Restores system configuration, including CMOS, from a diskette.

Restores factory default settings, which includes clearing any established passwords.

Exits Computer Setup without applying or saving any changes.

Saves changes to system configuration and exits

Computer Setup.

Lists all installed storage devices. The following options appear when a device is selected:

Diskette Type (For legacy diskette drives only)

Identifies the highest capacity media type accepted by the diskette drive. Options are 3.5" 1.44 MB,

3.5" 720 KB, 5.25" 1.2 MB, 5.25" 360 KB, and Not

Installed.

Drive Emulation (LS-120 and ZIP drives only)

Allows you to select a drive emulation type for a storage device. (For example, a Zip drive can be made bootable by selecting hard disk or diskette emulation.)

Transfer Mode (IDE devices only)

Specifies the active data transfer mode. Options

(subject to device capabilities) are PIO 0, Max PIO,

Enhanced DMA, Ultra DMA 0, and Max UDMA.

Continued





Table 7-3. Setup Utility Functions Continued

Heading Option

Storage

(continued)

Device

Configuration

(continued)

Storage Options

Description

Translation Mode (IDE disks only)

Lets you select the translation mode to be used for the device. This enables the BIOS to access disks partitioned and formatted on other systems and may be necessary for users of older versions of Unix (e.g., SCO Unix version 3.2).

Options are Bit-Shift, LBA Assisted, User, and None.

CAUTION: Ordinarily, the translation mode selected automatically by the BIOS should not be changed. If the selected translation mode is not compatible with the translation mode that was active when the disk was partitioned and formatted, the data on the disk will be inaccessible.

Translation Parameters (IDE Disks only)

Allows you to specify the parameters (logical cylinders, heads, and sectors per track) used by the BIOS to translate disk I/O requests (from the operating system or an application) into terms the hard drive can accept. Logical cylinders may not exceed 1024. The number of heads may not exceed 256. The number of sectors per track may not exceed 63. These fields are only visible and changeable when the drive translation mode is set to User.

Multisector Transfers (IDE ATA devices only)

Specifies how many sectors are transferred per multi-sector

PIO operation. Options (subject to device capabilities) are

Disabled, 8, and 16.

Quiet Drive (available on select drives only)

Performance - Allows the drive to operate at maximum performance.

Quiet (will not be displayed if not supported by drive)-

Reduces noise from the drive during operation. When set to

Quiet, the drive will not operate at maximum performance.

Removable Media Boot

Enables/disables ability to boot the system from removable media.

Note: After saving changes to Removable Media Boot, the computer will restart. Turn the computer off, then on, manually.

Removable Media Write

Enables/disables ability to write data to removable media.

Note: This feature applies only to legacy diskette, IDE LS-120

Superdisk, and IDE PD-CD drives.

Primary IDE Controller

Allows you to enable or disable the primary IDE controller.

Secondary IDE Controller

Allows you to enable or disable the secondary IDE controller.

Diskette MBR Validation

Allows you to enable or disable strict validation of the diskette

Master Boot Record (MBR).

Note: If you use a bootable diskette image that you know to be valid, and it does not boot with Diskette MBR Validation enabled, you may need to disable this option in order to use the diskette.

Continued




7-7


Heading

Storage

(continued)


Security

Option Description

DPS Self-Test

Boot Order

Allows user to execute self-tests on IDE hard drives capable of performing the Drive Protection System

(DPS) self-tests.

Note: This selection will only appear when at least one drive capable of performing the IDE DPS self-tests is attached to the system

Allows user to specify the order in which attached peripheral devices (such as diskette drive, hard drive,

CD-ROM, or network interface card) are checked for a bootable operating system image. Each device on the list may be individually excluded from or included for consideration as a bootable operating system source.

Note: MS-DOS drive lettering assignments may not apply after a non-MS-DOS operating system has started.

To boot one time from a device other than the default device specified in Boot Order, restart the computer and press F9 when the F10=Setup message appears on the screen. When POST is completed, a list of bootable devices is displayed. Use the arrow keys to select a device and press the Enter key.

Setup Password

Power-On Password

Password Options

Allows user to set and enable setup (administrator) password.

Note: If the setup password is set, it is required to change Computer Setup options, flash the ROM, and make changes to certain plug and play settings under

Windows. Also, this password must be set in order to use some Compaq remote security tools.

See the Troubleshooting Guide for more information.

Allows user to set and enable power-on password.

See the Troubleshooting Guide for more information.

Allows user to:

Enable/disable network server mode.

Note: This selection will appear only if a power-on password is set.

Specify whether password is required for warm boot

(CTRL+ALT+DEL).

Note: This selection is available only when Network

Server Mode is disabled.

See the Desktop Management Guide for more information.

Enable/disable the Smart Cover Lock

Enable/disable Smart Cover Sensor.

Notify User alerts the user that the sensor has detected that the cover has been removed. Setup

Password requires that the setup password be entered to boot the computer if the sensor detects that the cover has been removed.

Feature supported on select models only. Refer to the

Desktop Management Guide for more information.

Continued






Heading Option

Security

(continued)

Master Boot Record Security

Save Master Boot Record

Restore Master Boot Record

Description

Allows user to enable or disable Master Boot

Record (MBR) Security. When enabled, the BIOS rejects all requests to write to the MBR on the current bootable disk. Each time the computer is powered on or rebooted, the BIOS compares the

MBR of the current bootable disk to the previouslysaved MBR. If changes are detected, you are given the option of saving the MBR on the current bootable disk, restoring the previously-saved MBR, or disabling MBR Security. You must know the setup password, if one is set.

Note: Disable MBR Security before intentionally changing the formatting or partitioning of the current bootable disk. Several disk utilities (such as

FDISK and FORMAT) attempt to update the MBR.

If MBR Security is enabled and disk accesses are being serviced by the BIOS, write requests to the

MBR are rejected, causing the utilities to report errors. If MBR Security is enabled and disk accesses are being serviced by the operating system, any MBR change will be detected by the

BIOS during the next reboot, and an MBR Security warning message will be displayed.

Saves a backup copy of the Master Boot Record of the current bootable disk.

Note: Only appears if MBR Security is enabled.

Restores the backup Master Boot Record to the current bootable disk.

Note: Only appears if all of the following conditions are true:

MBR Security is enabled

A backup copy of the MBR has been previously saved

The current bootable disk is the same disk from which the backup copy of the MBR was saved.

Network Service Boot

System IDs and audio security.

Enables/disables the computer’s ability to boot from an operating system installed on a network server.

(Feature available on NIC models only; the network controller must reside on the PCI bus or be embedded on the system board.)

Allows user to set:

Asset tag (16-byte identifier) and Ownership Tag

(80-byte identifier displayed during POST) -

Refer to the Desktop Management guide for

more information

Chassis serial number or Universal Unique

Identifier (UUID) number - If current number is

invalid (these ID numbers are normally set in the

factory and are used to uniquely identify the system)

Keyboard locale setting (e.g., English or

German) for System ID entry.

Continued




7-9


Heading

Power


Advanced

(Advanced users only)

Option Description

Energy Saver

Timeouts

Energy Saver Options

Power-On Options

Allows user to set the energy saver mode

(advanced, disable, or minimal).

Note: In the minimal energy saver mode setting, the hard drive and system do not go into energy saver mode, but the setting allows you to press the power button to suspend the system.

This option is not available under ACPI-enabled operating systems.

Allows user to disable or manually select timeout values for the system and/or all attached IDE hard drives.

Note: This option has no effect under ACPI-enabled operating systems. This selection will only appear when energy saver mode is set to advanced.

Allows user to set:

Power button configuration (on/off or sleep/wake) under

APM-enabled operating systems

Power LED blink in suspend mode

(enable/disable). This option is not available under

ACPI-enabled operating systems.

Note: Energy Saver Options will not appear if the energy saver mode is disabled.

Allows user to set:

POST mode (QuickBoot, FullBoot, or FullBoot every 1-30

days)

POST messages (enable/disable)

Safe POST (enable/disable)

F10 prompt (enable/disable)

F12 prompt (enable/disable)

Option ROM prompt (enable/disable)

Remote wakeup boot sequence (remote

server/local hard drive)

After power loss (off/on)

If you connect your computer to an electric power strip, and would like to turn on power to the computer using the switch on the power strip, set this option to on.

Note: If you turn off power to your computer using the switch on a power strip, you will not be able to use the suspend/sleep feature or the

Remote Management features.

UUID (Universal Unique Identifier) (enable/disable)

Onboard Devices

PCI Devices

Allows you to set resources for or disable onboard system devices (diskette controller, serial port, parallel port).

Lists currently installed PCI devices and their IRQ settings.

Allows you to reconfigure IRQ settings for these devices or to disable them entirely.

Continued






Heading Option

Advanced

(continued)

Bus Options

Device Options

PCI VGA Configuration

Description

Allows user to enable or disable:

PCI bus mastering, which allows a PCI device to take control of the PCI bus

PCI VGA palette snooping, which sets the VGA palette snooping bit in PCI configuration space; this is only needed with more than one graphics controller installed

PCI SERR# Generation.

Allows user to set:

Printer mode (bi-directional, EPP & ECP, output only)

Num Lock state at power-on (off/on)

PME (power management event) wakeup events (enable/disable)

Processor cache (enable/disable)

Processor Number (enable/disable) for Pentium

III processors.

ACPI S3 support (enable/disable). S3 is an

ACPI (advanced configuration and power interface) sleep state that some add-in hardware options may not support.

AGP Aperture size (options vary depending on platform) allows you to modify the size of your AGP aperture size window.

Appears only if there are multiple PCI video adapters in the system. Allows users to specify which VGA controller will be the “boot” or primary

VGA controller.



7-11



7.5 CLIENT MANAGEMENT FUNCTIONS

Table 7-4 lists the client management BIOS functions supported by the systems covered in this guide. These functions, designed to support intelligent manageability applications, are Compaqspecific unless otherwise indicated.

Table 7-4. Client Management Functions (INT15)

Table 7-4.

Client Management Functions (INT15)

AX Function

E800h

E813h

E814h

E816h

E817h

E818h

Get system ID

Get monitor data

Get system revision

Get temperature status

Get drive attribute

Get drive off-line test

E819h Get chassis serial number

E820h [1] Get system memory map

E81Ah

E81Bh

Write chassis serial number

Get hard drive threshold

E81Eh

E827h

Get hard drive ID

DIMM EEPROM Access

NOTE:

[1] Industry standard function.

Mode

Real, 16-, & 32-bit Prot.




Real

Real


Real

Real

Real

Real


All 32-bit protected-mode functions are accessed by using the industry-standard BIOS32 Service

Directory. Using the service directory involves three steps:

1. Locating the service directory.

2. Using the service directory to obtain the entry point for the client management functions.

3. Calling the client management service to perform the desired function.

The BIOS32 Service Directory is a 16-byte block that begins on a 16-byte boundary between the physical address range of 0E0000h-0FFFFFh. The format is as follows:

Offset No.

00h 4

04h 4

08h 1

09h 1

0Ah 1

0Bh 5

Service identifier (four ASCII characters)

Entry point for the BIOS32 Service Directory

Revision level

Length of data structure (no. of 16-byte units)

Checksum (should add up to 00h)

Reserved (all 0s)





To support Windows NT an additional table to the BIOS32 table has been defined to contain 32bit pointers for the DDC locations. The Windows NT extension table is as follows:

; Extension to BIOS SERVICE directory table (next paragraph) db db

2

“$DDC”

; number of entries in table

; DDC POST buffer sig

? ;

dw

? ;

The service identifier for client management functions is “$CLM.” Once the service identifier is found and the checksum verified, a FAR call is invoked using the value specified at offset 04h to retrieve the CM services entry point. The following entry conditions are used for calling the

Desktop Management service directory:

INPUT:

EAX

EBX (31..8)

EBX (7..0)

CS

DS

= Service Identifier [$CLM]

= Reserved

= Must be set to 00h

= Code selector set to encompass the physical page holding

entry point as well as the immediately following physical page.

It must have the same base. CS is execute/read.

= Data selector set to encompass the physical page holding

entry point as well as the immediately following physical page.

OUTPUT:

SS

It must have the same base. DS is read only.

= Stack selector must provide at least 1K of stack space and be 32-bit.

(I/O permissions must be provided so that the BIOS can support as necessary)

EBX

ECX

EDX

00h, requested service is present

80h, requested service is not present

81h, un-implemented function specified in BL

86h and CF=1, function not supported

= Physical address to use as the selector BASE for the service

= Value to use as the selector LIMIT for the service

= Entry point for the service relative to the BASE returned in EBX

The following subsections provide a brief description of key Client Management functions.



7-13



7.5.1 SYSTEM ID AND ROM TYPE

Applications can use the INT 15, AX=E800h BIOS function to identify the type of system. This function will return the system ID in the BX register. These systems have the following IDs and

ROM family types:

System System ID ROM Family PnP ID

Small Form Factor

SDR SDRAM

DDR SDRAM

Desktop

SDR SDRAM

DDR SDRAM


SDR SDRAM

DDR SDRAM

788h

78Ch

77Ch

784h

77Ch

784h

686Y2

686Y2

686Y2

686Y2

686Y2

686Y2

CPQ0042

CPQ0042

CPQ003E

CPQ0040

CPQ003F

CPQ0041

The ROM family and version numbers can be verified with the Setup utility or the Compaq

Insight Manager or Diagnostics applications.

7.5.2 EDID RETRIEVE

The BIOS function INT 15, AX=E813h is a tri-modal call that retrieves the VESA extended display identification data (EDID). Two subfunctions are provided: AX=E813h BH=00h retrieves the EDID information while AX=E813h BX=01h determines the level of DDC support.

Input:

BH

BH

= 00 Get EDID .

= 01 Get DDC support level

If BH = 00 then

DS:(E)SI = Pointer to a buffer (128 bytes) where ROM will return block

If 32-bit protected mode then

DS:(E)SI = Pointer to $DDC location

Output:

(Successful)

If BH = 0:

DS:SI=Buffer with EDID file.

CX = Number of bytes written

CF =

AH =00h Completion of command

If BH

BH

BL

= 1:

= System DDC support

<0>=1 DDC1 support

<1>=1 DDC2 support

= Monitor DDC support

<0>=1 DDC1 support

<1>=1 DDC2 support

<2>=1 Screen blanked during transfer

(Failure)

AH = 86h or 87h





7.5.3 TEMPERATURE STATUS

The BIOS includes a function (INT15, AX=E816h) to retrieve the status of a system’s interior temperature. This function allows an application to check whether the temperature situation is at a

Normal, Caution, or Critical condition.

7.5.4 DRIVE FAULT PREDICTION

The Compaq BIOS directly supports Drive Fault Prediction for IDE-type hard drives. This feature is provided through two Client Management BIOS calls. Function INT 15, AX=E817h is used to retrieve a 512-byte block of drive attribute data while the INT 15, AX=E81Bh is used to retrieve the drive’s warranty threshold data. If data is returned indicating possible failure then the following message is displayed:

“1720-SMART Hard Drive detects imminent failure”

The BIOS includes Plug ’n Play (PnP) support for PnP version 1.0A. Table 7-5 lists the PnP functions supported.

Table 7-5. PnP BIOS Functions

Function Register

Table 7-5.

PnP BIOS Functions

00h

01h

02h

Get number of system device nodes

Get system device node

Set system device node

50h

51h

Get SMBIOS Structure Information

Get Specific SMBIOS Structure

The BIOS call INT 15, AX=E841h, BH=01h can be used by an application to retrieve the default settings of PnP devices for the user. The application should use the following steps for the display function:

1. Call PnP function 01(get System Device Node) for each devnode with bit 1 of the control flag set (get static configuration) and save the results.

2. Call INT 15, AX=E841h, BH=01h.

3. Call PnP “Get Static Configuration” for each devnode and display the defaults.

4. If the user chooses to save the configuration, no further action is required. The system board devices will be configured at the next boot. If the user wants to abandon the changes, then the application must call PnP function 02 (Set System Device Node) for each devnode (with bit 1 of the control flag set for static configuration) with the results from the calls made prior to invoking this function.



7-15



7.6.1 SMBIOS

In support of the DMI specification the PnP functions 50h and 51h are used to retrieve the

SMBIOS data. Function 50h retrieves the number of structures, size of the largest structure, and

SMBIOS version. Function 51h retrieves a specific structure. This system supports SMBIOS version 2.3.1 and the following structure types:

Type Data

0 BIOS Information

1 System Information

3 System Enclosure or Chassis

4 Processor Information

7 Cache Information

8 Port Connector Information

9 System Slots

13 BIOS Language Information

15 System Event Log Information

16 Physical Memory Array

17 Memory Devices

19 Memory Array Mapped Addresses

20 Memory Device Mapped Addresses

31 Boot Integrity Service Entry Point

32 System Boot Information

128 OEM Defined Structure with Intel Alert-On-LAN (AOL) Information

NOTE: System information on these systems is handled exclusively through the

SMBIOS. The System Information Table (SIT) method (and it’s associated BIOS functions) used on previous systems is no longer supported.





7.7 POWER MANAGEMENT FUNCTIONS

The BIOS ROM provides three types of power management support: independent PM support;

APM support, and ACPI support.

7.7.1 INDEPENDENT PM SUPPORT

The BIOS can provide power management (PM) of the system independently from an operating system that doesn’t support APM (including DOS, Unix, NT & older versions of OS/2). In the

Independent PM environment the BIOS and hardware timers determine when to switch the system to a different power state. State switching is not reported to the OS.

7.7.1.1 Staying Awake In Independent PM

There are two "Time-out to Standy" timers used in independent PM: the System Timer and the IDE Hard Drive Timer.

System Timer

In POST, the BIOS enables a timer in the ICH that generates an SMI once per minute. When the

BIOS detects the SMI it checks status bits in the ICH for device activity. If any of the device activity status bits are set at the time of the 1-minute SMI, BIOS resets the time-out minute countdown. The system timer can be configured through the Setup utility for counting down 0, 5,

10, 15, 20, 30, 40, 50, 60, 120, 180, or 240 minutes. The following devices are checked for activity:

♦ Keyboard

♦ Mouse

♦ Serial port(s)

♦ Parallel port

♦ IDE primary controller

NOTE: The secondary controller is NOT included. This is done to support autosense of a CD-ROM insertion (auto-run) in case Windows or NT is running.

Note also that SCSI drive management is the responsibility of the SCSI driver.

Any IDE hard drive access resets the hard drive timer.

IDE Hard Drive Timer

During POST, an inactivity timer each IDE hard drive is set to control hard drive spin down.

Although this activity is independent of the system timer, the system will not go to sleep until the primary IDE controller has been inactive for the system time-out time. The hard drive timer can be configured through the Setup utility for being disabled or counting down 10, 15, 20, 30, 60,

120, 180, or 240 minutes, after which time the hard drive will spin down.



7-17



7.7.1.2 Going to Sleep in Independent PM

When a time-out timer expires, Standby for that timer occurs.

System Standby

When the system acquires the Standby mode the BIOS blanks the screen. Since the hard drive inactivity timer is in the drive and triggered by drive access, the system can be in

Standby with the hard drives still spinning (awake).

NOTE: The BIOS does not turn the fan(s) off (as on previous products).

IDE Hard Drive Standby

During hard drive standby the platters stop spinning. Depending on drive type, some hard drives will also cut power to some of the drive electronics that are not needed. The drives can be in this state with the system still awake.

7.7.1.3 Suspend

Suspend is not supported in the Independent PM mode.

7.7.1.4 System OFF

When the system is turned Off but still plugged into a live AC outlet the NIC, ICH2, and I/O components continue to receive auxiliary power in order to power-up as the result of a Magic

Packet™ being received over a network. Some NICs are able to wake up a system from Standby in PM, most require their Windows/NT driver to reset them after one wake-up.

7.7.1.5 Waking Up in Independent PM

Activity of either of the following devices will cause the system to wake up with the screen restored:

♦ Keyboard

♦ Mouse (if driver installed)

The hard drive will not spin up until it is accessed. Any hard drive access will cause it to wake up and resume spinning. Since the BIOS returns to the currently running software, it is possible for the drive to spin up while the system is in Standby with the screen blanked.





7.7.2 ACPI SUPPORT

This system meets the hardware and firmware requirements for being ACPI compliant.

This system supports the following ACPI functions:

♦ PM timer

♦ Power button

♦ Power button override

♦ RTC alarm

♦ Sleep/Wake logic (S1,S3, S4 (Windows 2000), S5)

♦ C1 state (Halt)

♦ PCI Power Management Event (PME)

7.7.3 APM 1.2 SUPPORT

Advanced Power Management (APM) is an extension of power management. In APM, the O/S decides when a transition to another power state should occur. If going to Standby or Suspend, it notifies all APM-aware drivers requesting approval for the state change. If all drivers approve (the

BIOS is not involved in this process) each is instructed to go to that state, then the BIOS is told to go to that state. All versions of Windows, later versions of OS/2 and Linux support APM. . The

BIOS ROM for these systems support APM 1.2

The APM functions are initialized when the O/S loads. An INT 15h call is made to see if APM is supported by the BIOS, and at what level (1.0, 1.1 or 1.2). After that, the O/S gets a 32-bit address from the BIOS ROM so it can subsequently make 32 bit protected mode calls to access the different APM functions in the ROM.

Table 8-6 lists all the APM calls that the O/S can make to the BIOS. These functions are the major difference between PM and APM.



7-19



Table 7-6. APM BIOS Functions

APM BIOS Function

APM Installation Check

APM Real Mode Interface

Connect

APM Protected Mode 16-bit

APM Protected Mode 32-bit

APM Interface Disconnect

CPU Idle

CPU Busy

Set Power State

Enable/Disable Power

Management

Restore Power-On Defaults

Get Power Status

Get PM Event

Table 7-6.

APM BIOS Functions

Description

Allows the O/S to determine if the system's BIOS supports the APM functionality and if so, which version of the specification it supports. The APM version number returned from this call is the highest level of APM supported by the BIOS.

Establishes the cooperative interface between the O/S and the

BIOS. The BIOS provides OEM-defined power management functionality before the interface is established. Once the interface is established, the BIOS and the O/S Driver coordinate power management activities. The BIOS rejects an interface connect request if any real or protected mode connection already exists.

Initializes the 16-bit protected mode interface between the O/S and the BIOS. This interface allows a protected mode caller to invoke the BIOS functions without first switching into real or virtual-86 mode. This function must be invoked in real mode. This is not currently used by any O/S.

Iinitializes the 32-bit protected mode interface between the O/S and the BIOS. This interface allows a protected mode O/S to invoke the

BIOS functions without the need to first switch into real or virtual-86 mode. This function must be invoked in real mode.

Breaks the cooperative connection between the BIOS and the O/S, and returns control of the power management policy to the BIOS.

Power management parameter values (timer values, enable/disable settings, etc.) in effect at the time of the disconnect remain in effect.

The O/S uses this call to tell BIOS that the system is idle.

Informs the BIOS that the O/S has determined that the system is now busy. The BIOS should restore the CPU clock rate to full speed.

Sets the system or device specified in the power device ID into the requested power state.

Enables or disables all APM BIOS automatic power management.

When disabled, the BIOS does not automatically power manage devices, enter the Standby State, enter the Suspend State, or take power saving steps in response to CPU Idle calls.

Re-initializes all power-on defaults.

This call returns the system current power status.

Returns the next pending PM event, or indicates if no PM events are pending.

Get Power State

Enable/Disable Device PM

APM Driver Version

Engage/Disengage PM

Get Capabilities

Returns the device power state when a specific device ID is used.

Enables or disables APM BIOS automatic power management for a specified device. When disabled, the APM BIOS does not automatically power manage the device.

The O/S uses this call to indicate its level of APM support to the

BIOS. The BIOS returns the APM connection version number.

Engages or disengages cooperative power management of the system or device.

Returns the features which this particular APM 1.2 BIOS implementation supports.

This call gets, sets, or disables the system resume timer. Get/Set/Disable Resume

Timer

Enable/Disable Resume on

Ring

Enable/Disable Timer Based

Request

Enables or disables the system's resume on ring indicator functionality. It also returns the enabled/disabled status.

Enables or disables the BIOS's generation of global Standby and global Suspend requests based on inactivity timers.





7.7.3.1 Staying Awake in APM

There are two "Time-out to Standby" timers used in APM: the System Timer and the IDE had Drive Timer.

System Timer

In POST, the ROM enables a timer in the ICH2 that generates an SMI once per minute.

When the ROM gets the SMI it checks status bits in the ICH2 for activity at any of the following devices:

♦ Keyboard

♦ Mouse

♦ Serial port(s)

♦ Parallel port

♦ IDE primary controller

NOTE: The secondary controller is NOT included in order to support autosense of a CD-ROM insertion (auto-run) in case Windows or NT is running.

Note also that management of SCSI drives is the responsibility of the SCSI driver. Any IDE hard drive access resets the hard drive timer.

If any of the activity status bits are set when the ROM gets the 1-minute SMI, it resets its time-out minute countdown according to the value (0 (default), 5, 10, 15, 20, 30, 40, 50,

60, 120, 180, or 240 minutes) selected in the Setup utility (F10).

IDE Hard Drive Timer

During POST, an inactivity timer in the IDE hard drive controller is set to control hard drive spin down. This activity is independent of the system timer. The BIOS will not inform the O/S that it is time to go to sleep until there has been no IDE primary activity for the system time-out time. The IDE hard drive will spin down when its timer expires according to the countdown time (0 (disabled), 10, 15, 20, 30, 60, 120, 180, or 240 minutes) selected in the Setup utility (F10).

NOTE: The O/S (Win98 and later) can use the "Enable/Disable Timer Based Request"

APM BIOS call to disable the system timer the BIOS uses so that the O/S can have direct control of the timing.



7-21



7.7.3.2 Going to Sleep in APM

There are three levels of system sleep in APM: System/Hard Drive Standby, System

Suspend, and System Off.

System/Hard Drive Standby

System Standby is achieved only by a system timer time-out, at such time the following occurs:

1. All APM-aware device drivers put their respective devices into “Device Standby.”

2. The O/S makes a BIOS call to go into System Standby.

NOTE: The BIOS ROM of these systems will not turn the fan(s) off as on previous systems).

If the hard drive timer times out due to inactivity the hard drive motor stops spinning the platters. Depending on drive type, some drives can cut power to some of the drive electronics that are not needed during standby. The drive(s) can be in this state with the system still awake. Since the hard drive timer is in the hard drive controller and triggered by drive access, the system can be in Standby with the hard drive(s) still spinning

(awake).

System Suspend

System Suspend is invoked by pressing and releasing the power switch in under four seconds (pressing and holding the switch longer that four seconds will turn the system off).. The system does not time-out from Standby into Suspend.

Upon invoking Suspend, the following actions occur:

1. All APM-aware device drivers put their associated devices into “Device Standby.”

2. The O/S makes a BIOS call to go into Standby, and the BIOS: a. Spins down the IDE drives b. Halts the processor. The processor remains halted until the next 55ms tick from the RTC. c. At the 55ms tick of the RTC the processor executes a BIOS routine to check to see if anything has happened to wake the system up. If not, the processor is halted again. d. Steps B and C are repeated until a wake-up event occurs.

NOTE: These systems will not turn the fan(s) off as in previous systems.





System OFF

There are two ways to turn the system off:

1. Software shut-down as directed by the O/S. This, being the normal procedure, allows a NIC driver to re-arm the NIC for a Magic Packet™

2. Press and hold the power button for longer than 4 seconds (not recommended unless necessary).

7.7.3.3 Waking Up in APM

Any of the following activities will cause the system to wake up:

♦ Keyboard

♦ Mouse

♦ Ring Indicate

♦ RTC alarm

♦ Magic Packet

The hard drive will not spin up until it is accessed. Any hard drive access will cause it to wake up and resume spinning. Since the BIOS returns to the currently running software, it is possible for the drive to spin up while the system is in Standby with the screen blanked.

7.8 USB LEGACY SUPPORT

The BIOS ROM checks the USB port, during POST, for the presence of a USB keyboard. This allows a system with only a USB keyboard to be used during ROM-based setup and also on a system with an OS that does not include a USB driver.

On such a system a keystroke will generate an SMI and the SMI handler will retrieve the data from the device and convert it to PS/2 data. The data will be passed to the keyboard controller and processed as in the PS/2 interface. Changing the delay and/or typematic rate of a USB keyboard though BIOS function INT 16 is not supported.



7-23








Appendix A

ERROR MESSAGES AND CODES

A. Appendix A ERROR MESSAGES AND CODES

A.1 INTRODUCTION

This appendix lists the error codes and a brief description of the probable cause of the error.

NOTE: Errors listed in this appendix are applicable only for systems running Compaq

BIOS.

NOTE: Not all errors listed in this appendix may be applicable to a particular system model and/or configuration.

A.2 BEEP/KEYBOARD LED CODES

Table A–1. Beep/Keyboard LED Codes

Beeps

1 short, 2 long

1 long, 2 short

2 long, 1 short

1 long, 3 short

None

None

None

None

None

NOTE:

Table A-1.

Beep/Keyboard LED Codes

LED [1]

NUM lock blinking

CAP lock blinking

Scroll lock blinking

(None)

All three blink in sequence

NUM lock steady on

CAP lock steady on

All three blink together

All three steady on

Probable Cause

Base memory failure.

Video/graphics controller failure.

System failure (prior to video initialization).

Boot block executing

Keyboard locked in network mode.

ROMPAQ diskette not present, bad, or drive not ready.

Password prompt.

ROM flash failed.

Successful ROM flash.

[1] PS/2 keyboard only.

Compaq Personal Computers

Changed – November 2000

A-1

Appendix A Error Messages and Codes

A.3 POWER-ON SELF TEST (POST) MESSAGES

Table A–2. Power-On Self Test (POST) Messages

Error Message

Table A-2.

Power-On Self Test (POST) Messages

Probable Cause

Invalid Electronic Serial Number

Network Server Mode Active (w/o kybd)

101-Option ROM Checksum Error

102-system Board Failure

150-Safe POST Active

162-System Options Not Set

163-Time & Date Not Set

164-Memory Size Error

201-Memory Error

213-Incompatible Memory Module

216-Memory Size Exceeds Max

301-Keyboard Error

303-Keyboard Controller Error

304-Keyboard/System Unit Error

404-Parallel Port Address Conflict

510-Slpash Image Corrupt

601-Diskette Controller Error

912-Computer Cover Removed Since

Last System Start Up

917-Expansion Riser Not Detected

1720-SMART Hard Drive Detects

Imminent Failure

1721-SMART SCSI Hard Drive

Detects Imminent Failure

1801-Microcode Patch Error

1998-Master Boot Record Backup

Has Been Lost

1999-Master Boot Record Has

Changed. Press Any Key To Enter

Setup to Restore the MBR.

2000-Master boot Record hard drive has changed

Chassis serial number is corrupt. Use Setup to enter a valid number.

System is in network mode.

A device’s option ROM has failed/is bad.

Failed ESCD write, A20, timer, or DMA controller.

An option ROM failed to execute on a previous boot.

Invalid checksum, RTC lost power, or invalid configuration.

Date and time information in CMOS is not valid.

Memory has been added or removed.

Memory test failed.

BIOS detected installed DIMM(s) as being not compatible.

Installed memory exceeds the maximum supported by the system.

Keyboard interface test failed (improper connection or stuck key).

Keyboard buffer failed empty (8042 failure or stuck key).

Keyboard controller failed self-test.

Current parallel port address is conflicting with another device.

Corrupted splash screen image. Restore default image w/ROMPAQ.

Diskette drive removed since previous boot.

Cover (hood) removal has been detected by the Smart Cover Sensor.

Expansion (backplane) board not seated properly.

SMART circuitry on an IDE drive has detected possible equipment failure.

SMART circuitry on a SCSI drive has detected possible equipment failure.

A processor is installed for which the BIOS ROM has no patch.

Check for ROM update.

Backup copy of the hard drive master boot record is corrupted. Use

Setup to restore the backup from the hard drive.

If Master Boot Record Security is enabled, this message indicates that the MBR has changed since the backup was made.

The hard drive has been changed. Use Setup to create a backup of the new hard drive.

A-2 Compaq Personal Computers

Changed - November 2000


Table A–3. System Error Messages

Table A-3.

System Error Messages

Message Probable Cause

101

102

103

104-01

104-02

104-03

105-01

105-02

105-03

105-04

105-05

105-06

105-07

105-08

105-09

105-10

105-11

105-12

105-13

105-14

Option ROM error

System board failure (see note)

System board failure

Master int. cntlr. test fialed

Slave int. cntlr. test failed

Int. cntlr. SW RTC inoperative

Port 61 bit <6> not at zero





Port 61 bit <5> not at one




Port 61 I/O test failed



No int. generated by failsafe timer

NMI not triggered by failsafe timer

110-01

110-02

110-03

111-01

112-01

112-02

112-03

112-04

112-05

112-06

112-07

112-08

112-09

112-10

112-11

112-12

113-01

114-01

116-xx

162-xx

106-01

107-01

108-02

Keyboard controller test failed

CMOS RAM test failed

CMOS interrupt test failed

163-xx

164-xx

199-00

Programmable timer load data test failed

Programmable timer dynamic test failed

Program timer 2 load data test failed

Refresh detect test failed

Speed test Slow mode out of range

Speed test Mixed mode out of range

Speed test Fast mode out of range

Speed test unable to enter Slow mode

Speed test unable to enter Mixed mode

Speed test unable to enter Fast mode

Speed test system error

Unable to enter Auto mode in speed test

Unable to enter High mode in speed test

Speed test High mode out of range

Speed test Auto mode out of range

Speed test variable speed mode inop.

Protected mode test failed

Speaker test failed

Way 0 read/write test failed

Sys. options failed (mismatch in drive type)

Time and date not set

Memory size

Installed devices test failed

108-03

109-01

109-02

109-03

CMOS not properly initialized (int.test)

CMOS clock load data test failed

CMOS clock rollover test failed

CMOS not properly initialized (clk test)

NOTE: A 102 message code may be caused by one of a variety of processor-related problems that may be solved by replacing the processor, although system board replacement may be needed.



A-3


A.5 MEMORY ERROR MESSAGES (2xx-xx)

Table A–4. Memory Error Messages

Table A-4.

Memory Error Messages

200-04

200-05

200-06

200-07

200-08

201-01

202-01

202-02

202-03

203-01

203-02

203-03

204-01

204-02

204-03

204-04

204-05

205-01

205-02

205-03

206-xx

210-01

210-02

210-03

211-01

211-02

211-03

213-xx

214-xx

215-xx

Real memory size changed

Extended memory size changed

Invalid memory configuration

Extended memory size changed

CLIM memory size changed

Memory machine ID test failed

Memory system ROM checksum failed

Failed RAM/ROM map test

Failed RAM/ROM protect test

Memory read/write test failed

Error while saving block in read/write test

Error while restoring block in read/write test

Memory address test failed

Error while saving block in address test

Error while restoring block in address test

A20 address test failed

Page hit address test failed

Walking I/O test failed

Error while saving block in walking I/O test

Error while restoring block in walking I/O test

Increment pattern test failed

Memory increment pattern test

Error while saving memory during increment pattern test

Error while restoring memory during increment pattern test

Memory random pattern test

Error while saving memory during random memory pattern test

Error while restoring memory during random memory pattern test

Incompatible DIMM in slot x

Noise test failed

Random address test

Table A–5. Keyboard Error Messages


Table A-5.

Keyboard Error Messages

300-xx

301-01

301-02

301-03

301-04

301-05

302-01

303-01

303-02

303-03

303-04

Failed ID test 303-05

Kybd short test, 8042 self-test failed 303-06

Kybd short test, interface test failed 303-07

Kybd short test, echo test failed

Kybd short test, kybd reset failed

Kybd short test, kybd reset failed

303-08

303-09

304-01

Kybd long test failed

LED test, 8042 self-test failed

304-02

304-03

304-04

LED test, reset test failed

LED test, reset failed

304-05

304-06

LED test, LED command test failed --

LED test, LED command test failed



LED test, command byte restore test failed

LED test, LEDs failed to light

Keyboard repeat key test failed

Unable to enter mode 3

Incorrect scan code from keyboard

No Make code observed

Cannot /disable repeat key feature

Unable to return to Normal mode

--




A.7 PRINTER ERROR MESSAGES (4xx-xx)

Table A–6. Printer Error Messages


Table A-6.

Printer Error Messages

401-01

402-01

402-02

402-03

402-04

Printer failed or not connected

Printer data register failed

Printer control register failed

Data and control registers failed

Loopback test failed

402-11

402-12

402-13

402-14

402-15

402-05

402-06

402-07

402-08

402-09

402-10

Loopback test and data reg. failed 402-16

Loopback test and cntrl. reg. failed 402-01

Loopback tst, data/cntrl. reg. failed 403-xx

Interrupt test failed 404-xx

Interrupt test and data reg. failed 498-00

Interrupt test and control reg. failed --

Interrupt test, data/cntrl. reg. failed

Interrupt test and loopback test failed

Int. test, LpBk. test., and data register failed

Int. test, LpBk. test., and cntrl. register failed

Int. test, LpBk. test., and data/cntrl. reg. failed

Unexpected interrupt received

Printer pattern test failed

Printer pattern test failed

Parallel port address conflict

Printer failed or not connected

--

Table A–7. Video (Graphics) Error Messages

Table A-7.

Video (Graphics) Error Messages


501-01

502-01

503-01

504-01

505-01

Video controller test failed

Video memory test failed

Video attribute test failed

Video character set test failed

80x25 mode, 9x14 cell test failed

508-01

509-01

510-01

511-01

512-01

506-01

507-01


40x25 mode test failed

See Table A-14 for additional graphics messages.

514-01

516-01

320x200 mode, color set 0 test failed

320x200 mode, color set 1 test failed


Screen memory page test failed

Gray scale test failed

White screen test failed

Noise pattern test failed



A-5


A.9 DISKETTE DRIVE ERROR MESSAGES (6xx-xx)

Table A–8. Diskette Drive Error Messages

Table A-8.

Diskette Drive Error Messages


6xx-01

6xx-02

6xx-03

6xx-04

6xx-05

6xx-06

6xx-07

6xx-08

6xx-09

6xx-10

Exceeded maximum soft error limit

Exceeded maximum hard error limit

Previously exceeded max soft limit

Previously exceeded max hard limit

Failed to reset controller

Fatal error while reading

Fatal error while writing

Failed compare of R/W buffers

Failed to format a tract

Failed sector wrap test

6xx-20

6xx-21

6xx-22

6xx-23

6xx-24

6xx-25

6xx-26

6xx-27

6xx-28

--

Failed to get drive type

Failed to get change line status

Failed to clear change line status

Failed to set drive type in ID media

Failed to read diskette media

Failed to verify diskette media

Failed to read media in speed test

Failed speed limits

Failed write-protect test

--

600-xx = Diskette drive ID test

601-xx = Diskette drive format

602-xx = Diskette read test

603-xx = Diskette drive R/W compare test

604-xx = Diskette drive random seek test

605-xx = Diskette drive ID media

606-xx = Diskette drive speed test

607-xx = Diskette drive wrap test

608-xx = Diskette drive write-protect test

609-xx = Diskette drive reset controller test

610-xx = Diskette drive change line test

611-xx = Pri. diskette drive port addr. conflict

612-xx = Sec. diskette drive port addr. conflict

694-00 = Pin 34 not cut on 360-KB drive

697-00 = Diskette type error

698-00 = Drive speed not within limits

699-00 = Drive/media ID error (run Setup)

A.10 SERIAL INTERFACE ERROR MESSAGES (11xx-xx)

Table A–9. Serial Interface Error Messages

Table A-9.

Serial Interface Error Messages


1101-01

1101-02

1101-03

1101-04

1101-05

1101-06

1101-07

1101-08

1101-09

1101-10

1101-11

1101-12

UART DLAB bit failure

Line input or UART fault

Address line fault

Data line fault

UART cntrl. signal failure

UART THRE bit failure

UART Data RDY bit failure

UART TX/RX buffer failure

Interrupt circuit failure

COM1 set to invalid INT

COM2 set to invalid INT

DRVR/RCVR cntrl. signal failure

1101-13

1101-14

1109-01

1109-02

1109-03

1109-04

1109-05

1109-06

1150-xx

1151-xx

1152-xx

1155-xx

UART cntrl. signal interrupt failure

DRVR/RCVR data failure

Clock register initialization failure

Clock register rollover failure

Clock reset failure

Input line or clock failure

Address line fault

Data line fault

Comm port setup error (run Setup)

COM1 address conflict

COM2 address conflict

COM port address conflict




Table A–10. Serial Interface Error Messages

Table A-10.

Serial Interface Error Messages


1201-XX Modem internal loopback test

1201-01 UART DLAB bit failure

1201-02

1201-03

1201-04

Line input or UART failure

Address line failure

Data line fault

1201-05

1201-06

1201-07

1201-08

UART control signal failure

UART THRE bit failure

UART DATA READY bit failure

UART TX/RX buffer failure

1204-03

1204-04

1204-05

1204-06

1204-07

1204-08

1204-09

1204-10

1204-11

1201-09

1201-10

1201-11

1201-12

1201-13

1201-14

1201-15

Interrupt circuit failure

COM1 set to invalid inturrupt

COM2 set to invalid

DRVR/RCVR control signal failure

UART control signal interrupt failure

DRVR/RCVR data failure

Modem detection failure

1201-16

1201-17

Modem ROM, checksum failure

Tone detect failure

1202-XX Modem internal test

1202-01

1202-02

Time-out waiting for SYNC [1]

Time-out waiting for response [1]

1205-XX

1205-01

1205-02

1205-03

1205-04

1205-05

1205-06

1205-07

1205-08

1205-09

1205-10

1205-11

Data block retry limit reached [4]

RX exceeded carrier lost limit

TX exceeded carrier lost limit

Time-out waiting for dial tone

Dial number string too long

Modem time-out waiting for remote response

Modem exceeded maximum redial limit

Line quality prevented remote response

Modem time-out waiting for remote connection

Modem auto answer test





1202-03

1202-11

1202-12

1202-13

1202-21

1202-22

1202-23








1206-XX

1206-17

1210-XX

1210-01

1210-02

1210-03

1210-04

1203-XX Modem external termination test

1203-01 Modem external TIP/RING failure

1203-02

1210-05

1210-06

Modem external data TIP/RING fail 1210-07

1203-03 Modem line termination failure

1204-XX Modem auto originate test

1204-01

1204-02



1210-08

1210-09

1210-10

1210-11








Dial multi-frequency tone test

Tone detection failure

Modem direct connect test












NOTES:

[1] Local loopback mode

[2] Analog loopback originate mode

[3] Analog loopback answer mode

[4] Modem auto originate test

[5] Modem auto answer test

[6] Modem direct connect test



A-7


A.12 SYSTEM STATUS ERROR MESSAGES (16xx-xx)

Table A–11. System Status Error Messages

Table A-11.

System Status Error Messages

A.13 HARD DRIVE ERROR MESSAGES (17xx-xx)

Table A–12. Hard Drive Error Messages

Table A-12.

Hard Drive Error Messages


17xx-01

17xx-02

17xx-03

17xx-04

17xx-05

17xx-06

17xx-07

17xx-08

17xx-09

17xx-10

17xx-19

17xx-40

17xx-41

17xx-42

17xx-43

17xx-44

17xx-45

17xx-46

17xx-47

17xx-48

17xx-49

17xx-50

Exceeded max. soft error limit

Exceeded max. Hard error limit

17xx-51

17xx-52

Previously exceeded max. soft error limit 17xx-53

Previously exceeded max.hard error limit 17xx-54

Failed to reset controller 17xx-55

Fatal error while reading 17xx-56

Fatal error while writing

Failed compare of R/W buffers

Failed to format a track

Failed diskette sector wrap during read

Cntlr. failed to deallocate bad sectors

Cylinder 0 error

17xx-57

17xx-58

17xx-59

17xx-60

17xx-62

17xx-63

Drive not ready

Failed to recalibrate drive

Failed to format a bad track

Failed controller diagnostics

17xx-65

17xx-66

17xx-67

17xx-68

Failed to get drive parameters from ROM 17xx-69

Invalid drive parameters from ROM

Failed to park heads

Failed to move hard drive table to RAM

Failed to read media in file write test

Failed I/O write test

17xx-70

17xx-71

17xx-72

17xx-73

--

Failed I/O read test

Failed file I/O compare test

Failed drive/head register test

Failed digital input register test

Cylinder 1 error

Failed controller RAM diagnostics

Failed controller-to-drive diagnostics

Failed to write sector buffer

Failed to read sector buffer

Failed uncorrectable ECC error

Failed correctable ECC error

Failed soft error rate

Exceeded max. bad sectors per track

Failed to initialize drive parameter

Failed to write long

Failed to read long

Failed to read drive size

Failed translate mode

Failed non-translate mode

Bad track limit exceeded

Previously exceeded bad track limit

--

1700-xx = Hard drive ID test

1701-xx = Hard drive format test

1702-xx = Hard drive read test

1703-xx = Hard drive read/write compare test

1704-xx = Hard drive random seek test

1705-xx = Hard drive controller test

1706-xx = Hard drive ready test

1707-xx = Hard drive recalibrate test

1708-xx = Hard drive format bad track test

1709-xx = Hard drive reset controller test

1710-xx = Hard drive park head test

1714-xx = Hard drive file write test

1715-xx = Hard drive head select test

1716-xx = Hard drive conditional format test

1717-xx = Hard drive ECC test

1719-xx = Hard drive power mode test

1720-xx = SMART drive detects imminent failure

1721-xx = SCSI hard drive imminent failure

1724-xx = Net work preparation test

1736-xx = Drive monitoring test

1771-xx = Pri. IDE controller address conflict

1772-xx = Sec. IDE controller address conflict

1780-xx = Disk 0 failure


1782-xx = Pri. IDE controller failure



1792-xx = Se. controller failure

1793-xx = Sec. Controller or disk failure

1799-xx = Invalid hard drive type




A.14 HARD DRIVE ERROR MESSAGES (19xx-xx)

Table A–13. Hard Drive Error Messages

Table A-13.

Hard Drive Error Messages


19xx-01

19xx-02

19xx-03

19xx-04

19xx-05

19xx-06

19xx-07

19xx-08

19xx-09

19xx-10

19xx-11

19xx-12

19xx-13

19xx-14

19xx-15

19xx-16

19xx-17

19xx-18

19xx-19

19xx-20

Drive not installed

Cartridge not installed

Tape motion error

Drive busy erro

Track seek error

Tape write-protect error

Tape already Servo Written

Unable to Servo Write

Unable to format

Format mode error

Drive recalibration error

Tape not Servo Written

Tape not formatted

Drive time-out error

Sensor error flag

Block locate (block ID) error

Soft error limit exceeded

Hard error limit exceeded

Write (probably ID ) error

NEC fatal error

19xx-21

19xx-22

19xx-23

19xx-24

19xx-25

19xx-26

19xx-27

19xx-28

19xx-30

19xx-31

19xx-32

19xx-33

19xx-34

19xx-35

19xx-36

19xx-37

19xx-38

19xx-39

19xx-40

19xx-91

Got servo pulses second time but not first

Never got to EOT after servo check

Change line unset

Write-protect error

Unable to erase cartridge

Cannot identify drive

Drive not compatible with controller

Format gap error

Exception bit not set

Unexpected drive status

Device fault

Illegal command

No data detected

Power-on reset occurred

Failed to set FLEX format mode

Failed to reset FLEX format mode

Data mismatch on directory track

Data mismatch on track 0

Failed self-test

Power lost during test

1900-xx = Tape ID test failed

1901-xx = Tape servo write failed

1902-xx = Tape format failed

1903-xx = Tape drive sensor test failed

1904-xx = Tape BOT/EOT test failed

1905-xx = Tape read test failed

1906-xx = Tape R/W compare test failed

1907-xx = Tape write-protect failed

Table A–14. Video (Graphics) Error Messages

Table A-14.

Video (Graphics) Error Messages


2402-01

2403-01

2404-01

2405-01

2406-01

2407-01

2408-01

2409-01

2410-01

2411-01

2412-01

2414-01

2416-01

2417-01

2417-02

2417-03

2417-04

2418-01

Video memory test failed

Video attribute test failed

Video character set test failed




320x200 mode color set 0 test failed

320x200 mode color set 1 test failed


Screen memory page test failed

Gray scale test failed

2418-02

2419-01

EGA shadow RAM test failed

EGA ROM checksum test failed

2420-01 EGA attribute test failed

2421-01 640x200 mode test failed

2422-01 640x350 16-color set test failed


2424-01 EGA Mono. text mode test failed

2425-01 EGA Mono. graphics mode test failed

2431-01 640x480 graphics mode test failed


2448-01 Advanced VGA controller test failed

White screen test failed

Noise pattern test failed

2451-01 132-column AVGA test failed

2456-01 AVGA 256-color test failed

AVGA BitBLT test failed Lightpen text test failed, no response 2458-xx

Lightpen text test failed, invalid response 2468-xx

Lightpen graphics test failed, no resp. 2477-xx

AVGA DAC test failed

AVGA data path test failed

Lightpen graphics tst failed, invalid resp. 2478-xx

EGA memory test failed 2480-xx

AVGA BitBLT test failed

AVGA linedraw test failed



A-9


A.16 AUDIO ERROR MESSAGES (3206-xx)

Table A–15. Audio Error Messages

Table A-15.

Audio Error Message

3206-xx Audio subsystem internal error

Table A–16. DVD/CD-ROM Drive Error Messages

Table A-16.

DVD/CD-ROM Drive Error Messages

3301-xx

3305-XX

Drive test failed

Seek test failed

See Table A-18 for additional messages.

Table A–17. Network Interface Error Messages

Table A-17.

Network Interface Error Messages


6000-xx

6014-xx

6016-xx

6028-xx

6029-xx

Pointing device interface error

Ethernet configuration test failed

Ethernet reset test failed

Ethernet int. loopback test failed

Ethernet ext. loopback test failed

6054-xx

6056-xx

6068-xx

6069-xx

6089-xx

Token ring configuration test failed

Token ring reset test failed

Token ring int. loopback test failed

Token ring ext. loopback test failed

Token ring open




A.19 SCSI INTERFACE ERROR MESSAGES (65xx-xx, 66xx-xx, 67xx-xx)

Table A–18. SCSI Interface Error Messages

Table A-18.

SCSI Interface Error Messages


6nyy-02

6nyy-03

6nyy-05

6nyy-06

6nyy-07

6nyy-08

6nyy-09

6nyy-10

6nyy-11

6nyy-12

6nyy-13

6nyy-14

Drive not installed

Media not installed

Seek failure

Drive timed out

Drive busy

Drive already reserved

Reserved

Reserved

Media soft error

Drive not ready

Media error

Drive hardware error

6nyy-15

6nyy-16

6nyy-17

6nyy-18

6nyy-21

6nyy-24

Illegal drive command

Media was changed

Tape write-protected

No data detected

Drive command aborted

Media hard error

6nyy-25 Reserved

6nyy-30 Controller timed out

6nyy-32 Controller/drive not connected

6nyy-33

6nyy-34

6nyy-35

6nyy-36

6nyy-39

6nyy-40

6nyy-41

6nyy-42

6nyy-43

6nyy-44

6nyy-50

6nyy-51

6nyy-52

6nyy-53

6nyy-54

6nyy-60

6nyy-61

6nyy-65

6nyy-91

6nyy-92

6nyy-99

Illegal controller command

Invalid SCSI bus phase



Error status from drive

Drive timed out

SSI bus stayed busy

ACK/REQ lines bad

ACK did not deassert

Parity error

Data pins bad

Data line 7 bad

MSG, C/D, or I/O lines bad

BSY never went busy

BSY stayed busy

Controller CONFIG-1 register fault

Controller CONFIG-2 register fault

Media not unloaded

Over temperature condition

Side panel not installed

Autoloader reported tape not loaded properly n = 5, Hard drive

= 6, CD-ROM drive

= 7, Tape drive. yy = 00, ID

= 03, Power check

= 05, Read

= 06, SA/Media

= 08, Controller

= 23, Random read

= 28, Media load/unload

A.20 POINTING DEVICE INTERFACE ERROR MESSAGES (8601-xx)

Table A–19. Pointing Device Interface Error Messages

Table A-19.

Pointing Device Interface Error Messages


Mouse ID fails 8601-07 Right block not selected 8601-01

8601-02

8601-03

8601-04

8601-05

8601-06

Left mouse button is stuck closed 8601-09

Right mouse button is stuck closed 8602-xx

Left block not selected --

Mouse loopback test failed

I/F test failed

--



A-11






Appendix B

ASCII CHARACTER SET

B. Appendix B ASCII CHARACTER SET

B.1 INTRODUCTION

This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and hexadecimal values. All ASCII symbols may be called while in DOS or using standard text-mode editors by using the combination keystroke of holding the Alt key and using the Numeric Keypad to enter the decimal value of the symbol. The extended ASCII characters (decimals 128-255) can only be called using the Alt + Numeric Keypad keys.

NOTE: Regarding keystrokes, refer to notes at the end of the table. Applications may interpret multiple keystroke accesses differently or ignore them completely.

Figure B–1. ASCII Character Set

Table B-1.

ASCII Character Set

Dec Hex Symbol Dec Hex Symbol Dec Hex Symbol Dec Hex Symbol

3 03 ♥

4 04 ♦

5 05 ♣

6 06 ♠

7 07 O

8 08 P

35 23 # 67 43 C 99 63 c

36 24 $ 68 44 D 100 d

37 25 % 69 45 E 101 e

38 26 & 70 46 F 102 f

39 27 ‘ 71 47 G 103 g

40 28 ( 72 48 H 104 h

10 0A 42 2A * 74 4A J 106 j

11 0B 43 2B + 75 4B K 107 k

12 0C 44 2C ` 76 4C L 108 l

13 0D 45 2D - 77 4D M 109

14 0E 46 2E . 78 4E N 110 n

15 0F 47 2F / 79 4F O 111

16 10

4

17 11

3

48 30 0 80 50 P 112

49 31 1 81 51 Q 113 p q

18 12 ¦ 50 32 2 82 52 R 114 r

19 13 !! 51 33 3 83 53 S 115 s

20 14 ¶ 52 34 4 84 54 T 116 t

22 16

0

23 17 ¦

24 18 ↑

25 19 ↓

54 36 6 86 56 V 118 v

55 37 7 87 57 W 119 w

56 38 8 88 58 X 120 x

57 39 9 89 59 Y 121 y

26 1A →

27 1B ←

31 1F W

58 3A : 90 5A Z 122 z

59 3B ; 91 5B [ 123 {

28 1C 60 3C < 92 5C \ 124 |

29 1D ↔

30 1E V

61 3D = 93 5D ] 125 }

62 3E > 94 5E ^ 126 ~

63 3F ? 95 5F _ 127 7F [1]

Continued


Changed - July 2000

B-1

Appendix B ASCII Character Set

Table B-1. ASCII Code Set (Continued)

Dec Hex Symbol Dec Hex Symbol Dec Hex Symbol Dec Hex Symbol

128 80

Ç

160 A0

á

192 C0

└

224 E0

α

129 81

ü

161 A1

í

193 C1

┴

225 E1

ß

130 82

é

162 A2

ó

194 C2

┬

226 E2

Γ

131 83

â

163 A3

ú

195 C3

├

227 E3

π

132 84

ä

133 85

à

134 86

å

135 87

ç

136 88

ê

137 89

ë

138 8A

è

139 8B

ï

140 8C

î

141 8D

ì

142 8E

Ä

143 8F

Å

144 90

É

145 91

æ

146 92

Æ

147 93

ô

148 94

ö

149 95

ò

150 96

û

151 97

ù

152 98

ÿ

153 99

Ö

154 9A

Ü

155 9B

¢

156 9C

£

157 9D

¥

158 9E

₧

159 9F

ƒ

164 A4

ñ

165 A5

Ñ

166 A6

ª

167 A7

º

168 A8

¿

169 A9

⌐

170 AA

¬

171 AB

½

172 AC

¼

173 AD

¡

174 AE

«

175 AF

»

176 B0

░

177 B1

▒

178 B2

▓

179 B3

│

180 B4

┤

181 B5

╡

182 B6

╢

183 B7

╖

184 B8

╕

185 B9

╣

186 BA

║

187 BB

╗

188 BC

╝

189 BD

╜

190 BE

191 BF

╛

┐

196 C4

─

197 C5

┼

198 C6

╞

199 C7

╟

200 C8

╚

201 C9

╔

202 CA

╩

203 CB

╦

204 CC

╠

205 CD

═

206 CE

╬

207 CF

╧

208 D0

╨

209 D1

╤

210 D2

╥

211 D3

╙

212 D4

╘

213 D5

╒

214 D6

╓

215 D7

╫

216 D8

╪

217 D9

┘

218 DA

┌

219 DB

█

220 DC

▄

221 DD

▌

222 DE

223 DF

▐

▀

228 E4

Σ

229 E5

σ

230 E6

µ

231 E7

τ

232 E8

Φ

233 E9

Θ

234 EA

Ω

235 EB

δ

236 EC

∞

237 ED

φ

238 EE

ε

239 EF

∩

240 F0

≡

241 F1

±

242 F2

≥

243 F3

≤

244 F4

⌠

245 F5

⌡

246 F6

÷

247 F7

≈

248 F8

°

249 F9

·

250 FA

·

251 FB

√

252 FC ⁿ

253 FD

254 FE

²

■

255 FF Blank

NOTES:

[1] Symbol not displayed.

Dec # Keystroke(s)

1-26 Ctrl A thru Z respectively

33-43 Shift and key w/corresponding symbol

48-57 Key w/corresponding symbol, numerical keypad w/Num Lock active

58 Shift and key w/corresponding symbol

60 Shift and key w/corresponding symbol

62-64 Shift and key w/corresponding symbol

65-90 Shift and key w/corresponding symbol or key w/corresponding symbol and

Caps Lock active

94, 95 Shift and key w/corresponding symbol

97-126 Key w/corresponding symbol or Shift and key w/corresponding symbol

and Caps Lock active

128-255 Alt and decimal digit(s) of desired character

B-2 Compaq Personal Computers



Appendix C

KEYBOARD

C.

Appendix C KEYBOARD

C.1 INTRODUCTION

This appendix describes the Compaq keyboard that is included as standard with the system unit.

The keyboard complies with the industry-standard classification of an “enhanced keyboard” and includes a separate cursor control key cluster, twelve “function” keys, and enhanced programmability for additional functions.

This appendix covers the following keyboard types:

♦ Standard enhanced keyboard.

♦ Space-Saver Windows-version keyboard featuring additional keys for specific support of the

Windows operating system.

♦ Easy Access keyboard with additional buttons for internet accessibility functions.

Only one type of keyboard is supplied with each system. Other types may be available as an option.

NOTE: This appendix discusses only the keyboard unit. The keyboard interface is a function of the system unit and is discussed in Chapter 5, Input/Output Interfaces.

Topics covered in this appendix include the following:

♦ Keystroke processing (C.2)

♦ Connectors page C-2


Changed –- July 2000

C-1

Appendix C Keyboard

A functional block diagram of the keystroke processing elements is shown in Figure C-1. Power

(+5 VDC) is obtained from the system through the PS/2-type interface. The keyboard uses a

Z86C14 (or equivalent) microprocessor. The Z86C14 scans the key matrix drivers every 10 ms for pressed keys while at the same time monitoring communications with the keyboard interface of the system unit. When a key is pressed, a Make code is generated. A Break code is generated when the key is released. The Make and Break codes are collectively referred to as scan codes. All keys generate Make and Break codes with the exception of the Pause key, which generates a

Make code only.

Num

Lock

Caps

Lock

Scroll

Lock

Keyswitch

Matrix

Matrix

Drivers

Matrix

Receivers

Keyboard

Processor

Data/

CLK

Keyboard

Interface

(System Unit)

Figure C–1. Keystroke Processing Elements, Block Diagram

When the system is turned on, the keyboard processor generates a Power-On Reset (POR) signal after a period of 150 ms to 2 seconds. The keyboard undergoes a Basic Assurance Test (BAT) that checks for shorted keys and basic operation of the keyboard processor. The BAT takes from

300 to 500 ms to complete.

If the keyboard fails the BAT, an error code is sent to the CPU and the keyboard is disabled until an input command is received. After successful completion of the POR and BAT, a completion code (AAh) is sent to the CPU and the scanning process begins.

The keyboard processor includes a 16-byte FIFO buffer for holding scan codes until the system is ready to receive them. Response and typematic codes are not buffered. If the buffer is full (16 bytes held) a 17 th byte of a successive scan code results in an overrun condition and the overrun code replaces the scan code byte and any additional scan code data (and the respective key strokes) are lost. Multi-byte sequences must fit entirely into the buffer before the respective keystroke can be registered.

C-2 Compaq Personal Computers



C.2.1 PS/2-TYPE KEYBOARD TRANSMISSIONS

Clock

Data

The PS/2-type keyboard sends two main types of data to the system; commands (or responses to system commands) and keystroke scan codes. Before the keyboard sends data to the system

(specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and loads the data into a buffer. Once the inhibited state is removed, the data is sent to the system.

Keyboard-to-system transfers (in the default mode) consist of 11 bits as shown in Figure C-2.

Tcy

Tcl

Bit

Tch

Start

Th-b-t

(LSb)

Dat a

Dat a

Dat a

Dat a

Dat a

Dat a

Dat a

(MSb)

Dat a

Parity

Bit

Stop

Bit

Tcy (clock cycle)

Tcl (clock low)

Tch (clock high)

Th-b-t (high-before-transmit)

60 us

30 us

30 us

--

--

41 us

--

20 us

80 us

50 us

40 us

--

Figure C–2. PS/2 Keyboard-To-System Transmission, Timing Diagram

The system can halt keyboard transmission by setting the clock signal low. The keyboard checks the clock line every 60 us to verify the state of the signal. If a low is detected, the keyboard will finish the current transmission if the rising edge of the clock pulse for the parity bit has not occurred. The system uses the same timing relationships during reads (typically with slightly reduced time periods).

The enhanced keyboard has three operating modes:

♦ Mode 1 - PC-XT compatible

♦ Mode 2 - PC-AT compatible (default)

♦ Mode 3 - Select mode (keys are programmable as to make-only, break-only, typematic)

Modes can be selected by the user or set by the system. Mode 2 is the default mode. Each mode produces a different set of scan codes. When a key is pressed, the keyboard processor sends that key’s make code to the 8042 logic of the system unit. The When the key is released, a release code is transmitted as well (except for the Pause key, which produces only a make code). The

8042-type logic of the system unit responds to scan code reception by asserting IRQ1, which is processed by the interrupt logic and serviced by the CPU with an interrupt service routine. The service routine takes the appropriate action based on which key was pressed.



C-3


C.2.2 USB-TYPE KEYBOARD TRANSMISSIONS

The USB-type keyboard sends essentially the same information to the system that the PS/2 keyboard does except that the data receives additional NRZI encoding and formatting (prior to leaving the keyboard) to comply with the USB I/F specification (discussed in chapter 5 of this guide).

Packets received at the system’s USB I/F and decoded as originating from the keyboard result in an SMI being generated. An SMI handler routine is invoked that decodes the data and transfers the information to the 8042 keyboard controller where normal (legacy) keyboard processing takes place.




C.2.3 KEYBOARD LAYOUTS

Figures C-3 through C-8 show the key layouts for keyboards shipped with Compaq systems.

Actual styling details including location of the Compaq logo as well as the numbers lock, caps lock, and scroll lock LEDs may vary.

C.2.3.1 Standard Enhanced Keyboards

1

17

39

59

18

75

92

40

2

19

60

41

76

3

20

61

93

42

77

4

21

62

43

78

5

22

63

44

79

23

64

6

45

80

24

65

7

81

94

46

25

66

8

47

82

26

67

9

48

83

27

68

10

49

84

28

69

11

50

85

95

29

70

12

51

31

13

30

71

86

96

Figure C–3. U.S. English (101-Key) Keyboard Key Positions

14 15 16

32 33 34

52 53 54

87

97 98 99

1 2 3 4 5

6

7 8 9 10 11 12 13

17 18 19 20 21 22 23 24 25 26 27 28 29 31

39

59

75

92

40

60

41

61

42

62

43

63

44

64

45

65

46

66

47

67

48

68

49

69

50 51

70

103

71

104

76

93

77 78 79 80

94

81 82 83 84 85

95

86

96

14 15 16

32 33 34

52 53 54

87

97 98 99

Figure C–4. National (102-Key) Keyboard Key Positions

35 36 37 38

55 56

72 73

57

74

58

88

100

89 90

101

91

35 36 37 38

55 56

72 73

57

74

58

88

100

89 90

101

91



C-5


C.2.3.2 Windows Enhanced Keyboards

1

17

39

59

92

18

75

40

110

2

19

60

41

76

3

20

61

77

93

42

4

21

62

43

78

5

22

63

44

79

23

64

6

45

80

65

94

24

7

46

81

25

66

8

47

82

26

67

9

48

83

27

68

84

95

10

49

28

69

85

11

50

29

70

111 112

12

51

31

13

30

71

86

96

14 15 16

32 33 34

52 53 54

87

97 98 99

Figure C–5. U.S. English Windows (101W-Key) Keyboard Key Positions

1 2 3 4 5

6

7 8 9 10 11 12 13

17 18 19 20 21 22 23 24 25 26 27 28 29 31

39 40 41 42 43 44 45 46 47 48 49 50 51

75

59 60

104

76

61 62

77 78

63

79

64

80

65

81

66

82

67

83

68 69

84 85

70

103

86

71

92 110 93 94 95 111 112 96

14 15 16

32 33 34

52 53 54

87

97 98 99

Figure C–6. National Windows (102W-Key) Keyboard Key Positions

35 36 37 38

55 56

72 73

57

74

58

88

100

89 90

101

91

35 36 37 38

55 56

72 73

57

74

58

88

100

89 90

101

91




C.2.3.3 Easy Access Keyboards

The Easy Access keyboard is a Windows Enhanced-type keyboard that includes special buttons allowing quick internet navigation. Depending on system, either a 7-button or an 8-button layout may be supplied.

The 7-button Easy Access Keyboard uses the layout shown in Figure C-7 and is available with either a legacy PS/2-type connection or a Universal Serial Bus (USB) type connection.

Btn 1 Btn 2 Btn 3 Btn 4 Btn 5 Btn 6 Btn 7

NOTE:

Main key positions same as Windows Enhanced (Figures C-5 or C-6).

Figure C–7. 7-Button Easy Access Keyboard Layout

The 8-button Easy Access Keyboard uses the layout shown in Figure C-8 and uses the PS/2-type connection.

Btn 1 Btn 2 Btn 3 Btn 4 Btn 5 Btn 6 Btn 7 Btn 8

NOTE:

Main key positions same as Windows Enhanced (Figures C-5 or C-6).

Figure C–8. 8-Button Easy Access Keyboard Layout



C-7


C.2.4 KEYS

All keys generate a make code (when pressed) and a break code (when released) with the exception of the Pause key (pos. 16), which produces a make code only. All keys with the exception of the Pause and Easy Access keys are also typematic, although the typematic action of the Shift, Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins keys is suppressed by the

BIOS. Typematic keys, when held down longer than 500 ms, send the make code repetitively at a

10-12 Hz rate until the key is released. If more than one key is held down, the last key pressed will be typematic.

The following keys provide the intended function in most applications and environments.

Caps Lock - The Caps Lock key (pos. 59), when pressed and released, invokes a BIOS

routine that turns on the caps lock LED and shifts into upper case key positions 40-49, 60-68, and 76-82. When pressed and released again, these keys revert to the lower case state and the

LED is turned off. Use of the Shift key will reverse which state these keys are in based on the

Caps Lock key.

Num Lock - The Num Lock key (pos. 32), when pressed and released, invokes a BIOS routine that turns on the num lock LED and shifts into upper case key positions 55-57, 72-74, 88-90,

100, and 101. When pressed and released again, these keys revert to the lower case state and the

LED is turned off.

The following keys provide special functions that require specific support by the application.

Print Scrn - The Print Scrn (pos. 14) key can, when pressed, generate an interrupt that initiates a print routine. This function may be inhibited by the application.

Scroll Lock - The Scroll Lock key (pos. 15) when pressed and released, , invokes a BIOS routine that turns on the scroll lock LED and inhibits movement of the cursor. When pressed and released again, the LED is turned off and the function is removed. This keystroke is always serviced by the BIOS (as indicated by the LED) but may be inhibited or ignored by the application.

Pause - The Pause (pos. 16) key, when pressed, can be used to cause the keyboard interrupt to loop, i.e., wait for another key to be pressed. This can be used to momentarily suspend an operation. The key that is pressed to resume operation is discarded. This function may be ignored by the application.

The Esc, Fn (function), Insert, Home, Page Up/Down, Delete, and End keys operate at the discretion of the application software.




C.2.4.2 Multi-Keystroke Functions

Shift - The Shift key (pos. 75/86), when held down, produces a shift state (upper case) for keys in positions 17-29, 30, 39-51, 60-70, and 76-85 as long as the Caps Lock key (pos. 59) is toggled off. If the Caps Lock key is toggled on, then a held Shift key produces the lower (normal) case for the identified pressed keys. The Shift key also reverses the Num Lock state of key positions

55-57, 72, 74, 88-90, 100, and 101.

Ctrl - The Ctrl keys (pos. 92/96) can be used in conjunction with keys in positions 1-13, 16, 17-

34, 39-54, 60-71, and 76-84. The application determines the actual function. Both Ctrl key positions provide identical functionality. The pressed combination of Ctrl and Break (pos. 16) results in the generation of BIOS function INT 1Bh. This software interrupt provides a method of exiting an application and generally halts execution of the current program.

Alt - The Alt keys (pos. 93/95) can be used in conjunction with the same keys available for use with the Ctrl keys with the exception that position 14 (SysRq) is available instead of position 16

(Break). The Alt key can also be used in conjunction with the numeric keypad keys (pos. 55-57,

72-74, and 88-90) to enter the decimal value of an ASCII character code from 1-255. The application determines the actual function of the keystrokes. Both Alt key positions provide identical functionality. The combination keystroke of Alt and SysRq results in software interrupt

15h, AX=8500h being executed. It is up to the application to use or not use this BIOS function.

The Ctrl and Alt keys can be used together in conjunction with keys in positions 1-13, 17-34, 39-

54, 60-71, and 76-84. The Ctrl and Alt key positions used and the sequence in which they are pressed make no difference as long as they are held down at the time the third key is pressed. The

Ctrl , Alt, and Delete keystroke combination (required twice if in the Windows environment) initiates a system reset (warm boot) that is handled by the BIOS.

Windows-enhanced keyboards include three additional key positions. Key positions 110 and 111

(marked with the Windows logo ) have the same functionality and are used by themselves or in combination with other keys to perform specific “hot-key” type functions for the Windows operating system. The defined functions of the Windows logo keys are listed as follows:

Window Logo

Window Logo + F1

Window Logo + TAB

Window Logo + E

Open Start menu

Display pop-up menu for the selected object

Activate next task bar button

Explore my computer

Window Logo + F Find document

Window Logo + CTRL + F Find computer

Window Logo + M

Shift + Window Logo + M

Window Logo + R

Window Logo + PAUSE

Minimize all

Undo minimize all

Display Run dialog box

Perform system function

Window Logo + 0-9 Reserved for OEM use (see following text)

The combination keystroke of the Window Logo + 1-0 keys are reserved for OEM use for auxiliary functions (speaker volume, monitor brightness, password, etc.).

Key position 112 (marked with an application window icon ) is used in combination with other keys for invoking Windows application functions.



C-9


C.2.4.4 Easy Access Keystrokes

The Easy Access keyboards (Figures C-7 and C-8) include additional keys (also referred to as buttons) used to streamline internet access and navigation.

These buttons, which can be re-programmed to provide other functions, have the default functionality described below:

7-Button Easy Access Keyboard:

Button #

2

3

Description

Go to community

Extra web site

Default Function

Email

Emoney

Compaq web site

4 Go to favorite web site AltaVista web site

5 Internet Search

6 Instant answer

7 E-commerce

Travel expenses

Shopping

8-Button Easy Access Keyboard:

4

5

6

Button #

1

2

3

7

8

Description

Go to favorite web site

Go to AltaVista

Search

Check Email

Business Community

Market Monitor

Meeting Center

News/PC Lock

Default Function

Customer web site of choice

AltaVista web site

AltaVista search engine

Launches user Email

Industry specification info

Launches Bloomberg market monitor

Links to user’s project center

News retrieval service

All buttons may be re-programmed by the user through the Easy Access utility.




C.2.5 KEYBOARD COMMANDS

Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042type logic).

Table C–1. Keyboard-to-System Commands

Table C-1.

Keyboard-to-System Commands

Command

Key Detection Error/Over/run

Value Description

00h [1] Indicates to the system that a switch closure couldn’t be

FFh [2] identified.

BAT Completion

BAT Failure

Echo

Acknowledge (ACK)

Resend

Keyboard ID

AAh

FCh

EEh

FAh

Indicates to the system that the BAT has been successful.

Indicates failure of the BAT by the keyboard.

Indicates that the Echo command was received by the keyboard.

Issued by the keyboard as a response to valid system inputs (except the Echo and Resend commands).

FEh Issued by the keyboard following an invalid input.

83ABh Upon receipt of the Read ID command from the system, the keyboard issues the ACK command followed by the two IDS bytes.

Note:

[1] Modes 2 and 3.

[2] Mode 1 only.

C.2.6 SCAN CODES

The scan codes generated by the keyboard processor are determined by the mode the keyboard is operating in.

♦ Mode 1: In Mode 1 operation, the keyboard generates scan codes compatible with 8088-

/8086-based systems. To enter Mode 1, the scan code translation function of the keyboard controller must be disabled. Since translation is not performed, the scan codes generated in

Mode 1 are identical to the codes required by BIOS. Mode 1 is initiated by sending command

F0h with the 01h option byte. Applications can obtain system codes and status information by using BIOS function INT 16h with AH=00h, 01h, and 02h.

♦ Mode 2: Mode 2 is the default mode for keyboard operation. In this mode, the 8042 logic translates the make codes from the keyboard processor into the codes required by the BIOS.

This mode was made necessary with the development of the Enhanced III keyboard, which includes additional functions over earlier standard keyboards. Applications should use BIOS function INT 16h, with AH=10h, 11h, and 12h for obtaining codes and status data. In Mode

2, the keyboard generates the Break code, a two-byte sequence that consists of a Make code immediately preceded by F0h (i.e., Break code for 0Eh is “F0h 0Eh”).

♦ Mode 3: Mode 3 generates a different scan code set from Modes 1 and 2. Code translation must be disabled since translation for this mode cannot be done.



C-11


Table C–2. Keyboard Scan Codes

Key

Pos.

Legend

1 Esc

2 F1

3 F2

4 F3

5 F4

6 F5

7 F6

8 F7

9 F8

10 F9

11 F10

12 F11

13 F12

14 Print Scrn

15

16

22

23

24

25

26

27

17

18

19

20

21

28

29

30

31

32

33

34

35

36

Scroll Lock

Pause

8

9

0

5

6

7

`

1

2

3

4

-

=

\

Backspace

Insert

Home

Page Up

Num Lock

/

37 *

38 -

39 Tab

40 Q

Table C-2.

Keyboard Scan Codes

Make / Break Codes (Hex)

Mode 1 Mode 2

01/81

3B/BB

3C/BC

3D/BD

3E/BE

3F/BF

40/C0

41/C1

42/C2

43/C3

44/C4

57/D7

58/D8

E0 2A E0 37/E0 B7 E0 AA

E0 37/E0 B7 [1] [2]

54/84 [3]

46/C6

E1 1D 45 E1 9D C5/na

E0 46 E0 C6/na [3]

29/A9

02/82

03/83

04/84

05/85

06/86

07/87

08/88

09/89

0A/8A

0B/8B

0C/8C

0D/8D

2B/AB

0E/8E

E0 52/E0 D2

E0 AA E0 52/E0 D2 E0 2A [4]

E0 2A E0 52/E0 D2 E0 AA [6]

E0 47/E0 D2

E0 AA E0 52/E0 D2 E0 2A [4]

E0 2A E0 47/E0 C7 E0 AA [6]

E0 49/E0 C7

E0 AA E0 49/E0 C9 E0 2A [4]

E0 2A E0 49/E0 C9 E0 AA [6]

45/C5

E0 35/E0 B5

E0 AA E0 35/E0 B5 E0 2A [1]

37/B7

4A/CA

0F/8F

10/90

Mode 3

0E/F0 0E

46/F0 46

1E/F0 1E

26/F0 26

25/F0 25

2E/F0 2E

36/F0 36

3D/F0 3D

3E/F0 3E

46/F0 46

45/F0 45

4E/F0 4E

55/F0 55

5C/F0 5C

66/F0 66

67/na

08/na

07/na

0F/na

17/na

1F/na

27/na

2F/na

37/na

3F/na

47/na

4F/na

56/na

5E/na

57/na E0 2A E0 7C/E0 F0 7C E0 F0 12

E0 7C/E0 F0 7C [1] [2]

84/F0 84 [3]

7E/F0 7E

E1 14 77 E1 F0 14 F0 77/na

E0 7E E0 F0 7E/na [3]

0E/F0 E0

16/F0 16

1E/F0 1E

26/F0 26

25/F0 25

2E/F0 2E

36/F0 36

3D/F0 3D

3E/F0 3E

46/F0 46

45/F0 45

4E/F0 4E

55/F0 55

5D/F0 5D

66/F0 66

E0 70/E0 F0 70

E0 F0 12 E0 70/E0 F0 70 E0 12 [5]

E0 12 E0 70/E0 F0 70 E0 F0 12 [6]

E0 6C/E0 F0 6C

E0 F0 12 E0 6C/E0 F0 6C E0 12 [5]

E0 12 E0 6C/E0 F0 6C E0 F0 12 [6]

E0 7D/E0 F0 7D

E0 F0 12 E0 7D/E0 F0 7D E0 12 [5]

E0 12 E0 7D/E0 F0 7D E0 F0 12 [6]

77/F0 77

E0 4A/E0 F0 4A

E0 F0 12 E0 4A/E0 F0 4A E0 12 [1]

5F/na

62/na

6E/na

6F/na

76/na

77/na

7E/na

84/na

0D/na

15/na

Continued

([x] Notes listed at end of table.)




Table C-2. Keyboard Scan Codes (Continued)

Key

Pos Legend Mode 1


Mode 2

53

54

74

75

76

77

78

79

80

68

69

70

71

72

73

62

63

64

65

66

67

55

56

57

58

59

60

61

47

48

49

50

51

52

41

42

43

44

45

46

T

Y

U

W

E

R

I

O

P

[

]

Delete

End

Page Down

L

;

‘

Enter

4

5

X

C

V

B

6

Shift (left)

Z

H

J

K

D

F

G

7

8

9

+

Caps Lock

A

S

11/91

12/92

13/93

14/94

15/95

16/96

17/97

18/98

19/99

1A/9A

1B/9B

E0 53/E0 D3

E0 AA E0 53/E0 D3 E0 2A [4]

E0 2A E0 53/E0 D3 E0 AA [6]

E0 4F/E0 CF

E0 AA E0 4F/E0 CF E0 2A [4]

E0 2A E0 4F/E0 CF E0 AA [6]

E0 51/E0 D1

E0 AA E0 51/E0 D1 E0 2A [4]

E0 @a E0 51/E0 D1 E0 AA [6]

26/A6

27/A7

28/A8

1C/9C

4B/CB [6]

4C/CC [6]

4D/CD [6]

2A/AA

2C/AC

2D/AD

2E/AE

2F/AF

30/B0

47/C7 [6]

48/C8 [6]

49/C9 [6]

4E/CE [6]

3A/BA

1E/9E

1F/9F

20/A0

21/A1

22/A2

23/A3

24/A4

25/A5

1D/F0 1D

24/F0 24

2D/F0 2D

2C/F0 2C

35/F0 35

3C/F0 3C

43/F0 43

44/F0 44

4D/F0 4D

54/F0 54

5B/F0 5B

E0 71/E0 F0 71

E0 F0 12 E0 71/E0 F0 71 E0 12

[5]

E0 12 E0 71/E0 F0 71 E0 F0 12

[6]

E0 69/E0 F0 69

E0 F0 12 E0 69/E0 F0 69 E0 12

[5]

E0 12 E0 69/E0 F0 69 E0 F0 12

[6]

E0 7A/E0 F0 7A

E0 F0 12 E0 7A/E0 F0 7A E0 12

[5]

E0 12 E0 7A/E0 F0 7A E0 F0 12

[6]

6C/F0 6C [6]

75/F0 75 [6]

7D/F0 7D [6]

79/F0 79 [6]

58/F0 58

1C/F0 1C

1B/F0 1B

23/F0 23

2B/F0 2B

34/F0 34

33/F0 33

3B/F0 3B

42/F0 42

4B/F0 4B

4C/F0 4C

52/F0 52

5A/F0 5A

6B/F0 6B [6]

73/F0 73 [6]

74/F0 74 [6]

12/F0 12

1A/F0 1A

22/F0 22

21/F0 21

2A/F0 2A

32/F0 32

Mode 3

1D/F0 1D

24/F0 24

2D/F0 2D

2C/F0 2C

35/F0 35

3C/F0 3C

43/F0 43

44/F0 44

4D/F0 4D

54/F0 54

5B/F0 5B

64/F0 64

65/F0 65

6D/F0 6D

6C/na [6]

75/na [6]

7D/na [6]

7C/F0 7C

14/F0 14

1C/F0 1C

1B/F0 1B

23/F0 23

2B/F0 2B

34/F0 34

33/F0 33

3B/F0 3B

42/F0 42

4B/F0 4B

4C/F0 4C

52/F0 52

5A/F0 5A

6B/na [6]

73/na [6]

74/na [6]

12/F0 12

1A/F0 1A

22/F0 22

21/F0 21

2A/F0 2A

32/F0 32

Continued




C-13



Key

Pos.

Legend Mode 1


Mode 2

88

89

90

91

81

82

83

84

85

86

87

N

M

,

.

/

Shift (right)

1

2

3

Enter

31/B1

32/B2

33/B3

34/B4

35/B5

36/B6

E0 48/E0 C8

E0 AA E0 48/E0 C8 E0 2A [4]

E0 2A E0 48/E0 C8 E0 AA [6]

4F/CF [6]

50/D0 [6]

51/D1 [6]

E0 1C/E0 9C

31/F0 31

3A/F0 3A

41/F0 41

49/F0 49

4A/F0 4A

59/F0 59

E0 75/E0 F0 75

E0 F0 12 E0 75/E0 F0 75 E0 12 [5]

E0 12 E0 75/E0 F0 75 E0 F0 12 [6]

69/F0 69 [6]

72/F0 72 [6]

7A/F0 7A [6]

E0 5A/F0 E0 5A

98

99

100

101

102

103

104

110

92

93

94

95

96

97

111

Ctrl (left)

Alt (left)

(Space)

Alt (right)

Ctrl (right)

0

. na na na

(Win95) [7]

(Win95) [7]

1D/9D

38/B8

39/B9

E0 38/E0 B8

E0 1D/E0 9D

E0 4B/E0 CB

E0 AA E0 4B/E0 CB E0 2A [4]

E0 2A E0 4B/E0 CB E0 AA [6]

E0 50/E0 D0

E0 AA E0 50/E0 D0 E0 2A [4]

E0 2A E0 50/E0 D0 E0 AA [6]

E0 4D/E0 CD

E0 AA E0 4D/E0 CD E0 2A [4]

E0 2A E0 4D/E0 CD E0 AA [6]

52/D2 [6]

53/D3 [6]

7E/FE

2B/AB

36/D6

E0 5B/E0 DB

E0 AA E0 5B/E0 DB E0 2A [4]

E0 2A E0 5B/E0 DB E0 AA [6]

E0 5C/E0 DC

E0 AA E0 5C/E0 DC E0 2A [4]

E0 2A E0 5C/E0 DC E0 AA [6]

112 (Win

Apps)

E0 5D/E0 DD

E0 AA E0 5D/E0 DD E0 2A [4]

[7] E0 2A E0 5D E0 DD E0 AA [6]


Mode 3

31/F0 31

3A/F0 3A

41/F0 41

49/F0 49

4A/F0 4A

59/F0 59

63/F0 63

14/F0 14

11/F0 11

29/F0 29

E0 11/F0 E0 11

E0 14/F0 E0 14

E0 6B/Eo F0 6B

E0 F0 12 E0 6B/E0 F0 6B E0 12[5]

E0 12 E0 6B/E0 F0 6B E0 F0 12[6]

E0 72/E0 F0 72

E0 F0 12 E0 72/E0 F0 72 E0 12[5]

E0 12 E0 72/E0 F0 72 E0 F0 12[6]

E0 74/E0 F0 74

E0 F0 12 E0 74/E0 F0 74 E0 12[5]

E0 12 E0 74/E0 F0 74 E0 F0 12[6]

70/F0 70 [6]

71/F0 71 [6]

6D/F0 6D

5D/F0 5D

61/F0 61

E0 1F/E0 F0 1F

E0 F0 12 E0 1F/E0 F0 1F E0 12 [5]

E0 12 E0 1F/E0 F0 1F E0 F0 12 [6]

E0 2F/E0 F0 27

E0 F0 12 E0 27/E0 F0 27 E0 12 [5]

E0 12 E0 27/E0 F0 27 E0 F0 12 [6]

69/na [6]

72/na [6]

7A/na [6]

79/F0

79[6]

11/F0 11

19/F0 19

29/F0 29

39/na

58/na

61/F0 61

60/F0 60

6A/F0 6A

70/na [6]

71/na [6]

7B/F0 7B

53/F0 53

13/F0 13

8B/F0 8B

8C/F0 8C

E0 2F/E0 F0 2F

E0 F0 12 E0 2F/E0 F0 2F E0 12 [5]

8D/F0 8D

E0 12 E0 2F/E0 F0 2F E0 F0 12 [6

Continued





Key

Pos.

Legend

Btn 1 [8]

Btn 2 [8]

Btn 3 [8]

Btn 4 [8]

Btn 5 [8]

Btn 6 [8]

Btn 7 [8]

Btn 1 [9]

Btn 2 [9]

Btn 3 [9]

Btn 4 [9]

Btn 5 [9]

Btn 6 [9]

Btn 7 [9]

Btn 8 [9]

Mode 1

E0 1E/E0 9E

E0 26/E0 A6

E0 25/E0 A5

E0 23/E0 A3

E0 21/E0 A1

E0 12/E0 92

E0 32/E0 B2

E0 23/E0 A3

E0 1F/E0 9F

E0 1A/E0 9A

E0 1E/E0 9E

E0 13/E0 93

E0 14/E0 94

E0 15/E0 95

E0 1B/E0 9B


Mode 2

E0 1C/E0 F0 1C

E0 4B/E0 F0 4B

E0 42/E0 F0 42

E0 33/E0 F0 33

E0 2B/E0 F0 2B

E0 24/E0 F0 24

E0 3A/E0 F0 3A

E0 33/E0 F0 33

E0 1B/E0 F0 1B

E0 54/E0 F0 54

E0 1C/E0 F0 1C

E0 2D/E0 F0 2D

E0 2C/E0 F0 2C

E0 35/E0 F0 35

E0 5B/E0 F0 5B

NOTES:

All codes assume Shift, Ctrl, and Alt keys inactive unless otherwise noted.

NA = Not applicable

[1] Shift (left) key active.

[2] Ctrl key active.

[3] Alt key active.

[4] Left Shift key active. For active right Shift key, substitute AA/2A make/break codes for B6/36 codes.

[5] Left Shift key active. For active right Shift key, substitute F0 12/12 make/break codes

for F0 59/59 codes.

[6] Num Lock key active.

[7] Windows keyboards only.

[8] 7-Button Easy Access keyboard.

[9] 8-Button Easy Access keyboard.

Mode 3

95/F0 95

9C/F0 9C

9D/F0 9D

9A/F0 9A

99/F0 99

96/F0 96

97/F0 97

9A/F0 9A

80/F0 80

99/F0 99

95/F0 95

0C/F0 0C

9D/F0 9D

96/F0 96

97/F0 97



C-15


C.3 CONNECTORS

Two types of keyboard interfaces are used in Compaq systems: PS/2-type and USB-type. System units that provide a PS/2 connector will ship with a PS/2-type keyboard but may also support simultaneous connection of a USB keyboard. Systems that do not provide a PS/2 interface will ship with a USB keyboard. For a detailed description of the PS/2 and USB interfaces refer to chapter 5 “Input/Output” of this guide. The keyboard cable connectors and their pinouts are described in the following figures:

Pin Function

1 Data

5 6

3 Ground 3 4

1 2

5 Clock

Figure C–9. PS/2 Keyboard Cable Connector (Male)

Pin Function

4 3 2 1

4 Ground

Figure C–10. USB Keyboard Cable Connector (Male)




Appendix D

COMPAQ/NVIDIA VANTA LT

AGP GRAPHICS CARD

D. Appendix D Compaq/NVIDIA Vanta LT AGP Graphics Card

D.1 INTRODUCTION

This appendix describes the Compaq/NVIDIA Vanta LT AGP Graphics Card used in the standard configuration on some models and also available as an option. This card (layout shown in the following figure) installs in a system’s AGP slot. The Compaq/NVIDIA Vanta LT AGP Graphics card (P/N 192174-002) provides high 2D performance as well as 3D capabilities.

Analog

Monitor

Connector

SDRAM SDRAM

NVIDIA

Vanta LT

Controller

SDRAM

SDRAM

Figure D-1. Compaq/NVIDIA Vanta LT AGP Graphics Card (P/N 192174-002) Layout

This appendix covers the following subjects:

♦ Functional description (D.2)

♦ Monitor power management (D.5) page D-2

♦ Display modes (D.3) page D-3

♦ Software support information (D.4) page D-4 page D-4


Changed - October 2000

D-1

Appendix D Compaq/NVIDIA Vanta LT AGP Graphics Card

Card

Edge

Connector

AGP

Bus

The Compaq/NVIDIA Vanta LT Graphics Card provides high performance 2D and 3D display imaging. The card’s AGP design provides an economical approach to 3D processing by offloading 3D effects such as texturing, z-buffering and alpha blending to the system memory while

8 megabytes of on-board SDRAM stores the main display image.

AGP 4X

I/F

NVIDIA Vanta LT Graphics Controller

Video

Scalar

Memory

I/F

CRT

Controller

2D/VGA

Engine

BIOS

ROM

3D Array

Engine

250-MHz

RAM

DAC

128-bit

100-MHz

Data Bus

16 MB SDRAM

Frame Buffer

VSync

HSync

RGB

Figure D-2. Compaq/NVIDIA Vanta LT Graphics Card Block diagram

Analog

Monitor

Connector

The Compaq/NVIDIA Vanta LT Pro Graphics Card includes the following features:

♦ 8-MB SDRAM frame buffer using 128-bit 100-MHz access

♦ AGP 2X transfers with sideband addressing

♦ 2D drawing engine providing:

• 3 ROP BtBLT

• Triangle BLT

• Stretch BLT

• Line and poly draw

• Color expansion

• Coor conversion and scaling

♦ 3D rendering engine with:

• Triangle setup

• Anistropic filtering

• Flat and Gouraud shading

• Trilinear filtering

• TwinTexel engine

♦ 250-MHz RAMDAC

♦ 32-bit Z/stencil buffer eliminates hidden screen portions for faster loading

♦ 32-bit color for increased image quality

♦ 30-fps full-screen DVD playback

♦ Dual-monitor support with a PCI graphics card

D-2 Compaq Personal Computers



Resolution

640 x 480

640 x 480

640 x 480

800 x 600

800 x 600

800 x 600

1024 x 768

1024 x 768

1024 x 768

1152 x 864

1152 x 864

1152 x 864

1280 x 1024

1280 x 1024

1280 x 1024

1600 x 1200

1600 x 1200

The 2D graphics display modes supported by the Compaq/NVIDIA Vanta LT Graphics Card are listed in Table D-1.

Table D-1. NVIDIA Vanta LT 2D Graphics Display Modes

Table D-1.

NVIDIA Vanta LT Display Modes

Bits per pixel

16

24

8

16

24

8

16

24

8

16

8

16

24

8

16

24

8

Color Depth

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

Max. Refresh Frequency (Hz)

85

85

85

85

85

85

85

85

85

75

85

85

85

85

85

85

85



D-3


D.4 SOFTWARE SUPPORT INFORMATION

The Compaq/NVIDIA Vanta LT Pro graphics card is fully compatible with software written for legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes.

Drivers are provided with or available for the card to provide extended mode support for the current operating systems and programming environments such as:

♦ Windows 98, 95

♦ Windows NT 4.0, 3.51

♦ Windows 3.11, 3.1

♦ OS/2

♦ Quick Draw

♦ MS Direct Draw and Direct X

♦ Direct 3D

♦ OpenGL

This controller provides monitor power control for monitors that conform to the VESA display power management signaling (DPMS) protocol. This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition. Table I-2 lists the monitor power conditions.

Table D-2. Monitor Power Management Conditions

Table D-2.

Monitor Power Management Conditions

HSYNC VSYNC Power Mode Description

Active Active On

Active Inactive

Inactive Inactive

Suspend

Off

Monitor is completely powered up. If activated, the inactivity counter counts down during system inactivity and if allowed to tiemout, generates an SMI to initiate the Suspend mode.

Monitor’s high voltage section is turned off and CRT heater

(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode inactivity timer counts down from the preset value and if allowed to timeout, another SMI is generated and serviced, resulting in the monitor being placed into the Off mode. Wake up from

Suspend mode is typically a few seconds.

Monitor’s high voltage section and heater circuitry is turned off.

Wake up from Off mode is a little longer than from Suspend.

The graphics card’s maximum power consumption on the AGP bus is listed below:

Typical current draw @ 3.3 VDC: 1.5 A

Typical current draw @ 5.0 VDC: 50 mA




D.6 CONNECTORS

There is one connector associated with this graphics card; the monitor connector.

NOTE: The graphic card’s edge connector mates with the AGP slot connector on the system board. This interface is described in chapter 4 of this guide.

The DB-15 disply/monitor connector is provided for connection of a compatible RGB/analog monitor. The Feature connector allows the attachment of an optional card such as a video tuner.

D.6.1 MONITOR CONNECTOR

9

Figure D-3. VGA Monitor Connector, (Female DB-15, as viewed from rear).

Table D-3. DB-15 Monitor Connector Pinout

Table D-3.

DB-15 Monitor Connector Pinout

Pin Signal

1 R

2 G

3

4

B

NC

5 GND

6 R GND

7 G GND

Red Analog

Green Analog

Not Connected

Ground

Red Analog Ground

Green Analog Ground

9 PWR

10 GND

11

12

NC

SDA

13 HSync

14 VSync

15 SCL

8

NOTES:

B GND Blue Analog Ground -- --

[1] Fuse automatically resets when excessive load is removed.

+5 VDC (fused) [1]

Ground

Not Connected

DDC2-B Data

Vertical Sync

DDC2-B Clock

--



D-5






Appendix E

COMPAQ/NVIDIA QUADRO2 EX/MXR

AGP GRAPHICS CARDS

E.

Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics

Cards

E.1 INTRODUCTION

This appendix describes the Compaq/NVIDIA Quadro2 EX and MXR AGP Graphics Cards used in the standard configuration on some models and also available as an option. These cards (layout shown in the following figure) installs in a system’s AGP slot and provide high 2D performance as well as entry-level 3D capabilities.

DVI

Monitor

Connector

Analog

Monitor

Connector

Feature Connector

SDRAM SDRAM

NVIDIA

NV11GL

Controller

SDRAM

SDRAM

NOTES:

NVIDIA Quadro2 EX Graphics Card

NVIDIA Quadro2 MXR Graphics Card only

Figure E-1. Compaq/NVIDIA Quadro2 EX or MXR AGP Graphics Card Layout


♦ Functional description (E.2)

♦ Display modes (E.3) page E-3

♦ Software support information (E.4) page E-4

♦ Monitor power management (E.5)

♦ Connectors page E-2 page E-4



E-1

Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards

The NVIDIA Quadro2 MXR Graphics Card provides high performance 2D and 3D display imaging. The card’s AGP design provides an economical approach to 3D processing by offloading 3D effects such as texturing, z-buffering and alpha blending to the system memory while

32 megabytes of on-board SDRAM stores the main display image.

Card

Edge

Connector

AGP

Bus

AGP 4X

I/F

NVIDIA NV11GL Graphics Controller

Video

Scalar

Memory

I/F

CRT

Controller

128-bit

166-MHz

Data Bus

VSync

HSync

BIOS

ROM

2D/VGA

Engine

3D Array

Engine

350-MHz

RAM

DAC

RGB

Digital Video

Interface

Figure E-2. NVIDIA Quadro2 EX/MXR Graphics Card Block diagram

DVI

32 MB

SDRAM

Frame Buffer

Analog

Monitor

Connector

DVI

Monitor

Connector

(Quadro MXR only)

The NVIDIA Quadro2 EX/MXR Graphics Cards include the following features:



♦ 2D drawing engine

♦ 3D rendering engine

♦ 350-MHz RAMDAC

♦ 32-bit Z/stencil buffer eliminates hidden screen portions for faster loading

♦ 32-bit color for increased image quality

♦ 30-fps full-screen DVD playback

♦ Dual-monitor support with a PCI graphics card

♦ DVI monitor support (Quadro MXR only)

The NVIDIA Quadro2 MXR provides, in addition to the RGB monitor connector, a digital video interface (DVI) connector that can directly drive a DVI monitor or another RGB monitor through an adapter.

E-2 Compaq Personal Computers

Changed - October2001


The 2D graphics display modes supported by the NVIDIA Quadro2 MXR Graphics are listed in

Table E-1.

Table E-1. NVIDIA Quadro2 MXR Graphics Display Modes

Table E-1.

NVIDIA Quadro2 EX/MXR Graphics Display Modes

Resolution

640 x 480

640 x 480

640 x 480

800 x 600

800 x 600

800 x 600

1024 x 768

1024 x 768

1024 x 768

1152 x 864

1152 x 864

1152 x 864

1280 x 1024

1280 x 1024

1280 x 1024

1600 x 1000

1600 x 1000

1600 x 1000

1600 x 1200

1600 x 1200

1600 x 1200

1600 x 1280

1600 x 1280

1600 x 1280

1920 x 1080

1920 x 1080

1920 x 1080

1920 x 1200

1920 x 1200

1920 x 1200

Bits per pixel

8

16

32

8

16

32

8

16

32

8

16

32

8

16

32

8

16

32

8

16

32

8

16

32

8

16

32

8

16

32

Color Depth

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

Max. Refresh

Frequency (Hz) [1]

240

240

240

240

240

240

200

200

200

170

170

170

150

150

150

120

120

120

100

100

100

100

100

100

85

85

85

85

85

85

Memory Used

For Texture

NOTE:

[1] Values reflect hardware capability. May be restricted to lower frequency by operating system.

20.3 MB

N/A

N/A

16.6 MB

N/A

22.6 MB

13.3 MB

N/A

20.8 MB

9.5 MB

N/A

20.0 MB

N/A

N/A

28.4 MB

N/A

N/A

26.4 MB

N/A

N/A

22.8 MB

N/A

N/A

8.0 MB

N/A

19.9 MB

7.7 MB

N/A

18.5 MB

5.0 MB



E-3


E.4 SOFTWARE SUPPORT INFORMATION

The NVIDIA Quadro2 MXR graphics card is fully compatible with software written for legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes.


♦ Windows 3.1, 95, 98, 2000, ME

♦ Windows NT 4.0, 3.51

♦ Whistler

♦ Linux

♦ OS/2

♦ Quick Draw

♦ MS Direct Draw and Direct X

♦ Direct 3D

♦ OpenGL

This controller provides monitor power control for monitors that conform to the VESA display power management signaling (DPMS) protocol. This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition. Table E-2 lists the monitor power conditions.

Table E-2. Monitor Power Management Conditions

Table E-2.


HSYNC VSYNC Power Mode Description

Active Active On Monitor is completely powered up. If activated, the inactivity counter counts down during system inactivity and if allowed to timeout, generates an SMI to initiate the Suspend mode.

Active Inactive Suspend Monitor’s high voltage section is turned off and CRT heater



Inactive Inactive Off Monitor’s high voltage section and heater circuitry is turned off.





E.6 CONNECTORS

There are two connectors associated with the graphics subsystem; the display/monitor connector and the Feature connector.


The DB-15 disply/monitor connector is provided for connection of a compatible RGB/analog monitor. The Feature connector allows the attachment of an optional card such as a video tuner.

E.6.1 MONITOR CONNECTOR

5 4 3 2 1

15

10

14

9

13

8

12

7

11

6

Figure E-3. VGA Monitor Connector, (Female DB-15, as viewed from rear).

Table E-3. DB-15 Monitor Connector Pinout

Table E-3.


Pin Signal

1 R

2 G

3 B

4 NC

5 GND

6 R GND

7 G GND

Red Analog

Green Analog

Not Connected

Ground

Red Analog Ground

Green Analog Ground

9 PWR

10 GND

11 NC

12 SDA

13 HSync

14 VSync

15 SCL

8

NOTES:



+5 VDC (fused) [1]

Ground

Not Connected

DDC2-B Data

Vertical Sync

DDC2-B Clock

--



E-5






Appendix F

COMPAQ/Matrox Millennium G450

AGP GRAPHICS CARD

F.

Appendix F Compaq/Matrox Millennium G450 AGP Graphics

Card

F.1 INTRODUCTION

This appendix describes the Compaq/Matrox Millennium G450 AGP Graphics Card used in the standard configuration on some models and also available as an option. This card (layout shown in the following figure) installs in a system’s AGP slot. The Compaq/Matrox Millennium G450 graphics card (SP# 203626-001) provides high 2D performance and entry-level 3D capabilities.

This card features a dual-RAMDAC design for driving two analog displays.

Feature Connector

RGB Monitor

Connectors

SD

RAM

SD

RAM

MGA

Dual-RAMDAC

Controller

SDRAM

SDRAM

Figure F-1. Compaq/Matrox Millennium G450 AGP Graphics Card Layout (PCA# 202901-001)


♦ Functional description (F.2)

♦ Display modes (F.3) page F-3

♦ Software support information (F.4) page F-4

♦ Monitor power management (F.5)

♦ Connectors page F-2 page F-4


Original - November 2000

F-1

Appendix H Compaq/Matrox Millennium G450 AGP Graphics Card

ROM

The Matrox Millennium G450-SD Graphics Card provides high performance 2D and 3D display imaging. The card’s AGP design provides an economical approach to 3D processing by offloading 3D effects such as texturing, z-buffering and alpha blending to the system memory while

16 or 32 megabytes of on-board SDRAM stores the main display image.

Card

Edge

Connector

AGP

Bus

BIOS

AGP 4X

I/F

MGA Graphics Controller

2D/VGA

Engine

Video

Scalar

3D Array

Engine

Memory

I/F

350-MHz

RAMDAC

CRT

Controller

200-MHz

RAMDAC

128-bit

166-MHz

Data Bus

RGB

H/VSync

H/VSync

RGB

16 / 32 MB

SDRAM

Frame Buffer

Analog

Monitor

Connector 1

Analog

Monitor

Connector 2

Figure F-2. Matrox Millennium G450 Graphics Card Block diagram

The Matrox Millennium G450 Graphics Card includes the following features:



♦ 2D drawing engine with:

• 128-bit BitBLTs, rectangle/polygon fills, line draws

• Hardware cursor

• 8-/16-/32-bpp mode acceleration

♦ Dual-head features:

• Two analog monitor (RGB) ports

• DVD max mode

• DualHead zoom mode

• DualHead clone mode

• DualHead TV output mode

♦ 3D accelerator with:

• Hardware transform and lighting


• Specular lighting diffuse, flat and Gouraud shading

• 16-/24-bit Z-buffering

♦ 360-MHz primary RAMDAC, 200-MHz secondary RAMDAC

♦ VESA compliancy:

• Dual DDC2B monitor support

• VIP 2.0 interface

• DPMS, EPA Energy Star, and ACPI-compliant power management

F-2 Compaq Personal Computers



The graphics display modes supported by the Matrox Millennium G450 Graphics are listed in

Table F-1.

Table F-1. Matrox Millennium G450 Graphics Display Modes

Table F-1.

Matrox Millennium G450 Graphics Display Modes

Color Depth

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

16.7M

256

65K

Bits per pixel

24

32

8

16

24

32

8

16

24

32

8

16

24

32

8

16

24

32

8

16

24

32

8

16

24

8

16

24

8

16

8

16

24

32

8

16

24

8

16

Resolution

640 x 480

640 x 480

640 x 480

640 x 480

800 x 600

800 x 600

800 x 600

800 x 600

1024 x 768

1024 x 768

1024 x 768

1024 x 768

1152 x 864

1152 x 864

1152 x 864

1152 x 864

1280 x 960

1280 x 960

1280 x 960

1280 x 960

1280 x 1024

1280 x 1024

1280 x 1024

1280 x 1024

1600 x 1200

1600 x 1200

1600 x 1200

1600 x 1200

1800 x 1440

1800 x 1440

1800 x 1440

1856 x 1392

1856 x 1392

1856 x 1392

1920 x 1440

1920 x 1440

1920 x 1440

2048 x 768

2048 x 768

NOTE:

[1] Value reflects hardware capabilities only. May be restricted by operating system.

Max. Vertical

Refresh Freq. [1]

75 Hz

75 Hz

75 Hz

75 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

85 Hz

75 Hz

75 Hz

Supporting

RAMDAC

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary, Secondary

Primary

Primary

Primary

Primary

Primary

Primary

Primary

Primary

Primary

Primary

Primary



F-3


F.4 SOFTWARE SUPPORT INFORMATION

The Matrox Millennium G450 graphics card is fully compatible with software written for legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes.


♦ Windows 2000

♦ Windows NT 4.0

♦ Autodesk AutoCAD R14 and 2000

♦ Kintex 3D Studio Max

♦ 2D GDI

♦ MS DirectDraw DX6-7, ActiveX, DirectX, Direct3D,

♦ OpenGL 1.1 and 1.2

This controller provides monitor power control for monitors that conform to the VESA display power management signaling (DPMS) protocol. This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition. Table F-2 lists the monitor power conditions.

Table F-2. Monitor Power Management Conditions

Table F-2.



Active Active On Monitor is completely powered up. If activated, the inactivity counter counts down during system inactivity and if allowed to tiemout, generates an SMI to initiate the Suspend mode.


(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode inactivity timer counts down from the preset value and if allowed to timeout, another SMI is generated and serviced, resulting in

Inactive Inactive Off the monitor being placed into the Off mode. Wake up from


Monitor’s high voltage section and heater circuitry is turned off.


Power consumption of this card on the PCI bus is listed in the following table:

Voltage

VddQ

(1.5 VDC)

Vcc3

(3.3 VDC)

Maximum Current Drain .05 A

Maximum Power Consumption 0.75 W

Total maximum power consumption for this card is 9.1 watts.

2.4 A

7.99 W

Vcc5

(5.0 VDC)

0.2 A

1.04 W




F.6 CONNECTORS

There are three connectors associated with the graphics subsystem; two display/monitor connectors and the Feature connector.


F.6.1 MONITOR CONNECTOR

The display/monitor connector is provided for connection of a compatible RGB/analog monitor.

5 4 3 2 1

10 9 8 7 6

15 14 13 12 11

Figure F-3. VGA Monitor Connector, (One of two female DB-15, as viewed from rear).

Table F-3. DB-15 Monitor Connector Pinout

Table F-3.


Pin Signal

1 R

2 G

3 B

4 NC

5 GND

6 R GND

Red Analog

Green Analog

Not Connected

Ground

Red Analog Ground

9 PWR

10 GND

11 NC

12 SDA

13 HSync

14 VSync

7 G GND Green Analog Ground 15 SCL

8

NOTES:



+5 VDC (fused) [1]

Ground

Not Connected

DDC2-B Data

Vertical Sync

DDC2-B Clock

--



F-5


F.6.2 VIDEO FEATURE CONNECTOR

The Video Feature connector allows a video peripheral such as a TV tuner card to provide video input to the graphics card. This interface is compliant with VESA VIP specification 1.1.

2 / Y1

26 / Y13

1 / Z1 25 / Z13

Figure F-4. Feature Connector (26-Pin Header)

Pin

1 / Z1

3 / Z2

5 / Z3

7 / Z4

9 / Z5

11 / Z6

13 / Z7

15 / Z8

17 / Z9

19 / Z10

21 / Z11

23 / Z12

25 / Z13

Table F–4. Video In Connector Pinout

Table F-4.

Video In Connector Pinout

Signal Description Pin Signal

GND

GND

GND

HAD1

HAD0

HCTL

SCL

GND

GND

GND

GND

VIRQ

SDA

Ground

Ground

Ground

External Sync

External Clock

Serial Clock

Ground

Ground

Ground

Ground

Serial Data

2 / Y1

4 / Y2

6 / Y3

8 / Y4

10 / Y5

12 / Y6

14 / Y7

16 / Y8

18 / Y9

20 / Y10

22 / Y11

24 / Y12

26 / Y13

P0

P1

P2

P3

P4

P5

P6

P7

DCLK

NC

NC

--

GND

Pixel Data 0

Pixel Data 1

Pixel Data 2

Pixel Data 3

Pixel Data 4

Pixel Data 5

Pixel Data 6

Pixel Data 7

Pixel Data Clock

Not Connected

Not Connected

Key

Ground




Appendix G

COMPAQ/ADAPTEC 29160N SCSI HOST ADAPTER

G.

Appendix G Compaq/Adaptec SCSI Host Adapter

G.1 INTRODUCTION

The Compaq/Adaptec 29160N SCSI Host Adapter (Compaq SP# 158364-001) is a PCI peripheral that provides high performance interfacing with compatible SCSI peripherals, typically SCSI hard drives. The card installs in a PCI slot and supports full bus mastering capability.


♦ Functional description (G.2) page G-2

♦ SCSI adapter programming (G.3)

♦ Specifications page G-3

page

♦ SCSI connectors (G.5) page G-4

External

Internal

Wide-Ultra SCSI Connector

Internal

Ultra SCSI Connector

Ultra

AIC7892 SCSI Connector

Figure G–1. Compaq/Adaptec 29160N SCSI Host Adapter Card Layout (PCA# 157342-001)


Original - December 2000

G-1

Appendix G Compaq/Adaptec 29160N SCSI Host Adapter

A block diagram of the SCSI Adapter is shown in Figure L-2. The adapter’s architecture is based on the AIC-7892 SCSI controller working off the 32-bit, 66-/33-MHz PCI bus. Providing full bus mastering capability, the adapter supports data transfers up to 266 MB/s using the burst mode rate on a 66-MHz 32-bit PCI bus. The AIC-7892 controller is an Ultra160 controller with an on-board

20-MIPS SCSI sequencer that can process SCSI commands without intervention from the host microprocessor. The sequencer uses micro-code that is downloaded from the host during initialization. Single-ended SCSI drivers are built into the controller and a 1-K data FIFO and an internal 4-KB SRAM memory. An LED is provided to indicate SCSI bus activity.

The AIC7892 provides a memory interface that is used by the Serial EEPROM and the BIOS

ROM. The serial EEPROM stores non-volatile configuration data and the BIOS ROM (which is a flash ROM) contains additional configuration data and SCSI functions. The programmable array logic (PAL) controls the Serial EEPROM-to-AIC7892 interface.

PAL

Chip

SCSI

Activity

Serial

EEPROM

PCI

Slot

BIOS

ROM

PCI Bus

AIC7892

SCSI

Controller

40-MHz

Clock

Active Ultra160

SE Term.

AIC3860

Transceiver

Chip

Int. SCSI Connector (SE)

Ext. SCSI Connector (SE)

Int. SCSI Connector (SE/LVD)

Active Ultra160

SE/LVD Term.

Figure G–2. Compaq/Adaptec Ultra SCSI Adapter Card Block Diagram

The AIC7892 controller supports dual-mode low-voltage differential (LVD) SCSI I/O up to the

Ultra160 data rate of 160 Mbytes. Both single-ended (SE) and LVD devices can co-exist on the

SCSI bus, although operation will default to the SE mode. In SE mode, transfer rates are limited to the speed of the slower device. High-voltage differential (HVD) devices are supported for rates up to Ultra speeds.

The AIC7892 also supports cyclic redundancy check (CRC) codes, an improvement over parity checking used earlier.

G-2 Compaq Personal Computers



G.3 SCSI ADAPTER PROGRAMMING

G.3.1 SCSI ADAPTER CONFIGURATION

The Adaptec SCSI Host Adapter Card is a PCI device and configured using PCI protocol and PCI

Configuration Space registers (PCI addresses 00h-FFh) as discussed in Chapter 4 of this guide.

Configuration is accomplished by BIOS during POST and re-configurable with software. The vender ID and device ID for the adapter are as follows:

Vender ID (PCI config. addr. 00h): 9005h

Device ID (PCI config, addr. 02h): 0080h

G.3.2 SCSI ADAPTER CONTROL

Control of the SCSI host adapter is affected through I/O mapped registers mapped as listed in

Table G-1.

Table G–1. SCSI Host Adapter Card Control Register Mapping

I/O Addr. n00h-n1Fh

Table G-1.

Ultra SCSI Host Adapter Card

Control Register Mapping

Function

SCSI Register Array n60h-n7Fh Phase Engine (Sequencer) n = prefix address supplied by the BASEADR0 PCI Config. Reg.

G.4 SPECIFICATIONS

The operating specifications are listed in Table G-2.

Table G–2. Ultra SCSI Host Adapter Card Specifications

Table G-2.

Ultra SCSI Host Adapter Card Specifications

Operating Voltage +5 VDC

Maximum Current Draw

Operating Temperature

2 A

32

°F (0°C) to 131°F (55°C)



G-3


This SCSI card provides two internal header-type connectors (one 50-pin, one 68-pin) and one external D-type connector (50-pin).

G.5.1 EXTERNAL 50-PIN ULTRA SCSI CONNECTOR

The card provides one external 50-pin D-type Ultra SCSI connector. External cabling should meet

T-10 SPI-2 standards (50-conductor, round shielded).

Pin 1

Figure G–3. External Ultra SCSI Connector (50-pin)

Table G–3. External 50-Pin Ultra SCSI Connector Pinout

Table G-3.

External Ultra SCSI Connector Pinout

5

6

7

1

2

3

4

8

9

GND

GND

GND

GND

GND

GND

GND

GND

GND

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

26

27

28

29

30

31

32

33

34

DB0-

DB1-

DB2-

DB3-

DB4-

DB5-

DB6-

DB7-

DBP

Data Bit 0

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Data Bus Pulse

23 GND Ground


48


C-/D Control/Data Transfer Indicator


G.5.2 INTERNAL 50-PIN ULTRA SCSI CONNECTOR

The card provides one internal 50-pin header-type Ultra SCSI connector. Internal cabling to this connector should consists of an unshielded connector with a 50-conductor flat cable as specified in ANSI standard X3T9.2/375R.

Pin 49

Pin 50

Pin 1

Pin 2

Figure G–4. Internal 50-Pin Ultra SCSI Connector

Table G–4. Internal 50-Pin Ultra SCSI Connector Pinout

Table G-4.

Internal 50-Pin Ultra SCSI Connector Pinout

1

3

5

7

9

11

13

15

17

GND

GND

GND

GND

GND

GND

GND

GND

GND

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

2

4

6

8

10

12

14

16

18

DB0-

DB1-

DB2-

DB3-

DB4-

DB5-

DB6-

DB7-

DBP

Data Bit 0

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Data Bus Pulse

45 GND Ground 46 C-/D Control/Data Transfer Indicator



G-5


G.5.3 INTERNAL 68-PIN ULTRA160 SCSI CONNECTOR

The card provides one internal 68-pin Ultra160 SCSI connector. This connection is designed for a

68-conductor unshielded Twist ‘N Flat cable as specified in the T-10 SPI-2 standard.

Pin 34 Pin 1

Pin 68 Pin 35

Figure G–5. Ultra 160 SCSI Connector (68-pin header type)

Table G–5. Ultra160 SCSI Connector Pinout

Table G-5.

Ultra160 SCSI Connector Pinout

8

9

10

11

12

13

14

5

6

7

1

2

3

4

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

42

43

44

45

46

47

48

35

36

37

38

39

40

41

DB12

DB13

DB14

DB15

DBP-

DB0-

DB1-

DB2-

DB3-

DB4-

DB5-

DB6-

DB7-

DBP-

Data Bit 12

Data Bit 13

Data Bit 14

Data Bit 15

Data Bus Parity

Data Bit 0

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Data Bus Parity

28

31

32

33

34

GND Ground

GND

GND

GND

GND

Ground

Ground

Ground

Ground

62

65

66

67

68

C-/D Control/Data Transfer Indicator

DB8-

DB9-

DB10-

DB11-

Data Bit 8

Data Bit 9

Data Bit 10

Data Bit 11




Appendix H

COMPAQ/Matrox G200 MMS Quad-Head

PCI GRAPHICS CARD

H.

Appendix H Compaq/Matrox G200 MMS Quad-Head PCI

Graphics Card

H.1 INTRODUCTION

This appendix describes the Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card used in the standard configuration on some models and also available as an option. This card (layout shown in the following figure) installs in a system’s PCI slot. The Compaq/Matrox G200 MMS graphics card provides high performance multi-monitor imaging well suited for business environments where displaying large amounts of 2D data is needed. This card includes four separate G200 graphics controllers for supporting up to two pairs of analog or digital displays.

This card is available in both analog and digital kit forms. The analog kit (SPN 159513-B21) includes adapter cables for connecting analog (RGB) monitors while the digital kit (SPN 179597-

B21) includes adapter cables for connecting DVI-compliant digital displays. Either kit can be adapted to support analog or digital displays by ordering the appropriate adapter cable.

Adapter Cable

Adapter

Connector

For Monitors # 3 & 4

Adapter

Connector

For Monitors # 1 & 2

Figure H-1. Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card Layout


♦ Functional description (F.2)

♦ Display modes (F.3) page F-3

♦ Software support information (F.4) page F-4

♦ Monitor power management (F.5)

♦ Connectors page F-2 page F-4


Original - March 2002

H-1

Appendix H Compaq/Matrox G200 MMS Quad-Head PCI Graphics Card

Card

Edge

Connector

The Matrox G200 MMS Quad-Head PCI Graphics Card provides high performance, multimonitor 2D imaging. With four G200 graphics controllers each supported with an 8-MB SGRAM frame buffer, the card can provide, with appropriate OS, separate images on up to four displays.

Each controller can drive either an analog RGB monitor or a digital video interface-compliant monitor (but not both).

8 MB SGRAM

Frame Buffer

PCI

Bus

BIOS

ROM

Intel

21152

PCI Bridge

Controller

MGA G200

Graphics

Controller #4

MGA G200

Graphics

Controller #3

8 MB SGRAM

Frame Buffer

8 MB SGRAM

Frame Buffer

MGA G200

Graphics

Controller #2

MGA G200

Graphics

Controller #1

8 MB SGRAM

Frame Buffer

RGB

DVI

RGB

DVI

RGB

DVI

RGB

DVI

Adapter

Connector

For Monitors

#3 & 4

Adapter

Figure H-2. Matrox G200 MMS Quad-Head PCI Graphics Card Block diagram

Connector

For Monitors

#1 & 2

H-2 Compaq Personal Computers



Card

Edge

Connector

PCI

Bus

The card includes four MGA G200 graphics controllers. Each controller includes a VGA controller core, 2D and 3D engines, and a 250-MHz RAMDAC. Each controller can drive either an analog RGB monitor or a DVI-compliant digital monitor.

PCI

I/F

MGA G200 Graphics Controller

Video

Scalar

2D/VGA

Engine

Memory

I/F

3D Array

Engine

250-MHz

RAMDAC

CRT

Controller

DVI

Controller

Figure H-3. MGA G200 Graphics Controller Architecture

128-bit

Data Bus

RGB

H/VSync

DVI Data

Analog

Monitor

Digital

Monitor

The MGA G200 graphics controller includes the following features:

♦ 64-bit SGRAM interface

♦ PCI bus 2.1 compliant with bus-mastering support

♦ 2D drawing engine with:

• 128-bit BitBLTs, rectangle/polygon fills, line draws

• Hardware cursor

• 8-/16-/32-bpp mode acceleration

♦ Analog (RGB) or DVI monitor support

♦ 3D accelerator with:

• Vertex fog


• Specular lighting diffuse, flat and Gouraud shading

• Full-scene anti-aliasing

♦ 250-MHz RAMDAC

♦ VESA compliancy:

• Dual DDC2B monitor support

• VIP 2.0 interface

• DPMS, EPA Energy Star, and ACPI-compliant power management



H-3


The graphics display modes supported by each monitor port on the Matrox G200 MMS Graphics card are listed in Table H-1.

Table H-1. Matrox G200 MMS Graphics Display Modes

Table H-1.

Matrox G200 MMS Graphics Controller Display Modes

Resolution

640 x 480

640 x 480

640 x 480

640 x 480

800 x 600

800 x 600

800 x 600

800 x 600

1024 x 768

1024 x 768

1024 x 768

1024 x 768

1152 x 864

1152 x 864

1152 x 864

1152 x 864

1280 x 720

1280 x 720

1280 x 720

1280 x 720

1280 x 1024

1280 x 1024

1280 x 1024

1280 x 1024

1600 x 1024

1600 x 1024

1600 x 1024

1600 x 1024

1600 x 1200

1600 x 1200

1600 x 1200

1800 x 1440

1800 x 1440

1920 x 1080

1920 x 1080

1920 x 1080

1920 x 1200

1920 x 1200

NOTE:

Bits per pixel

16

24

32

8

16

24

32

8

16

24

32

8

16

24

32

8

16

24

8

16

24

32

8

16

24

8

16

16

24

8

16

8

32

8

16

24

32

8

Color Depth

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

16.7M

256

65K

16.7M

256

65K

256

65K

16.7M

256

65K

Max. Vertical

Refresh Freq. [1]

200 Hz

200 Hz

200 Hz

200 Hz

200 Hz

200 Hz

200 Hz

200 Hz

140 Hz

140 Hz

140 Hz

140 Hz

120 Hz

120 Hz

120 Hz

120 Hz

100 Hz

100 Hz

100 Hz

100 Hz

100 Hz

100 Hz

100 Hz

100 Hz

100 Hz

100 Hz

100 Hz

100 Hz

90 Hz

90 Hz

90 Hz

70 Hz

70 Hz

80 Hz

80 Hz

80 Hz

76 Hz

76 Hz

Monitor

Support

[1] Value reflects hardware capabilities only. May be restricted to lower frequency by

operating system.

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog or Digital

Analog only

Analog only

Analog only

Analog only

Analog only

Analog only

Analog only

Analog only

Analog only

Analog only

Analog only

Analog only

Analog only

Analog only




H.4.1 SINGLE-CARD CONFIGURATION

The Matrox G200 MMS Quad-Head PCI Graphics Card supports multiple monitors through the use of adapter cables. The graphics card as ordered from Compaq comes with either an analog adapter cable or a digital adapter cable, depending on order number. The card supports the following display configurations:

♦ Up to four analog (RGB) monitors

♦ Up to four digital (DVI-compliant) monitors

♦ One or two analog monitors and one or two digital monitors (NOTE: An analog/digital "mix" requires ordering the appropriate other cable type (analog or digital)).

H.4.2 MULTI-CARD CONFIGURATION WITH WINDOWS NT 4.0

Multiple Matrox G200 MMS Quad-Head PCI Graphics Cards can be installed in a single system to increase the amount of video real estate. Up to 16 monitors can be driven by a system using four cards and running Windows NT 4.0.

H.5 SOFTWARE SUPPORT INFORMATION

The Matrox G200 MMS graphics card is fully compatible with software written for legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes.

Drivers are provided with or available for the card to provide extended mode support for the current operating systems such as:

♦ Windows 2000

♦ Windows 98

♦ Windows NT 4.0



H-5


This controller provides monitor power control for monitors that conform to the VESA display power management signaling (DPMS) protocol. This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition. Table H-2 lists the monitor power conditions.

Table H-2. Monitor Power Management Conditions

Table H-2.



Active Active On Monitor is completely powered up. If activated, the inactivity counter counts down during system inactivity and if allowed to tiemout, generates an SMI to initiate the Suspend mode.




Inactive Inactive Off Monitor’s high voltage section and heater circuitry is turned off.





H.7 CONNECTORS

There are four types of connectors associated with the graphics card; an analog monitor connector, digital monitor connector, adapter cable connectors and the card edge connector.

NOTE: The graphic card’s edge connector mates with a PCI slot connector on the system board. This interface is described in chapter 4 of this guide.

H.7.1 ADAPTER CABLE CONNECTOR

A display or monitor cannot be attached directly to the graphics card. The graphics card includes two connectors for attaching adapter cables that are used to attach the monitor(s).

P16

P15 P1

P30

P45

P1

P31

P60

Figure H-4. Adapter Cable Connector, (One of two as viewed from rear).

Table H–3. Adapter Cable Connector Pinout

Pin Description

14

15

16

17

18

19

20

5

6

7

1

2

3

4

Ground

Analog Red

Analog Blue

Ground

5 VDC

SCL (DDC)

SDA (DDC)

8 Ground

9 SDA (DDC)

10 SCL (DDC)

11

12

13

5 VDC

Ground

Analog Blue

Analog Red

Ground

TMDS Data 0 +

TMDS Data 0 -

TMDS Data 2 +

TMDS Data 2 -

Not used

Monitor #1 or #3

Table H-3.

Adapter Cable Connector Pinout

Pin Description

21

22

Not used

Not used

31

32

33

34

35

36

37

24

25

26

27

28

29

30

Not used

Not used

Not used

TMDS Data 2 -

TMDS Data 2 +

TMDS Data 0 -

TMDS Data 0 +

TMDS Data 1 +

TMDS Data 1 -

TMDS Clock Data +

TMDS Clock Data -

Not used

Hot plug detect

Not used

48

49

50

51

52

41

42

43

44

45

46

47

39

40

Not used

Hot plug detect

54

55

56

57

58

59

60

Monitor #2 or #4

Not used

TMDS Clock Data -

TMDS Cllock Data +

TMDS Data 1 -

TMDS Data 1+

Ground

Analog Green

Not used

Ground

HSYNC

VSYNC

Ground

Ground

VSYNC

HSYNC

Ground

Not used

Analog Green

Ground



H-7


H.7.2 ANALOG MONITOR CONNECTOR

The analog adapter cable supplied with the analog version of the graphics card kit provides two

DB-15 VGA monitor connectors.

5 4 3 2 1

10 9 8 7 6

15 14 13 12 11

Figure H-5. Analog (VGA) Monitor Connector (One of two female DB-15 connectors).

Table H-4. DB-15 Monitor Connector Pinout

Table H-4.


Pin Signal

1 R

2 G

3 B

4 NC

5 GND

6 R GND

Red Analog

Green Analog

Not Connected

Ground

Red Analog Ground

9 PWR

10 GND

11 NC

12 SDA

13 HSync

14 VSync

7 G GND Green Analog Ground 15 SCL

8

NOTES:



+5 VDC (fused) [1]

Ground

Not Connected

DDC2-B Data

Vertical Sync

DDC2-B Clock

--




H.7.3 DIGITAL MONITOR CONNECTOR

The digital adapter cable supplied with the digital version of the graphics card kit provides two

DVI-D monitor connectors.

P9

P1

P8

P16

P17

P24

Figure H-6. DVI-D Monitor Connector (24-Pin Connector)

Table H–5. Video In Connector Pinout

Table H-4.

DVI-D Connector Pinout

Pin Description Pin

6

7

8

9

10

11

12

1

2

3

4

5

TMDS Data 2 -

TMDS Data 2 +

TMDS Data 2 & 4 Shield

TMDS Data 4 -

TMDS Data 4 +

DDV Clock

DDC Data

Not used

TMDS Data 1 -

TMDS data 1 +


TMDS Data 3 -

18

19

20

21

22

23

24

13

14

15

16

17

TMDS Data 3 +

5 VDC

Ground

Hot plug detect

TMDS Data 0 -

TMDS Data 0 +


TMDS Data 5 -

TMDS Data 5 +

TMDS Clock Shield

TMDS Clock +

TMDS Clock -



H-9





INDEX

I.

3D effects, D-2, E-2, F-2, H-2 abbreviations, 1-4

AC97 link bus, 5-28

Accelerated Graphics Port (AGP), 4-10

ACPI, 5-34 acronyms, 1-4

AGP, 4-10

Alert-On-LAN, 5-33

AOL, 5-33

AOL requirements, 5-33, 5-38

APIC, 4-16

APM, 5-34

APM BIOS support, 7-19 arbitration, PCI bus master, 4-6

ASCII character set, B-1 audio, 5-26 audio controller (AC97), 5-28 audio subsystem, 2-18 backplane, 2-7 battery replacement, 4-23

BIOS, ROM, 7-1 blinking LED, 6-4 boot block ROM, 7-2 cable lock, 4-26

CAS latency, 3-5

Celeron processor, 2-14 chassis fan, 4-29 chipsets, 2-15

Client Management, 7-12

CMOS, 4-23

CMOS, archive, 4-24

CMOS, clearing, 4-23

CMOS, restoring, 4-24 codec, audio, 5-29

Configuration Cycle, 4-4 configuration cycle (PCI), 4-4 configuration memory, 4-23 configuration space (PCI), 4-5

Connector

AGP bus, 4-14

Audio, CD, 5-27 audio, headphones out, 5-26 audio, line in, 5-26 audio, line out, 5-26

Audio, Mic In, 5-26

Audio, Speaker, 5-27 diskette drive interface, 5-7 display (VGA monitor), D-5, E-5, F-5, H-8

IDE interface, 5-3 keyboard/pointing device interface, 5-21

Network RJ-45, 5-36 parallel interface, 5-15

PCI bus, 4-9 serial interface (RS-232), 5-8

Ultra SCSI (50-pin D-type), G-4

Ultra SCSI (50-pin header type), G-5

Universal Serial Bus interface, 5-25

VGA pass-through (feature), F-6, H-9

Wide Ultra SCSI (68-pin header type), G-6 cooling, 4-28 core voltage, 6-8

DIMM detection, 7-5

DIMM support ,

7-15

Direct Rambus, 3-5 diskette drive interface, 5-4 display modes, D-3 display modes, Matrox Millennium G450, F-3,

H-4, H-5 display modes, NVIDIA Quadro2 EX/MXR, E-3

DMA, 4-19

DMI, 7-16 drive fault prediction, 7-15 dual-head support, F-2, H-3

East Access keys, C-10

Easy Access keyboards, C-7 effects, 3D, D-2, E-2, F-2, H-2

EIDE interface, 5-1

Enhanced Parallel Port (EPP), 5-12 events, wake up, 6-4 expansion card cage, 2-7

Extended Capabilities Port (ECP), 5-12 fan boxed processor, 4-29 chassis, 4-29 power supply, 4-29 feature connector, F-6, H-9 features, standard, 2-2 flash ROM, 7-2 graphics card, Matrox G200 MMS Quad-Head

PCI, H-1 graphics card, Matrox Millennium G450, F-1 graphics card, NVIDIA Quadro2 EX/MXR, E-1

graphics card, NVIDIA Vanta LT, D-1 graphics subsystem, 2-17 graphics, 3D, D-2, E-2, F-2, H-2

Hard drive activity indicator, 4-32

Hub link bus, 4-7

I/O controller (LPC47B34x), 4-31

I/O map, 4-30

IDE interface, 5-1

IDSEL, 4-4 index addressing, 1-3 interface audio, 2-18, 5-26 diskette drive, 5-4

IDE, 5-1 keyboard/pointing device, 5-16 parallel, 2-16, 5-11 serial, 2-16, 5-8

USB, 2-16, 5-22 interrupts maskable (IRQn), 4-15 nonmaskable (NMI, SMI), 4-17 interrupts, PCI, 4-7 key (keyboard) functions, C-8 keyboard, C-1 keyboard (micro)processor, C-2 keyboard layouts, C-5 keyboard, USB, C-4 keyboards, Easy Access, C-7 keys, Easy Access, C-10 keys, Windows, C-9

LED, 5-32

LED indications, 4-27, 6-4

LED, HD, 4-32

LED, Power, 4-32 low voltages, 6-8

LPC bus, 4-7

LPC47B34x I/O controller, 4-31

Magic Packet, 5-34 mass storage, 2-16 memory detection, 7-5 memory map, 3-7 memory, system (RAM), 2-16 microphone, 5-26 monitor power control, D-4, E-4, F-4, H-6 mouse interface, 5-18 network interface controller, 5-32 network support, 5-32

NIC, 5-32

NIC upgrading, 5-37 notational conventions, 1-2, 1-3

NUM lock, 3-5 option ROM, 4-7 options, 2-3 parallel interface, 2-16, 5-11 password, clearing, 4-23 password, power-on, 4-25

PCI bus, 2-16, 4-2

PCI Configuration Space, 4-5

PCI interrupts, 4-7

Pentium 4 processor, 3-2

Pentium II, 2-15

Pentium II processor, 2-14

PHY, 5-32 pinouts, header (connector), 6-11

Plug ’n Play, 2-2, 2-16, 7-15

Plug 'n Play BIOS function, 7-15 power button, 6-3

Power Button Override, 4-24 power consumption, graphics card, D-4 power distribution, 6-6

Power indicator, 4-32 power LED, 6-4 power management

ACPI, 4-27 network interface controller (NIC), 5-34

PCI, 4-7 power management BIOS function, 7-17 power states, system, 6-5 power supply, 6-1 power supply assembly, 6-2 power-on password, 4-25 processor upgrading, 3-4 processor, Celeron, 2-14 processor, Pentium 4, 3-2 processor, Pentium II, 2-14

RAM, 2-16

RDRAM, 3-5 reference sources, 1-2 remote flashing, 7-2 remote wake up, 5-34 restoring CMOS, 4-24

RIMM, 3-5

ROM BIOS, 7-1

ROM flashing, 7-2

ROM, option, 4-7

RS-232, 5-8

RTC, 4-23 scan codes (keyboard), C-11

SCSI Host card, Adaptec 29160N, G-1

SDRAM, D-2, H-3 security functions, 4-25 security, chassis, 4-26 security, interface, 4-26 sensor, thermal, 4-28 serial interface, 2-16, 5-8 sideband addressing, 4-11 signal distribution, 6-9, 6-11

Smart Cover Lock, 4-26

Smart Cover Sensor, 4-26

SMBIOS, 7-16

SMI, 4-18 speaker, 5-26 specifications electrical, 2-18 environmental, 2-18 physical, 2-19 power supply, 6-9, 6-10, 6-11

Specifications

8x CD-ROM Drive, 2-20

Audio subsystem, 5-31

Diskette Drive, 2-19

SCSI Host Adapter, G-3 specifications, system, 2-18

SSE2, 3-2 status, LED, 4-27 system board, 2-10, 2-11 system ID, 7-6, 7-14 system memory, 2-16 system resources, 4-15 system ROM, 7-1 system status indications, 4-27

TAFI, 4-29 temperature status, 7-15 thermal sensing, 4-28 typematic, C-8

UART, 5-8

Universal Serial Bus (USB) interface, 5-22 upgrading, BIOS, 7-2 upgrading, NIC, 5-37 upgrading, processor, 3-4

USB interface, 5-22

USB keyboard, C-4

USB legacy support, 7-23

USB ports, 2-16

VESA connector, F-6, H-7, H-9 voltage, core, 6-8 wake up (power), 6-4 wake up events, 6-4 wake up, remote, 5-34

Wake-On-LAN, 5-33, 6-4

Windows keys, C-9

WOL, 5-33, 6-4


Compaq Evo D500 - Convertible Minitower Reference Guide

Technical Reference Guide

For

Compaq Evo D300/D500 Personal Computers and

W4000 Workstations

Covers Small Form Factor, Desktop, and Configurable Minitower Models

Featuring the

Evo D300/D500 Personal Computers and

W4000 Workstations

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

Chapter 1

INTRODUCTION

Chapter 1 INTRODUCTION

Chapter 2

SYSTEM OVERVIEW

!

Chapter 3

PROCESSOR/

MEMORY SUBSYSTEM

!

Chapter 4

SYSTEM SUPPORT

AGP 1X Transfers

AGP 2X Transfers

A GP 4X Tra nsfers

S mart Cover Sensor

Smart Cover Lock

Chapter 5

INPUT/OUTPUT INTERFACES

Chapter 6

POWER and SIGNAL

DISTRIBUTION

Chapter 6 POWER SUPPLY AND DISTRIBUTION

Chapter 7

BIOS ROM

Chapter 8 BIOS ROM

Appendix A

ERROR MESSAGES AND CODES

Appendix B

ASCII CHARACTER SET

Appendix C

KEYBOARD

Appendix C KEYBOARD

Appendix D

COMPAQ/NVIDIA VANTA LT

AGP GRAPHICS CARD

Appendix E

COMPAQ/NVIDIA QUADRO2 EX/MXR

AGP GRAPHICS CARDS

Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics

Cards

Appendix F

COMPAQ/Matrox Millennium G450

AGP GRAPHICS CARD

Appendix F Compaq/Matrox Millennium G450 AGP Graphics

Card

Appendix G

COMPAQ/ADAPTEC 29160N SCSI HOST ADAPTER

Appendix G Compaq/Adaptec SCSI Host Adapter

Appendix H

COMPAQ/Matrox G200 MMS Quad-Head

PCI GRAPHICS CARD

Appendix H Compaq/Matrox G200 MMS Quad-Head PCI

Graphics Card

INDEX

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