An Online Phase Margin Monitor for Digitally Controlled Switched-Mode Power Supplies Jeff Morroni, Regan Zane and Dragan Maksimović Colorado Power Electronics Center University of Colorado at Boulder, USA Email: {morroni, zane, maksimov}@colorado.edu suited for one-time frequency response identification, e.g. upon start up, or at other times when the system is in steady state. In [6-11], frequency response information and tuning of compensator parameters is performed based on purposely induced limit-cycle oscillations in a sequence of steps, assuming steady-state operation. In this paper, inspired by the analog injection technique [1], a method is proposed to measure the crossover frequency and phase margin in a digitally controlled power supply online, i.e., during normal system operation. The proposed approach does not require opening the feedback loop and is capable of continuously updating the measured crossover frequency and phase margin outputs in the presence of load transients or other system disturbances. Applications of the technique include fast design time verifications, online dynamic performance monitoring of power supplies in power distribution systems (such as servers or spacecrafts [12-14]), as well as adaptive online tuning of control parameters [15]. Section II details the proposed approach. Section III presents experimental results. Conclusions are given in Section IV. Abstract — This paper presents a practical injection-based method for continuous monitoring of the crossover frequency and phase margin in digitally controlled switched-mode power supplies (SMPS). The proposed approach is based on Middlebrook’s loop-gain measurement technique [1], adapted to digital controller implementation. A digital square-wave signal is injected in the loop, and the injection signal frequency is adjusted while monitoring loop signals to obtain the system crossover frequency and phase margin online, i.e., during normal SMPS operation. The approach does not require open loop or steady-state SMPS operation and is capable of convergence in the presence of load transients or other disturbances. Experimental results are presented for various power stage configurations demonstrating close matches between monitored and expected crossover frequencies and phase margins. I. INTRODUCTION Switching power converters are nonlinear systems with dynamic responses that depend on the operating point. Typically, based on averaged small-signal models, switched-mode power supply (SMPS) feedback loops are designed conservatively so that stability margins and closed-loop regulation performance are maintained over expected ranges of operating conditions and tolerances in power stage parameters. At design time, it is a common practice to measure the system loop gain using a network analyzer to verify the system stability margins under various conditions. Middlebrook’s injection technique [1] has been widely adopted in practice as it allows loop gain measurements without breaking the feedback loop. In this way, designs can be verified offline to ensure desired performance before system deployment. With advances in digital control for high-frequency DC-DC converters [2], it becomes possible to consider alternative design approaches and techniques leading to improved closed-loop dynamic responses or improved robustness of SMPS. In particular, various methods have been proposed to measure converter frequency responses online [3-6] or to tune compensator parameters based on online assessments of the frequency responses [6-10]. In [3-5], a pseudo-random binary sequence perturbs the converter duty cycle for the purpose of identifying the open-loop control-to-output frequency response using cross-correlation methods. During duty-cycle perturbation, the system is temporarily operated in openloop steady state. As a result, these approaches are best 978-1-4244-1668-4/08/$25.00 ©2008 IEEE II. STABILITY MARGIN MONITOR Middlebrook’s analog loop gain measurement technique is a well known and widely accepted approach to measuring the loop frequency responses without breaking the feedback loop [1, 16]. Figure 1 illustrates this approach for the case of voltage injection Vz in series with the loop. The measured gain Tv(s) is 0 Block 1 Z1(s) + + _ G1(s)ve(s) Σ - Block 2 Vˆz ( s) vref(s) Zs(s) + Vˆy ( s ) + Vˆx ( s ) iˆ( s ) G2 ( s )Vˆx ( s ) Z2(s) - -Tv(s) H(s) Figure 1: Small-signal SMPS model illustrating analog loop gain measurement technique using voltage injection without breaking the feedback loop [1, 16]. 859 Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 13:03 from IEEE Xplore. Restrictions apply. Tv ( s ) = − Vˆy ( s ) Z (s) ⎞ Z (s ) ⎛ = T ( s )⎜1 + 1 ⎟ + 1 , ˆ Z Vx ( s) 2 (s) ⎠ Z 2 ( s) ⎝ T (e (1) −V y . Vx ϕ m = 180° + ∠T ⎛⎜ e ⎝ jωinjT ⎞⎟ . ⎠ ωinj =2πf c fc = finj , (5) V y = Vx . (6) Further, when (6) is satisfied, the phase margin can be directly measured as: ϕ = ϕ m = ∠V y ( f inj ) − ∠V x ( f inj ) . Σ _ Verr(t) Switched-Mode Power Converter Vy + + δ -δ Injection Generator δ Stability Margin Monitor Vref(t) + ADC -T Vz (7) Based on (2)-(7), the crossover frequency and phase margin can be monitored online in digitally controlled systems without requiring any additional power stage information. The monitoring can be performed continuously during normal operation of the system at the cost of a small output voltage perturbation imparted by the injection Vz. However, the perturbation amplitude seen at the converter output can be automatically controlled by adjusting the signal injection amplitude δ, as shown in Fig. 2. A more detailed block diagram of the stability margin monitor is shown in Fig. 3. Details regarding the design Vout(t) Σ (4) if (2) Vx (3) From (2) and (3), the crossover frequency fc is equal to the injection source frequency, From (2), the crossover frequency, fc, can be found as the frequency where: DPWM ) =1 , while the phase margin is obtained from where T(s) is the actual loop gain. Clearly, T(s) ≈ Tv(s) as long as ||Z1|| << ||Z2|| and ||T|| >> ||Z1/Z2||. In a SMPS with analog voltage-mode PWM control, points where the impedance conditions for the loop gain measurement using voltage injection are well satisfied typically include the converter output or the compensator output. Figure 2 shows an implementation of the injectionbased loop gain measurement technique applied to a digitally-controlled SMPS. The digital controller has the standard architecture including a voltage A/D converter (ADC), discrete-time compensator and digital pulsewidth modulator (DPWM). Similar to the analog voltage injection approach, a small digital injection source Vz can be added to a digital loop signal at a suitable point. For example, injection can occur at the compensator input or at the compensator output, as shown in Fig. 2. It should be noted that a similar signal injection technique has been proposed for the purpose of tuning a compensator gain to achieve desired crossover frequency as part of an autotuning process [10]. Given the injection source Vz, and the fact that ||Z1/Z2|| = 0 in the digital part of the loop, the system loop gain can be found as: T= jωinjT PID Compensator Gc(z) Injection Amplitude Controller finj φ Figure 2: Crossover frequency and phase margin monitor block diagram. The outputs of stability margin monitor are crossover frequency and phase margin. The injection amplitude controller automatically adjusts the square-wave perturbation amplitude, δ, to result in minimum (+/- 1 LSB) perturbation at the output voltage. 860 Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 13:03 from IEEE Xplore. Restrictions apply. To DPWM Σ Vx From Compensator + Band-pass Filter Σ Vp_ref _ Vp_err δ Injection Generator Vp + Peak Detector Vy Vz + Band-pass Filter Vy(finj) Verr[n] Injection Generator -δ δ ∫ δ Vx(finj) finj finj ∫ Peak Detector + ||Vx(finj)|| Σ Figure 4: Block diagram of the injection amplitude controller. The injection amplitude, δ, is adjusted via feedback until the desired output voltage perturbation magnitude is achieved. Peak Detector _ Phase Detector improved DC regulation, as explained in [17]. In particular, the +/- 1 LSB periodic oscillation imposed by Vz at the output voltage combined with the action of the integrator in the PID compensator will work to position the DC value of the output voltage in the center of the zero error bin. The accuracy with which the output voltage can be centered in the zero error bin then becomes a function of the DPWM resolution rather then the ADC resolution, which in general is finer to satisfy conventional limit cycle criteria [18, 19]. ||Vy(finj)|| φ Figure 3: Blocks required to implement the stability margin monitor. The injection frequency is adjusted, via feedback, until the filtered peaks, ||Vx(finj)|| and ||Vy(finj)|| are equal. At this point, finj = fc and φ=φm. and implementation of each block in Fig. 3 are presented in the following subsections. B. Band-pass Filters and Peak Detectors As described previously, in the proposed implementation of Fig. 3, Vz is a 50% duty cycle squarewave injection with adjustable frequency determined by the frequency command finj. However, (2)-(7) are based on the assumption that Vz is a purely sinusoidal injection. To account for the infinite odd harmonics introduced by the square-wave, band-pass filters are used to remove all unwanted frequency components of Vx and Vy. The outputs of the band-pass filters, Vy(finj) and Vx(finj), then contain only one frequency component, equal to the injection frequency. In Fig. 3, the band-pass filters, Gbp(z), are designed to be high Q-factor filters with the pass-band of the filter centered at finj. However, since finj changes in order to satisfy (5), the filter pass-bands must also continuously change. To understand how to realize adjustable bandpass digital filters, consider a general form 2nd order digital band-pass filter A. Injection Generator and Injection Amplitude Controller The injection generator block creates a 50% duty cycle, square-wave perturbation with frequency adjustable by the frequency command, finj. Practically, this square-wave signal can be generated with a digital counter, running off of a system clock having clock frequency fclk, and a simple comparator. The frequency resolution qfinj in finj depends on the ratio of the system crossover frequency fc and the system clock frequency fclk, q finj = f c2 . f clk (8) In a typical system, the crossover frequency fc is a fraction of the switching frequency fs, which, in turn is a fraction of the system clock frequency. Hence, the resolution qinj is typically a small fraction of fc. To minimize the impact of the signal injection on the output voltage ripple, it is desirable to control the injection signal amplitude, δ, to obtain a minimum detectable +/-1 least significant bit (LSB) output voltage perturbation. However, in general the required injection signal amplitude depends on finj. A block diagram of the proposed feedback loop used to control δ to account for changes in finj is shown in Fig. 4. The injection amplitude controller takes as input the quantized output voltage error Verr[n], which is then passed through a peak detector. The peak output voltage error, Vp, is compared to the desired LSB perturbation magnitude, Vp_ref. A simple integral compensator then adjusts δ until the desired output voltage perturbation is achieved. A secondary benefit to purposely introducing a periodic oscillation into a digital control loop involves Gbp ( z ) = A (z − 1) 2 z + Bz + C . (9) Based on the discrete-time to continuous-time mapping z=e s f sample , (10) the pass-band center frequency fpb and the Q-factor of (9) can be found as f pb = f sample 2π ⎛ B 2 − 4C tan −1 ⎜ ⎜ B ⎝ ⎞ ⎟, ⎟ ⎠ 861 Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 13:03 from IEEE Xplore. Restrictions apply. (11) ⎛ B 2 − 4C tan −1 ⎜⎜ B ⎜ 1 ⎝ Q= 2 ln C ⎞ ⎟ ⎟⎟ ⎠. degrees in the detected phase, f q PM = 360° c . (13) f clk Since fc is typically a fraction of the switching frequency, which is a fraction of the system clock frequency, (13) implies a phase detection resolution of several degrees. The other main factor in the resolution/accuracy of the phase detector is the sample rate, fsample, of the bandpass filters with respect to finj (12) Given fsample, fpb and Q, (11) and (12) can be used to solve for the filter coefficients B and C. Then, by holding A, B and C constant while varying fsample in proportion to finj, the filter pass-band center frequency fpb shifts in proportion to finj while Q stays constant. The peak detectors take as inputs the filtered waveforms, Vy(finj) and Vx(finj), and output ||Vx(finj)|| and ||Vy(finj)||, as shown in Fig. 3. The peak detectors give an assessment of the magnitudes of each signal such that (6) can be satisfied by closing an integral feedback loop around the injection frequency. fsample = γ finj. (14) where γ is an integer proportionality constant. Since Vy(finj) and Vx(finj) are sampled at a rate proportional to finj, their respective zero crossings could be shifted by as much as one sample period, 1/fsample, from the actual zerocrossings. Therefore, the phase error satisfies C. Integral Compensator A slow integral compensator is used to process the error between ||Vx(finj)|| and ||Vy(finj)||. Since the stability margin monitor control loop is a sampled-system, its bandwidth must be much slower than the injection frequency (which upon convergence equals fc). Therefore, a slow integral compensator is sufficient to close the feedback loop in the stability margin monitor. The output of the integral compensator is finj, the injection frequency command, which is adjusted until there is no error between ||Vx(finj)|| and ||Vy(finj)||, at which point (6) is satisfied and fc = finj. PM _ error ≤ 360° . (15) γ As γ is increased, (15) approaches zero and the phase margin resolution is dominated by (13). Note that (15) gives the maximum phase error (i.e. the phase error is guaranteed to be no larger than (15)). III. EXPERIMENTAL RESULTS There are two experimental test-beds, shown in Fig. 6, used to verify functionality of the proposed stability margin monitor, a synchronous buck converter and a boost converter which can be operated in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). 4 μH Point A D. Phase Detector The phase detector block diagram, used to monitor φm, is shown in Fig. 5 and is similar to some approaches used to detect phase in digital phase-locked loops [20]. The phase detector takes as input the filtered signals, Vy(finj) and Vx(finj). These signals are passed through a digital relay whose output is high when the input is above zero and low when the input is below zero. The two relay outputs are then XOR’d together to form an Enable pulse, labeled in Fig. 5, which is high when the two inputs are not equal. This enable pulse gives a direct relationship between the phases of the two inputs signals. A counter running at the system clock frequency, fclk, measures the length of time Enable is high which is related to the phase shift between Vy(finj) and Vx(finj). There are two important sampling effects which determine the resolution of the phase detector. First, the system clock frequency determines the resolution in + 12V 370 μF + _ 5V 0.4 _ D _ fc Vref ADC Digital Controller + φm (a) Synchronous buck converter L Point A + Vg Vy(finj) Relay 2 μF + _ Clk 30V .025 _ Enable XOR Vx(finj) Counter φ D _ Digital Controller Relay fc ADC Vref + φm (b) CCM or DCM boost converter Figure 5: Block diagram of the phase detector. A system clock, Clk, is used to measure the time shift between Vx(finj) and Vy(finj). Figure 6: Experimental prototypes used for testing stability monitor (a) Synchronous buck converter, (b) CCM or DCM boost converter. 862 Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 13:03 from IEEE Xplore. Restrictions apply. TABLE I SUMMARY OF EXPERIMENTAL STABILITY MONITORING RESULTS COMPARING STABILITY MARGINS BASED ON MODEL [21], MEASURED VIA PROPOSED MONITORING LOOP AND MEASURED VIA TRADITIONAL ANALOG LOOP GAIN MEASUREMENT [1] Digital Compensator Measured fc Average Measured φm Measured fc Measured φm (z − 0.762)(z − 0.91) (z + 0.4)(z − 1) 9.22 kHz 55.0° 9.20 kHz 51.4° 9.58 kHz 53.56° (z − 0.831)(z − 0.728 ) z (z − 1) 13.8 kHz 27° 13.89 kHz 28.4° 14.2 kHz 28.7° (z − 1) 1.20 kHz 85.1° 1.23 kHz 80.7° 1.78 kHz 84.8° (z − 0.8) (z − 1) 6.87 kHz 65.6° 6.42 kHz 61.5° 6.68 kHz 67.6° 0.035 2. 0 z The input injection magnitude, δ, is continuously updated based on the injection amplitude controller shown in Fig. 4 until the output voltage error Verr[n] is minimum possible, +/- 1 LSB. In the experimental prototypes, this amounts to +/- 0.4% output voltage perturbation in the buck converter and +/- 1.6% perturbation in the boost converter. The speed of the input amplitude controller has been designed to be faster then the monitoring control loop. Given the described experimental systems, Table I summarizes the experimental performance of the stability margin monitor with four different power stage configurations. In Table I, finj and φm based on the proposed monitoring approach closely match the expected values for each case, based on the discrete-time model of [21]. Further, the monitored phase margin never deviates more than 11.25° from the predicted value, thus satisfying the expected error given by (20). Note that the phase margin results given in Table I are averaged The nominal power stage parameters of the buck converter are given in Fig. 6(a). The buck converter output voltage ADC is a TI-THS1030 with an effective output voltage LSB resolution of 20 mV. The nominal switching frequency is 100 kHz. Nominally, the boost converter power stage parameters are as shown in Fig. 6(b) with Vg and L depending on the mode of operation (CCM or DCM). In CCM, Vg_CCM = 15V and LCCM = 100 μH. In DCM, Vg_DCM = 10V and LDCM = 20 μH. The boost converter ADC is an AD7822 with an effective output voltage resolution of 512 mV. As with the buck converter, the nominal switching frequency is 100 kHz. In all power stages, the system clock frequency is fclk = 50 MHz, which from (13) implies q PM = 360° fc = 7.2 × 10 −6 ( f c ) . 50 MHz (16) The matched band-pass filters were implemented using the following transfer function Gbp ( z ) = 0.00195 z −1 z 2 + 1.989 z − 0.998 10 8 . (17) 6 (a) Measured crossover frequency [kHz] Where fsample = 32 finj, i.e., γ = 32. Based on (11) and (12), the filter pass-band center frequency and Q-factor are 80° 60° 40° f sample 20° f pb = Analog Injection Results Analytical φm 2.0693 2.8203 Digital Stability Margin Detection Analytical fc Gc(z) System 1 Buck Converter System 2 Buck Converter System 3 CCM Boost Converter System 4 DCM Boost Converter Analytical Stability Margins 32 , PM_error (b) Measured phase margin (18) 10 Q = 100 = 40dB . (19) 8 6 Further, from (15) and (18), the maximum possible phase error expected in hardware is PM _ error ≤ 360° = 11.25° . 32 0.004 0.008 0.012 0.016 (c) Injection amplitude [DPWM LSB’s] 0.02 Time (s) Figure 7: Experimentally observed dynamic performance of the stability margin monitoring control loop. The dynamic response to a change from Vg = 12V to Vg = 8V with the compensator of System 1: (a) crossover frequency fc, (b) Phase margin φm with maximum expected phase error based on (20), (c) Injection amplitude δ. (20) 863 Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 13:03 from IEEE Xplore. Restrictions apply. monitor recognizes the bus voltage change and updates the outputs accordingly. The high frequency noise seen in the monitored phase margin is an artifact of the bandpass filter sample rate selection discussed previously. Note however that the magnitude of the high frequency noise is always less than the error predicted by (20), as expected. One advantage to the proposed solution to monitoring stability margins is that the system does not require open loop or steady-state operation. This allows the monitor to run and converge despite power stage transients (load, line, etc.). Figure 8 shows the load transient response of System 1 of Table I (buck converter) and System 4 of Table I (DCM boost converter) with and without the stability margin monitor. First, Fig. 8(a) is the load transient response, from 2.5A to 0A, of System 1 without the phase margin monitor. As expected, the load transient causes a deviation in output voltage, which returns to steady state after some time due to the action of the feedback loop. In Fig. 8(c), the same load transient is imposed as in Fig. 8(a), but with the stability margin over 100 samples. Table I also shows measured results based on the standard analog injection technique, obtained by introducing an analog voltage injection, Vz, at the converter output (Point A in Fig. 6), with the digital stability monitor disabled. The results from the standard analog injection technique indicate close matches with the measurements from the proposed digital technique and the discrete-time model. Based on the cases tested in Table I, worst case injection frequency and phase margin resolution can be determined from (8) and (13). Based on the highest crossover frequency for the tested systems, the injection frequency resolution is always greater than 4 Hz while the phase margin resolution is always greater then 0.1°. Figure 7 shows the experimentally observed dynamics of finj, φm and δ, captured in Chipscope (a Xilinx embedded FPGA logic analyzer), under a power stage line transient. In particular, Fig. 7(a), Fig. 7(b) and Fig. 7(c) show a bus voltage change in the synchronous buck converter power stage from 12V to 8V with the compensator of System 1. Under this change, the 1 LSB (c) System 1 (synchronous buck) with monitoring loop (a) System 1 (synchronous buck) without monitoring loop 1 LSB (b) System 4 (DCM boost) without monitoring loop (d) System 4 (DCM boost) with monitoring loop Figure 8: Output voltage and inductor current waveforms: (a) System 1 (synchronous buck) without crossover frequency and phase margin monitoring during a 2.5A Æ 0A load transient, (b) System 4 (DCM boost) without the crossover frequency and phase margin monitor during a 3A Æ 0.05A load transient (c) System 1 with crossover frequency and phase margin monitoring during a 2.5A Æ 0A load transient, (d) System 4 with the crossover frequency and phase margin monitor during a 3A Æ 0.05A load transient 864 Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 13:03 from IEEE Xplore. Restrictions apply. monitor control loop running. Note the oscillation imposed by Vz is only +/- 1 LSB due to the action of the feedback loop controlling δ. Also, note that the frequency of Vz is equal to the crossover frequency. Load transient results are presented in Fig. 8(b) and Fig. 8(d) for System 4 of Table I, the DCM boost converter. Since the boost converter is operating in DCM, the load transient (from 3A to 50mA) significantly affects the crossover frequency, as indicated by the oscillation frequency before and after the transient in Fig. 8(d). Based on the discrete-time model [21], the expected crossover frequency after the load transient is 4.1 kHz, which is approximately the frequency of oscillation seen in Fig. 8(d). In Fig. 8(c) and Fig. 8(d), notice the output voltage perturbation combined with the action of the integrator in the PID compensator centers the DC value of the output voltage in the zero error bin with accuracy related to the DPWM resolution rather than the ADC resolution, as discussed previously. Since in general the DPWM resolution is finer than the ADC resolution, this equates to more precise DC regulation accuracy with the imposed output voltage oscillation than without. As a final note, the hardware required to implement all of the above described blocks is summarized in Table II. As indicated, to implement the entire stability margin monitor requires a relatively modest gate count and no additional memory. [3] [4] [5] [6] [7] [8] [9] [10] [11] TABLE II REQUIRED LOGIC RESOURCES TO IMPLEMENT DIGITAL STABILITY MONITOR Function Logic Gates Injection/Clock Generator 1262 Band-pass Filters 2288 Peak Detectors 1220 Integral Compensator 1034 Amplitude Controller 1448 7252 Total III. [12] [13] [14] [15] CONCLUSIONS This paper presents a practical method for continuously monitoring the crossover frequency and phase margin in digitally controlled switching power converters. The proposed approach does not require open loop operation and is capable of converging to correct results in the presence of load transients or other disturbances. Further, the stability margin monitoring requires and ensures that only +/- 1 LSB output voltage perturbation is caused by the monitor. Experimental results are presented for four different system configurations indicating close matches between monitored and expected crossover frequencies and phase margins. Experimental results are also presented showing the observed output voltage and inductor current during a load transient, indicating that the control loop is unaffected by disturbances. [16] [17] [18] [19] [20] [21] REFERENCES [1] [2] R.D.Middlebrook, “Measurement of Loop Gain in Feedback Systems,” Int. J. Electronics, 1975, pp. 485-512. D. Maksimovic, R. Zane and R. Erickson, “Impact of digital control in power electronics,” in Proc. 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