datasheet for MFM8126W by Apta Group

datasheet for MFM8126W by Apta Group
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES.
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
128K x 8 FLASH
MFM8126 - 70/90/12
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Issue 4.3 : April 2001
Features
• Fast Access Time of 70 / 90 / 120ns.
• Operating Power Read
182mW (Max)
Program/Erase 305mW (Max)
Standby Power
6.4mW (Max)
• JEDEC standard package.
• Flexible Sector Erase Architecture - 16K byte sector
size, with hardware protection of any number of sectors.
• Single Byte Program of 14µs (typical), Sector Program /
Verify time of 0.3 sec. (typical).
• Device FLASH Erase / Verify of 3 seconds (typical).
• Erase/Write Cycle Endurance 10,000 (minimum)
• Extended endurance (E) option
• Can be screened in accordance with MIL-STD-883.
General Description
The MFM8126 is a 1Mbit CMOS 5.0V only FLASH
memory arranged as 128K X 8.
Flash memory combines the functionality of
EEPROM with on board electrical Write/Erasure,
which reliably stores data even after 10,000 cycles.
The device incorporates Automatic Programming
and Erase functions, thus simplifying the external
control circuitry.
In addition, a Sector Erase function is available
which can erase one 16K block of data randomly
and more than one block simultaneously. The
MFM8126 also features hardware sector
protection, which enables both program and erase
operations in any of the 8 sectors.
Pin Definitions
Block Diagram
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
D0-D7
Vcc
Input/Output
Buffers
Erase Voltage
Generator
State
Control
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
OE
Embedded
Algorithms
Y-Decoder
Y-Gating
L
a
t
c
h
X-Decoder
Cell Matrix
Package Details
Pin Count
Description
13
12
11
10
9
8
7
6
Timer
A0-A16
32
32
A
d
d
r
D1
D2
GND
D3
D4
D5
D6
14
15
16
17
18
19
20
TOP VIEW
J,W
4
3
2
1
32
31
30
A12
A15
A16
NC
VCC
WE
NC
D7
CS
A10
OE
A11
A9
A8
A13
A14
Vcc Detector
STB
D0
A0
A1
A2
A3
A4
A5
A6
A7
CS
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
5
Command
Register
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
22
23
24
25
26
27
28
29
WE
21
Vss
1
2
3
4
5
6
7
8 TOP VIEW
V,S
9
10
11
12
13
14
15
16
Package Type
0.1" Vertical-in-line (VILTM)
Leadless Chip Carrier (LCC)
V
W
Pin Functions
A0-A16
D0-D7
CS
WE
OE
Vcc
GND
Address Inputs
Data Inputs/Outputs
Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
DC Operating Conditions
Absolute Maximum Ratings (1)
max
unit
-2.0 to +7
V
-2.0 to +7
V
-2.0 to +14
V
-55 to +150 °C
Voltage on any pin w.r.t. Gnd(2) (except A9)
Supply Voltage(2)
Voltage on A9 w.r.t. Gnd
Storage Temperature
Notes : (1)
(2)
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operationof the device at those or any other conditions above those indicated in the operational sections of this
specification is not implied.
Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V. During
transitions voltage may overshoot by +/-1V for upto 10ns
Recommended Operating Conditions
Parameter
Symbol
min
typ
max
unit
Supply Voltage
Input High Voltage
Input Low Voltage
V CC
4.5
5.0
5.5
V
TTL
VIH
2.0
-
VCC+0.5
V
CMOS
VIHC
0.7 VCC
-
VCC+0.5
V
TTL
VIL
-0.5
-
0.8
V
CMOS
VILC
-0.5
-
0.8
V
TA
0
-
70
°C
TAI
-40
-
85
°C (-I suffix)
TAM
-55
-
125
°C (-M, MB suffix)
Operating Temperature
DC Electrical Characteristics (TA= -55°C to +125°C,VCC=5V±10%)
Parameter
Symbol Test Condition
min
typ
max
Unit
Input Leakage Current
ILI
VIN=0 to VCC , VCC = VCC max.
-
-
±2
µA
Output Leakage Current
ILO
VOUT=0 to VCC ,VCC = VCC max.
-
-
±2
µA
TTL
CMOS
ISB1
ISB2
CS=VIH ,VCC = VCC max.
CS=VCC+0.5 , VCC = VCC max.
-
-
-
-
1.15
115
mA
µA
Operating Current
Read
Program/Erase
ICC1
ICC2
CS = VIL, OE = VIH
CS = VIL, OE = VIH
-
33
55
mA
mA
Output LowVoltage
VOL
IOL=12mA , VCC = VCC min.
-
-
0.45
V
Output HighVoltage
VOH
IOH=-2.5mA , VCC = VCC min.
2.4
-
-
V
Low Vcc lock out voltage
VLKO
3.2
-
-
V
A9 voltage for autoselect
VID
12.5
V
Standby Supply Current
VCC =5.0V
11.5
-
Capacitance (TA=25oC,f=1MHz)
Parameter
Input Capacitance:
Output Capacitance:
Symbol
CIN
COUT
Test Condition
VIN=0V
VOUT=0V
Note: Capacitance calculated not measured.
2
typ
6
8.5
max
7.5
12
Unit
pF
pF
MFM8126S - 70/90/12
ISSUE 4.3 : April 2001
AC Test Conditions
* Input pulse levels : 0.0V to 3.0V
* Input rise and fall times : 5 ns
* Input and output timing reference levels : 1.5V
* VCC = 5V +/- 10%
166 Ω
I/O Pin
1.76V
30pF
Operating Modes
The following modes are used to control the MFM8126
OPERATION
CS
OE
WE
AO
A1
A9
I /O
Auto-Select Manufacturer Code
L
L
H
L
L
VID
Code
Auto Select Device Code
L
L
H
H
L
VID
Code
Read
L
L
H
A0
A1
A9
Dout
Standby
H
X
X
X
X
X
High Z
Output Disable
L
H
H
X
X
X
High Z
Write
L
H
L
A0
A1
A9
Din
Enable Sector Protect
L
VID
L
X
X
VID
X
Verify Sector Protect
L
L
H
L
H
VID
Code
3
ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
AC Operating Conditions
Read
Parameter
Symbol
-70
min
max
min
-90
max
min
-12
max
unit
Read Cycle Time
tRC
70
-
90
-
120
-
ns
Address to output delay
tAC
-
70
-
90
-
120
ns
Chip Select to output
tCE
-
70
-
90
-
120
ns
Output Enable to output
tOE
-
30
-
35
-
50
ns
Chip Select to O/P High Z
tDF
-
20
-
20
-
30
ns
Output Enable to output High Z
tDF
-
20
-
20
-
30
ns
Output hold time (From address,
tOH
0
-
0
-
0
-
ns
Symbol
min
max
min
max
min
max
unit
Write Cycle time
tWC
70
-
90
-
120
-
ns
Address Setup time
tAS
0
-
0
-
0
-
ns
Address Hold time
tAH
45
-
45
-
50
-
ns
Data Setup Time
tDS
30
-
40
-
50
-
ns
Data hold Time
tDH
0
-
0
-
0
-
ns
Output Enable Setup Time
tOES
0
-
0
-
0
-
ns
Output Enable Hold Time
tOEH
0
-
0
-
0
-
ns
Read Recover before Write
tGHWL
0
-
0
-
0
-
ns
CS setup time
tCS
0
-
0
-
0
-
ns
CS hold time
tCH
0
-
0
-
0
-
ns
Write Pulse Width
tWP
35
-
40
-
50
-
ns
Write Pulse Width High
tWPH
20
-
20
-
20
-
ns
Programming operation
tWHWH1
14
-
14
-
14
-
µs
tWHWH2
3
60
3
60
3
60
s
tVCS
50
-
50
-
50
-
µs
tVLHT
4
-
4
-
4
-
ns
CS or OE whichever occurs first)
Write/ Erase/ Program
-70
Parameter
(1)
Erase operation
Vcc setup time
(4)
Voltage Transition Time
Write Pulse Width
(2,4)
(2)
tWPP
10
-
10
-
10
-
ns
tOESP
4
-
4
-
4
-
ns
(3,4)
tCSP
4
-
4
-
4
-
ns
CS Setup time to WE active
(1)
(2)
(3)
(4)
-12
(2,4)
OE Setup time to WE active
Notes:
-90
This also includes the preprogramming time.
These timings are for Sector Protect/Unprotect operations.
This timing is only for Sector Unprotect.
Not 100% tested.
4
MFM8126S - 70/90/12
ISSUE 4.3 : April 2001
Write/Erase/Program (Alternate CS controlled Writes)
-70
Parameter
-90
-12
Symbol
min
max
min
max
min
max
unit
Write Cycle time
tWC
70
-
90
-
120
-
ns
Address Setup time
tAS
0
-
0
-
0
-
ns
Address Hold time
tAH
45
-
45
-
50
-
ns
Programming operation
tDS
30
-
40
-
50
-
ns
Data hold Time
tDH
0
-
0
-
0
-
ns
Output Enable Setup Time
tOES
0
-
0
-
0
-
ns
Output Enable Hold Time
tOEH
0
-
0
-
0
-
ns
Read Recover before Write
tGHEL
0
-
0
-
0
-
ns
WE setup time
tWS
0
-
0
-
0
-
ns
WE hold time
tWH
0
-
0
-
0
-
ns
CS Pulse Width
tCP
35
-
40
-
50
-
ns
CS Pulse Width High
tCPH
20
-
20
-
20
-
ns
Programming operation
tWHWH1
14
-
14
-
14
-
µs
tWHWH2
3
60
3
60
3
60
s
tVCS
2
-
2
-
2
-
µs
(1)
Erase operation
Vcc setup time
Notes:
(2)
(1) This also includes the preprogramming time.
(2) Not 100% tested.
5
ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
AC Waveforms for Read Operation
Address Valid
Address
tRC
CS
tCE
tOE
tDF
OE
WE
tOH
tACC
Output
Valid
HIGH Z
Data Out
HIGH Z
AC Programming Waveforms
Data Polling
5555H
Address
PA
t AS
t
PA
t RC
t AH
CS
t GHWL
OE
t WHWH1
t WP
WE
t OE
t WPH
t CS
t DH
A0H
DATA
t DF
PD
D7
D OUT
t DS
t CE
5.0 V
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6
t OH
MFM8126S - 70/90/12
ISSUE 4.3 : April 2001
AC Chip / Sector Erase Waveforms
t AS
Address
5555H
t AH
2AAAH
5555H
5555H
2AAAH
55H
80H
AAH
5HH
SA
CS
t GHWL
OE
t WP
WE
t WPH
t CS
t DH
Data
t DS
Vcc
AAH
10H/30H
t VCS
NOTES:
1. SA is the address for Sector Erase. Addresses = don't care for Chip Erase.
AC Waveforms for Data Polling During Embedded Algorithm Operations
t CH
CS
t DF
t OE
OE
t OEH
WE
t OH
t CE
D7
D7
*
t WHWH 1 OR 2
D0~6
D0~6=Invalid
HIGH Z
D7 =
Valid Data
D0~7
Valid Data
t OE
*
D7 = Valid data (The device has completed the Embeded Operation).
7
HIGH Z
ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
WE
tOEH
CS
OE
*
Data (D0~7)
D6=Toggle
D6=Toggle
D6 = Stop
Toggling
D0~7 Valid
tOE
tOH
D6 stops toggling (The device has completed the Embedded operation).
AC Waveforms For Sector Protection
A16
A15
A14
SA X
SA Y
A0
A1
12V
5V
A9
t VLHT
t VLHT
12V
5V
OE
t WPP
t VLHT
WE
t OESP
CS
Data
t OE
SAX = sector Addr for intial sector
SAY = sector Addr for next sector
8
01H
MFM8126S - 70/90/12
ISSUE 4.3 : April 2001
AC Waveforms for Sector Unprotect
≈
A16
A15
A14
≈ ≈
SA0
≈ ≈
A0
≈ ≈
A1
12V
5V
A9
≈
t VLHT
≈ ≈
A6
≈
A7
A12
OE
t VLHT
≈ ≈
12V
5V
t CSP
t WPP
VLHT
WE
CS
t VLHT
t VLHT
≈
Data
≈
12V
5V
Execute Auto Select
Command Sequence
9
00H
SA1
ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
A.C Waveforms - Alternate CS controlled Program operation timings
Data Polling
Address
5555H
PA
t WC
t AS
PA
t AH
WE
t GHEL
OE
t CP
t CPH
CS
DATA
t WS
t DH
A0H
DQ7
PD
t DS
VCC
NOTES:
1. PA is address of memory location to be programmed.
2. PD is data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
10
D OUT
MFM8126S - 70/90/12
ISSUE 4.3 : April 2001
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. The
following table defines these register command sequences.
COMMAND
Bus
Write
Cycle
SEQUENCE
Req'd
First Bus
Second Bus Third bus
Write Cycle Write Cycle Write Cycle
Addr Data Addr
Data
Addr Data
Fourth bus
Read/Write
Cycle
Addr
Data
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr
Data
Addr
Data
Read/Reset
4
5555H
AAH
2AAAH
55H
5555H
F0H
RA
RD
Autoselect
4
5555H
AAH
2AAAH
55H
5555H
90H
00H/01H
01H/20H
Byte Program
4
5555H
AAH
2AAAH
55H
5555H
A0H
PA
PD
Chip erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
Sector erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SA
30H
NOTES:
1. Address bit A15=X=Don't care. Write Sequences may be initiated with A15 in either state.
2. Address bit A16=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA).
3. RA=Address of the memory location to be read.
PA=Address of memory location to be programmed. Addresses are latched on the falling edge of the WE
pulse.
SA=Address of the sector to be erased. The combination of A16, A15 and A14 will uniquely select any
sector.
4. RD=Data read from location RA during read operation.
PD=Data to be programmed at location PA. Data is latched on the falling edge of WE
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for
reads until the command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters.
11
ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
Read Mode
The MFM8126 has two control functions which must be satisfied in order to obtain data at the outputs
CS is the power control and should be used for device selection
OE is the output control and should be used to gate data to the output pins if the device is selected.
Standby Mode
Two standby modes are available :
CMOS standby : CS held at Vcc +/- 0.5V
TTL standby : CS held at VIH
In the standby mode the outputs are in a high impedance state independent of the OE input. If the device is
deselected during erasure or programming the device will draw active current until the operation is completed.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify the device manufacturer and type. This mode is intended for use by programming equipment. This mode is functional over the full
military temperature range. The autoselect codes are as follows :
A16
A15
A14
DIE Manufacturer code
X
X
DIE device code
X
X
Sector protection
A1 A0 CODE
(HEX)
D7 D6
D5 D4 D3 D2
D1
D0
X
VIL VIL
01H
0
0
0
0
0
0
0
1
X
VIL VIH
20H
0
0
1
0
0
0
0
0
Sector Address VIH VIL
01H*
0
0
0
0
0
0
0
1
* Outputs 01H at protected sector address. Outputs 00H at unprotected sector address.
To activate this mode the programming equipment must force VID (11.5 to 12.5V) on address A9. Two identifier
bytes may then be sequenced from the device outputs by toggling A0 from VIL to VIH. All addresses are dont care
apart from A1 & A0. All identifiers for manufacturer and device will exhibit odd parity with D7 defined as the parity
bit.
The manufacturer and device codes may also be read via the command register, for instances when the
MFM8126 is erased or programmed in a system without access to high voltage on A9. All identifiers for
manufacturers and device will exhibit odd parity with the MSB(D7) defined as the parity bit. In order to read the
proper device codes when executing the Autoselect, A1 must be VIL.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device. The register is a latch used to store the commands along with the address and data information required to execute the
command. The command register is written by bringing WE to VIL while CS is at VIL and
OE is at VIH.Addresses are latched on the falling edge of WE while data is latched on the rising edge.
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Sector Protection
The MFM8126 features hardware sector protection. This feature will disable both program and erase operations
in any number of sectors (0 through 7). The sector protect feature is enabled using programming equipment at
the users site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE. The
sector adresses (A16, A15 and A14) should be set to the sector to be protected. Programming of the protection
circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector
addresses must be held constant during the WE pulse. (See Sector Address Table).To verify programming of the
protection equipment circuitry, the programming equipment must force VID on address pin A9 with CS and OE at
VIL and WE at VIH. Reading the device at a particular sector address (A16, A15 and A14) will produce 01H at data
outputs (D0-D7) for a protected sector. Otherwise the device will read 00H for unprotected sector. In this mode,
the lower order addresses, except for A0 and A1, are don't care. Address location 02H is reserved to verify sector
protection of the device. Address pin A1 must be held at VIH and A0 at VIL. Address location 00H aand 01H are
reserved for autoselect codes. If a verify of the sector protection circuitry were done at these addresses, the
device would output the manufacturer and device codes respectively.
It is also possible to determine if a sector is protected in the system by writing the autoselect command.
Performing a read operation at particular sector addresses (A16, A15 and A14) and with A1=VIH and A0=VIL (other
addresses are a don't care) will produce 01H data if those sectors are protected. Otherwise the device will read
00H for an unprotected sector. (See Sector Protect/Unprotect Algorithms for more details.)
Sector Adresses Table.
A16
A15
A14
SA0
0
0
0
00000H-3FFFH
SA1
0
0
1
04000H-07FFFH
SA2
0
1
0
08000H-0BFFFH
SA3
0
1
1
0C000H-0FFFFH
SA4
1
0
0
10000H-13FFFH
SA5
1
0
1
14000H-17FFFH
SA6
1
1
0
18000H-1BFFFH
SA7
1
1
1
1C000H-1FFFFH
13
Address Range
ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
Auto Select Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target systems. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally a desired system design practice.
The device contains an autoselect operation to supplement traditional PROM programming methodology. The
operation is initiated by writing the autoselect command sequence into the command register. Following the
command write, a read cycle from address XXX0H retrieves the manufacture code of 01H. A read cycle from
address XXX1H returns the device code 20H. A read cycle from address XXX2H returns information as to which
sectors are protected. All manufacturer and device codes will exhibit odd parity with the MSB (D7) defined as the
parity bit.
To terminate the operation, it is necessary to write the read/reset command sequence into the register.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycle. These are followed by the program set-up command and data write cycles. The addresses
are latched on the falling edge of CS or WE (whichever last), the data is latched on the rising edge of CS or WE
(whichever first), and then programming begins. Upon executing the Embedded Program Algorithm Command
sequence the system is not required to provide further controls or timings. The device will automatically provide
adequate internally generated program pulses and verify the programmed cell margin. The automatic
programming operation is completed when the data on D7 is equivalent to data written to this bit (see write
Operations Status) at which time the device returns to read mode and addresses are no longer latched. Data
Polling must be performed at the memory location which is being programmed.
Programming is allowed in any address sequence and across sector boundaries. Beware that data "0" cannot
be programmed back to a "1". Attempting to do so will hang up the device, or result in an apparent success
according to the data polling algorithm. However, a read from Read/Reset Mode will show data is still "0". Only
an erase operation can convert "0"s to "1"s.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device automatically will program and verify the entire memory for an all zero
data pattern prior to electrical erase. The systems is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on D7 is "1" (See Written Operation Section) at which time the device returns to read the mode.
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MFM8126S - 70/90/12
ISSUE 4.3 : April 2001
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock"write cycles. These are followed by writing the
"Set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE. A time-out of 80µs from the rising edge of the last sector erase
command will initiate the sector erase command(s).
Multiple sectors may be erased concurrently by writing the six bus cycle operations as desribed above. This
sequence is followed with writes of the sector erase command (30H) to addresses in other sectors required to
be concurrently erased. The time between writes must be less than 80µs, otherwise that command will not be
accepted. It is recommended that processor interrupts be disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector Erase command(s). If another falling edge of WE occurs
within the 80µs time-out window , the timer is reset.(D3 indicates if the timer window is still open). Loading the
sector erase buffer may be done in any sequence and with any number of sectors (0 to 7). Any command other
than Sector Erase during this period will reset the device to read mode, ignoring the previous.
Sector erase doesn't require the user to program the device prior to erase. The device automatically programs all
memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 100µs time-out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on D7 is "1" ( see Write Operation Status Section)
at which time the device returns to read mode. Data polling must be preformed at an address within any of the
sectors being erased.
Write Operations Status
Hardware Sequence Flags
STATUS
D7
D6
D5
D3
D2-D0
Auto-Programming
In Progress Programming in auto erase
D7
0
Toggle
Toggle
0
0
0
1
Reserved for
Erasing in Auto Erase
Auto-Programming
Programming in auto erase
Erasing in Auto-Erase
0
D7
0
0
Toggle
Toggle
Toggle
Toggle
0
1
1
1
1
0
1
1
Exceeded
Time limits
future use
Reserved for
future use
Data Polling - D7
The MFM8126 features Data Polling as a method to indicate to the host system that the Embedded Algorithms
are in progress or completed.
During the Embedded Programming Algorithm, an attempt to read the device will produce complement data of
the data last written to D7. Upon completion of the Embedded Programming Algorithm an attempt to read the
device will produce the true data last written to D7. Data Polling is valid after the rising edge of the forth WE
pulse in the four write pulse sequence.
During the Embedded Erase Algorithm, D7 will be "0" until the erase operation is completed. Upon completion
data at D7 is "1". For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, Data Polling is valid after the last rising edge of the sector erase WE
pulse.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out.
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ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
Toggle Bit - D6
The MFM8126 also features the "toggle bit" as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE Toggling) data from
the device will result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, D6 will stop toggling and valid data will be read on successive attempts. During programming, the Toggle bit is valid after the rising edge of the forth WE pulse in the four write pulse sequence. For chip
erase, the Toggle bit is valid after the sixth WE pulse in the six write pulse sequence.
For sector erase, the Toggle bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit
is active during the sector time-out. Note: CS or OE toggling will toggle D6.
Exceeding Time Limits - D5
D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will
produce "1", indicating the program or erase cycle was not successfully completed . Data Polling is the only
operating function of the device under this condition. The CS circuit will partially power down the device under
these conditions (to approximately 2mA). The OE and WE pins will control the output disable functions . To
reset the device, write reset command sequence to the device. This allows the system to continue to use the
other active sectors in the device.
If this failiure condition occurs during the sector erase operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still functional and may be used for additional program or erase
operations. The device must be reset to use other sectors. Write the Reset command sequence to the device,
and then execute the program or erase command sequence.
If this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or
combination of sectors are bad.
If this failure condition occurs during the byte programming operation, it specifies that the entire sector
containing that byte is bad and this sector may not be reused (other sectors are still functional and can be
reused). The device must be reset to use other sectors.
The D5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the system never reads valid data on the D7 bit and D6 never stops toggling. Once the device has exceeded
timing limits, the D5 bit will indicate a "1". Please note that this is not a device failure condition since the device
was incorrectly used. The device must be reset to continue using the device.
Hardware Sequence Flag - D4
If the device has exceeded the specified erase or program time and D5 is "1", then D4 will indicate at which step
in the algorithm the device exceeded the limits. A "0" in D4 indicates in programming, a "1" indicates an erase.
Sector Erase Timer - D3
After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
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MFM8126S - 70/90/12
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If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may be
used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase cycle
has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is
completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional sector erase
commands. To insure the command has been accepted, the software should check the status of D3 prior to and
following each subsequent sector erase command. If D3 were high on the second status check, the command
may not have been accepted.
Data Protection
The MFM8126 is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets the
internal state machine in the Read mode. Also, with its controls register architecture , alteration of the memory
contents only occurs after successful completion of specific multi-bus cycle command sequences. The device
also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up and power
down transitions or system noise.
Low VCCWrite Inhibit
To avoid initiation of a write cycle during VCC power up and power down, a write cycle is locked out for VCC less
than 3.2V (typically 3.7V). If VCC<VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to read mode. Subsequent writes will be ignored until the
VCC level is greater than VKLO. It is usually correct to prevent unintentional writes when VCC is above 3.2V.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE, CS, WE will not initiate a write cycle
Logical Inhibit
Writing is inhibited by holding any one of OE=VIL, CS=VIH or WE=VIH. To initiate a write cycle CS and WE
must be logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE=CS=VIL and OE=VIH will not accept commands on the rising edge of WE. The
internal state machine is automatically reset to the read mode on power-up.
Sector Protect
Sectors of the MFM8126 may be hardware protected at the users factory. The protection circuitry will disable
both program and erase functions for the protected sector(s). Requests to program or erase a protected sector
will be ignored by the device.
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ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
Embedded Programming Algorithm
Start
Write Program Command Sequence
(See Below)
Data Poll Device
No
Increment Address
Last Address?
Yes
Programme Completed
Program Command Sequence (Address/Command)
5555H/AAH
2AAAH/55H
5555H/AOH
Program Address/Program Data
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MFM8126S - 70/90/12
ISSUE 4.3 : April 2001
Embedded Erase Algorithm
Start
Write Erase Command Sequence
(see below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individu al Sector/M ultip le Se ctor
E rase C om m an d Sequence
(A ddress/C om m and)
5 5 5 5 H /A A H
5555H /A AH
2 A A A H /5 5 H
2A AA H /55H
5 5 5 5 H /8 0 H
5555H /80H
5 5 5 5 H /A A H
5555H /A AH
2 A A A H /5 5 H
2A AA H /55H
5555H/10H
SEC T OR AD DR ESS/3 0H
SEC T OR AD DR ESS/3 0H
Additional sector
erase commands
are optional
SEC T OR AD DR ESS/3 0H
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ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
Data Polling Algorithm
Start
VA = Byte Address for programming
Read Byte
(D0 - D7)
= Any of the sector addresses
within the sector being erased
during sector erase operation.
= XXXXH during chip erase
Addr=VA
Yes
D7=Data?
No
No
D5 = 1?
Yes
Read Byte
(D0 - D7)
Addr=VA
Yes
D7=Data?
Pass
No
Fail
Note : D7 is rechecked even if D5 = "1" beceause D7 may change simultaneousely
with D5.
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MFM8126S - 70/90/12
ISSUE 4.3 : April 2001
Toggle Bit Algorithm
Start
VA = Byte Address for programming
Read Byte
(D0 - D7)
Addr=VA
= Any of the sector addresses
within the sector being erased
during sector erase operation.
= XXXXH during chip erase
No
D6 = Toggle?
Yes
No
D5=1?
Yes
Read Byte
(D0 - D7)
Addr=VA
No
D6 = Toggle?
Pass
Yes
Fail
Note : D6 is rechecked even if D5 = "1" beceause D6 may stop toggling at the same time
as D5 changing to "1"
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ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
Sector Unprotect Algorithm
START
Set Vcc=5.0V
Protect All Sectors
PLSCNT = 1
Set Up Sector
Unprotect Mode
A12 = A7 = VIH , A6 = VIL
Set Vcc=5.0V
Set
OE = CS = A9 = V ID
Activate WE Pulse
Time Out 10ms
Set OE = CS= VIL
Remove VID from A9
Increment
PLSCNT
Set Vcc=4.25V
Write Autoselect
Command Sequence
Set Up Sector Addr SA0
Set A1=1, A0=0
Read Data
from Device
No
Increment
Sector Addr
Data
No
=00H
?
Write Reset
Command
PLSCNT
=1000
?
Yes
No
Sector
Device
Addr = SA7
?
Failed
Yes
Set Vcc=5.0V
Write Reset
Command
Sector Unprotect
Completed
NOTES:
SA0 = Sector Addr for intial sector
SA7 = Sector Addr to last sector
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MFM8126S - 70/90/12
ISSUE 4.3 : April 2001
Sector Protection Algorithm
START
Set Up Sector Addr
(A16, A15, A14)
PLSCNT = 1
OE = VID
A9=VID,CS=V IL
Activate WE Pulse
Time Out 100us
Power Down OE
Increment
PLSCNT
WE = V IH
CS = OE =V IL
A9 should remain V ID
Read from Sector
Addr=SA, A0=0, A1=1
No
PLSCNT
No
Data
= 25
=01H
?
?
Yes
Yes
Device
Failed
Protect
Another
Sector
No
Remove V ID From A9
Write Reset Command
Sector Protection
Complete
23
Yes
ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
Package Details Dimensions in inches.
32 pin Ceramic Vertical in Line - 'V' Package
41.02 (1.615)
3.18 (0.125)
40.26 (1.585)
10.41 (0.410)
11.43 (0.450)
2.67 (0.105)
4.00 (0.157)
3.00 (0.117)
1.54 (0.060)
2.67 (0.105)
0.51 (0.020)
1.02 (0.040)
2.41 (0.095)
0.41 (0.016)
2.54 (0.100)
32 Pad Leadless Chip Carrier (LCC) - 'W' Package
1.27 (0.050) typ
2.03 (0.080)
11.30 (0.445)
0.64 (0.025) typ
max
9.92 (0.390)
13.84 (0.545)
14.22 (0.560)
No. 1 Index
10.42 (0.410)
11.70 (0.460)
7.87 (0.310)
7.37 (0.290)
24
1.27 (0.050)
typ
MFM8126S - 70/90/12
ISSUE 4.3 : April 2001
Screening
Military Screening Procedure
Component Screening Flow for high reliability product using methods from 5004.
MB COMPONENT SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Mechanical
Temperature cycle
Constant acceleration
Pre-Burn-in electrical
Burn-in
1010 Condition C (10 Cycles,-65°C to +150°C)
2001 Condition D (Y, only) (20,000g)
Per applicable device specifications at TA=+25°C
Method 1015,Condition D,TA=+125°C,160hrs min
Endurance
As per internal specification
100%
100%
100%
100%
Write Cycle endurance and
Data Retention performance
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective allowable (PDA)
Calculated at post-burn-in at TA=+25°C
Hermeticity
1014
Fine
Gross
Condition A
Condition C
100%
100%
External Visual
2009 Per vendor or customer specification
100%
25
5%
ISSUE 4.3 : April 2001
MFM8126S - 70/90/12
Ordering Information
MFM8126VMB - 90E
Blank = 10,000 W/E Cycles
E
= 100,000 W/E Cycles
Speed
70
90
12
= 70 ns
= 90 ns
= 120 ns
Temp. range/screening
Blank
I
M
MB
=
=
=
=
Packages
V
W
= 32 Lead Ceramic 0.1" VIL
= 32 Lead Ceramic LCC
Organisation
8126 = 128Kx 8
Technology
F
Commercial Temperature
Industrial Temperature
Military Temperature
May be processed in
accordance with MIL-STD-883
= FLASH MEMORY
THE ABOVE PARTS ARE NOT RECOMMENDED FOR NEW
DESIGNS AND MAY BE MADE OBSOLETE WITHOUT
NOTICE....
Note :
Although this data is believed to be accurate, the information contained herein is not intended to and does not create any
warranty of merchantibilty or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval
of a company director.
26
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