datasheet for MSM8512S by Apta Group

datasheet for MSM8512S by Apta Group
512K x 8 SRAM
MSM8512 - 70/85/10
Issue 4.5 : April 2001
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Description
524,288 x 8 CMOS Static RAM
The MSM8512 is a 4Mbit monolithic SRAM
organised as 512K x 8 with access times from
70ns to 100ns available. The device has a low
power standby version which supports data
retention mode and is directly TTL compatible.
All versions can be screened in accordance with
MIL-STD-883C.
Features
Fast Access Times of 70/85/100 ns
JEDEC standard package.
Average Operating Power 385 mW (max)
Standby Power
550 µW (max) -L version
Low voltage data retention.
Completely Static Operation
Directly TTL compatible
May be processed in accordance with MIL-STD-883C
D0
I/O
BUFFER
4,194,304
BIT
MEMORY
ARRAY
COLUMN I/O
COLUMN DECODE
WE
Y ADDRESS BUFFER
OE
CS
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
Pin Definition
ROW DECODE
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
X ADDRESS BUFFER
Block Diagram
Package Details
Pin Count
32
Descripion
0.6" Dual-in-Line (DIP)
Package Type
S
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
32
2
31
3
30
4
29
5
28
27
6
7
8
9
S,V
Package
Top View
26
25
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
Vcc
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
Pin Functions
A0-A18
Address Inputs
D0-7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
VCC
Power (+5V)
GND
Ground
ISSUE 4.5 April 2001
MSM8512 - 70/85/10
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Voltage on any pin relative to VSS (2)
Power Dissipation
Storage Temperature
VT
PT
TSTG
-0.5
to
1
to
-55
+7.0
V
W
O
C
+150
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
VCC
VIH
VIL
TA
TAI
TAM
min
4.5
2.2
-0.3
0
-40
-55
typ
5.0
-
max
5.5
6.0
0.8
70
85
125
unit
V
V
V
o
C
o
C
o
C
(I suffix)
(M, MB suffix)
DC Electrical Characteristics (VCC = 5.0V±10%, TA=-55°C to +125°C)
Parameter
Symbol Test Condition
min
typ
max
-1
-1
-
1
1
µA
µA
CS=VIH, VIN=VIH or VIL
-
CS≥VCC-0.2V, VIN≥VCC -0.2V or 0.2V≥VIN
-
-
70
3
100
mA
mA
µA
2.4
-
0.4
-
V
V
Input Leakage Current
Output Leakage Current
ILI
ILO
VIN=0V to VCC
Average Supply Current
Standby Supply Current
-L version only
ICC1
ISB
ISB1
CS=VIL, II/O=0mA, min cycle, duty=100%
Output Voltage
VOL
VOH
IOL=2.1mA
CS=VIH, VI/O=0V to VCC, OE=VIH or WE=VIL
IOH=-1.0mA
Capacitance (VCC=5V±10%,TA=25°C)
Parameter
Input Capacitance:
I/O Capacitance:
Symbol
Test Condition
typ
max
Unit
CIN
CI/O
VIN = 0V
VI/O= 0V
-
8
10
pF
pF
Note : This parameter is sampled and not 100% tested.
AC Test Conditions
Output Load
* Input pulse levels: 0.8V to 2.2V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* Vcc=5V±10%
I/O Pin
645 Ω
1.76V
100pF
2
Unit
MSM8512 - 70/85/10
ISSUE 4.5 April 2001
Low Vcc Data Retention Characteristics - L Version Only (TA=-55°C to +125oC)
Parameter
Symbol Test Condition
VCC for Data Retention
Data Retention Current
Chip Deselect to Data Retention
Operation Recovery Time
VDR
ICCDR
t CDR
tR
CS≥VCC-0.2V
VCC=3.0V, CS≥VCC-0.2V,
See Retention Waveform
See Retention Waveform
min
typ
max
Unit
2.0
0
5
-
5.5
250
-
V
µA
ns
ms
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
Read Cycle Time
tRC
Address Access Time
tAA
Chip Select Access Time
tACS
Output Enable to Output Valid
tOE
Output Hold from Address Change
tOH
Chip Selection to Output in Low Z
tCLZ
Output Enable to Output in Low Z
tOLZ
(3)
Chip Deselection to Output in High Z tCHZ
Output Disable to Output in High Z(3) tOHZ
min
70
max
70
10
10
5
0
0
70
70
35
25
25
min
85
10
10
5
0
0
85
max
85
85
45
30
30
10
min max
100
10
10
5
0
0
100
100
50
30
30
min
10
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
Output Disable to Output in High Z
Symbol
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
tDW
tDH
tOW
tOHZ
min
70
max
70
60
60
0
50
0
0
30
0
5
0
3
30
25
min
85
75
75
0
55
5
0
35
0
5
0
85
max
30
30
100
80
80
0
60
5
0
40
0
5
0
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISSUE 4.5 April 2001
MSM8512 - 70/85/10
Read Cycle Timing Waveform (1,2)
t
RC
Address
t AA
OE
t OE
t OH
t OLZ
t CLZ
CS
t ACS
t CHZ(3)
t OHZ(3)
D0~7
High-Z
Data Valid
Notes:
(1) During the Read Cycle, WE is high.
(2) Address valid prior to or coincident with CS transition Low.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
t WC
Address
OE
t AS(3)
t AW
tWR
t CW(4)
(2)
(6)
CS
t WP(1)
WE
t OHZ(3,9)
t OW
High-Z
D0~7 out
t DW
D0~7 in
High-Z
4
t DH
MSM8512 - 70/85/10
ISSUE 4.5 April 2001
Write Cycle No.2 Timing Waveform (5)
t WC
Address
t CW
CS
(4)
(6)
t AW
t WR(2)
t WP(1)
WE
t AS(3)
t OH
t WHZ(3,9)
t OW
(8)
(7)
High-Z
D0~7 out
t DW
tDH
High-Z
D0~7 in
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS and a low WE.
(2) tWR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=VIL)
(6) DOUT is in the same phase as written data of this write cycle.
(7) DOUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Low VCC Data Retention Timing Waveform
Vcc
DATA RETENTION MODE
4.5V
4.5V
t CDR
tR
2.2V
2.2V
V DR
CS>Vcc-0.2V
CS
0V
5
ISSUE 4.5 April 2001
MSM8512 - 70/85/10
Package Details
32 pin 0.6" Dual-in-Line (DIP) - 'S' Package
41.05 (1.616)
14.99 (0.590)
15.49 (0.610)
40.23 (1.584)
1.52 (0.060)
1.02 (0.040)
4.30 (0.170)
3.30 (0.130)
4.00 (0.157)
3.00 (0.117)
0.51 (0.020)
0.41 (0.016)
2.67 (0.105)
2.41 (0.095)
All dimensions in mm (inches).
6
MSM8512 - 70/85/10
ISSUE 4.5 April 2001
Military Screening Procedure
Screening Flow for high reliability product in accordance with MIL-STD-883 method 5004 is shown below.
MB COMPONENT SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Visual and Mechanical
Internal visual
Temperature cycle
Constant acceleration
Pre-Burn-in electrical
Burn-in
2010 Condition B or manufacturers equivalent
1010 Condition C (10 Cycles,-65°C to +150°C)
2001 Condition E (Y, only) (30,000g)
Per applicable device specifications at TA=+25°C
Method 1015,Condition D,TA=+125°C,160hrs min
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective allowable (PDA)
Calculated at post-burn-in at TA=+25°C
5%
Hermeticity
1014
Fine
Gross
Condition A
Condition C
100%
100%
External Visual
2009 Per vendor or customer specification
100%
7
100%
100%
100%
100%
100%
ISSUE 4.5 April 2001
MSM8512 - 70/85/10
Ordering Information
MSM8512SLMB - 70
Speed
70
85
10
=
=
=
70ns
85ns
100ns
Temp. Range/Screening
Blank
I
M
MB
=
=
=
=
Commercial
Industrial
Military
Screened in accordance with
MIL-STD-883
Power Consumption
Blank
L
=
=
Standard Power
Low Power
S
=
32 pin 0.6" DIP
8512
=
5125K x 8 SRAM
Package
Memory Organisation
Although this data is beleived to be accurate, the information contained herein, is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of
a company director.
8
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