datasheet for PUMA68F4001A by Apta Group

datasheet for PUMA68F4001A by Apta Group
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
hmp
128K x 32 FLASH MODULE
PUMA 68F4001-15/17/20
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191 2590997
Issue 4.1 : August 1997
Description
Features
The PUMA 68F4001 is a 4Mbit CMOS FLASH
memory module organised as 128K x 32 in a
JEDEC 68 pin surface mount PLCC, available with
access times of 150, 170 and 200ns. The output
width is user configurable as 8 , 16 or 32 bits using
four Chip Selects (CS1~4). The plastic device is
screened to ensure high reliability.
Page write (128 Bytes) is performed in 10ms with
Toggle bit and DATA polling indication of cycle
completion. The device features both hardware
and software data protection and a low power
standby of 6.6mW. Write cycle endurance is
10,000 Erase/Write cycles with a data retention
time of 10 years.
• Access Times of 150,170 and 200ns.
• User Configurable as 8 / 16 / 32 bit wide output.
• Operating Power :
1320 mW (max)
• Standby Power : -L Part (CMOS)
6.6 mW (max)
• Page Write (128 Bytes) in 10ms typ.
• DATA Polling and Toggle bit indication of end of
write.
• Hardware and Software Data Protection.
• Endurance of 104 Erase/write Cycles and Data
Retention Time of 10 years.
OE
WE
128K x 8
FLASH
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
128K x 8
FLASH
128K x 8
FLASH
VCC
A9
A10
A8
A6
2
A7
3
WE
4
CS4
5
CS3
6
GND
A3
7
A4
A2
8
A5
A0
9
A1
Pin Definition
A0~A16
128K x 8
FLASH
• Industrial, Military or Military(High Rel) Grade.
NC
Block Diagram
• JEDEC 68 'J' leaded plastic Surface Mount
Substrate.
1 68 67 66 65 64 63 62 61
D0
10
60
D16
D1
11
59
D17
D2
12
58
D18
D3
13
57
D19
D4
14
56
D20
D5
15
55
D21
D6
16
54
D22
D7
17
53
D23
GND
18
52
GND
D8
19
FROM
51
D24
D9
20
50
D25
D10
ABOVE
21
49
D26
D11
22
48
D27
D12
23
47
D28
D13
24
46
D29
D14
25
45
D30
D15
26
44
D31
PUMA 68F4001
VIEW
Pin Functions
A0~16 Address Inputs
CS1~4 Chip Select
WE Write Enable
VCC Power (+5V)
D0~31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground
NC
GND
NC
NC
NC
NC
NC
CS2
OE
CS1
A16
A13
A14
A15
A12
A11
VCC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Operating Temperature
Storage Temperature
Input voltages (including N.C. pins) with Respect to GND
Output voltages with respect to GND
TOPR
TSTG
VIN
VOUT
°
-55 to +125
-65 to +150
-0.5 to +7.0
-0.5 to +7.0
C
C
V
V
°
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operating Conditions
DC Power Supply Voltage
Input Low Voltage
Input High Voltage
Operating Temp Range
VCC
VIL
VIH
TA
TAI
TAM
min
typ
max
4.5
-0.3
2.0
0
-40
-55
5.0
0.8
-
5.5
V
DC Electrical Characteristics (TA=-55°C to +125°C,V
Parameter
Symbol
VCC+0.3
70
85
125
V
V
°
C
°
C (I Suffix)
°
C (M, MB Suffix)
=5V ± 10%)
CC
Test Condition
min
Input Leakage Current
Output Leakage Current
ILI1
32 bit ILO
VIN = GND to VCC
Operating Supply Current
32 bit ICC32
16 bit ICC16
8 bit ICC8
CS(1)=OE=VIL, WE=VIH, IOUT=0mA, ƒ=5MHz
Standby Supply Current TTL levels ISB1
CMOS levels ISB2
Output Low Voltage
Output High Voltage
VOL
VOH
max
Unit
-
40
40
µA
µA
-
240
126
69
mA
mA
mA
-
12
1.2
mA
mA
2.4
0.4
-
V
V
(1)
VIN = GND to VCC, CS =VIH
As above
As above
CS(1) = VIH, II/O = 0mA, Other Inputs = VIH
(1)
CS = VCC-0.3V, II/O = 0mA, Other Inputs = VCC
IOL = 2.1mA.
IOH = -400µA.
Notes (1) CS above are accessed through CS1-4. These inputs must be operated simultaneously for 32 bit operation, in pairs
in 16 bit mode and singly for 8 bit mode.
Capacitance (TA=25°C,ƒ=1MHz) Note: These parameters are calculated, not measured.
Parameter
Input Capacitance
Output Capacitance
Symbol
CS1-4
Other Inputs
Test Condition
typ
max Unit
CIN1
CIN2
VIN=0V
VIN=0V
-
16
34
pF
pF
COUT
VOUT=0V
-
22
pF
2
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symnbol
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable Access Time
Chip Select High to High Z Output
Output Enable High to High Z Output
Output Hold from Address Change
tRC
tAA
tCS
tOE
tHZ
tOHZ
tOH
-15
min max
-17
min max
-20
min max
150
0
0
0
0
170
0
0
0
0
200
0
0
0
0
150
150
70
50
50
-
170
170
80
50
55
-
Unit
200
200
80
50
60
-
ns
ns
ns
ns
ns
ns
ns
Notes:(1) tHZ is specified from OE or CS 1-4 whichever occurs first (Cl=5 pf).
Write Cycle
Parameter
Symbol
min
typ
max
Unit
Write Cycle Time
tWC
-
-
10
ms
Address Set-up Time
tAS
0
-
-
ns
Address Hold Time
tAH
80
-
-
ns
Output Enable Set-up Time
tOES
0
-
-
ns
Output Enable Hold Time
tOEH
0
-
-
ns
Chip Select Set-up Time
tCS
0
-
-
ns
Chip Select Hold Time
tCH
0
-
-
ns
Write Pulse Width
tWP
100
-
-
ns
Write Enable High Recovery
tWPH
100
-
-
ns
Data Set-up Time
tDS
50
-
-
ns
Data Hold Time
tDH
10
-
-
ns
Delay to Next Write
tDW
10
-
-
µs
Byte Load Cycle
tBLC
-
-
150
µs
AC Test Conditions
Output Test Load
I/O Pin
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 10ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* VCC=5V±10%
645 Ω
1.76V
100pF
3
Notes
(1)
(1)
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
AC Write Waveform - WE Controlled
OE
t OEH
t OES
ADDRESS
t AS
CE
t CH
t AH
t CS
WE
t WPH
t WP
DATA
t DS
t DH
IN
AC Write Waveform - CS Controlled
OE
t OES
t OEH
ADDRESS
t AS
CE
t AH
t CH
t CS
WE
t WPH
t WP
t DS
DATA
IN
4
t DH
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
Read Cycle Timing Waveform
Address
Address Valid
t RC
t CS
CS
t OHZ
t OE
t OLZ
OE
t HZ
t OH
t LZ
HIGH z
Dout
Output
Valid
Output
Valid
t AA
Software Protected Write Waveform
OE
CE
tDLC
tWP
WE
tAS
tWPH
tAH
A0~A6
BYTE ADDRESS
05555
02AAA
05555
PAGE ADDRESS
A7~A16
tDS
Data
AA
tDH
55
tWC
A0
Byte 0
Byte 126
Byte 127
Note: (1) A7 through A16 must specify the page address during each high to low transition of Write Enable (or Chip select).
(2) Output Enable must be high only when Write Enable and Chip Select are both low.
(3) All bytes that are not loaded within the sector being programmed will be erased to FF.
5
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
DATA Polling Waveform
WE
CS 1-4
tOEH
OE
tDH
tWR
tOE
High Z
D7,D15
D23,D31
An
A0-A14
An
An
An
An
Toggle Bit Waveform
WE
CS1-4
tOEH
OE
tOE
tDH
tWR
HIGH Z
D6
(1) Toggling either OE or CE or both OE and CE will operate toggle bit.
(2) Beginning and adding state of D7, D15, D23, D31 may vary.
(3) Any address location may be used but the address should not vary.
Page Mode Write Waveform
OE
CE
tWPH
tWP
tBLC
WE
tAS
A0-A6
A7-A16
tAH
tDH
Byte
Add
Sector
Add
tDS
Data
Byte 0
Byte 1
Byte 2
Byte 3
6
Byte 126
Byte 127
tWC
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
Device Operation
Read
The PUMA 68F4001 read operations are initiated when Write Enable is high and both Output Enable and Chip
Select are LOW. The read operation is terminated by either Chip Select or Output Enable returning HIGH. This
2-line control architecture eliminates bus connection in a system environment. The data bus will be in a high
impedance state when either Output Enable or Chip Select is HIGH.
Write
The device is reprogrammed on a sector basis. Byte loads are used to enter the 128 bytes of a sector to be
programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE
or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising edge of CE or WE.
If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte
that is not loaded during the programming of its sector will be erased to read FFh.
During a reprogram cycle, the address locations and 128 bytes of data are internally latched, freeing the address
and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase
the sector and then program the latched data using an internal control timer. The end of a program cycle can be
detected by DATA polling on D7. Once the end of a program cycle has been detected, a new access for a read
or program can begin.
Each new byte to be programmed must have its high to low transition on WE (or CE) within 150µs of the high
to low transition of WE (or CE) of the preceding byte. If a high to low transition is not detected within 150 µs of
the last low to high transition, the load period will end and the internal programming period will start. A7 to A16
specify the sector address. The sector address must be valid during each high to low transition of WE (or CE).
A0 to A6 specify the byte address within the sector. The bytes may be loaded in any order; sequential loading
is not required.
DATA Polling
In order to detect the end of a write cycle, two methods are provided. During a write operation (Byte or Page)
an attempt to read the last byte written will result in the compliment of the written data appearing on D7 (or
D15, D23 or D31, depending on the device selected). Once the write cycle is completed, true data appears on
the outputs and the next write cycle may begin. Using this method of indicating the end of a write can
effectively reduce the total write time by 50%.
TOGGLE bit
In addition to DATA polling, another method is provided to determine the end of a Write Cycle. During a write
operation successive attempts to read data will result in D6 (or D14, D22 or D30, depending on the device selected).
toggling between 1 and 0. Once a write is complete, this toggling will stop and valid data will be read as normal,
allowing the next write cycle to be performed. This can eliminate the software housekeeping chore of saving and
fetching the last address and data written in order to implement DATA polling. This can be especially helpful in
an array composed of multiple PUMA 68F4001 modules that are frequently updated.
7
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
Hardware Data Protection
Both hardware and software protection is provided as described below.
Four types of hardware protection give high security against accidental writes:
If Vcc - 3.8V, Write is inhibited.
OE low, CS or WE high inhibits inadvertant Write Cycles during power-on and power-off. Write Cycle timing
specifications must be observed concurrently.
• Pulses are less than 20ns on WE do not initiate a Write Cycle.
•
•
Software controlled data protection, once enabled by the user, means that a software algorithm must be used
before any write can be performed. To enable this feature the algorithm opposite is followed, and must be
reused for each subsequent write operation. Once set the data protection remains operational until it is
disabled by using the second algorithm overleaf: power transitions will not reset this feature.
Software Algorithms
Selecting the software data protection mode requires the host system to precede datawrite operations by a series
of three write operations to three specfic addresses. The three byte sequence opens the page write window
enabling the host to write 128 bytes of data. Once the page load cycle has been completed, the device will
automatically be returned to the data protected state
Software Data Protection Algorithm (1)
Regardless of whether the device has been protected or not, once the software data protected algorithm is used
and the data is written, the PUMA 68F4001 will automatically disable further writes unless another command is
issued to cancel it. If no further commands are issued the PUMA 68F4001 will be write protected during powerdown and any subsequent power-up.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA
(4)
TO
SECTOR (128 BYTES)
WRITES
ENABLED (2)
Notes:
(1) Data Format I/O7-I/O0 (Hex);
Once initiated, this sequence of write operations should not be interrupted.
(2) Enable Write Protect state will be initiated at end of
write even if no other data is loaded.
(3) Disable Write Protect state will be initiated at end of
write period even if no other data is loaded.
(4) 128 bytes of data must be loaded.
ENTER DATA
PROTECT
STATE
8
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
Software Data Protect Disable
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an
E2PROM programmer. The following six step algorithm will reset the internal protection circuit. After tWC, the
PUMA 68F4001 will be in standard operating mode.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT
STATE (3)
LOAD DATA XX
TO
ANY ADDRESS (4)
LOAD LAST BYTE
TO
LAST ADDRESS
9
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
Chip Erase Algorithm
The Puma 68F4001 offers a chip erase function in which the entire device can be erased by a six byte algorithm.
Once this code has been entered, the device will set each byte to a high state, (FFh) erasing any stored data. The
device will also internally time this operation so that no external clocks are needed.
The Puma 68F4001 can also be completely erased by setting the entire device to a high state. This is accomplished
by first placing OE at 12 volts with CE low and WE high: when WE is pulsed low for a minimum of 20 ms, the contents
of the entire device will be erased.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 10
TO
ADDRESS 5555
Notes :
(1) Data format: I/O7 ~I/Oo (Hex.)
(2) Data polling may be used to determine the erase cycle by checking any address for data equal to FFh.
(3) After loading the six byte code, no byte loads are allowed until the completion of the erase cycle. The erase cycle
will time itself to completion within tWC.
Operating Modes
The table below shows the logic inputs required to control the operating modes of each device on the
PUMA 68F4001.
MODE
CS OE WE OUTPUTS
Read
0
0
1
Data Out
Write
0
I
0
Data in
Standby
1
X
X
High Z
Write Inhibit
X
X
1
Write Inhibit
X
0
X
Output Disable
X
Chip Erase
0
1
X
I
0
High Z
1 = VIH 0 = VIL X = Don't care
Note : (1) Refer to AC Programming Waveforms
10
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
SCREENING
Military Screening Procedure
Screening Flow for high reliability product is in accordance with Mil-883 method 5004 .
MB MODULE SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Visual and Mechanical
1010 Condition B (10 Cycles,-55oC to +125oC)
100%
Pre-Burn-in electrical
Burn-in
Per applicable device specifications at TA=+25oC
TA=+125oC,160hrs minimum.
100%
100%
Final Electrical Tests
Per applicable Device Specification
Static (DC)
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (AC)
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
External Visual
2009 Per vendor or customer specification
100%
Temperature cycle
Burn-In
Package Information
Dimensions in mm(inches)
Plastic 68 Pin JEDEC Surface mount PLCC
25.27 (0.995) sq.
5.08
(0.200) max
25.02 (0.985) sq.
0.10 (0.004)
0.90 (0.035) typ.
11
23.11 (0.910)
0.46
(0.018) typ.
24.13 (0.950)
1.27
(0.050) typ.
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
Ordering Information
PUMA 68F4001MB-15
Speed
15 = 150 ns
17 = 170 ns
20 = 200 ns
Temp. range/screening
Blank
I
M
MB
Organisation
4001 = 128K x 32, user configurable
as 256K x 16 and 512K x 8
Memory Type
Package
=
=
=
=
Commercial Temperature
Industrial Temperature
Military Temperature
Screened in accordance with
MIL-STD-883
F = FLASH
PUMA 68 = 68 pin "J" Leaded PLCC
THIS PRODUCT IS NOT RECOMMENDED FOR NEW DESIGNS
12
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