2 Gbit (256 Mbyte) 3.0V SPI Flash Memory S70GL02GS General Description

2 Gbit (256 Mbyte) 3.0V SPI Flash Memory S70GL02GS General Description
S70GL02GS
2 Gbit (256 Mbyte)
3.0V SPI Flash Memory
General Description
The Cypress S70GL02GS 2-Gigabit MirrorBit® Flash memory device is fabricated on 65 nm MirrorBit Eclipse process technology.
This device offers a fast page access time of 25 ns with a corresponding random access time of 110 ns. It features a Write Buffer
that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective programming time
than standard single byte/word programming algorithms. This makes the device an ideal product for today’s embedded applications
that require higher density, better performance and lower power consumption.
This document contains information for the S70GL02GS device, which is a dual die stack of two S29GL01GS die. For detailed
specifications, please refer to the discrete die data sheet:
Document
Cypress Document Number
S29GL01GS Data Sheet
001-98285
Distinctive Characteristics
 CMOS 3.0 Volt Core with Versatile I/O™
 Two 1024 Megabit (S29GL01GS) in a single 64-ball
Fortified-BGA package (see S29GL01GS datasheet for full
specifications)
 65 nm MirrorBit Eclipse™ process technology
 Single supply (VCC) for read / program / erase (2.7V to 3.6V)
 Versatile I/O Feature
– Wide I/O voltage (VIO): 1.65V to VCC
 x16 data bus
 16-word/32-byte page read buffer
 512-byte Programming Buffer
– Programming in Page multiples, up to a maximum of 512
bytes
 Sector Erase
– Uniform 128-kbyes sectors
– S70GL02GS: two thousand forty-eight sectors
 Suspend and Resume commands for Program and Erase
operations
 Status Register, Data Polling, and Ready/Busy pin methods
to determine device status
 Advanced Sector Protection (ASP)
– Volatile and non-volatile protection methods for each
sector
 Separate 1024-bye One Time Program (OTP) array with two
lockable regions
– Available in each device Support for CFI (Common Flash
Interface)
 WP# input
– Protects first or last sector, or first and last sectors of each
device, regardless of sector protection settings
 Industrial temperature range (–40°C to +85°C)
 100,000 erase cycles per sector typical
 20-year data retention typical
 Packaging Options
– 64-ball LSH Fortified BGA, 13 mm x 11 mm
Performance Characteristics
Typical Program and Erase Rates
Max. Read Access Times (ns) (Note 1)
Parameter
Random Access Time (tACC)
2 Gb
110
120
Page Access Time (tPACC)
20
30
CE# Access Time (tCE)
110
120
OE# Access Time (tOE)
25
35
Notes
1. Access times are dependent on VIO operating ranges. See Ordering
Information on page 3 for further details.
Buffer Programming (512 bytes)
1.5 MB/s
Sector Erase (128 kbytes)
477 kB/s
Maximum Current Consumption
Active Read at 5 MHz, 30 pF
60 mA
Program
100 mA
Erase
100 mA
Standby
200 µA
2. Contact a sales representative for availability.
Cypress Semiconductor Corporation
Document Number: 001-98296 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised Friday, March 04, 2016
S70GL02GS
Contents
General Description ............................................................. 1
Distinctive Characteristics .................................................. 1
Performance Characteristics............................................... 1
1.
1.1
Ordering Information ................................................... 3
Recommended Combinations........................................ 3
2.
Input/Output Descriptions and Logic Symbol........... 4
3.
3.1
3.2
Block Diagrams............................................................ 5
Special Handling Instructions for BGA Package............ 8
LSH064—64 ball Fortified Ball Grid Array, 13 x 11 mm. 9
4.
Memory Map ............................................................... 10
5.
Autoselect................................................................... 10
6.
DC Characteristics..................................................... 11
7.
BGA Package Capacitance ....................................... 12
8.
Device ID and Common Flash Interface (ID-CFI) ASO
Map.............................................................................. 13
9.
Revision History......................................................... 18
Document Number: 001-98296 Rev. *F
Page 2 of 19
S70GL02GS
1.
Ordering Information
1.1
Recommended Combinations
Recommended Combinations table below list various configurations planned to be available in volume. The table below will be
updated as new combinations are released. Check with your local sales representative to confirm availability of specific
configuration not listed or to check on newly released combinations.
S29GL-S Valid Combinations
Base OPN
Package and
Temperature
Speed (ns)
Model Number
Packing Type
Ordering Part Number
(yy = Model Number, x = Packing Type)
S70GL02GS11FHI01x
110
S70GL02GS11FHI02x
01, 02
S70GL02GS
S70GL02GS11FHV01x
FHI, FHV
0, 3
S70GL02GS11FHV02x
(Note 1)
(Note 2)
S70GL02GS12FHIV1x
120
S70GL02GS12FHIV2x
V1, V2
S70GL02GS12FHVV1x
S70GL02GS12FHVV2x
Notes
1. BGA package marking omits leading “S70” and packing type designator from ordering part number.
2. Packing Type “0” is standard option.
The ordering part number is formed by a valid combination of the following:
S70GL02GS
12
F
H
I
01
0
PACKING TYPE
0 = Tray (standard)
3 = 13” Tape and Reel
MODEL NUMBER (VIO range, protection when WP# =VIL)
01 = VIO = VCC = 2.7V to 3.6V, highest address sector protected
02 = VIO = VCC = 2.7V to 3.6V, lowest address sector protected
V1 = VIO = 1.65V to VCC, VCC = 2.7V to 3.6V, highest address sector protected
V2 = VIO = 1.65V to VCC, VCC = 2.7V to 3.6V, lowest address sector protected
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
V = Automotive - In Cabin (–40°C to +105°C )
PACKAGE MATERIALS SET
H = Low Halogen, Pb-free
PACKAGE TYPE
F = Fortified Ball Grid Array, 1.0 mm pitch package (LSH064), 11 mm x 13 mm
SPEED OPTION
11 = 110 ns
12 = 120 ns
DEVICE NUMBER/DESCRIPTION
S70GL02GS
3.0 Volt-Only, 2048 Megabit (128M x 16-Bit/256M x 8-Bit) Page-Mode Flash Memory
Manufactured on 65 nm MirrorBit Eclipse process technology
Document Number: 001-98296 Rev. *F
Page 3 of 19
S70GL02GS
2.
Input/Output Descriptions and Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
Type
A26–A0
Input
DQ15–DQ0
I/O
Description
Address lines for GL02GS.
Data input/output.
CE#
Input
Chip Enable.
OE#
Input
Output Enable.
WE#
Input
Write Enable.
VCC
Supply
Device Power Supply.
VIO
Supply
Versatile IO Input.
VSS
Supply
Ground.
RY/BY#
Output
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At
VIL, the device is actively erasing or programming. At High Z, the device is in ready.
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#
Input
Write Protect/Acceleration Input. At VIL, disables program and erase functions in the
outermost sectors. At VHH, accelerates programming; automatically places device in
unlock bypass mode. Should be at VIH for all other conditions.
NC
No Connect
Not Connected. No device internal signal is connected to the package connector nor is there any
future plan to use the connector for a signal. The connection may safely be used for routing space for
a signal on a Printed Circuit Board (PCB).
DNU
Reserved
Do Not Use. A device internal signal may be connected to the package connector. The connection
may be used by Cypress for test or other purposes and is not intended for connection to any host
system signal. Any DNU signal related function will be inactive when the signal is at VIL. The signal
has an internal pull-down resistor and may be left unconnected in the host system or may be tied to
VSS. Do not use these connections for PCB signal routing channels. Do not connect any host system
signal to these connections.
RFU
No Connect
Reserved for Future Use. No device internal signal is currently connected to the package connector
but there is potential future use for the connector for a signal. It is recommended to not use RFU
connectors for PCB routing channels so that the PCB may take advantage of future enhanced features
in compatible footprint devices.
Document Number: 001-98296 Rev. *F
Page 4 of 19
S70GL02GS
3.
Block Diagrams
Figure 3.1 Block Diagram for 2 x GL01GS (Highest and Lowest Address Sectors Protected)
A26
A0 to A25
CE#
OE#
WE#
RESET#
WP#
AMAX+1 Ext
A0-A25
CE#
1 Gb Flash
(Flash 1)
OE#
WE#
RESET#
VCC
VCCQ
VCC
VIO
VSS
VSSQ
VSS
AMAX+1 Int
DQ0-15
DQ0-15
RY/BY#
RY/BY#
WP#
Amax+1 Ext
A0-A25
CE#
OE#
WE#
RESET#
VCC
VCCQ
1 Gb Flash
(Flash 2)
VSS
VSSQ
AMAX+1 Int
DQ0-15
WP#
RY/BY#
Document Number: 001-98296 Rev. *F
Page 5 of 19
S70GL02GS
Figure 3.2 Block Diagram for 2 x GL01GS (Lowest Address Sector Protected)
A26
A0 to A25
CE#
OE#
WE#
RESET#
VIO
AMAX+1 Ext
A0-A25
CE#
1 Gb Flash
(Flash 1)
OE#
WE#
RESET#
VCC
VCCQ
VCC
VIO
VSS
VSSQ
VSS
AMAX+1 Int
DQ0-15
DQ0-15
RY/BY#
RY/BY#
WP#
Amax+1 Ext
A0-A25
CE#
OE#
WE#
RESET#
VCC
VCCQ
1 Gb Flash
(Flash 2)
VSS
VSSQ
AMAX+1 Int
DQ0-15
WP#
WP#
RY/BY#
Document Number: 001-98296 Rev. *F
Page 6 of 19
S70GL02GS
Figure 3.3 Block Diagram for 2 x GL01GS (Highest Address Sector Protected)
A26
A0 to A25
CE#
OE#
WE#
RESET#
WP#
AMAX+1 Ext
A0-A25
CE#
1 Gb Flash
(Flash 1)
OE#
WE#
RESET#
VCC
VCCQ
VCC
VIO
VSS
VSSQ
VSS
AMAX+1 Int
DQ0-15
DQ0-15
RY/BY#
RY/BY#
WP#
Amax+1 Ext
A0-A25
CE#
OE#
WE#
RESET#
VCC
VCCQ
1 Gb Flash
(Flash 2)
VSS
VSSQ
AMAX+1 Int
DQ0-15
VIO
WP#
RY/BY#
Document Number: 001-98296 Rev. *F
Page 7 of 19
S70GL02GS
3.1
Special Handling Instructions for BGA Package
Special handling is required for Flash Memory products in BGA packages.
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Figure 3.4 64-ball Fortified Ball Grid Array
64-ball Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
H8
NC
A22
A23
VIO
VSS
A24
A25
NC
A7
B7
C7
D7
E7
F7
G7
H7
A13
A12
A14
A15
A16
RFU
DQ15
VSS
A6
B6
C6
D6
E6
F6
G6
H6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
WE#
RESET#
A21
A19
DQ5
DQ12
VCC
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY#
WP#
A18
A20
DQ2
DQ10
DQ11
DQ3
A3
B3
C3
D3
E3
F3
G3
H3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A2
B2
C2
D2
E2
F2
G2
H2
A3
A4
A2
A1
A0
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
H1
NC
A26
NC
NC
DNU
VIO
RFU
NC
Notes
1. Ball E1, Do Not Use (DNU), a device internal signal is connected to the package connector. The connector may be used by Cypress for test or other purposes and is
not intended for connection to any host system signal. Do not use these connections for PCB Signal routing channels. Though not recommended, the ball can be
connected to VCC or VSS through a series resistor.
2. Balls F7 and G1, Reserved for Future Use (RFU).
3. Balls A1, A8, C1, D1, H1, and H8, No Connect (NC).
Document Number: 001-98296 Rev. *F
Page 8 of 19
S70GL02GS
3.2
LSH064—64 ball Fortified Ball Grid Array, 13 x 11 mm
Figure 3.5 LSH064—64-ball Fortified Ball Grid Array (FBGA), 13 x 11 mm
NOTES:
PACKAGE
LSH 064
JEDEC
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D XE
SYMBOL
13.00 mm x 11.00 mm
PACKAGE
MIN
NOM
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3, SPP-010.
MAX
NOTE
A
---
---
1.4
PROFILE
A1
0.40
---
---
BALL HEIGHT
D
13.00 BSC
E
11.00 BSC
BODY SIZE
7.00 BSC
MATRIX FOOTPRINT
MATRIX FOOTPRINT
E1
7.00 BSC
MD
8
MATRIX SIZE D DIRECTION
ME
8
MATRIX SIZE E DIRECTION
n
64
0.50
0.60
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
BALL COUNT
0.70
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
1.00 BSC
BALL PITCH
eD
1.00 BSC
BALL PITCH
SD / SE
0.50 BSC
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
BODY SIZE
D1
b
4.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SOLDER BALL PLACEMENT
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
g1005.2 \ f16-038.15 \ 08.10.10
Document Number: 001-98296 Rev. *F
Page 9 of 19
S70GL02GS
4. Memory Map
The S70GL02GS consist of uniform 64 kword (128-kbyte) sectors organized as shown in Table 4.1.
Table 4.1 S70GL02GS Sector and Memory Address Map
Uniform Sector
Size
64 kword/128 kB
Sector
Count
2048
Sector
Range
Address Range (16-bit)
Notes
SA00
0000000h–000FFFFh
Sector Starting Address
:
:
SA2047
7FF0000H–7FFFFFFh
Sector Ending Address
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA001-SA2046) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 kB sectors have the
pattern xxx0000h-xxxFFFFh.
5. Autoselect
Table 5.1 provides the device identification codes for the S70GL02GS. For more information on the autoselect function, refer to the
S29GL-S data sheet (publication number S29GL_128S_01GS_00).
Table 5.1 Autoselect Addresses in System
Description
Address
Read Data (word/byte mode)
Manufacturer ID
(Base) + 00h
0001h
Device ID, Word 1
(Base) + 01h
227Eh
Device ID, Word 2
(Base) + 0Eh
2248h
Device ID, Word 3
(Base) + 0Fh
2201h
Secure Device Verify
(Base) + 03h
Sector Protect Verify
(SA) + 02h
For S70GL02GS highest address sector protect: XX3Fh = Not Factory Locked
XXBFh = Factory Locked
For S70GL02GS lowest address sector protect: XX2Fh = Not Factory Locked
XXAFh = Factory Locked
xx01h/01h = Locked, xx00h/00h = Unlocked
Document Number: 001-98296 Rev. *F
Page 10 of 19
S70GL02GS
6.
DC Characteristics
Table 6.1 DC Characteristics
Parameter
Description
Test Conditions
Min
Typ
(Note 2)
Max
Unit
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC max
+0.04
±2.0
µA
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC max
+0.04
±2.0
µA
ICC4
VCC Standby Current
CE#, RESET#, OE# = VIH, VIH = VIO
VIL = VSS, VCC = VCC max
140
200
µA
ICC5
VCC Reset Current (Notes 2, 7)
CE# = VIH, RESET# = VIL,
VCC = VCC max
20
40
mA
VIH = VIO, VIL = VSS ,
VCC = VCC max, tACC + 30 ns
6
12
mA
VIH = VIO, VIL = VSS,
VCC = VCC max, tASSB
200
300
µA
RESET# = VIO, CE# = VIO, OE# = VIO,
VCC = VCC max,
106
160
mA
ICC6
ICC7
Automatic Sleep Mode (Note 3)
VCC Current during power up
(Notes 2, 6)
Notes
1. ICC active while Embedded Algorithm is in progress.
2. Not 100% tested.
3. Automatic sleep mode enables the lower power mode when addresses remain stable for a designated time.
4. VIO = 1.65V to VCC or 2.7V to VCC depending on the model.
5. VCC = 3V and VIO = 3V or 1.8V. When VIO is at 1.8V, I/O pins cannot operate at >1.8V.
6. During power-up there are spikes of current demand, the system needs to be able to supply this current to insure the part initializes correctly.
7. If an embedded operation is in progress at the start of reset, the current consumption will remain at the embedded operation specification until the embedded operation
is stopped by the reset. If no embedded operation is in progress when reset is started, or following the stopping of an embedded operation, ICC7 will be drawn during
the remainder of tRPH. After the end of tRPH the device will go to standby mode until the next read or write.
8. The recommended pull-up resistor for RY/BY# output is 5k to 10k Ohms.
9. For all other DC current values please refer to the S29GL-128S_01GS_00 data sheet.
Document Number: 001-98296 Rev. *F
Page 11 of 19
S70GL02GS
7.
BGA Package Capacitance
Parameter Symbol
CIN
COUT
A26
Typ
Max
Unit
Input Capacitance
Parameter Description
15
16
pF
Output Capacitance
10
11
pF
Highest Order Address
6
7
pF
CE#
Separated Control Pin
12
13
pF
OE#
Separated Control Pin
7
8
pF
WE#
Separated Control Pin
11
12
pF
WP#
Separated Control Pin
11
12
pF
RESET#
Separated Control Pin
8
9
pF
RY/BY#
Separated Control Pin
5
6
pF
Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Document Number: 001-98296 Rev. *F
Page 12 of 19
S70GL02GS
8. Device ID and Common Flash Interface (ID-CFI) ASO Map
The Device ID portion of the ASO (word locations 0h to 0Fh) provides manufacturer ID, device ID, Sector Protection State, and basic
feature set information for the device.
ID-CFI Location 02h displays sector protection status for the sector selected by the sector address (SA) used in the ID-CFI enter
command. To read the protection status of more than one sector it is necessary to exit the ID ASO and enter the ID ASO using the
new SA. The access time to read location 02h is always tACC and a read of this location requires CE# to go High before the read and
return Low to initiate the read (asynchronous read access). Page mode read between location 02h and other ID locations is not
supported. Page mode read between ID locations other than 02h is supported.
Table 8.1 ID (Autoselect) Address Map (Sheet 1 of 2)
Description
Address
Manufacture ID
(SA) + 0000h
Device ID
(SA) + 0001h
227Eh
(SA) + 0002h
Sector Protection State (1= Sector protected, 0= Sector unprotected). This protection state
is shown only for the SA selected when entering ID-CFI ASO. Reading other SA provides
undefined data. To read a different SA protection state ASO exit command must be used
and then enter ID-CFI ASO again with the new SA.
Protection
Verification
Read Data
0001h
For S70GL02GS highest address sector protect:
For S70GL02GS lowest address sector protect:
XX3Fh = Not Factory Locked
XXBFh = Factory Locked
XX2Fh = Not Factory Locked
XXAFh = Factory Locked
DQ15-DQ08 = 1 (Reserved)
DQ7 - Factory Locked Secure Silicon Region
1 = Locked
0 = Not Locked
Indicator Bits
(SA) + 0003h
DQ6 - Customer Locked Secure Silicon Region
1 = Locked
0 = Not Locked
DQ5 = 1 (Reserved)
DQ4 - WP# Protects
0 = lowest address Sector
1 = highest address Sector
DQ3 - DQ0 = 1 (Reserved)
(SA) + 0004h
Reserved
(SA) + 0005h
Reserved
(SA) + 0006h
Reserved
(SA) + 0007h
Reserved
(SA) + 0008h
Reserved
(SA) + 0009h
Reserved
(SA) + 000Ah
Reserved
(SA) + 000Bh
Reserved
RFU
Bit 0 - Status Register Support
1 = Status Register Supported
0 = Status Register not supported
Bit 1 - DQ polling Support
1 = DQ bits polling supported
Lower Software Bits
(SA) + 000Ch
0 = DQ bits polling not supported
Bit 3-2 - Command Set Support
11 = reserved
10 = reserved
01 = Reduced Command Set
00 = Classic Command set
Bits 4-15 - Reserved = 0
Upper Software Bits
(SA) + 000Dh
Reserved
Document Number: 001-98296 Rev. *F
Page 13 of 19
S70GL02GS
Table 8.1 ID (Autoselect) Address Map (Sheet 2 of 2)
Description
Address
Device ID
(SA) + 000Eh
2248h = 2 Gb
Read Data
Device ID
(SA) + 000Fh
2201h
Table 8.2 CFI Query Identification String
Word Address
Data
(SA) + 0010h
0051h
(SA) + 0011h
0052h
(SA) + 0012h
0059h
(SA) + 0013h
0002h
(SA) + 0014h
0000h
(SA) + 0015h
0040h
(SA) + 0016h
0000h
(SA) + 0017h
0000h
(SA) + 0018h
0000h
(SA) + 0019h
0000h
(SA) + 001Ah
0000h
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set
(00h = none exists)
Address for Alternate OEM Extended Table
(00h = none exists)
Table 8.3 CFI System Interface String
Word Address
Data
(SA) + 001Bh
0027h
Description
VCC Min. (erase/program) (D7-D4: volts, D3-D0: 100 mV)
(SA) + 001Ch
0036h
VCC Max. (erase/program) (D7-D4: volts, D3-D0: 100 mV)
(SA) + 001Dh
0000h
VPP Min. voltage (00h = no VPP pin present)
(SA) + 001Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
(SA) + 001Fh
0008h
Typical timeout per single word write 2N µs
(SA) + 0020h
0009h
Typical timeout for max
multi-byte program, 2N µs
(00h = not supported)
(SA) + 0021h
0008h
Typical timeout per individual block erase 2N ms
(SA) + 0022h
0013h (2 Gb)
(SA) + 0023h
0001h
Max. timeout for single word write 2N times typical
(SA) + 0024h
0002h
Max. timeout for buffer write 2N times typical
(SA) + 0025h
0003h
Max. timeout per individual block erase 2N times typical
(SA) + 0026h
0003h
Max. timeout for full chip erase 2N times typical
(00h = not supported)
Typical timeout for full chip erase 2N ms (00h = not supported)
Document Number: 001-98296 Rev. *F
Page 14 of 19
S70GL02GS
Table 8.4 CFI Device Geometry Definition
Word Address
Data
(SA) + 0027h
001Ch (2 Gb)
(SA) + 0028h
0001h
(SA) + 0029h
0000h
Description
Device Size = 2N byte
Flash Device Interface Description 0 = x8-only, 1 = x16-only, 2 = x8/x16 capable
(SA) + 002Ah
0009h
(SA) + 002Bh
0000h
(SA) + 002Ch
0001h
(SA) + 002Dh
00XXh
(SA) + 002Eh
000Xh
(SA) + 002Fh
0000h
(SA) + 0030h
000Xh
(SA) + 0031h
0000h
(SA) + 0032h
0000h
(SA) + 0033h
0000h
(SA) + 0034h
0000h
(SA) + 0035h
0000h
(SA) + 0036h
0000h
(SA) + 0037h
0000h
(SA) + 0038h
0000h
Max. number of byte in multi-byte write = 2N
(00 = not supported)
Number of Erase Block Regions within device
1 = Uniform Device, 2 = Boot Device
Erase Block Region 1 Information (refer to JEDEC JESD68-01 or JEP137 specifications)
00FFh, 0007h, 0000h, 0002h = 2 Gb
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
(SA) + 0039h
0000h
(SA) + 003Ah
0000h
(SA) + 003Bh
0000h
(SA) + 003Ch
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
Table 8.5 CFI Primary Vendor-Specific Extended Query (Sheet 1 of 3)
Word Address
Data
Description
(SA) + 0040h
0050h
(SA) + 0041h
0052h
(SA) + 0042h
0049h
(SA) + 0043h
0031h
Major version number, ASCII
(SA) + 0044h
0035h
Minor version number, ASCII
Query-unique ASCII string “PRI”
Address Sensitive Unlock (Bits 1-0)
00b = Required
01b = Not Required
Process Technology (Bits 5-2)
0000b = 0.23 µm Floating Gate
0001b = 0.17 µm Floating Gate
(SA) + 0045h
0010b = 0.23 µm MirrorBit
001Ch
0011b = 0.13 µm Floating Gate
0100b = 0.11 µm MirrorBit
0101b = 0.09 µm Floating Gate
0110b = 0.09 µm MirrorBit
0111b = 0.065 µm MirrorBit Eclipse
1000b = 0.065 µm MirrorBit
1001b = 0.045 µm MirrorBit
(SA) + 0046h
0002h
Erase Suspend
0 = Not Supported
1 = Read Only
2 = Read and Write
Document Number: 001-98296 Rev. *F
Page 15 of 19
S70GL02GS
Table 8.5 CFI Primary Vendor-Specific Extended Query (Sheet 2 of 3)
Word Address
(SA) + 0047h
Data
Description
0001h
Sector Protect
00 = Not Supported
0000h
Temporary Sector Unprotect
00 = Not Supported
X = Number of sectors in smallest group
(SA) + 0048h
01 = Supported
(SA) + 0049h
0008h
Sector Protect/Unprotect Scheme
04 = High Voltage Method
05 = Software Command Locking Method
08 = Advanced Sector Protection Method
(SA) + 004Ah
0000h
Simultaneous Operation
00 = Not Supported
X = Number of banks
(SA) + 004Bh
0000h
Burst Mode Type
00 = Not Supported
01 = Supported
Page Mode Type
00 = Not Supported
(SA) + 004Ch
01 = 4 Word Page
0003h
02 = 8 Word Page
03=16 Word Page
(SA) + 004Dh
0000h
ACC (Acceleration) Supply Minimum
00 = Not Supported
D7-D4: Volt
D3-D0: 100 mV
(SA) + 004Eh
0000h
ACC (Acceleration) Supply Maximum
00 = Not Supported
D7-D4: Volt
D3-D0: 100 mV
WP# Protection
00h = Flash device without WP Protect (No Boot)
01h = Eight 8 kB Sectors at TOP and Bottom with WP (Dual Boot)
(SA) + 004Fh
02h = Bottom Boot Device with WP Protect (Bottom Boot)
0004h (Bottom)
03h = Top Boot Device with WP Protect (Top Boot)
0005h (Top)
04h = Uniform, Bottom WP Protect (Uniform Bottom Boot)
05h = Uniform, Top WP Protect (Uniform Top Boot)
06h = WP Protect for all sectors
07h = Uniform, Top or Bottom WP Protect
(SA) + 0050h
0001h
Program Suspend
00 = Not Supported
0000h
Unlock Bypass
00 = Not Supported
01 = Supported
(SA) +0051h
01 =Supported
(SA) + 0052h
0009h
Secured Silicon Sector (Customer OTP Area) Size 2N (bytes)
Software Features
bit 0: status register polling (1 = supported, 0 = not supported)
bit 1: DQ polling (1 = supported, 0 = not supported)
bit 2: new program suspend/resume commands (1 = supported, 0 = not supported)
(SA) + 0053h
bit 3: word programming (1 = supported, 0 = not supported)
008Fh
bit 4: bit-field programming (1 = supported, 0 = not supported)
bit 5: autodetect programming (1 = supported, 0 = not supported)
bit 6: RFU
bit 7: multiple writes per Line (1 = supported, 0 = not supported)
(SA) + 0054h
0005h
Page Size = 2N bytes
Document Number: 001-98296 Rev. *F
Page 16 of 19
S70GL02GS
Table 8.5 CFI Primary Vendor-Specific Extended Query (Sheet 3 of 3)
Word Address
Data
(SA) + 0055h
0006h
Erase Suspend Timeout Maximum < 2N (µs)
Description
(SA) + 0056h
0006h
Program Suspend Timeout Maximum < 2N (µs)
(SA) + 0078h
0006h
Embedded Hardware Reset Timeout Maximum < 2N (µs)
Reset with Reset Pin
(SA) + 0079h
0009h
Non-Embedded Hardware Reset Timeout Maximum < 2N (µs)
Power on Reset
Document Number: 001-98296 Rev. *F
Page 17 of 19
S70GL02GS
9. Revision History
Spansion Publication Number: S70GL-S_00
Section
Description
Revision 01 (May 19, 2011)
Initial release
Revision 02 (July 8, 2011)
Performance Characteristics
Updated Typical Program and Erase Rates
Ordering Information
Updated model number description of V1 and V2
DC Characteristics
Modified Note 3
Revision 03 (September 23, 2011)
Distinctive Characteristics
Cosmetic changes
Order Information
Updated
CFI Device Geometry Definition
Data at (SA) + 002Eh modified
Revision 04 (December 15, 2011)
Global
Data sheet designation changed from Preliminary to Full Production
Performance Characteristics
Updated Sector Erase time
Figure: 64-ball Fortified Ball Grid Array
Added notes
BGA Package Capacitance
Updated
Revision 05 (June 27, 2014)
Global
Added –40°C to +105°C temperature range
Document History Page
Document Title: S70GL02GS 2 Gbit (256 Mbyte) 3.0V SPI Flash Memory
Document Number: 001-98296
Rev.
ECN No.
Orig. of
Change
Submission
Date
**

BWHA
05/19/2011
Initial release
Description of Change
*A

BWHA
07/08/2011
Performance Characteristics: Updated Typical Program and Erase Rates
Ordering Information: Updated model number description of V1 and V2
DC Characteristics: Modified Note 3
*B

BWHA
09/23/2011
Distinctive Characteristics: Cosmetic changes
Ordering Information: Updated
CFI Device Geometry Definition: Data at (SA) + 002Eh modified

BWHA
12/15/2011
Global: Data sheet designation changed from Preliminary to Full Production
Performance Characteristics: Updated Sector Erase time
Figure: 64-ball Fortified Ball Grid Array: Added notes
BGA Package Capacitance: Updated
*D

BWHA
06/27/2014
Global: Added –40°C to +105°C temperature range
*E
4871480
BWHA
08/13/2015
Updated to Cypress template
03/04/2016
General Description: Updated Cypress Document Number as “001-98285” in
the table.
Distinctive Characteristics: Updated link to S29GL01GS datasheet.
Updated to new template.
*C
*F
5157725
TOCU
Document Number: 001-98296 Rev. *F
Page 18 of 19
S70GL02GS
Sales, Solutions, and Legal Information
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Community | Forums | Blogs | Video | Training
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USB Controllers
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Wireless/RF
cypress.com/wireless
© Cypress Semiconductor Corporation 2011-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 001-98296 Rev. *F
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Revised Friday, March 04, 2016
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