User manual | STM32F372xx STM32F373xx

shows the general block diagram of the STM32F37x family.

UFBGA100 package available on 256-KB versions only.

Doc ID 022691 Rev 1 9/120

Device overview

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10/120 Doc ID 022691 Rev 1

STM32F37x

Example given for STM32F373xx device.

Device overview

2.1 ARM

Cortex™-M4 core

2.1.1 ARM

Cortex™-M4 core with embedded Flash and SRAM

The ARM Cortex-M4 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The ARM Cortex-M4 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.

With its embedded ARM core, the STM32F37x family is compatible with all ARM tools and software.

Figure 1

2.1.2 Memory protection unit

The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

●

The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:

Outstanding processing performance combined with fast interrupt handling

Enhanced system debug with extensive breakpoint and trace capabilities

Efficient processor core, system and memories

Ultralow power consumption with integrated sleep modes

Platform security robustness with optional integrated memory protection unit (MPU).

With its embedded ARM core, the STM32F37x devices are compatible with all ARM development tools and software.

Doc ID 022691 Rev 1 11/120

Device overview

2.2

STM32F37x

Nested vectored interrupt controller (NVIC)

The STM32F37x devices embed a nested vectored interrupt controller (NVIC) able to handle up to 60 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

●

Closely coupled NVIC gives low latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving higher priority interrupts

Support for tail chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

The external interrupt/event controller consists of 29 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 84

GPIOs can be connected to the 16 external interrupt lines.

2.4

2.5 Embedded Flash memory

All STM32F37x devices feature up to 256 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above).

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

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STM32F37x Device overview

2.7

All STM32F37x devices feature up to 32 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed

APB domain is 36 MHz.

At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:

●

Boot from user Flash

Boot from system memory

Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1, USART2 or USB.

2.9.1

2.9.2

Power supply schemes

●

DD: external power supply for I/Os and the internal regulator. It is provided externally through V

DD pins, and can be 2.0 to 3.6 V.

DDA

= 2.0 to 3.6 V:

– external analog power supplies for Reset blocks, RCs and PLL

– supply voltage for 12-bit ADC, DACs and comparators (minimum voltage to be applied to V

DDA

is 2.4 V when the 12-bit ADC and DAC are used).

SDADC1_VDD/SDADC2_VDD and SDADC3_VDD = 2.2 V to 3.6: supply voltages for

SDADC1/2 and SDADCD3 sigma delta ADCs. Independent from V

DDA

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

DD is not present.

Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains

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Device overview STM32F37x

in reset mode when V

DD is below a specified threshold, V

POR/PDR

, without the need for an external reset circuit.

●

The POR monitors only the V

supply voltage. During the startup phase it is required that V

DDA

should arrive first and be greater than or equal to V

The PDR monitors both the V

and V

DDA

supply voltages, however the V

DDA

power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V

DDA

is higher than or equal to V

The device features an embedded programmable voltage detector (PVD) that monitors the

DD power supply and compares it to the V

PVD threshold. An interrupt can be generated when V

DD drops below the V

PVD threshold and/or when V

DD is higher than the V

PVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

●

The regulator has three operation modes: main (MR), low power (LPR), and power-down.

The MR mode is used in the nominal regulation mode (Run)

The LPR mode is used in Stop mode.

The power-down mode is used in Standby mode: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The voltage regulator is always enabled after reset. It is disabled in Standby mode.

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The STM32F37x supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

●

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

●

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the USARTs, the I2Cs, the

CEC, the USB wakeup, and the RTC alarm.

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

Doc ID 022691 Rev 1

STM32F37x

Note:

Device overview

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

2.11 Real-time clock (RTC) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

DD supply when present or through the V

BAT pin.The backup registers are thirty two 32-bit registers used to store 128 bytes of user application data when V

DD power is not present.

They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode.

●

The RTC is an independent BCD timer/counter. Its main features are the following:

●

Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.

2 programmable alarms with wake up from Stop and Standby mode capability.

Periodic wakeup unit with programmable resolution and period.

●

On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy.

●

3 anti-tamper detection pins with programmable filter. The MCU can be woken up from

Stop and Standby modes on tamper event detection.

Timestamp feature which can be used to save the calendar content. This function can triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.

The RTC clock sources can be:

●

A 32.768 kHz external crystal

A resonator or oscillator

The internal low-power RC oscillator (typical frequency of 40 kHz)

The high-speed external clock divided by 32

2.12 DMA (direct memory access)

The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

The two DMAs can be used with the main peripherals: SPIs, I2Cs, USARTs, DACs, ADC,

SDADCs, general-purpose timers.

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Device overview

2.13

STM32F37x

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

2.14 Touch sensing controller (TSC)

The device has an embedded independent hardware controller (TSC) for controlling touch sensing acquisitions on the I/Os.

Up to 24 touch sensing electrodes can be controlled by the TSC. The touch sensing I/Os are organized in 8 acquisition groups, with up to 4 I/Os in each group.

Table 3.

Capacitive sensing GPIOs available on STM32F37x devices

Pin name

Capacitive sensing group name

Pin name

Capacitive sensing group name

PA6

PA7

PC4

PC5

PB0

PB1

PE2

PE3

PE4

PE5

PA0

PA1

PA2

PA3

PA4

PA5

G1_IO1

G1_IO2

G1_IO3

G1_IO4

G2_IO1

G2_IO2

G2_IO3

G2_IO4

G3_IO1

G3_IO2

G3_IO3

G3_IO4

G7_IO1

G7_IO2

G7_IO3

G7_IO4

PB6

PB7

PB14

PB15

PD8

PD9

PD12

PD13

PD14

PD15

PA9

PA10

PA13

PA14

PB3

PB4

G4_IO1

G4_IO2

G4_IO3

G4_IO4

G5_IO1

G5_IO2

G5_IO3

G5_IO4

G6_IO1

G6_IO2

G6_IO3

G6_IO4

G8_IO1

G8_IO2

G8_IO3

G8_IO4

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STM32F37x Device overview

Table 4.

No. of capacitive sensing channels available on STM32F37x devices

Number of capacitive sensing channels

Analog I/O group

STM32F37xCx STM32F37xRx STM32F37xVx

Number of capacitive sensing channels

17 24

2.15 12-bit ADC (analog-to-digital converter)

The 12-bit analog-to-digital converter is based on a successive approximation register

(SAR) architecture. It has up to 16 external channels (AIN15:0) and 3 internal channels

(temperature sensor, voltage reference, VBAT voltage measurement) performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the timers (TIMx) can be internally connected to the ADC start and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

The temperature sensor (TS) generates a voltage V

SENSE that varies linearly with temperature.

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

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Device overview STM32F37x

Table 5.

Temperature sensor calibration values

Calibration value name Description

TS_CAL1

TS_CAL2

TS ADC raw data acquired at temperature of 30 °C,

DDA

= 3.3 V

TS ADC raw data acquired at temperature of 110 °C

DDA

= 3.3 V

Memory address

0x1FFF F7B8 - 0x1FFF F7B9

0x1FFF F7C2 - 0x1FFF F7C3

2.15.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

) provides a stable (bandgap) voltage output for the

ADC and Comparators. V

REFINT precise voltage of V

REFINT

is internally connected to the ADC_IN17 input channel. The

is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 6.

Temperature sensor calibration values

Calibration value name Description

VREFINT_CAL

Raw data acquired at temperature of 30 °C

DDA

= 3.3 V

Memory address

0x1FFF F7BA - 0x1FFF F7BB

2.15.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT

battery voltage using the internal ADC channel ADC_IN18. As the V

BAT

voltage may be higher than V

DDA

, and thus outside the ADC input range, the V

BAT

pin is internally connected to a divider by 2.

As a consequence, the converted digital value is half the V

BAT

voltage.

2.16 16-bit sigma delta analog-to-digital converters (SDADC)

Up to three 16-bit sigma-delta analog-to-digital converters are embedded in the

STM32F37x. They have up to two separate supply voltages allowing the analog function voltage range to be independent from the STM32F37x power supply. They share up to 21 input pins which may be configured in any combination of single-ended (up to 21) or differential inputs (up to 11).

The conversion speed is up to 16.6 ksps for each SDADC when converting multiple channels and up to 50 ksps per SDADC if single channel conversion is used. There are two conversion modes: single conversion mode or continuous mode, capable of automatically scanning any number of channels. The data can be automatically stored in a system RAM buffer, reducing the software overhead.

A timer triggering system can be used in order to control the start of conversion of the three

SDADCs and/or the 12-bit fast ADC. This timing control is very flexible, capable of triggering simultaneous conversions or inserting a programmable delay between the ADCs.

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STM32F37x Device overview

Up to two external reference pins (SD_V

REF+

, SD_V

REF-

) and an internal 1.2/1.8V reference can be used in conjunction with a programmable gain (x0.5 to x32) in order to fine-tune the input voltage range of the SDADC.

2.17 DAC (digital-to-analog converter)

The devices feature up to two 12-bit buffered DACs with three output channels that can be used to convert three digital signals into three analog voltage signal outputs. The internal structure is composed of integrated resistor strings and an amplifier in inverting configuration.

●

This digital Interface supports the following features:

●

Up to two DAC converters with three output channels:

– DAC1 with two output channels

– DAC2 with one output channel.

8-bit or 12-bit monotonic output

Left or right data alignment in 12-bit mode

Synchronized update capability

Noise-wave generation triangular-wave generation

Dual DAC channel independent or simultaneous conversions (DAC1 only)

DMA capability for each channel

External triggers for conversion

2.19

The STM32F37x embeds up to 2 comparators with rail-to-rail inputs and high-speed output.

The reference voltage can be internal or external (delivered by an I/O).

The threshold can be one of the following:

●

DACs channel outputs

External I/O

Internal reference voltage (V

REFINT

)

REFINT

) or submultiple (1/4 V

REFINT

, 1/2 V

REFINT

and 3/4

The comparators can be combined into a window comparator.

Both comparators can wake up the device from Stop mode and generate interrupts and breaks for the timers.

Timers and watchdogs

The STM32F37x includes two 32-bit and nine 16-bit general-purpose timers, three basic timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers.

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Device overview STM32F37x

Table 7.

Timer type

Generalpurpose

Basic

Timer feature comparison

Timer

TIM2

TIM5

TIM3,

TIM4,

TIM19

TIM12

TIM15

TIM13,

TIM14

TIM16,

TIM17

TIM6,

TIM7,

TIM18

Counter resolution

32-bit

16-bit

Counter type

Prescaler factor

DMA request generation

Up, Down,

Up/Down

Any integer between 1 and 65536

Up, Down,

Up/Down

Any integer between 1 and 65536

Yes

Capture/ compare

Channels

Complementary outputs

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STM32F37x Device overview

2.19.1 General-purpose timers (TIM2 to TIM5, TIM12 to TIM17, TIM19)

There are eleven synchronizable general-purpose timers embedded in the STM32F37x (see

Table 7

for differences). Each general-purpose timer can be used to generate PWM outputs,

or act as a simple time base.

●

TIM2, 3, 4, 5 and 19

These five timers are full-featured general-purpose timers:

–

TIM2 and TIM5 have 32-bit auto-reload up/downcounters and 32-bit prescalers

TIM3, 4, and 19 have 16-bit auto-reload up/downcounters and 16-bit prescalers.

●

These timers all feature 4 independent channels for input capture/output compare,

PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

TIM12, 13, 14, 15, 16, 17

These six timers general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

–

TIM12 has 2 channels

TIM13 and TIM14 have 1 channel

TIM15 has 2 channels and 1 complementary channel

TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB1 clock (PCLK1) derived from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

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Device overview STM32F37x

●

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

A 24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0.

Programmable clock source

2.20.1 I

C bus

Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz) modes with

20 mA output drive. They support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters.

Table 8.

Benefits

Drawbacks

Comparison of I2C analog and digital filters

Pulse width of suppressed spikes



50 ns

Analog filter

Available in Stop mode

Variations depending on temperature, voltage, process

Digital filter

Programmable length from 1 to 15

I2C peripheral clocks

1. Extra filtering capability vs. standard requirements.

2. Stable length

Disabled when Wakeup from Stop mode is enabled

In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,

Host notify protocol, hardware CRC (PEC) generation/verification, timeout verifications and

ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the application to wake up the MCU from Stop mode on address match.

The I2C interfaces can be served by the DMA controller

The STM32F37x embeds three universal synchronous/asynchronous receiver transmitters

(USART1, USART2 and USART3).

All USARTs interfaces are able to communicate at speeds of up to 9 Mbit/s.

They provide hardware management of the CTS and RTS signals, they support IrDA SIR

ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode, Smart Card mode (ISO 7816 compliant), autobaudrate feature and have LIN Master/Slave capability.The USART interfaces can be served by the DMA controller.

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STM32F37x Device overview

2.20.3 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate at up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

The SPIs can be served by the DMA controller.

electronics control (CEC)

The device embeds a HDMI-CEC controller that provides hardware support for the

Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception.

Three standard I

S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with

16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I

S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

2.20.7

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

Universal serial bus (USB)

The STM32F37x embeds an USB device peripheral compatible with the USB full-speed 12

Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48

MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

Doc ID 022691 Rev 1 23/120

Device overview STM32F37x

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

The ARM embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F37x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

24/120 Doc ID 022691 Rev 1

STM32F37x

3 Pinouts and pin description

Figure 2.

STM32F37x LQFP48 pinout

Pinouts and pin description

6"!4

0#4!-0%27+50

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0!4!-0%27+50

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3$?62%&

-36

Doc ID 022691 Rev 1 25/120

Pinouts and pin description

Figure 3.

STM32F37x LQFP64 pinout

STM32F37x

6"!4

0#4!-0%27+50

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0#/3#?/54

0&/3#?).

0&/3#?/54

.234

633!3!2?6333!2?62%&

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0!4!-0%27+50

PINS

3$?62%&

-36

26/120 Doc ID 022691 Rev 1

STM32F37x

Figure 4.

STM32F37x LQFP100 pinout

Pinouts and pin description

0%4!-0%27+50

6"!4

0#4!-0%27+50

0#/3#?).

0#/3#?/54

0&/3#?).

0&/3#?/54

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!$#?62%&

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PINS

6$$?

633?

3$?62%&

3$!$#?6$$

-36

Doc ID 022691 Rev 1 27/120

Pinouts and pin description STM32F37x

Table 9.

STM32F37x BGA100 pinout

2 3 4 5

PE3 PE1

6 7 8 9 10 11 12

PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12

PE4 PE2 PB9 PB7 PB6

PC13_

TAMPE

R1-

WKUP2

PE5 PE0

PC14-

OSC32

_ IN

PE6-

TAMPE

R3-

WKUP3

PC15-

OSC32

_ OUT

VBAT

VSS_1

PF4

VDD_1 PB5

PD6 PD4 PD3 PD1 PC12 PC10 PA11

PD2 PD0 PC11 PF6

PA9

PC8

PA8

PC7

PA10

PC9

PC6

PF0-

OSC_

PF1-

OSC_

OUT

PF9

PF10

VSS_3

SDAD

C1_SD

ADC2_

SDAD

C3_VS

VDD_3

SDAD

C1_SD

ADC2_

VDD

PC0-

ADC10

NRST VDD_2 PD15 PD14 PD13

PF2 PC1 PC2

VSSA-

ADC_V

SS-

ADC_

VREF-

PC3

ADC_

VREF+

PA0-

TAMPE

R2-

WKUP1

VDDA-

ADC_V

PA1

PA2

PA3

PA4

PA5 PC4

PA6

PA7

PC5

PB0

PB2

PB1

PE8 PE10 PE12 PB10

SD_

VREF-

SDAD

C3_

VDD

PE7

PD9

PE9

PD8

PD12 PD11 PD10

PB15 PB14

SD_

VREF+

PE11 PE13 PE14 PE15

28/120 Doc ID 022691 Rev 1

STM32F37x Pinouts and pin description

Table 10.

Name

Legend/abbreviations used in the pinout table

Abbreviation Definition

Pin name

Pin type

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S Supply pin

I/O

FTf

Input only pin

Input / output pin

5 V tolerant I/O

5 V tolerant I/O, FM+ capable

I/O structure

Notes

TTa

RST

3.3 V tolerant I/O directly connected to ADC

Standard 3.3V I/O

Dedicated BOOT0 pin

Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Alternate functions

Functions selected through GPIOx_AFR registers

Pin functions

Additional functions

Functions directly selected/enabled through peripheral registers

Table 11.

STM32F37x pin definitions

Pin numbers

Pin name

(function after reset)

Pin type

Pin functions

Alternate function Additional functions

E2 1 1

PE2

PE3

PE4

PE5

PE6 -

TAMPER3 -

WKUP3

VBAT

PC13 -

TAMPER1 -

WKUP2

PC14 -

OSC32_IN

I/O FT

I/O

TTa

I/O TC

TRACED3, RTC_TAMPER3

RTC_TAMPER1

WKUP3

WKUP2_ALARM_OUT_

CALIB_OUT_TIMESTAMP

OSC32_IN

Doc ID 022691 Rev 1 29/120

Pinouts and pin description STM32F37x

Table 11.

STM32F37x pin definitions (continued)

Pin numbers

Pin name

(function after reset)

Pin type

Pin functions

Alternate function Additional functions

PC15 -

OSC32_OUT

PF9

PF10

PF0 -

OSC_IN

PF1 -

OSC_OUT

NRST

PC0

PC1

J3 10

L2 14 10

PF2

VSSA /

ADC_VSS /

ADC_

VREF-

VDDA ,

ADC_VDD ,

ADC_

VREF+

VDDA ,

ADC_VDD

ADC_

VREF+

PA0 -

TAMPER2 -

WKUP1

15 11

PC2

PC3

PA1

I/O TC

I/O FT

TIM14_CH1

I2C2_SDA

I2C2_SCL

I/O

RST

TTa

I/O FT

TIM5_CH1_ETR

TIM5_CH2

SPI2_MISO, I2S2_MCK,

TIM5_CH3

SPI2_MOSI, I2S2_SD,

TIM5_CH4

I2C2_SMBAI

I/O

TTa

OSC32_OUT

OSC_IN

OSC_OUT

ADC_IN10

ADCIN11

ADC_IN12

ADC_IN13

USART2_CTS,TIM2_CH1_ET,

TIM5_CH1_ETR,TIM19_CH1,

G1_IO1,COMP1_OUT

RTC_ TAMPER2, WKUP1,

ADC_IN0,COMP1_INn

SPI3_SCK_I2S3_CK,

USART2_RTS,TIM2_CH2,

TIM15_CH1N,TIM5_CH2,

TIM19_CH2,G1_IO2,

RTC_REF_CLK_IN

ADC_IN1,COMP1_INp

30/120 Doc ID 022691 Rev 1

STM32F37x Pinouts and pin description

Table 11.

STM32F37x pin definitions (continued)

Pin numbers

Pin name

(function after reset)

Pin type

Pin functions

Alternate function Additional functions

25 K3 16 12

26 L3 18 13

32 M4 23

35 M5 26 18

36 M6 27 19

37 L6 28 20

PA2

PA3

H3 19 17

PF4

VDD_2

29 M3 20 14

30 K4 21 15

31 L4 22 16

38 M7

39 L7 29 21

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PE7

PE8

I/O

TTa

COMP2_OUT ,SPI3_MISO,

I2S3_MCK, USART2_TX,

TIM2_CH3, TIM15_CH1,

TIM5_CH3,TIM19_CH3,

TIM2_OUT, G1_IO3

SPI3_MOSI,I2S3_SD,

USART2_RX,TIM2_CH4,

TIM15_CH2,TIM5_CH4,

TIM19_CH4,G1_IO4

I/O

ADC_IN2,

COMP2_INn

ADC_IN3 ADC_IN3,

COMP2_Inp

TTa

SPI1_NSS,I2S1_WS,

SPI3_NSS_I2S3_WS,

TIM2_CK,TIM3_CH2,

TIM12_CH1,G2_IO1,

COMP1_OUT

SPI1_SCK,I2S1_CK,CEC,

TIM2_CH1_ETR,

TIM14_CH1,TIM12_CH2,

G2_IO2

SPI1_MISO,I2S1_MCK,

TIM3_CH1, TIM13_CH1,

TIM16_CH1,COMP1_OUT,

G2_IO3

ADC_IN4, DAC1_OUT1

ADC_IN5, DAC1_OUT2

ADC_IN6, DAC2_OUT1

G2_IO4,SPI1_MOSI,I2S1_SD,

TIM14_CH1,TIM17_CH1,

TIM3_CH1

COMP2_OUT,ADC_IN7

TIM1_TX,TIM13_CH1,G3_IO1

TIM1_RX,G3_IO2

SPI1_MOSI,I2S1_SD,

TIM3_CH3,G3_IO3

ADC_IN14

ADC_IN15

ADC_IN8,

SDADC1_ADC_IN6P

TIM3_CH4,G3_IO4/AIN9

SDADC1_5P,

SDADC1_AIN6M

SDADC1_AIN4P,

SDADC2_AIN6P

SDADC1_AIN3P,

SDADC1_AIN4M,

SDADC2_AIN5P,

SDADC2_AIN6M

SDADC1_AIN8P,

SDADC2_AIN8P

Doc ID 022691 Rev 1 31/120

Pinouts and pin description STM32F37x

Table 11.

STM32F37x pin definitions (continued)

Pin numbers

Pin name

(function after reset)

Pin type

Pin functions

Alternate function Additional functions

M10

30 22 PE9

PE10

PE11

PE12

PE13

I/O

TTa

USART3_RX

SPI2_SCK_I2S2_CK,USART3

_TX,CEC,SYNC

SDADC1_AIN7P,

SDADC1_AIN8M,

SDADC2_AIN7P,

SDADC2_AIN8M

SDADC1_AIN2P

SDADC1_AIN1P,

SDADC1_AIN2M,

SDADC2_AIN4P

SDADC1_AIN0P,

SDADC2_AIN3P,

SDADC2_AIN4M

SDADC1_AIN0M ,

SDADC2_AIN2P

SDADC2_AIN1P,

SDADC2_AIN2M

SDADC2_AIN0P

TIM2_CH3,

SDADC2_AIN0M

M11

M12

L10

PE14

PE15

PB10

L11

F12

SD_VREF-

SDADC1,

SDADC2_

SDADC3_

VSS

G12

31 23

SD1_

SD2_

SDADC3_

VSS ,

SD_VREF-

SDADC1,SD

ADC2_ VDD

L12

32 24

K12 33 25

SD1_

SD2 _VDD,

SDADC3_

VDD

SDADC3_

VDD

SD_VREF+

I/O

53 K11 34 26 PB14 I/O TTa

SPI2_MISO,I2S2_MCK,

USART3_RTS,

TIM15_CH1,TIM12_CH1,

G6_IO1

SDADC3_AIN8P

32/120 Doc ID 022691 Rev 1

STM32F37x Pinouts and pin description

55 K9 36 28

56 K8

57 J12

58 J11

59 J10

60 H12

H11

H10

63 E12 37

64 E11 38

65 E10 39

66 D12 40

Table 11.

STM32F37x pin definitions (continued)

Pin numbers

Pin name

(function after reset)

Pin type

Pin functions

Alternate function Additional functions

54 K10 35 27

67 D11 41 29

68 D10 42 30

69 C12 43 31

70 B12 44 32

PB15

PD13

PD14

PD15

PC6

PC7

PC8

PC9

PD8

PD9

PD10

PD11

PD12

PA8

PA9

PA10

PA11

I/O

TTa

SPI2_MOSI,I2S2_SD,

TIM15_CH1N,TIM15_CH2,

TIM12_CH2,G6_IO2

SDADC3_7P,SDADC3_AIN8

M,RTC_REFCLKIN

SPI2_SCK,I2S2_CK,USART3_

TX,G6_IO3

SDADC3_AIN6P

USART3_RX,G6_IO4

USART3_CK

SDADC3_AIN5P,

SDADC3_AIN6M

SDADC3_AIN4P

USART3_CTS

USART3_RTS

SDADC3_AIN3P,

SDADC3_AIN4M

TIM4_CH1,G8_IO1,

SDADC3_AIN2P

TIM4_CH2,G8_IO2

TIM4_CH3,G8_IO3

TIM4_CH4,G8_IO4

I2S2_MCK,SPI1_NSS,

I2S1_WS, TIM3_CH1

SDADC3_AIN1P,

SDADC3_AIN2M

SDADC3_AIN0P

SDADC3_AIN0M

I2S3_MCK,SPI1_SCK,

I2S1_CK,TIM3_CH2

SPI1_MISO,TIM3_CH3

SPI1_MOSI,I2S1_SD,

TIM3_CH4

SPI2_SCK_I2S2_CK,

I2C2_SMBAl,

USART1_CK,TIM4_ETR,

TIM5_CH1_ETR,CLK_CLKOU

SPI2_MISO_I2S2_MCK,

I2C2_SCL,USART1_TX,

TIM2_CH3,TIM15_BKIN,

TIM13_CH1,G4_IO1

SPI2_MOSI_I2S2_SD,

TIM2_SDA,USART1_RX,

TIM2_CH4,TIM17_BKIN,

TIM14_CH1,G4_IO2

SPI2_NSS,I2S2_WS,SPI1_NS

S,I2S1_WS,USART1_CTS,

USBDM,CAN_RX,TIM4_CH1,

TIM5_CH2, COMP1_OUT

Doc ID 022691 Rev 1 33/120

Pinouts and pin description STM32F37x

73 C11 47 35

F11

G11

48 36

76 A10 49 37

PF6

VSS_3

VDD_3

PF7

PA14

78 B11 51

79 C10 52

80 B10 53

C8 54

84 B8

85 B7

86 A6

87 B6

Table 11.

STM32F37x pin definitions (continued)

Pin numbers

Pin name

(function after reset)

Pin type

Pin functions

Alternate function Additional functions

71 A12 45 33

72 A11 46 34

77 A9 50 38

PA12

PA13

PA15

PC10

PC11

PC12

PD0

PD1

PD2

PD3

PD4

PD5

PD6

I/O

SPI1_SCK,I2S1_CK,USART1_

RTS, USBDP, CAN_TX,

TIM16_CH1,TIM4_CH2,

TIM5_CH3, COMP2_OUT

SPI1_MISO,I2S1_MCK,

USART3_CTS,IR_OUT,

TIM16_CH1N,TIM4_CH3,

TIM5_CH4,G4_IO3,SWDAT,

JTMS

SPI1_MOSI,I2S1_SD,

USART2_SCL,USART3_RTS,

TIM4_CH4,I2C2_SCL

I/O

I2C2_SDA,USART2_CK

I2C1_SDA,USART2_TX,

TIM12_CH1,G4_IO4,SWCLK,

JTCK

SPI1_NSS,I2S1_WS,SPI3_NS

S,I2S3_WS,I2C1_SCL,

USART2_RX,TIM2_CH1_ETR,

TIM12_CH2,SYNC, JTDI

SPI3_SCK,I2S3_CK,

USART3_TX, TIM19_CH1

SPI3_MISO,I2S3_MCK,

USART3_RX, TIM19_CH2

SPI3_MOSI,I2S3_SD,

USART3_CK, TIM19_CH3

CAN_RX,TIM19_CH4

CAN_TX,TIM19_ETR

TIM3_ETR

SPI2_MISO,I2S2_MCK,

USART2_CTS

SPI2_MOSI,I2S2_SD,

USART2_RTS

USART2_TX

SPI2_NSS_I2S2_WS,

USART2_RX

34/120 Doc ID 022691 Rev 1

STM32F37x Pinouts and pin description

Table 11.

STM32F37x pin definitions (continued)

Pin numbers

Pin name

(function after reset)

Pin type

Pin functions

Alternate function Additional functions

88 A5

89 A8 55 39

90 A7 56 40

91 C5 57 41

92 B5 58 42

93 B4 59 43

94 A4 60 44

95 A3 61 45

96 B3 62 46

100

63 47

64 48

PD7

PB3

PB4

PB5

PB6

PB7

BOOT0

PB8

PB9

I/O

PE0

PE1

I/O

VSS_1 S

VDD_1 S

SPI2_SCK_I2S2_CK,

USART2_CK

SPI1_SCK,I2S1_CK,SPI3_SC

K,I2S3_CK,USART2_TX,

TIM2_CH2,TIM3_ETR,

TIM4_ETR,TIM13_CH1,G5_IO

1,JTDO, TRACESWO

SPI1_MISO,I2S1_MCK,SPI3_

MISO,I2S3_MCK,USART2_RX

TIM16_CH1,TIM3_CH1,

TIM17_BKIN,TIM15_CH1N,

G5_IO2, JNTRST

SPI1_MOSI,I2S1_SD,

SPI3_MOSI,I2S3_SD,I2C1_S

MBAl,USART2_CK,TIM16_BKI

N,TIM3_CH2,TIM17_CH1,

TIM19_ETR

I2C1_SCL,USART1_TX,TIM16

_CH1N,TIM3_CH3,TIM4_CH1,

TIM19_CH1,

TIM15_CH1,G5_IO3

I2C1_SDA,USART1_RX,

TIM17_CH1N,

TIM3_CH4,TIM4_CH2,

TIM19_CH2,

TIM15_CH2,G5_IO4

SPI2_SCK,I2S2_CK,I2C1_SC

L,USART3_TX,CAN_RX,CEC,

TIM16_CH1,TIM4_CH3,

TIM19_CH3,

COMP1_OUT,SYNC

SPI2_NSS,I2S2_WS,I2C1_SD

A,USART3_RX,CAN_TX,IR_O

UT,TIM17_CH1,TIM4_CH4,

TIM19_CH4, COMP2_OUT

USART1_TX,TIM4_ETR

USART1_RX

Doc ID 022691 Rev 1 35/120

Table 12.

AF n°

Port

Pin

Name

Alternate functions

AF0 AF1 AF2 AF3

7 PA0

TIM2_

CH1_

ETR

TIM5

_CH1

_ETR

G1_

IO1

AF4

PA1

PA2

PA3

PA4

PA5

PA6

PA7

TIM2_

CH2

TIM5

_CH2

G1_

IO2

TIM2_

CH3

TIM5

_CH3

G1_

IO3

TIM2_

CH4

TIM5

_CH4

G1_

IO4

TIM3

_CH2

G2_

IO1

TIM2_

CH1_

ETR

TIM

16_

CH1

TIM

17_

CH1

G2_

IO2

TIM3

_CH1

G2_

IO3

TIM3

_CH2

G2_

IO4

AF5 AF6 AF7 AF8 AF9 AF10 AF11

USART

CTS

SPI1_

NSS /

1_WS

SPI1_

SCK /

1_CK

SPI1_

MISO /

1_MCK

SPI1_

MOSI /

1_SD

SPI3_

SCK /

3_CK

SPI3_

MISO /

3_MCK

SPI3_

MOSI /

3_SD

SPI3_

NSS /

3_WS

USART

2_RTS

USART

2_TX

USART

2_RX

USART

2_CK

CEC

COMP1

_OUT

TIM15

_CH1N

COMP2

_OUT

TIM15

_CH1

TIM15

_CH2

TIM14

_CH1

COMP1

_OUT

TIM13

_CH1

COMP2

_OUT

TIM14

_CH1

TIM12

_CH1

TIM12

_CH2

TIM19_

CH1

TIM19_

CH2

TIM19_

CH3

TIM19_

CH4

AF12 AF13 AF14 AF15

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

Table 12.

AF n°

Port

Pin

Name

Alternate functions (continued)

AF0 AF1 AF2 AF3 AF4

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

AF5 AF6 AF7

MCO

TIM

17_

BKIN

TIM

16_

CH1

TIM5

_CH1

_ETR

TIM

13_

CH1

G4_

IO1

I2C2_

SCL

G4_

IO2

I2C2_

SMBAI

I2C2_

SDA

SPI2_

SCK /

2_CK

SPI2_

MISO /

2_MCK

SPI2_

MOSI /

2_SD

TIM5

_CH2

SPI2_

NSS /

2_WS

TIM5

_CH3

JTMS-

SWDAT

TIM

16_

CH1N

JTCK-

SWCLK

JTDI

TIM2_

CH1_E

TIM5

_CH4

G4_

IO3

G4_

IO4

I2C1_

SDA

I2C1_

SCL

IR-Out

SPI1_

NSS /

1_WS

SPI1_

NSS /

1_WS

SPI1_

SCK /

1_CK

SPI1_

MISO /

1_MCK

SPI3_

NSS /

3_WS

USART

1_CK

USART

1_TX

USART

1_RX

USART

1_CTS

USART

1_RTS

USART

3_CTS

AF8 AF9

TIM15

_BKIN

TIM2_

CH3

TIM14

_CH1

TIM2_

CH4

COMP1

_OUT

CAN_

COMP2

_OUT

CAN_

AF10

TIM4_

ETR

TIM4_

CH1

TIM4_

CH2

TIM4_

CH3

TIM12

_CH1

TIM12

_CH2

AF11 AF12 AF13 AF14 AF15

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

USBDM

EVEN

TOUT

USBDP

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

5 PB0

3 PB1

TIM3

_CH3

G3_

IO3

TIM3

_CH4

G3_

IO4

SPI_

MOSI /

1_SD

TIM3_

CH2

EVEN

TOUT

EVEN

TOUT

Table 12.

AF n°

Port

Pin

Name

Alternate functions (continued)

AF0 AF1 AF2 AF3 AF4

AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PB10

PB14

JTDO/

TRACE

SWO

TIM2_

CH2

JTRST

TIM

16_

CH1

TIM

16_

BKIN

TIM4

_ETR

G5_

IO1

SPI1_

SCK /

1_CK

SPI2_

SCK /

2_CK

SPI2_

NSS /

2_WS

SPI3_

SCK /

3_CK

CEC

IR-Out

SPI2_

SCK /

2_CK

SPI2_

MISO /

2_MCK

CEC

USART

2_TX

TIM3

_CH1

G5_

IO2

TIM3

_CH2

SPI1_

MISO /

1_MCK

SPI3_

MISO /

3_MCK

USART

2_RX

I2C1_

SMBAI

SPI1_

MOSI /

1_SD

SPI3_

MOSI /

3_SD

USART

2_CK

TIM

16_

CH1N

TIM

17_

CH1N

TIM2_

CH3

TIM4

_CH1

TIM4

_CH2

G5_

IO3

G5_

IO4

TIM

16_CH

TIM

17_

CH1

TIM4

_CH3

TIM4

_CH4

I2C1_

SCL

I2C1_

SDA

I2C1_

SCL

I2C1_

SDA

TIM

15_

CH1

G6_

IO1

USART

1_TX

USART

1_RX

USART

3_TX

USART

3_RX

USART

3_TX

USART

3_RTS

TIM13

_CH1

TIM15

_CH1N

TIM15

_CH1

TIM15

_CH2

COMP1

_OUT

CAN_

COMP2

_OUT

CAN_

TIM12

_CH1

TIM3_

ETR

TIM17

_BKIN

TIM17

_CH1

TIM3_

CH3

TIM3_

CH4

TIM19_

ETR

TIM19_

CH1

TIM19_

CH2

TIM19_

CH3

TIM19_

CH4

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

EVEN

TOUT

Table 12.

AF n°

Port

Pin

Name

Alternate functions (continued)

AF0 AF1 AF2 AF3 AF4

6 PB15

TIM

15_

CH2

TIM

15_

CH1N

G6_

IO2

AF5

SPI2_

MOSI /

2_SD

AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

TIM12

_CH2

EVEN

TOUT

2 PC0

2 PC1

3 PC2

3 PC3

4 PC4

3 PC5

3 PC6

3 PC7

3 PC8

EVENT

OUT

TIM5

_CH1

_ETR

EVENT

OUT

TIM5

_CH2

EVENT

OUT

TIM5

_CH3

EVENT

OUT

TIM5

_CH4

EVENT

OUT

TIM

13_

CH1

EVENT

OUT

G3_

IO1

G3_

IO2

EVENT

OUT

TIM3

_CH1

EVENT

OUT

TIM3

_CH2

EVENT

OUT

TIM3

_CH3

SPI2_

MISO /

2_MCK

SPI2_

MOSI /

2_SD

SPI1_

NSS /

1_WS

SPI1_

SCK /

1_CK

SPI1_

MISO

USART

1_TX

USART

1_RX

Table 12.

AF n°

Port

Pin

Name

Alternate functions (continued)

AF0 AF1 AF2 AF3 AF4

PC9

PC10

PC11

PC12

EVENT

OUT

TIM3

_CH4

EVENT

OUT

TIM

19_

CH1

EVENT

OUT

TIM

19_

CH2

EVENT

OUT

TIM

19_

CH3

PC13

PC14

PC15

AF5 AF6 AF7

SPI1_

MOSI /

1_SD

SPI3_

SCK /

3_CK

SPI3_

MISO /

3_MCK

SPI3_

MOSI /

3_SD

USART

3_TX

USART

3_RX

USART

3_CK

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

3 PD0

3 PD1

2 PD2

3 PD3

EVENT

OUT

TIM

19_

CH4

EVENT

OUT

TIM

19_

ETR

EVENT

OUT

TIM3

_ETR

EVENT

OUT

SPI2_

MISO /

2_MCK

CAN_R

CAN_T

USART

2_CTS

Table 12.

AF n°

Port

Pin

Name

Alternate functions (continued)

AF0 AF1 AF2 AF3 AF4

PD4

PD5

PD6

EVENT

OUT

EVENT

OUT

EVENT

OUT

PD7

PD8

EVENT

OUT

AF5

SPI2_

MOSI /

2_SD

SPI2_

NSS /

2_WS

SPI2_

SCK /

2_CK

SPI2_

SCK /

2_CK

PD9

PD10

PD11

PD12

PD13

PD14

PD15

EVENT

OUT

G6_

IO3

EVENT

OUT

EVENT

OUT

G6_

IO4

EVENT

OUT

EVENT

OUT

TIM4

_CH1

G8_

IO1

EVENT

OUT

TIM4

_CH2

G8_

IO2

EVENT

OUT

TIM4

_CH3

G8_

IO3

EVENT

OUT

TIM4

_CH4

G8_

IO4

AF6 AF7

USART

2_RTS

USART

2_TX

USART

2_RX

USART

2_CK

USART

3_TX

USART

3_RX

USART

3_CK

USART

3_CTS

USART

3_RTS

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Table 12.

AF n°

Port

Pin

Name

Alternate functions (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

PE8

PE9

PE10

PE11

PE12

EVENT

OUT

TIM4

_ETR

EVENT

OUT

TRACE

CLK

EVENT

OUT

TRACE

EVENT

OUT

TRACE

EVENT

OUT

EVENT

OUT

G7_

IO1

G7_

IO2

G7_

IO3

G7_

IO4

TRACE

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

USART

1_TX

USART

1_RX

PF0

PF1

PF2

PF4

5 PF6

3 PF7

2 PF9

1 PF10

Table 12.

AF n°

Port

Pin

Name

Alternate functions (continued)

AF0 AF1 AF2 AF3 AF4

PE13

PE14

PE15

EVENT

OUT

EVENT

OUT

EVENT

OUT

AF5 AF6 AF7

USART

3_RX

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

I2C2_

SDA

I2C2_

SCL

I2C2_

SMBAI

EVENT

OUT

EVENT

OUT

EVENT

OUT

TIM4

_CH4

EVENT

OUT

EVENT

OUT

TIM

14_

CH1

EVENT

OUT

I2C2_

SCL

SPI1_

MOSI /

1_SD

I2C2_

SDA

USART

3_RTS

USART

2_CK

Memory mapping STM32F37x

Figure 5.

STM32F37x memory map

0xFFFF FFFF

Cortex-M4

Internal

Peripherals

0xE000 0000

0xC000 0000

0xA000 0000

0x8000 0000

0x6000 0000

0x4000 0000

0x2000 0000

Peripherals

SRAM

CODE

0x0000 0000

Reserved

0x4800 17FF

0x4800 0000

0x4002 43FF

0x4002 0000

0x4001 6C00

0x4001 0000

0x4000 A000

0x4000 0000

AHB2

Reserved

AHB1

Reserved

APB2

Reserved

APB1

0x1FFF FFFF

Option bytes

0x1FFF F800

System memory

0x1FFF D800

Reserved

0x0804 0000

Flash memory

0x0800 0000

Reserved

0x0004 0000

Flash, system memory or SRAM, depending on BOOT configuration

0x0000 0000

MS30360V1

44/120 Doc ID 022691 Rev 1

STM32F37x Memory mapping

Table 13.

Bus

AHB2

AHB1

STM32F37x peripheral register boundary addresses

Boundary address

0x4800 1400 - 0x4800 17FF

0x4800 1000 - 0x4800 13FF

0x4800 0C00 - 0x4800 0FFF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 4000 - 0x4002 43FF

0x4002 3400 - 0x4002 3FFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0800- 0x4002 0FFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

0x4001 6C00 - 0x4001 FFFF

Size

1 KB

3 KB

1 KB

3 KB

1 KB

3 KB

1KB

~128 MB

1 KB

2 KB

1 KB

37 KB

Peripheral

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

Reserved

TSC

Reserved

CRC

Reserved

FLASH memory interface

Reserved

RCC

Reserved

DMA2

DMA1

Reserved

Doc ID 022691 Rev 1 45/120

Memory mapping STM32F37x

Table 13.

Bus

APB2

APB1

STM32F37x peripheral register boundary addresses (continued)

Boundary address Size Peripheral

0x4001 6800 - 0x4001 6BFF

0x4001 6400 - 0x4001 67FF

0x4001 6000 - 0x4001 63FF

0x4001 5C00 - 0x4001 5FFF

0x4001 4C00 - 0x4001 5BFF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2800 - 0x4001 2FFF

0x4001 2400 - 0x4001 27FF

0x4001 0800 - 0x4001 23FF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 4000 - 0x4000 FFFF

0x4000 9C00 – 0x4000 9FFF

0x4000 9800 - 0x4000 9BFF

0x4000 7C00 - 0x4000 97FF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6800 - 0x4000 6FFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

1 KB

2 KB

1 KB

24 KB

1 KB

8 KB

1 KB

7 KB

1 KB

4 KB

1 KB

SDADC3

SDADC2

SDADC1

TIM19

Reserved

TIM17

TIM16

TIM15

Reserved

USART1

Reserved

SPI1/I2S1

Reserved

ADC

Reserved

EXTI

SYSCFG

Reserved

TIM18

DAC2

Reserved

CEC

DAC1

PWR

Reserved

CAN

USB packet SRAM

USB FS

46/120 Doc ID 022691 Rev 1

STM32F37x Memory mapping

Table 13.

Bus

APB1

STM32F37x peripheral register boundary addresses (continued)

Boundary address Size Peripheral

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 4C00 - 0x4000 53FF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1C00 - 0x4000 1FFF

0x4000 1800 - 0x4000 1BFF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

1 KB

2 KB

1 KB

TIM12

TIM7

TIM6

TIM5

TIM4

TIM3

TIM2

I2C2

I2C1

Reserved

USART3

USART2

Reserved

SPI3/I2S3

SPI2/I2S2

Reserved

IWWDG

WWDG

RTC

Reserved

TIM14

TIM13

Doc ID 022691 Rev 1 47/120

Electrical characteristics STM32F37x

5.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

= 25 °C and T

= T

A max (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3



Unless otherwise specified, typical data are based on T

= 25 °C, V

= V

DDA

SDADCx_VDD = 3.3 V. They are given only as design guidelines and are not tested.

Typical ADC and SDADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2



)

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 6

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 7

Figure 6.

Pin loading conditions Figure 7.

Pin input voltage

-#5PIN -#5PIN

C = 50 pF

6).

-36 -36

48/120 Doc ID 022691 Rev 1

STM32F37x

5.1.6 Power supply scheme

Figure 8.

Power supply scheme

6"!4

Electrical characteristics

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Doc ID 022691 Rev 1 49/120

Electrical characteristics

Figure 9.

Current consumption measurement scheme

)$$?6"!4

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6$$?3$?3$

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STM32F37x

50/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 14: Voltage characteristics

Table 15: Current characteristics

, and

Table 16: Thermal characteristics

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 14.

Symbol

Voltage characteristics

Ratings Min Max Unit

–V

DDA

SDADC_VDD -

DDA

External main supply voltage (including V

DDA,

SDADCx_V

and V

)

–0.3

4.0

Allowed voltage difference for V

> V

DDA

0.4

Allowed voltage difference for SDADC_VDD > V

DDA

0.4

SSX



ESD(HBM)

Input voltage on FT and FTf pins

Input voltage on TTa pins in anaolog mode

Input voltage on TTa pins in digital mode

Input voltage on TTa pins on SDADCx channels inputs

(1)



0.3

-0.3

+ 4.0

DDA

+ 0.3

SDADCx_VDD

+0.3

Input voltage on any other pin V



0.3

4.0

Variations between all the different ground pins 50

Electrostatic discharge voltage (human body model)

see

Section 5.3.11: Electrical sensitivity characteristics

V mV

SDADC1_VDD/SDADC2_VDD is external power supply for PB0 to PB2, PB10, and PE7 to PE15 I/O pins (I/O pin ground is internally connected to V

). SDADC3_VDD is external power supply for PB14 to PB15 and PD8 to PD15 I/O pins (I/O pin ground is internally connected to V

)

All main power (V

, SDADC1_VDD/SDADC2_VDD, SDADC3_V

DD and V

DDA

) and ground

, SDADC1_VSS/SDADC2_VSS, SDADC3_V

SS and V

SSA

) pins must always be connected to the external power supply, in the permitted range.

The following relationship must be respected between V

DDA

and V

: V

DDA

must power on before or at the same time as V

DD in the power up sequence. V

DDA must be greater than or equal to V

The following relationship must be respected between V

DDA

and

SDADC1_VDD/SDADC2_VDD: V

DDA

must power on before or at the same time as

SDADC1_VDD/SDADC2_VDD or SDADC3_VDDin the power up sequence. V

DDA must be greater than or equal to SDADC1_VDD/SDADC2_VDD or SDADC3_VDD.

The following relationship must be respected between SDADC1_VDD/SDADC2_VDD and

SDADC3_VDD: SDADC3_VDD must power on before or at the same time as

SDADC1_VDD/SDADC2_VDD in the power up sequence.

Doc ID 022691 Rev 1 51/120

Electrical characteristics STM32F37x

Table 15.

Current characteristics

(1)

Symbol Ratings Max.

Unit

VDD

VSS

Total current into V

DD power lines (source)

(2)

Total current out of V

ground lines (sink)

Negative injection disturbs the analog performance of the device. See note 2 below

Output current sunk by any I/O and control pin

TBD

INJ(PIN)

(3)

Output current source by any I/Os and control pin

Injected current on FT and FTf pins

(4)

Injected current on any other pin

(5)

Total injected current (sum of all I/O and control pins)

(6)



-5/+NA

± 5 mA



INJ(PIN)

± 25

TBD stands for “to be defined”.

All main power (V

, SDADC1_VDD/SDADC2_VDD, SDADC3_VDD

SDADC1_VSS/SDADC2_VSS, SDADC3_VSS the permitted range.

and V and V

DDA

) and ground (V

SSA

) pins must always be connected to the external power supply, in

Table 58 on page 96

Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. A negative injection is induced by V

. I

INJ(PIN)

must never be exceeded. Refer to

Table 14: Voltage characteristics

for the maximum allowed input voltage values.

A positive injection is induced by V

while a negative injection is induced by V

. I

INJ(PIN) exceeded. Refer to

Table 14: Voltage characteristics

for the maximum allowed input voltage values.

must never be

When several inputs are submitted to a current injection, the maximum



I negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the positive and

Table 16.

Symbol

Thermal characteristics

Ratings

STG

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

52/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

5.3.1 General operating conditions

Table 17.

Symbol

General operating conditions

(1)

Parameter Conditions Min Max Unit

f f

V f

HCLK

PCLK1

PCLK2

DDA

(2)

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Analog operating voltage

(ADC and DAC not used)

Analog operating voltage

(ADC and DAC used)

Must have a potential equal to or higher than V

SDADC1_

VDD/

SDADC2_

VDD

SDADC3_

VDD

BAT

SDADC1 / SDADC2 operating voltage

SDADC3 operating voltage

Backup operating voltage

Power dissipation at T

85 °C for suffix 6 or T

105 °C for suffix 7

(3)

Ambient temperature for 6 suffix version

Ambient temperature for 7 suffix version

Junction temperature range

WLCSP66

LQFP100

LQFP64

LQFP48

Maximum power dissipation

Low power dissipation

(4)

Maximum power dissipation

Low power dissipation

(4)

6 suffix version

7 suffix version

2.4

2.2

1.65

3.6

–40

–40 105

–40 125

–40

105

125

434

444

364

MHz

V mW

°C

TBD stands for “to be defined”.

When the ADC is used, refer to

Table 56: ADC characteristics

If T

is lower, higher P

characteristics

values are allowed as long as T

does not exceed T

Jmax

(see

Table 16: Thermal

In low power dissipation state, T

can be extended to this range as long as T

Table 16: Thermal characteristics

does not exceed T

Jmax

(see

Doc ID 022691 Rev 1 53/120

Electrical characteristics STM32F37x

5.3.3

are derived from tests performed under the ambient

Table 18

temperature condition summarized in

Table 18.

Symbol

Operating conditions at power-up / power-down

Parameter

t t

VDD

VDDA

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

TBD stands for “to be defined”.

Conditions

(1)

Min

Max Unit

µs/V

Embedded reset and power control block characteristics

Table 19

supply voltage conditions summarized in

temperature and V

Table 19.

Symbol

Embedded reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

POR/PDR

(1)

Power on/power down reset threshold

Falling edge

1.8

(2)

1.88

1.96

Rising edge 1.84

1.92

2.0

PDRhyst

RSTTEMPO

(3)

PDR hysteresis

Reset temporization 1.5

2.5

4.5

The PDR detector monitors V

DD monitors only V

and also V

DDA

(if kept enabled in the option bytes). The POR detector

The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

Guaranteed by design, not tested in production.

mV ms

54/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 20.

Symbol

Programmable voltage detector characteristics

Parameter Conditions Min

(1)

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6

PVD7

PVD threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

PVD threshold 7

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

PVDhyst

(2)

IDD(PVD)

PVD hysteresis

PVD current consumption

Data based on characterization results only, not tested in production.

Guaranteed by design, not tested in production.

2.28

2.47

2.37

2.57

2.47

2.66

2.56

2.76

2.66

2.1

2.19

2.09

2.28

2.18

2.38

0.15

Max

(1)

2.48

2.69

2.59

2.79

2.69

2.9

2.8

2.9

2.26

2.16

2.37

2.27

2.48

2.38

2.58

Typ

2.38

2.58

2.48

2.68

2.58

2.78

2.68

2.88

2.78

100

2.18

2.08

2.28

2.18

2.38

2.28

2.48

Unit

V mV

0.26

µA

Doc ID 022691 Rev 1 55/120

Electrical characteristics STM32F37x

Table 21

supply voltage conditions summarized in

temperature and V

Table 21.

Symbol

Embedded internal reference voltage

Parameter Conditions Min Max

Typ

1.21

1.24

REFINT

S_vrefint

(1)

Internal reference voltage

ADC sampling time when reading the internal reference voltage

–40 °C < T

< +105 °C

REFINT_s

(2)

Internal reference voltage spread over the temperature range

= 3 V

Coeff

START

Figure 9: Current consumption measurement scheme

Temperature coefficient

Startup time

Shortest sampling time can be determined in the application by multiple iterations.

Guaranteed by design, not tested in production.

1.18

100

Unit

µs mV ppm/°C

µs

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark x.x code.

Typical and maximum current consumption

●

The MCU is placed under the following conditions:

●

All I/O pins are in input mode with a static value at V

or V

(no load)

All peripherals are disabled except when explicitly mentioned

The Flash memory access time is adjusted to the f

HCLK

frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz)

Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled f

APB1

= f

AHB

/2 , f

APB2

= f

AHB

ambient temperature and supply voltage conditions summarized in

Table 22

Table 33

are derived from tests performed under

Table 44: I/O static characteristics

56/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 22.

Typical and maximum current consumption from V

supply at V

= 3.6 V

All peripherals enabled All peripherals disabled

Symbol Parameter Conditions

HCLK

72 MHz 65

64 MHz

Supply current in

Run mode, code executing from Flash

External clock (HSE bypass)

48 MHz

32 MHz

24 MHz

8 MHz

1 MHz

64 MHz

48 MHz

Internal clock (HSI)

32 MHz

24 MHz

8.8

8 MHz

72 MHz

8.5

Supply current in

Run mode, code executing from RAM

64 MHz

External clock (HSE bypass)

48 MHz

32 MHz

24 MHz

8 MHz

1 MHz

64 MHz

48 MHz

Internal clock (HSI)

32 MHz

24 MHz

8 MHz

Typ

Max @ T

(1)

25 °C 85 °C 105 °C

Typ

5.3

25 °C

Max @ T

(1)

85 °C 105 °C

Unit

Doc ID 022691 Rev 1 57/120

Electrical characteristics STM32F37x

Table 22.

Typical and maximum current consumption from V

supply at V

= 3.6 V

All peripherals enabled All peripherals disabled

Symbol Parameter Conditions f

HCLK

Typ

Max @ T

(1)

25 °C 85 °C 105 °C

Typ

25 °C

Max @ T

(1)

85 °C 105 °C

Unit

72 MHz

Supply current in

Sleep mode, code executing from Flash or RAM

64 MHz

External clock (HSE bypass)

48 MHz

32 MHz

24 MHz

8 MHz

1 MHz

64 MHz

48 MHz

Internal clock (HSI)

32 MHz

24 MHz

8 MHz

8.6

5.8

Data based on characterization results, not tested in production unless otherwise specified.

Table 23.

Typical and maximum current consumption from V

DDA

supply

DDA

= 2.4 V V

DDA

= 3.6 V

Symbol Parameter Conditions f

HCLK

Max @ T

(1)

Max @ T

(1)

Typ Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

Unit

DDA

Supply current in

Run or

Sleep mode, code executing from Flash or RAM

72 MHz

64 MHz

External clock (HSE bypass)

48 MHz

32 MHz

24 MHz

8 MHz

1 MHz

64 MHz

48 MHz

Internal clock (HSI)

32 MHz

24 MHz

8 MHz

260

170

297

240

162

Data based on characterization results, not tested in production unless otherwise specified.

µA

58/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 24.

Symbol

Typical and maximum V

consumption in Stop and Standby modes

[email protected]

DDA

) Max

Parameter Conditions

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25 °C

85 °C

105 °C

Unit

Supply current in

Stop mode

Supply current in

Standby mode

Regulators in run mode, all oscillators

OFF

Regulators in low-power mode, all oscillators

OFF

LSI ON and

IWDG ON

LSI OFF and

IWDG OFF

21.9

9.5

1.73

1.23

µA

Note: V

DDA

monitoring is OFF and SDADC12_VDD monitoring is OFF

Doc ID 022691 Rev 1 59/120

Electrical characteristics STM32F37x

Table 25.

Typical and maximum V

DDA

consumption in Stop and Standby modes

[email protected]

DDA

) Max

(1)

Symbol Parameter Conditions

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25 °C

85 °C

105 °C

Unit

DDA

Supply current in

Stop mode

Supply current in

Standby mode

Supply current in

Stop mode

Supply current in

Standby mode

Regulator in run mode, all oscillators OFF

Regulator in low-power mode, all oscillators OFF

LSI ON and

IWDG ON

LSI OFF and

IWDG OFF

Regulator in run mode, all oscillators OFF

Regulator in low-power mode, all oscillators OFF

LSI ON and

IWDG ON

LSI OFF and

IWDG OFF

2.71

1.4

2.13

1.29

µA

Data based on characterization results and tested in production.

Table 26.

Typical and maximum current consumption from V

BAT

supply

Typ @ V

BAT

Symbol Parameter Conditions

25 °C

Max

(1)

85 °C

105 °C

Unit

DD_

VBAT

Backup domain supply current

LSE & RTC ON; "Xtal mode" lower driving capability;

LSEDRV[1:0] = '00'

LSE & RTC ON; "Xtal mode" higher driving capability;

LSEDRV[1:0] = '11'

Data based on characterization results and tested in production.

µA

60/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Typical current consumption

●

The MCU is placed under the following conditions:

DDA

= SDADC1_SDADC2_VDD = SDADC3_VDD = 3.3 V

All I/O pins are in analog input configuration

The Flash access time is adjusted to f

HCLK

frequency (0 wait states from 0 to 24 MHz,

1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz)

Prefetech is ON when the peripherals are enabled, otherwise it is OFF

When the peripherals are enabled, f

APB1

= f

AHB/2

, f

APB2

= f

AHB

PLL is used for frequencies greater than 8 MHz

AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and

500 kHz respectively

Doc ID 022691 Rev 1 61/120

Electrical characteristics STM32F37x

Table 27.

Symbol

Typical current consumption in Run mode, code with data processing running from

Flash

Typ

Parameter Conditions f

HCLK

Unit

Peripherals enabled

Peripherals disabled

64.35

38.42

DDA

Supply current in

Run mode from

supply

Supply current in

Run mode from

DDA

supply

ISDADC12 +

ISDADC3

Supply currents in

Run mode from

SDADC1_SDADC2

_VDD and

SDADC3_VDD

(SDADCs are off)

Running from HSE crystal clock 8 MHz, code executing from

Flash

64 MHz

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

72 MHz

8 MHz

72 MHz

64 MHz

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

72 MHz

1 MHz

45.34

25.57

8.91

250

165

1.5

250 mA

µA

62/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 28.

Symbol

Typical current consumption in Sleep mode, code running from Flash or RAM

Typ

Parameter Conditions f

HCLK

Peripherals enabled

Peripherals disabled

Unit

36.7

7.6

DDA

Supply current in

Sleep mode from

supply

Supply current in

Sleep mode from

DDA

supply

ISDADC12 +

ISDADC3

Supply currents in

Sleep mode from

SDADC1_SDADC2

_VDD and

SDADC3_VDD

(SDADCs are off)

Running from HSE crystal clock 8 MHz, code executing from

Flash or RAM

64 MHz

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

72 MHz

8 MHz

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

72 MHz

1 MHz

237 237 mA

µA

Doc ID 022691 Rev 1 63/120

Electrical characteristics STM32F37x

Caution:

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC and SDADC input pins which should be configured as analog inputs.

Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 34: Peripheral current consumption

), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

= V

 f



C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

64/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

On-chip peripheral current consumption

●

The current consumption of the on-chip peripherals is given in

Table 34

. The MCU is placed under the following conditions: all I/O pins are in input mode with a static value at V

or V

(no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption

–

– with all peripherals clocked off with only one peripheral clocked on

● ambient operating temperature and V

Table 14

supply voltage conditions summarized in

Doc ID 022691 Rev 1 65/120

Electrical characteristics STM32F37x

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in

Section 5.3.13

. However,

the recommended clock input waveform is shown in

Figure 10

Table 29.

Symbol

High-speed external user clock characteristics

Parameter

(1)

Conditions Min

HSE_ext

User external clock source frequency

HSEH

HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

Guaranteed by design, not tested in production.

0.7V

Typ

Max

0.3V

Unit

MHz

V ns

Figure 10.

High-speed external clock source AC timing diagram

6(3%(

6(3%,

TR(3%

4(3%

TF(3%

T7(3%(

T7(3%,

-36

66/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in

Section 5.3.13

. However,

the recommended clock input waveform is shown in

Figure 11

Table 30.

Symbol

Low-speed external user clock characteristics

Parameter

(1)

Conditions Min

LSE_ext

LSEH

User External clock source frequency

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)

OSC32_IN high or low time

OSC32_IN rise or fall time

Guaranteed by design, not tested in production.

0.7V

450

Typ

32.768

Max

1000

0.3V

Unit

kHz

V ns

Figure 11.

Low-speed external clock source AC timing diagram

T7,3%(

6,3%(

6,3%,

TR,3%

4,3%

TF,3%

T7,3%,

-36

Doc ID 022691 Rev 1 67/120

Electrical characteristics

Note:

STM32F37x

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design

simulation results obtained with typical external components specified in

Table 31

. In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Table 31.

Symbol

HSE oscillator characteristics

Parameter Conditions

(1)

Min

. In the application, the

Typ Max

(2)

Unit

OSC_IN

Oscillator frequency

Feedback resistor

4 8

200

32 MHz k



HSE current consumption

During startup

(3)

=3.3 V, Rm= 30



CL=10 [email protected] MHz

=3.3 V, Rm= 45



CL=10 [email protected] MHz

=3.3 V, Rm= 30



CL=5 [email protected] MHz

=3.3 V, Rm= 30



CL=10 [email protected] MHz

=3.3 V, Rm= 30



CL=20 [email protected] MHz

0.4

0.5

0.8

1.5

8.5

g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time V

Startup

is stabilized

Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2 mA/V ms

Guaranteed by design, not tested in production.

This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 12

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

68/120 Doc ID 022691 Rev 1

STM32F37x

Figure 12.

Typical application with an 8 MHz crystal

2ESONATORWITH

INTEGRATEDCAPACITORS

-( Z

RESONATOR

2%84

/3#?).

/3#?/5 4

"IAS

CONTROLLED

GAIN

EXT

value depends on the crystal characteristics.

Electrical characteristics

F(3%

-36

Doc ID 022691 Rev 1 69/120

Electrical characteristics STM32F37x

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 32

resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 32.

Symbol

LSE oscillator characteristics (f

LSE

= 32.768 kHz)

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit

DD g m

LSE current consumption

Oscillator transconductance

LSEDRV[1:0]=00 lower driving capability

LSEDRV[1:0]= 01 medium low driving capability

LSEDRV[1:0] = 10 medium high driving capability

LSEDRV[1:0]=11 higher driving capability

LSEDRV[1:0]=00 lower driving capability

LSEDRV[1:0]= 01 medium low driving capability

LSEDRV[1:0] = 10 medium high driving capability

0.5

0.9

1.3

1.6

µA

µA/V

LSEDRV[1:0]=11 higher driving capability

25 t

SU(LSE)

(3)

Startup time V

is stabilized 2

Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

Guaranteed by design, not tested in production.

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

70/120 Doc ID 022691 Rev 1

STM32F37x

Figure 13.

Typical application with a 32.768 kHz crystal

2ESONATORWITH

INTEGRATEDCAPACITORS

/3#?).

K( Z

RESONATOR

$RIVE

PROGRAMMABLE

AMPLIFIER

/3#?/5 4

Electrical characteristics

F,3%

Note:

5.3.7

-36

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

Internal clock source characteristics

Table 33

temperature and supply voltage conditions summarized in

High-speed internal (HSI) RC oscillator

Table 33.

Symbol

HSI oscillator characteristics

(1)

Parameter Conditions

HSI

TRIM

DuCy

(HSI)

Frequency

HSI user trimming step

Duty cycle

ACC

HSI

Accuracy of the HSI oscillator (factory calibrated)

= –40 to 105 °C

= –10 to 85 °C

= 0 to 70 °C

= 25 °C

I t su(HSI)

DD(HSI)

HSI oscillator startup time

HSI oscillator power consumption

DDA

=3.3 V, T

= –40 to 105 °C unless otherwise specified.

Guaranteed by design, not tested in production.

Data based on characterization results, not tested in production.

Min

–2

(3)

–1.5

–1.3

–1.1

Typ

Max

(2)

2.5

2.2

1.8

100

Unit

MHz

µs

µA

Doc ID 022691 Rev 1 71/120

Electrical characteristics STM32F37x

Low-speed internal (LSI) RC oscillator

Table 34.

Symbol

LSI oscillator characteristics

(1)

Parameter Min

LSI t su(LSI)

(2)

DD(LSI)

voltage conditions summarized in

Frequency 30

LSI oscillator startup time

LSI oscillator power consumption

DDA

3.3 V, T

= –40 to 105 °C unless otherwise specified.

Guaranteed by design, not tested in production.

Typ

0.75

Max

1.2

Unit

kHz

µs

µA

Wakeup time from low-power mode

●

The wakeup times given in is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:

Stop or Standby mode: the clock source is the RC oscillator

Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V

supply

Table 35.

Low-power mode wakeup timings

Symbol Parameter Conditions

Typ @V

= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V

Max Unit

5.88

5.43

t t

WUSTOP

Wakeup from Stop mode

Regulator in run mode

Regulator in low power mode t

WUSTANDBY

Wakeup from

Standby mode

WUSLEEP

Wakeup from Sleep mode

9.35

3.2

7.26

3.2

µs

72/120

Table 36

temperature and supply voltage conditions summarized in

Table 36.

PLL characteristics

Symbol Parameter

Value

Typ

PLL_IN

PLL input clock

(1)

PLL input clock duty cycle

Min

Max

Unit

MHz

Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 36.

PLL characteristics (continued)

Value

Symbol Parameter Unit

PLL_OUT t

LOCK

Jitter

PLL multiplier output clock

PLL lock time

Cycle-to-cycle jitter

Min

Typ Max

200

300

(2)

MHz

µs ps

Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

Guaranteed by design, not tested in production.

Flash memory

The characteristics are given at T

= –40 to 105 °C unless otherwise specified.

Table 37.

Flash memory characteristics

Symbol Parameter Conditions

t t

I prog

ERASE t

16-bit programming time

Page (1 KB) erase time

Mass erase time

Supply current



–40 to +105 °C



–40 to +105 °C



–40 to +105 °C

Read mode f

HCLK

= 72 MHz with 2 wait states, V

= 3.3 V

Write mode

= 3.3V

Erase mode

= 3.3V

Power-down / Halt mode,

= 3.0 to 3.6 V

V prog

Programming voltage

Guaranteed by design, not tested in production.

Min

Typ

52.5

Max

(1)

Unit

µs ms ms

TBD

3.6

mA mA mA

µA

Doc ID 022691 Rev 1 73/120

Electrical characteristics

Table 38.

Flash memory endurance and data retention

Symbol Parameter Conditions

N t

END

RET

Endurance

Data retention

= –40 to +85 °C (6 suffix versions)

= –40 to +105 °C (7 suffix versions)

1 kcycle

(2)

at T

= 85 °C

1 kcycle

at T

= 105 °C

10 kcycles

Unless otherwise specified, the parameters given in

at T

= 55 °C

Data based on characterization results, not tested in production.

Cycling performed over the whole temperature range.

STM32F37x

Value

Min

(1)

Unit

kcycles

Years

74/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

●

Electrostatic discharge (ESD)

(positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

FTB

: A Burst of Fast Transient voltage (positive and negative) is applied to V

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in

Table 39

. They are based on the EMS levels and classes defined in application note AN1709.

Table 39.

EMS characteristics

Symbol Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V

SS pins to induce a functional disturbance f



3.3 V, LQFP100, T

HCLK



72 MHz



+25 °C, conforms to IEC 61000-4-2 f



3.3 V, LQFP100, T

HCLK



72 MHz



+25 °C, conforms to IEC 61000-4-4

TBD

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

●

The software flowchart must include the management of runaway conditions such as:

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Doc ID 022691 Rev 1 75/120

Electrical characteristics STM32F37x

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 40.

EMI characteristics

Symbol

EMI

Parameter Conditions

Peak level



3.3V, T



25 °C,

LQFP64 package compliant with IEC

61967-2

Monitored frequency band

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

Max vs. [f

8/72 MHz

HSE

HCLK

TBD

TBD

]

Unit

dBµV

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Table 41.

ESD absolute maximum ratings

(1)

Symbol Ratings Conditions

ESD(HBM)

Electrostatic discharge voltage (human body model)



+25 °C, conforming to JESD22-A114

ESD(CDM)

Electrostatic discharge voltage (charge device model)



+25 °C, conforming to JESD22-C101

Class Maximum value

(2)

Unit

TBD

TBD stands for “to be defined”.

Data based on characterization results, not tested in production.

76/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Static latch-up

●

Two complementary static tests are required on six parts to assess the latch-up performance:

A supply overvoltage is applied to each power supply pin

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 42.

Symbol

Electrical sensitivities

(1)

Parameter

Static latch-up class

Conditions



+105 °C conforming to JESD78A

TBD stands for “to be defined”.

Class

TBD

As a general rule, current injection to the I/O pins, due to external voltage below V

or above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the

I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

The test results are given in

Table 43

Table 43.

Symbol

I/O current injection susceptibility

(1)

Functional susceptibility

Description

Negative injection

Positive injection

INJ

Injected current on OSC_IN32,

OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins

Injected current on all FTf pins

Injected current on all TTa pins

Injected current on any other pin

TBD stands for “to be defined”.

TBD

Unit

Doc ID 022691 Rev 1 77/120

Electrical characteristics STM32F37x

General input/output characteristics

Table 44

are derived from tests

performed under the conditions summarized in

. All I/Os are CMOS and TTL compliant.

Table 44.

Symbol

V hys

I/O static characteristics

Parameter Conditions

Standard I/O input low level voltage

TTa I/O input low level voltage

FT and FTf

I/O input low level voltage

Standard I/O input high level voltage

TTa I/O input high level voltage

FT and FTf

(1)

I/O input high level voltage

Standard I/O Schmitt trigger voltage hysteresis

(2)

TTa I/O Schmitt trigger voltage hysteresis

FT and FTf I/O Schmitt trigger voltage hysteresis

mentioned in the Table 44 . represents power voltage for given I/O pin (V

I lkg

Input leakage current

(3)



I/O TC, FT and FTf

2 V



DDA



3.6 V

I/O TTa used in digital mode

5 V

I/O FT and FTf

3.6 V

2 V



DDA =

3.6 V

I/O TTa used in digital mode

2 V



DDA



3.6 V

I/O TTa used in analog mode

Min

–0.3

0.445V

+0.398 V

+0.3

0.445V

+0.398 V

+0.3

0.5V

+0.2 5.5

200

100

Typ Max

0.3V

+0.07

0.3V

+0.07

0.475V

-0.2



±0



±0.2

Unit

V mV

µA

78/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 44.

Symbol

I/O static characteristics (continued)

Parameter Conditions Min Typ Max

Weak pull-up equivalent resistor

(4)

Weak pull-down equivalent resistor

(4)



I/O pin capacitance 5

To sustain a voltage higher than V

+0.3 the internal pull-up/pull-down resistors must be disabled.

Hysteresis voltage between Schmitt trigger switching levels. Data based on characterization, not tested in production.

Leakage could be higher than max. if negative current is injected on adjacent pins.

Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order).

Unit

 k

 pF

Note: I/O pins are powered from V

voltage except pins which can be used as SDADC inputs:

- PB0 to PB2, PB10, and PE7 to PE15 I/O pins are powered from SDADC1_SDADC2_VDD

- PB14 to PB15 and PD8 to PD15 I/O pins are powered from SDADC3_VDD. All I/O pin ground is internally connected to V

SDADC1_SDADC2_VDD or SDADC3_VDD).

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in

Figure 14

and

Figure 15

for standard I/Os, and in

Figure 16

and

Figure 17

for 5 V tolerant I/Os.

Figure 14.

TC and TTa I/O input characteristics - CMOS port

(V)

IHmin

2.0

CMOS standard requirements V

IHmin

= 0.7V

IHmin

= 0.445V

+0.398

1.3

ILmax

= 0.3V

+0.07

Input range not guaranteed

CMOS standard requirements V

ILmax

= 0.3V

ILmax

0.7

0.6

(V)

2.0

2.7

3.0

3.3

3.6

MS30255V1

Doc ID 022691 Rev 1 79/120

Electrical characteristics STM32F37x

Figure 15.

TC and TTa I/O input characteristics - TTL port

(V)

IHmin

2.0

1.3

TTL standard requirements V

IHmin

= 2 V

IHmin

= 0.445V

+0.398

ILmax

= 0.3V

+0.07

Input range not guaranteed

ILmax

0.8

0.7

TTL standard requirements V

ILmax

= 0.8 V

(V)

2.0

2.7

3.0

3.3

3.6

MS30256V1

80/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Figure 16.

Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port

(V)

2.0

1.0

CMOS standard requirements V

IH min

= 0.7V

IHmin

= 0.5V

+0.2

Input range not guaranteed

ILmax

CMOS standard requirements V

ILmax

= 0.3V

= 0.475V

-0.2

0.5

(V)

2.0

3.6

MS30257V1

Figure 17.

Five volt tolerant (FT and FTf) I/O input characteristics - TTL port

(V)

2.0

1.0

0.8

0.5

TTL standard requirements V

IHmin

= 2 V

IHmin

= 0.5V

+0.2

Input range not guaranteed

ILmin

= 0.475V

-0.2

TTL standard requirements V

ILmax

= 0.8 V

(V)

2.0

2.7

3.6

MS30258V1

Doc ID 022691 Rev 1 81/120

Electrical characteristics STM32F37x

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V

OL/

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 5.2

●

The sum of the currents sourced by all the I/Os on V

DD, plus the maximum Run consumption of the MCU sourced on V

DD, cannot exceed the absolute maximum rating

VDD

(see

The sum of the currents sunk by all the I/Os on V

plus the maximum Run consumption of the MCU sunk on V

cannot exceed the absolute maximum rating

VSS

(see

Unless otherwise specified, the parameters given in

Output voltage levels

Table 45

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

. All I/Os are CMOS and TTL compliant (FT, TTa or TC unless otherwise specified).

Table 45.

Output voltage characteristics

Conditions

Symbol Parameter

STM32F37xVx

STM32F37xCx,

STM32F37xRx

(1)

(3)

Output low level voltage for an

I/O pin when 8 pins are sunk at same time

Output high level voltage for an

I/O pin when 8 pins are sourced at same time

Output low level voltage for an

I/O pin when 8 pins are sunk at same time

Output high level voltage for an

I/O pin when 8 pins are sourced at same time

CMOS port

= +8 mA

2.7 V < V

< 3.6 V

TTL port

= +8 mA

2.7 V < V

< 3.6 V

CMOS port

(2)

= +8 mA

2.7 V < V

< 3.6 V

CMOS port

= +4 mA

2.7 V < V

< 3.6 V

TTL port

=+ 8 mA

2.7 V < V

< 3.6 V

TTL port

=+ 4 mA

2.7 V < V

< 3.6 V

(1)(4)

Output low level voltage for a

TTL pin when 8 pins are sunk at same time

(3)(4)

Output high level voltage for an

I/O pin when 8 pins are sourced at same time

= +20 mA

2.7 V < V

< 3.6 V

= +20 mA

2.7 V < V

< 3.6 V

= +10 mA

2.7 V < V

< 3.6 V

Min

–0.4

2.3

–1.3

Max Unit

0.4

1.3

82/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 45.

Symbol

Output voltage characteristics (continued)

Conditions

Parameter

STM32F37xVx

STM32F37xCx,

STM32F37xRx

Min Max Unit

(1)(4)

Output low level voltage for an

I/O pin when 8 pins are sunk at same time

(3)(4)

Output high level voltage for an

I/O pin when 8 pins are sourced at same time

= +6 mA

2 V < V

< 2.7 V

= +5 mA

2 V < V

< 2.7 V

–0.4

0.4

OLFM+

Output low level voltage for a FTf

I/O pins in FM+ mode

= +20 mA

2 V < V

< 3.6 V

= +20 mA

2 V < V

< 3.6 V

0.4

The I

current sunk by the device must always respect the absolute maximum rating specified in

(I/O ports and control pins) must not exceed I

VSS

and the sum of

TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

The I

current sourced by the device must always respect the absolute maximum rating specified in

mentioned in the Table 45 . represents power voltage for given I/O pin (V

and the sum of I

(I/O ports and control pins) must not exceed I

VDD

Data based on characterization results, not tested in production.

Note: I/O pins are powered from V

voltage except pins which can be used as SDADC inputs:

- PB0 to PB2, PB10, and PE7 to PE15 I/O pins are powered from SDADC1_SDADC2_VDD

- PB14 to PB15 and PD8 to PD15 I/O pins are powered from SDADC3_VDD. All I/O pin ground is internally connected to V

SDADC1_SDADC2_VDD or SDADC3_VDD).

Doc ID 022691 Rev 1 83/120

Electrical characteristics STM32F37x

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 18

and

Table 46

, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 46.

OSPEEDRy

[1:0] value

(1)

I/O AC characteristics

(1)

Symbol Parameter

01 f max(IO)out

Maximum frequency

(2) t f(IO)out

Output high to low level fall time t r(IO)out f max(IO)out

Output low to high level rise time

Maximum frequency

t t f(IO)out r(IO)out

Output high to low level fall time

Output low to high level rise time

Conditions

= 50 pF, V

= 2 V to 3.6 V

= 50 pF, V

= 2 V to 3.6 V

= 50 pF, V

= 2 V to 3.6 V

= 50 pF, V

= 2 V to 3.6 V

Min Max

125

(3)

125

Unit

MHz ns

11 f max(IO)out t t f(IO)out r(IO)out

Maximum frequency

fall time rise time

Output high to low level

Output low to high level

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2 V to 2.7 V

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2 V to 2.7 V

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2 V to 2.7 V

TBD

TBD

MHz

MHz ns

FM+ configuration

(4) f max(IO)out

Maximum frequency

Unless otherwise specified, the parameters given in

t f(IO)out

Output high to low level fall time t t r(IO)out

EXTIpw

Output low to high level rise time

Pulse width of external signals detected by the

EXTI controller

TBD

The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0091 reference manual for a description of

GPIO Port configuration register.

The maximum frequency is defined in

Figure 18

Guaranteed by design, not tested in production.

The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F05xxx reference manual RM0091 for a description of FM+ I/O mode configuration.

MHz ns ns

84/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Figure 18.

I/O AC characteristics definition

10%

50%

90% 10%

50%

90%

EXT ERNAL

OUTPUT

ON 50pF tr(IO)out

T tr(IO)out

Maximum fr equency is achieved if (tr + tf)



2/3) T and if the duty cycle is (45-55%)

 when loaded by 50pF ai14131

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 44

Table 47

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 47.

Symbol

NRST pin characteristics

Parameter Conditions Min Typ Max Unit

IL(NRST)

(1)

IH(NRST)

NRST Input low level voltage

NRST Input high level voltage

V hys(NRST)

NRST Schmitt trigger voltage hysteresis

F(NRST)

NF(NRST)

. Otherwise the reset will not be taken into account by the device.

Weak pull-up equivalent resistor

(2)

NRST Input filtered pulse

NRST Input not filtered pulse



–0.5

300

200

0.8

+0.5

100

Guaranteed by design, not tested in production.

The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum

(~10% order)

V mV k

 ns ns

Doc ID 022691 Rev 1 85/120

Electrical characteristics

Figure 19.

Recommended NRST pin protection

%XTERNAL

RESETCIRCUIT

.234

6$$

205

&ILTER

)NTERNAL2ESET

STM32F37x

-36

The reset network protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 47

The BOOT0 pin input driver does not have a standard CMOS threshold value. The threshold value does not depend on the V

voltage.

Unless otherwise specified, the parameters given in

Table 49

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 48.

Symbol

BOOT0 pin characteristics

Parameter

(BOOT0)

BOOT0 Input low level voltage

BOOT0 Input high level voltage

Conditions Min

1.0

Typ Max

0.4

Unit

86/120

are guaranteed by design.

Table 49

Refer to

for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Table 49.

Symbol

TIMx

(1)

characteristics

Parameter Conditions Min

t res(TIM) f

EXT

Res

TIM

Timer resolution time

TIMxCLK

= 72 MHz

Timer external clock frequency on CH1 to CH4 f

TIMxCLK

= 72 MHz

TIMx (except TIM2)

Timer resolution

TIM2

13.9

0 t

COUNTER

16-bit counter clock period

TIMxCLK

= 72 MHz

0.0139

Max

TIMxCLK

65536

910

Unit

TIMxCLK ns

MHz

MHz bit t

TIMxCLK

µs

Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 49.

Symbol

TIMx

(1)

characteristics (continued)

Parameter Conditions Min Max Unit

MAX_COUNT

Maximum possible count with 32-bit counter

65536 × 65536 t

TIMxCLK

= 72 MHz 59.65

TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14,

TIM15, TIM16 , TIM17, TIM18 and TIM19 timers.

Table 50.

IWDG min/max timeout period at 40 kHz (LSI)

(1)

Prescaler divider PR[2:0] bits

Min timeout (ms) RL[11:0]=

0x000

Max timeout (ms) RL[11:0]=

0xFFF

/16

/32

/64

/128

/256

0.1

0.2

0.4

0.8

1.6

3.2

6.4

409.6

819.2

1638.4

3276.8

6553.6

13107.2

26214.4

These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Table 51.

Prescaler

WWDG min-max timeout value @72 MHz (PCLK)

WDGTB Min timeout value

TBD

Max timeout value

TBD

Doc ID 022691 Rev 1 87/120

Electrical characteristics STM32F37x

I

C interface characteristics

Unless otherwise specified, the parameters given in

Table 52

are derived from tests performed under ambient temperature, f

PCLK1 frequency and V

supply voltage conditions summarized in

The I

C interface meets the requirements of the standard I

C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I

C characteristics are described in

Table 52

. Refer also to

for more details on the input/output alternate function characteristics (SDA

and SCL).

Table 52.

C characteristics

(1)

Standard mode Fast mode Fast mode Plus

Symbol Parameter Unit

Min Max Min Max Min Max

t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time t su(STA)

Start condition hold time

Repeated Start condition setup time t su(STO) t w(STO:STA)

Stop condition setup time

Stop to Start condition time

(bus free)

4.7

4.0

250

4.0

4.7

4.0

4.7

3450

300

1000

1.3

0.6

100

(2)

0.6

1.3

900

(3)

300

0.5

0.26

(4)

0.26

0.6 0.26

0.26

0.5

450

Unless otherwise specified, the parameters given in

120

µs ns

µs



 s s

C b

Capacitive load for each bus line

400 400 550 pF

The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when

I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in production.

The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal.

The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

88/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 53.

Symbol

I2C analog filter characteristics

(1)

Parameter

Pulse width of spikes that are suppressed by the analog filter

Guaranteed by design, not tested in production.

Min

Figure 20.

C bus AC waveforms and measurement circuit

6$$

-#5

) #BUS

3$!

3#,

Max

260

Unit

3 4!242%0%!4%$

3 4!24

3$!

TF3$!

TH34!

TR3$!

TW3#,,

TSU3$!

TH3$!

3#,

TW3#,(

TR3#,

TF3#,

Measurement points are done at CMOS levels: 0.3V

and 0.7V

TSU34!

3 4/0

TSU34/

3 4!24

TW34/34!

-36

Doc ID 022691 Rev 1 89/120

Electrical characteristics STM32F37x

SPI/I

S characteristics

S are derived from tests performed under ambient temperature, f

PCLKx frequency and V

DD supply voltage conditions summarized in

Refer to

for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I

S).

Table 54.

Symbol

SPI characteristics

Parameter Conditions Min Max Unit

1/t f

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode

TBD

MHz t r(SCK) t f(SCK)

SPI clock rise and fall time

Capacitive load: C = 30 pF TBD TBD ns

DuCy(SCK)

SPI slave input clock duty cycle

Slave mode TBD TBD % t su(NSS)

(1) t h(NSS)

t t w(SCKH)

w(SCKL)

t t su(MI)

t h(SI)

t a(SO)

t dis(SO)

t v(SO)

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output disable time

Data output valid time

Data output hold time

Slave mode

Master mode, f presc = 4

Master mode

Slave mode

Master mode

Slave mode

Slave mode, f

Slave mode

PCLK

= 36 MHz,

= 20 MHz

Slave mode (after enable edge)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

TBD

Data based on characterization results, not tested in production.

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

90/120 Doc ID 022691 Rev 1

STM32F37x

Figure 21.

SPI timing diagram - slave mode and CPHA = 0

NSS input tc(SCK) tSU(NSS)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tw(SCKH) tw(SCKL) ta(SO)

MISO

OUT P UT tsu(SI)

MOSI

I NPUT tv(SO)

MS B O UT

M SB IN th(SI) th(SO)

BI T6 OUT

B I T1 IN

Figure 22.

SPI timing diagram - slave mode and CPHA = 1

(1)

Electrical characteristics

th(NSS) tr(SCK) tf(SCK)

LSB OUT tdis(SO)

LSB IN ai14134c

NSS input tSU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 tw(SCKH) tw(SCKL)

MISO

OUT P UT ta(SO) tsu(SI)

MOSI

I NPUT tc(SCK) tv(SO)

MS B O UT th(SI)

M SB IN B I T1 IN th(SO)

BI T6 OUT th(NSS) tr(SCK) tf(SCK) tdis(SO)

LSB OUT

LSB IN

Measurement points are done at CMOS levels: 0.3V

and 0.7V

ai14135

Doc ID 022691 Rev 1 91/120

Electrical characteristics

Figure 23.

SPI timing diagram - master mode

(1)

(IGH

.33INPUT

TC3#+

#0(!

#0/,

#0(!

#0/,

STM32F37x

#0(!

#0/,

#0(!

#0/,

-)3/

).0 54

-/3)

/54054

TSU-)

TW3#+(

TW3#+,

-3 ").

TH-)

- 3"/54

TV-/

") 4).

" ) 4/54

TH-/

TR3#+

TF3#+

,3").

,3"/54

Measurement points are done at CMOS levels: 0.3V

and 0.7V

Table 55.

Symbol

S characteristics

Parameter Conditions

DuCy(SCK)

I2S slave input clock duty cycle

Slave mode f

1/t c(CK)

S clock frequency

Master mode (data: 16 bits, Audio frequency = 48 kHz)

Slave mode

Min

TBD

AI6

Max

TBD

Unit

MHz

92/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 55.

Symbol

S characteristics (continued)

Parameter Conditions

t r(CK) t f(CK) t v(WS)

(1) t h(WS)

t h(WS)

t w(CKH)

t su(SD_SR)

S clock rise and fall time

WS valid time

WS hold time

WS setup time

WS hold time

CK high and low time

Capacitive load C

Master mode

Slave mode

Master f

PCLK

= 50 pF

= 16 MHz, audio frequency = 48 kHz t t t

h(SD_MT)

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Data output valid time

Data output hold time

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Data based on design simulation and/or characterization results, not tested in production.

Depends on f

PCLK

. For example, if f

PCLK

=8 MHz, then T

PCLK

= 1/f

PLCLK

=125 ns.

Min

TBD

Unit

Max

TBD

Doc ID 022691 Rev 1 93/120

Electrical characteristics

Figure 24. I

S slave timing diagram (Philips protocol)

(1)

tc(CK)

CPOL = 0

STM32F37x

CPOL = 1 tw(CKH) tw(CKL) th(W

S )

W S inp u t

S Dtr a n s mit t su (W S )

L S B tr a n s mit

(2) t su ( S D_ S R)

L S B receive

(2)

M S B tr a n s mit

M S B receive tv(

S D_ S T)

Bitn tr a n s mit th(

S D_ S R)

Bitn receive th(

S D_ S T)

L S B tr a n s mit

L S B receive

S Dreceive a i14 88 1 b

Measurement points are done at CMOS levels: 0.3 × V

and 0.7 × V

LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 25. I

S master timing diagram (Philips protocol)

(1)

tf(CK) tr(CK) tc(CK)

CPOL = 0 tw(CKH)

CPOL = 1 tv(W

S ) tw(CKL) th(W

S )

W S o u tp u t

S Dtr a n s mit L S B tr a n s mit

(2) t su ( S D_MR)

L S B receive

(2)

M S B tr a n s mit

S B receive tv(

S D_MT)

Bitn tr a n s mit th(

S D_MR)

Bitn receive th(

L S

S D_MT)

B tr a n s

L S B receive mit

S Dreceive a i14 88 4 b

Data based on characterization results, not tested in production.

LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

94/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Note:

Unless otherwise specified, the parameters given in

Table 56

are preliminary values derived

from tests performed under ambient temperature, f

PCLK2 frequency and V

DDA

supply voltage

conditions summarized in

It is recommended to perform a calibration after each power-up.

Table 56.

Symbol

DDA f

ADC f

(1)

ADC characteristics

Parameter

Analog supply voltage for

ADC ON

ADC clock frequency

Sampling rate

Conditions Min

2.4

0.6

0.05

Typ Max

3.6

Unit

V f

TRIG

External trigger frequency

AIN

Conversion voltage range

External input impedance

Sampling switch resistance

Internal sample and hold capacitor f

ADC

= 14 MHz

for details

823

REF+

MHz

MHz kHz

1/f

ADC

V k

 k

 pF t

Calibration time

Trigger conversion latency

Sampling time

Power-up time t

CONV

) is used to determine the maximum external impedance

Total conversion time

(including sampling time) f

ADC

= 14 MHz f

ADC

= 14 MHz f

ADC

= 14 MHz f

ADC

= 14 MHz

5.9

0.107

1.5

0.143

17.1

239.5

14 to 252 (t

for sampling +12.5 for successive approximation)

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

Guaranteed by design, not tested in production.

Doc ID 022691 Rev 1 95/120

Electrical characteristics STM32F37x

Equation 1: R

AIN

AIN

 f

ADC



max formula

ADC

 ln



N + 2



–

ADC

The formula above (

Equation 1

allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 57.

AIN

max for f

ADC

= 14 MHz

(1)

T s

(cycles) t

(µs)

1.5

0.11

7.5

13.5

28.5

41.5

55.5

71.5

239.5

0.54

0.96

2.04

2.96

3.96

5.11

17.1

Guaranteed by design, not tested in production.

AIN

max (k



)

0.4

5.9

11.4

25.2

37.2

Table 58.

Symbol

ADC accuracy

Parameter

(1)(2) (3)

Test conditions Typ Max

(4)

Unit

Total unadjusted error

Offset error

Gain error

Differential linearity error f

ADC

DDA

= 14 MHz, R

= 3 V to 3.6 V

= 25 °C

AIN

< 10 k



±1.3

±1

±0.5

±0.7

±3

±2

±1.5

±1

LSB

Integral linearity error

Total unadjusted error

Offset error

±0.8

±2

±1.5

±5

±2.5

Gain error

Differential linearity error f

ADC

= 14 MHz, R

AIN

< 10 k



DDA

= 2.5 V to 3.6 V

= -40 to 105 °C

(5)

±1.5

±1

±3

±2

LSB

EL Integral linearity error ±1.5

±3

ADC DC accuracy values are measured after internal calibration.

ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

INJ(PIN) affect the ADC accuracy.

and



INJ(PIN)

Section 5.3.13

does not

Better performance may be achieved in restricted V

DDA

, frequency and temperature ranges.

Data based on characterization results, not tested in production.

DDA

= 2.4 to 3.6 V if T

= 0 to 105 °C

96/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Figure 26.

ADC accuracy characteristics

DDA

1 LSB

IDEAL

4095

4094

4093

(2)

1 LSB

IDEAL

(3)

SSA

1 2 3 4 5 6 7

(1)

4093 4094 4095 4096

DDA

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

=Offset Error: deviation between the first actual transition and the first ideal one.

=Gain Error: deviation between the last ideal transition and the last actual one.

=Differential Linearity Error: maximum deviation between actual steps and the ideal one.

=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

-36

Figure 27.

Typical connection diagram using the ADC

6!).

2!).

!).X

#PARASITIC

6$$

),!

3AMPLEANDHOLD!$#

CONVERTER

2!$#

BIT

CONVERTER

#!$#

-36

Refer to

Table 56

for the values of R

AIN

, R

ADC

and C

ADC

C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high C parasitic this, f

ADC

should be reduced.

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 8

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

Doc ID 022691 Rev 1 97/120

Electrical characteristics STM32F37x

Table 59.

Symbol

DDA

REF+

SSA

LOAD

(1)

DAC characteristics

Parameter Min

Analog supply voltage 2.4

Reference supply voltage

Ground

Resistive load with buffer ON 5

2.4

LOAD

Impedance output with buffer

OFF

Capacitive load

DAC_OUT

min

Lower DAC_OUT voltage with buffer ON

Typ

0.2 -

Max Unit Comments

3.6

DDA

– 0.2

V V

REF+

must always be below V

DDA

V k

 k



When the buffer is OFF, the Minimum resistive load between DAC_OUT and V

1.5 M



to have a 1% accuracy is pF

Maximum capacitive load at

DAC_OUT pin (when the buffer is

ON).

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at V

REF+

= 3.6 V and (0x155) and (0xEAB) at V

REF+

2.4 V

DAC_OUT max

Higher DAC_OUT voltage with buffer ON

DAC_OUT

min

Lower DAC_OUT voltage with buffer OFF

DAC_OUT max

Higher DAC_OUT voltage with buffer OFF

DDVREF+

DAC DC current consumption in quiescent mode (Standby mode)

DDA

DNL

(2)

DAC DC current consumption in quiescent mode (Standby mode)

Differential non linearity

Difference between two consecutive code-1LSB)

0.5

REF+

– 1LSB mV

It gives the maximum output excursion of the DAC.

220

380

480

µA

With no load, worst code (0xF1C) at

REF+

= 3.6 V in terms of DC consumption on the inputs

µA

With no load, middle code (0x800) on the inputs

µA

With no load, worst code (0xF1C) at

REF+

= 3.6 V in terms of DC consumption on the inputs

±0.5 LSB

Given for the DAC in 10-bit configuration

±2

±1

LSB

Given for the DAC in 12-bit configuration

LSB

Given for the DAC in 10-bit configuration

INL

Integral non linearity

(difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)

±4 LSB

Given for the DAC in 12-bit configuration

98/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 59.

Symbol

DAC characteristics (continued)

Parameter Min Typ

Offset

Offset error

(difference between measured value at Code

(0x800) and the ideal value =

REF+

/2)

Gain error

Update rate

Gain error t

SETTLING

Settling time (full scale: for a

10-bit input code transition between the lowest and the highest input codes when

DAC_OUT reaches final value ±1LSB

Max frequency for a correct

DAC_OUT change when small variation in the input code (from code i to i+1LSB)

3 t

WAKEUP

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

PSRR+

Power supply rejection ratio

(to V

DDA

) (static DC measurement

6.5

-67

Guaranteed by design, not tested in production.

Guaranteed by characterization, not tested in production.

Max

±10

±3

±12

±0.5

-40

Unit Comments

Given for the DAC in 12-bit configuration

LSB

Given for the DAC in 10-bit at V

REF+

= 3.6 V

LSB

Given for the DAC in 12-bit at V

REF+

= 3.6 V

Given for the DAC in 12bit configuration

µs C

LOAD



50 pF, R

LOAD



5 k



MS/s C

LOAD



50 pF, R

LOAD



5 k



µs

LOAD



50 pF, R

LOAD



5 k

 input code between lowest and highest possible ones.

dB R

LOAD

, C

LOAD

= 50 pF

Figure 28.

12-bit buffered /non-buffered DAC

B u ffered/Nonbu ffered DAC

B u ffer(1)

LOAD

12b it digit a l to a n a log converter

DACx_OUT

LOAD a i17157

The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

Doc ID 022691 Rev 1 99/120

Electrical characteristics STM32F37x

Table 60.

Symbol

t t

START

DDA

S_SC t

D offset dV offset

/dT

DD(COMP)

Comparator characteristics

Parameter Conditions

Analog supply voltage

Comparator input voltage range

Scaler input voltage

Scaler offset voltage

Scaler startup time from power down

Comparator startup time

Startup time to reach propagation delay specification

Ultra-low power mode

Propagation delay for

200 mV step with 100 mV overdrive

Low power mode

Medium power mode

High speed power mode

DDA



2.7 V



DDA



2.7 V

Ultra-low power mode

Propagation delay for full range step with 100 mV overdrive

Low power mode

Medium power mode

High speed power mode

DDA



2.7 V



DDA



2.7 V

Comparator offset error

Offset error temperature coefficient

COMP current consumption

Ultra-low power mode

Low power mode

Medium power mode

High speed power mode

Min Typ Max

(1)

2 3.6

Unit

0 V

DDA

1.2

±5 ±10

0.1

mV ms

60 µs

1.2

2.1

1.2

180

300



4.5

1.5

0.6

100

240

0.7

0.3

110



0.7

0.3

100

1.5

100

µs ns

µs ns mV

µV/°C

µA

100/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 60.

Symbol

V hys

Comparator characteristics (continued)

Parameter Conditions

No hysteresis

(COMPxHYST[1:0]=00)

Comparator hysteresis

Low hysteresis

(COMPxHYST[1:0]=01)

Medium hysteresis

(COMPxHYST[1:0]=10)

High hysteresis

(COMPxHYST[1:0]=11)

Min Typ Max

(1)

Unit

High speed power mode

All other power modes

High speed power mode

All other power modes

High speed power mode

All other power modes

40 mV

Data based on characterization results, not tested in production.

Doc ID 022691 Rev 1 101/120

Electrical characteristics STM32F37x

Table 61.

Avg_Slope

25 t

START

(1)

Symbol

S_temp

(2)(1)

TS characteristics

Parameter

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature

Min

4.0

1.34

17.1

Typ



4.3

1.43

Guaranteed by design, not tested in production.

Shortest sampling time can be determined in the application by multiple iterations.

Max



4.6

1.52

5.3.22 V

BAT monitoring characteristics

Table 62.

Symbol

BAT

monitoring characteristics

Parameter Min Typ

(1)

S_vbat

(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1mV accuracy

-1

Guaranteed by design, not tested in production.

Shortest sampling time can be determined in the application by multiple iterations.

Max

Unit



µs

Unit

°C mV/°C

µs

102/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 63.

USB startup time

Symbol Parameter

STARTUP

(1)

USB transceiver startup time

Guaranteed by design, not tested in production.

Table 64.

Symbol

USB DC electrical characteristics

Parameter Conditions

Max

Min.

(1)

Unit

µs

Max.

(1)

Unit

Input levels

(4)

USB operating voltage

(2)

Differential input sensitivity

Differential common mode range

Single ended receiver threshold

I(USBDP, USBDM)

Includes V

DI range

3.0

(3)

0.2

0.8

1.3

3.6

2.5

2.0

Output levels

Static output level low

Static output level high

of 1.5 k

of 15 k



to 3.6 V

(5)



to V

(5)

2.8

0.3

3.6

All the voltages are measured from the local ground potential.

To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 k



resistor to a 3.0-to-3.6 V voltage range.

The STM32F3xxx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V V

voltage range.

Guaranteed by design, not tested in production.

is the load connected on the USB drivers

Figure 29.

Differen tial

Data L ines

VCRS

USB timings: definition of data signal rise and fall time (to be added)

Crossover points

VS S tf tr

ai14137

Table 65.

Symbol

USB: Full-speed electrical characteristics

(1)

Parameter

Driver characteristics

t t f r t rfm

CRS

Rise time

(2)

Fall time

Rise/ fall time matching

Output signal crossover voltage

Conditions

= 50 pF

= 50 pF t r

/t f

Min

1.3

Max

110

2.0

Unit

ns ns

Doc ID 022691 Rev 1 103/120

Electrical characteristics STM32F37x

Guaranteed by design, not tested in production.

Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

Refer to

for more details on the input/output alternate

function characteristics (CAN_TX and CAN_RX).

Table 66.

Symbol

SDADC characteristics

Parameter Conditions

I f

SDADC_

VDD

ADC

REF+

REF-

Power supply

SDADC clock frequency

Positive ref. voltage

Negative ref. voltage

Slow mode (f

ADC

= 1.5 MHz)

Fast mode (f

ADC

= 6 MHz)

Slow mode (f

ADC

= 1.5 MHz)

Fast mode (f

ADC

= 6 MHz)

SD_

VDD

Supply current

(SDADC_V

DD = 3.3V)

Fast mode (f

ADC

= 6 MHz)

Slow mode (f

ADC

= 1.5 MHz)

Standby

Power down

SD_ADC off

AIN

DIFF f

Common input voltage range

Differential input voltage

Sampling rate

Single ended mode (zero reference)

Single ended offset mode

Differential mode

Differential mode only

Slow mode (f

ADC

= 1.5 MHz)

Slow mode one channel only (f

ADC

1.5 MHz)

Fast mode multiplexed channel (f

ADC

= 6

MHz)

Fast mode one channel only (f

ADC

= 6 MHz)

Min

2.2

2.4

0.5

Typ

1.5

Max

DDA

1.65

6.3

Unit

MHz

Note

1.1

SDADC

_VDD

SSA

VSSA

SSA

800 1200

600

200

REF

/ gain

REF

/ gain/2

SDADC

_VDD

µA

Voltage on

AINP or

AINN pin

REF

/gain/

4.166

12.5

REF

/ gain/2

Differential voltage between

AINP and

AINN f

ADC

/360 f

ADC

/120 kHz

16.66

50 f

ADC

/360 f

ADC

/120

104/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 66.

Symbol

SDADC characteristics (continued)

Parameter Conditions

CONV

Rain t

CALIB

Conversion time

Analog input impedance

One channel, gain = 0.5, f

ADC

= 1.5 MHz

One channel, gain = 0.5, f

ADC

= 6 MHz

One channel, gain = 8, f

ADC

= 6 MHz

Calibration time f

ADC

= 6 MHz, one offset calibration

Min Typ Max Unit

1/fs

540

135

5120 k s



Note

see reference manual for detailed description t

STAB

Stabilization time

From power down f

ADC

= 6 MHz t

STANDBY

Wakeup from standby time f f

ADC

= 6 MHz

= 1.5 MHz

EO Offset error f f

ADC

1.5 MHz f

ADC

MHz

ADC

MHz f

ADC

= 6

1.5 MHz

REF

= 3.3

REF

= 1.2

REF

= 3.3

REF

= 1.2

SDADC

_VDD =

3.3

REF

= 3.3

REF

= 3.3

REF

= 1.2

REF

= 3.3

REF

= 1.2

REF

= 3.3

Dvoffsett emp

Offset drift with temperature

Differential or single ended mode, gain = 1,

SDADC_VDD = 3.3 V

Gain error gain = 0.5, differential mode, single ended mode gain = 1, differential mode, single ended mode gain = 2, differential mode, single ended mode gain = 4, differential mode, single ended mode gain = 8, differential mode, single ended mode

3.6

100

4.5

100

110

100

1800

1500

5 uV uV/K

µs

30720/f

ADC

600/f

ADC

75/f

ADC

SLOWCK=1

300/f

ADC

75/f

ADC

SLOWCK=1 after offset calibration

Doc ID 022691 Rev 1 105/120

Electrical characteristics STM32F37x

Table 66.

Symbol

SDADC characteristics (continued)

Parameter Conditions

EGT

Gain drift with temperature gain = 1, differential mode, single ended mode

Integral linearity error

REF

= 1.2

REF

= 3.3

REF

= 1.2

SDADC

_VDD=

3.3

REF

= 3.3

REF

= 1.2

REF

= 3.3

REF

= 1.2

Min Typ Max

Unit

ppm/K

LSB

Differential linearity error

REF

= 3.3

REF

= 1.2

REF

= 3.3

REF

= 1.2

SDADC

_VDD=

3.3

REF

= 3.3

REF

= 1.2

REF

= 3.3

REF

= 1.2

REF

= 3.3

2.9

2.8

4.1

2.3

1.8

3.5

3.3

LSB

Note

106/120 Doc ID 022691 Rev 1

STM32F37x Electrical characteristics

Table 66.

Symbol

SDADC characteristics (continued)

Parameter Conditions

SNR

SINAD

Signal to noise ratio

Signal to noise and distortion ratio f f

ADC

1.5 MHz

REF

3.3

(1)

= f

ADC

= 6

MHz

REF

1.2

(2)

REF

= 3.3

REF

1.2

= f

ADC

= 6

MHz f

ADC

= 1.5

MHz

REF

= 3.3

SDADC

_VDD =

3.3

REF

3.3

ADC

1.5MHz

REF

= 3.3

ADC

MHz

= 6

REF

1.2

REF

= 3.3

REF

1.2

= f f

ADC

1.5 MHz

REF

= 3.3

REF

3.3

= f

ADC

= 6

MHz

REF

1.2

REF

= 3.3

REF

1.2

= f

ADC

= 6

MHz f

ADC

= 1.5

MHz

REF

= 3.3

SDADC

_VDD =

3.3

REF

3.3

ADC

1.5MHz

REF

= 3.3

ADC

MHz

= 6

REF

1.2

REF

= 3.3

REF

1.2

REF

= 3.3

Min

Typ Max

Unit

Note

ENOB =

SINAD/6.02

-0.292

Doc ID 022691 Rev 1 107/120

Electrical characteristics STM32F37x

Table 66.

Symbol

SDADC characteristics (continued)

Parameter Conditions Min Typ Max Unit Note

THD

(3)

Total harmonic distortion

Total unadjusted error f

ADC

= 1.5

MHz

REF

3.3

= f f

ADC

= 6

MHz

ADC

MHz

= 6 f

ADC

= 1.5

MHz

REF

1.2

REF

= 3.3

REF

1.2

SDADC

_VDD =

3.3

REF

= 3.3

REF

3.3

REF

1.2

= f

ADC

MHz

= 6

REF

= 3.3

REF

1.2