Arria ® GX Schematic Review Worksheet

Arria ® GX Schematic Review Worksheet
<Project Name> <Date>
Arria® GX Device Schematic Review Worksheet
This document is intended to help you review your schematic and compare the pin usage against the Arria GX Device Family Pin Connection
Guidelines (PDF) version 1.1 and other referenced literature for this device family. The technical content is divided into focus areas such as FPGA
power supplies, transceiver power supplies and pin usage, configuration, FPGA I/O, and external memory interfaces.
Within each focus area, there is a table that contains the voltage or pin name for all of the dedicated and dual purpose pins for the device family.
In some cases, the device density and package combination may not include some of the pins shown in this worksheet, you should cross
reference with the pin-out file for your specific device. Links to the device pin-out files are provided at the top of each section.
Before you begin using this worksheet to review your schematic and commit to board layout, Altera highly recommends:
1) Review the Knowledge Database for Arria GX Device Known Issues and Arria GX Device Handbook Known Issues.
2) Compile your design in the Quartus® II software to completion.
For example, there are many I/O related placement restrictions and VCCIO requirements for the I/O standards used in the device. If you do not
have a complete project, then at a minimum a top level project should be used with all I/O pins defined, placed, and apply all of the configurable
options that you plan to use. All I/O related megafunctions should also be included in the minimal project, including, but not limited to, external
memory interfaces, PLLs, altgx, altlvds, and altddio. The I/O Analysis tool in the Pin Planner can then be used on the minimal project to validate
the pinout in Quartus II software to assure there are no conflicts with the device rules and guidelines.
When using the I/O Analysis tool you must ensure there are no errors with your pinout. Additionally, you should check all warning and critical
warning messages to evaluate their impact on your design. You can right click your mouse over any warning or critical warning message and
select “Help”. This will bring open a new Help window with further information on the cause of the warning, and the action that is required.
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For example, the following warning is generated when a PLL is driven by a global network where the source is a valid dedicated clock input pin,
but the pin is not one dedicated to the particular PLL:
Warning: PLL "<PLL Instance Name>" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by
a non-dedicated input
Info: Input port INCLK[0] of node "<PLL Instance Name>" is driven by clock~clkctrl which is OUTCLK output port of Clock Control Block
type node clock~clkctrl
The help file provides the following:
CAUSE:
ACTION:
The specified PLL's input clock is not driven by a dedicated input pin. As a result, the input clock delay will not be fully compensated
by the PLL. Additionally, jitter performance depends on the switching rate of other design elements. This can also occur if a global
signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.
If you want compensation of the specified input clock or better jitter performance, connect the input clock only to an input pin, or
assign the input pin only to a dedicated input clock location for the PLL. If you do not want compensation of the specified input clock,
then set the PLL to No Compensation mode.
When assigning the input pin to the proper dedicated clock pin location, refer to PLLs in Arria GX Devices (PDF) for the proper port mapping of
dedicated clock input pins to PLLs.
There are many reports available for use after a successful compilation or I/O analysis. For example, you can use the “All Package Pins” and “I/O
Bank Usage” reports within the Compilation – Fitter – Resource Section to see all of the I/O standards and I/O configurable options that are
assigned to all of the pins in your design, as well as view the required VCCIO for each I/O bank. These reports must match your schematic pin
connections.
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The review table has the following heading:
Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
The first column (Plane/Signal) lists the FPGA voltage or signal pin name. You should only edit this column to remove dedicated or dual purpose
pin names that are not available for your device density and package option.
The second column (Schematic Name) is for you to enter your schematic name(s) for the signal(s) or plane connected to the FPGA pin(s).
The third column (Connection Guidelines) should be considered “read only” as this contains Altera’s recommended connection guidelines for the
voltage plane or signal.
The fourth column (Comments/Issues) is an area provided as a “notepad” for you to comment on any deviations from the connection guidelines,
and to verify guidelines are met. In many cases there are notes that provide further information and detail that compliment the connection
guidelines
Here is an example of how the worksheet can be used:
Plane/Signal
<Plane / Signal name
provided by Altera>
VCCINT
Schematic Name
<user entered text>
+1.2V
Connection Guidelines
<Device Specific Guidelines provided by
Altera>
Comments / Issues
<user entered text>
Connected to +1.2V plane, no isolation
is necessary.
Missing low and medium range
decoupling, check PDN.
See Notes (1-1) (1-2).
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Legal Note:
PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THIS SCHEMATIC REVIEW WORKSHEET
(“WORKSHEET”) PROVIDED TO YOU. BY USING THIS WORKSHEET, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND
CONDITIONS, WHICH CONSTITUTE THE LICENSE AGREEMENT ("AGREEMENT") BETWEEN YOU AND ALTERA CORPORATION OR ITS
APPLICABLE SUBSIDIARIES ("ALTERA").
1. Subject to the terms and conditions of this Agreement, Altera grants to you, for no additional fee, a non-exclusive and non-transferable right to
use this Worksheet for the sole purpose of verifying the validity of the pin connections of an Altera programmable logic device-based design. You
may not use this Worksheet for any other purpose. There are no implied licenses granted under this Agreement, and all rights, except for those
granted under this Agreement, remain with Altera.
2. Altera does not guarantee or imply the reliability, or serviceability, of this Worksheet or other items provided as part of this Worksheet. This
Worksheet is provided 'AS IS'. ALTERA DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. ALTERA HAS NO OBLIGATION TO PROVIDE
YOU WITH ANY SUPPORT OR MAINTENANCE.
3. In no event shall the aggregate liability of Altera relating to this Agreement or the subject matter hereof under any legal theory (whether in tort,
contract, or otherwise), exceed One Hundred US Dollars (US$100.00). In no event shall Altera be liable for any lost revenue, lost profits, or other
consequential, indirect, or special damages caused by your use of this Worksheet even if advised of the possibility of such damages.
4. This Agreement may be terminated by either party for any reason at any time upon 30-days’ prior written notice. This Agreement shall be
governed by the laws of the State of California, without regard to conflict of law or choice of law principles. You agree to submit to the exclusive
jurisdiction of the courts in the County of Santa Clara, State of California for the resolution of any dispute or claim arising out of or relating to this
Agreement. The parties hereby agree that the party who is not the substantially prevailing party with respect to a dispute, claim, or controversy
relating to this Agreement shall pay the costs actually incurred by the substantially prevailing party in relation to such dispute, claim, or
controversy, including attorneys' fees. Failure to enforce any term or condition of this Agreement shall not be deemed a waiver of the right to later
enforce such term or condition or any other term or condition of the Agreement.
BY USING THIS WORKSHEET, YOU ACKNOWLEDGE THAT YOU HAVE READ THIS AGREEMENT, UNDERSTAND IT, AND AGREE TO BE
BOUND BY ITS TERMS AND CONDITIONS. YOU AND ALTERA FURTHER AGREE THAT IT IS THE COMPLETE AND EXCLUSIVE
STATEMENT OF THE AGREEMENT BETWEEN YOU AND ALTERA, WHICH SUPERSEDES ANY PROPOSAL OR PRIOR AGREEMENT,
ORAL OR WRITTEN, AND ANY OTHER COMMUNICATIONS BETWEEN YOU AND ALTERA RELATING TO THE SUBJECT MATTER OF THIS
AGREEMENT.
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Index
Section I:
Section II:
Section III:
Section IV:
a:
b:
c:
Section V:
a:
b:
Section VI:
Power
Configuration
Transceiver
I/O
Clock Pins
Dedicated Pins
Dual Purpose Differential I/O pins
External Memory Interface Pins
DDR/2 Interface pins
DDR/2 Termination Guidelines
Document Revision History
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Section I: Power
Arria GX Recommended Reference Literature/Tool List
Arria GX Pin Out Files
Arria GX Device Family Pin Connection Guidelines (PDF)
Power Supply Integrity Support Page (General decoupling guidelines)
Power Delivery Network (PDN) Tool
Power Delivery Network (PDN) Tool User Guide (PDF)
Early Power Estimator
PowerPlay Early Power Estimator User Guide For Arria GX FPGAs (PDF)
PowerPlay Power Analyzer Support Resources
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
AN 597: Getting Started Flow for Board Designs (PDF)
Index
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Plane/Signal
VCCINT
Schematic Name
Connection Guidelines
All VCCINT pins require a 1.2V supply.
Decoupling for these pins depends on the
design decoupling requirements of the specific
board.
VCCIO[1..4,7,8]
Supported voltages are 1.5V, 1.8V, 2.5V, 3.3V.
1.2V is supported on VCCIO[4,7,8] for 1.2V
HSTL I/O standards.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2).
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2).
Decoupling for these pins depends on the
design decoupling requirements of the specific
board.
Index Top of Section
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Plane/Signal
VCCPD[1..4,7,8]
Schematic Name
Connection Guidelines
The VCCPD pins require 3.3V and must rampup from 0V to 3.3V within 100ms to ensure
successful configuration. For Secure
Configuration this needs to power to 3.7V for no
longer than one minute (on VCCPD[8] only).
TDO buffer is powered by VCCIO not VCCPD.
Comments / Issues
Verify Guidelines have been meet or list
required actions for compliance.
See Notes (1-1) (1-2).
Decoupling for these pins depends on the
design decoupling requirements of the specific
board.
GND
All GND pins should be connected to the board
GND plane.
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2).
VREFB[1..4,7,8]
N[2..0]
(not all pins are
available in each
device / package
combination)
Input reference voltage for each I/O bank.
VREF pins for each I/O bank are internally
shorted together and must be connected to the
same voltage level.
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2).
If VREF pins are not used, designers should
connect them to either the VCCIO in the bank in
which the pin resides or GND.
Decoupling for these pins depends on the
design decoupling requirements of the specific
board.
Index Top of Section
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Plane/Signal
VCC_PLL5_OUT
Schematic Name
Connection Guidelines
This pin should be connected to the voltage
level of the target device which PLL5 in bank 9
is driving.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2).
Decoupling for these pins depends on the
design decoupling requirements of the specific
board.
VCC_PLL6_OUT
This pin should be connected to the voltage
level of the target device which PLL6 in bank 10
is driving.
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2).
Decoupling for these pins depends on the
design decoupling requirements of the specific
board.
Index Top of Section
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Plane/Signal
VCC_PLL11_OUT
Schematic Name
(not all pins are
available in each
device / package
combination)
Connection Guidelines
This pin should be connected to the voltage
level of the target device which PLL11 in bank
11 is driving.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2).
For devices which do not have PLL11, but do
have bank 11, VCCIO for bank 3 powers the I/O
pins for bank 11.
Decoupling for these pins depends on the
design decoupling requirements of the specific
board.
VCC_PLL12_OUT
(not all pins are
available in each
device / package
combination)
This pin should be connected to the voltage
level of the target device which PLL12 in bank
12 is driving.
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2).
For devices which do not have PLL12, but do
have bank 12, VCCIO for bank 8 powers the I/O
pins for bank 12.
Decoupling for these pins depends on the
design decoupling requirements of the specific
board.
Index Top of Section
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Plane/Signal
VCCA_PLL[1,2,5..8,
11,12]
Schematic Name
(not all pins are
available in each
device / package
combination)
VCCD_PLL[1,2,5..8,
11,12]
Connection Guidelines
Connect these pins to 1.2V, even if the PLL is
not used. Use an isolated linear supply. Power
on the PLLs operating at the same frequency
should be decoupled.
See Notes (1-1) (1-2).
Decoupling for these pins depends on the
design decoupling requirements of the specific
board.
Connect these pins to 1.2V, even if the PLL is
not used. Power on the PLLs operating at the
same frequency should be decoupled.
(not all pins are
available in each
device / package
combination)
Decoupling for these pins depends on the
design decoupling requirements of the specific
board.
GNDA_PLL[1,2,5..8,
11,12]
All GNDA_PLL pins should be connected to the
board GND plane.
(not all pins are
available in each
device / package
combination)
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2).
Verify Guidelines have been met or list
required actions for compliance.
See Notes (1-1) (1-2).
Index Top of Section
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Notes:
1-1. This worksheet does not calculate required decoupling, it is expected the designer will select decoupling based on analysis of power required
and impedance of power path required based on static and switching current values. Refer to Altera’s Power Supply Integrity Web Support Page
and Power Delivery Network (PDN) Tool for further information.
Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the frequency of
operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and
voltage drop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board
capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design
techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling.
Altera highly recommends using an independent PCB via for each independent power or ground ball on the package. Sharing power or ground
pin vias on the PCB could lead to noise coupling into the device and result in reduced jitter performance.
1-2. This worksheet does not include power estimation for the different power supplies provided. Ensure each power supply is adequate for the
device current requirements. Refer to Altera’s Early Power Estimator Tools and PowerPlay Power Analyzer Support Resources for further
guidance.
Use Altera’s Early Power Estimator Tools to ensure the junction temperature of the device is within operating specifications based on your design
activity.
Additional Comments:
Index Top of Section
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Section II: Configuration
Configuration & Remote System Upgrades (PDF)
Arria GX Device Family Pin Connection Guidelines (PDF)
USB-Blaster Download Cable User Guide (PDF)
ByteBlaster II Download Cable User Guide (PDF)
AN 597: Getting Started Flow for Board Designs (PDF)
Index
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Configuration
Scheme
Configuration
Voltage
VCCIO of Configuration banks
Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
User I/O pins and dual-purpose I/O pins
(nCSO, ASDO, DATA[7..0], nWS, nRS,
RDYnBSY, nCS, CS, RUnLU, PGM[],
CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn)
are on or off before and during configuration. A
logic high (1.5V, 1.8V, 2.5V, or 3.3V) turns off
the weak pull-up, while a logic low turns it on.
Verify Guidelines have been met or list
required actions for compliance.
nIO_PULLUP
The nIO-PULLUP can be tied directly to
VCCPD, use a 1-kΩ pull-up resistor, or tied
directly to GND, depending on how the device
is used.
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Plane/Signal
Schematic Name
VCCSEL
Connection Guidelines
Comments / Issues
Dedicated input that selects which input buffer is
used on configuration input pins: nCONFIG,
DCLK (when used as an input), DATA[7..0],
RUnLU, nCE, nWS, nRS, CS, nCS, and
CLKUSR.
Verify Guidelines have been met or list
required actions for compliance.
The 3.3V/2.5V input buffer is powered by
VCCPD, while the 1.8V/1.5V input buffer is
powered by VCCIO.
A logic high (VCCPD) selects the 1.8V/1.5V
input buffer, while a logic low selects the
3.3V/2.5V input buffer.
VCCSEL should be set to comply with the logic
levels driven out of the configuration device or
MAX II device/microprocessor with flash
memory.
The VCCSEL input buffer is powered by
VCCPD and must be hardwired to VCCPD in
order to enable the 1.8V/1.5V input buffers for
configuration. VCCSEL tied to GND will enable
a 3.3V/2.5V POR trip point, which may be
above 1.8V.
Index Top of Section
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Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
DCLK
Dedicated configuration clock pin. In PS and
FPP configuration, DCLK is used to clock
configuration data from an external source
into the Arria GX device. In AS mode, DCLK
is an output from the Arria GX device that
provides timing for the configuration interface.
In PPA mode, DCLK should be tied to VCC to
prevent this pin from floating.
Verify Guidelines have been met or list
required actions for compliance.
MSEL[3..0]
These pins are internally connected through a
5-kΩ resistor to GND. Do not leave these pins
floating. When these pins are unused,
connect them to GND.
Verify Guidelines have been met or list
required actions for compliance.
Depending on the configuration scheme used,
these pins should be tied to VCCPD or GND
either directly or through 0-Ω resistors. Refer
to Configuring Arria GX Devices (PDF). If only
JTAG configuration is used, connect these
pins to ground.
Index Top of Section
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Plane/Signal
Schematic Name
nCE
Connection Guidelines
Comments / Issues
In multi-device configuration, nCE of the first
device is tied directly to GND while its nCEO
pin drives the nCE of the next device in the
chain. In single device configuration and
JTAG programming, nCE is directly to GND.
Verify Guidelines have been met or list
required actions for compliance.
If you use an Active Serial Programming
header then the nCE should be tied to GND
through a 10-kΩ resistor.
nCONFIG
If the configuration scheme uses an enhanced
configuration device or EPC2, nCONFIG can
be tied directly to the nINIT_CONF pin of the
configuration device. If this pin is not used, it
requires a connection directly or through a
resistor to VCCPD.
Verify Guidelines have been met or list
required actions for compliance.
CONF_DONE
Pull high to VCCIO via an external 10-kΩ
resistor, unless internal pull-up resistors on
the enhanced configuration device are used.
When using EPC2 devices, external 10-kΩ
pull-up resistors must be used.
Verify Guidelines have been met or list
required actions for compliance.
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Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
nCEO
During multi-device configuration, this pin
feeds the nCE pin of a subsequent device.
During single-device configuration, this pin is
left floating. For Connection Guidelines on
how to connect nCEO in a chain with multiple
voltages across the devices in the chain, refer
to Arria GX Architecture (PDF).
Verify Guidelines have been met or list
required actions for compliance.
nSTATUS
Pull high to VCCIO via a 10-kΩ resistor,
unless internal pull-up resistors on the
enhanced configuration device are used.
When using EPC2 devices, external 10-kΩ
pull-up resistors must be used.
Verify Guidelines have been met or list
required actions for compliance.
PORSEL
The PORSEL pin should be tied directly to
VCCPD or GND.
Verify Guidelines have been met or list
required actions for compliance.
When not programming the device in AS
mode, nCSO is not used. Also, when this pin
is not used as an I/O, Altera recommends that
you leave the pin unconnected.
Verify Guidelines have been met or list
required actions for compliance.
Optional/DualPurpose
Configuration Pins
nCSO
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Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
ASDO
When not programming the device in AS
mode, ASDO is not used. Also, when this pin
is not used as an I/O, Altera recommends
that you leave the pin unconnected.
Verify Guidelines have been met or list
required actions for compliance.
CRC_ERROR
When the dedicated output for CRC_ERROR
is not used and this pin is not used as an I/O,
Altera recommends that you leave the pin
unconnected.
Verify Guidelines have been met or list
required actions for compliance.
DEV_CLRn
This pin is optional and allows you to override
all clears on all device registers.
Verify Guidelines have been met or list
required actions for compliance.
When the dedicated input DEV_CLR is not
used and this pin is not used as an I/O, Altera
recommends that you tie this pin to VCCPD
or ground.
DEV_OE
This pin is optional and allows you to override
all tri-states on the device.
Verify Guidelines have been met or list
required actions for compliance.
When the dedicated input DEV_OE is not
used and this pin is not used as an I/O, Altera
recommends that you tie this pin to VCCPD
or ground.
Index Top of Section
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Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
DATA0
Dual-purpose configuration data input pin.
The DATA0 pin can be used for bit-wide
configuration or as an I/O pin after
configuration is complete. When the
dedicated input for DATA0 is not used and it
is not used as an I/O, Altera recommends
that you leave this pin unconnected.
Verify Guidelines have been met or list
required actions for compliance.
DATA[6..1]
When the dedicated inputs for DATA[6..1] are
not used and these pins are not used as an
I/O, Altera recommends that you leave these
pins unconnected.
Verify Guidelines have been met or list
required actions for compliance.
DATA7
When the dedicated input for DATA7 is not
used and it is not used as an I/O, Altera
recommends that you leave this pin
unconnected
Verify Guidelines have been met or list
required actions for compliance.
INIT_DONE
Connect this pin to a 10-kΩ resistor to
VCCIO3.
Verify Guidelines have been met or list
required actions for compliance.
nCS, CS
When the dedicated inputs for nCS, CS are
not used and these pins are not used as an
I/O, Altera recommends that you leave these
pins unconnected.
Verify Guidelines have been met or list
required actions for compliance.
nRS
If the nRS pin is not used in PPA mode, it
should be tied to VCCIO8.
Verify Guidelines have been met or list
required actions for compliance.
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Plane/Signal
Schematic Name
Connection Guidelines
Comments / Issues
nWS
If the device is not being programmed in PPA
mode and the pin is not being used, Altera
recommends that you connect the nWS pin to
the power bank this pin resides in.
Verify Guidelines have been met or list
required actions for compliance.
CLKUSR
If the CLKUSR pin is not used as a
configuration clock input and the pin is not
used as an I/O, Altera recommends that you
connect this pin to ground.
Verify Guidelines have been met or list
required actions for compliance.
RDYnBSY
If the device is not being programmed in PPA
mode and the pin is not being used as an I/O,
Altera recommends that you leave the
RDYnBSY pin unconnected.
Verify Guidelines have been met or list
required actions for compliance.
PGM[2..0]
If the PGM[2..0] pins are not used as page
select output and these pins are not used as
I/O, Altera recommends that you leave these
pins unconnected.
Verify Guidelines have been met or list
required actions for compliance.
RUnLU
If the RUnLU pin is not used as a local or
remote configuration input and the pin is not
used as an I/O, Altera recommends that you
leave this pin unconnected.
Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section
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Plane/Signal
Schematic Name
TCK
Connection Guidelines
Comments / Issues
Connect this pin to a 1-kΩ pull-down resistor
to GND. The JTAG circuitry can be disabled
by connecting TCK to GND.
Verify Guidelines have been met or list
required actions for compliance.
Treat this signal like a clock and follow typical
clock routing guidelines.
TMS
Connect this pin through a pull up resistor
with a value between 1-kΩ and 10-kΩ to
VCCPD.
Verify Guidelines have been met or list
required actions for compliance.
See Note (2-1).
The JTAG circuitry can be disabled by
connecting TMS to VCC.
TDI
Connect this pin through a pull up resistor
with a value between 1-kΩ and 10-kΩ to
VCCPD.
Verify Guidelines have been met or list
required actions for compliance.
See Note (2-1).
The JTAG circuitry can be disabled by
connecting TDI to VCC.
TDO
Connect TDO to the correct JTAG interface
signal. To disable JTAG circuitry, leave TDO
unconnected.
Verify Guidelines have been met or list
required actions for compliance.
TRST
Connect TRST directly to VCCPD if JTAG
circuitry is used. To disable JTAG circuitry,
connect TRST to GND.
Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 22 of 59
<Project Name> <Date>
Plane/Signal
Schematic Name
JTAG Header
Connection Guidelines
Comments / Issues
Power the ByteBlaster II or USB-Blaster
cable’s VCC (pin 4 of the header) with the
same supply as the VCCIO of the I/O bank
that contains the JTAG pins.
Verify Guidelines have been met or list
required actions for compliance.
For multi-device JTAG chains with different
VCCIO voltages, voltage translators may be
required to meet the I/O voltages for the
devices in the chain and JTAG header.
The ByteBlaster II and USB-Blaster cables do
not support a target supply voltage of 1.2 V.
For the target supply voltage value, refer to
the ByteBlaster II Download Cable User
Guide and the USB-Blaster Download Cable
User Guide.
Notes:
2-1. The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin), ByteBlaster II, or
ByteBlasterMV cable.
Additional Notes:
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 23 of 59
<Project Name> <Date>
Section III: Transceiver
Arria GX Recommended Reference Literature/Tool List
Arria GX Pin Out Files
Arria GX Device Family Pin Connection Guidelines (PDF)
Power Supply Integrity Support Page (General decoupling guidelines)
Power Delivery Network (PDN) Tool
Power Delivery Network (PDN) Tool User Guide (PDF)
Early Power Estimator
PowerPlay Early Power Estimator User Guide For Arria GX FPGAs (PDF)
PowerPlay Power Analyzer Support Resources
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
AN 597: Getting Started Flow for Board Designs (PDF)
Technical Brief 92: High-Speed Board Design Advisor Power Distribution Network (PDF)
Index
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 24 of 59
<Project Name> <Date>
Device Plane
VCCA
Schematic Name
Connection Guidelines
GX bank [15..13] analog power. This power is
connected to 3.3V.
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
Connect VCCA to a 3.3V linear regulator.
See Note (3-1).
Decoupling depends on the design decoupling
requirements of the specific board design.
VCCH_B[15..13]
GX bank [15..13] Transmitter driver analog
power.
Verify Guidelines have been met or list required
actions for compliance.
See Note (3-1).
Connect VCCH_B[] to a 1.2V or 1.5V linear
regulator.
Decoupling depends on the design decoupling
requirements of the specific board design.
VCCP
GX bank [15..13] PCS power.
Connect VCCP to an isolated 1.2V linear
regulator. These pins need to be isolated from
noisy digital voltage planes.
Verify Guidelines have been met or list required
actions for compliance.
See Note (3-1).
Decoupling depends on the design decoupling
requirements of the specific board design.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 25 of 59
<Project Name> <Date>
Plane/Signal
VCCL_B[15..13]
Schematic Name
Connection Guidelines
GX bank [15..13] VCO analog power and
general transceiver clock circuitry.
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
Connect VCCL_B[] to a 1.2V linear regulator.
These pins maybe tied to the same 1.2V plane
as VCCT_B[] and/or VCCR.
However, for the best jitter performance at high
data rates, this plane should be isolated from all
other power supplies.
See Note (3-1).
Decoupling depends on the design decoupling
requirements of the specific board design.
VCCT_B[15..13]
GX bank [15..13] transmitter analog power.
Connect VCCT_B[] to a 1.2V linear regulator.
These pins may be tied to the same 1.2V plane
as VCCR and/or VCCL_B[].
However, for the best jitter performance at high
data rates, this plane should be isolated from all
other power supplies.
Verify Guidelines have been met or list required
actions for compliance.
See Note (3-1).
Decoupling depends on the design decoupling
requirements of the specific board design.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 26 of 59
<Project Name> <Date>
Plane/Signal
VCCR
Schematic Name
Connection Guidelines
GX bank [15..13] receiver analog power
Connect VCCR to a 1.2V linear regulator.
These pins may be tied to the same 1.2V plane
as VCCT_B[] and/or VCCL_B[].
However, for the best jitter performance at high
data rates, this plane should be isolated from all
other power supplies.
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (3-1).
Decoupling depends on the design decoupling
requirements of the specific board design.
REFCLK[0,1]_B
[15..13]p/n
High speed differential I/O reference clocks.
Verify Guidelines have been met or list required
actions for compliance.
These pins should be AC coupled when used.
See Note (3-2).
Connect unused REFCLK[0,1]_B[]p pins to the
VCCT_B[] or VCCR tied together w/ VCCT_B[])
1.2V plane either individually through a 10k-Ω
resistor or tie all unused pins together through a
single 10k-Ω resistor.
Connect all unused REFCLK[0,1]_B[]n pins
either individually to GND through a 10k-Ω
resistor or tie all unused pins together through a
single 10k-Ω resistor.
Ensure that the trace from pin to the resistor is
as short as possible.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 27 of 59
<Project Name> <Date>
Device Pins
GXB_RX[11..0]p/n
Schematic Name
Connection Guidelines
High speed differential receiver channels.
Comments/ Issues
Verify Guidelines have been met or list required
actions for compliance.
These pins should be AC coupled when used.
See Note (3-3).
Connect all unused GXB_RX[]p pins to the
VCCR 1.2V plane either individually through a
10k-Ω resistor or tie all unused pins together
through a single 10k-Ω resistor.
Connect all unused GXB_RX[]n pins either
individually to GND through a 10k-Ω resistor or
tie all unused pins together through a single
10k-Ω resistor.
Ensure that the trace from the pins to the
resistor(s) is as short as possible.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 28 of 59
<Project Name> <Date>
Device Pins
GXB_TX[11..0]p/n
Schematic Name
Connection Guidelines
High speed differential transmitter channels.
Comments/ Issues
Verify Guidelines have been met or list required
actions for compliance.
These pins should be AC coupled when used.
See Note (3-4).
Connect all unused GXB_TX[]p pins to the
VCCT_B[] or VCCR (if tied together w/
VCCT_B[]) 1.2V plane either individually
through a 10k-Ω resistor or tie all unused pins
together through a single 10k-Ω resistor
Connect all unused GXB_TX[]n pins either
individually to GND through a 10k-Ω resistor or
tie all unused pins together through a single
10k-Ω resistor.
Ensure that the trace from the pins to the
resistor(s) is as short as possible.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 29 of 59
<Project Name> <Date>
Device Pins
RREFB[15..13]
Schematic Name
Connection Guidelines
Reference resistor for GX side banks.
These pins should be connected to a 2.00k-Ω
1% resistor to GND.
Comments/ Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (3-5).
In the PCB layout, the trace from this pin to the
resistor needs to be routed so that it avoids any
aggressor signals.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 30 of 59
<Project Name> <Date>
Notes:
3-1. This worksheet does not calculate required decoupling, it is expected the designer will select decoupling based on analysis of power required
and impedance of power path required based on static and switching current values. Refer to Altera’s Power Supply Integrity Web Support Page
and Power Delivery Network (PDN) Tool for further information.
Capacitance values for the power supply should be selected after considering the amount of power they need to supply over the frequency of
operation of the particular circuit being decoupled. The target impedance for the power plane should be calculated based on current draw and
voltage droop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors. Onboard capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board
design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling.
Altera highly recommends using an independent PCB via for each independent power or ground ball on the package. Sharing power or ground
pin vias on the PCB could lead to noise coupling into the device and result in reduced jitter performance.
3-2. In PCI Express configuration, DC-coupling is allowed on REFCLK if the selected REFCLK I/O standard is HCSL (High-Speed Current
Steering Logic).
3-3. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires the AC-coupling
capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
3-4. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires the AC-coupling
capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
3-5. Each pin must have a separate resistor.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 31 of 59
<Project Name> <Date>
Additional Comments:
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 32 of 59
<Project Name> <Date>
Section IV: I/O
Arria GX Recommended Reference Literature/Tool List
Arria GX Pin Out Files
Arria GX Device Family Pin Connection Guidelines (PDF)
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
AN 597: Getting Started Flow for Board Designs (PDF)
Index
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 33 of 59
<Project Name> <Date>
Part A: Clock Pins
Plane/Signal
CLK[1,3]p
Schematic Name
Connection Guidelines
These pins can be used as single ended or
differential clock input pins or general single
ended or differential input pins. Connect
unused pins to the bank VCCIO or GND.
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
Use dedicated clock pins to drive clocks into the
device. These pins can connect to the device
PLLs.
These pins do not support differential OCT.
These pins can only be used as inputs, they do
not support output functions.
These pins do not support the programmable
weak internal pull up resistor option.
CLK[1,3]n
These pins can be used as general single
ended input pins or negative clock input pins for
differential clock input. Connect unused pins to
GND.
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
When used as single ended inputs, these pins
do not connect to the global / regional networks
and cannot drive PLL inputs.
These pins can only be used as inputs, they do
not support output functions.
These pins do not support the programmable
weak internal pull up resistor option.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 34 of 59
<Project Name> <Date>
Plane/Signal
CLK[0,2]p
Schematic Name
Connection Guidelines
These pins can be used as single ended I/O
pins, single ended clock input pins with PLL
connectivity, the positive terminal data pins of
differential receiver channels, or the positive
terminal of differential clocks.
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins support differential OCT.
Unused pins can be tied to GND or
unconnected. If unconnected, use Quartus II
software programmable options to internally
bias these pins. They can be reserved as
inputs tristate with weak pull up resistor
enabled, or as outputs driving GND.
CLK[0,2]n
These pins can be used as I/O pins, the
negative clock input pins for differential clock
input, or the negative data pins of differential
receiver channels.
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
When used as single ended inputs, these pins
do not connect to the global / regional networks
and cannot drive PLL inputs.
Unused pins can be tied to GND or
unconnected. If unconnected, use Quartus II
software programmable options to internally
bias these pins. They can be reserved as
inputs tristate with weak pull up resistor
enabled, or as outputs driving GND.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 35 of 59
<Project Name> <Date>
Plane/Signal
CLK[4-7,12-15]p
Schematic Name
Connection Guidelines
These pins can be used as single ended or
positive differential clock input pins with PLL
connectivity or general single ended or positive
differential input pins. They can also be used as
general single ended output pins.
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins do not support differential OCT.
These pins can be used for input or output (nondifferential) operations.
Unused pins can be tied to GND or
unconnected. If unconnected, use Quartus II
software programmable options to internally
bias these pins. They can be reserved as
inputs tristate with weak pull up resistor
enabled, or as outputs driving GND.
CLK[4-7,12-15]n
These pins can be used as single ended or
negative differential clock input pins with PLL
connectivity or general single ended or negative
differential input pins. They can also be used as
general single ended output pins.
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins can connect to the global / regional
networks.
Unused pins can be tied to GND or
unconnected. If unconnected, use Quartus II
software programmable options to internally
bias these pins. They can be reserved as
inputs tristate with weak pull up resistor
enabled, or as outputs driving GND.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 36 of 59
<Project Name> <Date>
Plane/Signal
FPLL[7..8]CLKp
Schematic Name
(not all pins are
available in each
device / package
combination)
Connection Guidelines
Dedicated positive clock inputs for fast PLLs
(PLLs 7 and 8) which can also be used for data
inputs. Connect unused pins to the bank VCCIO
or GND.
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins do not support differential OCT.
These pins do not connect to the global /
regional networks.
These pins can only be used as inputs, they do
not support output functions.
These pins do not support the programmable
weak internal pull up resistor option.
FPLL[7..8]CLKn
(not all pins are
available in each
device / package
combination)
Dedicated negative clock inputs for fast PLLs
(PLLs 7 through 10) which can also be used for
data inputs. Connect unused pins to GND.
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
When used as single ended input, this pin does
not connect to a PLL.
These pins do not connect to the global /
regional networks, and they cannot be used for
output functions.
These pins do not support the programmable
weak internal pull up resistor option.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 37 of 59
<Project Name> <Date>
Plane/Signal
PLL5_OUT[1,0]p
Schematic Name
Connection Guidelines
Optional positive external clock outputs [1,0]
from enhanced PLL 5. These pins can be
differential (two output pin pairs) or single ended
(four clock outputs from PLL5).
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins cannot be used as differential
inputs, but can be used as general purpose I/O
pins if not used as PLL outputs.
These pins support LVDS and LVPECL output
operations when VCC_PLL5_OUT is powered
by 3.3V.
PLL5_OUT[1,0]n
Optional negative external clock outputs [1,0]
from enhanced PLL 5. These pins can be
differential (two output pin pairs) or single ended
(four clock outputs from PLL5).
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins cannot be used as differential
inputs, but can be used as general purpose I/O
pins if not used as PLL outputs.
These pins support LVDS and LVPECL output
operations when VCC_PLL5_OUT is powered
by 3.3V.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 38 of 59
<Project Name> <Date>
Plane/Signal
PLL6_OUT[1,0]p
Schematic Name
Connection Guidelines
Optional positive external clock outputs [1,0]
from enhanced PLL 6. These pins can be
differential (two output pin pairs) or single ended
(four clock outputs from PLL6).
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins cannot be used as differential
inputs, but can be used as general purpose I/O
pins if not used as PLL outputs.
These pins support LVDS and LVPECL output
operations when VCC_PLL6_OUT is powered
by 3.3V.
PLL6_OUT[1,0]n
Optional negative external clock outputs [1,0]
from enhanced PLL 6. These pins can be
differential (two output pin pairs) or single ended
(four clock outputs from PLL6).
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins cannot be used as differential
inputs, but can be used as general purpose I/O
pins if not used as PLL outputs.
These pins support LVDS and LVPECL output
operations when VCC_PLL6_OUT is powered
by 3.3V.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 39 of 59
<Project Name> <Date>
Plane/Signal
PLL11_OUT[1,0]p
Schematic Name
(not all pins are
available in each
device / package
combination)
Connection Guidelines
Optional positive external clock outputs [1,0]
from enhanced PLL 11. These pins can be
differential (two output pin pairs) or single ended
(four clock outputs from PLL11).
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins cannot be used as differential
inputs, but can be used as general purpose I/O
pins if not used as PLL outputs.
These pins support LVDS and LVPECL output
operations when VCC_PLL11_OUT is powered
by 3.3V.
PLL11_OUT[1,0]n
(not all pins are
available in each
device / package
combination)
Optional negative external clock outputs [1,0]
from enhanced PLL 11. These pins can be
differential (two output pin pairs) or single ended
(four clock outputs from PLL11).
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins cannot be used as differential
inputs, but can be used as general purpose I/O
pins if not used as PLL outputs.
These pins support LVDS and LVPECL output
operations when VCC_PLL11_OUT is powered
by 3.3V.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 40 of 59
<Project Name> <Date>
Plane/Signal
PLL12_OUT[1,0]p
Schematic Name
(not all pins are
available in each
device / package
combination)
Connection Guidelines
Optional positive external clock outputs [1,0]
from enhanced PLL 12. These pins can be
differential (two output pin pairs) or single ended
(four clock outputs from PLL12).
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins cannot be used as differential
inputs, but can be used as general purpose I/O
pins if not used as PLL outputs.
These pins support LVDS and LVPECL output
operations when VCC_PLL12_OUT is powered
by 3.3V.
PLL12_OUT[1,0]n
(not all pins are
available in each
device / package
combination)
Optional negative external clock outputs [1,0]
from enhanced PLL 12. These pins can be
differential (two output pin pairs) or single ended
(four clock outputs from PLL12).
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins cannot be used as differential
inputs, but can be used as general purpose I/O
pins if not used as PLL outputs.
These pins support LVDS and LVPECL output
operations when VCC_PLL12_OUT is powered
by 3.3V.
Index Top of Section
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DS_01005-2.1
Page 41 of 59
<Project Name> <Date>
Plane/Signal
PLL[5..6]_FBp/
OUT2p
Schematic Name
Connection Guidelines
These pins can be used as I/O pins, positive
external feedback input pins or external clock
outputs for PLL[5,6].
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins can be configured as general I/O, as
positive differential input, or as positive
differential output. They do not support
bidirectional differential operations, and do not
support differential OCT.
Differential standards are supported when
VCC_PLL[5..6]_OUT is powered by 3.3V.
Unused pins can be connected to GND, or
internally biased with Quartus II software
reserve pin settings.
PLL[5..6]_FBn/
OUT2n
These pins can be used as I/O pins, negative
external feedback input pins or external clock
outputs for PLL[5,6].
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins can be configured as general I/O, as
negative differential input, or as negative
differential output. They do not support
bidirectional differential operations, and do not
support differential OCT.
Differential standards are supported when
VCC_PLL[5..6]_OUT is powered by 3.3V.
Unused pins can be connected to GND, or
internally biased with Quartus II software
reserve pin settings.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 42 of 59
<Project Name> <Date>
Plane/Signal
PLL[11..12]_FBp/
OUT2p
Schematic Name
(not all pins are
available in each
device / package
combination)
Connection Guidelines
These pins can be used as I/O pins, positive
external feedback input pins or external clock
outputs for PLL[11,12].
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins can be configured as general I/O, as
positive differential input, or as positive
differential output. They do not support
bidirectional differential operations, and do not
support differential OCT.
Differential standards are supported when
VCC_PLL[11..12]_OUT is powered by 3.3V.
Unused pins can be connected to GND, or
internally biased with Quartus II software
reserve pin settings.
PLL[11..12]_FBn/
OUT2n
(not all pins are
available in each
device / package
combination)
These pins can be used as I/O pins, negative
external feedback input pins or external clock
outputs for PLL[11,12].
Verify Guidelines have been met or list required
actions for compliance.
See Note (4-1).
These pins can be configured as general I/O, as
negative differential input, or as negative
differential output. They do not support
bidirectional differential operations, and do not
support differential OCT.
Differential standards are supported when
VCC_PLL[11..12]_OUT is powered by 3.3V.
Unused pins can be connected to GND, or
internally biased with Quartus II software
reserve pin settings.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 43 of 59
<Project Name> <Date>
Notes:
4-1. Refer to Knowledge Database solution rd12102002_3281 for further information regarding the concerns when I/O pins are left floating with no
internal or external bias. Ensure there are no conflicts between the Quartus II software device wide default configuration for unused I/Os and the
board level connection. Altera recommends setting unused I/O pins on a project wide basis to behave as inputs tri-state with weak pull up resistor
enabled. Individual unused pins can be reserved with specific behavior such as output driving ground or as output driving VCC to comply with the
PCB level connection.
Additional Comments:
Index Top of Section
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DS_01005-2.1
Page 44 of 59
<Project Name> <Date>
Part B: Dedicated Pins
Plane/Signal
Schematic Name
NC
Connection Guidelines
Do not drive signals into these pins.
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
When migrating devices, in some cases NC
pins need to be connected to VCC/GND to allow
successful migration see Knowledge Database
solution rd03132006_933.
PLL_ENA
If a PLL uses the pllena port, drive the
PLL_ENA pin low to reset all PLLs, including the
counters, to their default state.
Verify Guidelines have been met or list required
actions for compliance.
If VCCSEL = 0, then you must drive the
PLL_ENA with a 3.3/2.5V signal to enable the
PLLs. If VCCSEL = 1, connect PLL_ENA to
1.8/1.5 V to enable the PLLs.
If no PLLs use the pllena port, this pin can be
tied to GND.
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 45 of 59
<Project Name> <Date>
Part C: Dual Purpose Differential I/O pins
Plane/Signal
Schematic Name
Connection Guidelines
DIFFIO_RX[##]p,n
Dual-purpose differential receiver channels.
These channels can be used for receiving
(Refer to the device
LVDS-compatible signals. Pins with a "p" suffix
Pin Table for number
carry the positive signal for the differential
of channels based
channel. Pins with an "n" suffix carry the
on device selected)
negative signal for the differential channel.
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See note (4-2).
These pins support OCT Rd.
These pins do not support differential
transmitter operations.
If not used for differential signaling, these pins
are available as single ended user I/O pins.
Unused pins can be tied to GND or
unconnected. If unconnected, use Quartus II
software programmable options to internally
bias these pins. They can be reserved as
inputs tristate with weak pull up resistor
enabled, or as outputs driving GND.
Index Top of Section
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DS_01005-2.1
Page 46 of 59
<Project Name> <Date>
Plane/Signal
DIFFIO_TX[##]p,n
Schematic Name
(Refer to the device
Pin Table for number
of channels based
on device selected)
Connection Guidelines
Dual-purpose differential transmitter channels.
These channels can be used for transmitting
LVDS-compatible signals. Pins with a "p" suffix
carry the positive signal for the differential
channel. Pins with an "n" suffix carry the
negative signal for the differential channel.
Comments / Issues
Verify Guidelines have been met or list required
actions for compliance.
See note (4-2).
These pins do not support differential receiving
operations.
If not used for differential signaling, these pins
are available as single ended user I/O pins.
Unused pins can be tied to GND or
unconnected. If unconnected, use Quartus II
software programmable options to internally
bias these pins. They can be reserved as
inputs tristate with weak pull up resistor
enabled, or as outputs driving GND.
Notes:
4-2. Refer to Knowledge Database solution rd12102002_3281 for further information regarding the concerns when I/O pins are left floating with no
internal or external bias. Ensure there are no conflicts between the Quartus II software device wide default configuration for unused I/Os and the
board level connection. Altera recommends setting unused I/O pins on a project wide basis to behave as inputs tri-state with weak pull up resistor
enabled. Individual unused pins can be reserved with specific behavior such as output driving ground or as output driving VCC to comply with the
PCB level connection.
Index Top of Section
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DS_01005-2.1
Page 47 of 59
<Project Name> <Date>
Additional Comments:
Index Top of Section
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DS_01005-2.1
Page 48 of 59
<Project Name> <Date>
Section V: External Memory Interface Pins
Arria GX Literature
External Memory Interfaces in Arria GX Devices (PDF)
Arria GX Pin Out Files
Arria GX Device Family Pin Connection Guidelines (PDF)
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
AN 597: Getting Started Flow for Board Designs (PDF)
External Memory Interface Literature
AN 449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices (PDF)
Board Layout Guidelines (PDF)
DDR and DDR2 Literature
AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (PDF)
Board Layout Guidelines (PDF)
Index
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DS_01005-2.1
Page 49 of 59
<Project Name> <Date>
Part A: DDR/2 Interface
Pins
Plane/Signal
Data pins - DQ
Schematic Name
Connection Guidelines
Place it on DQ pins of the DQ/DQS group.
The order of the DQ bits within a designated
DQ group/bus is not important; however, use
caution when making pin assignments if you
plan on migrating to a different memory
interface that has a different DQ bus width
(e.g. migrating from x4 to x8). Analyze the
available DQ pins across all pertinent DQS
columns in the pin list.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
Data strobe - DQS/DQSn
Only Single ended DQS is supported.
Connect the DQS pin to the DQS pin of the
corresponding DQ/DQS group.
Verify Guidelines have been met or list
required actions for compliance.
Data Mask DM
Place it on one of the DQ pins in the group.
DM pins need to be part of the write DQS/DQ
group.
Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section
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DS_01005-2.1
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<Project Name> <Date>
Plane/Signal
mem_clk and mem_clk_n
Schematic Name
Connection Guidelines
1) PLL dedicated clock output pin pairs on
the same side as the interface resides.
2) DQS/DQSn pin pair in the same bank or
side as the interface resides.
3) If the above pins are not available,
memory clock can be assigned any
regular I/O pins.
4) Dedicated PLL clock output pins are ideal
for memory clock pins as they are
optimized for SI, but if the design is big
and the data pins are using up all top
bank pins then LVDS pin pairs on the side
banks of the device can be used.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
clock_source
The clock input pin of the system PLL should
be on the same side or same bank of the
device as the data, address and command
signals. (CLK[4..7]&[12..15]p/n pair can be
used as input clock pin. For single ended
clock sources, ALWAYS use the p pin of the
dedicated clock inputs.
Verify Guidelines have been met or list
required actions for compliance.
Address
Any user I/O pin. To minimize skew, you
should place address and command pins in
the same bank or side of the device as the
following pins:
● mem_clk* pins.
● DQ, DQS, or DM pins.
Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section
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DS_01005-2.1
Page 51 of 59
<Project Name> <Date>
Plane/Signal
Command
Schematic Name
Reset
Connection Guidelines
Any user I/O pin. To minimize skew, you
should place address and command pins in
the same bank or side of the device as the
following pins:
● mem_clk* pins.
● DQ, DQS, or DM pins.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
Dedicated clock input pin. (high fan-out signal)
Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section
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DS_01005-2.1
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<Project Name> <Date>
Part B: DDR/2
Termination
Guidelines
Plane/Signal
Memory clocks @
Memory
Schematic Name
Connection Guidelines
Memory clocks use Unidirectional class I
termination. They are typically differentially
terminated with an effective 100-Ω resistance.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
For DIMM no termination is required as
termination is placed on the DIMM itself.
Memory clocks @
FPGA
[email protected]
Use series 50-Ω OCT output termination
without calibration on the FPGA side by
sourcing
<variation_name>_pin_assignments.tcl file to
make these assignments automatically for hp
ddr2 controller.
Verify Guidelines have been met or list
required actions for compliance.
For DDR2 use ODT feature. For DDR use
50-Ω external parallel termination.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
See Note (5-1).
Index Top of Section
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<Project Name> <Date>
Plane/Signal
DQS @ FPGA
Schematic Name
Connection Guidelines
Use series 25-Ω OCT without calibration as
output termination. Source
<variation_name>_pin_assignments.tcl file to
make these assignments automatically for hp
ddr2 controller.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
Use external parallel 50-Ω as input
termination.
DQ @ Memory
For DDR2 use ODT feature. For DDR use
50-Ω external parallel termination.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
DQ @ FPGA
Use series 25-Ω OCT without calibration as
output termination. Source
<variation_name>_pin_assignments.tcl file to
assign these assignments automatically for hp
ddr2 controller.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
Use external parallel 50-Ω as input
termination.
[email protected] Memory
For DDR2 use ODT. For DDR Use 50-Ω
external parallel termination.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
Index Top of Section
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<Project Name> <Date>
Plane/Signal
DM @ FPGA
Schematic Name
Address [BA,
mem_addr] @ Memory
Address [BA,
mem_addr] @ FPGA
Connection Guidelines
Use series 50-Ω OCT without calibration as
output termination. Source
<variation_name>_pin_assignments.tcl file to
make this assignment automatically.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
Unidirectional class I termination. For multiloads Altera recommends the ideal topology is
a balanced symmetrical tree. Altera
recommends that the class I termination to
VTT is placed:
■ At the DIMM connector (for interfaces using
DIMMs).
■ At the first split or division of the
symmetrical tree for discrete devices.
Nonsymmetrical topologies or DIMMs result in
over or undershoot and oscillations on the
line, which may require compensation
capacitors or a lower than ideal drive strength
to be specified resulting in de-rated interface
performance.
Verify Guidelines have been met or list
required actions for compliance.
Use maximum current strength setting.
Source
<variation_name>_pin_assignments.tcl file to
make this assignment automatically for hp
ddr2 controller.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
See Note (5-1).
See Note (5-1).
Index Top of Section
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DS_01005-2.1
Page 55 of 59
<Project Name> <Date>
Plane/Signal
Command [CKE,
CS_N, RAS, CAS,
WE_N] @ Memory
Schematic Name
Command [CKE,
CS_N, RAS, CAS,
WE_N] @ FPGA
Connection Guidelines
Unidirectional class I termination. All class I
signals are multi-load signals—they either go
to a DIMM that has multiple memory devices,
or they go to all memory devices that make up
the interface. Altera recommends the ideal
topology is a balanced symmetrical tree.
Altera recommends that the class I
termination to VTT is placed:
■ At the DIMM connector (for interfaces using
DIMMs)
■ At the first split or division of the
symmetrical tree for discrete devices
Nonsymmetrical topologies or DIMMs result in
over or undershoot and oscillations on the
line, which may require compensation
capacitors or a lower than ideal drive strength
to be specified resulting in derated interface
performance.
Comments / Issues
Verify Guidelines have been met or list
required actions for compliance.
Use maximum current strength setting.
Source
<variation_name>_pin_assignments.tcl file to
make this assignment automatically for hp
ddr2 controller.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-1).
See Note (5-1).
Notes:
5-1. The termination schemes suggested in the table are general guidelines. You should do board level simulation for your particular system/board
to determine optimal termination scheme.
Index Top of Section
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DS_01005-2.1
Page 56 of 59
<Project Name> <Date>
Miscellaneous
Pin Description
Vref
Schematic Name
Connection Guidelines
Use a voltage regulator to generate this
voltage.
Comments/ Issues
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-2).
Vtt
Use a voltage regulator to generate this
voltage.
Verify Guidelines have been met or list
required actions for compliance.
See Note (5-2).
Notes:
5-2. This worksheet does not calculate required decoupling, it is expected the designer will select decoupling based on analysis of power required
and impedance of power path required based on static and switching current values. Refer to Altera’s Power Supply Integrity Web Support Page
and Power Delivery Network (PDN) Tool for further information.
Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the frequency of
operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and
voltage drop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board
capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design
techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling.
Index Top of Section
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DS_01005-2.1
Page 57 of 59
<Project Name> <Date>
Additional Comments:
Index Top of Section
Arria GX Schematic Review Worksheet 2.1
DS_01005-2.1
Page 58 of 59
<Project Name> <Date>
Section VI: Document Revision History
Revision
Changes Made
Date
V2.1
Synchronized to Arria GX Pin Connection Guidelines version 1.1.
Updated pull up resistor values for TMS and TDI.
Minor text and formatting edits throughout the document.
April 2010
Initial Release, based on Arria GX Pin Connection Guidelines version 1.0.
May 2009
V2.0
Index
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DS_01005-2.1
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