S25FL064A 64 Megabit CMOS 3.0 Volt Flash Memory Data Sheet

S25FL064A 64 Megabit CMOS 3.0 Volt Flash Memory Data Sheet

S25FL064A

64 Megabit CMOS 3.0 Volt Flash Memory with 50-MHz SPI (Serial Peripheral Interface) Bus

Data Sheet

S25FL064A Cover Sheet

This product has been retired and is not recommended for designs. For new and current designs,

S25FL064P supercedes S25FL064A. This is the factory-recommended migration path. Please refer to the

S25FL064P data sheet for specifications and ordering information.

Availability of this document is retained for reference and historical purposes only.

Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.

Publication Number S25FL064A_00 Revision C Amendment 4 Issue Date February 27, 2009

D a t a S h e e t

Notice On Data Sheet Designations

Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion

Inc. therefore places the following conditions upon Advance Information content:

“This document contains information on one or more products under development at Spansion Inc.

The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:

“This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.”

Combination

Some data sheets contain a combination of products with different designations (Advance Information,

Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC

Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or V

IO

range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local sales office.

2 S25FL064A S25FL064A_00_C4 February 27, 2009

S25FL064A

64 Megabit CMOS 3.0 Volt Flash Memory with 50-MHz SPI (Serial Peripheral Interface) Bus

Data Sheet

This product has been retired and is not recommended for designs. For new and current designs, S25FL064P supercedes

S25FL064A. This is the factory-recommended migration path. Please refer to the S25FL064P data sheet for specifications and ordering information.

Distinctive Characteristics

Architectural Advantages

„ Single power supply operation

– Full voltage range: 2.7 to 3.6 V read and program operations

„ Memory Architecture

– 128 sectors with 512 Kb each

„ Program

– Page Program (up to 256 bytes) in 1.5 ms (typical)

– Program operations are on a page by page basis

„ Erase

– 1.5 s typical sector erase time

– Bulk erase command

„ Cycling Endurance

– 100,000 cycles per sector typical

„ Data Retention

– 20 years typical

„ Device ID

– JEDEC standard two-byte electronic signature

– RES command one-byte electronic signature for backward compatibility

„ Process Technology

– Manufactured on 0.20 µm MirrorBit

®

process technology

„ Package Option

– Industry Standard Pinouts

– 16-pin SO package (300 mils)

Performance Characteristics

„ Speed

– 50 MHz clock rate (maximum)

„ Power Saving Standby Mode

– Standby Mode 50 µA (max)

– Deep Power Down Mode 1 µA (typical)

Memory Protection Features

„ Memory Protection

– W# pin works in conjunction with Status Register Bits to protect specified memory areas

– Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read-only

Software Features

– SPI Bus Compatible Serial Interface

General Description

The S25FL064A is a 3.0 Volt (2.7 V to 3.6 V), single-power-supply Flash memory device. The device consists of 128 sectors, each with 512 Kb memory.

The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3.0 volt V

CC

supply.

The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands.

Each device requires only a 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device does not require a

V

PP

supply.

Publication Number S25FL064A_00 Revision C Amendment 4 Issue Date February 27, 2009

This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.

D a t a S h e e t

Table of Contents

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.1

Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.

Spansion SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.

Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.1

Byte or Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.2

Sector Erase / Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.3

Monitoring Write Operations Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.4

Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.5

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.6

Data Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.7

Hold Mode (HOLD#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.

Sector Address Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

9.

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9.1

Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9.2

Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

9.3

Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9.4

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9.5

Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9.6

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9.7

Write Status Register (WRSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9.8

Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.9

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.10

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.11

Deep Power Down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.12

Release from Deep Power Down (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.

Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

11.

Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

12.

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

13.

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

14.

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15.

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

16.

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

17.

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

17.1

SO3 016 wide—16-pin Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . . . 35

18.

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

February 27, 2009 S25FL064A_00_C4 S25FL064A 5

D a t a S h e e t

Figures

Figure 2.1

Figure 6.1

Figure 6.2

Figure 7.1

Figure 9.1

Figure 9.2

Figure 9.3

Figure 9.4

16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 17

Read Identification (RDID) Command Sequence and Data-Out Sequence . . . . . . . . . . . . . 18

Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9.5

Figure 9.6

Figure 9.7

Figure 9.8

Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read Status Register (RDSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Write Status Register (WRSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Page Program (PP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9.9

Sector Erase (SE) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9.10

Bulk Erase (BE) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 9.11

Deep Power Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 9.12

Release from Deep Power Down (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 9.13

Release from Deep Power Down and Read Electronic Signature (RES)

Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 10.1

Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12.1

Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 12.2

Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 15.1

AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 16.1

SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 16.2

SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 16.3

HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 16.4

Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . . 34

6 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

Tables

Table 5.1

Table 7.1

Table 8.1

Table 8.2

Table 9.1

Table 9.2

Table 9.3

Table 9.4

S25FL064A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

S25FL064A Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

S25FL064A Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

S25FL064A Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

S25FL064A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 10.1

Power-Up Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 12.1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 13.1

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 14.1

DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 15.1

Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 16.1

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

February 27, 2009 S25FL064A_00_C4 S25FL064A 7

1.

Block Diagram

SRAM

D a t a S h e e t

PS

Logic

Array - L

X

D

E

C

Array - R

RD

IO

DATA PATH

8

2.

Connection Diagrams

Figure 2.1 16-pin Plastic Small Outline Package (SO)

HOLD#

VCC

NC

NC

NC

NC

CS#

SO

3

4

5

6

7

8

1

2

16

SCK

14

13

12

11

10

9

15

SI

NC

NC

NC

NC

GND

W#

S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

3.

Input/Output Descriptions

Signal

SO

SI

SCK

CS#

HOLD#

W#

V

CC

GND

I/O Description

Output Signal Data Output: Transfers data serially out of the device on the falling edge of SCK.

Input

Input

Input

Serial Data Input: Transfers data serially into the device. Device latches commands, addresses, and program data on SI on the rising edge of SCK.

Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on rising edge of SCK. Triggers output on SO after the falling edge of SCK.

Chip Select: Places device in active power mode when driven low. Deselects device and places

SO at high impedance when high. After power-up, device requires a falling edge on CS# before any command is written. Device is in standby mode when a program, erase, or Write Status

Register operation is not in progress.

Input

Input

Input

Input

Hold: Pauses any serial communication with the device without deselecting it. When driven low,

SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be driven low.

Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When driven low, prevents any program or erase command from altering the data in the protected memory area.

Supply Voltage

Ground

4.

Logic Symbol

V

CC

SO

SI

SCK

CS#

W#

HOLD#

GND

February 27, 2009 S25FL064A_00_C4 S25FL064A 9

D a t a S h e e t

5.

Ordering Information

This product has been retired and is not recommended for designs. For new and current designs,

S25FL064P supercedes S25FL064A. This is the factory-recommended migration path. Please refer to the

S25FL064P data sheet for specifications and ordering information.

The ordering part number is formed by a valid combination of the following:

S25FL 064 A 0L M A I 00 1

PACKING TYPE

(Note 1)

1 = Tube

3 = 13” Tape and Reel

MODEL NUMBER (Additional Ordering Options)

00 = No additional ordering options

TEMPERATURE RANGE

I = Industrial (–40°C to + 85°C)

PACKAGE MATERIALS

A = Standard

F = Lead

PACKAGE TYPE

M = 16-pin SO package

SPEED

0L = 50 MHz

DEVICE TECHNOLOGY

A = 0.20 µm MirrorBit

®

Process Technology

DENSITY

064 = 64 Mbit

DEVICE FAMILY

S25FL

Spansion

TM

Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory

Table 5.1 S25FL064A Valid Combinations Table

Base Ordering

Part Number

S25FL064A

S25FL064A Valid Combinations

Speed Option

Package &

Temperature

0L

MAI, MFI,

NAI, NFI

Model

Number

00

Notes

1. Contact your local sales office for availability.

2. Package marking omits leading “S25” and speed, package, and model number form.

3. A for standard package (non-Pb free); F for Pb-free package.

Packing Type

0, 1, 3

(Note 1)

Package Marking

(Note 2)

FL064A + (Temp) +

(Note 3)

5.1

Valid Combinations

Table 5.1

lists the valid combinations configurations planned to be supported in volume for this device.

10 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

6.

Spansion SPI Modes

A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices:

„ CPOL = 0, CPHA = 0 (Mode 0)

„ CPOL = 1, CPHA = 1 (Mode 3)

Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes.

When the bus master is in standby mode, SCK is as shown in

Figure 6.2

for each of the two modes:

„ SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)

„ SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3)

Figure 6.1 Bus Master and Memory Devices on the SPI Bus

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

Bus Master

SO

SI

SCK

SCK SO SI SCK SO SI SCK SO SI

SPI Memory

Device

SPI Memory

Device

SPI Memory

Device

CS3 CS2 CS1

CS# W# HOLD# CS# W# HOLD# CS# W# HOLD#

Note

The Write Protect (W#) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate.

Figure 6.2 SPI Modes Supported

CS#

Mode 0

CPOL CPHA

0 0 SCK

Mode 3 1 1

SCK

SI

SO

MSB

MSB

February 27, 2009 S25FL064A_00_C4 S25FL064A 11

D a t a S h e e t

7.

Device Operations

All Spansion SPI devices (S25FL-A) accept and output data in bytes (8 bits at a time).

7.1

Byte or Page Programming

Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program

(PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation.

Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation. Before this can be applied, the bytes of the memory need to be first erased to all

1’s (FFh) before any programming.

7.2

Sector Erase / Bulk Erase

The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1. While bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level.

7.3

Monitoring Write Operations Using the Status Register

The host system can determine when a Write Status Register, program, or erase operation is complete by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit.

7.4

Active Power and Standby Power Modes

The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device is disabled, but may still be in the Active Power mode until all program, erase, and Write Status

Register operations have completed. The device then goes into the Standby Power mode, and power consumption drops to I

SB

. The Deep Power Down (DP) command provides additional data protection against inadvertent signals. After writing the DP command, the device ignores any further program or erase commands, and reduces its power consumption to I

DP

.

7.5

Status Register

The Status Register contains the status and control bits that can be read or set by specific commands

(

Table 9.2, S25FL064A Status Register on page 20

):

„ Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or erase operation.

„ Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.

„ Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected against program and erase commands.

„ Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit is set to 1 and the W# input is driven low. In this mode, the non-volatile bits of the Status Register (SRWD,

BP2, BP1, BP0) become read-only bits.

12 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

7.6

Data Protection Modes

Spansion SPI Flash memory devices provide the following data protection methods:

„ The Write Enable (WREN) command: Must be written prior to any command that modifies data. The

WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up or after the device completes the following commands:

– Page Program (PP)

– Sector Erase (SE)

– Bulk Erase (BE)

– Write Disable (WRDI)

– Write Status Register (WRSR)

„ Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be read but not programmed or erased.

Table 7.1

shows the sizes and address ranges of protected areas that are defined by Status Register bits BP2:BP0.

„ Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable

(SRWD) bit together provide write protection.

„ Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands consist of a clock pulse count that is a multiple of eight before executing them.

Table 7.1 S25FL064A Protected Area Sizes

Status Register

Block Protect Bits

0

1

1

1

1

BP2 BP1

0

0

0

0

0

1

1

0

0

1

1

1

0

1

0

1

BP0

0

1

0

Protected

Address Range

None

7E0000h–7FFFFFh

7C0000h–7FFFFFh

780000h–7FFFFFh

700000h–7FFFFFh

600000h–7FFFFFh

400000h–7FFFFFh

000000h–7FFFFFh

Memory Array

Protected Sectors

Unprotected

Address Range

(0)

(2) SA127:SA126

(4) SA127:SA124

000000h–7FFFFFh

000000h–7DFFFFh

000000h–7BFFFFh

(8) SA127:SA120

(16) SA127:SA112

(32) SA127:SA96

(64) SA127:SA64

(128) SA127:SA0

000000h–77FFFFh

000000h–6FFFFFh

000000h–5FFFFFh

000000h–3FFFFFh

None

Unprotected

Sectors

SA127:SA0

SA125:SA0

SA123:SA0

SA119:SA0

SA111:SA0

SA95:SA0

SA63:SA0

None

Protected

Portion of

Total Memory

Area

0

1/64

1/32

1/16

1/8

1/4

1/2

All

February 27, 2009 S25FL064A_00_C4 S25FL064A 13

D a t a S h e e t

7.7

Hold Mode (HOLD#)

The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write

Status Register, program or erase operation that is currently in progress.

The Hold mode starts on the falling edge of HOLD# if SCK is also low (see

Figure 7.1

, standard use). If the

falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of

SCK (non-standard use).

The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (nonstandard use) See

Figure 7.1

.

The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the

Hold mode.

CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high, followed by driving CS# low.

Figure 7.1 Hold Mode Operation

SCK

HOLD#

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

8.

Sector Address Table

Table 8.1

shows the size of the memory array, sectors, and pages. The device uses pages to cache the program data before the data is programmed into the memory array. Each page or byte can be individually programmed (bits are changed from 1 to 0). The data is erased (bits are changed from 0 to 1) on a sector- or

device-wide basis using the SE or BE commands.

Table 8.2 on page 15

shows the starting and ending

address for each sector. The complete set of sectors comprises the memory array of the Flash device.

Each Device has

8,388,608

32,768

128

Table 8.1 S25FL064A Device Organization

Each Sector has

65,536

256

Each Page has

256

— bytes pages sectors

14 S25FL064A S25FL064A_00_C4 February 27, 2009

SA100

SA99

SA98

SA97

SA96

SA95

SA94

SA106

SA105

SA104

SA103

SA102

SA101

SA93

SA92

SA91

SA90

SA89

SA88

SA87

SA86

SA85

SA112

SA111

SA110

SA109

SA108

SA107

SA118

SA117

SA116

SA115

SA114

SA113

Sector

SA127

SA126

SA125

SA124

SA123

SA122

SA121

SA120

SA119

D a t a S h e e t

6A0000h

690000h

680000h

670000h

660000h

650000h

640000h

630000h

620000h

610000h

600000h

5F0000h

5E0000h

5D0000h

5C0000h

5B0000h

5A0000h

590000h

580000h

570000h

560000h

550000h

760000h

750000h

740000h

730000h

720000h

710000h

700000h

6F0000h

6E0000h

6D0000h

6C0000h

6B0000h

Address Range

7F0000h

7E0000h

7D0000h

7FFFFFh

7EFFFFh

7DFFFFh

7C0000h

7B0000h

7A0000h

790000h

780000h

770000h

7CFFFFh

7BFFFFh

7AFFFFh

79FFFFh

78FFFFh

77FFFFh

76FFFFh

75FFFFh

74FFFFh

73FFFFh

72FFFFh

71FFFFh

70FFFFh

6FFFFFh

6EFFFFh

6DFFFFh

6CFFFFh

6BFFFFh

6AFFFFh

69FFFFh

68FFFFh

67FFFFh

66FFFFh

65FFFFh

64FFFFh

63FFFFh

62FFFFh

61FFFFh

60FFFFh

5FFFFFh

5EFFFFh

5DFFFFh

5CFFFFh

5BFFFFh

5AFFFFh

59FFFFh

58FFFFh

57FFFFh

56FFFFh

55FFFFh

Table 8.2 S25FL064A Sector Address Table

SA57

SA56

SA55

SA54

SA53

SA52

SA51

SA63

SA62

SA61

SA60

SA59

SA58

SA50

SA49

SA48

SA47

SA46

SA45

SA44

SA43

SA42

SA69

SA68

SA67

SA66

SA65

SA64

SA75

SA74

SA73

SA72

SA71

SA70

Sector

SA84

SA83

SA82

SA81

SA80

SA79

SA78

SA77

SA76

3F0000h

3E0000h

3D0000h

3C0000h

3B0000h

3A0000h

390000h

380000h

370000h

360000h

350000h

340000h

330000h

320000h

310000h

300000h

2F0000h

2E0000h

2D0000h

2C0000h

2B0000h

2A0000h

4B0000h

4A0000h

490000h

480000h

470000h

460000h

450000h

440000h

430000h

420000h

410000h

400000h

Address Range

540000h

530000h

520000h

54FFFFh

53FFFFh

52FFFFh

510000h

500000h

4F0000h

4E0000h

4D0000h

4C0000h

51FFFFh

50FFFFh

4FFFFFh

4EFFFFh

4DFFFFh

4CFFFFh

4BFFFFh

4AFFFFh

49FFFFh

48FFFFh

47FFFFh

46FFFFh

45FFFFh

44FFFFh

43FFFFh

42FFFFh

41FFFFh

40FFFFh

3FFFFFh

3EFFFFh

3DFFFFh

3CFFFFh

3BFFFFh

3AFFFFh

39FFFFh

38FFFFh

37FFFFh

36FFFFh

35FFFFh

34FFFFh

33FFFFh

32FFFFh

31FFFFh

30FFFFh

2FFFFFh

2EFFFFh

2DFFFFh

2CFFFFh

2BFFFFh

2AFFFFh

SA14

SA13

SA12

SA11

SA10

SA9

SA8

SA20

SA19

SA18

SA17

SA16

SA15

SA3

SA2

SA1

SA0

SA7

SA6

SA5

SA4

SA26

SA25

SA24

SA23

SA22

SA21

SA32

SA31

SA30

SA29

SA28

SA27

Sector

SA41

SA40

SA39

SA38

SA37

SA36

SA35

SA34

SA33

140000h

130000h

120000h

110000h

100000h

0F0000h

0E0000h

0D0000h

0C0000h

0B0000h

0A0000h

090000h

080000h

070000h

060000h

050000h

040000h

030000h

020000h

010000h

000000h

200000h

1F0000h

1E0000h

1D0000h

1C0000h

1B0000h

1A0000h

190000h

180000h

170000h

160000h

150000h

Address Range

290000h

280000h

270000h

29FFFFh

28FFFFh

27FFFFh

260000h

250000h

240000h

230000h

220000h

210000h

26FFFFh

25FFFFh

24FFFFh

23FFFFh

22FFFFh

21FFFFh

20FFFFh

1FFFFFh

1EFFFFh

1DFFFFh

1CFFFFh

1BFFFFh

1AFFFFh

19FFFFh

18FFFFh

17FFFFh

16FFFFh

15FFFFh

14FFFFh

13FFFFh

12FFFFh

11FFFFh

10FFFFh

0FFFFFh

0EFFFFh

0DFFFFh

0CFFFFh

0BFFFFh

0AFFFFh

09FFFFh

08FFFFh

07FFFFh

06FFFFh

05FFFFh

04FFFFh

03FFFFh

02FFFFh

01FFFFh

00FFFFh

February 27, 2009 S25FL064A_00_C4 S25FL064A 15

D a t a S h e e t

9.

Command Definitions

The host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on

the rising edge of SCK.

Table 9.4 on page 28

lists the complete set of commands.

Every command sequence begins with a one-byte command code. The command may be followed by address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the command sequence has been written.

The Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at Higher Speed

(FAST_READ) and Read Identification (RDID) command sequences are followed by a data output sequence on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation.

The Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable

(WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high when the number of clock pulses after CS# is driven low is an exact multiple of eight.

The device ignores any attempt to access the memory array during a Write Status Register, program, or erase operation, and continues the operation uninterrupted.

9.1

Read Data Bytes (READ)

The Read Data Bytes (READ) command reads data from the memory array at the frequency (f

SCK

) presented at the SCK input, with a maximum speed of 33 MHz. The host system must first select the device by driving

CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0). Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency f

SCK

, on the falling edge of SCK.

Figure 9.1

and

Table 9.4 on page 28

detail the READ command sequence. The first byte specified can be at any location. The device automatically increments to the next higher address after each byte of data is output.

The entire memory array can therefore be read with a single READ command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.

The READ command is terminated by driving CS# high at any time during data output. The device rejects any

READ command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted.

Figure 9.1 Read Data Bytes (READ) Command Sequence

CS#

Mode 3

SCK

Mode 0

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Command 24-Bit Address

SI

SO

Hi-Z

23 22 21

MSB

3 2 1 0

Data Out 1

7 6 5

MSB

4

3

2

1 0 7

Data Out 2

16 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

9.2

Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ command reads data from the memory array at the frequency (f

SCK

) presented at the SCK input, with a maximum speed of 50 MHz. The host system must first select the device by driving CS# low. The

FAST_READ command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency f

SCK

, on the falling edge of SCK.

The FAST_READ command sequence is shown in

Figure 9.2

and

Table 9.4 on page 28

. The first byte

specified can be at any location. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single FAST_READ command.

When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.

The FAST_READ command is terminated by driving CS# high at any time during data output. The device rejects any FAST_READ command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted.

Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence

CS#

SCK

Mode 3

Mode 0

SI

SO

Hi-Z

0 1 2

3 4

5 6

7

8

9 10 28 29 30 31 32 33 34 35 36 37 38

39

40 41 42 43 44

45

46 47

Command

24-Bit Address

23 22 21

Dummy Byte

3 2

1 0

7

6 5 4

3

2 1 0

7 6

MSB

5 4

3

DATA OUT 1

2 1 0 7

MSB

DATA OUT 2

February 27, 2009 S25FL064A_00_C4 S25FL064A 17

D a t a S h e e t

9.3

Read Identification (RDID)

The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device identification, to the host system.

JEDEC assigns the manufacturer identification byte; for Spansion devices it is 01h. The device manufacturer assigns the device identification: the first byte provides the memory type; the second byte indicates the

memory capacity. See

Table 9.1 on page 18

or

Table 9.4 on page 28

for device ID data.

The host system must first select the device by driving CS# low. The RDID command is then written to SI, and each bit is latched on the rising edge of SCK. The 24-bit device identification data is output from the memory array on SO at a frequency f

SCK

, on the falling edge of SCK.

The RDID command sequence is shown in

Figure 9.3

and

Table 9.4 on page 28

.

Driving CS# high after the device identification data has been read at least once terminates the READ_ID command. Driving CS# high at any time during data output also terminates the RDID operation.

The device rejects any RDID command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted.

Figure 9.3 Read Identification (RDID) Command Sequence and Data-Out Sequence

CS#

SCK

Mode 3

Mode 0

0

1 2 3 4 5 6

7 8 9 10 11 12 13 14 15 16 17 18

28 29 30 31

Command

SI

Manufacturer Identification

SO

Hi-Z

Device Identification

15

14

13

3 2

1 0

MSB

Table 9.1 Read Identification (RDID) Data-Out Sequence

Manufacturer Identification

01h

Memory Type

02h

Device Identification

Memory Capacity

16h

18 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

9.4

Write Enable (WREN)

The Write Enable (WREN) command (see

Figure 9.4

) sets the Write Enable Latch (WEL) bit to a 1, which enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command.

The host system must first drive CS# low, write the WREN command, and then drive CS# high.

Figure 9.4 Write Enable (WREN) Command Sequence

CS#

SCK

Mode 3

Mode 0

0 1 2 3 4 5 6

7

Command

SI

Hi-Z

SO

9.5

Write Disable (WRDI)

The Write Disable (WRDI) command (see

Figure 9.5

) resets the Write Enable Latch (WEL) bit to a 0, which disables the device from accepting a Write Status Register, program, or erase command. The host system must first drive CS# low, write the WRDI command, and then drive CS# high.

Any of following conditions resets the WEL bit:

„ Power-up

„ Write Disable (WRDI) command completion

„ Write Status Register (WRSR) command completion

„ Page Program (PP) command completion

„ Sector Erase (SE) command completion

„ Bulk Erase (BE) command completion

Figure 9.5 Write Disable (WRDI) Command Sequence

CS#

Mode 3

SCK

Mode 0

0

1 2 3 4 5 6 7

Command

SI

SO

Hi-Z

February 27, 2009 S25FL064A_00_C4 S25FL064A 19

D a t a S h e e t

9.6

Read Status Register (RDSR)

The Read Status Register (RDSR) command outputs the state of the Status Register bits.

Table 9.2

shows the status register bits and their functions.

The RDSR command may be written at any time, even while a program, erase, or Write Status Register operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new command to the device if an operation is already in progress.

Figure 9.6

shows the RDSR command

sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven high.

Bit

7

6

5

4

3

2

Status Register Bit

SRWD

BP2

BP1

BP0

Table 9.2 S25FL064A Status Register

Bit Function

Status Register Write Disable

Description

1 = Protects when W# is low

0 = No protection, even when W# is low

Not used

Not used

Block Protect

000–111 = Protects upper half of address range in 5 sizes. See

Table 7.1 on page 13

.

1

0

WEL

WIP

Write Enable Latch

Write in Progress

1 = Device accepts Write Status Register, program, or erase commands

0 = Ignores Write Status Register, program, or erase commands

1 = Device Busy. A Write Status Register, program, or erase operation is in progress

0 = Ready. Device is in standby mode and can accept commands.

Figure 9.6 Read Status Register (RDSR) Command Sequence

CS#

Mode 3

SCK

Mode 0

0

1

2 3 4 5 6

7

8 9 10 11

12 13 14

15

Command

SI

SO

Hi-Z

7 6 5 4 3

2

1 0 7

6

5 4

3 2

1 0 7

MSB MSB

Status Register Out Status Register Out

20 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

The following describes the status and control bits of the Status Register.

Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Status Register, program, or erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of these operations is in progress; if WIP is 0, no such operation is in progress.

Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Status

Register, program, or erase command. When set to 1, the device accepts these commands; when set to 0, the device rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the

WRDI command, and is also automatically reset to 0 after the completion of a Write Status Register, program, or erase operation. WEL cannot be directly set by the WRSR command.

Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against any changes to the stored data. The Write Status Register (WRSR) command controls these bits, which are

non-volatile. When one or more of these bits is set to 1, the corresponding memory area (see

Table 7.1 on page 13

) is protected against Page Program (PP) and Sector Erase (SE) commands. If the Hardware

Protected mode is enabled, BP2:BP0 cannot be changed. The Bulk Erase (BE) command is executed only if all Block Protect (BP2, BP1, BP0) bits are 0.

Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write

Protect (W#) signal. When SRWD is set to 1 and W# is driven low, the device enters the Hardware Protected mode. The non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the device ignores any Write Status Register (WRSR) command.

9.7

Write Status Register (WRSR)

The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable

(WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to writing the WRSR command.

Table 9.2, S25FL064A Status Register on page 20

shows the status register

bits and their functions.

The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI

(

Figure 9.7

).

The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always read as 0 and have no user significance.

The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit and W# together place the device in the Hardware Protected Mode (HPM). The device ignores all WRSR

commands once it enters the Hardware Protected Mode (HPM).

Table 9.3 on page 22

shows that W# must

be driven low and the SRWD bit must be 1 for this to occur.

Figure 9.7 Write Status Register (WRSR) Command Sequence

CS#

Mode 3

SCK

Mode 0

0 1 2 3 4 5 6 7

8 9 10 11 12 13 14 15

Command

Status Register In

SI

SO

Hi-Z

7 6 5 4 3 2 1 0

MSB

February 27, 2009 S25FL064A_00_C4 S25FL064A 21

D a t a S h e e t

Table 9.3 Protection Modes

W#

Signal

1

1

0

0

SRWD

Bit

1

0

0

1

Mode

Software

Protected

(SPM)

Hardware

Protected

(HPM)

Write Protection of the Status Register

Status Register is writable (if the WREN command has set the WEL bit). The values in the SRWD, BP2, BP1 and BP0 bits can be changed.

Status Register is Hardware write protected.

The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed.

Protected Area

(See Note)

Protected against program and erase commands

Unprotected Area

(See Note)

Ready to accept Page

Program and Sector Erase commands

Protected against program and erase commands

Ready to accept Page

Program and Sector Erase commands

Note

As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.1 on page 13

.

Table 9.3

shows that neither W# or SRWD bit by themselves can enable HPM. The device can enter HPM either by setting the SRWD bit after driving W# low, or by driving W# low after setting the SRWD bit.

However, the device disables HPM only when W# is driven high.

Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in

HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM).

If W# is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status

Register) can be used.

22 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

9.8

Page Program (PP)

The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN command is required prior to writing the PP command.

The host system must drive CS# low, and then write the PP command, three address bytes, and at least one data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence

is shown in

Figure 9.8

and

Table 9.4 on page 28

.

The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256 bytes sent at the starting address of the specified page. This may result in data being programmed into different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses.

The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of t

PP

. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the

Write Enable Latch to 0 before the operation completes (the exact timing is not specified).

The device does not execute a Page Program (PP) command that specifies a page that is protected by the

Block Protect bits (BP2:BP0) (see

Table 7.1 on page 13

).

Figure 9.8 Page Program (PP) Command Sequence

CS#

Mode 3

SCK Mode 0

0 1

2

3

4 5 6 7 8

9 10

28

29 30 31

32 33 34

35 36 37 38

39

SI

Command

24-Bit Address Data Byte 1

3 2 1 0 7 6 5 4 3 2 1 0

23 22 21

MSB MSB

CS#

SCK

40

41 42 43

44 45 46

47 48 49 50

51 52 53 54

55

SI

Data Byte 2 Data Byte 3

7 6 5 4 3 2 1

0 7 6

5 4 3 2 1

0

MSB MSB

Data Byte 256

7 6 5 4 3 2 1 0

MSB

February 27, 2009 S25FL064A_00_C4 S25FL064A 23

D a t a S h e e t

9.9

Sector Erase (SE)

The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN command is required prior to writing the PP command.

The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any address within the sector (see

Table 7.1 on page 13

) is a valid address for the SE command. CS# must be

driven low for the entire duration of the SE sequence. The command sequence is shown in

Figure 9.9

and

Table 9.4 on page 28

.

The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise the device does not execute the command. The SE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of t

SE

. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the

Write Enable Latch to 0 before the operation completes (the exact timing is not specified).

The device does not execute an SE command that specifies a sector that is protected by the Block Protect

bits (BP2:BP0) (see

Table 7.1 on page 13

).

Figure 9.9 Sector Erase (SE) Command Sequence

CS#

Mode 3

SCK

Mode 0

0 1

2 3 4 5 6 7 8 9 10 28 29 30 31

SI

Command 24-bit Address

23 22 21

MSB

3 2 1 0

SO

Hi-Z

24 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

9.10

Bulk Erase (BE)

The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command is required prior to writing the PP command.

The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the entire duration of the BE sequence. The command sequence is shown in

Figure 9.10

and

Table 9.4 on page 28

.

The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise the device does not execute the command. The BE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of t

BE

. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the

Write Enable Latch to 0 before the operation completes (the exact timing is not specified).

The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see

Table 7.1 on page 13

). Otherwise, the device ignores the command.

Figure 9.10 Bulk Erase (BE) Command Sequence

CS#

Mode 3

SCK

Mode 0

0 1 2 3 4 5 6 7

Command

SI

SO

Hi-Z

February 27, 2009 S25FL064A_00_C4 S25FL064A 25

D a t a S h e e t

9.11

Deep Power Down (DP)

The Deep Power Down (DP) command provides the lowest power consumption mode of the device. It is intended for periods when the device is not in active use, and ignores all commands except for the Release from Deep Power Down (RES) command. The DP mode therefore provides the maximum data protection

against unintended write operations. The standard standby mode, which the device goes into automatically when CS# is high (and all operations in progress are complete), should generally be used for the lowest power consumption when the quickest return to device activity is required.

The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the

entire duration of the DP sequence. The command sequence is shown in

Figure 9.11

and

Table 9.4 on page 28

.

The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise the device does not execute the command. After a delay of t

DP, the device enters the DP mode and current reduces from I

SB

to I

DP

(see

Table 14.1 on page 31

).

Once the device has entered the DP mode, all commands are ignored except the RES command (which releases the device from the DP mode). The RES command also provides the Electronic Signature of the device to be output on SO, if desired (see

Section 9.12

and

9.12.1)

.

DP mode automatically terminates when power is removed, and the device always powers up in the standard standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write

Status Register operation, and continues the operation uninterrupted.

Figure 9.11 Deep Power Down (DP) Command Sequence

CS# tDP

0 1

2 3 4 5 6 7

Mode 3

SCK

Mode 0

Command

SI

SO

Hi-Z

Standby Mode Deep Power-down Mode

26 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

9.12

Release from Deep Power Down (RES)

The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down mode. When the device is in the Deep Power Down mode, all commands except RES are ignored.

The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire

duration of the sequence. The command sequence is shown in

Figure 9.12

and

Table 9.4 on page 28

.

The host system must drive CS# high t

RES(max) after the 8-bit RES command byte. The device transitions from DP mode to the standby mode after a delay of t

RES

(see

Table 16.1 on page 32

). In the standby mode,

the device can execute any read or write command.

Figure 9.12 Release from Deep Power Down (RES) Command Sequence

CS#

Mode 3

SCK

Mode 0

0 1 2 3 4 5 6

7

Command t

RES

SI

SO

Hi-Z

Deep Power-down Mode

Standby Mode

February 27, 2009 S25FL064A_00_C4 S25FL064A 27

28

D a t a S h e e t

9.12.1

Release from Deep Power Down and Read Electronic Signature (RES)

The device features an 8-bit Electronic Signature, which can be read using the RES command. See

Figure 9.13

and

Table 9.4 on page 28

for the command sequence and signature value. The Electronic

Signature is not to be confused with the identification data obtained using the RDID command. The device offers the Electronic Signature so that it can be used with previous devices that offered it; however, the

Electronic Signature should not be used for new designs, which should read the RDID data instead.

After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the

Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to output the Electronic Signature repeatedly.

When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of t

RES

, as previously described. The RES command always provides access to the Electronic Signature of the device and can be applied even if DP mode has not been entered.

Any RES command issued while an erase, program, or WRSR operation is in progress not executed, and the operation continues uninterrupted.

Figure 9.13 Release from Deep Power Down and Read Electronic Signature (RES)

Command Sequence

CS#

SCK

SI

SO

Hi-Z

0

1 2

3 4 5 6 7

8 9

10

28 29 30 31 32 33 34 35 36 37 38

Command

23 22 21

MSB

3 Dummy Bytes

3

2

1 0

7 6 5 4

3 2 1

0

MSB

Electronic ID out t

RES

Deep Power-down Mode

Standby Mode

Table 9.4 Command Definitions

Operation

Read

Write Control

Erase

Program

Status Register

Power Saving

Command

READ

Description

Read Data Bytes

FAST_READ Read Data Bytes at Higher Speed

RDID

Read Identification (Note 1)

WREN

WRDI

SE

BE

Write Enable

Write Disable

Sector Erase

Bulk (Chip) Erase

PP

RDSR

WRSR

DP

RES

Page Program

Read from Status Register

Write to Status Register

Deep Power Down

Release from Deep Power Down

Release from Deep Power Down and

Read Electronic Signature (Note 2)

One-Byte

Command Code

03H (0000 0011)

0BH (0000 1011)

9FH (1001 1111)

06H (0000 0110)

04H (0000 0100)

D8H (1101 1000)

C7H (1100 0111)

02H (0000 0010)

05H (0000 0101)

01H (0000 0001)

B9H (1011 1001)

ABH (1010 1011)

ABH (1010 1011)

Address

Bytes

3

3

0

0

0

3

0

3

0

0

0

0

0

Dummy

Byte

0

1

0

0

0

0

0

0

0

0

0

0

3

Data Bytes

1 to

1 to

1 to 3

0

0

0

0

1 to 256

1 to

1

0

0

1 to

Notes

1.

The S25FL064A has a manufacturer ID of 01h, and a device ID consisting of the memory type (02h) and the memory capacity (16h).

2. The S25FL064A has an Electronic Signature ID of 16h.

S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

10. Power-up and Power-down

During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied on V

CC

, and must not be driven low to select the device until V

CC

reaches the allowable values as follows

(see

Figure 10.1

and

Table 10.1

):

„ At power-up, V

CC

(min) plus a period of t

PU

„ At power-down, V

SS

A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.

No Write Status Register, program, or erase command should be sent to the device until V

CC

rises to the V

CC min, plus a delay of t

PU

. At power-up, the device is in standby mode (not Deep Power Down mode) and the

WEL bit is reset (0).

Each device in the host system should have the V

CC

rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the V

CC

feed.

When V

CC

drops from the operating voltage to below the minimum V

CC

threshold at power-down, all operations are disabled and the device does not respond to any commands. Note that data corruption may result if a power-down occurs while a Write Register, program, or erase operation is in progress.

Figure 10.1 Power-Up Timing Diagram

V cc

V cc

(max)

V cc

(min) t

PU

Full Device Access

Time

Symbol

V

CC(min) t

PU

Table 10.1 Power-Up Timing Characteristics

Parameter

V

CC

(minimum)

V

CC

(min) to device operation

Min

2.7

10

Max Unit

V ms

11. Initial Delivery State

The device is delivered with all bits set to 1 (each byte contains FFh) upon initial factory shipment. The Status

Register contains 00h (all Status Register bits are 0).

February 27, 2009 S25FL064A_00_C4 S25FL064A 29

D a t a S h e e t

12. Absolute Maximum Ratings

Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device may result. These are stress ratings only and device operation at these or any other conditions beyond those

indicated in this section and in the

Operating Ranges

section of this document is not implied. Device operation for extended periods at the limits listed in this section may affect device reliability.

Table 12.1 Absolute Maximum Ratings

Description

Ambient Storage Temperature

Voltage with Respect to Ground: All Inputs and I/Os

Rating

–65°C to +150°C

–0.5 V to V

CC

+0.5 V

Notes

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot V

SS

to –2.0 V for periods of

up to 20 ns. See Figure 12.2

. Maximum DC voltage on output and I/O pins is 3.6 V. During voltage transitions output pins may overshoot to V

CC

+ 2.0 V for periods up to 20 ns. See

Figure 12.2

.

2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 12.1 Maximum Negative Overshoot Waveform

20 ns 20 ns

+0.8 V

–0.5 V

–2 V

20 ns

Figure 12.2 Maximum Positive Overshoot Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V

20 ns 20 ns

13. Operating Ranges

Table 13.1 Operating Ranges

Description

Ambient Operating Temperature (T

A

)

Commerical

Industrial

Voltage Range Positive Power Supply

Note

Operating ranges define those limits between which functionality of the device is guaranteed.

Rating

0°C to +70°C

–40°C to +85°C

2.7 V to 3.6 V

30 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

14. DC Characteristics

This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in

Table 15.1 on page 31

, when relying on the quoted parameters.

Parameter

V

CC

Description

Supply Voltage

Table 14.1 DC Characteristics (CMOS Compatible)

Test Conditions

(See Note)

Min

2.7

SCK = 0.1 V

CC

/0.9V

CC

33 MHz

I

CC1

Active Read Current

I

CC2

I

CC3

I

CC4

I

CC5

I

SB

I

DP

Active Page Program Current

Active WRSR Current

Active Sector Erase Current

Active Bulk Erase Current

Standby Current

Deep Power Down Current

I

LI

I

LO

V

IL

V

IH

V

OL

V

OH

Input Leakage Current

Output Leakage Current

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Note

Typical values are at T

A

= 25

°

C and 3.0 V.

Typ.

3

8

Max

3.6

10

SCK = 0.1 V

CC

/0.9V

CC

V

CC

= 3.0V

50 MHz

10 13

CS# = V

CC

CS# = V

CC

CS# = V

CC

CS# = V

CC

V

CC

= 3.0 V

CS# = V

CC

V

CC

= 3.0 V

CS# = V

CC

19.5

1

28

28

26

26

50

10

V

IN

= GND to V

CC

V

IN

= GND to V

CC

1

1

–0.3

V

0.3 V

CC

CC

+ 0.5

I

OL

= 1.6 mA, V

CC

= V

CC min

0.4

I

OH

= –0.1 mA

0.7 V

CC

V

CC

– 0.2

Unit

V mA mA mA mA mA mA

µA

µA

V

V

V

µA

µA

V

15. Test Conditions

Figure 15.1 AC Measurements I/O Waveform

0.8 V

CC

Input Levels

0.2 V

CC

0.7 V

CC

0.5 V

CC

0.3 V

CC

Input and Output

Timing Reference levels

Symbol

C

L

Table 15.1 Test Specifications

Parameter

Load Capacitance

Input Rise and Fall Times

Input Pulse Voltage

Input Timing Reference Voltage

Output Timing Reference Voltage

Min Max

30

0.2 V

CC

to 0.8 V

CC

0.3 V

CC

to 0.7 V

CC

0.5 V

CC

5

V

V

V

Unit

pF ns

February 27, 2009 S25FL064A_00_C4 S25FL064A 31

D a t a S h e e t

16. AC Characteristics

Table 16.1 AC Characteristics

Symbol

(Notes) Parameter Min

Typ

(Notes)

Max

(Notes)

F

F

SCK

SCK

SCK Clock Frequency READ command

SCK Clock Frequency for:

FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR

Clock Rise Time (Slew Rate)

D.C.

D.C.

25

50 t

W t

DP t

RES t

PP t

SE t

BE t

F t

LZ

(3)

t

HZ

(3)

t

DIS

(3)

t

WPS

(3)

t

WPH

(3)

t

CRT t

CFT t

WH t

WL t

CS t

CSS

(3)

t

CSH

(3)

t

HD

(3)

t

CD

(3)

t

HC t

CH t

V t

HO t

HD:DAT t

SU:DAT t

R

Clock Fall Time (Slew Rate)

SCK High Time

SCK Low Time

CS# High Time

CS# Setup Time

CS# HOLD Time

HOLD# Setup Time (relative to SCK)

HOLD# Hold Time (relative to SCK)

HOLD# Setup Time (relative to SCK)

HOLD# Hold Time (relative to SCK)

Output Valid

Output Hold Time

Data in Hold Time

Data in Setup Time

Input Rise Time

Input Fall Time

HOLD# to Output Low Z

HOLD# to Output High Z

Output Disable Time

Write Protect Setup Time

Write Protect Hold Time

Write Status Register Time

CS# High to Deep Power Down Mode

Release DP Mode

Page Programming Time

Sector Erase Time

Bulk Erase Time

0.1

0.1

9

9

100

5

5

5

5

5

5

0

0

5

5

15

15

67

1.5

0.5

192

(1)

(1)

(1)

9

5

10

10

10

150

30

3

3

5

3

(2)

(2)

384 (2)

Notes

1. Typical program and erase times assume the following conditions: 25°C, V

CC

= 3.0 V; 10,000 cycles; checkerboard data pattern

2. Under worst-case conditions of 90°C; V

CC

= 2.7V; 100,000 cycles

3. Not 100% tested

Unit

MHz

MHz

V/ns

V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms

µs

µs ms sec sec

32 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

Figure 16.1 SPI Mode 0 (0,0) Input Timing t

CS

CS#

SCK t

CSH t

CSS

SI t

SU:DAT t

HD:DAT

MSB IN

SO

Hi-Z t

CRT t

CFT t

CSH

LSB IN

Figure 16.2 SPI Mode 0 (0,0) Output Timing t

CSS

CS# t

WH

SCK t

HO t

V

SO t

HO t

V t

WL

LSB OUT t

DIS

Figure 16.3 HOLD# Timing

CS#

SCK t

CH t

HD t

HZ t

CD t

HC t

LZ

SO

SI

HOLD#

February 27, 2009 S25FL064A_00_C4 S25FL064A 33

D a t a S h e e t

W#

Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 t

WPS t

WPH

CS#

SCK

SI

SO

Hi-Z

34 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

17. Physical Dimensions

17.1

SO3 016 wide—16-pin Plastic Small Outline Package (300-mil Body Width)

PACKAGE SO3 016 (inches)

JEDEC MS-013(D)AA

SYMBOL

A

MIN

0.093

MAX

0.104

SO3 016 (mm)

MS-013(D)AA

MIN

2.35

MAX

2.65

A1

A2 b b1

0.004

0.081

0.012

0.011

0.012

0.104

0.020

0.019

0.10

2.05

0.31

0.27

c c1

0.008

0.008

0.013

0.012

0.20

0.20

0.33

0.30

D 0.406 BSC 10.30 BSC

E 0.406 BSC 10.30 BSC

E1 0.295 BSC 7.50 BSC e .050 BSC 1.27 BSC

0.30

2.55

0.51

0.48

L 0.016

0.050

0.40

L1 .055 REF 1.40 REF

1.27

L2 .010 BSC 0.25 BSC

N 16 16 h

θ

θ1

θ2

0.10

0.30

15˚

0.25

0˚ 0˚

0.75

15˚

February 27, 2009 S25FL064A_00_C4

NOTES:

1.

ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.

2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.

3.

.

DIMENSION D DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm

PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1

DIMENSIONS ARE DETERMINED AT DATUM H.

4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE

BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE

OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF

MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD

FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP

AND BOTTOM OF THE PLASTIC BODY.

5. DATUMS A AND B TO BE DETERMINED AT DATUM H.

6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR

THE SPECIFIED PACKAGE LENGTH.

7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD

BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.

8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL

IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL

CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE

LOWER RADIUS OF THE LEAD FOOT.

9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,

THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX

AREA INDICATED.

10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED

FROM THE SEATING PLANE.

3601 \ 16-038.03 \ 8.31.6

S25FL064A 35

D a t a S h e e t

18. Revision History

Section

Revision A (April 26, 2005)

Global

Revision B0 (April 18, 2006)

Global

AC Characteristics table

Revision B1 (June 29, 2006)

DC Characteristics

Revision C0 (September 6, 2006)

Global

Revision C1 (January 31, 2007)

AC Characteristics

Revision C2 (March 14, 2007)

Global

Absolute Maximum Ratings

Revision C3 (June 29, 2007)

Device Operations

Revision C4 (February 27, 2009)

Global

Initial release.

Description

Changed document status from Advance Information to Preliminary. Changed title from family of devices to specific device.

Updated t

W

specifications.

Changed typical and maximum specifications for I

CC2

.

Rewrote entire document for better flow and clarity. No specifications were changed.

Changed typical specification for t

SE

.

Changed document status from Preliminary to Full Production.

Added undershoot and overshoot information.

Added a sentence to Byte or Page Programming

Added obsolescence information to Cover Sheet, Distinctive Characteristics, and Ordering

Information sections of data sheet.

36 S25FL064A S25FL064A_00_C4 February 27, 2009

D a t a S h e e t

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document.

Copyright © 2005-2009 Spansion Inc. All rights reserved. Spansion

®

, the Spansion Logo, MirrorBit

®

, MirrorBit

®

Eclipse

, ORNAND

,

ORNAND2

, HD-SIM

, EcoRAM

and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.

February 27, 2009 S25FL064A_00_C4 S25FL064A 37

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