datasheet for TMS320DM647 by Texas Instruments

TMS320DM647

TMS320DM648 www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

TMS320DM647/TMS320DM648 Digital Media Processor

Check for Samples: TMS320DM647 , TMS320DM648

1

1 Features

• High-Performance Digital Media Processor

– 720-MHz, 800-MHz, 900-MHz, 1.1-GHz

C64x+™ Clock Rates

• C64x+ L1/L2 Memory Architecture

– 256K-bit (32K-byte) L1P Program RAM/Cache

[Direct Mapped]

– 1.39 ns (-720), 1.25 ns (-800), 1.11 ns (-900),

0.91 ns (-1100) Instruction Cycle Time

– 5760, 6400, 7200, 8800 MIPS

– Eight 32-Bit C64x+ Instructions/Cycle

– 256K-bit (32K-byte) L1D Data RAM/Cache

[2-Way Set-Associative]

– 2M-bit/256K-byte (DM647) or 4M-Bit/512Kbyte) (DM648) L2 Unified Mapped

RAM/Cache [Flexible Allocation]

– Fully Software-Compatible With C64x/Debug

– Commercial Temperature Ranges (-720, -900, and -1100 only)

– Extended Temperature Ranges (-800 only)

• Supports Little Endian Mode Only

• Five Configurable Video Ports

– Industrial Temperature Ranges (-720, -900, and -1100 only)

• VelociTI.2™ Extensions to VelociTI™

Advanced Very-Long-Instruction-Word (VLIW)

TMS320C64x+™ DSP Core

– Eight Highly Independent Functional Units

With VelociTI.2 Extensions:

– Providing a Glueless I/F to Common Video

Decoder and Encoder Devices

– Supports Multiple Resolutions/Video

Standards

• VCXO Interpolated Control Port (VIC)

– Supports Audio/Video Synchronization

• External Memory Interfaces (EMIFs)

• Six ALUs (32-/40-Bit), Each Supports

Single 32-bit, Dual 16-bit, or Quad 8-bit

Arithmetic per Clock Cycle

• Two Multipliers Support Four 16 x 16-bit

Multiplies (32-bit Results) per Clock Cycle or Eight 8 x 8-bit Multiplies (16-Bit

Results) per Clock Cycle

– 32-Bit DDR2 SDRAM Memory Controller With

– Asynchronous 16-Bit Wide EMIF (EMIFA)

•

•

512M-Byte Address Space (1.8-V I/O)

Up to 128M-Byte Total Address Reach

64M-Byte Address Reach per CE Space

– Glueless Interface to Asynchronous

Memories (SRAM, Flash, and EEPROM)

1

– Load-Store Architecture With Non-Aligned

Support

– 64 32-bit General-Purpose Registers

– Instruction Packing Reduces Code Size

– All Instructions Conditional

– Additional C64x+™ Enhancements

• Protected Mode Operation

• Exceptions Support for Error Detection and Program Redirection

• Hardware Support for Modulo Loop Auto-

Focus Module Operation

– Synchronous Memories (SBSRAM and ZBT

SRAM)

– Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)

• Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

• 3-Port Gigabit Ethernet Switch Subsystem

• Four 64-Bit General-Purpose Timers (Each

Configurable as Two 32-Bit Timers)

• One UART (With RTS and CTS Flow Control)

• C64x+ Instruction Set Features

– Byte-Addressable (8-/16-/32-/64-bit Data)

– 8-bit Overflow Protection

– Bit-Field Extract, Set, Clear

• One 4-wire Serial Port Interface (SPI) With Two

Chip-Selects

• Master/Slave Inter-Integrated Circuit (I2C

Bus™)

– Normalization, Saturation, Bit-Counting

– VelociTI.2 Increased Orthogonality

• Multichannel Audio Serial Port (McASP)

– Ten Serializers and SPDIF (DIT) Mode

– C64x+ Extensions

• Compact 16-bit Instructions

• 16/32-Bit Host-Port Interface (HPI)

• Advanced Event Triggering (AET) Compatible

• Additional Instructions to Support

Complex Multiplies

• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component

Interconnect (PCI) Master/Slave Interface

Conforms to PCI Specification 2.3

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2007–2012, Texas Instruments Incorporated

TMS320DM647

TMS320DM648


• VLYNQ™ Interface (FPGA Interface)

• On-Chip ROM Bootloader

• Individual Power-Saving Modes

• Flexible PLL Clock Generators

• IEEE-1149.1 (JTAG™) Boundary-Scan-

Compatible

• 32 General-Purpose I/O (GPIO) Pins www.ti.com

(Multiplexed With Other Device Functions)

• Package:

– 529-pin nFBGA (ZUT suffix)

– 19x19 mm 0.8 mm pitch BGA

– 0.09-

μ

m/6-Level Cu Metal Process (CMOS)

• 3.3-V and 1.8-V I/O, 1.2-V Internal (-720, -800, -

900, -1100)

1.1

Applications

• Digital Video Recording

1.2

Trademarks

TMS320C64x+, C64x, C64x+, VelociTI, VelociTI.2, VLYNQ, TMS320C6000, C6000, TI, and TMS320 are trademarks of Texas Instruments.

I2C Bus is a registered trademark of Koninklijke Philips Electronics N.V.

Windows is a registered trademark of Microsoft Corporation in the United States and/or other countries.

All trademarks are the property of their respective owners.

1.3

Description

The TMS320C64x+™ DSPs (including the TMS320DM647/TMS320DM648 devices) are the highestperformance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM647, DM648 devices are based on the third-generation high-performance, advanced VelociTI™ very-long-instructionword (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and

C64x+ CPU, respectively.

With performance of up to 8800 million instructions per second (MIPS) at a clock rate of 1.1 GHz, the

C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The

C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications.

The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for up to 4400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for up tp 8800 MMACS. For more details on the

C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 ).

The devices also have application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 4Mbit (DM648) or 2M-bit (DM647) memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes five configurable 16-bit video port peripherals (VP0, VP1, VP2, VP3, and

VP4). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-

BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M), a VCXO interpolated control port (VIC); a 1000

Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two SGMII

2

Features


Submit Documentation Feedback

Product Folder Link(s):

TMS320DM647 TMS320DM648

TMS320DM647


SPRS372H – MAY 2007 – REVISED APRIL 2012 ports (DM648) or one SGMII port (only DM647); a 4-bit transmit, 4-bit receive VLYNQ interface; an interintegrated circuit (I2C) bus interface; a multichannel audio serial port (McASP) with ten serializers; four 64bit general-purpose timers each configurable as two independent 32-bit timers; a user-configurable 16-bit or 32-bit host-port interface (HPI); 32 pins for general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART; and two glueless external memory interfaces: a synchronous and asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher DDR2 SDRAM interface.

The video port peripherals provide a glueless interface to common video decoder and encoder devices.

The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656,

BT.1120, SMPTE 125M, 260M, 274M, and 296M).

The video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels (A and B) with a 5120-byte capture/display buffer that is splittable between the two channels.

For more details on the video port peripherals, see the TMS320DM647/DM648 Video Port User's Guide

(literature number SPRUEM1 ).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The devices have a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.





Features

3

TMS320DM647

TMS320DM648


1.4

Functional Block Diagram

Figure 1-1

shows the functional block diagram of the device.

Timers

(4 64-bit or 8 32-bit)

PCI66 or

UHPI

3-port Ethernet

Switch

Subsystem

SGMII

(x2, DM648)

(x1, DM647)

TC

EDMA 3.0

TC

CC

TC TC

VLYNQ

DDR2

EMIFA 16-bit

Video Ports (5)

McASP

UART

SPI

I2C

Switched Central Resource

L1D 32KB

C64x+

Mega

L2 RAM

256KB

(DM647)

512KB

(DM648)

L1P 32KB L2 ROM

64KB

Imaging Coprocessor

Figure 1-1. Functional Block Diagram

PLL

JTAG

GPIO x32

VIC www.ti.com

4

Features





www.ti.com

1 Features

...................................................

1

1.1

Applications

1.2

Trademarks

..........................................

2

..........................................

2

1.3

Description

...........................................

2

1.4

Functional Block Diagram

...........................

4

Revision History

..............................................

6

2 Device Overview

........................................

7

2.1

Device Characteristics

...............................

7

2.2

CPU (DSP Core) Description

2.3

C64x+ CPU

........................

8

.........................................

11

2.4

Memory Map Summary

............................

12

2.5

Pin Assignments

....................................

16

2.6

Terminal Functions

.................................

20

2.7

Device Support

.....................................

34

3 Device Configuration

.................................

38

3.1

System Module Registers

..........................

38

3.2

Bootmode Registers

................................

39

3.3

Pullup/Pulldown Resistors

..........................

49

4 System Interconnect

..................................

50

4.1

Internal Buses, Bridges, and Switch Fabrics

.......

50

4.2

Data Switch Fabric Connections

...................

50

4.3

Configuration Switch Fabric

5 Device Operating Conditions

5.3

Electrical Characteristics

........................

52

.......................

54

5.1

Absolute Maximum Ratings

........................

54

5.2

Recommended Operating Conditions

..............

55

...........................

56

6 Peripheral Information and Electrical

Specifications

..........................................

57

6.1

Parameter Information

..............................

57

TMS320DM647

TMS320DM648


6.2

Recommended Clock and Control Signal Transition

Behavior

............................................

59

6.3

Power Supplies

.....................................

59

6.4

PLL1 Controller

6.5

PLL2 Controller

.....................................

65

.....................................

69

6.6

Enhanced Direct Memory Access (EDMA3)

Controller

...........................................

71

6.7

Reset Controller

....................................

84

6.8

Interrupts

...........................................

96

6.9

DDR2 Memory Controller

.........................

100

6.10

External Memory Interface A (EMIFA)

6.11

Video Port

............

111

.........................................

118

6.12

VCXO Interpolated Control (VIC)

.................

126

6.13

Universal Asynchronous Receiver/Transmitter

(UART)

............................................

128

6.14

Serial Peripheral Interface Port (SPI)

6.15

Inter-Integrated Circuit (I2C)

.............

130

......................

134

6.16

Host-Port Interface (HPI) Peripheral

..............

138

6.17

Peripheral Component Interconnect (PCI)

6.18

Multichannel Audio Serial Port (McASP)

........

149

..........

154

6.19

3-Port Ethernet Switch Subsystem (3PSW)

6.20

Management Data Input/Output (MDIO)

.......

162

..........

172

6.21

Timers

.............................................

173

6.22

VLYNQ Peripheral

.................................

175

6.23

General-Purpose Input/Output (GPIO)

............

178

6.24

Emulation Features and Capability

6.25

IEEE 1149.1 JTAG

...............

180

................................

181

7 Mechanical Data

......................................

183

7.1

Thermal Data for ZUT

7.2

Packaging Information

.............................

183

............................

184





Contents

5

TMS320DM647

TMS320DM648


www.ti.com

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the SPRS372G device-specific data manual to make it an SPRS372H revision. Applicable updates to the TMS320DM64x Digital Media

Processors device family , specifically relating to the TMS320DM647, TMS320DM648 devices which are now in the production data (PD) stage of development, have been incorporated.

SEE

Section 1

Section 1.1

Table 2-4

Figure 6-5

Section 6.4.1

Table 6-44

Figure 6-21

Table 6-49

Section 7.2

DM647/DM648 Revision History

ADDITIONS, DELETIONS, MODIFICATIONS

External Memory Interfaces (EMIFs):

• Deleted the footnote reference (1) from "512M-Byte Address Space (1.8-V I/O)" subbullet

• Deleted associated footnote [devices are PD; SR1.0 was TMX]

Added separate Applications section (new format structure)

Terminal Functions, Power Pins:

• Added "or left unconnected" to the V

CCMON

Device-Specific Silicon Errata.]

(L19) pin DESCRIPTION column [For the Advisory, see the

Corrected CLKDIR to VLYNQ to show 0 is VLYNQ, external

PLL1 Controller Device-Specific Information

• Added "[When SYSCLK4 is used as the EMIF input clock source, the actual clock goes through a divider and the frequency would be SYSCLK4 divide-by-2 (see

Figure 6-5 , PLL Input Clock).]" to the

SYSCLK4 is used as the EMIFA AECLKOUT bullet [Cleared Doc Feedback]

Timing Requirements for Asynchronous Memory Cycles for EMIFA Module:

• Changed 3ns to 0ns for t h

(AOEH-EDV)

Updated to show times 3 and 4 are referred to rising edge AAOE/ASOE.

Changed 5.4ns to 4.2ns for t w(VKIH) and t w(VKIL)

.

Deleted duplicated Orderable Addendum table

6

Contents





TMS320DM647


2 Device Overview


2.1

Device Characteristics

Table 2-1 , provides an overview of the DSP. The tables show significant features of the devices, including

the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.

Table 2-1. Characteristics of the Processor

DM647 HARDWARE FEATURES

DDR2 memory controller (32-bit bus width) [1.8 V I/O]

16-bit bus width synchronous/asynchronous

EMIF [EMIFA]

EDMA3 (64 independent channels, 8 QDMA channels)

1

1

1

Timers

4 64-bit General Purpose

(each configurable as 1 64-bit or 2 32bit)

(with RTS and CTS flow control)

1 (Master/Slave)

1 (4-wire, 2 chip select)

1 (10 serializers)

UART

Peripherals

I2C

Not all peripheral SPI pins are available

McASP at the same time

(For more detail, see

Section 3 .)

3-port Ethernet Switch

Subsystem supporting

10/100/1000 Base-T

Management data input/output

(MDIO)

VLYNQ

General-purpose input/output port (GPIO)

HPI (16/32-bit)

PCI (32 bit) (33 MHz or 66

MHz)

VIC

Configurable video ports

Size (bytes)

On-Chip Memory

Organization

1 SGMII port available

1

Up to 32 pins

1

1 (PCI33 or PCI66)

1

5

320KB RAM, 64KB ROM

32KB L1 program (L1P)/cache (up to

32KB)

32KB L1 data (L1D)/cache (up to

32KB)

256KB unified mapped RAM/Cache

(L2)

64KB Boot ROM

DM648

1

1

1

4 64-bit General Purpose

(each configurable as 1 64-bit or 2 32-bit)

(with RTS and CTS flow control)

1 (Master/Slave)

1 (4-wire, 2 chip select)

1 (10 serializers)

2 SGMII ports available

1

Up to 32 pins

1

1 (PCI33 or PCI66)

1

5

576KB RAM, 64KB ROM

32KB L1 program (L1P)/cache (up to 32KB)

32KB L1 data (L1D)/cache (up to 32KB)

512 KB unified mapped RAM/Cache (L2)

64KB Boot ROM

MegaModule

Rev ID

Revision ID Register

(MM_REVID[15:0])

(address location 0x0181 2000)

CPU ID + CPU

Rev ID

JTAG BSDL_ID

Control Status Register

(CSR.[31:16])

JTAGID register

(address location: 0x0204 9018)

CPU Frequency MHz

0x0003

0x1000

0x1B77 A02F

720, 900, 1100

0x0003

0x1000

Cycle Time

Voltage ns

Core (V)

I/O (V)

1.39 ns (-720)

1.11 ns (-900)

0.91 ns (-1100)

1.2 V (-720, -900, -1100)

1.8 V, 3.3 V

0x1B77 A02F

720, 800, 900, 1100

1.39 ns (-720)

1.25 ns (-800)

1.11 ns (-900)

0.91 ns (-1100)

1.2 V (-720, -800, -900, -1100)

1.8 V, 3.3 V

Device Overview

7





TMS320DM647

TMS320DM648


www.ti.com

Table 2-1. Characteristics of the Processor (continued)

PLL Options

HARDWARE FEATURES

CLKIN1 frequency multiplier

DM647

x1 (Bypass),

PLLM = 15, 16, …, 31

(x16, x17, …, x32)

(1)

529-Pin Flip Chip Plastic BGA (ZUT) BGA Package

Process

Technology

Product Status

(2)

0.09μ m/6-Level Cu Metal

Process (CMOS)

Production Data (PD)

(1) The maximum CPU frequency must not be violated.

(2) See

Section 2.7

for a description of each stage of development.

0.09

PD

μ m

DM648

x1 (Bypass),

PLLM = 15, 16, …, 31

(x16, x17, …, x32)

(1)

529-Pin Flip Chip Plastic BGA (ZUT)

0.09

μ m

PD

2.2

CPU (DSP Core) Description

The C64x+ central processing unit (CPU) consists of eight functional units, two register files, and two data paths as shown in

Figure 2-1 . The two general-purpose register files (A and B) each contain 32 32-bit

registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

The C64x+ CPU extends the performance of the C64x core through enhancements and new features.

Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x

32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four

16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for

Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The

32 x 32 bit multiply instructions provide the extended precision necessary for audio and other highprecision algorithms on a variety of signed and unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were available only on the .L units. On the C64x+ core they are also available on the .S unit, which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

8

Device Overview





TMS320DM647



• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.

• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.

• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal opcodes).

• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.

• Time-Stamp Counter - Primarily targeted for real-time operating system (RTOS) robustness, a freerunning time-stamp counter that is not sensitive to system stalls is implemented in the CPU.

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 )

• TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871 )

• TMS320C64x to TMS320C64x+ CPU Migration Guide Application Report (literature number SPRAA84 )

• TMS320C64x+ DSP Cache User's Guide (literature number SPRU862 )





Device Overview

9

TMS320DM647

TMS320DM648


Data path A

ST1b

ST1a

32 MSB

32 LSB

LD1b

LD1a

32 MSB

32 LSB

DA1 src1

.L1

src2 odd dst even dst long src

8 long src even dst

.S1

odd dst src1 src2

.M1

dst2 dst1 src1 src2

8

32

32

.D1

dst src1 src2

.D2

src2 src1 dst

(D)

Odd register file A

(A1, A3,

A5...A31)

Even register file A

(A0, A2,

A4...A30)

(D)

(A)

(B)

(C)

DA2

LD2a

LD2b

32 LSB

32 MSB

(C)

(B)

(A)

2x

1x

Odd register file B

(B1, B3,

B5...B31)

Even register file B

(B0, B2,

B4...B30)

Data path B

.M2

src2 src1 dst2 dst1 src2 src1

.S2

odd dst even dst long src

32

32

8

(D)

ST2a

ST2b

32 MSB

32 LSB long src even dst

.L2

odd dst src2 src1

8

(D)

Control Register

A. On .M unit, dst2 is 32 MSB.

B. On .M unit, dst1 is 32 LSB.

C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit,src2 is 64 bits.

D. On .L and .S units, odd dst connects to odd register files andeven dst connects to even register files.

Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths www.ti.com

10

Device Overview





TMS320DM647



HEX ADDRESS RANGE

0x0184 0000

0x0184 0020

0x0184 0024

0x0184 0040

0x0184 0044

0x0184 0048 - 0x0184 0FFC

0x0184 1000

0x0184 1004 - 0x0184 1FFC

0x0184 2000

0x0184 2004

0x0184 2008

0x0184 200C

0x0184 2010 - 0x0184 3FFF

0x0184 4000

0x0184 4004

0x0184 4010

0x0184 4014

0x0184 4018

0x0184 401C

0x0184 4020

0x0184 4024

0x0184 4030

0x0184 4034

0x0184 4038

0x0184 4040

0x0184 4044

0x0184 4048

0x0184 404C

0x0184 4050 - 0x0184 4FFF

0x0184 5000

0x0184 5004

0x0184 5008

0x0184 500C - 0x0184 5027

0x0184 5028

0x0184 502C - 0x0184 5039

0x0184 5040

0x0184 5044

0x0184 5048

2.3

C64x+ CPU

The C64x+ core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of 32KB memory space that can be configured as mapped memory or direct mapped cache. The

Level 1 data memory/cache (L1D) consists of 32KB that can be configured as mapped memory or 2-way associated cache. The Level 2 memory/cache (L2) consists of a 256KB (DM647)/512 KB (DM648) memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both.

Table 2-2

shows a memory map of the C64x+ CPU cache registers for the device.

Table 2-2. C64x+ Cache Registers

L1PIBAR

L1PIWC

L1DWIBAR

L1DWIWC

-

L1DWBAR

L1DWWC

L1DIBAR

L1DIWC

-

L2WB

L2WBINV

L2INV

-

L1PINV

-

L1DWB

L1DWBINV

L1DINV

REGISTER ACRONYM

L2CFG

L1PCFG

L1PCC

L1DCFG

L1DCC

-

-

-

L2ALLOC0

L2ALLOC1

L2ALLOC2

L2ALLOC3

-

L2WBAR

L2WWC

L2WIBAR

L2WIWC

L2IBAR

L2IWC

DESCRIPTION

L2 cache configuration register

L1P size cache configuration register

L1P freeze mode cache configuration register

L1D size cache configuration register

L1D freeze mode cache configuration register

Reserved

Reserved

Reserved

L2 allocation register 0




Reserved

L2 writeback base address register

L2 writeback word count register

L2 writeback invalidate base address register

L2 writeback invalidate word count register

L2 invalidate base address register

L2 invalidate word count register

L1P invalidate base address register

L1P invalidate word count register

L1D writeback invalidate base address register

L1D writeback invalidate word count register

Reserved

L1D block writeback

L1D block writeback

L1D invalidate base address register

L1D invalidate word count register

Reserved

L2 writeback all register

L2 writeback invalidate all register

L2 global invalidate without writeback

Reserved

L1P global invalidate

Reserved

L1D global writeback

L1D global writeback with invalidate

L1D global invalidate without writeback

Device Overview

11





TMS320DM647

TMS320DM648



0x0184 8000 - 0x0184 80FC

0x0184 80C0 - 0x0184 80FC

0x0184 8100 - 0x0184 813C

0x0184 8140 - 0x0184 827C

0x0184 8280 - 0x0184 82BC

0x0184 82C0 - 0x0184 82FC

0x0184 8130 - 0x0184 813C

0x0184 8300 - 0x0184 837C

0x0184 8380 - 0x0184 83BC

0x0184 83C0 - 0x0184 83FC

www.ti.com

Table 2-2. C64x+ Cache Registers (continued)


MAR0 - MAR63

MAR48 - MAR63

MAR64 - MAR79

MAR80 - MAR159

MAR160 - MAR175

MAR176 - MAR191

MAR76 - MAR79

MAR192 - MAR223

MAR224 - MAR239

MAR240 - MAR255

DESCRIPTION

Reserved 0x0000 0000 - 0x3FFF FFFF


Memory attribute registers for PCI Data 0x4000 0000 - 0x4FFF FFFF


Memory attribute registers for EMIFA CE2 0xA000 0000 - 0xA3FF FFFF

Memory attribute registers for EMIFA CE3 0xB000 0000 - 0xB3FF FFFF

Memory Attribute Registers for VLYNQ 0x4C00 0000 - 0x4FFF FFFF

Reserved 0xC000 0000 - 0xDFFF FFFF

Memory attribute registers for DDR2 0xE000 0000 - 0xEFFF FFFF

Memory attribute registers for DDR2 0xF000 0000 - 0xFFFF FFFF

0x00F0 8000

0x0100 0000

0x0180 0000

0x0181 0000

0x0181 1000

0x0181 2000

0x0181 3000

0x0182 0000

0x0182 0410

0x0183 0000

0x0184 0000

0x0185 0000

0x01BC 0000

START

ADDRESS

0x0000 0000

0x0010 0000

0x0020 0000

0x0080 0000

0x008C 0000

0x00A0 0000

0x00A4 0000

0x00A8 0000

0x00E0 0000

0x00E0 8000

0x00F0 0000

0x01BD 0000

0x01BE 0000

0x01BE 0000

0x0200 0000

0x0200 0080

0x0204 0000

2.4

Memory Map Summary

Table 2-3

shows the memory map address ranges of the device. The device has multiple on-chip memories associated with its processor and various subsystems. To help simplify software development, a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters.

Table 2-3. Memory Map Summary

0x00FF FFFF

0x017F FFFF

0x0180 FFFF

0x0181 0FFF

0x0181 1FFF

0x0181 2FFF

0x0181 FFFF

0x0182 040F

0x0182 FFFF

0x0183 FFFF

0x0184 FFFF

0x01BB FFFF

0x01BC FFFF

END

ADDRESS

0x000F FFFF

0x0011 FFFF

0x007F FFFF

0x008B FFFF

0x009F FFFF

0x00A3 FFFF

0x00A7 FFFF

0x00DF FFFF

0x00E0 7FFF

0x00EF FFFF

0x00F0 7FFF

0x01BD FFFF

0x01BF FFFF

0x01FF FFFF

0x0200 007F

0x0203 FFFF

0x0204 3FFF

1M – 32K

8M

64K

4K

4K

4K

52K

1040B

64K – 16

64K

64K

3, 520K

64K

SIZE

(Bytes)

1M

128K

6M

768K

2M - 768K

256K

256K

4M - 512K

32K

1M – 32K

32K

64K

128K

4.125M

128B

256K – 128

16K

C64x+

MEMORY MAP

Reserved

VICP

Reserved

Internal ROM

Reserved

L2 SRAM (for both DM647 and DM648)

L2 SRAM (for DM648 only)

Reserved

L1P SRAM

Reserved

L1D SRAM

Reserved

Reserved

C64x+ Interrupt Controller

C64x+ Power-down Control

C64x+ Security ID

C64x+ Revision ID

Reserved

C64x+ EMC

Reserved

Reserved

C64x+ Memory control

Reserved

Emulation

Reserved

Reserved

Reserved

HPI Control

Reserved

McASP Control

12

Device Overview





TMS320DM647



0x02B4 0000

0x02B4 0200

0x02B8 0000

0x02BA 0000

0x02BC 0000

0x02C0 0000

0x02C0 4000

0x02C0 8000

0x02C0 C000

0x02C1 0000

0x02C1 4000

0x02C4 0000

0x02C8 0000

0x02A2 0000

0x02A2 8000

0x02A3 0000

0x02A3 8000

0x02A4 0000

0x02A8 0000

0x02A8 0500

0x02AC 0000

0x02AE 0000

0x02B0 0000

0x02B0 0100

0x02B0 4000

0x02B0 4080

0x0204 8400

0x0204 8800

0x0204 9000

0x0204 A000

0x0208 0000

0x020A 0000

0x020E 0000

0x020E 0200

0x0212 0000

0x0212 0200

0x0216 0000

0x02A0 0000

0x02A0 8000

START

ADDRESS

0x0204 4000

0x0204 4400

0x0204 4800

0x0204 4C00

0x0204 5000

0x0204 5400

0x0204 6000

0x0204 7000

0x0204 7400

0x0204 7800

0x0204 7C00

0x0204 8000

Table 2-3. Memory Map Summary (continued)

0x02B4 01FF

0x02B7 FFFF

0x02B9 FFFF

0x02BB FFFF

0x02BF FFFF

0x02C0 3FFF

0x02C0 7FFF

0x02C0 BFFF

0x02C0 FFFF

0x02C1 3FFF

0x02C3 FFFF

0x02C7 FFFF

0x02CB FFFF

0x02A2 7FFF

0x02A2 FFFF

0x02A3 7FFF

0x02A3 FFFF

0x02A7 FFFF

0x02A8 04FF

0x02AB FFFF

0x02AD FFFF

0x02AF FFFF

0x02B0 00FF

0x02B0 3FFF

0x02B0 407F

0x02B3 FFFF

0x0204 87FF

0x0204 8FFF

0x0204 9FFF

0x0207 FFFF

0x0209 FFFF

0x020D FFFF

0x020E 01FF

0x0211 FFFF

0x0212 01FF

0x0215 FFFF

0x029C FFFF

0x02A0 7FFF

0x02A1 FFFF

END

ADDRESS

0x0204 43FF

0x0204 47FF

0x0204 4BFF

0x0204 4FFF

0x0204 53FF

0x0204 5FFF

0x0204 6FFF

0x0204 73FF

0x0204 77FF

0x0204 7BFF

0x0204 7FFF

0x0204 83FF

512

256K – 512

128K

128K

256K

16K

16K

16K

16K

16K

176K

256K

256K

32K

32K

32K

32K

256K

1.25K

256K – 1.25K

128K

128K

256

16K – 256

128

256K – 128

1K

2K

4K

216K

128K

256K

512

256K – 512

512

256K – 512

9M - 576K

32K

96K

1K

1K

1K

1K

3K

4K

1K

SIZE

(Bytes)

1K

1K

1K

1K

1K

Reserved

Reserved

Reserved

Reserved

Reserved

VP0 Control

VP1 Control

VP2 Control

VP3 Control

VP4 Control

Reserved

Reserved

Reserved

EDMA3TC0

EDMA3TC1

EDMA3TC2

EDMA3TC3

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

McASP Data

Timer0

Timer1

Timer2

Timer3

Reserved

PSC

UART

VIC Control

SPI

I2C Data and Control

GPIO

PCI Control

Reserved

Chip-Level Registers

Reserved

VICP Configuration

Reserved

PLL Controller 1

Reserved

PLL Controller 2

Reserved

Reserved

EDMA3CC

Reserved

C64x+

MEMORY MAP

Device Overview





13

TMS320DM647

TMS320DM648


www.ti.com

0x5000 0000

0x5200 0000

0x5400 0000

0x5600 0000

0x5800 0000

0x5A00 0000

0x5C00 0000

0x5E00 0000

0x6000 0000

0x6200 0000

0x6400 0000

0x6600 0000

0x6800 0000

0x7000 0000

0x7800 0000

0x8000 0000

0x9000 0000

0xA000 0000

0xA400 0000

0xB000 0000

0xB400 0000

0xC000 0000

0x0300 0000

0x0400 0000

0x1000 0000

0x2000 0000

0x3000 0000

0x3000 0100

0x3400 0000

0x3400 0100

0x3800 0000

0x3C00 0000

0x3D00 0000

0x3E00 0000

0x4000 0000

START

ADDRESS

0x02CC 0000

0x02D0 0000

0x02D0 2000

0x02D0 3000

0x02D0 4000

0x02D0 4800

0x02D0 4C00

0x02D0 5000

0x02D0 5800

0x02DC 0000

0x02E0 0000

0x02E0 4000


32M

32M

32M

32M

32M

128M

32M

32M

32M

32M

32M

32M

32M

128M

128M

256M

256M

64M

256 - 64M

64M

256 - 64M

256M

16M

192M

256M

256M

256

64M – 256

256

64M – 256

64M

16M

16M

32M

256M

SIZE

(Bytes)

256K

8K

4K

4K

2K

1K

1K

2K

746K

256K

16K

2M – 16K

0x51FF FFFF

0x53FF FFFF

0x55FF FFFF

0x57FF FFFF

0x59FF FFFF

0x5BFF FFFF

0x5DFF FFFF

0x5FFF FFFF

0x61FF FFFF

0x63FF FFFF

0x65FF FFFF

0x67FF FFFF

0x6FFF FFFF

0x77FF FFFF

0x7FFF FFFF

0x8FFF FFFF

0x9FFF FFFF

0xA3FF FFFF

0xAFFF FFFF

0xB3FF FFFF

0xBFFF FFFF

0xCFFF FFFF

0x03FF FFFF

0x0FFF FFFF

0x1FFF FFFF

0x2FFF FFFF

0x3000 00FF

0x33FF FFFF

0x3400 00FF

0x37FF FFFF

0x3BFF FFFF

0x3CFF FFFF

0x3DFF FFFF

0x3FFF FFFF

0x4FFF FFFF

END

ADDRESS

0x02CF FFFF

0x02D0 1FFF

0x02D0 2FFF

0x02D0 3FFF

0x02D0 47FF

0x02D0 4BFF

0x02D0 4FFF

0x02D0 57FF

0x02DB FFFF

0x02DF FFFF

0x02E0 3FFF

0x02FF FFFF

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

VLYNQ

Reserved

Reserved

Reserved

PCI Data

C64x+

MEMORY MAP

Reserved

Ethernet Subsystem CPPI RAM

(1)

Ethernet Subsystem Control

Ethernet Subsystem 3PSW

Ethernet Subsystem MDIO

Ethernet Subsystem SGMII0

Ethernet Subsystem SGMII1 (DM648 only)

Reserved

Reserved

Reserved

Reserved

Reserved

VP0 ChannelA Data

VP0 ChannelB Data

VP1 ChannelA Data

VP1 ChannelB Data

VP2 ChannelA Data

VP2 ChannelB Data

Reserved

Reserved

VP3 ChannelA Data

VP3 ChannelB Data

VP4 ChannelA Data

VP4 ChannelB Data

Reserved

EMIFA Configuration

DDR2 EMIF Configuration

Reserved

Reserved

EMIFA CE2

(2)

Reserved

EMIFA CE3

(2)

Reserved

Reserved

(1) The 8K CPPI Descriptor memory is mapped to an address range 0x02C8 2000 - 0x02C8 3FFF, from the perspective of the Ethernet subsystem 3PSW. The buffer descriptors, when accessed from the C64x+, are addressed from 0x02D0 0000. However, within these buffer descriptors, when the pointer to the next buffer descriptor is programmed, the Ethernet subsystem 3PSW is interpreting this value.

Thus, this programmed value should be in the address range starting from 0x02C8 2000.

(2) The EMIFA CS0 and CS1 are not functionally supported; therefore, they are not pinned out.

14

Device Overview





www.ti.com

START

ADDRESS

0xD000 0000

0xE000 0000

0xF000 0000

TMS320DM647

TMS320DM648



END

ADDRESS

0xDFFF FFFF

0xEFFF FFFF

0xFFFF FFFF

SIZE

(Bytes)

256M

256M

256M

Reserved

DDR2 SDRAM

DDR2 SDRAM

C64x+

MEMORY MAP





Device Overview

15

TMS320DM647

TMS320DM648


2.5

Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. For more information on pin muxing, see

Section 3.2.6

, PINMUX Register.

2.5.1

Pin Map (Bottom View)

Figure 2-2

through

Figure 2-5

show the bottom view of the ZUT package pin assignments in four quadrants (A, B, C, and D).

1 2 3 4 5 6 7 8 9 10 11 12

www.ti.com

AC

V

SS

D

VDD33

AHCLKX AHCLKR D

VDD33

ACLKR ACLKX V

SS

SGMII1RXN V

SS

REFCLKN V

SS

AB VP2CLK0 VP2CTL1 AMUTEIN AXR3

V

SS

AXR0

D

VDD33

A

VDDT

SGMII1RXP

A

VDDR

REFCLKP

D

VDD33

AA

VP2CTL0 VP2D03

V

SS

Y

VP2CTL2/

VSCRUN

VP2D06 VP2D04

AXR6

VDAC/

AXR9

AXR2

D

VDD33

AXR4

AFSX

V

SS

AXR1

STCLK/

AXR8

D

VDD33

SGMII0RXP SGMII0RXN

V

SS

V

SS

V

SS

SGMII0TXP

PREQ/

GP03

RSV21

W

VP2CLK1/

VCLK

VP2D12/

VRXD0

VP2D07 VP2D09 VP2D02 AFSR

V

SS

SGMII1TXP SGMII1TXN

A

VDDA

SGMII0TXN RSV22

V V

SS

D

VDD33

VP2D13

/VRXD1

VP2D14/

VRXD2

VP2D08 AXR7 AXR5

C

VDD

R

VP3CTL1/

AR/W

VP3D12/

AED08

VP3D09/

AED07

VP3D08/

AED06

VP3D07/

AED05

VP3D06/

AED04

D

VDD33

V

SS

C

VDD

C

VDDESS

RSV17

A

VDDA

PINTA/

GP02

U

VP2D15/

VRXD3

VP2D17/

VTXD1

VP2D16/

VTXD0

VP2D19/

VTXD3

VP2D18/

VTXD2

VP2D05 AMUTE MDIO MDCLK D

VDDD

T

VP3CLK0/

AECLKIN

VP3CTL0/ VP3D05/

AED03

VP3D04/

AED02

VP3D03/

AED01

VP3D02/

AED00

V

SS

D

VDD33

V

SS

D

VDDD

V

SS

A

VDDT

V

SS

C

VDDESS

PRST/

GP01

D

VDD33

V

SS

P

VP3CLK1/

AECLKOUT

VP3CTL2/ VP3D16/

AED12

VP3D15/

AED11

VP3D14/

AED10

VP3D13/

AED09

V

SS

D

VDD33

V

SS

C

VDD

V

SS

C

VDD

N V

SS

D

VDD33

PLLV1

VP3D17/

AED13

VP3D19/

AED15

VP3D18/

AED14

D

VDD33

M CLKIN1 RSV9 SYSCLK5

VP4D03/

ABE01

VP4D04/

AEA10

VP4D05

V

SS

V

SS

D

VDD33

C

VDD

V

SS

V

SS

C

VDD

C

VDD

V

SS

V

SS

C

VDD

Figure 2-2. ZUT Pin Map [Top Left Quadrant]

16

Device Overview





www.ti.com

13

AD26/

HD26

14

AD22/

HD22

15

PCLK/

HHWIL

AD27/

HD27

AD23/

HD23

AD17/

HD17

16

V

SS

17

PCBE1 /

HDS2

18

AD14/

HD14

D

VDD33

PIRDY /

HRDY

AD12/

HD12

19

D

VDD33

V

SS

AD08/

HD08

AD05/

HD05

AD01/

HD01

TMS320DM647

TMS320DM648

20

PCBE0/

GP04


21 22 23

AD02/

HD02

AD04/

HD04

D

VDD33

AC

V

SS

AB

AD28/

HD28

PIDSEL/

GP06

AD18/

HD18

PFRAME/

HINT

PTRDY/

GP05

AD15/

HD15

AD13/

HD13

AD09/

HD09

AD06/

HD06

AD00/

HD00

AD03/

HD03

AA

AD29/

HD29

PCBE3/

GP07

AD19/

HD19

AD16/

HD16

PDEVSEL/

HCNTL1

PSTOP/

HCNTL0

AD11/

HD11

AD10/

HD10

AD07/

HD07

VP0CTL0 VP0CLK0

Y

AD30/

HD30

AD24/

HD24

AD31/

HD31

Ad25/

HD25

AD20/

HD20

PCBE2 /

HR/ W

PPERR /

HCS

PSERR /

HDS1

PPAR/

HAS

VP0D02 VP0D06

AD21/

HD21

D

VDD33

V

SS

V

SS

D

VDD33

W

VP0D03 VP0D05 VP0D09

VP0D12/

GP12

VP0CTL1 VP0CLK1

V

PGNT/

GP00

V

SS

D

VDD33

V

SS

D

VDD33

VP0D04 VP0D08 VP0D16 VP0D18 VP0D17 VP0CTL2 U

C

V

SS

VDD

D

VDD33

V

SS

V

C

SS

VDD

C

VDD

V

SS

V

SS

VP0D07

VP0D13/

GP13

VP0D14/

GP14

VP0D15/

GP15

V

SS

D

VDD33

T

D

VDD33

VP0D19

VP1D02/

GP16

VP1D07/

GP21

VP1D06/

GP20

VP1D05/

GP19

VP1CTL0 R

V

C

VDD

V

SS

SS

C

C

VDD

V

SS

VDD

C

V

VDD

V

SS

SS

D

VDD33

D

V

SS

VDD33

V

SS

VP1D04/

GP18

VP1D03/

GP17

VP1D14/

GP26

VP1D13/

GP25

VP1CTL1 VP1CLK0 P

D

VDD33

VP1D17/

GP29

VP1D12/

GP24

VP1D09/

GP23

VP1D08/

GP22

VP1CTL2 VP1CLK1 N

V

SS

VP1D16/

GP28

VP1D19/

GP31

VP1D15/

GP27

VP1D18/

GP30

V

SS

D

VDD33

M

Figure 2-3. ZUT Pin Map [Top Right Quadrant]





Device Overview

17

TMS320DM647

TMS320DM648


L

VP4CLK0/

AARDY

VP4D02/

ABE00

VP4D06/

ACE2

VP4D07/

ACE3

VP4D08/

AEA00

VP4D13/

AEA03

D

VDD33

V

SS

K VP4CLK1

VP4CTL2/ VP4D09/

AEA01

VP4D12/

AEA02

VP4D14/

AEA04

VP4D19/

AEA09

V

SS

J

VP4CTL1/

ABA1

VP4CTL0/

ABA0

VP4D15/

AEA05

VP4D16/

AEA06

VP4D17/

AEA07

VP4D18/

AEA08

D

VDD33

D

VDD33

V

SS

C

VDD

V

SS

C

VDD

V

V

C

SS

VDD

SS

C

V

C

VDD

SS

VDD

V

C

V

SS

VDD

SS

H

V

SS

UHPIEN

HPIWIDTH/

AEA16

AEA23 AEA19

RSV_BOOT/

AEA15

RSV7

G

D

VDD33

F

CLKIN2

FASTBOOT

/AEA21

EMIFA

WIDTH/

AEA22

AECLKIN

SEL/

AEA17

DEVICE

ENABLE0/

AEA20

BOOT

MODE0/

AEA11

BOOT

MODE1/

AEA12

PCI66/

AEA18

BOOT

MODE2/

AEA13

BOOT

MODE3/

AEA14

RSV18

PLLV2

V

SS

E

RSV12 RSV11 RSV14 RSV13

D

VDD18

V

SS

D

RSV8

V

SS

VDD18

DDR_D07 DDR_D04

C

D

VDD1

VDD18

D

VDD18

V

SS

DDR_CS DDR_A13

D

V

SS

VDD18

D

V

VDD18

SS

DDR_A06 DDR_A08

DDR_D00

DDR_RAS

DDR_BA[2] DDR_A12

D

RSV4 RSV3

C

RSV20 RSV19

RSV6 RSV5

D

VDD18

V

SS

DDR_

DQM[1]

DDR_D10

DDR_

DQGATE0

DDR_D05 V

SS

DDR_CAS DDR_WE V

SS

DDR_D15 DDR_D08 DDR_D06 DDR_D03 DDR_D01 D

VDD18

DDR_

VREF

DDR_BA[0]

B

D

VDD18

A

V

SS

1

V

DD18MON

DDR_D12 DDR_D14

D

VDD18

DDR_

DQGATE1

DDR_D09

DDR_

DQM[0]

DDR_D02 A

VDLL1

DDR_CKE DDR_BA[1]

RSV10 DDR_D11 DDR_D13

2 3

V

SS

DDR_

DQS[1]

DDR_

DQS[1]

DDR_

DQS[0]

DDR_

DQS[0]

RSV15

4 5 6 7 8 9

Figure 2-4. ZUT Pin Map [Bottom Left Quadrant]

10

DDR_CLK DDR_CLK

11 12

www.ti.com

18

Device Overview





www.ti.com

TMS320DM647

TMS320DM648


C

VDD

V

SS

C

V

SS

C

VDD

VDD

V

SS

V

SS

D

VDD33

EMU4

V

CCMON

RSV1 RSV2 TMS TRST

L

D

VDD33

V

SS

EMU11 EMU6 EMU3 EMU2 EMU1 EMU0

K

C

VDD1

V

SS

C

VDD

V

SS

D

VDD33

NMI EMU10 EMU8 EMU5 TDI TDO

J

V

SS

D

VDD18

V

SS

D

VDD33

V

SS

POR

RESETSTAT

EMU9 EMU7

D

VDD33

TCLK

H

D

VDD18

V

SS

DDR_A02

D

VDD18

D

VDD18

V

SS

V

SS

D

VDD18

D

VDD18

V

SS

V

SS

D

VDD18

D

VDD33

V

SS

RESET

V

DD33MON

V

SS

SPIDI/

UARTRTS

G

D

VDD33

SPIDO/

UARTCTS

SPICLK

SPICS2/

UARTRX

F

DDR_ODT0 DDR_A03

DDR_

DQM[2]

DDR_D19 DDR_D23

DDR_

DQGATE2

DDR_D31

T0INP12/

GP08

T1INP12/

GP10

D

VDD33

DDR_A09 DDR_A04 DDR_A00 DDR_D18 DDR_D22 DDR_D25 DDR_D29

V

SS

V

SS

E

T0OUT12/

GP09

SCL

SPICS1/

UARTTX

D

D

VDD18

DDR_A05 DDR_A01

DDR_D17 DDR_D21 DDR_D24 DDR_D27

DDR_D30 D

VDD18

T1OUT12/

GP11

SDA

C

D

VDD18

B

DDR_A11 DDR_A07 D

VDD18

DDR_D16 DDR_D20 D

VDD18

DDR_D26 DDR_D28

DDR_

DQM[3]

A

VDLL2

DDR_A10 DDR_ODT1

13

V

SS

DDR_

DQS[2]

DDR_

DQS[2]

V

SS

DDR_

DQS[3]

DDR_

DQS[3]

DDR_

DQGATE3

RSV16

14 15 16 17 18 19 20

Figure 2-5. ZUT Pin Map [Bottom Right Quadrant]

21 22

V

SS

23

A





Device Overview

19

TMS320DM647

TMS320DM648


www.ti.com

2.6

Terminal Functions

The terminal functions tables ( Table 2-4

through

Table 2-5 ) identify the external signal names, the

associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and debugging considerations, see

Section 3 .

All device boot and configuration pins are multiplexed with functional pins. These pins function as device boot and configuration pins only during device reset. When both the reset pin (RESET) and the power-on reset pin (POR) are deasserted, the input states of these multiplexed device boot and configuration pins are sampled and latched into the BOOTCFG register. For proper device operation, these pins must be pulled up/down to the desired value via an external resistor.

Table 2-4. Terminal Functions

TERMINAL NAME NO TYPE

1)

(

INTERNAL

PULLUP/

PULLDOWN

OPER

VOLT

DESCRIPTION

CLKIN1

CLKIN2

REFCLKN

(2)

REFCLKP

(2)

PLLV1

PLLV2

SYSCLK5

TCLK

TDI

TDO

TMS

TRST

EMU0

EMU1

EMU2

EMU3

EMU4

EMU5

EMU6

EMU7

EMU8

EMU9

EMU10

EMU11

NMI

RESETSTAT

RESET

POR

M1

F1

AC11

AB11

N3

G7

M3

H23

J22

J23

L22

L23

J18

H19

G20

H18

A

A

I/O/Z

I

I

I

I

I

I

OZ

I

I

K23 I/O/Z

K22 I/O/Z

K21 I/O/Z

K20 I/O/Z

L18 I/O/Z

J21 I/O/Z

K19 I/O/Z

H21 I/O/Z

J20 I/O/Z

H20 I/O/Z

J19 I/O/Z

K18 I/O/Z

I

O

I

I

IPD

IPD

IPD

IPU

IPU

IPU

IPU

IPD

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPD

Clock/PLL Configuration

3.3 V Clock Input for PLL1

3.3 V Clock Input for PLL2

Differential Reference Clock input (negative) for SGMII

1.8 V

1.8 V

Differential Reference Clock input (positive) for SGMII

1.8-V I/O Supply Voltage for PLL1

1.8-V I/O Supply Voltage for PLL2

3.3 V

JTAG

Clock out of device speed/4

3.3 V

3.3 V

JTAG Test Port Clock

JTAG Test Port Data In

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

JTAG Test Port Data Out

JTAG Test Port Mode Select

JTAG Test Port Reset

JTAG Test Port Emulation 0







3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

RESET/INTERRUPTS

3.3 V

3.3 V

3.3 V

3.3 V






Nonmaskable Interrupt

Reset Status Pin

Device Reset

Power On Reset

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2) The clock input buffers on the REFCLKP/N pins are compatible with LVDS and LVPECL clock sources. These input buffers include a

100Ω termination (P to N) and a common-mode biasing. Because the common-mode biasing is included, the clock source must be AC coupled.

20

Device Overview





TMS320DM647



Table 2-4. Terminal Functions (continued)

TERMINAL NAME

AD00/HD00

AD01/HD01

AD02/HD02

NO TYPE

1)

(

INTERNAL

PULLUP/

PULLDOWN

OPER

VOLT

DESCRIPTION

HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) or GPIO[0:7]

AA22 I/O/Z 3.3 V Host Port data [15:00] pin or PCI data-address bus [15:00]

[default]

AB22 I/O/Z

AC21 I/O/Z

3.3 V

3.3 V

AD03/HD03

AD04/HD04

AD05/HD05

AD06/HD06

AD07/HD07

AD08/HD08

AD09/HD09

AA23

AC22

AB21

AA21 I/O/Z

Y21 I/O/Z

AB20

AA20

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

AD10/HD10

AD11/HD11

AD12/HD12

AD13/HD13

AD14/HD14

AD15/HD15

AD16/HD16

AD17/HD17

AD18/HD18

AD19/HD19

Y20

Y19 I/O/Z

AB18 I/O/Z

AA19

AC18

AA18

Y16 I/O/Z

AB15 I/O/Z

AA15

Y15

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

Host Port data [31:16] pin or PCI data-address bus [31:16]

[default]

AD20/HD20

AD21/HD21

AD22/HD22

AD23/HD23

AD24/HD24

AD25/HD25

AD26/HD26

AD27/HD27

AD28/HD28

AD29/HD29

AD30/HD30

AD31/HD31

PPAR/HAS

PSTOP/HCNTL0

W15 I/O/Z

V15 I/O/Z

AC14 I/O/Z

AB14 I/O/Z

W14 I/O/Z

V14 I/O/Z

AC13 I/O/Z

AB13 I/O/Z

AA13 I/O/Z

Y13 I/O/Z

W13 I/O/Z

V13 I/O/Z

W19 I/O/Z

Y18 I/O/Z

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

PDEVSEL/HCNTL1

PPERR/HCS

PSERR/ HDS1

PCBE0/GP04

PCBE1/HDS2

PCBE2/HR/W

PCBE3/GP07

PCLK/HHWIL

Y17

W17

AC17

I/O/Z

I/O/Z

W18 I/O/Z

AC20 I/O/Z

I

W16 I/O/Z

Y14 I/O/Z

AC15 I/O/Z

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

Host Address Strobe (I) or PCI parity [default]

Host Control selects between control, address, or data registers (I) or PCI Stop [default]

Host Control selects between control, address, or data registers (I) or PCI Device Select [default]

Host Chip Select (I) or PCI Parity Error [default]

Host Data Strobe 1 (I) or PCI System Error [default]

PCI Command/Byte Enable 0 or GP[4] [default

PCI Command/Byte Enable 1 or host data strobe 2

PCI Command/Byte Enable 2 or host read or write select (I)

PCI Command/Byte Enable 3 or GPIO[7]

PCI Clock (I) [default] or host Half-word Select - first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] (I)

Device Overview

21





TMS320DM647

TMS320DM648

DDR_CLK

DDR_D00

DDR_D01

DDR_D02

DDR_D03

DDR_D04

DDR_D05

DDR_D06

DDR_D07

DDR_D08

DDR_D09

DDR_D10

DDR_D11

DDR_D12

DDR_D13

DDR_D14

DDR_D15

DDR_BA[0]

DDR_BA[1]

DDR_BA[2]

DDR_CS

DDR_A00

DDR_A01

DDR_A02

DDR_A03

DDR_A04

DDR_A05

DDR_A06

DDR_A07

DDR_A08

DDR_A09

DDR_A10

DDR_A11

DDR_A12

DDR_A13

DDR_CLK


TERMINAL NAME

PFRAME/HINT

PIRDY/HRDY

PGNT/GP00

PRST/GP01

PINTA/GP02

PREQ/GP03

PTRDY/GP05

PIDSEL/GP06

www.ti.com

C12 I/O/Z

B12 I/O/Z

E11 I/O/Z

F9 I/O/Z

D15 I/O/Z

C15 I/O/Z

F13 I/O/Z

E14 I/O/Z

D14 I/O/Z

C14 I/O/Z

F11 I/O/Z

B14 I/O/Z

F12 I/O/Z

D13 I/O/Z

A13 I/O/Z

B13 I/O/Z

E12 I/O/Z

F10 I/O/Z

A12 I/O/Z

A4

B4

C5

D6

A3

B3

C8

E8

D8

C7

E7

C6

B7

A11 I/O/Z

E9 I/O/Z

C9

B9

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

NO TYPE

1)

(

AA16 I/O/Z

AB17 I/O/Z

U13 I/O/Z

U12 I/O/Z

V12 I/O/Z

AA12 I/O/Z

AA17 I/O/Z

AA14 I/O/Z


INTERNAL

PULLUP/

PULLDOWN

OPER

VOLT

DESCRIPTION

3.3 V

3.3 V

3.3 V

3.3 V

PCI Frame or host interrupt from DSP to host (O/Z)

PCI Initiator Ready [default] or Host Ready from DSP to host (O/Z)

PCI Bus Grant (I) or GPIO[0]

PCI Reset (I) or GPIO[1]

3.3 V

3.3 V

PCI Interrupt A (O/Z) or GPIO[2]

PCI Bus Request (O/Z) or GPIO[3]

3.3 V

1.8 V

1.8 V

PCI Target Ready or GPIO[5]

3.3 V PCI Initialization Device Select (I) or GPIO[6]

DDR2 MEMORY CONTROLLER

DDR2 Memory Controller Bank Address Control

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

DDR2 Memory Controller Memory Space Enable

DDR2 Memory Controller External Address

Negative DDR2 Memory Controller Output Clock (CLKIN2 frequency x 10)

DDR2 Memory Controller Output Clock (CLKIN2 frequency x 10)

DDR2 Memory Controller External Data

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

22

Device Overview





DDR_D16

DDR_D17

DDR_D18

DDR_D19

DDR_D20

DDR_D21

DDR_D22

DDR_D23

DDR_D24

DDR_D25

DDR_D26

DDR_D27

DDR_D28

DDR_D29

DDR_D30

DDR_D31

DDR_ODT0

DDR_ODT1

DDR_CAS

DDR_CKE

DDR_DQGATE0

DDR_DQGATE1

DDR_DQGATE2

DDR_DQGATE3

DDR_DQM[0]

DDR_DQM[1]

DDR_DQM[2]

DDR_DQM[3]

DDR_DQS[0]

DDR_DQS[1]

DDR_DQS[2]

DDR_DQS[3]

DDR_DQS[0]

DDR_DQS[1]

DDR_DQS[2]

DDR_DQS[3]

DDR_RAS

DDR_WE

www.ti.com

TERMINAL NAME

TMS320DM647

TMS320DM648


B16 I/O/Z

C16 I/O/Z

D16 I/O/Z

E16 I/O/Z

B17 I/O/Z

C17 I/O/Z

D17 I/O/Z

E17 I/O/Z

C18 I/O/Z

D18 I/O/Z

B19 I/O/Z

C19 I/O/Z

B20 I/O/Z

D19 I/O/Z

C20 I/O/Z

E19 I/O/Z

E13 I/O/Z

A14 I/O/Z

D10 I/O/Z

B11 I/O/Z

D7

B6

I/O/Z

I/O/Z

E18 I/O/Z

A21 I/O/Z

B8 I/O/Z

D5 I/O/Z

E15 I/O/Z

B21 I/O/Z

A9

A7

I/O/Z

I/O/Z

A17 I/O/Z

A20 I/O/Z

A8 I/O/Z

A6 I/O/Z

A16 I/O/Z

A19 I/O/Z

E10 I/O/Z

D11 I/O/Z

NO TYPE

1)

(


INTERNAL

PULLUP/

PULLDOWN

OPER DESCRIPTION

VOLT

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

DDR2 Memory Controller External Data (continued)

On-die termination signals to external DDR2 SDRAM. These pins are reserved for future use and should not be connected to the

DDR2 SDRAM.

Note: There are no on-die termination resistors implemented on the DM647/DM648 DSP die.

DDR2 Memory Controller SDRAM column address strobe

DDR2 Memory Controller SDRAM clock-enable

DDR2 Memory Controller Data Strobe Gate

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

DDR2 Memory Controller Byte-enable Controls. Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. Byte-write enables for most types of memory. Can be directly connected to

SDRAM read and write mask signal (SDQM).

DDR2 Memory Controller Data Strobe [3:0]

DDR2 Memory Controller Data Strobe [3:0] Negative

DDR2 Memory Controller SDRAM Row Address Strobe

DDR2 Memory Controller SDRAM Write Enable





Device Overview

23

TMS320DM647

TMS320DM648


www.ti.com

TERMINAL NAME

DEVICEENABLE0/

AEA20

EMIFAWIDTH/

AEA22

FASTBOOT/

AEA21

UHPIEN

HPIWIDTH/

AEA16

RSV_BOOT/

AEA15

PCI66/AEA18

NO TYPE

1)

(

F2

G3

G2

H2

H3

H6

G5

BOOTMODE0/AEA11 F3

BOOTMODE1/AEA12 F4

BOOTMODE2/AEA13 F5

BOOTMODE3/AEA14 G6

I/O/Z

I/O/Z

I/O/Z

I

I/O/Z

I/O/Z

I/O/Z

I/O/Z


INTERNAL

PULLUP/

PULLDOWN

IPD

IPD

OPER

VOLT

DESCRIPTION

CONFIGURATION AND EMIFA

3.3 V EMIFA External Address 20 (word address). (O/Z) For proper device operation, this pin must be externally pulled up with a 1-k Ω resistor at device reset

3.3 V EMIFA External Address 22 (word address). (O/Z) EMIFA data bus width selection pin state captured at the rising edge of

RESET.

0 - sets EMIFA CS2 to 8-bit data bus width

1 - sets EMIFA CS2 to 16 bit data bus width. For details, see

Section 3 .

IPD 3.3 V

IPD

IPD

IPU

IPD

IPD

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

EMIFA External Address 22 (word address). (O/Z) Enables FAST

BOOT of the device. For details, see

Section 3

.

UHPI Enable Pin. This pin controls the selection (enable/disable) of the HPI and GPIO[0:7] muxed with PCI. For details, see

Section 3 .

EMIFA External Address 16 (word address) (O/Z) HPI peripheral bus width (HPI_WIDTH) select (Applies only when HPI is enabled;

UHPIEN pin = 1)

EMIFA External Address 15 (word address) (O/Z) For proper device operation, this pin must be externally pulled up with a 1-k Ω resistor at device reset.

PCI Frequency Selection (PCI66). The PCI peripheral must be enabled (UHPIEN = 0) to use this function. PCI66_AEA18 selects the PCI operating frequency of 66 MHz or 33 MHz. PCI operating frequency is selected at reset via the pullup/pulldown resistor on the PCI66 pin AEA18:

0 - PCI operates at 33 MHz (default)

1 - PCI operates at 66 MHz.

The BOOTMODE[3:0] defines what boot code is executed on device reset. See

Section 3.2.1

for more details.

SCL

SDA

SGMII0RXN

SGMII0RXP

SGMII0TXN

SGMII0TXP

SGMII1RXN

SGMII1RXP

SGMII1TXN

SGMII1TXP

MDCLK

D22 I/O/Z

C23 I/O/Z

AA10

AA9

W11

Y11

AC9

AB9

W9

W8

U9

I

I

O

O

OZ

I

I

O

O

IPD

INTER-INTEGRATED CIRCUIT (I2C)

3.3 V I2C clock. When the I2C module is used, use an external pullup resistor.

3.3 V I2C data. When I2C is used, make certain there is an external pullup resistor.

SGMII0/1 and MDIO

(1) (2)

1.2 V

1.2 V

1.2 V

1.2 V

Differential SGMII Port 0 RX input (negative)

Differential SGMII Port 0 RX input (positive)

Differential SGMII Port 0 TX output (negative)

Differential SGMII Port 0 TX output (positive)

1.2 V

1.2 V

1.2 V

1.2 V

3.3 V

Differential SGMII Port 1 RX input (negative)

Differential SGMII Port 1 RX input (positive)

Differential SGMII Port 1 TX output (negative)

Differential SGMII Port 1 TX output (positive)

MDIO Serial Clock (MDCLK)

(1) For DM647: Leave the SGMII1RXP/N and SGMII1TXP/N pins disconnected. Disable ENTX/ENRX bits in CFGTX1/CFGRX1 for SGMII1 and still configure the CFGPLL because the SerDes TXBCLK0 is used as the internal VBUS clock. For DM648: if one of the SGMII pair is not used, the same approach must be used.

(2) If the Ethernet Subsystem is not used at all, these connections must be followed:

• Disconnect AA10, AA9, W11,Y11, AC9, AB9, W9, W8, and U9

• Connect AC11 to CV

DD

• Connect AB11 to V

SS

• Directly connect V11 (V

DDA

), W10 (V

DDA

), T10 (V

DDD

), U10 (V

DDD

) , AB8 (V

DDT

), U11 (V

DDT

), R9 (ESS core power), R11 (ESS core power) to CV

DD

• Directly connect AB10, (V

DDR

) to DV

DD18

24

Device Overview





MDIO

VP0CLK0

VP0CLK1

VP0CTL0

VP0CTL1

VP0CTL2

VP0D02

VP0D03

VP0D04

VP0D05

VP0D06

VP0D07

VP0D08

SPICLK

SPICS1/UARTTX

SPICS2/UARTRX

SPIDI/UARTRTS

SPIDO/UARTCTS

T0INP12/GP08

T0OUT12/GP09

T1INPL/GP10

T1OUT12/GP11

AHCLKR

AHCLKX

ACLKR

ACLKX

AFSR

AFSX

AXR0

AXR1

AXR2

AXR3

AXR4

AXR5

AXR6

AXR7

STCLK/AXR8

VDAC/AXR9

AMUTEIN

AMUTE

www.ti.com

TERMINAL NAME

TMS320DM647

TMS320DM648


NO TYPE

1)

(

U8 I/O/Z

F22 I/O/Z

D23 I/O/Z

F23 I/O/Z

G23 I/O/Z

F21 I/O/Z

E20 I/O/Z

D21 I/O/Z

E21 I/O/Z

C22 I/O/Z

AC4 I/O/Z

AC3 I/O/Z

AC6 I/O/Z

AC7 I/O/Z

W6 I/O/Z

AA7 I/O/Z

AB6 I/O/Z

Y6

AA6

AB4

Y5

V7

AA4

V6

Y7 I/O/Z

AA5 I/O/Z

AB3 I/O/Z

U7 I/O/Z

Y23 I

V23 I/O/Z

Y22 I/O/Z

V22 I/O/Z

U23 I/O/Z

W20 I/O/Z

V18 I/O/Z

U18 I/O/Z

V19 I/O/Z

W21 I/O/Z

T18 I/O/Z

U19 I/O/Z


IPU

IPD

IPD

IPD

IPD

IPU

IPU

IPU

IPU

IPD

IPD

IPD

INTERNAL

PULLUP/

PULLDOWN

IPU

OPER

VOLT

DESCRIPTION

IPU

IPU

IPU

IPU

3.3 V MDIO Serial Data (MDIO)

SPI or UART

3.3 V

3.3 V

SPI Clock Output

SPI Chip Select 1 or UART Transmit (O/Z)

3.3 V

3.3 V

SPI Chip Select 2 or UART Receive

SPI Data input or UART Ready to send (O/Z)

IPU 3.3 V SPI Data Output or UART Clear to send

TIMER 0/1 or GPIO[8:11]

3.3 V Timer 0 input pin for lower 32-bit counter (I) or GPIO 8 IPD

IPD

IPD

IPD

3.3 V

3.3 V

3.3 V

Timer 0 output pin for lower 32-bit counter (O/Z) or GPIO 9

Timer 1 input pin for lower 32-bit counter (I) or GPIO 10

Timer 1 output pin for lower 32-bit counter(O/Z) or GPIO 11

IPD

McASP OR VIDEO PORT OR VIC

3.3 V McASP Receive high-frequency master clock

IPD

IPD

3.3 V

3.3 V

McASP Transmit high-frequency master clock

McASP Receive master clock

IPD

IPD

IPD

IPD

IPD

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

McASP Transmit master clock

McASP Receive Frame sync or left/right clock (LRCLK)

McASP Transmit Frame sync or left/right clock (LRCLK)

McASP Data Pin [0:7]

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

The STCLK signal drives the hardware counter for use by the video ports (I) or McASP data pin 8.

VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC) output (O) or McASP data pin 9

McASP Mute Input

McASP Mute Output

VIDEO PORT 0 OR GPIO[12:15]

3.3 V

3.3 V

Video Port 0 Clock 0 (I)

Video Port 0 Clock 1

3.3 V

3.3 V

Video Port 0 Control 0


3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V


Video Port 0 Data 2

Video Port 0 Data 3

Video Port 0 Data 4

Video Port 0 Data 5

Video Port 0 Data 6

Video Port 0 Data 7

Video Port 0 Data 8

Device Overview

25





TMS320DM647

TMS320DM648


TERMINAL NAME

VP0D09

VP0D12/GP12

VP0D13/GP13

VP0D14/GP14

VP0D15/GP15

VP0D16

VP0D17

VP0D18

VP0D19

VP1CLK0

VP1CLK1

VP1CTL0

VP1CTL1

VP1CTL2

VP1D02/GP16

VP1D03/GP17

VP1D04/GP18

VP1D05/GP19

VP1D06/GP20

VP1D07/GP21

VP1D08/GP22

VP1D09/GP23

VP1D12/GP24

VP1D13/GP25

VP1D14/GP26

VP1D15/GP27

VP1D16/GP28

VP1D17/GP29

VP1D18/GP30

VP1D19/GP31

VP2CLK0

VP2CLK1/VCLK

VP2CTL0

VP2CTL1

VP2CTL2/VSCRUN

VP2D02

VP2D03

VP2D04

VP2D05

VP2D06

VP2D07

VP2D08

VP2D09

VP2D12/VRXD0

www.ti.com

P23 I

N23 I/O/Z

R23 I/O/Z

P22 I/O/Z

N22 I/O/Z

R19 I/O/Z

P19 I/O/Z

P18 I/O/Z

R22 I/O/Z

R21 I/O/Z

R20 I/O/Z

N21 I/O/Z

N20 I/O/Z

N19 I/O/Z

P21 I/O/Z

P20 I/O/Z

M20 I/O/Z

M18 I/O/Z

N18 I/O/Z

M21 I/O/Z

M19 I/O/Z

AB1 I

W1 I/O/Z

AA1 I/O/Z

AB2 I/O/Z

Y1 I/O/Z

W5 I/O/Z

AA2 I/O/Z

Y3

U6

I/O/Z

I/O/Z

Y2 I/O/Z

W3 I/O/Z

V5 I/O/Z

W4 I/O/Z

W2 I/O/Z

NO TYPE

1)

(

V20 I/O/Z

V21 I/O/Z

T19 I/O/Z

T20 I/O/Z

T21 I/O/Z

U20 I/O/Z

U22 I/O/Z

U21 I/O/Z

R18 I/O/Z


IPU

IPD

IPD

IPD

IPD

IPU

IPU

IPU

IPU

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

INTERNAL

PULLUP/

PULLDOWN

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

OPER

VOLT

3.3 V

3.3 V

3.3 V

3.3 V

DESCRIPTION

Video Port 0 Data 9

Video Port 0 Data 12 or GPIO 12



3.3 V

3.3 V

3.3 V

3.3 V

3.3 V


Video Port 0 Data 16




VIDEO PORT 1 OR GPIO[16:31]

3.3 V Video Port 1 Clock 0 IPU

IPU

IPU

IPU

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V






IPU

IPD

IPD

IPD

IPD

IPD

IPD

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V






3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V











VIDEO PORT 2 OR VLYNQ

3.3 V

3.3 V

Video Port 2 Clock 0 (I)

Video Port 2 Clock 1 or VLYNQ Clock (I/O)

3.3 V

3.3 V



3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

Video Port 2 Control 2 or VLYNQ serial clock run request (I/O)

Video Port 2 Data 2

Video Port 2 Data 3

Video Port 2 Data 4

Video Port 2 Data 5

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

Video Port 2 Data 6

Video Port 2 Data 7

Video Port 2 Data 8

Video Port 2 Data 9

Video Port 2 Data 12 or VLYNQ receive data pin [0] (I)

26

Device Overview





TMS320DM647


TERMINAL NAME

VP2D13/VRXD1

VP2D14/VRXD2

VP2D15/VRXD3

VP2D16/VTXD0

VP2D17/VTXD1

VP2D18/VTXD2

VP2D19/VTXD3

VP3CLK0/ AECLKIN

VP3CLK1/

AECLKOUT

VP3CTL0/

AAWE/ASWE

VP3CTL1/ AR/W

VP3CTL2/

AAOE/ASOE

VP3D02/AED00

VP3D03/AED01

VP3D04/AED02

VP3D05/AED03

VP3D06/AED04

VP3D07/AED05

VP3D08/AED06

VP3D09/AED07

VP3D12/AED08

VP3D13/AED09

VP3D14/AED10

VP3D15/AED11

VP3D16/AED12

VP3D17/AED13

VP3D18/AED14

VP3D19/AED15

VP4CLK0/AARDY

VP4CLK1

VP4CTL0/ABA0

VP4CTL1/ABA1

T2

R1

P2

R6

R5

R4

R3

R2

P6

P5

T6

T5

T4

T3

P4

P3

N4

N6

N5

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z


NO TYPE

1)

(

U2

U5

U4

V3

V4

U1

U3

T1

P1

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I

I/O/Z


INTERNAL

PULLUP/

PULLDOWN

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

OPER

VOLT

3.3 V

3.3 V

3.3 V

3.3 V

DESCRIPTION




Video Port 2 Data 16 or VLYNQ transmit data pin [0] (O)

3.3 V

3.3 V



3.3 V Video Port 2 Data 19 or VLYNQ transmit data pin [3] (O)

VIDEO PORT 3 OR EMIFA

3.3 V Video Port 3 Clock 0 (I) or EMIFA external input clock (I)

3.3 V Video Port 3 Clock 1 or EMIFA output clock (O/Z)

L1

K1

J2

J1

I

I/O/Z

I/O/Z

I/O/Z

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPD

IPD

IPD

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

Video Port 3 Control 0 or Asynchronous memory write enable/Programmable synchronous interface write-enable

Video Port 3 Control 1 or Asynchronous memory read/write (O/Z)

Video Port 3 Control 2 or Asynchronous/Programmable synchronous memory output-enable (O/Z)

Video Port 3 Data 2 or EMIFA External Data 0











3.3 V

3.3 V

3.3 V

3.3 V

3.3 V






VIDEO PORT 4 OR EMIFA

3.3 V

3.3 V

3.3 V

Video Port 4 Clock 0 (I) or Asynchronous memory ready input (I)


3.3 V

Video Port 4 Control 0 or EMIFA bank address control (ABA[1:0])

(O/Z). Active-low bank selects for the 16-bit EMIFA. When interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of the byte address. For an 8-bit asynchronous interface, ABA[1:0] are used to carry bits 1 and 0 of the byte address.

Video Port 4 Control 1 or EMIFA bank address control (ABA[1:0])

(O/Z). Active-low bank selects for the 16-bit EMIFA. WHEN interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of the byte address. For an 8-bit asynchronous interface, ABA[1:0] are used to carry bits 1 and 0 of the byte address.





Device Overview

27

TMS320DM647

TMS320DM648


www.ti.com

TERMINAL NAME

VP4CTL2/ ASADS/

ASRE

VP4D02/ ABE00

VP4D03/ABE01

VP4D04/AEA10

VP4D05

VP4D06/ACE2

VP4D07/ACE3

VP4D08/AEA00

VP4D09/AEA01

VP4D12/AEA02

VP4D13/AEA03

VP4D14/AEA04

VP4D15/AEA05

VP4D16/AEA06

VP4D17/AEA07

VP4D18/AEA08

VP4D19/AEA09

NO TYPE

1)

(

K2

L2

M4

M5

M6

L3

L4

L5

K3

K4

L6

K5

J3

J4

J5

J6

K6

AEA23

AEA19

H4

H5

AECLKINSEL/AEA17 G4

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

I/O/Z

OZ

O/Z

I/O/Z


INTERNAL

PULLUP/

PULLDOWN

IPD

OPER DESCRIPTION

VOLT

IPU

IPU

IPU

IPU

IPU

IPU

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPD

IPU

IPD

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

Video Port 4 Control 2 or Programmable synchronous address strobe or read-enable. For programmable synchronous interface, the r_enable field in the ChipSelect x Configuration Register selects between ASADS and ASRE:

– If r_enable = 0, then the ASADS/ASRE signal functions as the

ASADS signal.

– If r_enable = 1, then the ASADS/ASRE signal functions as the

ASRE signal.

Video Port 4 Data 2 or EMIFA byte-enable control 0. Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory.

Byte-write enables for most types of memory.

Video Port 4 Data 3 or EMIFA byte-enable control 1. Number of address bits or byte enables used depends on the width of external memory. Byte-write enables for most types of memory.

Video Port 4 Data 4 or EMIFA External Address 10 (word address)

(O/Z)

Video Port 4 Data 5

Video Port 4 Data 6 or EMIFA memory space enable 2

Video Port 4 Data 7 or EMIFA memory space enable 3


(O/Z)


(O/Z)


(O/Z)


(O/Z)


(O/Z)


(O/Z)


(O/Z)


(O/Z)

3.3 V

3.3 V


(O/Z)


(O/Z)

EMIFA

3.3 V EMIFA External Address 23 (word address) (O/Z)

3.3 V

3.3 V

EMIFA External Address 19 (word address) (O/Z)

Select EMIFA external clock (I) (The EMIFA input clock AECLKIN or SYSCLK4 is selected at reset via the pullup/pulldown resistor on this pin. Note: AECLKIN is the default for the EMIFA input clock.) or EMIFA external address 17 (word address) (O/Z)

28

Device Overview





TMS320DM647


TERMINAL

NAME

NO

K11

K13

K15

K17

L8

J12

J14

J16

K7

K9

L10

L12

L14

L16

M7

M9

H13

H15

H17

J8

J10

G16

G18

G22

H1

H11

F19

G8

G10

G12

G14

E6

E23

F7

F15

F17

A1

A5

A15

A18

A23

C4

D9

D12

D20

Table 2-5. Terminal Functions (Ground and Power Supply)

TYPE

(1)

INTERNAL

PULLUP/

PULLDOWN

OPER

VOLT

DESCRIPTION

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal





Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground


Device Overview

29

TMS320DM647

TMS320DM648


www.ti.com

30

TERMINAL

NAME

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

Device Overview

Table 2-5. Terminal Functions (Ground and Power Supply) (continued)

NO TYPE

(1)

INTERNAL

PULLUP/

PULLDOWN

OPER

VOLT

DESCRIPTION

Y10

AA3

AA8

AA11

AB5

V9

V17

W7

W22

Y9

AB19

AB23

AC1

AC8

AC10

T17

T22

U14

U16

V1

T7

T9

T11

T13

T15

P17

R10

R12

R14

R16

P7

P9

P11

P13

P15

M11

M13

M15

M17

M22

N1

N8

N10

N12

N14

N16

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground





www.ti.com

TERMINAL

NAME

V

SS

V

SS

CV

DD1

AV

DDA

AV

DDA

DV

DDD

DV

DDD

AV

DDR

AV

DDT

AV

DDT

DV

DD33

DV

DD33

DV

DD33

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DDESS

CV

DDESS

AV

DLL1

AV

DLL2

CV

DD1


NO

AC12

AC16

P14

R13

N9

T16

R8

N11

N13

N15

P10

P12

R15

V8

R11

R9

B10

B22

H9

L9

L11

L13

L15

M10

M12

M14

J9

J11

J15

K10

K12

K14

J13

V11

W10

T10

U10

AB10

AB8

U11

E22

F20

G1

TYPE

(1)

INTERNAL

PULLUP/

PULLDOWN

OPER

VOLT

DESCRIPTION





TMS320DM647

TMS320DM648


Ground

Ground

POWER PINS

1.2-V Core Power Supply

























1.2-V Core Power Supply for Ethernet Subsystem

1.2-V Core Power Supply for Ethernet Subsystem

1.8-V I/O supply

1.8-V I/O supply

1.2-V Power supply for DDR, DDR I/Os, EMIF-DDR

Subsystem

1.2-V Power supply for DDR, DDR I/Os, EMIF-DDR

Subsystem

1.2-V SerDes Analog supply

1.2-V SerDes Analog supply

1.2-V SerDes Digital Supply

1.2-V SerDes Digital Supply

1.8-V SerDes Analog Supply (Regulator)

1.2-V SerDes Analog Supply

1.2-V SerDes Analog Supply

3.3-V I/O supply voltage



Device Overview

31

TMS320DM647

TMS320DM648


www.ti.com

32

TERMINAL

NAME

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

DV

DD33

Device Overview


NO TYPE

(1)

INTERNAL

PULLUP/

PULLDOWN

OPER

VOLT

DESCRIPTION

AB16

AC2

AC5

AB12

AC19

AC23

B1

B5

B15

B18

B23

C3

C10

C13

C21

V2

V16

W23

Y4

Y8

T14

T23

AB7

U15

U17

P16

R7

R17

T8

T12

M23

N2

N7

N17

P8

G19

J7

H16

H22

J17

K8

K16

L7

L17

M8

M16






































1.8-V I/O supply voltage (DDR2 Memory Controller)













TMS320DM647



TERMINAL

NAME

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DV

DD18

DDR_VREF

V

CCMON

V

DD18MON

V

DD33MON

RSV 1

RSV 2

RSV 3

RSV 4

RSV 5

RSV 6

RSV 7

RSV 8

RSV 9

RSV 10

RSV 11

RSV 12

RSV 13

RSV 14

L20

L21

D2

D1

D4

D3

H7


NO TYPE

(1)

INTERNAL

PULLUP/

PULLDOWN

OPER

VOLT

DESCRIPTION

E5

F8

F14

F16

F18

G9

G11

G13

G15

G17

H10

H12

H14

C11

L19

B2

G21














(DV

DD18

/2)-V reference for SSTL buffer (DDR2 Memory

Controller0. This input voltage cn be generated directly from

DV

DD18 circuit.

using two 1-K Ω resistors to form a resister divider

Die-side 1.2-V core supply voltage monitor pin. The monitor pins indicate the voltage on the die, and, therefore, provide the best probe point for voltage monitoring purposes. If the V

CCMON pin is not used, it should be connected directly to the 1.2-V core supply or left unconnected.

Die-side 1.8-V I/O supply voltage monitor pin. The monitor pins indicate the voltage on the die and, therefore, provide the best probe point for voltage monitoring purposes. If the V

DD18MON pin is not used, it should be connected directly to the 1.8-V I/O supply (DV

DD18

).

Die-side 3.3-V I/O supply voltage monitor pin. The monitor pins indicate the voltage on the die and, therefore, provide the best probe point for voltage monitoring purposes. If the V

DD33MON pin is not used, it should be connected directly to the 3.3-V I/O supply (DV

DD33

).

Reserved

H8

M2

A2

E2

E1

E4

E3

A

A

O

O

A

A

A

O

O

A

Reserved. Unconnected






Reserved. These pins must be connected directly to V

SS proper device operation.

for

Reserved. These pins must be connected directly to V

SS proper device operation.

for



Reserved This pin must be connected directly to V

SS device operation.

for proper

Reserved. This pin must be connected directly to 1.8-V I/O supply

Reserved This pin must be connected directly to V

SS device operation.

for proper

Reserved. This pin must be connected directly to 1.8-V I/O supply

Device Overview

33





TMS320DM647

TMS320DM648


TERMINAL

NAME

RSV 15

RSV 16

RSV 17

RSV 18

RSV 19

RSV 20

RSV 21

RSV 22

www.ti.com


NO TYPE

(1)

INTERNAL

PULLUP/

PULLDOWN

OPER

VOLT

DESCRIPTION

A10

A22

V10

F6

C2

C1

Y12

W12

A

A

A

I




Reserved. These pins must be connected directly to 1.8-V I/O supply(DV

DD18

) for proper device operation.

Reserved. This pin must be connected to the 1.8-V I/O supply

(DV

DD18

) via a 200Ω resistor for proper device operation.

NOTE: If the DDR2 Memory Controller is not used, the

DDR_VREF, RSV19, and RSV20 pins can be directly connected to ground (V

SS

) to save power. However, connecting these pins directly to ground will prevent boundary scan from functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2 Memory

Controller pins, see

Section 6.3.6

.

Reserved. This pin must be connected to ground (V

SS

) via a

200Ω resistor for proper device operation.

NOTE: If the DDR2 Memory Controller is not used, the RSV 19 and RSV 20 pins can be directly connected to ground (V

SS

) to save power. However, connecting these pins directly to ground will prevent boundary scan from functioning on the DDR2

Memory Controller pins. To preserve boundary-scan functionality on the DDR2 Memory Controller pins, see

Section 6.3.6

.

Reserved. This pin must be connected via a 20Ω resistor directly to 3.3-V I/O Supply (DV

DD33

) for proper device operation. The resistor used should have a minimal rating of

250 mW.

Reserved. This pin must be connected via a 40Ω resistor directly to ground (V

SS

) for proper device operation. The resistor used should have a minimal rating of 100 mW.

2.7

Device Support

2.7.1

Development Support

TI offers an extensive line of development tools for the TMS320DM64x DMP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tools support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE).

The following products support development of TMS320DM64xx DMP-based applications:

Software Development Tools:

Code Composer Studio™ Integrated Development Environment (IDE): including Editor

C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software needed to support any SoC application.

Hardware Development Tools:

Extended Development System (XDS™) Emulator (supports TMS320DM64x multiprocessor system debug) EVM (Evaluation Module)

For a complete listing of development-support tools for the TMS320DM64x platform, visit the Texas

Instruments website at www.ti.com

. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

34

Device Overview





TMS320DM647



2.7.2

Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,

TMP, or TMS (e.g., TMS320DM648ZUTA7). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

Experimental device that is not necessarily representative of the final device's electrical specifications.

TMP

TMS

Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification.

Fully-qualified production device.

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS

Fully qualified development-support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZUT), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, "Blank" is the default [720-

MHz]).

Figure 2-6

provides a legend for reading the complete device name for the devices.

ZUT

( ) (7)

TMS 320 DM648

PREFIX

TMX = Experimental device

TMS = Qualified device

DEVICE SPEED RANGE

7

8

= 720 MHz

= 800 MHZ

9

1

= 900 MHZ

= 1.1 GHz

DEVICE FAMILY

320 = TMS320 DSP family

DEVICE

C64x+ DSP

DM647

DM648

TEMPERATURE RANGE

Blank

A

D

= -40° C to 90° C, Industrial Temperature (720, 900, 1100)

PACKAGE TYPE

ZUT = 520-pin plastic ball grid array (BGA)

Figure 2-6. Device Nomenclature

Device Overview

35





TMS320DM647

TMS320DM648


www.ti.com

2.7.3

Related Documentation From Texas Instruments

The following documents describe the devices. Copies of these documents are available on the Internet at www.ti.com

. Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DM64x DMP, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .

SPRU732

TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

SPRUEK5

TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide describes the DDR2 memory controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The

DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant

DDR2 SDRAM devices and standard Mobile DDR SDRAM devices.

SPRUEK6

TMS320DM647/DM648 DSP External Memory Interface (EMIF) User's Guide describes the operation of the asynchronous external memory interface (EMIF) in the

TMS320DM647/DM648 Digital Signal Processor (DSP). The EMIF supports a glueless interface to a variety of external devices.

SPRUEK7

TMS320DM647/DM648 DSP General-Purpose Input/Output (GPIO) User's Guide

describes the general-purpose input/output (GPIO) peripheral in the TMS320DM647/DM648

Digital Signal Processor (DSP). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of the input by reading the state of an internal register. When configured as an output, you can write to an internal register to control the state driven on the output pin.

SPRUEK8

TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital Signal

Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus.

External components attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and from the DSP through the I2C peripheral. This document assumes the reader is familiar with the I2C-bus specification.

SPRUEL0

TMS320DM647/DM648 DSP 64-Bit Timer User's Guide describes the operation of the 64bit timer in the TMS320DM647/DM648 Digital Signal Processor (DSP). The timer can be configured as a general-purpose 64-bit timer or dual general-purpose 32-bit timers.

SPRUEL1

TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guide

describes the multichannel audio serial port (McASP) in the TMS320DM647/DM648 Digital

Signal Processor (DSP). The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for timedivision multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).

SPRUEL2

TMS320DM647/DM648 DSP Enhanced DMA (EDMA) Controller User's Guide describes the operation of the enhanced direct memory access (EDMA3) controller in the

TMS320DM647/DM648 Digital Signal Processor (DSP). The EDMA3 controller’s primary purpose is to service user-programmed data transfers between two memory-mapped slave endpoints on the DSP.

SPRUEL4

TMS320DM647/DM648 DSP Peripheral Component Interconnect (PCI) User's Guide

describes the peripheral component interconnect (PCI) port in the TMS320DM647/DM648

Digital Signal Processor (DSP). The PCI port supports connection of the C642x DSP to a

36

Device Overview





TMS320DM647



PCI host via the integrated PCI master/slave bus interface. The PCI port interfaces to the

DSP via the enhanced DMA (EDMA) controller. This architecture allows for both PCI master and slave transactions, while keeping the EDMA channel resources available for other applications.

SPRUEL5

TMS320DM647/DM648 DSP Host Port Interface (UHPI) User's Guide describes the host port interface (HPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The HPI is a parallel port through which a host processor can directly access the CPU memory space.

The host device functions as a master to the interface, which increases ease of access. The host and CPU can exchange information via internal or external memory. The host also has direct access to memory-mapped peripherals. Connectivity to the CPU memory space is provided through the enhanced direct memory access (EDMA) controller.

SPRUEL8

TMS320DM647/DM648 DSP Universal Asynchronous Receiver/Transmitter (UART)

User's Guide describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP). The UART peripheral performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data received from the CPU.

SPRUEL9

TMS320DM647/DM648 DSP VLYNQ Port User's Guide describes the VLYNQ port in the

TMS320DM647/DM648 Digital Signal Processor (DSP). The VLYNQ port is a high-speed point-to-point serial interface for connecting to host processors and other VLYNQ compatible devices. It is a full-duplex serial bus where transmit and receive operations occur separately and simultaneously without interference.

SPRUEM1

TMS320DM647/DM648 DSP Video Port/VCXO Interpolated Control (VIC) Port User's

Guide discusses the video port and VCXO interpolated control (VIC) port in the

TMS320DM647/DM648 Digital Signal Processor (DSP). The video port can operate as a video capture port, video display port, or transport channel interface (TCI) capture port. The

VIC port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. When the video port is used in TCI mode, the VIC port is used to control the system clock, VCXO, for MPEG transport channel.

SPRUEM2

TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial

Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This reference guide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-length shift register, used for high speed communication between external peripherals or other DSPs.

SPRUEU6

TMS320DM647/DM648 DSP Subsystem User's Guide describes the subsystem in the

TMS320DM647/DM648 Digital Signal Processor (DSP). The subsystem is responsible for performing digital signal processing for digital media applications. The subsystem acts as the overall system controller, responsible for handling many system functions such as systemlevel initialization, configuration, user interface, user command execution, connectivity functions, and overall system control.

SPRUF57

TMS320DM647/DM648 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide

describes the operation of the 3 port switch (3PSW) ethernet subsystem in the

TMS320DM647/DM648 Digital Signal Processor (DSP). The 3 port switch gigabit ethernet subsystem provides ethernet packet communication and can be configured as an ethernet switch (DM648 only). It provides the serial gigabit media independent interface (SGMII), the management data input output (MDIO) for physical layer device (PHY) management.





Device Overview

37

TMS320DM647

TMS320DM648


3 Device Configuration

www.ti.com

3.1

System Module Registers

The system module includes status and control registers required for configuration of the device. Brief descriptions of the various registers are shown in

Table 3-1

. System Module registers required for device configuration are described in the following sections.

Table 3-1. System Module Register Memory Map


0x0204 9000

0x0204 9004

0x0204 9008

0x0204 900C

0x0204 9010

0x0204 9014

0x0204 9018

0x0204 901C

0x0204 9020 -0x0204 9053

0x0204 9054

0x0204 9060 - 0x0204 90A7

0x0204 90A8

0x0204 90AC

0x0204 90B0

0x0204 90B4

0x0204 90B8

0x0204 90BC

0x0204 90C0

0x0204 90C4

0x0204 90C8

0x0204 90CC

0x0204 90D0

0x0204 90D4

REGISTER NAME

PINMUX

Reserved

DSPBOOTADDR

BOOTCMPLT

BOOTCFG

JTAGID

PRI_ALLOC

Reserved

KEY_REG

Reserved

CFGPLL

Reserved

CFGRX0

CFGRX1

CFGTX0

CFGTX1

Reserved

MAC_ADDR_R0

MAC_ADDR_R1

MAC_ADDR_RW0

MAC_ADDR_RW0

ESS_LOCK

DESCRIPTION

Pin multiplexing control 0

Reserved

Boot Address of DSP, decoded by bootloader software for host boots

Boot Complete

Reserved

Device boot configuration

Device ID number. See

Section 6.25

for details.

Bus master priority control. See

Section 4

for details

Reserved

Key Register to protect against accidental writes.

Reserved

CFGPLL inputs for SerDes

Reserved

Configure SGMII0 RX

(1)

Configure SGMII1 RX

(1)

Configure SGMII0 TX.

(1)

Configure SGMII1 TX

(1)

Reserved

MAC Address Read Only Register 0

MAC Address Read Only Register 1

MAC Address Read/Write Register 0

MAC Address Read/Write Register 1

Ethernet Sub System Lock Register

(1) See the TMS320DM647/DM648 DSP Ethernet Subsystem User's Guide Reference Guide (literature number SPRUF57 ) for details.

38

Device Configuration





TMS320DM647



3.2

Bootmode Registers

The BOOTCFG and DSPBOOTADDR registers are described in the following sections. At reset, the status levels of various pins required for proper boot are stored within these registers.

3.2.1

Boot Configuration (BOOTCFG) Register

Configuration pins latched at reset are presented in the BOOTCFG register accessible through the system module. This is a read-only register. The bits show the true latched value of the corresponding input at

RESET or POR deassertion. This is desirable since the most important use of this MMR is for the user to debug/view the actual value driven on the pins during device reset.

Figure 3-1. BOOTCFG Register

31

23

AECLKINSEL

22

PC166

21

HPIWIDTH

R-L

20

Reserved

Reserved

R-0

19

FASTBOOT

R-L

15

7 4

Reserved

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Reserved

R-0

3

18

Reserved

17

DUHPIEN

R-L

BOOTMODE

R-L

24

16

EMIFAWIDTH

R-L

8

0

Bit Field

31:24 Reserved

23 AECLKINSEL

22

21

20

19

18

17

16

PCI66

HPIWIDTH

Reserved

FASTBOOT

Reserved

DUHPIEN

EMIFAWIDTH

15:4 Reserved

Table 3-2. BOOTCFG Register Field Descriptions

Value Description

Reserved

1

0

0

1

Controls the clock input for EMIFA. Latched from AECLKINSEL at RESET or POR deassertion

EMIFA clocked from internal SYSCLK

EMIFA clocked from outside from AECLKIN

Controls PCI speed. PCI. Latched from PCI66 at RESET or POR deassertion

33 MHz PCI

66 MHz

Controls HPI bus width. Latched from HPIWIDTH at RESET or POR deassertion

16 bit 0

1

1

32 bit

Reserved

0

1

Fast Boot. Latched from FASTBOOT at RESET or POR deassertion

No Fast Boot

Fast Boot

Reserved

PCI Enable Default. Latched from UHPIEN at RESET or POR deassertion

0

1

0

1

UHPI disabled

UHPI enabled

EMIFA CS2 Bus Width Default. Latched from EMIFAWIDTH at RESET or POR deassertion

8-bit

16-bit

Reserved






39

TMS320DM647

TMS320DM648


Bit

3:0

Field

BOOTMODE

Table 3-2. BOOTCFG Register Field Descriptions (continued)


Boot Mode. Latched from Bootmode at RESET or POR deassertion

www.ti.com

Table 3-3. Boot Modes

DEVICE BOOT AND

CONFIGURATION PINS

BOOTMODE[3:0] UHPIEN FASTBOOT

0000

0001

0 or 1

0

1

0 or 1

1

0 or 1

0010

0011

0

1

0 or 1

0100

0101

0110

0111

1000

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

1

0 or 1

0

0

1

0 or 1

0 or 1

0 or 1

0 or 1

1001

1010

1011

1100

1101

1110

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

0

BOOT DESCRIPTION

(1) (2)

No boot (emulation boot)

PCI boot no auto-initialization

HPI boot

PCI boot with auto-initialization

HPI boot

UART boot with no hardware flow control

EMIFA ROM direct boot (PLL bypass mode)

EMIFA ROM AIS boot

I2C Boot (standard mode)

SPI boot

Reserved

SGMII0 - Boot port, no packet forwarding

SGMII0 - Boot port, SGMII1 packet forwarding (reserved in DM647)

SGMII1 - Boot port, SGMII0 packet forwarding (reserved in DM647)

Reserved

Reserved

Reserved

UART Boot with hardware flow control

[UART0]

Reserved

DM647, DM648

(MASTER/SLAVE)

-

Slave

Slave

Slave

Slave

Slave

Master

Master

Master

Master

-

Slave

Slave

Slave

-

-

-

Slave

DSPBOOTADDR

(DEFAULT)

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

0xA000 0000

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

0x0080 0000

1111 0 or 1 0 or 1 0x0080 0000

(1) In all bootmodes other than EMIFA ROM Direct Boot (BOOTMODE[3:0] = 0100b, UHPIEN = 0b or 1b, FASTBOOT = 0b) all C64x+ cache is disabled (L1P,L1D,L2).

(2) For details of the boot process, see Using the TMS320DM647 Bootloader Application Report (literature number SPRAAJ1 ).

3.2.2

DSPBOOTADDR Register Description

The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register format is shown in

Figure 3-2

and bit field descriptions are shown in

Table 3-4 . DSPBOOTADDR is

readable and writable by software after reset. DSPBOOTADDR Decode: This decode logic determines the default of the DSPBOOTADDR Register. It can default to the base address of L2 ROM (0x00800000) or the base address of EMIFA CS2 (0xA0000000).

Figure 3-2. DSPBOOTADDR Register

10 9 31

BOOTADDR

R/W-0100 0010 0010 0000 0000 00


Reserved

R-0

0

Bit Field

31:10 BOOTADDR

9:0 Reserved

Table 3-4. DSPBOOTADDR Register Field Descriptions


Upper 22 bits of the C64x+ DSP bootmode address

Reserved

40






TMS320DM647



3.2.3

Boot Complete (BOOTCMPLT) register

The BOOTCMPLT register contains a BC (boot complete) field in bit 0, and a ERR (boot error) field in bits

19:16.

The BC field is written by the external host to indicates that it has completed boot. In the bootloader code, the CPU can poll for this bit. Once this bit = 1, the CPU can begin executing from DSPBOOTADDR.

The ERR field is written by the bootloader software if the software detects a boot error. Coming out of a boot, application software can read this field to determine if boot was accomplished. Actual error code is determined by software.

Figure 3-3. BOOTCMPLT Register 3

31

Reserved

R-0

15

Reserved

R-0


20 19

ERR

R-0

1

16

0

BC

R-0

Bit Field

31:20 Reserved

19:16 ERR

15:1 Reserved

0 BC

Table 3-5. BOOTCMPLT Register Field Descriptions


Reserved

0000

Boot error

No error

0001 – 1111 Bootloader software detected boot error. For details on boot errors, see the Using the

TMS320DM647/DM648 Bootloader Application Report (literature number SPRAAJ1 ).

0

1

Reserved

Boot Complete Flag from host. This is applicable only to host boots.

Host has not completed booting this device.

Host has completed booting this device and the DSP can begin executing from

DSPBOOTADDR.






41

TMS320DM647

TMS320DM648


www.ti.com

3.2.4

Priority Allocation (PRI_ALLOC)

Each of the masters (excluding the C64x+ Megamodule) is assigned a priority via the Priority Allocation

Register (PRI_ALLOC), see

Figure 3-4 . The priority is enforced when several masters in the system are

vying for the same endpoint. A value of 000b has the highest priority, while 111b has the lowest priority.

Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the

C64x+ Megamodule.

The Ethernet Subsystem and VLYNQ fields specify the priority of the Ethernet Subsystem and VLYNQ peripherals, respectively. Similarly, the HOST field applies to the priority of the HPI and PCI peripherals.

Other master peripherals are not present in the PRI_ALLOC register as they have their own registers to program their priorities. For more information on the default priority values in these peripheral registers, see the device-compatible peripheral reference guides.

TI recommends that these priority registers be reprogrammed during device initialization.

MASTER

EDMA3TC0

EDMA3TC1

EDMA3TC2

EDMA3TC3

64x+_DMAP

64x+_CFGP

Ethernet Subsystem

VLYNQ

UHPI

PCI

VICP

Table 3-6. Default Master Priorities

DEFAULT PRIORITY

0 (EDMA CC QUEPRI Register)




7 (C64x+ MDMAARBE.PRI Register bit field)

1 (C64x+ MDMAARBE.PRI Register bit field)

3 (PRI_ALLOC register)





Figure 3-4. Priority Allocation Register (PRI_ALLOC)

31

Reserved

R-0000000000001000

15 12 11 9 8

Reserved

R-0000

VICP

R/W-101


VLYNQ

R/W-100

6 5

HOST

R/W-100

3

16

2 0

Ethernet Subsystem

R/W-011

42






TMS320DM647



3.2.5

KEY_REG (write protection)

KEY_REG protects against accidental writes to certain system configuration registers. The complete set of registers protected by the KEY_REG is:

• PINMUX

• BOOTCFG

• PRI_ALLOC

• CFGPLL

• CFGRX0

• CFGTX0

• CFGRX1

• CFGTX1

• MAC_ADDR_RW0

• MAC_ADDR_RW1

Writes to these registers are locked/blocked by default. To enable writes to these registers, write

0xADDDECAF to the KEY_REG. After enabling writes to protected registers by doing the above, the register writes should occur within 10000 CPU/6 cycles, after which the key will be reset.

Figure 3-5. KEY_REG

31

KEY_REG

W-0x00000000


0






43

TMS320DM647

TMS320DM648


www.ti.com

3.2.6

PINMUX Register

All pin multiplexing options are controlled by software via PINMUX register (except the ones mentioned in

Table 3-8 , whose default is selected by configuration pins). This PINMUX register reside within the system

module portion of the CFG bus memory map. The format of the registers and a description of the pins they control are in the following sections.

The PINMUX Register controls all the software-controlled pin muxing. The register format is shown in

Figure 3-6 . A brief description of each field is shown in Table 3-7 .

Figure 3-6. PINMUX Register

22 31

15 14 13 12

Reserved

R-0000 0000 00

11 10 9 8

VP34_EN SPI_UART_EN Reserved MCASP_EN

R/W-00 R/W-00 R-00 R/W-00


7

Reserved

R-00

6

21 20

GPIO_EN

R/W-00

5 4

VLYNQ_EN

R/W-00

19 18

Reserved

R-00

3

Reserved

R-000

17

VPI_EN

16

R/W-00

1 0

TIMER

_EN

R/W-0

Bit Field

31:22 Reserved

21:20 GPIO_EN

19:18 Reserved

17:16 VP1_EN

Table 3-7. PINMUX Register Field Descriptions


Reserved

00

01

10

11

Controls the pin muxing between Video Port 0 and the GPIO[12:15]

UNMUXED

(1)

UNMUXED

(2)

SECONDARY MUXED

(3)

.VP0D16-19

3-state

3-state

VP0D02-09/CLK/CTL

3-state

3-state

VP0D12-15

3-state

3-state

GP12-15

Enable

3-state

Enable

Enable

VP0D12-15

GP12-15

00

01

10

11

Reserved

Controls the pin muxing between Video Port 1 and GPIO[16:31]

UNMUXED

(4)

VP1CLK0-

1/VP1CTL0-2

3-state

MUXED

(5)

VP1 Data

(V1D02-09/12-19)

3-state

3-state

3-state

Enable

GP[16-31]

3-state

GP16-31

VP1D02-09 and VP1D12-19

(1) The complete list of pins: U20, U21, U22, R18.

(2) The complete list of pins: Y23, V23, Y22, V22, U23, W20, V18, U18, V19, W21, T18, U19, V20.

(3) The complete list of pins: V21, T19, T20, T21.

(4) The complete list of pins: P23, N23, R23, P22, N22

(5) The complete list of pins: R19, P19, P18, R22, R21, R20, N21, N20, N19, P21, P20, M20, M18, N18, M21, M19

44






TMS320DM647


Bit Field

15:14 VP34_EN

13:12 SPI_UART_EN

11:10 Reserved


Table 3-7. PINMUX Register Field Descriptions (continued)


Controls the pin muxing between Video Port 3-4 and EMIFA

(6)

UNMUXED

(7)

00

01

10

11

VP4D05/VP4CLK1

3-state

3-state

Disable

Enable

VP3/VP4

00

01

10

11

Controls the pin muxing between SPI and UART

UNMUXED

(9)

SPICLK

3-state

Enable

Disable

Enable

MUXED

3-state

3-state

EMIFA

(8)

VP3/VP4

MUXED

(10)

SPI or UART

3-state

SPI

UART

SPIDI

SPIDO

UART_TX

UART_RX

Reserved

EMIFA

(6) The value of VP34_EN depends on the BOOTMODE[3:0] pin value at reset. If the BOOTMODE[3:0] is 0100, the VP3/4 and the EMIFA mux defaults to EMIFA enable (the value is 10b).

(7) The complete list of pins: K1, M6.

(8) The complete list of pins: T1, P1, T2, R1, P2, T6, T5, T4, T3, R6, R5, R4, R3, R2, P6, P5, P4, P3, N4, N6, N5, L1, J2, J1, K2, L2, M4,

M5, L3, L4, L5, K3, K4, L6, K5, J3, J4, J5, J6, K6.

(9) The complete list of pin:F22

(10) The complete list of pins: D23, F23, G23, F21


45





TMS320DM647

TMS320DM648


www.ti.com

Table 3-7. PINMUX Register Field Descriptions (continued)

Bit

9:8

7:6

5:4

3:1

0

Field

MCASP_EN

Reserved

VLYNQ_EN

Reserved

TIMER_EN


Controls the pin muxing between McASP and VIC

UNMUXED

00

01

10

11

00

01

10

11

0

1

MUXED

(11)

STCLK, VCTL, or McASP

3-state

McASP (all McASP Pins)

(McASP without AXR8, AXR9)

ACLKR

AFSR

AXR0

AXR1

AC:LKX

AFSX

AXR2

AXR3

AHCLKR

AMUTEIN

AXR4

AXR5

AHCLKX

AMUTE

AXR6

AXR7

STCLK

VCTL

Reserved

Reserved

Controls the pin muxing between Video Port 2 and VLYNQ

UNMUXED

(12)

VP2#1

3-state

MUXED

(13)

VP2#2 VLYNQ

3-state

3-state

Enable

Enable

Reserved

Controls the pin muxing between TIMER and GPIO[8:11]

3-state

VP2D12-19, VP2CLK1, VP2CTL2

VRXD0-3 and VTXD0-3, VCLK, VSCRUN

MUXED

(14)

GPIO[8:11]

Timer 0/1

(11) The complete list of pins: AC4, AC3, AC6, AC7, W6, AA7, AB6, Y6, AA6, AB4, Y5, V7, AA4, V6, Y7, AA5, AB3, U7

(12) For the first half of the Video Port 2, the complete list of pins with function: AB1(VP2CLK0), AA1 (VP2CTL0), AB2 (VP2CTL1) and W5,

AA2, Y3, U6, Y2, W3, V5, W4 (VP2D02, VP2D03, VP2D04, VP2D05, VP2D06, VP2D07, VP2D08, VP2D09)

(13) For the second half of the Video Port 2, the complete list of pins with function: W1 (VP2CLK1/VCLK), Y1(VP2CTL2/VSCRUN), W2, V3,

V4, U1, U3, U2, U5, U4 (VP2D12/VRXD0, VP2D13/VRXD1, VP2D14/VRXD2, VP2D15/VRXD3, VP2D16/VTXD0, VP2D17/VTXD1,

VP2D18/VTXD2, VP2D19/VTXD3)

(14) The complete list of pins:E20, D21, E21, C22

46






TMS320DM647

TMS320DM648


www.ti.com

Table 3-8. PCI/UHPI/GPIO Block: PCI MUXed With UHPI and GPIO[0:7]

MUXED

(1)

PCI UHPI/GPIO[0:7]

UHPIEN (pin)

1

0

UHPI/GPIO[0:7]

PCI

(1) The complete list of pin:AA22, AB22, AC21, AA23, AC22, AB21, AA21, Y21, AB20, AA20, Y20, Y19, AB18, AA19, AC18, AA18, Y16,

AB15, AA15, Y15, W15, V15, AC14, AB14, W14, V14, AC13, AB13, AA13, Y13 , W13, V13, W19, Y18, Y17, W17, W18, AC20, AC17,

W16, Y14, AC15, AA16, AB17, U13, U12, V12, AA12, AA17, AA14.

For information on the Ethernet Subsystem registers, see the TMS320DM647/DM648 DSP Subsystem

Reference Guide (literature number SPRUEU6 ).

3.2.7

MAC Address Registers

• MAC_ADDR_R0

• MAC_ADDR_R1

• MAC_ADDR_RW0

• MAC_ADDR_RW1

Two sets of registers provide default MAC addresses for the device. One set - MAC_ADDR_R0 and

MAC_ADDR_R1 - is read only and the other set - MAC_ADDR_RW0 and MAC_ADDR_RW1 - includes read and write registers.

Figure 3-7. MAC_ADDR_R0 Register

31

MAC_ID

R-MAC ADDRESS[31:0]


0

Bit Field

31:0 MAC_ID

Table 3-9. MAC_ADDR_R0 Register Field Descriptions

Value

Mac

Address[31:0] of the device

Description

Bit 0 of MAC_ID is bit 0 of MAC Address

Figure 3-8. MAC_ADDR_R1 Register

31 24 23

CRC

R-CRC for the MAC_ID

15

MAC_ID

R-MAC ADDRESS[47:32]


Reserved

R-00000000

Bit Field

31:24 CRC

23:16 Reserved

Table 3-10. MAC_ADDR_R1 Register Field Descriptions


CRC of the MAC This field will hold the CRC of the MAC address of that particular device.

ID

0x00 Reserved

16

0


47





TMS320DM647

TMS320DM648


Bit Field

15:0 MAC_ID

Table 3-10. MAC_ADDR_R1 Register Field Descriptions (continued)

Value

Mac


Description

Bit 0 of MAC_ID is Bit 32 of MAC Address

Figure 3-9. MAC_ADDR_RW0 Register

31

MAC_ADDR_R0

R/W - MAC ID[31:0]


Bit Field

31:0 MAC_ID

Table 3-11. MAC_ADDR_RW0 Register Field Descriptions

Value

Mac


Description

Bit 0 of MAC_ID is bit 0 of MAC Address

Figure 3-10. MAC_ADDR_RW1 Register

31 24 23

CRC

R/W-CRC for the MAC_ID

15

MAC_ID

R-MAC ADDRESS[47:32]


Reserved

R/W-00000000

Bit Field

31:24 CRC

23:16 Reserved

15:0 MAC_ID

Table 3-12. MAC_ADDR_RW1 Register Field Descriptions

Value

0x00

Description

CRC of the This field will hold the CRC of the MAC address of that particular device.

MAC ID

Reserved

Bit 0 of MAC_ID is Bit 32 of MAC Address Mac


www.ti.com

16

0

0

48






TMS320DM647



3.3

Pullup/Pulldown Resistors

Proper board design should specify that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor must be used in the following situations:

• Boot and Configuration Pins: If the pin is both routed out and in high-impedance mode, an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.

• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.

If the boot and configuration pins are both routed out and in high-impedance mode, it is recommended that an external pullup/pulldown resistor be used. Although internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help specify that valid logic levels are latched on these important boot configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

• Select a resistor with the largest possible resistance

• Calculate the worst-case leakage current that flows through this external resistor. Worst-case leakage current can be calculated by adding up all the leakage current at the pin—e.g., the input current (I

I

) from the device, and leakage current from the other device(s) to which this pin is connected.

• Specify that the voltage at the pin stays well within the low-/high-level input voltages (V

IL worst-case leakage current is flowing through this external resistor.

or V

IH

) when

– To oppose an IPU and pull the signal to a logic low, the voltage at the pin must stay well below V

IL

.

– To oppose an IPD and pull the signal to a logic high, the voltage at the pin must stay well above

V

IH

.

For most systems, a 1-k Ω resistor can be used to oppose the IPU/IPD while meeting the above criteria.

Users should confirm this resistor value is correct for their specific application.

For most systems, a 20-k Ω resistor can be used to complement the IPU/IPD on the boot and configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (I

I

), and the low-/high-level input voltages (V

IL and V

IH

) , see

Section 5.3

, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

Temperature.

For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table.






49

TMS320DM647

TMS320DM648


www.ti.com

4 System Interconnect

The C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers between master peripherals and slave peripherals. Through a switch fabric, the CPU can send data to the video ports without affecting a data transfer between the PCI and the DDR2 memory controller. The switch fabrics also allow for seamless arbitration between the system masters when accessing system slaves.

4.1

Internal Buses, Bridges, and Switch Fabrics

Two types of buses exist in the device: data buses and configuration buses. Some device peripherals have both a data bus and a configuration bus interface, while others only have one type of interface.

Furthermore, the bus interface width and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers. However, in some cases, the configuration bus is also used to transfer data. For example, data is transferred to the UART or I2C via their configuration bus. Similarly, the data bus can also be used to access the register space of a peripheral. For example, the EMIFA and DDR2 memory controller registers are accessed through their data bus interface.

The C64x+ Megamodule, the EDMA3 traffic controllers, and the various system peripherals can be divided into two categories: masters and slaves. Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves, on the other hand, rely on the

EDMA3 to perform transfers to and from them. Masters include the EDMA3 traffic controllers and PCI.

Slaves include the McASP, video ports, and I2C.

The device contains two switch fabrics through which masters and slaves communicate. The data switch fabric, known as the data switched central resource (SCR), is a high-throughput interconnect mainly used to move data across the system (for more information, see

Section 4.2

). The data SCR connects masters to slaves via 128-bit data buses running at a SYSCLK1 frequency (SYSCLK1 is generated from PLL1 controller). Peripherals that have a 128-bit data bus interface running at this speed can connect directly to the data SCR; other peripherals require a bridge.

The configuration switch fabric, also known as the configuration switch central resource (SCR) is mainly used by the C64x+ Megamodule to access peripheral registers (for more information, see

Section 4.3

).

The configuration SCR connects the C64x+ Megamodule to slaves via 32-bit configuration buses running at a SYSCLK1 frequency (SYSCLK1 is generated from the PLL1 controller). As with the data SCR, some peripherals require the use of a bridge to interface to the configuration SCR. Note that the data SCR also connects to the configuration SCR. Bridges perform a variety of functions:

• Conversion between configuration bus and data bus.

• Width conversion between peripheral bus width and SCR bus width

• Frequency conversion between peripheral bus frequency and SCR bus frequency

For example, the EMIFA memory controller require a bridge to convert their 64-bit data bus interface into a

128-bit interface so that they can connect to the data SCR.

Some peripherals can be accessed through the data SCR and also through the configuration SCR.

4.2

Data Switch Fabric Connections

Figure 4-1

shows the connection between slaves and masters through the data switched central resource

(SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves via 128-bit data buses running at a SYSCLK1 frequency. SYSCLK1 is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency divided by 3. Some peripherals, like PCI and the

C64x+ Megamodule, have both slave and master ports. Each EDMA3 transfer controller has an independent connection to the data SCR.

Masters can access the configuration SCR through the data SCR. The configuration SCR is described in

Section 4.3

.

50

System Interconnect





TMS320DM647



Not all masters on the device may connect to all slaves. Allowed connections are summarized in

Table 4-

1

.

128 SYSCLK1

S Megamodule

M

Megamodule M

HPI

PCI

VLYNQ

M0

EDMA3

Transfer

Controller

M1

M2

M3

32 SYSCLK3

M

M

32 SYSCLK3

128 SYSCLK1

128 SYSCLK1

128 SYSCLK1

128 SYSCLK1

128 SYSCLK1

32 SYSCLK3

Bridge

M

32 SYSCLK3

128 SYSCLK1

3-port Gigabit

Ethernet Switch M

32 TXBCLK

Bridge

128 SYSCLK1

S

S

0

S

1

S

2

S

3

S

S

M

M

128 SYSCLK1

S

DDR2

Memory

Controller

128

SYSCLK1

64

SYSCLK1

Bridge

64

SYSCLK1

64

SYSCLK1

S

S

EMIFA

Video Port 0

M

Bridge

128 SYSCLK1

64

SYSCLK1

S

64

SYSCLK1

S

64

SYSCLK1

64

SYSCLK1

S

Video Port 1

Video Port 2

Video Port 3

M

M

Bridge

Bridge

64

SYSCLK1

S

32

128 SYSCLK1

32

SYSCLK3

SYSCLK3

S

32

SYSCLK3

Video Port 4

PCI

M

128

128 SYSCLK1

32

SYSCLK1

SYSCLK1

Bridge

S

S VLYNQ

Config SCR

Figure 4-1. Data SCR






51

TMS320DM647

TMS320DM648


TC0

TC1

TC2

TC3

Megamodule

HPI

PCI

VLYNQ

Ethernet Subsystem

Table 4-1. Connectivity Matrix for Data SCR

MEGAMODULE DDR2 EMIF EMIFA

N

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

VIDEO VIDEO

PORT 0-2 PORT 3-4

Y

Y

Y

Y

Y

Y

Y

Y

N

N

N

N

N

N

N

N

N

N

PCI

Y

Y

Y

Y

N

Y

N

Y

Y

VLYNQ

Y

Y

Y

Y

N

Y

N

Y

Y

www.ti.com

Configuration

SCR

Y

Y

Y

N

N

Y

Y

Y

N

4.3

Configuration Switch Fabric

Figure 4-2

shows the connection between the C64x+ megamodule and the configuration SCR, which is mainly used by the C64x+ Megamodule to access peripheral registers. The data SCR also has a connection to the configuration SCR that allows masters to access most peripheral registers. The only registers not accessible by the data SCR through the configuration SCR are the device configuration registers and the PLL1 and PLL2 controller registers; these can be accessed only by the C64x+

Megamodule. The configuration SCR uses 32-bit configuration buses running at SYSCLK1 frequency.

SYSCLK1 is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency divided by 3.

52






www.ti.com

Megamodule M

Config SCR

32-bit SYSCLK1

S

Data SCR

VICP M

M

32-bit

SYSCLK3

32-bit SYSCLK1

Bridge

S

32-bit

SYSCLK1

S

TMS320DM647

TMS320DM648

M

M

M

M


32-bit

SYSCLK1

32-bit

SYSCLK1

Bridge

128-bit

SYSCLK1

32-bit

SYSCLK3

Bridge

32-bit

SYSCLK1

32-bit

SYSCLK1

Bridge

32-bit

SYSCLK1

Bridge

32-bit

TXBCLK

S

Ethernet

SubSystem

32-bit

SYSCLK1

S

32-bit

SYSCLK1

32-bit

SYSCLK1

S

S

32-bit

SYSCLK1

S

32-bit

SYSCLK1

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

S

32-bit

SYSCLK3

32-bit

SYSCLK3

S

S

32-bit

SYSCLK1

S

32-bit

SYSCLK1

S

32-bit

SYSCLK1

S

32-bit

SYSCLK1

S

32-bit

SYSCLK1

S

Video Port 0

Video Port 1

Video Port 2

Video Port 3

Video Port 4

UART

I2C

Timer 0

Timer 1

Timer 2

Timer 3

PSC

PLL Controllers

PCI

McASP

SPI

VIC

GPIO

VICP CFG

HPI

EDMA3 CC

EDMA3 TC0

EDMA3 TC1

EDMA3 TC2

EDMA3 TC3

Figure 4-2. Configuration SCR






53

TMS320DM647

TMS320DM648


5 Device Operating Conditions

www.ti.com

5.1

Absolute Maximum Ratings

Over Operating Temperature Range (Unless Otherwise Noted)

(1)

Supply voltage ranges:

Input voltage ranges:

Output voltage ranges:

Core (CV

DD

DV

DDD

, AV

, CV

DDESS

(2)

DDT

)

, CV

DD1

, AV

DDA

,

I/O, 3.3V (DV

DD33

)

(2)

I/O, 1.8V (DV

DD18

, AV

DLL1

, AV

DLL2

, AV

DDR

)

(2)

V

I

I/O, 3.3-V pins

V

I

I/O, 1.8 V

V

O

I/O, 3.3-V pins

V

O

I/O, 1.8 V

Commercial

1.20-V operation -0.5 V to 1.5 V

-0.5 V to 4.2 V

-0.5 to 2.5 V

-0.5 V to 4.2 V

-0.5 V to 2.5 V

-0.5 V to 4.2 V

-0.5 V to 2.5 V

Operating case temperature, T case

Storage temperature range, T stg

Extended

Industrial

(default)

0°C to 90°C

-40°C to 105°C

-40°C to 90°C

-65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V

SS.

54

Device Operating Conditions





TMS320DM647



5.2

Recommended Operating Conditions

MIN NOM MAX UNIT

CV

DD

CV

DDESS

CV

DD1

AV

DDA

DV

DDD

AV

DDT

DV

DD33

DV

DD18

AV

DLL1

AV

DLL2

AV

DDR

V

SS

DDR_VREF

V

IH

Supply voltage, Core

(1)

Supply voltage, Ethernet Subsystem Core

(1)

Supply voltage, DDR Core

(1)

Supply voltage, SerDes Analog

(1)

Supply voltage, SerDes Digital

(1)

Supply voltage, SerDes Analog

(1)

Supply voltage, I/O, 3.3 V

Supply voltage, DDR I/O, 1.8 V

(-720, -800, -900, -

1100 devices)



Supply voltage, 1.8-V SerDes Analog Supply (Regulator)

Supply ground (V

SS

)

DDR2 reference voltage

(2)

High-level input voltage, 3.3 V (except PCI-capable and I2C pins)

High-level input voltage, I2C

PCI-capable pins

DDR2 memory controller pins (DC)

1.14

3.14

1.71

0

0.49DV

DD18

2

0.7DV

DD33

0.5DV

DD33

DDR_VREF +

0.125

1.2

3.3

1.8

0

0.5DV

DD18

1.26

3.46

1.89

0

0.51DV

DD18

DV

DD33

+ 0.5

DV

DD18

+ 0.3

V

V

V

V

V

V

V

V

V

V

IL

T case

F

SYSCLK1

Low-level input voltage, 3.3 V(except PCI-capable and I2C pins)

Low-level input voltage, I2C

PCI-capable pins

DDR2 memory controller pins (DC)

Operating case temperature

Commercial

(3)

Extended

(4)

Industrial

(-1100 devices)

(3)

DSP Operating Frequency (SYSCLK1)

(-900 devices)

(-720 devices)

(-800 devices)

0

-0.5

-0.3

0

-40

-40

33.3

33.3

33.3

33.3

0.8

0.3DV

DD33

0.3DV

DD33

DDR_VREF - 0.125

90

105

90

1100

900

720

800

V

V

V

V

MHz

MHz

MHz

MHz

(1) Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,

1.1 V, 1.14 V, 1.2, 1.26 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Not incorporating a flexible supply may limit the system ability to easily adapt to future versions of TI SOC devices.

(2) DDR_VREF is expected to equal 0.5DV

DDR2 of the transmitting device and to track variations in the DV

DD18

.

(3) To avoid significant device degradation for 1.1GHz devices, the device power-on hours (POH) must be limited to less than 87.6K.

(4) To avoid significant device degradation for extended temperature devices (- 40°C must be limited to less than 50K.

≤

T case

≤

105°C), the device power-on hours (POH)






55

TMS320DM647

TMS320DM648


www.ti.com

5.3

Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS

(1)

MIN TYP

V

OH

High-level output voltage

3.3-V pins (except PCI-capable and I2C pins)

PCI-capable pins(2)

DDR2 memory controller pins


DV

DD33

= MIN, I

OH

= MAX

DV

DD33

= 3.3V, I

OH

= -0.5 mA

DV

DD33

= MIN, I

OL

= MAX

0.8DV

DD33

0.9DV

DD33

1.4

V

OL

Low-level output voltage

PCI-capable pins(2)

I2C pins


DV

DD33

= 3.3V, I

OL

= 1.5 mA

Pulled up to 3.3 V, 3 mA sink current

I

I

I

I

Input current [dc]

V

I

= V

SS to DV

DD33 pulldown resistor without internal pullup oe


V

I

(2)

= V

SS to DV

DD33 with internal pullup resistor

V

I

= V

SS to DV

DD33 pulldown resistor

(2) with opposing internal

Input current [dc] (I2C) 0.1DV

DD33

≤ V

I

≤ 0.9DV

DD33

PCI-capable pins(4)

I

OH

High-level All peripherals other than DDR2 output current [dc] and PCI


PCI-capable pins(2)

I

OL

Low-level All peripherals other than output current [dc] DDR2 , PCI and I2C

I2C pins


PCI-capable pins(2)

I

OZ

I/O Off-state output current [DC]

3.3-V pins

CDD

Core (CV current

(3)

DD

, V

DDA_1P1V

) supply

CV

DD

= 1.2-V, DSP clock = 720 MHz

CV

DD


CV

DD


CV

DD


DV

DD

= 3.3-V, DSP clock = 720 MHz, 800 MHz,

900 MHz, 1100 MHz

DDD

C

C

I o

3.3-V I/O (DV

DD33

) supply current

(3)

1.8-V I/O (DV

DDR2

,

DDR_VDDDLL, PLLV

PRW18

,

V

DDA_1P8V current

(3)

, MXV

DD

) supply

Input capacitance

Output capacitance

DV

DD

= 1.8-V, DSP clock = 720 MHz, 800 MHz,

900 MHz, 1100 MHz

-1

50

-400

-10

-600

-20

100

-100

2497

2605

2741

3013

227

311

MAX UNIT

V

0.22DV

DD33

0.1DV

DD33

0.4

0.4

1

400

10

10

V

μ

A

μ A mA pF pF

(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

(2) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

(3) Assumes the following conditions: 50% DSP CPU utilization; (peripheral configurations, other housekeeping activities) DDR2 at 50% utilization (266 MHz ), 50% writes, 32 bits, 100% bit switching, 110-MHz Video Ports at 100% utilization, MCASP operating at 25 MHz with 100% utilization with 10 serializers, Timer0,1 at 100% utilization, VICP with 100% utilization, PCI operating at 66 MHz with 50% writes at room temp (25°C) using ZUT package. (as in the power appnote) for the three items.

mA mA mA

μ A mA mA mA mA

μ A

μ A

μ A mA mA mA mA mA

-50

10

600

-8

-4

-0.5

8

3

4

1.5

20

56






TMS320DM647

TMS320DM648


www.ti.com

6 Peripheral Information and Electrical Specifications

6.1

Parameter Information

Tester Pin Electronics

42 Ω 3.5 nH

4.0 pF 1.85 pF

T ransmission Line

Z0 = 50 Ω

(see Note)

Data Sheet Timing Reference Point

Output

Under

Test

Device Pin

(see Note)

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 6-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of ac timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

6.1.1

3.3-V Signal Transition Levels

All input and output timing parameters are referenced to V ref

V ref

= 1.5 V. For 1.8-V I/O, V ref

= 0.9 V.

for both 0 and 1 logic levels. For 3.3-V I/O,

V ref

Figure 6-2. Input and Output Voltage Reference Levels for ac Timing Measurements

All rise and fall transition timing parameters are referenced to V

IL

V

OL

MAX and V

OH

MIN for output clocks.

MAX and V

IH

MIN for input clocks,

V ref

= V

IH

MIN (or V

OH

MIN)

V ref

= V

IL

MAX (or V

OL

MAX)

Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels

6.1.2

3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).


Peripheral Information and Electrical Specifications




57

TMS320DM647

TMS320DM648


www.ti.com

6.1.3

Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays caused by board routings.

As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing

Analysis Application Report (literature number SPRA839 ). If needed, external logic hardware such as buffers may be used to compensate for any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see

Table 6-1

and

Figure 6-4 ).

Figure 6-4

represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device.

8

9

10

11

5

6

7

NO.

1

2

3

4

Table 6-1. Board-Level Timing Example

(see

Figure 6-4 )

DESCRIPTION

Clock route delay

Minimum DSP hold time

Minimum DSP setup time

External device hold time requirement

External device setup time requirement

Control signal route delay

External device hold time

External device access time

DSP hold time requirement

DSP setup time requirement

Data route delay

(Output from DSP)

1

(Input to External Device)

2

Control Signals

(A)

(Output from DSP)

3

4

5

6

Control Signals

(Input to External Device)

7

8

Data Signals

(B)

(Output from External Device)

10

9

Data Signals

(B)

(Input to DSP)

11

A.

Control signals include data for writes.

B.

Data signals are generated during reads from an external device.

Figure 6-4. Board-Level Input/Output Timings

58






TMS320DM647



6.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V

IH manner.

and V

IL

(or between V

IL and V

IH

) in a monotonic

6.3

Power Supplies

For more information regarding TI's power management products and suggested devices to power TI

DSPs, visit www.ti.com/dsppower .

6.3.1

Power-Supply Sequencing

The device includes 1.2-V core supply (CV

DD

, CV

DDESS

, CV

DD1

, AV

DDA

, DV

DDD

, AV

DDT

), and two I/O supplies—3.3-V (DV

DD33

) and 1.8-V (DV

DD18

, AV

DLL1

, AV

DLL2

, AV

DDR

). To ensure proper device operation, a specific power-up sequence must be followed. Some TI power-supply devices include features that facilitate power sequencing — for example, Auto-Track and Slow-Start/Enable features. For more information on TI power supplies and their features, visit www.ti.com/dsppower .

Following is a summary of the power sequencing requirements:

• The power ramp order must be 3.3-V (DV

DD33

) before 1.8-V (DV

DD18

, AV

DLL1

, AV

DLL2

, AV

DDR

), and 1.8-

V (DV

DD18

, AV

DLL1

, AV

DLL2

, AV

DDR

) before 1.2-V core supply (CV

DD

, CV

DDESS

, CV

DD1

, AV

DDA

, DV

DDD

,

AV

DDT

) —meaning during power up, the voltage at the 1.8-V rail should never exceed the voltage at the 3.3-V rail. Similarly, the voltage at the 1.2-V rail should never exceed the voltage at the DV

DDR2 rail.

• From the time that power ramp begins, all power supplies (3.3 V, 1.8 V, 1.2 V) must be stable within

200 ms. The term "stable" means reaching the recommended operating condition (see

Section 5.2

).

6.3.2

Power-Supply Design Considerations

Core and I/O supply voltage regulators should be located close to the DSP to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the device, the PC board should include separate power planes for core, I/O, and ground; all bypassed with high-quality low-ESL/ESR capacitors.

6.3.3

Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors; therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 μ F) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint.

6.3.4

Power and Sleep Controller (PSC)

The power and sleep controller (PSC) controls power by turning off unused power domains or by gating off clocks to individual peripherals/modules. The device uses the clock-gating feature of the PSC only for power savings. The PSC consists of a global PSC (GPSC) and a set of local PSCs (LPSCs).

The GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset control. The LPSCs are shown in

Table 6-2 . The PSC register memory map is given in Table 6-3

. For more details on the PSC, see the TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide

(literature number SPRUEU6 ).






59

TMS320DM647

TMS320DM648


Table 6-2. LPSC Assignments

17

18

19

20

21

12

13

14

15

16

LPSC NUMBER

0

1

2

3

4

7

8

9

5

6

10

11

27

28

29

30

31

32

33

34

22

23

24

25

26

SPI

I2C

PCI

VP0

VP1

TIMER1

Reserved

Reserved

Reserved

Reserved

PERIPHERAL/ MODULE

EDMA3CC

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

DDR2 Memory Controller

UHPI

VLYNQ

GPIO

TIMER0

VP2

VP3

VP4

EMIFA

TIMER2

TIMER3

VIC

McASP

UART

VICP

Reserved

C64x+ CPU

Ethernet Subsystem

www.ti.com


0x0204 6000

0x0204 6004- 0x0204 600F

0x0204 6010

0x0204 6014

0x0204 6018

0x0204 601C- 0x0204 603F

0x0204 6040

0x0204 6044

0x0204 6048- 0x0204 604F

60

Table 6-3. PSC Register Memory Map


PID

–

–

INTEVAL

–

–

MERRPR1

–

DESCRIPTION

Peripheral Revision and Class Information Register

Reserved

Reserved

Reserved

Interrupt Evaluation Register

Reserved

Reserved

Module Error Pending 1 (mod 32- 63) Register

Reserved






www.ti.com

0x0204 6808

0x0204 680C

0x0204 6810

0x0204 6814

0x0204 6818

0x0204 681C

0x0204 6820

0x0204 6824

0x0204 6828

0x0204 682C

0x0204 6830

0x0204 6834

0x0204 6838

0x0204 683C

0x0204 6840

0x0204 6844

0x0204 6848

0x0204 684C

0x0204 6850

0x0204 6854

0x0204 6858

0x0204 685C

0x0204 6860

0x0204 6864

0x0204 6868

0x0204 686C


0x0204 6050

0x0204 6054

0x0204 6058- 0x0204 605F

0x0204 6060

0x0204 6064- 0x0204 6067

0x0204 6068

0x0204 606C- 0x0204 611F

0x0204 6120

0x0204 6124- 0x0204 6127

0x0204 6128

0x0204 612C- 0x0204 61FF

0x0204 6200

0x0204 6204- 0x0204 62FF

0x0204 6300

0x0204 6304- 0x1C4 150F

0x0204 6510

0x0204 6514

0x0204 6518- 0x0204 65FF

0x0204 6600- 0x0204 67FF

0x0204 6800

0x0204 6804


Table 6-3. PSC Register Memory Map (continued)

–

–

–

–

–

MDSTAT7

MDSTAT8

MDSTAT9

MDSTAT10

MDSTAT11

–

–

MDSTAT12

–

–

MDSTAT17

MDSTAT18

MDSTAT19

MDSTAT20

MDSTAT21

MDSTAT22

MDSTAT23

MDSTAT24

MDSTAT25

MDSTAT26

MDSTAT27

–

–

PDSTAT0

–

PDCTL0

–

–

–

MDSTAT0

–

–

–


–

MERRCR1

–

–

–

PTCMD

–

PTSTAT

–

TMS320DM647

TMS320DM648

DESCRIPTION

Reserved

Module Error Clear 1 (mod 32 - 63) Register

Reserved

Reserved

Reserved

Reserved

Reserved

Power Domain Transition Command Register

Reserved

Power Domain Transition Status Register

Reserved

Power Domain Status 0 Register (Always On)

Reserved

Power Domain Control 0 Register (Always On)

Reserved

Reserved

Reserved

Reserved

Reserved

Module Status 0 Register (EDMACC)

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Module Status 7 Register (DDR2)

Module Status 8 Register (HPI)

Module Status 9 Register (VLYNQ)

Module Status 10 Register (GPIO)

Module Status 11 Register (TIMER 0)


Reserved

Reserved

Reserved

Reserved

Module Status 17 Register (SPI)

Module Status 18 Register (I2C)

Module Status 19 Register (PCI)

Module Status 20 Register (Video Port 0)





Module Status 25 Register (EMIFA)








61

TMS320DM647

TMS320DM648


0x0204 6870

0x0204 6874

0x0204 6878

0x0204 687C

0x0204 6880

0x0204 6884

0x0204 6888

0x0204 688C-0x0204 69FF

0x0204 6A00

0x0204 6A04

0x0204 6A08

0x0204 6A0C

0x0204 6A10

0x0204 6A14

0x0204 6A18

0x0204 6A1C

0x0204 6A20

0x0204 6A24

0x0204 6A28

0x0204 6A2C

0x0204 6A30

0x0204 6A34

0x0204 6A38

0x0204 6A3C

0x0204 6A40

0x0204 6A44

0x0204 6A48

0x0204 6A4C

0x0204 6A50

0x0204 6A54

0x0204 6A58

0x0204 6A5C

0x0204 6A60

0x0204 6A64

0x0204 6A68

0x0204 6A6C

0x0204 6A70

0x0204 6A74

0x0204 6A78

0x0204 6A7C

0x0204 6A80

0x0204 6A84

0x0204 6A88

0x0204 6A90- 0x0204 6FFF


Table 6-3. PSC Register Memory Map (continued)

MDCTL23

MDCTL24

MDCTL25

MDCTL26

MDCTL27

MDCTL28

MDCTL29

MDCTL30

MDCTL31

–

MDCTL33

MDCTL34

–

–

–

–

–

MDCTL17

MDCTL18

MDCTL19

MDCTL20

MDCTL21

MDCTL22

–

–

–

–

MDCTL7

MDCTL8

MDCTL9

MDCTL10

MDCTL11

MDCTL12


MDSTAT28

MDSTAT29

MDSTAT30

MDSTAT31

–

MDSTAT33

–

–

MDSTAT34

–

MDCTL0

DESCRIPTION

Module Status 28 Register (VIC)

Module Status 29 Register (McASP)

Module Status 30 Register (UART)

Module Status 31 Register (VICP)

Reserved

Module Status 33 Register (C64x+ CPU)

Module Status 34 Register (Ethernet Subsystem)

Reserved

Module Control 0 Register (EDMACC)

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Module Control 7 Register (DDR2)

Module Control 8 Register (HPI)

Module Control 9 Register (VLYNQ)

Module Control 10 Register (GPIO)

Module Control 11 Register (TIMER 0)


Reserved

Reserved

Reserved

Reserved

Module Control 17 Register (SPI)

Module Control 18 Register (I2C)

Module Control 19 Register (PCI)

Module Control 20 Register (Video Port 0)





Module Control 25 Register (EMIFA)



Module Control 28 Register (VIC)

Module Control 29 Register (McASP)

Module Control 30 Register (UART)

Module Control 31 Register (VICP)

Reserved

Module Control 33 Register (C64x+ CPU)

Module Control 34 Register (Ethernet Subsystem)

Reserved

www.ti.com

62






TMS320DM647



POWER DOMAIN

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

System Domain

Ethernet Subsystem Domain

6.3.5

Power and Clock Domains

The device includes two power domains: the System Domain and the Ethernet Subsystem Domain. Both of these power domains are always on when the chip is on. Both of these domains are powered by the

CV

DD pins of the device.

The primary PLL controller generates the input clock to the C64x+ megamodule as well as most of the system peripherals such as the multichannel audio serial ports (McASPs) and the external memory interface (EMIFA). The secondary PLL controller generates interface clocks for the DDR2 memory controller. The Ethernet Subsystem is clocked through the SerDes module, which takes input from

REFCLKP/N. The primary PLL controller (PLL1 controller) uses the device input clock CLKIN1 and the secondary PLL controller (PLL2 controller) uses the device input clock CLKIN2.

Table 6-4

provides a listing of the clock domains.

Table 6-4. Power and Clock Domains

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV6

CLOCK DOMAIN

CLKDIV1

CLKDIV3

CLKDIV3

CLKDIV3

CLKDIV3

CLKDIV3

CLKDIV3

CLKDIV3

CLKDIV3

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV6

CLKDIV4 0

CLKDIV4 1

CLKDIV4 2

CLKDIV2

SerDes TXBCLK

HPI

PCI

VLYNQ

UART

I2C

TIMER 0

TIMER 1

TIMER 2

TIMER 3

SPI

PERIPHERAL/MODULE/USAGE

C64x+ CPU

EDMA/SCR

DDR Subsystem

Video Port 0

Video Port 1

Video Port 2

Video Port 3

Video Port 4

EMIFA

McASP

VIC

GPIO

PLL Controller 1

PLL Controller 2

Config SCR

Internal EMIFA Clock

Emulation and Trace

VICP cop_clk/2

VICP cop_clk

Ethernet Subsystem






63

TMS320DM647

TMS320DM648


www.ti.com

The device architecture is divided into the power and clock domains shown in

Table 6-5 , which further

shows the clock domains and their ratios.

Table 6-5. Clock Domain Assignment

SUBSYSTEM

DSP Subsystem

Peripherals (CLKDIV3 Domain)

Emulation/Trace

Peripherals (CLKDIV6 Domain)

Internal EMIFA Clock

VICP cop_clk/2

VICP cop_clk

CLOCK DOMAIN

CLKDIV1

CLKDIV3

CLKDIV4 1

CLKDIV6

CLKDIV4 0

CLKDIV4 2

CLKDIV2

DOMAIN CLOCK SOURCE

PLLC1.REFSYSCLK

PLLC1.SYSCLK1

PLLC1.SYSCLK2

PLLC1.SYSCLK3

PLLC1.SYSCLK4

PLLC1.SYSCLK5

PLLC1.SYSCLK6

FIXED RATIO vs SYSREFCLK

FREQUENCY

-

1:3

1:4

1:6

1:4

(1)

1:4

1:2

(1) There is a /2 divider in the path of PLLC1.SYSCLK4 so the effective EMIFA clock is PLLC1.SYSCLK4/2. By default the internal EMIFA

Clock is 1:8.

6.3.6

Preserving Boundary-Scan Functionality on DDR2 Memory Pins

Similarly, when the DDR2 Memory Controller is not used, the DDR_VREF, RSV19, and RSV20 pins can be connected directly to ground (V

SS

) to save power. However, this will prevent boundary-scan from functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2

Memory Controller pins, DDR_VREF, RSV19, and RSV20 should be connected as follows:

• DDR_VREF - connect to a voltage of DV

DD18

/2. The DV

DD18

/2 voltage can be generated directly from the DV

DD18 supply using two 1-k Ω resistors to form a resistor divider circuit.

• RSV19 - connect this pin to the 1.8-V I/O supply (DV

DD18

) via a 200Ω resistor

• RSV20 - connect this pin to ground (V

SS

) via a 200Ω resistor.

64






TMS320DM647



6.4

PLL1 Controller

The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as well as most of the system peripherals such as the multichannel audio serial ports (McASPs) and the external memory interface (EMIFA).

Figure 6-5

shows a functional block diagram of the PLL Input Clock.

+1.8 V

EMI Filter

C1

560 pF

C2

PLLV1

CLKIN1

PLL1 Controller

PLL1

DIVIDER PREDIV

/1, /2, /3

ENA

PLLM x1, x16 to x32

1

0

PLLEN (PLLCTL.[0])

SYSREFCLK

(C64x+ MegaModule)

DIVIDER D1

/3

SYSCLK1

PREDEN (PREDIV.[15])

D2EN (PLLDIV2.[15])

DIVIDER D2

/1, /2,

..., /8

ENA

DIVIDER D3

/6

SYSCLK2

(Emulation and Trace)

SYSCLK3

D4EN (PLLDIV4.[15])

DIVIDER D4

/4 ... /8

ENA

DIVIDER D5

/4

SYSCLK4

SYSCLK5

VICP cop_clk/2

DIVIDER D6

/2

SYSCLK6

VICP cop_clk

AECLKIN (External EMIF Clock Input)

VCLK

0 1

VLYNQ

/1, /2,

..., /8

CLKDIV

CLKDIR

(CTRL.[15])

(CTRL.[18:16])

0 1

EMIFA

(EMIF Input Clock)

AECLKINSEL

(AEA[17] pin)

/2

(Internal

EMIF Clock

Input)

AECLKOUT

SYSCLK5

Figure 6-5. PLL Input Clock






65

TMS320DM647

TMS320DM648


www.ti.com

As shown in

Figure 6-5 , the PLL1 controller features a software-programmable PLL multiplier controller

(PLLM) and seven dividers (PREDIV, D1, D2, D3, D4, D5). The PLL1 controller uses the device input clock CLKIN1 to generate a system reference clock (SYSREFCLK) and system clocks (SYSCLK1,

SYSCLK2, SYSCLK3, SYSCLK4, SYSCLK5). PLL1 power is supplied externally via the PLL1 powersupply pin (PLLV1). An external EMI filter circuit must be added to PLLV1. The 1.8-V supply of the EMI filter must be from the same 1.8-V power plane supplying the I/O power-supply pin, DV

DD18

. TI requires

EMI filter manufacturer Murata, part number NFM18CC222R1C3.

All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the C64x+ DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components

(C1, C2, and the EMI Filter). The minimum CLKIN1 rise and fall times should also be observed. For the input clock timing requirements, see

Section 6.4.4

.

6.4.1

PLL1 Controller Device-Specific Information

As shown in

Figure 6-5

, the PLL1 controller generates several internal clocks including the system reference clock (SYSREFCLK), and the system clocks (SYSCLK1/2/3/4/5/6). The high-frequency clock signal SYSREFCLK is directly used to clock the C64x+ megamodule (including the CPU) and also serves as a reference clock for the rest of the DSP system. Dividers D1, D2, D3, D4, D5, and D6 divide the highfrequency clock SYSREFCLK to generate SYSCLK1, SYSCLK2, SYSCLK3, SYSCLK4, SYSCLK5, and

SYSCLK6, respectively.

The system clocks are used to clock different portions of the DSP as follows:

• SYSCLK1 is used for the following modules: 3PDMA, the SCR and the bridges, DDR Subsystem internal logic, Video Port 0, Video Port 1, Video Port 2, Video Port 3, Video Port 4, EMIFA internal logic.

• SYSCLK2 is used for Emulation and Trace

• SYSCLK3 is used for most of the peripherals. These modules are clocked from SYSCLK3: HPI, PCI,

VLYNQ, UART, I2C, TIMER 0, TIMER 1, TIMER 2, TIMER 3, SPI, McASP, VIC, GPIO, PLL Controller

1, PLL Controller 2, Config SCR

• SYSCLK4 is used as the EMIFA AECLKOUT

[When SYSCLK4 is used as the EMIF input clock source, the actual clock goes through a divider and the frequency would be SYSCLK4 divide-by-2 (see

Figure 6-5

, PLL Input Clock).]

• SYSCLK5 is used as the VICP internal clock

• SYSCLK6 is used as the VICP internal clock

The PLL multiplier controller (PLLM) must be programmed after reset. There is no hardware CLKMODE selection on the device. Since the divider ratio bits for dividers D1, D3, D5, and D6 are fixed, the frequency of SYSCLK1, SYCLK3, SYSCLK5, and SYSCLK6 is tied to the frequency of SYSREFCLK.

However, the frequency of SYSCLK2 and SYSCLK4 depends on the configuration of dividers D2 and D4.

For example, with PLLM in the PLL1 multiply control register set to 10011b (x20 mode) and a 35-MHz

CLKIN1 input, the PLL output PLLOUT is set to 700 MHz and SYSCLK1 and SYSCLK3 run at 233 MHz and 117 MHz, respectively. Divider D4 can be programmed through the PLLDIV4 register to divide

SYSREFCLK by 8 (2 * (PLLDIV4.RATIO+1)) such that SYSCLK4 runs at 87.5 MHz.

Note that there is a minimum and maximum operating frequency for PLLREF, PLLOUT, and SYSCLK4.

The PLL1 Controller must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). For the PLL clocks input and output frequency ranges, see

Table 6-6 .

66






TMS320DM647



Table 6-6. PLL1 Clock Frequency Ranges

CLOCK SIGNAL

CLKIN1

PLLREF (PLLEN = 1)

(1)

PLLOUT

(1)

MIN

25

25

400

400

400

400

1/16P

(3)

MAX

66.6

66.6

720 (-720 devices)

800 (-800 devices)

(2)

900 (-900 devices)

1100 (-1100 devices)

PLLOUT/ (2*(PLLDIV4.RATIO+1))

(4)

UNIT

MHz

MHz

MHz

MHz

MHz

MHz

MHz SYSCLK4

(1) Only applies when the PLL1 Controller is set to PLL mode (PLLEN = 1 in the PLLCTL register). Based on CLKIN1 and PLLOUT, PLL1 multiplier factor ranges from x16 to x32.

(2) Only for Extended Temperature Range device (-800 MHz)

(3) P = 1/CPU clock frequency in ns

(4) PLLDIV4.RATIO =3

6.4.2

PLL1 Controller Operating Modes

The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM. In bypass mode, CLKIN1 is fed directly to SYSREFCLK.

All hosts (i.e., HPI) must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed.

6.4.3

PLL1 Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device power-up. The PLL should not be operated until this stabilization time has finished.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1) for the

PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL1 reset time value, see

Table 6-7 .

Table 6-7. PLL1 Stabilization, Lock, and Reset Times

PLL stabilization time

PLL lock time

PLL reset time

MIN

150

128 × C

(1)

TYP

(1) C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.

MAX

2000 × C

(1)

UNIT

μ s

μ s

μ s






67

TMS320DM647

TMS320DM648


6.4.4

PLL1 Controller Input and Output Clock Electrical Data/Timing

www.ti.com

Table 6-8. Timing Requirements for CLKIN1

(1) (2)

(see

Figure 6-6

)

NO.

720, 800, 900, 1100

PLL MODES

(3)

1

2

3

4

5 t c(CLKIN1) t w(CLKIN1H) t w(CLKIN1L) t t(CLKIN1) t

J(CLKIN1)

Cycle time, CLKIN1

Pulse duration, CLKIN1 high

Pulse duration, CLKIN1 low

Transition time, CLKIN1

Period jitter, (peak-to-peak), CLKIN1

MIN

15

0.4C

0.4C

MAX

40

1.2

100

(1) The reference points for the rise and fall transitions are measured at 3.3-V V

IL

MAX and V

IH

MIN.


(3) The PLL1 multiplier factors (x1 [BYPASS], x16 to x32) further limit the MIN and MAX values for t c(CLKIN1)

. See

Section 6.3.5

for supported PLL1 multiplier factors.

UNIT

ns ns ns ns ps

5

1

4

2

CLKIN

3

4

Figure 6-6. CLKIN1 Timing

6.4.5

PLL1 Controller Register Description(s)

A summary of the PLL1 controller registers is shown in

Table 6-9 .


0x020E 0000

0x020E 00E4

0x020E 0100

0x020E 0110

0x020E 0114

0x020E 011C

0x020E 0138

0x020E 013C

0x020E 0140

0x020E 0144

0x020E 0150

0x020E 0160

Table 6-9. PLL1 and Reset Controller Registers Memory Map

REGISTER NAME

PID

RSTYPE

PLLCTL

PLLM

PREDIV

PLLDIV2

PLLCMD

PLLSTAT

ALNCTL

DCHANGE

SYSTAT

PLLDIV4

DESCRIPTION

Peripheral Identification and Revision Information Register

Reset Type Register

PLL Controller 1 Operations Control Register

PLL Controller 1 Multiplier Control Register

PLL Pre-Divider Control Register

PLL Controller 1 Control-Divider 2 Register (SYSCLK2)

PLL Controller 1 Command Register

PLL Controller 1 Status Register (Shows PLLC1 Status)

PLL Controller Clock Align Control Register

PLLDIV Ratio Change Status Register

PLL Controller 1 System Clock Status 1 Register (Indicates SYSCLK on/off

Status)

PLL Controller 1 Control-Divider 4 Register (SYSCLK4)

68






TMS320DM647



6.5

PLL2 Controller

The secondary PLL controller generates interface clocks for the DDR2 memory controller.

As shown in

Figure 6-7 , the PLL2 controller features a PLL multiplier controller. The PLL multiplier is fixed

to a x20 multiplier rate. PLL2 power is supplied externally via the PLL2 power supply (PLLV2). An external

PLL filter circuit must be added to PLLV2 as shown in

Figure 6-7

. The 1.8-V supply for the EMI filter must be from the same 1.8-V power plane supplying the I/O power-supply pin, DV

DD18

. TI requires EMI filter manufacturer Murata, part number NFM18CC222R1C3.

+1.8 V

EMI Filter

C161 C162

560 pF 0.1 F

PLLV2

CLKIN2 PLLREF

PLL2

PLLOUT

SYSCLK1 (From PLL Controller 1)

DDR2 Memory Controller

PLLM x20

Figure 6-7. PLL Controller

All PLL external components (C161, C162, and the EMI Filter) should be placed as close to the C64x+

DSP device as possible. For the best performance, TI requires that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components

(C161, C162, and the EMI Filter). The minimum CLKIN2 rise and fall times should also be observed. For the input clock timing requirements, see

Section 6.5.3

, PLL2 Controller Input Clock Electrical Data/Timing.

6.5.1

PLL2 Controller Device-Specific Information

As shown in

Figure 6-7 , the output of PLL2, PLLOUT, is directly fed to the DDR2 memory controller. This

clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUTz. Note that, internally, the data bus interface of the DDR2 memory controller is clocked by SYSCLK1 of the PLL1 controller.

Note that there is a minimum and maximum operating frequency for PLLREF and PLLOUT. The clock generator must not be configured to exceed any of these constraints. For the PLL clocks input and output frequency ranges, see

Table 6-10 .

Table 6-10. PLL2 Clock Frequency Ranges

CLOCK SIGNAL

PLLREF (CLKIN2 )

PLLOUT (DDR2 clock)

REQUIRED FREQUENCY

20 - 26.6

400 - 533

(1)

(1) This clock is the 2x of the DDR clock. The DDR PHY divides the clock down /2.

UNIT

MHz

MHz






69

TMS320DM647

TMS320DM648


www.ti.com

6.5.2

PLL2 Controller Operating Modes

Unlike the PLL1 controller that can operate in bypass and a PLL mode, the PLL2 controller only operates in PLL mode. PLL2 is unlocked only during the power-up sequence (see

Section 6.7

) and is locked by the

time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

6.5.3

PLL2 Controller Input Clock Electrical Data/Timing

NO.

Table 6-11. Timing Requirements for CLKIN2

(1) (2)

(see

Figure 6-8 )

1 t c(CLKIN2)

2 t w(CLKIN2H)

3 t w(CLKIN2L)

4 t t(CLKIN2)

5 t

J(CLKIN2)

Cycle time, CLKIN2

Pulse duration, CLKIN2 high

Pulse duration, CLKIN2 low

Transition time, CLKIN2

Period jitter, (peak-to-peak) CLKIN2

(1) The reference points for the rise and fall transitions are measured at 3.3-V V

IL

MAX and V

IH

MIN.


720, 800, 900, 1100

PLL MODE x20

MIN

37.5

0.4C

0.4C

UNIT

MAX

50 ns ns ns

1.2

ns

100 ps

5

1

4

2

CLKIN

3

4

Figure 6-8. CLKIN2 Timing

6.5.4

PLL2 Controller Register Description(s)

A summary of the PLL2 controller registers is shown in

Table 6-12

.


0x0212 0000

0x0212 0100

0x0212 0110

0x0212 0138

0x0212 013C

Table 6-12. PLL2 and Reset Controller Registers Memory Map

REGISTER NAME

PID

PLLCTL

PLLM

PLLCMD

PLLSTAT

DESCRIPTION

Peripheral Identification and Revision Information Register

PLL Controller 2 Operations Control Register

PLL Controller 2 Multiplier Control Register

PLL Controller 2 Command Register

PLL Controller 2 Status Register (Shows PLLC1 Status)

70






TMS320DM647



6.6

Enhanced Direct Memory Access (EDMA3) Controller

The EDMA controller handles all data transfers between memories and the device slave peripherals on the device. These data transfers include cache servicing, non-cacheable memory accesses, userprogrammed data transfers, and host accesses. These are summarized as follows:

• Transfer to/from on-chip memories

– DSP L1D memory

– DSP L2 memory

• Transfer to/from external storage

– DDR2 SDRAM

– Synchronous/Asynchronous EMIF (EMIFA)

• Transfer to/from peripherals/hosts

– VLYNQ

– HPI

– McASP

– UART

– Video Port 0/1/2/3/4

– Timer 0/1/2/3

– SPI

– I2C

6.6.1

EDMA3 Channel Synchronization Events

The EDMA supports up to 64 EDMA channels that service peripheral devices and external memory.

Table 6-13

lists the source of EDMA synchronization events associated with each of the programmable

EDMA channels. The association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ER,

ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320DM647/DM648 DSP Enhanced DMA (EDMA)

Controller User's Guide (literature number SPRUEL2 ).

TPCC DEFAULT BINARY

CHANNEL EVENT#

0 0 000 0000

3

4

1

2

1

2

3

4

000 0001

000 0010

000 0011

000 0100

5

6

7

8

9

5

6

7

8

9

000 0101

000 0110

000 0111

000 1000

000 1001

13

14

15

10

11

12

13

14

15

10

11

12

000 1010

000 1011

000 1100

000 1101

000 1110

000 1111

Table 6-13. EDMA Channel Synchronization Events

DEFAULT EVENT

HPI/PCI : DSPINT

TIMER0 : TINT0L

TIMER0 : TINT0H

TIMER2 : TINT2L

TIMER2 : TINT2H

TIMER3 : TINT3L

TIMER3 : TINT3H

VICP: IMXINT

VICP: VLCDINT

VICP: DSQINT

McASP: AXEVTE

McASP: AXEVTO

McASP: AXEVT

McASP: AREVTE

McASP: AREVTO

McASP: AREVT


CHANNEL EVENT #

32 32 010 0000

33

34

35

36

33

34

35

36

010 0001

010 0010

010 0011

010 0100

37

38

39

40

41

37

38

39

40

41

010 0101

010 0110

010 0111

010 1000

010 1001

45

46

47

42

43

44

45

46

47

42

43

44

010 1010

010 1011

010 1100

010 1101

010 1110

010 1111

DEFAULT EVENT

VP2EVTYA

VP2EVTCbA

VP2EVTCrA

VP2EVTYB

VP2EVTCbB

VP2EVTCrB

VP3EVTYA

VP3EVTCbA

VP3EVTCrA

VP3EVTYB

VP3EVTCbB

VP3EVTCrB

ICREVT

ICXEVT

SPI: SPIXEVT

SPI: SPIREVT






71

TMS320DM647

TMS320DM648


www.ti.com

Table 6-13. EDMA Channel Synchronization Events (continued)

28

29

30

31

25

26

27


CHANNEL EVENT#

16

17

16

17

001 0000

001 0001

18

19

18

19

001 0010

001 0011

20

21

22

23

24

20

21

22

23

24

001 0100

001 0101

001 0110

001 0111

001 1000

28

29

30

31

25

26

27

001 1001

001 1010

001 1011

001 1100

001 1101

001 1110

001 1111

DEFAULT EVENT

TIMER1 : TINT1L

TIMER1 : TINT1H

UART: URXEVT

UART: UTXEVT

VP0EVTYA

VP0EVTCbA

VP0EVTCrA

VP0EVTYB

VP0EVTCbB

VP0EVTCrB

VP1EVTYA

VP1EVTCbA

VP1EVTCrA

VP1EVTYB

VP1EVTCbB

VP1EVTCrB

60

61

62

63

57

58

59


CHANNEL EVENT #

48

49

48

49

011 0000

011 0001

50

51

50

51

011 0010

011 0011

52

53

54

55

56

52

53

54

55

56

011 0100

011 0101

011 0110

011 0111

011 1000

60

61

62

63

57

58

59

011 1001

011 1010

011 1011

011 1100

011 1101

011 1110

011 1111

DEFAULT EVENT

VP4EVTYA

VP4EVTCbA

VP4EVTCrA

VP4EVTYB

VP4EVTCbB

VP4EVTCrB

GPIO : GPINT6

GPIO : GPINT7

GPIO : GPINT8

GPIO : GPINT9

GPIO : GPINT10

GPIO : GPINT11

GPIO : GPINT12

GPIO : GPINT13

GPIO : GPINT14

GPIO : GPINT15

6.6.2

EDMA Peripheral Register Description(s)

Table 6-14

lists the EDMA registers, their corresponding acronyms, and device memory locations.

HEX ADDRESS

0x02A0 0000

0x02A0 0004

0x02A0 0008 - 0x02A0 00FC

0x02A0 0100

0x02A0 0104

0x02A0 0108

0x02A0 010C

0x02A0 0110

0x02A0 0114

0x02A0 0118

0x02A0 011C

0x02A0 0120

0x02A0 0124

0x02A0 0128

0x02A0 012C

0x02A0 0130

0x02A0 0134

0x02A0 0138

0x02A0 013C

0x02A0 0140

0x02A0 0144

0x02A0 0148

0x02A0 014C

0x02A0 0150

DCHMAP0

DCHMAP1

DCHMAP2

DCHMAP3

DCHMAP4

DCHMAP5

DCHMAP6

DCHMAP7

DCHMAP8

DCHMAP9

DCHMAP10

DCHMAP11

DCHMAP12

DCHMAP13

DCHMAP14

DCHMAP15

DCHMAP16

DCHMAP17

DCHMAP18

DCHMAP19

DCHMAP20

Table 6-14. EDMA Channel Controller Registers

ACRONYM

PID

CCCFG

REGISTER NAME

Peripheral ID Register

EDMA3CC Configuration Register

Reserved

DMA Channel 0 Mapping Register





















72






TMS320DM647



0x02A0 01A8

0x02A0 01AC

0x02A0 01B0

0x02A0 01B4

0x02A0 01B8

0x02A0 01BC

0x02A0 01C0

0x02A0 01C4

0x02A0 01C8

0x02A0 01CC

0x02A0 01D0

0x02A0 01D4

0x02A0 01D8

0x02A0 01DC

0x02A0 01E0

0x02A0 01E4

0x02A0 01E8

0x02A0 01EC

0x02A0 01F0

0x02A0 01F4

0x02A0 01F8

0x02A0 01FC

0x02A0 0200

0x02A0 0204

0x02A0 0208

0x02A0 020C

HEX ADDRESS

0x02A0 0154

0x02A0 0158

0x02A0 015C

0x02A0 0160

0x02A0 0164

0x02A0 0168

0x02A0 016C

0x02A0 0170

0x02A0 0174

0x02A0 0178

0x02A0 017C

0x02A0 0180

0x02A0 0184

0x02A0 0188

0x02A0 018C

0x02A0 0190

0x02A0 0194

0x02A0 0198

0x02A0 019C

0x02A0 01A0

0x02A0 01A4

Table 6-14. EDMA Channel Controller Registers (continued)

DCHMAP42

DCHMAP43

DCHMAP44

DCHMAP45

DCHMAP46

DCHMAP47

DCHMAP48

DCHMAP49

DCHMAP50

DCHMAP51

DCHMAP52

DCHMAP53

DCHMAP54

DCHMAP55

DCHMAP56

DCHMAP57

DCHMAP58

DCHMAP59

DCHMAP60

DCHMAP61

DCHMAP62

DCHMAP63

QCHMAP0

QCHMAP1

QCHMAP2

QCHMAP3

ACRONYM

DCHMAP21

DCHMAP22

DCHMAP23

DCHMAP24

DCHMAP25

DCHMAP26

DCHMAP27

DCHMAP28

DCHMAP29

DCHMAP30

DCHMAP31

DCHMAP32

DCHMAP33

DCHMAP34

DCHMAP35

DCHMAP36

DCHMAP37

DCHMAP38

DCHMAP39

DCHMAP40

DCHMAP41

REGISTER NAME












































QDMA Channel 0 Mapping to PaRAM Register









73

TMS320DM647

TMS320DM648



HEX ADDRESS

0x02A0 0210

0x02A0 0214

0x02A0 0218

0x02A0 021C

0x02A0 0220 - 0x02A0 021C

0x02A0 0220 - 0x02A0 023C

0x02A0 0240

0x02A0 0244

0x02A0 0248

0x02A0 024C

0x02A0 0250

0x02A0 0254

0x02A0 0258

0x02A0 025C

0x02A0 0260

0x02A0 0264 - 0x02A0 0280

0x02A0 0284

0x02A0 0288 - 0x02A0 02FC

0x02A0 0300

0x02A0 0304

0x02A0 0308

0x02A0 030C

0x02A0 0310

0x02A0 0314

0x02A0 0318

0x02A0 031C

0x02A0 0320

0x02A0 0324 - 0x02A0 033C

0x02A0 0340

0x02A0 0344

0x02A0 0348

0x02A0 034C

0x02A0 0350

0x02A0 0354

0x02A0 0358

0x02A0 035C

0x02A0 0360

0x02A0 0364

0x02A0 0368

0x02A0 036C

0x02A0 0370

0x02A0 0374

0x02A0 0378

0x02A0 037C

0x02A0 0380

0x02A0 0384

0x02A0 0388

EMCRH

QEMR

QEMCR

CCERR

CCERRCLR

EEVAL

-

DRAE0

DRAEH0

DRAE1

DRAEH1

DRAE2

DRAEH2

DRAE3

DRAEH3

DRAE4

DRAEH4

DRAE5

DRAEH5

DRAE6

DRAEH6

DRAE7

DRAEH7

QRAE0

QRAE1

QRAE2

ACRONYM

QCHMAP4

QCHMAP5

QCHMAP6

QCHMAP7

-

-

DMAQNUM0

DMAQNUM1

DMAQNUM2

DMAQNUM3

DMAQNUM4

DMAQNUM5

DMAQNUM6

DMAQNUM7

QDMAQNUM

-

QUEPRI

-

EMR

EMRH

EMCR

REGISTER NAME





Reserved

Reserved

DMA Queue Number Register 0 (Channels 00 to 07)








CC QDMA Queue Number

Reserved

Queue Priority Register

Reserved

Event Missed Register

Event Missed Register High

Event Missed Clear Register

Event Missed Clear Register High

QDMA Event Missed Register

QDMA Event Missed Clear Register

EDMA3CC Error Register

EDMA3CC Error Clear Register

Error Evaluate Register

Reserved

DMA Region Access Enable Register for Region 0

DMA Region Access Enable Register High for Region 0















QDMA Region Access Enable Register for Region 0



74

www.ti.com






TMS320DM647



0x02A0 0440

0x02A0 0444

0x02A0 0448

0x02A0 044C

0x02A0 0450

0x02A0 0454

0x02A0 0458

0x02A0 045C

0x02A0 0460

0x02A0 0464

0x02A0 0468

0x02A0 046C

0x02A0 0470

0x02A0 0474

0x02A0 0478

0x02A0 047C

0x02A0 0480

0x02A0 0484

0x02A0 0488

0x02A0 048C

0x02A0 0490

0x02A0 0494

0x02A0 0498

0x02A0 049C

0x02A0 04A0

0x02A0 04A4

HEX ADDRESS

0x02A0 038C

0x02A0 0390

0x02A0 0394

0x02A0 0398

0x02A0 039C

0x02A0 0400

0x02A0 0404

0x02A0 0408

0x02A0 040C

0x02A0 0410

0x02A0 0414

0x02A0 0418

0x02A0 041C

0x02A0 0420

0x02A0 0424

0x02A0 0428

0x02A0 042C

0x02A0 0430

0x02A0 0434

0x02A0 0438

0x02A0 043C


Q1E10

Q1E11

Q1E12

Q1E13

Q1E14

Q1E15

Q2E0

Q2E1

Q2E2

Q2E3

Q2E4

Q2E5

Q2E6

Q2E7

Q2E8

Q2E9

Q1E0

Q1E1

Q1E2

Q1E3

Q1E4

Q1E5

Q1E6

Q1E7

Q1E8

Q1E9

Q0E6

Q0E7

Q0E8

Q0E9

Q0E10

Q0E11

Q0E12

Q0E13

Q0E14

Q0E15

ACRONYM

QRAE3

QRAE4

QRAE5

QRAE6

QRAE7

Q0E0

Q0E1

Q0E2

Q0E3

Q0E4

Q0E5

REGISTER NAME






Event Queue 0 Entry Register 0















































75

TMS320DM647

TMS320DM648



0x02A0 04FC

0x02A0 0500 - 0x02A0 051C

0x02A0 0520 - 0x02A0 05FC

0x02A0 0600

0x02A0 0604

0x02A0 0608

0x02A0 060C

0x02A0 0610 - 0x02A0 061C

0x02A0 0620

0x02A0 0624

0x02A0 0640

0x02A0 0644 - 0x02A0 06FC

0x02A0 0700 - 0x02A0 07FC

0x02A0 0800

0x02A0 0804

0x02A0 0808

0x02A0 080C

0x02A0 0810

0x02A0 0814

0x02A0 0818

0x02A0 081C

0x02A0 0820

0x02A0 0824

0x02A0 0828

0x02A0 082C - 0x02A0 0FFC

0x02A0 1000

HEX ADDRESS

0x02A0 04A8

0x02A0 04AC

0x02A0 04B0

0x02A0 04B4

0x02A0 04B8

0x02A0 04BC

0x02A0 04C0

0x02A0 04C4

0x02A0 04C8

0x02A0 04CC

0x02A0 04D0

0x02A0 04D4

0x02A0 04D8

0x02A0 04DC

0x02A0 04E0

0x02A0 04E4

0x02A0 04E8

0x02A0 04EC

0x02A0 04F0

0x02A0 04F4

0x02A0 04F8

CCSTAT

-

-

MPFAR

MPFSR

MPFCR

MPPA0

MPPA1

MPPA2

MPPA3

Q3E15

-

-

QSTAT0

QSTAT1

QSTAT2

QSTAT3

-

QWMTHRA

-

MPPA4

MPPA5

MPPA6

MPPA7

-

ER

Q3E5

Q3E6

Q3E7

Q3E8

Q3E9

Q3E10

Q3E11

Q3E12

Q3E13

Q3E14

ACRONYM

Q2E10

Q2E11

Q2E12

Q2E13

Q2E14

Q2E15

Q3E0

Q3E1

Q3E2

Q3E3

Q3E4

REGISTER NAME























Reserved

Reserved

Queue 0 Status Register

Queue 1 Status Register

Queue Status Register 2

Queue Status Register 3

Reserved

Queue Watermark Threshold A Register for Q[3:0]

Reserved

EDMA3CC Status Register

Reserved

Reserved

Memory Protection Fault Address Register

Memory Protection Fault Status Register

Memory Protection Fault Command Register

Memory Protection Page Attribute Register 0








Reserved

Event Register

76

www.ti.com






TMS320DM647




HEX ADDRESS

0x02A0 1004

0x02A0 1008

0x02A0 100C

0x02A0 1010

0x02A0 1014

0x02A0 1018

0x02A0 101C

0x02A0 1020

0x02A0 1024

0x02A0 1028

0x02A0 102C

0x02A0 1030

0x02A0 1034

0x02A0 1038

0x02A0 103C

0x02A0 1040

0x02A0 1044

0x02A0 1048 - 0x02A0 104C

0x02A0 1050

0x02A0 1054

0x02A0 1058

0x02A0 105C

0x02A0 1060

0x02A0 1064

0x02A0 1068

0x02A0 106C

0x02A0 1070

0x02A0 1074

0x02A0 1078

0x02A0 107C

0x02A0 1080

0x02A0 1084

0x02A0 1088

0x02A0 108C

0x02A0 1090

0x02A0 1094

0x02A0 1098 - 0x02A0 1FFF

0x02A0 2000- 0x02A0 2097

0x02A0 2098 - 0x02A0 21FF

0x02A0 2200 - 0x02A0 2297

0x02A0 2298 - 0x02A0 23FF

0x02A0 2400 - 0x02A0 2497

0x02A0 2498 - 0x02A0 25FF

0x02A0 2600 - 0x02A0 2697

0x02A0 2698 - 0x02A0 27FF

0x02A0 2800 - 0x02A0 2897

0x02A0 2898 - 0x02A0 29FF

-

-

-

-

-

QEER

QEECR

QEESR

QSER

QSECR

-

-

-

-

-

-

IER

IERH

IECR

IECRH

IESR

IESRH

IPR

IPRH

ICR

ICRH

IEVAL

-

QER

ACRONYM

ERH

ECR

ECRH

ESR

ESRH

CER

CERH

EER

EERH

EECR

EECRH

EESR

EESRH

SER

SERH

SECR

SECRH

REGISTER NAME

Event Register High

Event Clear Register

Event Clear Register High

Event Set Register

Event Set Register High

Chained Event Register

Chained Event Register High

Event Enable Register

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

Secondary Event Register High

Secondary Event Clear Register

Secondary Event Clear Register High

Reserved

Interrupt Enable Register

Interrupt Enable Register High

Interrupt Enable Clear Register

Interrupt Enable Clear Register High

Interrupt Enable Set Register

Interrupt Enable Set Register High

Interrupt Pending Register

Interrupt Pending Register High

Interrupt Clear Register

Interrupt Clear Register High

Interrupt Evaluate Register

Reserved

QDMA Event Register

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

Shadow Region 0 Channel Registers

Reserved


Reserved


Reserved


Reserved


Reserved






77

TMS320DM647

TMS320DM648


www.ti.com


HEX ADDRESS

0x02A0 2A00 - 0x02A0 2A97

0x02A0 2A98 - 0x02A0 2BFF

0x02A0 2C00 - 0x02A0 2C97

0x02A0 2C98 - 0x02A0 2DFF

0x02A0 2E00 - 0x02A0 2E97

0x02A0 2E98 - 0x02A0 2FFF

ACRONYM

-

-

-

-

-

-

REGISTER NAME


Reserved


Reserved


Reserved

Table 6-15

shows an abbreviation of the set of registers that make up the parameter set for each of 128

EDMA events. Each of the parameter register sets consist of eight 32-bit word entries.

Table 6-16

shows the parameter set entry registers with relative memory address locations within each of the parameter sets.


0x02A0 4000 - 0x02A0 401F

0x02A0 4020 - 0x02A0 403F

0x02A0 4040 - 0x02A0 405F

0x02A0 4060 - 0x02A0 407F

0x02A0 4080 - 0x02A0 409F

0x02A0 40A0 - 0x02A0 40BF

...

0x02A0 4FC0 - 0x02A0 4FDF

0x02A0 4FE0 - 0x02A0 4FFF

...

0x02A0 5FC0 - 0x02A0 5FDF

0x02A0 5FE0 - 0x02A0 5FFF

...

0x02A0 7FC0 - 0x02A0 7FDF

0x02A0 7FE0 - 0x02A0 7FFF

Table 6-15. EDMA Parameter Set RAM

DESCRIPTION

Parameters Set 0 (8 32-bit words)






...



...



...



78

HEX OFFSET ADDRESS

WITHIN THE PARAMETER SET

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

Table 6-16. Parameter Set Entries

ACRONYM

OPT

SRC

A_B_CNT

DST

SRC_DST_BIDX

LINK_BCNTRLD

SRC_DST_CIDX

CCNT

PARAMETER ENTRY

Option

Source Address

A Count, B Count

Destination Address

Source B Index, Destination B Index

Link Address, B Count Reload

Source C Index, Destination C Index

C Count


02A2 0000

02A2 0004

02A2 0008 - 02A2 00FC

Table 6-17. EDMA3 Transfer Controller 0 Registers

ACRONYM

PID

TCCFG

-

REGISTER NAME

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved






TMS320DM647



Table 6-17. EDMA3 Transfer Controller 0 Registers (continued)


02A2 0100

02A2 0104 - 02A2 011C

02A2 0120

02A2 0124

02A2 0128

02A2 012C

02A2 0130

02A2 0134 - 02A2 013C

02A2 0140

02A2 0144 - 02A2 023C

02A2 0240

02A2 0244

02A2 0248

02A2 024C

02A2 0250

02A2 0254

02A2 0258

02A2 025C

02A2 0260

02A2 0264 - 02A2 027C

02A2 0280

02A2 0284

02A2 0288

02A2 028C - 02A2 02FC

02A2 0300

02A2 0304

02A2 0308

02A2 030C

02A2 0310

02A2 0314

02A2 0318 - 02A2 033C

02A2 0340

02A2 0344

02A2 0348

02A2 034C

02A2 0350

02A2 0354

02A2 0358 - 02A2 037C

02A2 0380

02A2 0384

02A2 0388

02A2 038C

02A2 0390

02A2 0394

02A2 0398 - 02A2 03BC

02A2 03C0

02A2 03C4

ACRONYM

TCSTAT

-

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

RDRATE

-

SAOPT

REGISTER NAME

EDMA3TC Channel Status Register

Reserved

Error Register

Error Enable Register

Error Clear Register

Error Details Register

Error Interrupt Command Register

Reserved

Read Rate Register

Reserved

Source Active Options Register

SASRC

SACNT

SADST

SABIDX

SAMPPRXY

Source Active Source Address Register

Source Active Count Register

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

SACNTRLD Source Active Count Reload Register

SASRCBREF Source Active Source Address B-Reference Register

SADSTBREF Source Active Destination Address B-Reference Register

-

DFCNTRLD

Reserved

Destination FIFO Set Count Reload

DFSRCBREF Destination FIFO Set Destination Address B Reference Register

DFDSTBREF Destination FIFO Set Destination Address B Reference Register

Reserved

DFOPT0

DFSRC0

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

DFCNT0

DFDST0

DFBIDX0

Destination FIFO Count Register 0

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

DFMPPRXY0 Destination FIFO Memory Protection Proxy Register 0

Reserved

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1







-

DFOPT2

Reserved


DFSRC2

DFCNT2



DFDST2 Destination FIFO Destination Address Register 2

DFBIDX2 Destination FIFO BIDX Register 2


-

DFOPT3

DFSRC3

Reserved








79

TMS320DM647

TMS320DM648




02A2 03C8

02A2 03CC

02A2 03D0

02A2 03D4

02A2 03D8 - 02A2 7FFF

ACRONYM

DFCNT3

REGISTER NAME





Reserved

80

www.ti.com


02A2 8000

02A2 8004

02A2 8008 - 02A2 80FC

02A2 8100

02A2 8104 - 02A2 811C

02A2 8120

02A2 8124

02A2 8128

02A2 812C

02A2 8130

02A2 8134 - 02A2 813C

02A2 8140

02A2 8144 - 02A2 823C

02A2 8240

02A2 8244

02A2 8248

02A2 824C

02A2 8250

02A2 8254

02A2 8258

02A2 825C

02A2 8260

02A2 8264 - 02A2 827C

02A2 8280

02A2 8284

02A2 8288

02A2 828C - 02A2 82FC

02A2 8300

02A2 8304

02A2 8308

02A2 830C

02A2 8310

02A2 8314

02A2 8318 - 02A2 833C

02A2 8340

02A2 8344

02A2 8348

02A2 834C

02A2 8350


ACRONYM

PID

TCCFG

-

TCSTAT

-

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

RDRATE

-

SAOPT

SASRC

SACNT

SADST

SABIDX

REGISTER NAME



Reserved


Reserved

Error Register





Reserved

Read Rate Register

Reserved






SAMPPRXY Source Active Memory Protection Proxy Register




Reserved

DFCNTRLD Destination FIFO Set Count Reload



-

DFOPT0

Reserved


DFSRC0

DFCNT0

DFDST0






-

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1

Reserved











TMS320DM647





02A2 8354

02A2 8358 - 02A2 837C

02A2 8380

02A2 8384

02A2 8388

02A2 838C

02A2 8390

02A2 8394

02A2 8398 - 02A2 83BC

02A2 83C0

02A2 83C4

02A2 83C8

02A2 83CC

02A2 83D0

02A2 83D4

02A2 83D8 - 02A2 FFFF

ACRONYM REGISTER NAME


-

DFOPT2

DFSRC2

DFCNT2

DFDST2

Reserved







Reserved

DFOPT3

DFSRC3



DFCNT3

DFDST3

DFBIDX3





Reserved


02A3 0000

02A3 0004

02A3 0008 - 02A3 00FC

02A3 0100

02A3 0104 - 02A3 011C

02A3 0120

02A3 0124

02A3 0128

02A3 012C

02A3 0130

02A3 0134 - 02A3 013C

02A3 0140

02A3 0144 - 02A3 023C

02A3 0240

02A3 0244

02A3 0248

02A3 024C

02A3 0250

02A3 0254

02A3 0258

02A3 025C

02A3 0260

02A3 0264 - 02A3 027C

02A3 0280

02A3 0284

02A3 0288

02A3 028C - 02A3 02FC

02A3 0300


ACRONYM

PID

TCCFG

-

TCSTAT

-

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

RDRATE

REGISTER NAME



Reserved


Reserved

Error Register





Reserved

Read Rate Register

-

SAOPT

SASRC

SACNT

SADST

Reserved





SABIDX

SAMPPRXY

SACNTRLD


Source Active Memory Protection Proxy Register

Source Active Count Reload Register



Reserved




Reserved

DFOPT0 Destination FIFO Options Register 0






81

TMS320DM647

TMS320DM648




02A3 0304

02A3 0308

02A3 030C

02A3 0310

02A3 0314

02A3 0318 - 02A3 033C

02A3 0340

02A3 0344

02A3 0348

02A3 034C

02A3 0350

02A3 0354

02A3 0358 - 02A3 037C

02A3 0380

02A3 0384

02A3 0388

02A3 038C

02A3 0390

02A3 0394

02A3 0398 - 02A3 03BC

02A3 03C0

02A3 03C4

02A3 03C8

02A3 03CC

02A3 03D0

02A3 03D4

02A3 03D8 - 02A3 7FFF

ACRONYM

DFSRC0

DFCNT0

DFDST0

DFBIDX0

REGISTER NAME






Reserved

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1







-

DFOPT2

Reserved


DFSRC2

DFCNT2






-

DFOPT3

Reserved


DFSRC3

DFCNT3

DFDST3






Reserved

82

www.ti.com


02A3 8000

02A3 8004

02A3 8008 - 02A3 80FC

02A3 8100

02A3 8104 - 02A3 811C

02A3 8120

02A3 8124

02A3 8128

02A3 812C

02A3 8130

02A3 8134 - 02A3 813C

02A3 8140

02A3 8144 - 02A3 823C

02A3 8240

02A3 8244

02A3 8248

02A3 824C


ACRONYM

PID

TCCFG

-

TCSTAT

-

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

RDRATE

-

SAOPT

SASRC

SACNT

SADST

REGISTER NAME



Reserved


Reserved

Error Register





Reserved

Read Rate Register

Reserved










TMS320DM647





02A3 8250

02A3 8254

02A3 8258

02A3 825C

02A3 8260

02A3 8264 - 02A3 827C

02A3 8280

02A3 8284

02A3 8288

02A3 828C - 02A3 82FC

02A3 8300

02A3 8304

02A3 8308

02A3 830C

02A3 8310

02A3 8314

02A3 8318 - 02A3 833C

02A3 8340

02A3 8344

02A3 8348

02A3 834C

02A3 8350

02A3 8354

02A3 8358 - 02A3 837C

02A3 8380

02A3 8384

02A3 8388

02A3 838C

02A3 8390

02A3 8394

02A3 8398 - 02A3 83BC

02A3 83C0

02A3 83C4

02A3 83C8

02A3 83CC

02A3 83D0

02A3 83D4

02A3 83D8 - 02A3 FFFF

ACRONYM

SABIDX

REGISTER NAME


SAMPPRXY Source Active Memory Protection Proxy Register




Reserved




-

DFOPT0

Reserved


DFSRC0

DFCNT0

DFDST0






-

DFOPT1

DFSRC1

DFCNT1

DFDST1

Reserved







Reserved

DFOPT2

DFSRC2



DFCNT2

DFDST2

DFBIDX2





Reserved

DFOPT3

DFSRC3

DFCNT3




DFDST3

DFBIDX3




Reserved






83

TMS320DM647

TMS320DM648


www.ti.com

6.7

Reset Controller

The reset controller detects the different types of resets supported on the device and manages the distribution of those resets throughout the device.

The device has several types of resets: power-on reset, warm reset, max reset and system reset.

Table 6-

21

explains further the types of reset, the reset initiator, and the effects of each reset on the chip. See

Section 6.7.9

for more information on the effects of each reset on the PLL controllers and their clocks.

TYPE

Power-on Reset

Warm Reset

Max Reset

System Reset

POR pin

RESET pin

Emulator

Table 6-21. Device-Level Reset Types

INITIATOR

PCI via the PRST pin

EFFECT(s)

Resets the entire chip including the test and emulation logic

Resets everything except for the test and emulation logic and the

Ethernet Subsystem

Same as a warm reset

A system reset maintains memory contents and does not reset the test and emulation circuit and the Ethernet Subsystem. The device configuration pins are also not re-latched and system reset does not affect the state of the peripherals (enable/disable).

In addition to device-level global resets, the PSC provides the capability to cause local resets to peripherals and/or the CPU.

6.7.1

Power-on Reset (POR Pin)

Power-on reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test and emulation logic. Power-on reset is also referred to as a cold reset since the device usually goes through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. Note that a device power-up cycle is not required to initiate a power-on reset.

The following sequence must be followed during a power-on reset:

1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted

(driven low). While POR is asserted, all pins will be in high-impedance mode. After the POR pin is deasserted (driven high), all Z-group pins, low-group pins, and high-group pins are set to their reset state and will remain at their reset state until configured by their respective peripheral. The clock and reset of each peripheral is determined by the default settings of the power and sleep controller (PSC).

2. Once all the power supplies are within valid operating conditions, the POR pin must remain asserted

(low) for a minimum number of 256 CLKIN2 cycles. The PLL1 controller input clock, CLKIN1, and the

PCI input clock, PCLK, must be valid during this time. PCLK is needed only if the PCI module is being used. If the DDR2 memory controller and the Ethernet Subsystem are not needed, CLKIN2 can be tied low and REFCLKP/REFCLKN can be connected to V

SS and CV

DD respectively. In this case, the POR pin must remain asserted (low) for a minimum of 256 CLKIN1 cycles after all power supplies have reached valid operating conditions. Within the low period of the POR pin, the following occurs:

(a) The reset signals flow to the entire chip (including the test and emulation logic), resetting modules that use reset asynchronously.

(b) The PLL1 controller clocks are started at the frequency of the system reference clock. The clocks are propagated throughout the chip to reset modules that use reset synchronously. By default,

PLL1 is in reset and unlocked.

(c) The PLL2 controller clocks are started at the frequency of the system reference clock. PLL2 is held in reset. Since the PLL2 controller always operates in PLL mode, the system reference clock and all the system clocks are invalid at this point.

(d) The RESETSTAT pin stays asserted (low), indicating the device is in reset.

3. The POR pin may now be deasserted (driven high). When the POR pin is deasserted, the configuration pin values are latched, and the PLL controllers change their system clocks to their default divide-down values. PLL2 is taken out of reset and automatically starts its locking sequence. Other

84






TMS320DM647


SPRS372H – MAY 2007 – REVISED APRIL 2012 device initialization is also started.

4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time,

PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their default divide-by settings.

The device is now out of reset; device execution begins as dictated by the selected boot mode.

6.7.2

Warm Reset (RESET Pin)

A warm reset has the same effect as a power-on reset, except that in this case, the test and emulation logic are not reset.

The following sequence must be followed during a warm reset:

1. Hold the RESET pin low for a minimum of 24 CLKIN1 cycles. Within the low period of the RESET pin, the following occurs:

(a) The Z-group pins, low-group pins, and the high-group pins are set to their reset state

(b) The reset signals flow to the entire chip (excluding the test and emulation logic), resetting modules that use reset asynchronously

(c) The PLL Controllers are reset. PLL1 switches back to PLL bypass mode, resetting all their registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock. The PLL1 controller clocks start running at the frequency of the system reference clock. The clocks are propagated throughout the chip to reset modules that use reset synchronously.

(d) The RESETSTAT pin becomes active (low), indicating the device is in reset.

2. The RESET pin may now be released (driven inactive high). When the RESET pin is released, the configuration pin values are latched and the PLL controllers immediately change their system clocks to their default divide-down values. Other device initialization is also started.

After device initialization is complete, the RESETSTAT pin goes inactive (high). All system clocks are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks. After the pause the system clocks are restarted at their default divide-by settings.

The clock and reset of each peripheral is determined by the default settings of the PSC.

The device is now out of reset, device execution begins as dictated by the selected boot mode.

6.7.3

Maximum Reset

A maximum (max) reset is initiated by the emulator. The effects are the same as a warm reset, except the device boot and configuration pins are not re-latched. The emulator initiates a maximum reset via the

ICEPICK module. This ICEPICK initiated reset is nonmaskable.

The max reset sequence is as follows:

1. Max reset is initiated by the emulator. During this time, the following happens:

(a) The reset signals flow to the entire chip, resetting all the modules on chip except the test and emulation logic.

(b) The PLL controllers are reset, PLL1 switches back to PLL bypass mode, resetting all their registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock.

(c) The RESETSTAT pin becomes asserted (low), indicating the device is in reset.

2. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles. At the end of these 10 cycles, the RESETSTAT pin is deasserted (driven high). At this point, the following occurs:

(a) The I/O pins are controlled by the default peripherals (default peripherals are determined by

PINMUX register).

(b) The clock and reset of each peripheral is determined by the default settings of the power and sleep controller (PSC).






85

TMS320DM647

TMS320DM648


www.ti.com

(c) The C64x+ begins executing from DSPBOOTADDR (determined by bootmode selection).

After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not latched with a max reset, the previous values (as shown in the BOOTCFG register) are used to select the bootmode. For more details on the boot sequence, see the Using the

TMS320DM647/DM648 Bootloader Application Report (literature number SPRAAJ1 ). After the boot sequence, follow the software initialization sequence.

6.7.4

System Reset

A system reset maintains memory contents and does not reset the clock logic or the test and emulation circuitry. The device configuration pins are also not re-latched and the state of the peripherals

(enabled/disabled) is also not affected. A system reset is initiated by the PRST pin of PCI peripheral.

During a system reset, the following happens:

1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate through the system. Internal system clocks are not affected.

2. After the internal reset signal has propagated, the PLL controllers pause and restart their system clocks for about 10 cycles of their system reference clocks, but retain their configuration. The PLLs also remain locked.

3. The boot sequence is started after the system clocks are restarted. Since the configuration pins

(including the BOOTMODE[3:0] pins) are not latched with a system reset, the previous values, as shown in the BOOTCFG register, are used to select the boot mode.

6.7.5

Peripheral Local Reset

The user can configure the local reset and clock state of a peripheral through programming the PSC.

Table 6-2

identifies the LPSC numbers and the peripherals capable of being locally reset by the PSC. For more detailed information on the programming of these peripherals by the PSC, see the

TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide (literature number SPRUEU6 ).

6.7.6

Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTRL processes only the highest priority reset request. The reset request priorities are as follows (high to low):

• Power-on Reset

• Maximum Reset

• Warm Reset

• System Reset

86






TMS320DM647



6.7.7

Reset Controller Register

The reset type status (RSTYPE) register is the only register for the reset controller.

The RSTYPE register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The reset type status register is shown in

Figure 6-9

and described in

Table 6-22

.

Figure 6-9. Reset Type Status Register (RSTYPE)

31

Reserved

R-0

15

Reserved

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

4

16

3 2 1 0

SRST MRST WRST POR

R-0 R-0 R-0 R-0

Bit Field

31:4 Reserved

3 SRST

2

1

0

MRST

WRST

POR

Table 6-22. Reset Type Status Register (RSTYPE) Field Descriptions


Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

0

1

System reset

System Reset was not the last reset to occur.

System Reset was the last reset to occur.

Max reset

0

1

0

1

Max Reset was not the last reset to occur.

Max Reset was the last reset to occur.

Warm reset

Warm Reset was not the last reset to occur.

Warm Reset was the last reset to occur.

0

1

Power-on reset

Power-on Reset was not the last reset to occur.

Power-on Reset was the last reset to occur.

6.7.8

Pin Behaviors at Reset

During normal operation, devices pins are controlled by the selected peripheral. During device level global reset, the pin behaviors are classified into the following Reset Groups:

• Z Group: These pins are 3-stated when a device-level global reset source (e.g., POR, RESET, or Max

Reset) is asserted. When the reset source is de-asserted, these pins remain 3-stated until configured otherwise by their respective peripheral (after the peripheral is enabled by the PSC).

• Z/High Group: These pins are 3-stated when a device-level global reset source (e.g., POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins drive a logic High.

• Z/Low Group: These pins are 3-stated when a device-level global reset source (e.g. POR, RESET, or

Max Reset) is asserted. When the reset source is de-asserted, these pins drive a logic Low.

• DDR2 Z/High Group: These pins are 3-stated when a device-level global reset source (e.g. POR,

RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven High.

• DDR2 Low/High Group: These pins are driven Low when a device-level global reset source (e.g.

POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven

High.

• DDR2 High/Low Group: These pins are driven High when a device-level global reset source (e.g.

POR, RESET, or Max Reset) is asserted. When the reset source is de-asserted, these pins are Driven

Low.






87

TMS320DM647

TMS320DM648


www.ti.com

• Clock Group: These clock pins are toggling by default. They pause momentarily before RESETSTAT is de-asserted (high).

Table 6-23

lists the Reset Group for each pin.

Table 6-23. Pin Behaviors at Reset

NMI

RESET

POR

AD00/HD00

AD01/HD01

AD02/HD02

AD03/HD03

AD04/HD04

AD05/HD05

AD06/HD06

AD07/HD07

AD08/HD08

AD09/HD09

AD10/HA10

AD11/HD11

AD12/HD12

AD13/HD13

AD14/HD14

AD15/HD15

AD16/HD16

AD17/HD17

EMU2

EMU3

EMU4

EMU5

EMU6

EMU7

EMU8

EMU9

EMU10

EMU11

Pin Name

CLKIN1

CLKIN2

REFCLKN

REFCLKP

SYSCLK5

TCLK

TDI

TDO

TMS

TRST

EMU0

EMU1

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Reset Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

88






www.ti.com

TMS320DM647

TMS320DM648


Table 6-23. Pin Behaviors at Reset (continued)

PCBE3/GP07

PCLK/HHWIL

PGNT/GPO0

PRST/GPO1

PINTA/GPO2

PREQ/GPO3

PTRDY/GPO5

PIDSEL/GPO6

DEVICEENABLE0/AEA20

EMIBWIDTH/AEA22

FASTBOOT/AEA21

UHPIEN

HPIWIDTH/AEA16

RSV_BOOT/AEA15

PCI66/AEA18

BOOTMODE0/AEA11

BOOTMODE1/AEA12

BOOTMODE2/AEA13

BOOTMODE3/AEA14

SCL

SDA

SGMII0RXN

SGMII0RXP

SGMII1RXN

SGMII1RXP

SGMII0TXN

Pin Name

AD18/HS18

AD19/HD19

AD20/HD20

AD21/HD21

AD22/HD22

AD23/HD23

AD24/HD24

AD25/HS25

AD26/HD26

AD27/AD27

AD28/HD28

AD29/HD29

AD30/HD30

AD31/HD31

PPAR/HAS

PSTOP/HCNTL0

PDEVSEL/HCNTL1

PPERR/HCS

PSERR/HDS1

PCBE0/GP04

PCBE2/HR/W

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Reset Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group






89

TMS320DM647

TMS320DM648



AXR2

AXR3

AXR4

AXR5

AXR6

AXR7

STCLK/AXR8

VDAC/AXR9

AMUTEIN

AMUTE

VP0CLK0

VP0CLK1

VP0CTL0

VP0CTL1

VP0CTL2

VP0D02

VP0D03

VP0D04

VP0D05

VP0D06

VP0D07

VP0D08

VP0D09

VP0D12/GP12

VP0D13/GP13

VP0D14/GP14

Pin Name

SGMII0TXP

SGMII1TXN

SGMII1TXP

MDIO

SPICLK

SPICS1/UARTTX

SPICS2/UARTRX

SPIDI/UARTRTS

SPIDO/UARTCTS

T0INP12/GP08

T0OUT12/GP09

T1INPL/GP10

T1OUT12/GP11

AHCLKR

ALHCLKX

ACLKR

ACLKX

AFSR

AFSX

AXR0

AXR1

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Reset Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

90

www.ti.com






www.ti.com

TMS320DM647

TMS320DM648



VP1D15/GP27

VP1D16/GP28

VP1D17/GP29

VP1D18/GP30

VP1D19/GP31

VP2CLK0

VP2CLK1/VCLK

VP2CTL0

VP2CTL1

VP2CTL2/SCRUN

VP2D02

VP2D03

VP2D04

VP2D05

VP2D06

VP2D07

VP2D08

VP2D09

VP2D12/VRXD0

VP2D13/VRXD1

VP2D14/VRXD2

VP2D15/VRXD3

VP3CLK1/AECLKOUT

VP3CTL0/AAWE/ASWE

VP3CTL1/AR/W

VP3CTL2/AAOE/ASOE

Pin Name

VP0D15/GP15

VP0D16

VP0D17

VP0D18

VP0D19

VP1CLK0

VP1CLK1

VP1CTL0

VP1CTL1

VP1CTL2

VP1D02/GP16

VP1D03/GP17

VP1D04/GP18

VP1D05/GP19

VP1D06/GP20

VP1D07/GP21

VP1D08/GP22

VP1D09/GP23

VP1D12/GP24

VP1D13/GP25

VP1D14/GP26

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Reset Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group






91

TMS320DM647

TMS320DM648



VP4D03/ABE01

VP4D04/AEA10

VP4D05

VP4D06/ACE2

VP4D07/ACE3

VP4D08/AEA00

VP4D09/AEA01

VP4D12/AEA02

VP4D13/AEA03

VP4D14/AEA04

VP4D15/AEA05

VP4D16/AEA06

VP4D17/AEA07

VP4D18/AEA08

VP4D19/AEA09

AEA23

AEA19

AEA17

MDCLK

VP4CLK0/AARDY

PFRAME/HINT

PIRDY/HRDY

VP2D16/VTXD0

VP2D17/VTXD1

VP2D18/VTXD2

VP2D19/VTXD3

Pin Name

VP3D02/AED00

VP3D03/AED01

VP3D04/AED02

VP3D05/AED03

VP3D06/AED04

VP3D07/AED05

VP3D08/AED06

VP3D09/AED07

VP3D12/AED08

VP3D13/AED09

VP3D14/AED10

VP3D15/AED11

VP3D16/AED12

VP3D17/AED13

VP3D18/AED14

VP3D19/AED15

VP4CLK1

VP4CTL0/ABA0

VP4CTL1/ABA1

VP4CTL2/ASADS/ASRE

VP4D02/ABE00

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z/High Group

Z/High Group

Z/High Group

Z/Low Group

Z/Low Group

Z/Low Group

Z/Low Group

Z/Low Group

Reset Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

Z Group

92

www.ti.com






www.ti.com

TMS320DM647

TMS320DM648



DDR_D21

DDR_D22

DDR_D23

DDR_D24

DDR_D25

DDR_D26

DDR_D27

DDR_D28

DDR_D29

DDR_D30

DDR_D31

DDR_DQGATE1

DDR_DQGATE3

DDR_DQS[0]P

DDR_DQS[1]P

DDR_DQS[2]P

DDR_DQS[3]P

DDR_DQS[0]N

DDR_DQS[1]N

DDR_DQS[2]N

DDR_DQS[3]N

DDR_DQM[0]

DDR_DQM[1]

DDR_DQM[2]

DDR_DQM[3]

DDR_CAS

DDR_D11

DDR_D12

DDR_D13

DDR_D14

DDR_D15

DDR_D16

DDR_D17

DDR_D18

DDR_D19

DDR_D20

Pin Name

DDR_D00

DDR_D01

DDR_D02

DDR_D03

DDR_D04

DDR_D05

DDR_D06

DDR_D07

DDR_D08

DDR_D09

DDR_D10

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z/High Group

DDR2 Z/High Group

DDR2 Z/High Group

DDR2 Z/High Group

DDR2 High Group

Reset Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group

DDR2 Z Group






93

TMS320DM647

TMS320DM648



Pin Name

DDR_RAS

DDR_WE

DDR_A00

DDR_A01

DDR_A02

DDR_A03

DDR_A04

DDR_A05

DDR_A06

DDR_A07

DDR_A08

DDR_A09

DDR_A10

DDR_A11

DDR_A12

DDR_A13

DDR_ODT0

DDR_ODT1

DDR_CKE

DDR_DQGATE0

DDR_DQGATE2

DDR_BA[0]

DDR_BA[1]

DDR_BA[2]

DDR_CS

DDR_CLKP

DDR_CLKN

VP3CLK0/AECLKIN

RESETSTAT

Reset Group

DDR2 High Group

DDR2 High Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low Group

DDR2 Low/High Group

DDR2 Low/High Group

DDR2 Low/High Group

DDR2 High/Low Group

Clock

Clock

Clock

Reflects POR or RESET value

6.7.9

Reset Electrical Data/Timing

NOTE

If a configuration pin must be routed out from the device, the internal pullup/pulldown

(IPU/IPD) resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor.

www.ti.com

NO.

5 t w(POR)

6 t w(RESET)

7 t su(boot)

Table 6-24. Timing Requirements for Reset

(1) (2)

(see

Figure 6-10 )

Pulse duration, POR low

(3)

Pulse duration, RESET low

Setup time, boot mode and configuration pins valid before POR high or

RESET high

(4)

720, 800, 900, 1100

MIN

256D

MAX

24C

6P

UNIT

ns ns ns

(1) C = 1/CLKIN1 clock frequency in ns

(2) D = 1/CLKIN2 clock frequency in ns

(3) If CLKIN2 is not used, t w(POR) must be measured in terms of CLKIN1 cycles; otherwise, use the slower of the CLKIN1,CLKIN2 cycles.

(4) P = 1/CPU clock frequency in nanoseconds

94






TMS320DM647


NO.

8 t h(boot)


Table 6-24. Timing Requirements for Reset

(1) (2)

(see

Figure 6-10 ) (continued)

720, 800, 900, 1100

MIN MAX

Hold time, boot mode and configuration pins valid after POR high or RESET high

(4)

6P

UNIT

ns

Table 6-25. Switching Characteristics Over Recommended Operating Conditions During Reset

(see

Figure 6-10 )

(1)

NO.

PARAMETER

720, 800, 900, 1100

MIN MAX

1500C

UNIT

9 t d(PORH-RSTATH)

Delay time, POR high AND RESET high to RESETSTAT high ns

(1) C = 1/CLKIN1 clock frequency in ns.

• Z group consists of: all I/O/Z and O/Z pins, except for Low and High group pins. Pins become high impedance as soon as their respective power supply has reached normal operating conditions. Pins remain in high impedance until configured otherwise by their respective peripherals.

• Low group consists of pins that become low as soon as their respective power supply has reached normal operating conditions. Pins remain low until configured otherwise by their respective peripheral.

• High group consists of pins that become high as soon as their respective power supply has reached normal operating conditions. Pins remain high until configured otherwise by their respective peripheral.

• All peripherals must be enabled through software following a power-on reset; for more details, see

Section 6.7.1

, Power-on Reset.

• For power-supply sequence requirements, see

Section 6.3.1

.

A.

RESET should be used only after the device has been powered up. For more details on the use of the RESET pin, see

Section 6.7

, Reset Controller.

B.

A reset signal is generated internally during a Warm Reset. This internal reset signal has the same effect as the

RESET pin during a Warm Reset.

C.

Boot and Device Configuration Inputs (during reset) include AEA[22:11], and UHPIEN.

Figure 6-10. Warm Reset and Max Reset Timing






95

TMS320DM647

TMS320DM648


www.ti.com

6.8

Interrupts

The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable. Also, the interrupt controller controls the generation of the CPU exception, NMI, and emulation interrupts and the generation of AEG events.

Table 6-27

summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP interrupt control, see TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide (literature number SPRUEU6 ).

Table 6-26. DSP Interrupt Events

INTERRUPT SOURCE DSP

INTERRUPT

EVENT NUMBER

0

1

2

3

4-8

9

25

26

27

28

29

20

21

22

23

24

15

16

17

18

19

10

11

12

13

14

36

37

38

39

40

30 -31

32

33

34

35

96

EVENT

EVT0

EVT1

EVT2

EVT33

EMU_DTDMA

Reserved

EMU_RTDXRX

EMU_RTDXTX

IDMA0 EMC

IDMA1 EMC

DSPINT

I2CINT

Reserved

AEASYNCERR event

TINT2L

TINT2H

TINT3L

TINT3H

PSCINT

TPCC_GINT

SPIINT0

SPIINT1

DSQINT

IMXINT

VLCDINT

Reserved

RX_PULSE

RX_THRESH_PULSE

TX_PULSE

MISC_PULSE

UART_INT

VP0_INT

VP1_INT

VP2_INT

VP3_INT

Output of event combiner 0, for events 1 – 31




Reserved

ECM interrupt for:

• Host scan access event

• DTDMA transfer complete event

• AET interrupt event

Reserved

RTDX receive complete event

RTDX transmit complete event

C64x+ EMC 0 event

C64x+ EMC 1 event

Host (PCI/HPI) to DSP interrupt event

I2C interrupt event

Reserved

EMIFA Error Interrupt event

Timer interrupt low event

Timer interrupt high event



PSC-ALLINT event

EDMA3 channel global completion interrupt event

SPI Interrupt

SPI Interrupt

VICP – Sqr (DSP int)

VICP – IMX

VICP - VLCD

Reserved

Ethernet Subsystem RX pulse interrupt event

Ethernet Subsystem RX threshold interrupt event

Ethernet Subsystem TX pulse interrupt event

Ethernet Subsystem MISC pulse interrupt event

UART Interrupt

VP0 Interrupt

VP1 Interrupt

VP2 Interrupt

VP3 Interrupt






TMS320DM647


EVENT


Table 6-26. DSP Interrupt Events (continued)

INTERRUPT SOURCE

81

82

83

84

85

76

77

78

79

80

86

87

88

89

90

71

72

73

74

75

66

67

68

69

70

61

62

63

64

65

56

57

58

59

60

45-49

50

51

52

53

54

55

DSP

INTERRUPT

EVENT NUMBER

41

42

43

44

VP4_INT

GPIO_BNK1_INT

AXINT

ARINT

VINT

GPINT0

GPINT1

GPINT2

GPINT3

GPINT4

GPINT5

GPINT6

GPINT7

GPINT8

GPINT9

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

GPINT15

TINT0L

TINT0H

TINT1L

TINT1H

EDMA3CC_INT0

EDMA3CC_INT1

EDMA3CC_INT2

EDMA3CC_INT3

EDMA3CC_INT4

EDMA3CC_INT5

EDMA3CC_INT6

EDMA3CC_INT7

EDMA3CC_ERRINT

EDMA3CC_MPINT

EDMA3TC0_ERRINT

EDMA3TC1_ERRINT

EDMA3TC2_ERRINT

EDMA3TC3_ERRINT

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

VP4 Interrupt

(GPIO16:31) GPIO Bank 1 Interrupt event

TX Interrupt McASP

RX Interrupt McASP

Reserved

VLYNQ Pulse Interrupt event

GPIO Interrupt event












GPIO Interrupt

GPIO Interrupt







EDMA3CC Completion Interrupt - Mask0 event

EDMA3CC Completion Interrupt – Mask1 event







EDMA3CC Error Interrupt event

EDMA3CC Memory Protection Interrupt event

EDMA3TC0 Error Interrupt event




Reserved

Reserved

Reserved

Reserved

Reserved

Reserved






97

TMS320DM647

TMS320DM648


EVENT

Table 6-26. DSP Interrupt Events (continued)

INTERRUPT SOURCE

123

124

125

126

127

118

119

120

121

122

102 - 112

113

114-115

116

117

95

96

97

98

99

100

101

DSP

INTERRUPT

EVENT NUMBER

91

92

93

94

Reserved

Reserved

Reserved

Reserved

Reserved

INTERR

EMC_IDMAERR

Reserved

Reserved

EFIINTA

EFIINTB

Reserved

L1P_ED

Reserved

L2_ED1

L2_ED2

PDC_INT

Reserved

L1P_CMPA

L1P_DMPA

L1D_CMPA

L1D_DMPA

L2_CMPA

L2_DMPA

IDMA_CMPA

IDMA_BUSERR

Reserved

Reserved

Reserved

Reserved

Reserved

C64x+ Interrupt Controller Dropped CPU Interrupt Event

C64x+ EMC Invalid IDMA Parameters event

Reserved

Reserved

EFI Interrupt from side A event

EFI Interrupt from side B event

Reserved

L1P Single bit error detected during DMA read event

Reserved

L2 single bit error detected event

L2 two bit error detected event

Power Down sleep interrupt event

Reserved

L1P CPU memory protection fault event

L1P DMA memory protection fault event

L1D CPU memory protection fault event

L1D DMA memory protection fault event

L2 CPU memory protection fault event

L2 DMA memory protection fault event

IDMA CPU memory protection fault event

IDMA bus error interrupt event

www.ti.com

98






www.ti.com

TMS320DM647

TMS320DM648


0x0180 00C8

0x0180 00CC

0x0180 00E0

0x0180 00E4

0x0180 00E8

0x0180 00EC

0x0180 0104

0x0180 0108

0x0180 010C

0x0180 0140

0x0180 0144

0x0180 0180

0x0180 0184

0x0180 0188

0x0180 01C0

HEX ADDRESS

0x0180 0000

0x0180 0004

0x0180 0008

0x0180 000C

0x0180 0020

0x0180 0024

0x0180 0028

0x0180 002C

0x0180 0040

0x0180 0044

0x0180 0048

0x0180 004C

0x0180 0080

0x0180 0084

0x0180 0088

0x0180 008C

0x0180 00A0

0x0180 00A4

0x0180 00A8

0x0180 00AC

0x0180 00C0

0x0180 00C4

Table 6-27. C64x+ Interrupt Controller Registers

EXPMASK2

EXPMASK3

MEXPFLAG0

MEXPFLAG1

MEXPFLAG2

MEXPFLAG3

INTMUX1

INTMUX2

INTMUX3

AEGMUX0

AEGMUX1

INTXSTAT

INTXCLR

INTDMASK

EVTASRT

ACRONYM

EVTFLAG0

EVTFLAG1

EVTFLAG2

EVTFLAG3

EVTSET0

EVTSET1

EVTSET2

EVTSET3

EVTCLR0

EVTCLR1

EVTCLR2

EVTCLR3

EVTMASK0

EVTMASK1

EVTMASK2

EVTMASK3

MEVTFLAG0

MEVTFLAG1

MEVTFLAG2

MEVTFLAG3

EXPMASK0

EXPMASK1

REGISTER DESCRIPTION

Event flag register 0




Event set register 0




Event clear register 0




Event mask register 0




Masked event flag register 0




Exception mask register 0




Masked exception flag register 0




Interrupt mux register 1



Advanced event generator mux register 0

Advanced event generator mux register 1

Interrupt exception status

Interrupt exception clear

Dropped interrupt mask register

Event assert register






99

TMS320DM647

TMS320DM648


www.ti.com

6.9

DDR2 Memory Controller

The 32-bit DDR2 memory controller bus of the device is used to interface to JESD79D-2A standardcompliant DDR2 SDRAM devices. The DDR2 external bus interfaces only to DDR2 SDRAM devices; it does not share the bus with any other types of peripherals. The decoupling of DDR2 memories from other devices simplifies board design and provides I/O concurrency from a second external memory interface,

EMIFA.

The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum throughput of the DDR2 bus. The data rate of the DDR2 bus is equal to the CLKIN2 frequency multiplied by 20. The internal data bus clock frequency of the DDR2 memory controller is fixed at a divide-by-three ratio of the CPU frequency. The maximum DDR2 throughput is determined by the smaller of the two bus frequencies. For example, if the internal data bus frequency is 300 MHz (CPU frequency is 900 MHz) and the DDR2 data rate is 533 MHz (266 MHz clock rate as CLKIN2 frequency is 26.6 MHz), the maximum data rate achievable by the DDR2 memory controller is 2.13 Gbytes/sec.

6.9.1

DDR2 Memory Controller Device-Specific Information

The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces such as EMIF and HPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models.

For the DDR2 memory bus, the approach is to specify compatible DDR2 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has performed the simulation and system characterization to be sure all DDR2 interface timings in this solution are met.

The ODT[1:0] pins of the memory controller must be left unconnected. The ODT pins on the DDR2 memory device(s) must be connected to ground.

The DDR2 memory controller on the device supports the following memory topologies:

• A 32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices.

• A 16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device.

A race condition may exist when certain masters write data to the DDR2 memory controller. For example, if master A passes a software message via a buffer in external memory and does not wait for indication that the write completes, when master B attempts to read the software message, then the master B read may bypass the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.

Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

1. Perform the required write.

2. Perform a dummy write to the DDR2 memory controller module ID and revision register.

3. Perform a dummy read to the DDR2 memory controller module ID and revision register.

4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of the read in step 3 ensures that the previous write was done.

The master peripherals that need to implement this workaround are HPI, PCI, and VLYNQ.

100






TMS320DM647



6.9.2

DDR2 Memory Controller Peripheral Registers

Table 6-28. DDR2 Memory Controller Registers

(1)


0x7800 0000

0x7800 0004

0x7800 0008

0x7800 000C

0x7800 0010

0x7800 0014

0x7800 0018

0x7800 0020

0x7800 0024 - 0x7800 004C

0x7800 0050 - 0x7800 0078

0x7800 007C - 0x7800 00BC

0x7800 00C0 - 0x7800 00E0

0x7800 00E4

0x7800 00E8 - 0x7800 00FC

0x7800 0100 - 0x7FFF FFFF

ACRONYM

MIDR

DMCSTAT

SDCFG

SDRFC

SDTIM1

SDTIM2

-

BPRIO

-

-

-

-

DMCCTL

-

-

Reserved

Reserved

DDR2 Memory Controller Control Register

Reserved

Reserved

REGISTER NAME

DDR2 Memory Controller Module and Revision Register

DDR2 Memory Controller Status Register

DDR2 Memory Controller SDRAM Configuration Register

DDR2 Memory Controller SDRAM Refresh Control Register

DDR2 Memory Controller SDRAM Timing 1 Register

DDR2 Memory Controller SDRAM Timing 2 Register

Reserved

DDR2 Memory Controller Burst Priority Register

Reserved

Reserved

(1) For details about the DDR2 registers and their modes, see the TMS320DM647/DM648 DSP DDR2 Memory Controller (DDR2) User's

Guide (literature number SPRUEK5 ).

6.9.3

DDR2 Interface

This section provides the timing information for the DDR2 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2 specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification ( SPRAAV0 ).

6.9.3.1

DDR2 Interface Schematic

Figure 6-11

shows the DDR2 interface schematic for a x32 DDR2 memory system. The x16 DDR2 system schematic shown in

Figure 6-12

is identical except that the high word DDR2 device is deleted.

6.9.3.2

Compatible JEDEC DDR2 Devices

Table 6-29

shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.

Generally, the DDR2 interface is compatible with x16 DDR2-533 speed grade DDR2 devices.

Table 6-29. Compatible JEDEC DDR2 Devices

NO.

1

2

3

4

PARAMETER

JEDEC DDR2 Device Speed Grade

(1)

JEDEC DDR2 Device Bit Width

JEDEC DDR2 Device Count

(2)

JEDEC DDR2 Device Ball Count

(3)

MIN

DDR2-533 x16

1

84

MAX

x16

2

92

UNIT

Bits

Devices

Balls

(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.

(2) One DDR2 device is used for 16-bit DDR2 memory system. Two DDR2 devices are used for 32-bit DDR2 memory system.

(3) 92 ball devices retained for legacy support. New designs will migrate to 84 ball DDR2 devices. Electrically, the 92 and 84 ball DDR2 devices are the same.






101

TMS320DM647

TMS320DM648


www.ti.com

DM647/DM648

DDR_ODT0

DDR_D00

NC

DDR_D7

DDR_DQM0

DDR_DQS0

DDR_DQS0

DDR_D08

DDR_D15

DDR_DQM1

DDR_DQS1

DDR_DQS1

DDR_DQGATE0

DDR_DQGATE1

DDR_DQGATE2

DDR_DQGATE3

DDR_ODT1

DDR_D16

T

T

NC

DDR_D23

DDR_DQM2

DDR_DQS2

DDR_DQS2

DDR_D24

DDR_D31

DDR_DQM3

DDR_DQS3

DDR_DQS3

DDR_BA0

T

DDR_BA2

DDR_A00

T

T

DDR_A13

DDR_CS0

DDR_CAS

DDR_RAS

BSDWE

DDR_CKE

DDR_CLK

DDR_CLK

DDR_VREF

T

T

T

T

T

T

T

T

0.1 µF

(B)

T

DDR2

ODT

BED0

T

T

T

T

T

BED0

LDM

LDQS

LDQS

BED7

T

T

T

T

BED15

UDM

UDQS

UDQS

BA0

BA2

A0

A13

CS

CAS

RAS

WE

CKE

CK

CK

VREF VREF

0.1 µF

(B)

0.1 µF

(B)

T

T

T

T

T

T

T

T

T

T

DDR2

ODT

BED0

BED7

LDM

LDQS

LDQS

BED8

BED15

UDM

UDQS

UDQS

BA0

BA2

A0

A13

CS

CAS

RAS

WE

CKE

CK

CK

VREF VREF

0.1 µF

0.1 µF

Vio 1.8

(A)

1 kΩ 1%

VREF

1 kΩ 1%

T

Terminator, if desired. See terminator comments.

A.

DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:

DM647/DM648.

B.

V io

1.8 is the power supply for the DDR2 memory interface.

C.

One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin.

Figure 6-11. 32-Bit DDR2 High-Level Schematic

102






TMS320DM647

TMS320DM648


www.ti.com

DM647/DM648

DDR_ODT0

DDR_D00

DDR_D7

DDR_DQM0

DDR_DQS0

DDR_DQS0

DDR_D08

DDR_D15

DDR_DQM1

DDR_DQS1

DDR_DQS1

DDR_DQGATE0

DDR_DQGATE1

DDR_DQGATE2

DDR_DQGATE3

DDR_ODT1

DDR_D16

NC

T

NC 1 kΩ

NC

NC

DDR_D23

DDR_DQM2

DDR_DQS2

DDR_DQS2

DDR_D24

NC

NC

1 kΩ

NC

1 kΩ

DDR_D31

DDR_DQM3

DDR_DQS3

DDR_DQS3

DDR_BA0

T

NC

NC

1 kΩ

1 kΩ

DDR_BA2

DDR_A00

DDR_A13

DDR_CS0

DDR_CAS

DDR_RAS

BSDWE

DDR_CKE

DDR_CLK

DDR_CLK

DDR_VREF

T

T

T

T

T

T

T

T

T

T

0.1 µF

(B)

Vio 1.8

(A)

Vio 1.8

(A)

T

T

T

T

T

T

T

T

T

T

DDR2

ODT

BED0

BED7

LDM

LDQS

LDQS

BED8

BED15

UDM

UDQS

UDQS

BA0

BA2

A0

A13

CS

CAS

RAS

WE

CKE

CK

CK

VREF VREF

0.1 µF

0.1 µF

Vio 1.8

(A)

1 kΩ 1%

VREF

1 kΩ 1%

0.1 µF

(B)

T

Terminator, if desired. See terminator comments.

A.


DM647/DM648.

B.

One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin.

C.

Vio 1.8 is the power supply for the DDR2 memory interface.

Figure 6-12. 16-Bit DDR2 High-Level Schematic






103

TMS320DM647

TMS320DM648


www.ti.com

6.9.3.3

PCB Stackup

The minimum stackup required for routing the device is a six-layer stack as shown in

Table 6-30

.

Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size of the PCB footprint.

LAYER

1

2

3

4

5

6

Table 6-30. Minimum PCB Stack Up

TYPE

Signal

Plane

Plane

Signal

Plane

Signal

Complete stack up specifications are provided in

Table 6-31

.

DESCRIPTION

Top routing mostly horizontal

Ground

Power

Internal routing

Ground

Bottom routing mostly vertical

Table 6-31. PCB Stack Up Specifications

4

5

6

7

8

NO.

PARAMETER

1 PCB Routing/Plane Layers

2

3

Signal Routing Layers

Full ground layers under DDR2 routing Region

Number of ground plane cuts allowed within DDR routing region

Number of ground reference planes required for each DDR2 routing layer

Number of layers between DDR2 routing layer and reference ground plane

8

9

10

11

12

13

PCB Routing Feature Size

PCB Trace Width w

PCB BGA escape via pad size

PCB BGA escape via hole size

DSP Device BGA pad size

(1)

DDR2 Device BGA pad size

(2)

Single Ended Impedance, Zo

Impedance Control

(3)

MIN

6

3

2

1

50

Z-5

(1) See the Flip Chip Ball Grid Array Package Reference Guide ( SPRU811 ) for DSP device BGA pad size.

(2) See the DDR2 device manufacturer documenation for the DDR2 device BGA pad size.

(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.

TYP

18

8

4

4

Z

MAX UNIT

0

0

75

Z+5

Mils

Mils

Mils

Mils

Ω

Ω

6.9.3.4

Placement

Figure 6-13

shows the required placement for the device as well as the DDR2 devices. The dimensions for

Figure 6-13

are defined in

Table 6-32 . The placement does not restrict the side of the PCB where the

devices are mounted. The purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For 16-bit DDR memory systems, the high word DDR2 device is omitted from the placement.

104






TMS320DM647

TMS320DM648


www.ti.com

X

A1

Y

OFFSET

Y

DDR2

Device

Y

OFFSET

DM648

A1

Recommended DDR2 Device

Orientation

A.


DM647/DM648.

Figure 6-13. DDR2 Device Placement

Table 6-32. Placement Specifications

NO.

PARAMETER

1 X

(1) (2)

2

3

4

Y

(1) (2)

Y Offset

(1) (2) (3)

DDR2 Keepout Region

(4)

5 Clearance from non-DDR2 signal to DDR2 Keepout Region

(5)

MIN MAX

1660

1280

650

4 w

(1) See

Figure 6-11

for dimension defintions.

(2) Measurements from center of DSP device to center of DDR2 device.

(3) For 16-bit memory systems, it is recommended that Y Offset be as small as possible.

(4) DDR2 Keepout region to encompass entire DDR2 routing area

(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.

UNIT

Mils

Mils

Mils

6.9.3.5

DDR2 Keep Out Region

The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep out region is defined for this purpose and is shown in

Figure 6-14 . The size of this region varies with the

placement and DDR routing. Additional clearances required for the keep out region are shown in

Table 6-

32 .

A1

DDR2 Device

A1

Figure 6-14. DDR2 Keepout Region






105

TMS320DM647

TMS320DM648


www.ti.com

NOTE

The region (see

Figure 6-14 ) should encompass all DDR2 circuitry and varies depending on

placement. Non-DDR2 signals should not be routed on the DDR signal layers within the

DDR2 keep out region. Non-DDR2 signals may be routed in the region provided they are routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region. In addition, the 1.8-V power plane should cover the entire keep out region.

6.9.3.6

Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.

Table 6-33

contains the minimum numbers and capacitance required for the bulk bypass capacitors. This table covers only the bypass needs of the DSP and DDR2 interfaces. Additional bulk bypass capacitance may be needed for other circuitry.

Table 6-33. Bulk Bypass Capacitors

NO.

PARAMETER

1 DV

DD18

Bulk Bypass Capacitor Count

(1)

2

3

DV

DD18

Bulk Bypass Total Capacitance

DDR#1 Bulk Bypass Capacitor Count

(2)

4

5

6

DDR#1 Bulk Bypass Total Capacitance

DDR#2 Bulk Bypass Capacitor Count

(2) (3)

DDR#2 Bulk Bypass Total Capacitance

(3)

MIN

3

30

1

10

1

10

MAX UNIT

Devices

μ F

Devices

μ F

Devices

μ F

(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed

(HS) bypass caps.

(2) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed

(HS) bypass caps.

(3) Only used on 32-bit wide DDR2 memory systems

6.9.3.7

High-Speed Bypass Capacitors

High-Speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR power, and

DSP/DDR ground connections.

Table 6-34

contains the specification for the HS bypass capacitors as well as for the power connections on the PCB.

6.9.3.8

Net Classes

Table 6-35

lists the clock net classes for the DDR2 interface.

Table 6-36

lists the signal net classes, and associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the termination and routing rules that follow.

Table 6-34. High-Speed Bypass Capacitors

NO.

PARAMETER

1 HS Bypass Capacitor Package Size

(1)

2 Distance from HS bypass capacitor to device being bypassed

3 Number of connection vias for each HS bypass capacitor

(2)

4 Trace length from bypass capacitor contact to connection via

5 Number of connection vias for each DDR2 device power or ground balls

6 Trace length from DDR2 device power ball to connection via

7 DV

DD18

HS Bypass Capacitor Count

(3)

8 DV

DD18

HS Bypass Capacitor Total Capacitance

MIN

2

1

1

20

1.2

MAX

0402

250

(1) L × W, 10 mil units ( i.e., a 0402 is a 40 × 20 mil surface mount capacitor)

(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.

(3) These devices should be placed as close as possible to the device being bypassed.

30

35

106

UNIT

10 Mils

Mils

Vias

Mils

Vias

Mils

Devices

μ F






TMS320DM647



Table 6-34. High-Speed Bypass Capacitors (continued)

NO.

PARAMETER

9 DDR#1 HS Bypass Capacitor Count

(3)

10 DDR#1 HS Bypass Capacitor Total Capacitance

11 DDR#2 HS Bypass Capacitor Count

(3) (4)

12 DDR#2 HS Bypass Capacitor Total Capacitance

(4)

(4) Only used on 32-bit wide DDR2 memory systems

MIN

8

0.4

8

0.4

Table 6-35. Clock Net Class Definitions

CLOCK NET CLASS

CK

DQS0

DQS1

DQS2

(1)

DQS3

(1)

DSP PIN NAMES

DDR_CLK/DDR_CLK

DDR_DQS0/DDR_DQS0

DDR_DQS1/DDR_DQS1

DDR_DQS2/DDR_DQS2

DDR_DQS3/DDR_DQS3

(1) Only used on 32-bit wide DDR2 memory systems.

MAX UNIT

Devices

μ F

Devices

μ F

Table 6-36. Signal Net Class Definitions

CLOCK NET CLASS ASSOCIATED CLOCK NET CLASS DSP PIN NAMES

ADDR_CTRL

DQ0

CK

DQS0

DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS,

DDR_WE, DDR_CKE

DDR_D[7:0], DDR_DQM0

DQ1

DQ2

(1)

DQ3

(1)

DQGATEL

DQGATEH

(1)

DQS1

DQS2

DQS3

CK, DQS0, DQS1

CK, DQS2, DQS3




DDR_DQGATE0, DDR_DQGATE1

DDR_DQGATE2, DDR_DQGATE3

(1) Only used on 32-bit wide DDR2 memory systems.

6.9.3.9

DDR2 Signal Termination

No terminations of any kind are required in order to meet signal integrity and overshoot requirements.

Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted.

Table 6-37

shows the specifications for the series terminators.

Table 6-37. DDR2 Signal Terminations

NO.

PARAMETER

1 CK Net Class

(1)

2

3

4

ADDR_CTRL Net Class

(1) (2) (3)

Data Byte Net Classes (DQS0-DQS3, DQ0-DQ3)

(1) (2) (3) (4)

DQGATE Net Classes (DQGATEL, DQGATEH)

(1) (2) (3)

MIN

0

0

0

0

TYP

22

22

10

(1) Only series termination is permitted, parallel or SST specifically disallowed.

(2) Terminator values larger than typical only recommended to address EMI issues.

(3) Termination value should be uniform across net class.

(4) When no termination is used on data lines (0 Ω s), the DDR2 devices must be programmed to operate in 60% strength mode.

MAX UNIT

10 Ω

Zo

Zo

Zo

Ω

Ω

Ω






107

TMS320DM647

TMS320DM648


6.9.3.10 VREF Routing

VREF is used as a reference by the input buffers of the DDR2 memories as well as the device’s. VREF is intended to be 1/2 the DDR2 power supply voltage and should be created using a resistive divider as shown in

Figure 6-11

. Other methods of creating VREF are not recommended.

Figure 6-15

shows the layout guidelines for VREF.

VREF Bypass Capacitor

www.ti.com

DDR2 Device

A1

VREF Nominal Minimum

Trace Width is 20 Mils

DM648

Device

A1

Neck down to minimum in BGA escape regions is acceptable. Narrowing to accommodate via congestion for short distances is also acceptable.

Best performance is obtained if the width of

VREF is maximized.

A.


DM647/DM648.

Figure 6-15. VREF Routing and Topology

6.9.3.11 DDR2 CK and ADDR_CTRL Routing

Figure 6-16

shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.

A1

T

A

DM648

A1

A.


DM647/DM648.

Figure 6-16. CK and ADDR_CTRL Routing and Topology

108






TMS320DM647



Table 6-38. CK and ADDR_CTRL Routing Specification

(1)

9

10

11

6

7

8

NO

1

4

5

2

3

PARAMETER

Center to center CK-CK spacing

CK A to B/A to C Skew Length Mismatch

(1)

CK B to C Skew Length Mismatch

Center to center CK to other DDR2 trace spacing

(2)

CK/ADDR_CTRL nominal trace length

(3)

ADDR_CTRL to CK Skew Length Mismatch

ADDR_CTRL to ADDR_CTRL Skew Length Mismatch

Center to center ADDR_CTRL to other DDR2 trace spacing

(2)

Center to center ADDR_CTRL to other ADDR_CTRL trace spacing

(2)

ADDR_CTRL A to B/A to C Skew Length Mismatch

(1)

ADDR_CTRL B to C Skew Length Mismatch

MIN

4w

CACLM-50

4w

3w

TYP

CACLM

MAX

2w

25

25

CACLM+50

100

100

100

100

UNIT

Mils

Mils

Mils

Mils

Mils

Mils

Mils

(1) Series terminator, if used, should be located closest to DSP.

(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

Figure 6-17

shows the topology and routing for the DQS and DQ net classes; the routes are point to point.

Skew matching across bytes is not needed nor recommended.

A1

T

T

E0

E1

DM648

T

E2

A1

T

E3

A.


DM647/DM648.

Figure 6-17. DQS and DQ Routing and Toplogy

Table 6-39. DQS and DQ Routing Specification

(1)

MIN

4

5

6

NO.

PARAMETER

1 Center to center DQS-DQS spacing

2

3

DQS E Skew Length Mismatch

Center to center DQS to other DDR2 trace spacing

(2)

DQS/DQ nominal trace length

(1) (3) (4) (5)

DQ to DQS Skew Length Mismatch

(3) (4) (5)

DQ to DQ Skew Length Mismatch

(3) (4) (5)

4 w

DQLM-50

TYP

DQLM

MAX

2 w

25

DQLM+50

100

100

UNIT

Mils

Mils

Mils

Mils

(1) Series terminator, if used, should be located closest to DDR.

(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(3) A 16-bit DDR memory system has two sets of data net classes, one for data byte 0, and one for data byte 1, each with an associated

DQS (2 DQSs).

(4) A 32-bit DDR memory system will have four sets of data net classes, one each for data bytes 0 through 3, and each associated with a

DQS (4 DQSs).

(5) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte

1.

109






TMS320DM647

TMS320DM648


www.ti.com

Table 6-39. DQS and DQ Routing Specification

(1)

(continued)

TYP NO.

PARAMETER

7 Center to center DQ to other DDR2 trace spacing

(2) (6)

8

9

Center to Center DQ to other DQ trace spacing

(7) (2)

DQ/DQS E Skew Length Mismatch

(3) (4) (5)

(6) DQs from other DQS domains are considered other DDR2 trace.

(7) DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.

MIN

4 w

3w

MAX

100

UNIT

Mils

Figure 6-18

shows the routing for the DQGATE net classes.

Table 6-40

contains the routing specification.

A1

T

T

DM648

A1

A.


DM647/DM648.

Figure 6-18. DQGATE Routing

Table 6-40. DQGATE Routing Specification

MIN NO.

PARAMETER

1 DQGATEL Length F

(1)

2 DQGATEH Length F

(2) (3)

3

4

Center to center DQGATE to any other trace spacing

DQS/DQ nominal trace length

4 w

DQLM - 50

5

6

DQGATEL Skew

(4)

DQGATEH Skew

(5) (3)

(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.

(2) CKB2B3 is the sum of the length of the CK net plus the average length of the DQS2 and DQS3 nets.

(3) Only used on 32-bit-wide DDR2 memory systems.

(4) Skew from CKB0B1

(5) Skew from CKB2B3

TYP

CKB0B1

CKB2B3

DQLM

MAX UNIT

DQLM + Mils

50

100 Mils

100 Mils

110






TMS320DM647



6.10 External Memory Interface A (EMIFA)

The EMIFA can interface to a variety of external devices or ASICs, including:

• Pipelined and flow-through synchronous-burst SRAM (SBSRAM)

• ZBT (zero bus turnaround) SRAM and late write SRAM

• Synchronous FIFOs

• Asynchronous memory, including SRAM, ROM, and Flash

6.10.1 EMIFA Device-Specific Information

Timing analysis must be done to verify all ac timing requirements are met. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all ac timing.

To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS

Models for Timing Analysis Application Report (literature number SPRA839 ).

To maintain signal integrity, serial termination resistors should be inserted into all EMIFA output signal lines.

A race condition may exist when certain masters write data to the EMIFA. For example, if master A passes a software message via a buffer in external memory and does not wait for indication that the write completes, when master B attempts to read the software message, then the master B read may bypass the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.

Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

1. Perform the required write.

2. Perform a dummy write to the EMIFA module ID and revision register.

3. Perform a dummy read to the EMIFA module ID and revision register.

4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of the read in step 3 ensures that the previous write was done.

6.10.2 EMIFA Peripheral Register Description(s)

For more information on the EMIF registers shown in

Table 6-41

, see TMS320DM647/DM648 DSP

External Memory Interface (EMIF) User's Guide (literature number SPRUEK6 ).


0x7000 0000

0x7000 0004

0x7000 0008

0x7000 000C - 0x7000 001C

0x7000 0020

0x7000 0024 - 0x7000 004C

0x7000 0050 - 0x7000 007C

0x7000 0080

0x7000 0084

0x7000 0088

0x7000 008C

0x7000 0090 - 0x7000 009C

0x7000 00A0

Table 6-41. EMIFA Registers

ACRONYM

MIDR

STAT

-

-

BPRIO

-

-

CE2CFG

CE3CFG

-

-

-

AWCC

REGISTER NAME

Module ID and Revision Register

Status Register

Reserved

Reserved

Burst Priority Register

Reserved

Reserved

EMIFA CE2 Configuration Register

EMIFA CE3 Configuration Register

Reserved

Reserved

Reserved

EMIFA Async Wait Cycle Configuration Register






111

TMS320DM647

TMS320DM648


www.ti.com


0x7000 00A4 - 0x7000 00BC

0x7000 00C0

0x7000 00C4

0x7000 00C8

0x7000 00CC

0x7000 00D0 - 0x7000 00DC

0x7000 00E0 - 0x77FF FFFF

Table 6-41. EMIFA Registers (continued)

ACRONYM

-

INTRAW

INTMSK

INTMSKSET

INTMSKCLR

-

-

REGISTER NAME

Reserved

EMIFA Interrupt RAW Register

EMIFA Interrupt Masked Register

EMIFA Interrupt Mask Set Register

EMIFA Interrupt Mask Clear Register

Reserved

Reserved

6.10.3 EMIFA Electrical Data/Timing

Table 6-42. Timing Requirements for AECLKIN for EMIFA

(1) (2)

(see

Figure 6-19 )

NO.

1

2

3

4

5 t c(EKI) t w(EKIH) t w(EKIL) t t(EKI) t

J(EKI)

Cycle time, AECLKIN

Pulse duration, AECLKIN high

Pulse duration, AECLKIN low

Transition time, AECLKIN

Period Jitter, AECLKIN

720, 800, 900, 1100

MIN

6

(3)

MAX

16P

(4)

2.7

2.7

0.02E

2

(5)

UNIT

ns ns ns ns ns

(1) The reference points for the rise and fall transitions are measured at V

IL

MAX and V

(2) E = the EMIF input clock (AECLKIN or SYSCLK4/2) period in ns for EMIFA.

IH

MIN.

(3) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.

(4) P is P = 1/CPU clock frequency in ns.

(5) This timing applies only when AECLKIN is used for EMIFA.

5

1

4

2

AECLKIN

3

4

Figure 6-19. AECLKIN Timing for EMIFA

Table 6-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the

EMIFA Module

(1) (2) (3)

(see

Figure 6-20 )

NO.

PARAMETER

720, 800, 900, 1100

MIN MAX

UNIT

1

2

3

4

5

6 t c(EKO) t w(EKOH) t w(EKOL) t t(EKO) t d(EKIH-EKOH) t d(EKIL-EKOL)

Cycle time, AECLKOUT

Pulse duration, AECLKOUT high

Pulse duration, AECLKOUT low

Transition time, AECLKOUT

Delay time, AECLKIN high to AECLKOUT high

Delay time, AECLKIN low to AECLKOUT low

E - 0.7

EH - 0.7

EL - 0.7

1

1

E + 0.7

EH + 0.7

EL + 0.7

1

8

8

(1) E = the EMIF input clock (AECLKIN or SYSCLK4/2) period in ns for EMIFA.


OL

MAX and V

OH

MIN.

(3) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.

ns ns ns ns ns ns

112






TMS320DM647

TMS320DM648


www.ti.com

AECLKIN

4

5

1

2

3 3

AECLKOUT

A.

E = the EMIF input clock (AECLKIN or SYSCLK4/2) period in ns for EMIFA.

B.

The reference points for the rise and fall transitions are measured at V

OL

MAX and V

OH

MIN.

C.

EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.

Figure 6-20. AECLKOUT Timing for the EMIFA Module

6.10.3.1 Asynchronous Memory Timing

Table 6-44. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module

(1) (2) (3)

(see

Figure 6-21

and

Figure 6-22 )

NO.

3

4

5

6

7

8

9 t t t t t t t su(EDV-A OEH) h(AOEH-EDV) su(ARDY-EKOH) h(EKOH-ARDY) w(ARDY ) d(ARDY-HOLD) su(ARDY-HOLD)

Setup time, AEDx valid before AAOE/ASOE high

Hold time, AEDx valid after AAOE/ASOE high

Setup time, AARDY valid before AECLKOUT low

Hold time, AARDY valid after AECLKOUT low

Pulse width, AARDY assertion and deassertion

Delay time, from AARDY sampled deasserted on AECLKOUT falling to beginning of programmed hold period

Setup time, before end of programmed strobe period by which

AARDY should be asserted in order to insert extended strobe wait states.

720, 800, 900, 1100

MIN MAX

6.5

0

1

2

2E + 5

2E

4E

UNIT

ns ns ns ns ns ns ns

(1) E = AECLKOUT period in ns for EMIFA

(2) To specify data setup time, simply program the strobe width wide enough.

(3) AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E to specify setup and hold time is met.

Table 6-45. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for EMIFA Module

(1) (2) (3)

(see

Figure 6-21

and

Figure 6-22 )

NO.

1

2

10

11

12

13 t osu(SELV-AOEL) t oh(AOEH-SELIV) t d(EKOH-AOEV) t osu(SELV-AWEL) t oh(AWEH-SELIV) t d(EKOH-AWEV)

PARAMETER

Output setup time, select signals valid to AAOE/ASOE low

Output hold time, AAOE/ASOE high to select signals invalid

Delay time, AECLKOUT high to AAOE/ASOE valid

Output setup time, select signals valid to AAWE/ASWE low

Output hold time, AAWE/ASWE high to select signals invalid

Delay time, AECLKOUT high to AAWE/ASWE valid

720, 800, 900, 1100

MIN

RS × E - 1.5

MAX

RS × E - 1.9

1

WS × E - 1.7

WH × E - 1.8

1.3

7.28

7.1

UNIT

ns ns ns ns ns ns

(1) E = AECLKOUT period in ns for EMIFA

(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIFA CE Configuration registers (CEnCFG).

(3) Select signals for EMIFA include: ACEx, ABE[1:0], AEA[23:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[15:0].






113

TMS320DM647

TMS320DM648


AECLKOUT

ACEx

ABE[1:0]

AEA[23:0]/

ABA[1:0]

AED[15:0]

Setup = 1

1

1

1

10

Strobe = 4

Byte Enables

Address

Hold = 1

2

2

2

3 4

Read Data

10

AR/W

AARDY

DEASSERTED

A.

AAOE/ASOE and AAWE/ASWE operate as AAOE/ASOE (identified under select signals) and AAWE/ASWE, respectively, during asynchronous memory accesses.

B.

Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC).

Figure 6-21. Asynchronous Memory Read Timing for EMIFA

Strobe = 4

Setup = 1

Hold = 1

AECLKOUT

ACEx

ABE[1:0]

AEA[23:0]/

ABA[1:0]

11

11

11

Byte Enables

Address

12

12

12

11 12

AED[15:0]

(A)

(A)

13

Write Data

13

11

12

AR/W

AARDY

(B)

DEASSERTED

A.

AAOE/ASOE and AAWE/ASWE operate as AAOE/ASOE and AAWE/ASWE (identified under select signals) during asynchronous memory accesses.

B.


Figure 6-22. Asynchronous Memory Write Timing for EMIFA www.ti.com

114






TMS320DM647


Strobe


Strobe

Hold = 2 Setup = 2 Extended Strobe

8

9

AECLKOUT

6

5

7

7

AARDY

(A)

ASSERTED DEASSERTED

A.


Figure 6-23. AARDY Timing

6.10.3.2 Programmable Synchronous Interface Timing

Table 6-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module

(see

Figure 6-24 )

NO.

6

7 t su(EDV-EKOH) t h(EKOH-EDV)

Setup time, read AEDx valid before AECLKOUT high

Hold time, read AEDx valid after AECLKOUT high

720, 800, 900, 1100

MIN MAX

2

1.5

UNIT

ns ns

Table 6-47. Switching Characteristics Over Recommended Operating Conditions for Programmable

Synchronous Interface Cycles for EMIFA Module

(1)

(see

Figure 6-24

Figure 6-26 )

NO.

1

2

3

4

5

8

9

10

11

12 t d(EKOH-CEV) t d(EKOH-BEV) t d(EKOH-BEIV) t d(EKOH-EAV) t d(EKOH-EAIV) t d(EKOH-ADSV) t d(EKOH-OEV) t d(EKOH-EDV) t d(EKOH-EDIV) t d(EKOH-WEV)

PARAMETER

Delay time, AECLKOUT high to ACEx valid

Delay time, AECLKOUT high to ABEx valid

Delay time, AECLKOUT high to ABEx invalid

Delay time, AECLKOUT high to AEAx valid

Delay time, AECLKOUT high to AEAx invalid

Delay time, AECLKOUT high to ASADS/ASRE valid

Delay time, AECLKOUT high to AAOE/ASOE valid

Delay time, AECLKOUT high to AEDx valid

Delay time, AECLKOUT high to AEDx invalid

Delay time, AECLKOUT high to AAWE/ASWE valid

720, 800, 900, 1100

MIN MAX

1.3

1.3

1.3

1.3

1.3

1.3

1.3

4.9

4.9

4.9

4.9

4.9

4.9

4.9

UNIT

ns ns ns ns ns ns ns ns ns ns

(1) The following parameters are programmable via the EMIFA CE Configuration registers (CEnCFG):

• Read latency (R_LTNCY): 0-, 1-, 2-, or 3-cycle read latency

• Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

• ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CE_EXT = 0). For synchronous FIFO interface with glue, ACEx is active when AAOE/ASOE is active (CE_EXT = 1).

• Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE has deselect cycles

(R_ENABLE = 0). For FIFO interface, ASADS/ASRE has NO deselect cycles (R_ENABLE = 1).






115

TMS320DM647

TMS320DM648


www.ti.com

READ latency = 2

AECLKOUT

1 1

ACEx

2 3

ABE[7:0]

AEA[19:0]/ABA[1:0]

AED[63:0]

4

EA1 EA2

6

EA3

Q1

EA4

7

Q2

5

Q3 Q4

8

8

ASADS/ASRE

(B)

9 9

AAOE /ASOE

(B)

AAWE/ASWE

(B)

Figure 6-24. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)

NOTE

This information applies to

Figure 6-25

and

Figure 6-26

.

The following parameters are programmable via the EMIF Chip Select n Configuration

Register (CESECn):

• Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency

• Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

• ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CE_EXT = 0). For synchronous

FIFO interface, ACEx is active when AAOE/ASOE is active (CE_EXT = 1).

• Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface,

ASADS/ASRE has deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE has NO deselect cycles (R_ENABLE = 1).

AECLKOUT

ACEx

ABE[1:0]

AEA[23:0]/ABA[1:0]

AED[15:0]

10

1

2

BE1

4

EA1

10

Q1

8

BE2

EA2

Q2

BE3

EA3

Q3

BE4

EA4

Q4

1

3

5

11

8

12 12

A.

In this figure, W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

Figure 6-25. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)

116






www.ti.com

AECLKOUT

ACEx

ABE[1:0]

AEA[23:0]/ABA[1:0]

AED[15:0]

TMS320DM647

TMS320DM648


Write

Latency = 1

1

2

BE1

4

EA1

10

8

BE2

10

EA2

Q1

BE3

EA3

Q2

BE4

EA4

Q3

1

3

5

Q4

11

8

12 12

Figure 6-26. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1)






117

TMS320DM647

TMS320DM648


www.ti.com

6.11 Video Port

Each video port is capable of sending and receiving digital video data. The video ports are also capable of capturing/displaying RAW data. The video port peripherals follow video standards such as BT.656 and

SMPTE296.

6.11.1 Video Port Device-Specific Information

The devices have five video port peripherals.

The video port peripheral can operate as a video capture port, video display port, or as a transport channel interface (TCI) capture port.

The port consists of two channels: A and B. A 5120-byte capture/display buffer is splittable between the two channels. The entire port (both channels) is always configured for either video capture or display only.

Separate data pipelines control the parsing and formatting of video capture or display data for each of the

BT.656, Y/C, raw video, and TCI modes.

For video capture operation, the video port may operate as two 8-bit channels of BT.656 or raw video capture; or as a single channel of 8-bit BT.656, 8-bit raw video, 8-bit Y/C video, 16-bit raw video, or 8-bit

TCI.

For video display operation, the video port may operate as a single channel of 8-bit BT.656; or as a single channel of 8-bit BT.656, 8-bit raw video, 8-bit Y/C video, or 16-bit raw video. It may also operate in a two channel 8-bit raw mode in which the two channels are locked to the same timing. Channel B is not used during single channel operation.

For more detailed information on the video port peripherals, see the TMS320DM647/DM648 Video Port

User's Guide (literature number SPRUEM1 ).

6.11.2 Video Port Peripheral Register Description(s)

Table 6-48. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers

VP0

0x02C0 0000

0x02C0 0004

0x02C0 0008

0x02C0 000C

0x02C0 0020

0x02C0 0024

0x02C0 0028

0x02C0 002C

0x02C0 0030

0x02C0 0034

0x02C0 0038

0x02C0 003C

0x02C0 0040

0x02C0 0044

0x02C0 00C0

0x02C0 00C4

0x02C0 00C8

0x02C0 00CC

0x02C0 0100

0x02C0 0104

VP1

0x02C0 4000


VP2

0x02C0 8000

VP3

0x02C0 C000

0x02C0 4004

0x02C0 4008

0x02C0 400C

0x02C0 4020

0x02C0 4024

0x02C0 4028

0x02C0 402C

0x02C0 4030

0x02C0 4034

0x02C0 4038

0x02C0 403C

0x02C0 4040

0x02C0 4044

0x02C0 40C0

0x02C0 40C4

0x02C0 40C8

0x02C0 40CC

0x02C0 4100

0x02C0 8004

0x02C0 8008

0x02C0 800C

0x02C0 8020

0x02C0 8024

0x02C0 8028

0x02C0 802C

0x02C0 8030

0x02C0 8034

0x02C0 8038

0x02C0 803C

0x02C0 8040

0x02C0 8044

0x02C0 80C0

0x02C0 80C4

0x02C0 80C8

0x02C0 80CC

0x02C0 8100

0x02C0 C004

0x02C0 C008

0x02C0 C00C

0x02C0 C020

0x02C0 C024

0x02C0 C028

0x02C0 C02C

0x02C0 C030

0x02C0 C034

0x02C0 C038

0x02C0 C03C

0x02C0 C040

0x02C0 C044

0x02C0 C0C0

0x02C0 C0C4

0x02C0 C0C8

0x02C0 C0CC

0x02C0 C100

0x02C0 4104 0x02C0 8104 0x02C0 C104

VP4

0x02C1 0000

0x02C1 0004

0x02C1 0008

0x02C1 000C

0x02C1 0020

0x02C1 0024

0x02C1 0028

0x02C1 002C

0x02C1 0030

0x02C1 0034

0x02C1 0038

0x02C1 003C

0x02C1 0040

0x02C1 0044

0x02C1 00C0

0x02C1 00C4

0x02C1 00C8

0x02C1 00CC

0x02C1 0100

0x02C1 0104

ACRONYM

VPPID

PCR

-

-

PFUNC

PDIR

PDIN

PDOUT

PDSET

PDCLR

PIEN

PIPOL

PISTAT

PICLR

VPCTL

VPSTAT

VPIE

VPIS

VCASTAT

VCACTL

DESCRIPTION

Video Port Peripheral Identification

Register

Video Port Peripheral Control Register

Reserved

Reserved

Video Port Pin Function Register

Video Port Pin Direction Register

Video Port Pin Data Input Register

Video Port Pin Data Output Register

Video Port Pin Data Set Register

Video Port Pin Data Clear Register

Video Port Pin Interrupt Enable Register

Video Port Pin Interrupt Polarity Register

Video Port Pin Interrupt Status Register

Video Port Pin Interrupt Clear Register

Video Port Control Register

Video Port Status Register

Video Port Interrupt Enable Register

Video Port interrupt Status Register

Video Capture Channel A Status Register

Video Capture Channel A Control

Register

118






TMS320DM647



Table 6-48. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers (continued)

VP0 VP1


VP2 VP3 VP4

ACRONYM DESCRIPTION

0x02C0 0108

0x02C0 010C

0x02C0 0110

0x02C0 0114

0x02C0 0118

0x02C0 011C

0x02C0 0120

0x02C0 0140

0x02C0 0144

0x02C0 0148

0x02C0 014C

0x02C0 0150

0x02C0 0154

0x02C0 0158

0x02C0 015C

0x02C0 0160

0x02C0 0180

0x02C0 0184

0x02C0 0188

0x02C0 018C

0x02C0 0190

0x02C0 0194

0x02C0 0198

0x02C0 019C

0x02C0 01A0

0x02C0 01A4

0x02C0 0200

0x02C0 0204

0x02C0 0208

0x02C0 020C

0x02C0 0210

0x02C0 0214

0x02C0 0218

0x02C0 021C

0x02C0 4108

0x02C0 410C

0x02C0 4110

0x02C0 4114

0x02C0 4118

0x02C0 411C

0x02C0 4120

0x02C0 4140

0x02C0 4144

0x02C0 4148

0x02C0 414C

0x02C0 4150

0x02C0 4154

0x02C0 4158

0x02C0 415C

0x02C0 4160

0x02C0 4180

0x02C0 4184

0x02C0 4188

0x02C0 418C

0x02C0 4190

0x02C0 4194

0x02C0 4198

0x02C0 419C

0x02C0 41A0

0x02C0 41A4

0x02C0 4200

0x02C0 4204

0x02C0 4208

0x02C0 420C

0x02C0 4210

0x02C0 4214

0x02C0 4218

0x02C0 421C

0x02C0 8108

0x02C0 810C

0x02C0 8110

0x02C0 8114

0x02C0 8118

0x02C0 811C

0x02C0 8120

0x02C0 8140

0x02C0 8144

0x02C0 8148

0x02C0 814C

0x02C0 8150

0x02C0 8154

0x02C0 8158

0x02C0 815C

0x02C0 8160

0x02C0 8180

0x02C0 8184

0x02C0 8188

0x02C0 818C

0x02C0 8190

0x02C0 8194

0x02C0 8198

0x02C0 819C

0x02C0 81A0

0x02C0 81A4

0x02C0 8200

0x02C0 8204

0x02C0 8208

0x02C0 820C

0x02C0 8210

0x02C0 8214

0x02C0 8218

0x02C0 821C

0x02C0 C108

0x02C0 C10C

0x02C0 C110

0x02C0 C114

0x02C0 C118

0x02C0 C11C

0x02C0 C120

0x02C0 C140

0x02C0 C144

0x02C0 C148

0x02C0 C14C

0x02C0 C150

0x02C0 C154

0x02C0 C158

0x02C0 C15C

0x02C0 C160

0x02C0 C180

0x02C0 C184

0x02C0 C188

0x02C0 C18C

0x02C0 C190

0x02C0 C194

0x02C0 C198

0x02C0 C19C

0x02C0 C1A0

0x02C0 C1A4

0x02C0 C200

0x02C0 C204

0x02C0 C208

0x02C0 C20C

0x02C0 C210

0x02C0 C214

0x02C0 C218

0x02C0 C21C

0x02C1 0108

0x02C1 010C

0x02C1 0110

0x02C1 0114

0x02C1 0118

0x02C1 011C

0x02C1 0120

0x02C1 0140

0x02C1 0144

0x02C1 0148

0x02C1 014C

0x02C1 0150

0x02C1 0154

0x02C1 0158

0x02C1 015C

0x02C1 0160

0x02C1 0180

0x02C1 0184

0x02C1 0188

0x02C1 018C

0x02C1 0190

0x02C1 0194

0x02C1 0198

0x02C1 019C

0x02C1 01A0

0x02C1 01A4

0x02C1 0200

0x02C1 0204

0x02C1 0208

0x02C1 020C

0x02C1 0210

0x02C1 0214

0x02C1 0218

0x02C1 021C

VCASTRT1

VCASTOP1

VCASTRT2

VCASTOP2

VCAVINT

VCATHRLD

VCAEVTCT

VCBSTAT

VCBCTL

VCBSTRT1

VCBSTOP1

Video Capture Channel A Field 1 Start

Register

Video Capture Channel A Field 1 Stop

Register

Video Capture Channel A Field 2 Start

Register

Video Capture Channel A Field 2 Stop

Register

Video Capture Channel A Vertical

Interrupt Register

Video Capture Channel A Threshold

Register

Video Capture Channel A Event Count

Register

Video Capture Channel B Status Register

Video Capture Channel B Control

Register

Video Capture Channel B Field 1 Start

Register

Video Capture Channel B Field 1 Stop

Register

VCBSTRT2

VCBSTOP2

VCBVINT

Video Capture Channel B Field 2 Start

Register

Video Capture Channel B Field 2 Stop

Register

Video Capture Channel B Vertical

Interrupt Register

VCBTHRLD

VCBEVTCT

TCICTL

Video Capture Channel B Threshold

Register

Video Capture Channel B Event Count

Register

TCI Capture Control Register

TCICLKINITL TCI Clock Initialization LSB Register

TCICLKINITM TCI Clock Initialization MSB Register

TCISTCLKL

TCISTCLKM

TCI System Time Clock LSB Register

TCI System Time Clock MSB Register

TCISTCMPL

TCISTCMPM

TCISTMSKL

TCISTMSKM

TCITICKS

VDSTAT

VDCTL

VDFRMSZ

VDHBLNK

VDVBLKS1

VDVBLKE1

VDVBLKS2

VDVBLKE2

TCI System Time Clock Compare LSB

Register

TCI System Time Clock Compare MSB

Register

TCI System Time Clock Compare Mask

LSB Register

TCI System Time Clock Compare Mask

MSB Register

TCI System Time Clock Ticks Interrupt

Register

Video Display Status Register

Video Display Control Register

Video Display Frame Size Register

Video Display Horizontal Blanking

Register

Video Display Field 1 Vertical Blanking

Start Register


End Register


Start Register


End Register






119

TMS320DM647

TMS320DM648


www.ti.com

Table 6-48. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers (continued)

VP0 VP1


VP2 VP3 VP4

ACRONYM DESCRIPTION

0x02C0 0220

0x02C0 0224

0x02C0 0228

0x02C0 022C

0x02C0 0230

0x02C0 0234

0x02C0 0238

0x02C0 023C

0x02C0 0240

0x02C0 0244

0x02C0 0248

0x02C0 024C

0x02C0 0250

0x02C0 0254

0x02C0 0258

0x02C0 025C

0x02C0 0260

0x02C0 0264

0x02C0 0268

0x02C0 026C

0x5000 0000

0x5000 0020

0x5000 0040

0x5000 0080

0x5000 00A0

0x5000 00C0

0x5200 0000

0x5200 0020

0x5200 0040

0x5200 0080

0x02C0 4220

0x02C0 4224

0x02C0 4228

0x02C0 422C

0x02C0 4230

0x02C0 4234

0x02C0 4238

0x02C0 423C

0x02C0 4240

0x02C0 4244

0x02C0 4248

0x02C0 424C

0x02C0 4250

0x02C0 4254

0x02C0 4258

0x02C0 425C

0x02C0 4260

0x02C0 4264

0x02C0 4268

0x02C0 426C

0x5400 0000

0x5400 0020

0x5400 0040

0x5400 0080

0x5400 00A0

0x5400 00C0

0x5600 0000

0x5600 0020

0x5600 0040

0x5600 0080

0x02C0 8220

0x02C0 8224

0x02C0 8228

0x02C0 822C

0x02C0 8230

0x02C0 8234

0x02C0 8238

0x02C0 823C

0x02C0 8240

0x02C0 8244

0x02C0 8248

0x02C0 824C

0x02C0 8250

0x02C0 8254

0x02C0 8258

0x02C0 825C

0x02C0 8260

0x02C0 8264

0x02C0 8268

0x02C0 826C

0x5800 0000

0x5800 0020

0x5800 0040

0x5800 0080

0x5800 00A0

0x5800 00C0

0x5A00 0000

0x5A00 0020

0x5A00 0040

0x5A00 0080

0x02C0 C220

0x02C0 C224

0x02C0 C228

0x02C0 C22C

0x02C0 C230

0x02C0 C234

0x02C0 C238

0x02C0 C23C

0x02C0 C240

0x02C0 C244

0x02C0 C248

0x02C0 C24C

0x02C0 C250

0x02C0 C254

0x02C0 C258

0x02C0 C25C

0x02C0 C260

0x02C0 C264

0x02C0 C268

0x02C0 C26C

0x6000 0000

0x6000 0020

0x6000 0040

0x6000 0080

0x6000 00A0

0x6000 00C0

0x6200 0000

0x6200 0020

0x6200 0040

0x6200 0080

0x02C1 0220

0x02C1 0224

0x02C1 0228

0x02C1 022C

0x02C1 0230

0x02C1 0234

0x02C1 0238

0x02C1 023C

0x02C1 0240

0x02C1 0244

0x02C1 0248

0x02C1 024C

0x02C1 0250

0x02C1 0254

0x02C1 0258

0x02C1 025C

0x02C1 0260

0x02C1 0264

0x02C1 0268

0x02C1 026C

0x6400 0000

0x6400 0020

0x6400 0040

0x6400 0080

0x6400 00A0

0x6400 00C0

0x6600 0000

0x6600 0020

0x6600 0040

0x6600 0080

VDIMGOFF1

VDIMGSZ1

VDIMGOFF2

VDIMGSZ2

VDFLDT1

VDFLDT2

VDTHRLD

VDHSYNC

VDVSYNS1

VDVSYNE1

VDVSYNS2

VDVSYNE2

VDRELOAD

VDDISPEVT

VDCLIP

VDDEFVAL

VDVINT

VDFBIT

VDVBIT1

VDVBIT2

YSRCA

CBSRCA

CRSRCA

YDSTA

CBDST

CRDST

YSRCB

CBSRCB

CRSRCB

YDSTB

Video Display Field 1 Image Offset

Register

Video Display Field 1 Image Size

Register

Video Display Field 2 Image Offset

Register

Video Display Field 2 Image Size

Register

Video Display Field 1 Timing Register

Video Display Field 2 Timing Register

Video Display Threshold Register

Video Display Horizontal Synchronization

Register

Video Display Field 1 Vertical

Synchronization Start Register


Synchronization End Register


Synchronization Start Register


Synchronization End Register

Video Display Counter Reload Register

Video Display Event Register

Video Display Clipping Register

Video Display Default Display Value

Register

Video Display Vertical Interrupt Register

Video Display Field Bit Register

Video Display Field 1Vertical Blanking Bit

Register

Video Display Field 2Vertical Blanking Bit

Register

Y FIFO Source Register A

CB FIFO Source Register A

CR FIFO Source Register A

Y FIFO Destination Register A

CB FIFO Destination Register

CR FIFO Destination Register

Y FIFO Source Register B

CB FIFO Source Register B

CR FIFO Source Register B

Y FIFO Destination Register B

120






TMS320DM647


6.11.3 Video Port (VP0, VP1, VP2, VP3, VP4) Electrical Data/Timing

6.11.3.1 VCLKIN Timing (Video Capture Mode)


NO.

Table 6-49. Timing Requirements for Video Capture Mode for VPxCLKINx

(1)

(see

Figure 6-27 )

1 t c(VKI)

2 t w(VKIH)

3 t w(VKIL)

4 t t(VKI)

Cycle time, VPxCLKINx

Pulse duration, VPxCLKINx high

Pulse duration, VPxCLKINx low

Transition time, VPxCLKINx


IL

MAX and V

IH

MIN.

-720

-800

-900

-1100

MIN MAX

9.259

4.2

4.2

3

1 4

2 3

UNIT

ns ns ns ns

VPxCLKINx

4

Figure 6-27. Video Port Capture VPxCLKINx TIming






121

TMS320DM647

TMS320DM648


6.11.3.2 Video Data and Control Timing (Video Capture Mode) www.ti.com

NO.

Table 6-50. Timing Requirements in Video Capture Mode for Video Data and Control Inputs

(see

Figure 6-28 )

1 t su(VDATV-VKIH)

2 t h(VDATV-VKIH)

3 t su(VCTLV-VKIH)

4 t h(VCTLV-VKIH)

Setup time, VPxDx valid before VPxCLKINx high

Hold time, VPxDx valid after VPxCLKINx high

Setup time, VPxCTLx valid before VPxCLKINx high

Hold time, VPxCTLx valid after VPxCLKINx high

-720

-800

-900

-1100

MIN MAX

2.4

0.5

2.4

0.5

UNIT

ns ns ns ns

VPxCLKINx

1

2

VPxD[19:0] (Input)

3

4

VPxCTLx (Input)

Figure 6-28. Video Port Capture Data and Control Input Timing

122






TMS320DM647


6.11.3.3 VCLKIN Timing (Video Display Mode)


NO.

Table 6-51. Timing Requirements for Video Display Mode for VPxCLKINx

(1)

(see

Figure 6-29

)

1 t c(VKI)

2 t w(VKIH)

3 t w(VKIL)

4 t t(VKI)

Cycle time, VPxCLKINx

Pulse duration, VPxCLKINx high

Pulse duration, VPxCLKINx low

Transition time, VPxCLKINx


IL

MAX and V

IH

MIN.

-720

-800

-900

-1100

MIN MAX

9

4.1

4.1

3

UNIT

ns ns ns ns

1

4

2 3

VPxCLKINx

4

Figure 6-29. Video Port Display VPxCLKINx Timing

6.11.3.4 Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx and VPxCLKOUTx (Video Display Mode)

Table 6-52. Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to

VPxCLKINx and VPxCLKOUTx (see

Figure 6-30 )

NO.

13 t su(VCTLV-VKIH)

14 t h(VCTLV-VKIH)

15 t su(VCTLV-VKOH)

16 t h(VCTLV-VKOH)

Setup time, VPxCTLx valid before VPxCLKINx high

Hold time, VPxCTLx valid after VPxCLKINx high

Setup time, VPxCTLx valid before VPxCLKOUTx high

(1)

Hold time, VPxCTLx valid after VPxCLKOUTx high

(1)

(1) Assuming non-inverted VPxCLKOUTx signal.

-720

-800

-900

-1100

MIN

2.4

0.5

7.4

-0.9

MAX

UNIT

ns ns ns ns






123

TMS320DM647

TMS320DM648


www.ti.com

Table 6-53. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx

(1) (2)

(see

Figure 6-30 )

NO.

PARAMETER

1 t c(VKO)

2 t w(VKOH)

3 t w(VKOL)

4 t t(VKO)

5 t d(VKIH-VKOH)

6 t d(VKIL-VKOL)

7 t d(VKIH-VKOL)

8 t d(VKIL-VKOH)

9 t d(VKIH-VPOUTV)

10 t d(VKIH-VPOUTIV)

11 t d(VKOH-VPOUTV)

12 t d(VKOH-VPOUTIV)

Cycle time, VPxCLKOUTx

Pulse duration, VPxCLKOUTx high

Pulse duration, VPxCLKOUTx low

Transition time, VPxCLKOUTx

Delay time, VPxCLKINx high to VPxCLKOUTx high

(3)

Delay time, VPxCLKINx low to VPxCLKOUTx low

(3)

Delay time, VPxCLKINx high to VPxCLKOUTx low

Delay time, VPxCLKINx low to VPxCLKOUTx high

Delay time, VPxCLKINx high to VPxOUT valid

(4)

Delay time, VPxCLKINx high to VPxOUT invalid

(4)

Delay time, VPxCLKOUTx high to VPxOUT valid

(1) (4)

Delay time, VPxCLKOUTx high to VPxOUT invalid

(1) (4)

(1) V = the video input clock (VPxCLKINx) period in ns.

(2) VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.

(3) Assuming non-inverted VPxCLKOUTx signal.

(4) VPxOUT consists of VPxCTLx and VPxD[19:0]

-720

-800

-900

-1100

MIN MAX

V - 0.7

V + 0.7

VH - 0.7

VH + 0.7

VL - 0.7

VL + 0.7

1.8

5

5

5

5

7

1.7

4.7

0.7

UNIT

ns ns ns ns ns ns ns ns ns ns ns ns

VPxCLKINx

5 2

1

6

VPxCLKOUTx

[VCLK2P = 0]

3

4

7

4

VPxCLKOUTx

(Inverted)

[VCLK2P = 1]

8

11

9

12

10

VPxCTLx,V

PxD[19:0]

(Outputs)

15

16

14

13

VPxCTLx

(Input)

Figure 6-30. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to

VPxCLKINx and VPxCLKOUTx

124






TMS320DM647



6.11.3.5

Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx)

NO.

Table 6-54. Timing Requirements for Dual-Display Sync Mode for VPxCLKINx (see

Figure 6-31 )

1 t skr(VKI)

Skew rate, VPxCLKINx before VPyCLKINy

-720<br

Placement="li ne"/>-800<br

Placement="li ne"/>-900

-1100

MIN MAX

±500

UNIT

ps

VPxCLKINx

VPyCLKINy

1

Figure 6-31. Video Port Dual-Display Sync Timing






125

TMS320DM647

TMS320DM648


www.ti.com

6.12 VCXO Interpolated Control (VIC)

The VIC can be used in conjunction with the video ports (VPs) to maintain synchronization of a video stream. The VIC can also be used to control a VCXO to adjust the pixel clock rate to a video port.

6.12.1 VIC Device-Specific Information

The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from 9bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output (VDAC pin).

Typical D/A converters provide a discrete output level for every value of the digital word that is being converted. This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A converter by choosing a few widely spaced output levels and interpolating values between them. The interpolating mechanism causes the output to oscillate rapidly between the levels in such a manner that the average output represents the value of input code.

In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented to interpolate between these levels with a rapidly changing signal. The frequency of interpolation is dependent on the resolution needed.

When the video port is used in transport channel interface (TCI) mode, the VIC port is used to control the system clock, VCXO, for MPEG transport stream.

The VIC supports the following features:

• Single interpolation for D/A conversion

• Programmable precision from 9-to-16 bits

• Interface for register accesses

For more detailed information on the VCXO interpolated control (VIC) peripheral, see the

TMS320DM647/DM648 Video Port User's Guide (literature number SPRUEM1 ).

6.12.2 VIC Peripheral Register Description(s)

Table 6-55. VCXO Interpolated Control (VIC) Port Registers


0x0204 7400

0x0204 7404

0x0204 7408

0x0204 740C - 0x0204 77FF

ACRONYM

VICCTL

VICIN

VPDIV

-

REGISTER NAME

VIC control register

VIC input register

VIC clock divider register

Reserved

126






TMS320DM647


6.12.3 VIC Electrical Data/Timing

6.12.3.1 STCLK Timing


Table 6-56. Timing Requirements for STCLK

(1)

(see

Figure 6-32 )

NO.

1 t c(STCLK)

2 t w(STCLKH)

3 t w(STCLKL)

4 t t(STCLK)

Cycle time, STCLK

Pulse duration, STCLK high

Pulse duration, STCLK low

Transition time, STCLK


IL

MAX and V

IH

MIN.

1

2 3

-720

-800

-900

-1100

MIN MAX

33.3

16

16

3

UNIT

ns ns ns ns

4

STCLK

4

Figure 6-32. STCLK Timing






127

TMS320DM647

TMS320DM648


6.13 Universal Asynchronous Receiver/Transmitter (UART)

The device has a UART peripheral. The UART has the following features:

• 16-byte storage space for both the transmitter and receiver FIFOs

• 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA

• DMA signaling capability for both received and transmitted data

• Programmable auto-rts and auto-cts for autoflow control

• Frequency pre-scale values from 1 to 65, 535 to generate appropriate baud rates

• Prioritized interrupts

• Programmable serial data formats

– 5, 6, 7, or 8-bit characters

– Even, odd, or no parity bit generation and detection

– 1, 1.5, or 2 stop bit generation

• False start bit detection

• Line break generation and detection

• Internal diagnostic capabilities

– Loopback controls for communications link fault isolation

– Break, parity, overrun, and framing error simulation

• Modem control functions (CTS, RTS).

The UART registers are listed in

Table 6-57

.

6.13.1 UART Peripheral Register Description(s)


0x0204 7000

0x0204 7000

0x0204 7004

0x0204 7008

0x0204 7008

0x0204 700C

0x0204 7010

0x0204 7014

0x0204 7018

0x0204 701C

0x0204 7020

0x0204 7024

0x0204 7028

0x0204 702C

0x0204 7030

0x0204 7034

0x0204 7038 - 0x0204 73FF

Table 6-57. UART Register Descriptions

LCR

MCR

-

-

LSR

ACRONYM

RBR

THR

IER

IIR

FCR

DLL

DLH

PID

-

PWREMU_MGMT

MDR

REGISTER NAME

UART Receiver Buffer Register (Read Only)

UART Transmitter Holding Register (Write Only)

UART Interrupt Enable Register

UART Interrupt Identification Register (Read Only)

UART FIFO Control Register (Write Only)

UART Line Control Register

UART Modem Control Register

UART Line Status Register

Reserved

Reserved

UART Divisor Latch (LSB)

UART Divisor Latch (MSB)


Reserved

UART Power and Emulation Management Register

Mode Definition Register

Reserved

www.ti.com

128






TMS320DM647


6.13.2 UART Electrical Data/Timing


NO.

Table 6-58. Timing Requirements for UARTx Receive

(1)

(see

Figure 6-33

)

4

5 t w(URXDB) t w(URXSB)

Pulse duration, receive data bit (RXDn) [15/30/100 pF]

Pulse duration, receive start bit [15/30/100 pF]

(1) U = UART baud time = 1/programmed baud rate.

720, 800, 900, 1100

MIN MAX

0.96U

0.96U

1.05U

1.05U

UNIT

ns ns

Table 6-59. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit

(1)

(see

Figure 6-33 )

NO.

PARAMETER

1

2

3 f

(baud) t w(UTXDB) t w(UTXSB)

Maximum programmable baud rate

Pulse duration, transmit data bit (TXDn) [15/30/100 pF]

Pulse duration, transmit start bit [15/30/100 pF]

(1) U = UART baud time = 1/programmed baud rate.

720, 800, 900, 1100

MIN MAX

U - 2

U - 2

UNIT

5 MHz

U + 2 ns

U + 2 ns

3

2

UART_TXDn

Start

Bit

Data Bits

5

4

UART_RXDn

Start

Bit

Data Bits

Figure 6-33. UART Transmit/Receive Timing






129

TMS320DM647

TMS320DM648


www.ti.com

6.14 Serial Peripheral Interface Port (SPI)

6.14.1 SPI Device-Specific Information

Figure 6-34

is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. The SPI can operate only as a master, in which case, it initiates a transfer and drives the

SPICLK pin. Four clock phase and polarity options are supported as well as many data formatting options.

SPIDO

SPIDI

Peripheral

Configuration Bus

Interrupt and

DMA Requests

16-Bit Shift Register

16-Bit Buffer

16-Bit Emulation Buffer

GPIO

Control

(all pins)

State

Machine

Clock

Control

SPICSx

SPICLK

Figure 6-34. Block Diagram of SPI Module

The SPI supports 3- and 4-pin operation with three basic pins (SPICLK, SPIDO, and SPIDI) and two optional pins (SPICSx).

The optional SPICSx (Slave Chip Select) pin is most useful to enable in master mode when there are more than one slave devices on the same SPI port. The device only shifts data and drives the SPIDI pin when SPICSx is held low.

Optional − Slave Chip Select

SPICSx

SPICSx

SPICLK

SPIDI

SPIDO

SPICLK

SPIDO

SPIDI

MASTER SPI SLAVE SPI

Figure 6-35. Illustration of SPI Master-to-SPI Slave Connection

130






TMS320DM647



6.14.2 SPI Peripheral Register Descriptions

Table 6-60

is a list of the SPI registers.

Table 6-60. SPI Configuration Registers

SPI0

BYTE ADDRESS

0x0204 7800

0x0204 7804

0x0204 7808

0x0204 780C

0x0204 7810

0x0204 7814

0x0204 7818

0x0204 781C

0x0204 783C

0x0204 7840

0x0204 7844

0x0204 7848

0x0204 784C

0x0204 7850

0x0204 7854

0x0204 7858

0x0204 785C

0x0204 7860

0x0204 7864

REGISTER NAME

SPIGCR0

SPIGCR1

SPIINT0

SPILVL

SPIFLG

SPIPC0

SPIPC1

SPIPC2

SPIDAT1

SPIBUF

SPIEMU

SPIDELAY

SPIDEF

SPIFMT0

SPIFMT1

SPIFMT2

SPIFMT3

TGINTVECT0

TGINTVECT1

DESCRIPTION

Global Control Register 0

Global Control Register 1

Interrupt Register

Interrupt Level Register

Flag Register

Pin Control Register 0 (Pin Function)

Pin Control Register 1 (Pin Direction)

Pin Control Register 2 (Pin Data In)

Shift Register 1 (with format select)

Buffer Register

Emulation Register

Delay Register

Default Chip Select Register

Format Register 0

Format Register 1

Format Register 2

Format Register 3

Interrupt Vector for SPI INT0

Interrupt Vector for SPI INT1






131

TMS320DM647

TMS320DM648


www.ti.com

6.14.3 SPI Electrical Data/Timing

6.14.3.1 Serial Peripheral Interface (SPI) Timing

Table 6-61

assumes testing over recommended operating conditions (see

Figure 6-36 ).

Table 6-61. General Timing Requirements for SPIx Master Modes

(1)

NO.

1

2

3 t

4

5

6

7

8 t t t t t t t c(SPC)M w(SPCH)M w(SPCL)M d(SIMO_SPC)M d(SPC_SIMO)M oh(SPC_SIMO)M su(SOMI_SPC)M ih(SPC_SOMI)M

Cycle Time, SPICLK, All Master Modes

Pulse Width High, SPICLK, All Master Modes

Pulse Width Low, SPICLK, All Master Modes

Delay, initial data bit valid on SPIDO to initial edge on

SPICLK

(2)

Polarity = 0, Phase = 0, to SPICLK rising


Polarity = 1, Phase = 0, to SPICLK falling


Delay, subsequent bits valid on SPIDO after transmit edge of SPICLK

Output hold time, SPIDO valid after receive edge of SPICLK, except for final bit

(3)

Polarity = 0, Phase = 0, from SPICLK rising

Polarity = 0, Phase = 1, from SPICLK falling







Input Setup Time, SPIDI valid before receive edge of SPICLK

Input Hold Time, SPIDI valid after receive edge of SPICLK








Polarity = 1, Phase = 1, from SPICLK falling greater of 8P or

100 ns greater of 4P or 45 ns greater of 4P or 45 ns

0.5t

0.5t

c(SPC)M c(SPC)M

0.5t

0.5t

0.5t

0.5t

c(SPC)M c(SPC)M c(SPC)M c(SPC)M

MIN

4P

+ 4P

4P

+ 4P

- 10

- 10

- 10

- 10

0.5P + 15

0.5P + 15

0.5P + 15

0.5P + 15

0.5P + 5

0.5P + 5

0.5P + 5

0.5P + 5

MAX UNIT

256P

15

15

15

15 ns ns ns ns ns ns ns ns

(1) P = SYSCLK3 period

(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPIDO.

MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIDI.

(3) The final data bit will be held on the SPIDO pin until the SPIDAT1 register is written with new data.

132






www.ti.com

SPICLK

SPIDO

SPIDI

SPICLK

SPIDO

SPIDI

SPICLK

SPIDO

SPIDI

SPICLK

SPIDO

SPIDI

2

1

3

4

MO(0)

7

MI(0)

8

5

MO(1)

MI(1)

TMS320DM647

TMS320DM648


Master Mode

Polarity = 0 Phase = 0

MO(n−1)

6

MI(n−1)

MO(n)

MI(n)

Master Mode


4

MO(0)

7

MI(0)

8

5

MO(1)

6

MI(1)

MO(n−1)

MI(n−1)

MO(n)

MI(n)

4

MO(0)

7

MI(0)

8

5

MO(1)

MI(1)

Master Mode


MO(n−1)

6

MI(n−1)

MO(n)

MI(n)

Master Mode


4

MO(0)

7

MI(0)

8

5

MO(1)

6

MO(n−1)

MI(1) MI(n−1)

Figure 6-36. SPI Timings—Master Mode

MO(n)

MI(n)






133

TMS320DM647

TMS320DM648


www.ti.com

6.15 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module provides an interface between the DM647/DM648 device and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1.

External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the

DSP through the I2C module. The I2C port does not support CBUS-compatible devices.

The I2C port supports:

• Compatible with Philips I2C Specification Revision 2.1 (January 2000)

• Fast Mode up to 400 Kbps (no fail-safe I/O buffers)

• Noise Filter to Remove Noise 50 ns or less

• Seven- and Ten-Bit Device Addressing Modes

• Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality

• Events: DMA, Interrupt, or Polling

• Slew-Rate Limited Open-Drain Output Buffers

I2C Module

Clock

Prescale

I2CPSC

Peripheral Clock

(DSP/6)

I2C Clock

SCL

Noise

Filter

Bit Clock

Generator

I2CCLKH

I2CCLKL

Transmit

I2CXSR

I2CDXR

Transmit

Shift

Transmit

Buffer

Control

I2COAR

I2CSAR

I2CMDR

I2CCNT

I2CEMDR

Own

Address

Slave

Address

Mode

Data

Count

Extended

Mode

I2C Data

SDA

Noise

Filter

Receive

I2CDRR

I2CRSR

Receive

Buffer

Receive

Shift

Interrupt/DMA

I2CIMR

I2CSTR

I2CIVR

Interrupt

Mask/Status

Interrupt

Status

Interrupt

Vector

Shading denotes control/status registers.

Figure 6-37. I2C Module Block Diagram

For more detailed information on the I2C peripheral, see the TMS320DM647/DM648 DSP Inter-Integrated

Circuit (I2C) Module User's Guide (literature number SPRUEK8 ).

134






TMS320DM647



6.15.1 I2C Peripheral Register Description(s)


0x0204 7C00

0x0204 7C04

0x0204 7C08

0x0204 7C0C

0x0204 7C10

0x0204 7C14

0x0204 7C18

0x0204 7C1C

0x0204 7C20

0x0204 7C24

0x0204 7C28

0x0204 7C2C

0x0204 7C30

0x0204 7C34

ACRONYM

ICOAR

ICIMR

ICSTR

ICCLKL

ICCLKH

ICCNT

ICDRR

ICSAR

ICDXR

ICMDR

ICIVR

ICEMDR

ICPSC

ICDMAC

Table 6-62. I2C Registers

REGISTER NAME

I2C Own Address Register

I2C Interrupt Mask Register

I2C Interrupt Status Register

I2C Clock Divider Low Register

I2C Clock Divider High Register

I2C Data Count Register

I2C Data Receive Register

I2C Slave Address Register

I2C Data Transmit Register

I2C Mode Register

I2C Interrupt Vector Register

I2C Extended Mode Register

I2C Prescaler Register

I2C DMA Control Register






135

TMS320DM647

TMS320DM648


6.15.2 I2C Electrical Data/Timing

6.15.2.1 Inter-Integrated Circuits (I2C) Timing www.ti.com

Table 6-63. Timing Requirements for I2C Timings

(1)

(see

Figure 6-38

)

NO.

720, 800, 900, 1100

STANDARD

MODE

FAST MODE

MIN MAX

10

MIN

2.5

MAX

UNIT

1

2

3

8

9

10

11

12

4

5

6

7

13

14

15 t t t c(SCL) su(SCLH-SDAL) h(SCLL-SDAL) t w(SCLL) t w(SCLH) t su(SDAV-SCLH) t h(SDA-SCLL) t w(SDAH) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t su(SCLH-SDAH) t w(SP)

C b

(5)

Cycle time, SCL

Setup time, SCL high before SDA low (for a repeated START condition)

Hold time, SCL low after SDA low (for a START and a repeated

START condition)

Pulse duration, SCL low

Pulse duration, SCL high

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

Pulse duration, SDA high between STOP and START conditions

Rise time, SDA

Rise time, SCL

Fall time, SDA

Fall time, SCL

Setup time, SCL high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

4.7

4

4.7

4

250

0

(3)

4.7

4

1.3

1000 20 + 0.1C

b

(5)

1000 20 + 0.1C

b

(5)

300 20 + 0.1C

b

(5)

300 20 + 0.1C

b

(5)

0.6

400

0.6

0.6

µs

µs

µs

1.3

0.6

100

(2)

0

(3)

0.9

(4)

µs

300 ns

0

300

300 ns

300 ns

50

µs

µs ns

µs ns

µs ns

400 pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.

(2) A Fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement t su(SDA-SCLH)

≥ 250 ns must then be met. This will be the case automatically if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

(3) the LOW period of the SCL signal, it must output the next data bit to the SDA line t r max + t

(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.

su(SDA-SCLH)

= 1000 + 250 = 1250 ns

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V undefined region of the falling edge of SCL.

IHmin of the SCL signal) to bridge the

(4) The maximum t h(SDA-SCLL)

(5) C b has to be met only if the device does not stretch the low period [t w(SCLL)

] of the SCL signal.

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

11 9

SDA

8

6

14

13

10

4

5

SCL

1

12

3

2

3

7

Stop Start Repeated

Start

Figure 6-38. I2C Receive Timings

Stop

136






TMS320DM647



NO.

16

17

18

19

20

21

22

23

24

25

26 t c(SCL) t d(SCLH-SDAL) t d(SDAL-SCLL) t w(SCLL) t w(SCLH) t d(SDAV-SCLH) t v(SCLL-SDAV) t w(SDAH)

Table 6-64. Switching Characteristics for I2C Timings

(1)

(see

Figure 6-39

)

PARAMETER

720, 800, 900, 1100

STANDARD

MODE

FAST MODE

MIN MAX

10

MIN MAX

2.5

Cycle time, SCL

Delay time, SCL high to SDA low (for a repeated START condition)

Delay time, SDA low to SCL low (for a START and a repeated START condition)

Pulse duration, SCL low

Pulse duration, SCL high

Delay time, SDA valid to SCL high

Valid time, SDA valid after SCL low

Pulse duration, SDA high between STOP and START conditions

4.7

4

4.7

4

250

0

4.7

0.6

0.6

1.3

UNIT

µs

µs

µs

1.3

0.6

µs

µs

100 ns

0 0.9

µs

µs t r(SDA)

Rise time, SDA 1000

20 + 0.1C

b

(2)

300 ns t r(SCL) t f(SDA)

Rise time, SCL

Fall time, SDA

1000

300

20 + 0.1C

b

(2)

20 + 0.1C

b

(2)

20 + 0.1C

b

(2)

300 ns

300 ns

300 ns 27 t f(SCL)

Fall time, SCL 300

28

29 t d(SCLH-SDAH)

C p

Delay time, SCL high to SDA high (for STOP condition)

Capacitance for each I2C pin

4

10

(1) C b

(2) C b



0.6

µs

10 pF

26 24

SDA

23

21

19

28

25

20

SCL

16

27

18

17

18

22

Stop Start Repeated

Start

Figure 6-39. I2C Transmit Timings

Stop






137

TMS320DM647

TMS320DM648


www.ti.com

6.16 Host-Port Interface (HPI) Peripheral

6.16.1 HPI Device-Specific Information

The device includes a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32). The AEA14 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit peripheral.

Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported.

An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the

EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.

6.16.2 HPI Peripheral Register Description(s)

Table 6-65. HPI Control Registers


0x0200 0000

0x0200 0004

0x0200 0008 - 0x0200 0024

0x0200 0028

0x0200 002C

ACRONYM

PID

PWREMU_MGMT

-

-

-

REGISTER NAME


HPI power and emulation management register

Reserved

Reserved

Reserved

COMMENTS

PWREMU_MGMT has both host/CPU read/write access.

0x0200 0030 HPIC HPI control register

The host and the CPU have read/write access to the HPIC register.

(1)

0x0200 0034

0x0200 0038

HPIA

(HPIAW)

(2)

HPIA

(HPIAR)

(2)

-

HPI address register

(Write)

HPI address register

(Read)

Reserved

The host has read/write access to the

HPIA registers. The CPU has read access only to the HPIA registers.

0x0200 003C - 0x0200 007F

(1) The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an interrupt from the host.

(2) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that

HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5 ).

138






TMS320DM647


6.16.3 HPI Electrical Data/Timing


Table 6-66. Timing Requirements for Host-Port Interface Cycles

(1) (2)

47 )

(see

Figure 6-40

through

Figure 6-

NO.

9

10

11

12

13

14

15

16

17

18

37

38 t t t t t t t su(HASL-HSTBL) t h(HSTBL-HASL) su(SELV-HASL) t h(HASL-SELV) t w(HSTBL) t w(HSTBH) t su(SELV-HSTBL) h(HSTBL-SELV) su(HDV-HSTBH) h(HSTBH-HDV) su(HCSL-HSTBL) h(HRDYL-HSTBL)

Setup time, HAS low before HSTROBE low

Hold time, HAS low after HSTROBE low

Setup time, select signals

(3) valid before HAS low

Hold time, select signals

(3) valid after HAS low

Pulse duration, HSTROBE low

Pulse duration, HSTROBE high between consecutive accesses

Setup time, select signals

(3) valid before HSTROBE low

Hold time, select signals

(3) valid after HSTROBE low

Setup time, host data valid before HSTROBE high

Hold time, host data valid after HSTROBE high

Setup time, HCS low before HSTROBE low

Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly.

1.1

(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.

(2) M = SYSCLK3 period = 6/CPU clock frequency in ns.

(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.

720, 800, 900, 1100

MIN MAX

5

2

5

5

2M

2M

5

5

5

1

0

UNIT







139

TMS320DM647

TMS320DM648


www.ti.com

Table 6-67. Switching Characteristics for Host-Port Interface Cycles

(1) (2)

(see

Figure 6-40

through

Figure 6-47 )

NO.

PARAMETER

720, 800, 900, 1100

MIN

5

MAX

15

1 t d(HSTBL-HDV)

Delay time, HSTROBE low to

DSP data valid

Case 1. HPIC or HPIA read

Case 2. HPID read with no autoincrement

(3)

Case 3. HPID read with auto-increment and read FIFO initially empty

(3)

Case 4. HPID read with auto-increment and data previously prefetched into the read FIFO

Disable time, HD high-impedance from HSTROBE high

Enable time, HD driven from HSTROBE low

5

9 × M + 20

9 × M + 20

15

2

3

4

5

6

7

34 t t t t t t dis(HSTBH-HDV) t en(HSTBL-HD) d(HSTBL-HRDYH) d(HSTBH-HRDYH) d(HSTBL-HRDYL) d(HDV-HRDYL) d(DSH-HRDYL)

Delay time, HSTROBE low to HRDY high

Delay time, HSTROBE high to HRDY high

Case 1. HPID read with no autoincrement

(3)

Delay time, HSTROBE low to

HRDY low

Case 2. HPID read with auto-increment and read FIFO initially empty

(3)

Delay time, HD valid to HRDY low

Case 1. HPIA write

(3)

Delay time, HSTROBE high to

HRDY low

Case 2. HPID write with no autoincrement

(3)

1

3

0

10 × M + 20

10 × M + 20

5 × M + 20

5 × M + 20

35 t d(HSTBL-HRDYL)

Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not empty

(3)

Delay time, HAS low to HRDY high

40 × M + 20

36 t d(HASL-HRDYH)

(1) M = SYSCLK3 period = 6/CPU clock frequency in ns.

(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3) Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.

12

4

15

12

12

UNIT


140






TMS320DM647

TMS320DM648


www.ti.com

HCS

HAS

HCNTL[1:0]

HR/W

HHWIL

15

37

16

13

37

14

15

16

13

HSTROBE

3

1

2

3

1

2

HD[15:0]

38

4

7

6

HRDY

A.

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

B.

Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with autoincrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number

SPRUEL5 ).

Figure 6-40. HPI16 Read Timing (HAS Not Used, Tied High)






141

TMS320DM647

TMS320DM648


HCS

HAS

12

11

12

11

HCNTL[1:0]

12

11

12

11

HR/W

12

11

12

11

HHWIL

10

9

10

37

9

13

37

13

14

HSTROBE(A)

1

3

2

1

3 2

HD[15:0]

7

36

38

6

HRDY(B)

A.


B.


SPRUEL5 ).

Figure 6-41. HPI16 Read Timing (HAS Used) www.ti.com

142






TMS320DM647



HCS

HAS

HCNTL[1:0]

HR/W

HHWIL

15

37

16

13

14

37

15

13

16

HSTROBE

(A)

18

18

17

17

HD[15:0]

4

35

38

34

5

5

34

HRDY

(B)

A.


B.


SPRUEL5 ).

Figure 6-42. HPI16 Write Timing (HAS Not Used, Tied High)






143

TMS320DM647

TMS320DM648


HCS

HAS

12

11

12

11

HCNTL[1:0]

12

11

12

11

HR/W

12

11

12

11

HHWIL

10

9

10

37

9

13

37

13

14

HSTROBE(A)

1

3

2

1

3 2

HD[15:0]

7

36

38

6

HRDY(B)

A.


B.


SPRUEL5 ).

Figure 6-43. HPI16 Write Timing (HAS Used) www.ti.com

144






TMS320DM647

TMS320DM648


www.ti.com

HAS (input)

15

HCNTL[1:0] (input)

16

HR/W (input)

13

HSTROBE

(A)

(input)

37

HCS (input)

1

3

2

HD[31:0] (output)

38

7

6

4

HRDY

(B)

(output)

A.

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.

B.


SPRUEL5 )

Figure 6-44. HPI32 Read Timing (HAS Not Used, Tied High)






145

TMS320DM647

TMS320DM648


HAS (input)

HCNTL[1:0] (input)

11

10

12

HR/W (input)

9

13

HSTROBE (A) (input)

37

HCS (input)

1

2

3

HD[31:0] (output)

7

38

6

36

HRDY (B) (output)

A.


B.


SPRUEL5 )

Figure 6-45. HPI32 Read Timing (HAS Used) www.ti.com

146






TMS320DM647

TMS320DM648


www.ti.com

HAS (input)

16

15

HCNTL[1:0]

(input)

HR/W (input)

13

HSTROBE

(A)

(input)

37

HCS (input)

18

17

HD[31:0] (input)

35

38

34

5

4

HRDY

(B)

(output)

A.


B.


SPRUEL5 )

Figure 6-46. HPI32 Write Timing (HAS Not Used, Tied High)






147

TMS320DM647

TMS320DM648


10

HAS (input)

HCNTL[1:0]

(input)

11

12

HR/W (input)

9

13

HSTROBE

(A)

(input)

37

HCS (input)

18

17

HD[31:0] (input)

35 34

38

36

5

HRDY

(B)

(output)

A.


B.


SPRUEL5 )

Figure 6-47. HPI32 Write Timing (HAS Used) www.ti.com

148






TMS320DM647



6.17 Peripheral Component Interconnect (PCI)

The device supports connections to a PCI backplane via the integrated PCI master/slave bus interface.

The PCI port interfaces to DSP internal resources via the data switched central resource. .

For more detailed information on the PCI port peripheral module, see the TMS320DM647/DM648

Peripheral Component Interconnect (PCI) User's Guide (literature number SPRUEL4 ).

6.17.1 PCI Device-Specific Information

The PCI peripheral conforms to the PCI Local Bus Specification (version 2.3). The PCI peripheral can act both as a PCI bus master and as a target. It supports PCI bus operation of speeds up to 66 MHz and uses a 32-bit data/address bus.

The pins of the PCI peripheral are multiplexed with the pins of the HPI, and GPIO peripherals. PCI functionality for these pins is controlled (enabled/disabled) by the UHPIEN pin (H2). The maximum speed of the PCI, 33 MHz or 66 MHz, is controlled through the PCI66 pin (G5). For more detailed information on the peripheral control, see

Section 3 .

The device provides an initialization mechanism through which the default values for some of the PCI configuration registers can be read from an I2C EEPROM.

Table 6-68

shows the registers which can be initialized through the PCI auto-initialization. Also shown is the default value of these registers when PCI auto-initialization is not used. PCI auto-initialization is enabled by selecting PCI boot with autoinitialization. For more information on this feature, see the TMS320DM647/DM648 Peripheral Component

Interconnect (PCI) User's Guide (literature number SPRUEL4 ) and the Using the TMS320DM647/DM648

Bootloader Application Report (literature number SPRAAJ1 ).

Table 6-68. Default Values for PCI Configuration

Registers

REGISTER

Vendor ID/Device ID Register (PCIVENDEV)

Class Code/Revision ID Register (PCICLREV)

Subsystem Vendor ID/Subsystem ID Register

(PCISUBID)

Max Latency/Min Grant/Interrupt Pin/Interrupt Line

Register (PCILGINT)

DEFAULT

VALUE

104C B003h

0000 0001h

0000 0000h

0000 0100h






149

TMS320DM647

TMS320DM648


6.17.2 PCI Peripheral Register Description(s)

Table 6-69. PCI Configuration Registers

PCI HOST ACCESS

HEX ADDRESS OFFSET

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28 - 0x2B

0x2C

0x30

0x34

0x38 - 0x3B

0x3C

0x40 - 0x7F

ACRONYM

PCIVENDEV

PCICSR

PCICLREV

PCICLINE

PCIBAR0

PCIBAR1

PCIBAR2

PCIBAR3

PCIBAR4

PCIBAR5

-

PCISUBID

-

PCICPBPTR

-

PCILGINT

-

PCI HOST ACCESS REGISTER NAME

Vendor ID/Device ID

Command/Status

Class Code/Revision ID

BIST/Header Type/Latency Timer/Cacheline Size

Base Address 0

Base Address 1

Base Address 2

Base Address 3

Base Address 4

Base Address 5

Reserved

Subsystem Vendor ID/Subsystem ID

Reserved

Capabilities Pointer

Reserved

Max Latency/Min Grant/Interrupt Pin/Interrupt Line

Reserved

www.ti.com

Table 6-70. PCI Back End Configuration Registers

150

DSP ACCESS


0x0204 8400 - 0x0204 840F

0x0204 8410

0x0204 8414

0x0204 8418 - 0x0204 841F

0x0204 8420

0x0204 8424

0x0204 8428 - 0x0204 842F

0x0204 8430

0x0204 8434

0x0204 8438

0x0204 843C - 0x0204 84FF

0x0204 8500

0x0204 8504

0x0204 8508

0x0204 850C

0x0204 8510

0x0204 8514

0x0204 8518

0x0204 851C

0x0204 8520

0x0204 8524

0x0204 8528 - 0x0204 852B

0x0204 852C

0x0204 8530

ACRONYM DSP ACCESS REGISTER NAME

Reserved

PCISTATSET PCI Status Set Register

PCISTATCLR PCI Status Clear Register

Reserved

PCIHINTSET PCI Host Interrupt Enable Set Register

PCIHINTCLR PCI Host Interrupt Enable Clear Register

Reserved

PCIBINTSET PCI Back End Application Interrupt Enable Set Register

PCIBINTCLR PCI Back End Application Interrupt Enable Clear Register

PCIBCLKMGT PCI Back End Application Clock Management Register

Reserved

PCIVENDEVMIR PCI Vendor ID/Device ID Mirror Register

PCICSRMIR PCI Command/Status Mirror Register

PCICLREVMIR PCI Class Code/Revision ID Mirror Register

PCICLINEMIR PCI BIST/Header Type/Latency Timer/Cacheline Size Mirror Register

PCIBAR0MSK PCI Base Address Mask Register 0






Reserved

PCISUBIDMIR PCI Subsystem Vendor ID/Subsystem ID Mirror Register

Reserved






TMS320DM647



Table 6-70. PCI Back End Configuration Registers (continued)

DSP ACCESS


0x0204 8534

0x0204 8538 - 0x0204 853B

0x0204 853C

0x0204 8540 - 0x0204 857F

0x0204 8580

0x0204 8584 - 0x0204 85BF

0x0204 85C0

0x0204 85C4

0x0204 85C8

0x0204 85CC

0x0204 85D0

0x0204 85D4

0x0204 85D8 - 0x0204 85DF

0x0204 85E0

0x0204 85E4

0x0204 85E8

0x0204 85EC

0x0204 85F0

0x0204 85F4

0x0204 85F8 - 0x0204 86FF

0x0204 8700

0x0204 8704

0x0204 8708

0x0204 870C - 0x0204 870F

0x0204 8710


PCICPBPTRMIR PCI Capabilities Pointer Mirror Register

Reserved

PCILGINTMIR PCI Max Latency/Min Grant/Interrupt Pin/Interrupt Line Mirror Register

Reserved

PCISLVCNTL PCI Slave Control Register

Reserved

PCIBAR0TRL PCI Slave Base Address 0 Translation Register






Reserved

PCIBAR0MIR PCI Base Address Register 0 Mirror Register






Reserved

PCIMCFGDAT PCI Master Configuration/IO Access Data Register

PCIMCFGADR PCI Master Configuration/IO Access Address Register

PCIMCFGCMD PCI Master Configuration/IO Access Command Register

Reserved

PCIMSTCFG PCI Master Configuration Register

Table 6-71. PCI Hook Configuration Registers

DSP ACCESS


0x0204 8794

0x0204 8798

0x0204 879C

0x0204 87A0

0x0204 87A4

0x0204 87A8

0x0204 87AC

0x0204 87B0

0x0204 87B4

0x0204 87B8

0x0204 87BC

0x0204 87C0

0x0204 87C4

0x0204 87C8

0x0204 87CC

0x0204 87D0

0x0204 87D4

0x0204 87D8


PCIVENDEVPRG PCI Vendor ID and Device ID Program Register

PCICMDSTATPRG PCI Command and Status Program Register

PCICLREVPRG PCI Class Code and Revision ID Program Register

PCISUBIDPRG PCI Subsystem Vendor ID and Subsystem ID Program Register

PCIMAXLGPRG PCI Max Latency and Min Grant Program Register

PCILRSTREG PCI LRESET Register

PCICFGDONE PCI Configuration Done Register

PCIBAR0MPRG PCI Base Address Mask Register 0 Program Register






PCIBAR0PRG PCI Base Address Register 0 Program Register










151

TMS320DM647

TMS320DM648

HEX ADDRESS OFFSET

0x4000 0000 - 0x407F FFFF

0x4080 0000 - 0x40FF FFFF

0x4100 0000 - 0x417F FFFF

0x4180 0000 - 0x41FF FFFF

0x4200 0000 - 0x427F FFFF

0x4280 0000 - 0x42FF FFFF

0x4300 0000 - 0x437F FFFF

0x4380 0000 - 0x43FF FFFF

0x4400 0000 - 0x447F FFFF

0x4480 0000 - 0x44FF FFFF

0x4500 0000 - 0x457F FFFF

0x4580 0000 - 0x45FF FFFF

0x4600 0000 - 0x467F FFFF

0x4680 0000 - 0x46FF FFFF

0x4700 0000 - 0x477F FFFF

0x4780 0000 - 0x47FF FFFF

0x4800 0000 - 0x487F FFFF

0x4880 0000 - 0x48FF FFFF

0x4900 0000 - 0x497F FFFF

0x4980 0000 - 0x49FF FFFF

0x4A00 0000 - 0x4A7F FFFF

0x4A80 0000 - 0x4AFF FFFF

0x4B00 0000 - 0x4B7F FFFF

0x4B80 0000 - 0x4BFF FFFF

0x4C00 0000 - 0x4C7F FFFF

0x4C80 0000 - 0x4CFF FFFF

0x4D00 0000 - 0x4D7F FFFF

0x4D80 0000 - 0x4DFF FFFF

0x4E00 0000 - 0x4E7F FFFF

0x4E80 0000 - 0x4EFF FFFF

0x4F00 0000 - 0x4F7F FFFF

0x4F80 0000 - 0x4FFF FFFF


DSP ACCESS


0x0204 87DC

0x0204 87E0

0x0204 87E4

0x0204 87E8

0x0204 87EC

0x0204 87F0

0x0204 87F4

0x0204 87F8

0x0204 87FC - 0x0204 87FF

Table 6-71. PCI Hook Configuration Registers (continued)



PCIBAR0TRLPRG PCI Base Address Translation Register 0 Program Register






PCIBASENPRG PCI Base En Prog Register

Reserved

Table 6-72. PCI External Memory Space

REGISTER NAME

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ACRONYM

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

PCI Master Window 0

PCI Master Window 1

PCI Master Window 2

PCI Master Window 3

PCI Master Window 4

PCI Master Window 5

PCI Master Window 6

PCI Master Window 7

PCI Master Window 8

PCI Master Window 9

PCI Master Window 10






















www.ti.com

152






TMS320DM647



6.17.3 PCI Electrical Data/Timing

Texas Instruments (TI) has performed the simulation and system characterization to be sure that the PCI peripheral meets all ac timing specifications as required by the PCI Local Bus Specification (version 2.3).

The ac timing specifications are not reproduced here. For more information on the ac timing specifications, see Section 4.2.3, Timing Specification (33 MHz timing), and Section 7.6.4, Timing Specification (66 MHz timing), of the PCI Local Bus Specification (version 2.3). Note that the PCI peripheral only supports 3.3-V signaling.






153

TMS320DM647

TMS320DM648


www.ti.com

6.18 Multichannel Audio Serial Port (McASP)

The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated

Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).

6.18.1 McASP Device-Specific Information

The device includes one multichannel audio serial port (McASP) interface peripheral. The McASP is a serial port optimized for the needs of multichannel audio applications.

The McASP consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. The McASP module also includes a pool of 16 shift registers that may be configured to operate as either transmit data or receive data.

The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for

S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial format.

The McASP can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the same format. However, the transmit and receive formats need not be the same.

Both the transmit and receive sections of the McASP also support burst mode which is useful for nonaudio data (for example, passing control information between two DSPs).

The McASP peripheral has additional capability for flexible clock generation, and error detection/handling, as well as error management.

For more detailed information on and the functionality of the McASP peripheral, see the

TMS320DM647/DM648 Multichannel Audio Serial Port (McASP) User's Guide (literature number

SPRUEL1 ).

6.18.1.1 McASP Block Diagram

Figure 6-48

illustrates the major blocks along with external signals of the McASP peripheral; and shows the 10 serial data [AXR] pins.

154






www.ti.com

DIT

RAM

T ransmit

Clock Check

(High-

Frequency)

McASP

Transmit

Frame Sync

Generator

Transmit

Clock

Generator

Error

Detect

Receive

Clock Check

(High-

Frequency)

Transmit

Data

Formatter

Receive

Clock

Generator

Receive

Frame Sync

Generator

AFSR

AFSX

AHCLKX

ACLKX

AMUTE

AMUTEIN

AHCLKR

ACLKR

TMS320DM647

TMS320DM648


Serializer 0

Serializer 1

Serializer 2

Serializer 3

Serializer 9

AXR0[0]

AXR0[1]

AXR0[2]

AXR0[3]

AXR0[9]

Receive

Data

Formatter

GPIO

Control

Figure 6-48. McASP Configuration






155

TMS320DM647

TMS320DM648


www.ti.com

0x0204 0020

0x0204 0024 - 0x0204 0040

0x0204 0044

0x0204 0048

0x0204 004C

0x0204 0050

0x0204 0054 - 0x0204

005C

0x0204 0060

0x0204 0064

0x0204 0068

0x0204 006C

0x0204 0070

0x0204 0074

0x0204 0078

0x0204 007C

0x0204 0080

0x0204 0084

0x0204 0088

0x0204 008C - 0x0204

009C

0x0204 00A0

0x0204 00A4

0x0204 00A8

0x0204 00AC

0x0204 00B0

0x0204 00B4

0x0204 00B8

0x0204 00BC

0x0204 00C0

0x0204 00C4

0x0204 00C8

6.18.1.2 McASP Peripheral Register Description(s)


0x0204 0000

0x0204 0004

0x0204 0008

0x0204 000C

0x0204 0010

0x0204 0014

0x0204 0018

0x0204 001C

RGBLCTL

RMASK

RFMT

AFSRCTL

ACLKRCTL

AHCLKRCTL

RTDM

RINTCTL

RSTAT

RSLOT

RCLKCHK

-

Table 6-73. McASP Control Registers

ACRONYM

PID

PWRDEMU

-

-

PFUNC

REGISTER NAME

Peripheral Identification register [Register value: 0x0010 0101]

Power down and emulation management register

Reserved

Reserved

Pin function register

PDIR

PDOUT

Pin direction register

Pin data out register

Pin data in/data set register

PDIN/PDSET Read returns: PDIN

Writes affect: PDSET

PDCLR

-

Pin data clear register

Reserved

GBLCTL

AMUTE

DLBCTL

DITCTL

Global control register

Mute control register

Digital Loop-back control register

DIT mode control register

Reserved

XGBLCTL

XMASK

XFMT

AFSXCTL

ACLKXCTL

AHCLKXCTL

XTDM

XINTCTL

XSTAT

XSLOT

XCLKCHK

Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive.

Receiver format UNIT bit mask register

Receive bit stream format register

Receive frame sync control register

Receive clock control register

High-frequency receive clock control register

Receive TDM slot 0-31 register

Receiver interrupt control register

Status register - Receiver

Current receive TDM slot register

Receiver clock check control register

Reserved

Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive.

Transmit format UNIT bit mask register

Transmit bit stream format register

Transmit frame sync control register

Transmit clock control register

High-frequency Transmit clock control register

Transmit TDM slot 0-31 register

Transmit interrupt control register

Status register - Transmitter

Current transmit TDM slot

Transmit clock check control register

156






www.ti.com

Table 6-73. McASP Control Registers (continued)


-

XBUF0

XBUF1

XBUF2

XBUF3

XBUF4

XBUF5

XBUF6

XBUF7

SRCTL0

SRCTL1

SRCTL2

SRCTL3

SRCTL4

SRCTL5

SRCTL6

SRCTL7

SRCTL8

SRCTL9

-

DITUDRA1

DITUDRA2

DITUDRA3

DITUDRA4

DITUDRA5

DITUDRB0

DITUDRB1

DITUDRB2

DITUDRB3

DITUDRB4

DITUDRB5

DITCSRA0

DITCSRA1

DITCSRA2

DITCSRA3

DITCSRA4

DITCSRA5

DITCSRB0

DITCSRB1

DITCSRB2

DITCSRB3

DITCSRB4

DITCSRB5

DITUDRA0

-

Reserved

Left (even TDM slot) channel status register file






Right (odd TDM slot) channel status register file






Left (even TDM slot) user data register file






Right (odd TDM slot) user data register file






Reserved

Serializer 0 control register










Reserved

Transmit Buffer for Serializer 0








TMS320DM647

TMS320DM648



0x0204 00CC - 0x0204

00FC

0x0204 0100

0x0204 0104

0x0204 0108

0x0204 010C

0x0204 0110

0x0204 0114

0x0204 0118

0x0204 011C

0x0204 0120

0x0204 0124

0x0204 0128

0x0204 012C

0x0204 0130

0x0204 0134

0x0204 0138

0x0204 013C

0x0204 0140

0x0204 0144

0x0204 0148

0x0204 014C

0x0204 0150

0x0204 0154

0x0204 0158

0x0204 015C

0x0204 0160 - 0x0204

017C

0x0204 0180

0x0204 0184

0x0204 0188

0x0204 018C

0x0204 0190

0x0204 0194

0x0204 0198

0x0204 019C

0x0204 01A0

0x0204 01A4

0x0204 01A8 - 0x0204

01FC

0x0204 0200

0x0204 0204

0x0204 0208

0x0204 020C

0x0204 0210

0x0204 0214

0x0204 0218

0x0204 021C






157

TMS320DM647

TMS320DM648



0x0204 021A

0x0204 0220

0x0204 0224-0x0204 027C

0x0204 0280

0x0204 0284

0x0204 0288

0x0204 028C

0x0204 0290

0x0204 0294

0x0204 0298

0x0204 029C

0x0204 02A0

0x0204 02A4

0x0204 02A8-0x0204 3FFF

Table 6-73. McASP Control Registers (continued)

ACRONYM

XBUF8

XBUF9

-

RBUF0

RBUF1

RBUF2

RBUF3

RBUF4

RBUF5

RBUF6

RBUF7

RBUF8

RBUF9

-



Reserved

Receive Buffer for Serializer 0










Reserved

REGISTER NAME www.ti.com


0204 4000 - 0204 43FF

Table 6-74. McASP Data Registers


RBUF/XBUF

McASP receive buffers or McASP transmit buffers via the Peripheral Data Bus.

COMMENTS

(Used when RSEL or XSEL bits = 0

[these bits are located in the RFMT or

XFMT registers, respectively].)

6.18.1.3 McASP Electrical Data/Timing

6.18.1.3.1 Multichannel Audio Serial Port (McASP) Timing

NO.

1 t c(AHCKRX)

2 t w(AHCKRX)

3 t c(CKRX)

4 t w(CKRX)

Table 6-75. Timing Requirements for McASP (see

Figure 6-49

and

Figure 6-50

)

(1)

5 t su(FRX-CKRX)

6 t h(CKRX-FRX)

7 t su(AXR-CKRX)

8 t h(CKRX-AXR)

Cycle time, AHCLKR/X

Pulse duration, AHCLKR/X high or low

Cycle time, ACLKR/X

Pulse duration, ACLKR/X high or low

Setup time, AFSR/X input valid before ACLKR/X latches data

Hold time, AFSR/X input valid after ACLKR/X latches data

Setup time, AXR input valid before ACLKR/X latches data

Hold time, AXR input valid after ACLKR/X latches data

ACLKR/X ext

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

720, 800, 900,

1100

MIN MAX

20

10

33

16.5

5

12.08

5

5

5

5

5

7.35

(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

UNIT


158






TMS320DM647



NO.

Table 6-76. Switching Characteristics Over Recommended Operating Conditions for McASP

(see

Figure 6-49

and

Figure 6-50 )

(1)

9 t c(AHCKRX)

10 t w(AHCKRX)

11 t c(CKRX)

12 t w(CKRX)

13 t d(CKRX-FRX)

14 t d(CKX-AXRV)

15 t dis(CKRX-AXRHZ)

PARAMETER

Cycle time, AHCLKR/X

Pulse duration, AHCLKR/X high or low

Cycle time, ACLKR/X

Pulse duration, ACLKR/X high or low

Delay time, ACLKR/X transmit edge to AFSX/R output valid

Delay time, ACLKX transmit edge to AXR output valid

Disable time, AXR high impedance following last data bit from

ACLKR/X transmit edge

ACLKR/X int

ACLKR/X int

ACLKR/X int

ACLKR/X ext

ACLKX int

ACLKX ext

ACLKR/X int

ACLKR/X ext

720, 800, 900,

1100

MIN MAX

20

10

33

16.5

5

14.28

10

12.5

10

12.5

UNIT


(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1






159

TMS320DM647

TMS320DM648


www.ti.com

1 2

2

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

4

3

4

ACLKR/X (CLKRP = CLKXP = 0)

(A)


(B)

6

5

AFSR/X (Bit Width, 0 Bit Delay)



AFSR/X (Slot Width, 0 Bit Delay)



8

7

AXR[n] (Data In/Receive)

A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3

A.

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).

B.

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).

C31

Figure 6-49. McASP Input Timing

160






TMS320DM647

TMS320DM648


www.ti.com

AHCLKR/X (Falling Edge Polarity)

9

AHCLKR/X (Rising Edge Polarity)


(A)


(B)

11



10

10

13

12

12

13

13

13




13 13

13


14

15

AXR[n] (Data Out/T ransmit)

A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3

A.

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).

B.

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).

Figure 6-50. McASP Output Timing

C31






161

TMS320DM647

TMS320DM648


www.ti.com

6.19 3-Port Ethernet Switch Subsystem (3PSW)

The Ethernet module controls the flow of packet data between the device and two external Ethernet PHYs

(DM648 only) or one external Ethernet PHY (DM647 only), with hardware flow control and quality-ofservice (QOS) support. See

Figure 6-51

for a block diagram of the Ethernet module. The Ethernet

Subsystem contains a 3-port gigabit switch, where one port is internally connected to the C64x+ DSP (via the switched central resource) and the other two ports are brought out externally. Each of the external

Ethernet ports support the modes shown in

Table 6-77

.

The Ethernet module controls the flow of packet data between the device and two external Ethernet

PHYs , with hardware flow control and quality-of-service (QOS) support. See

Figure 6-51

for a block diagram of the Ethernet module. The Ethernet Subsystem contains a 3-port gigabit switch, where one port is internally connected to the C64x+ DSP (via the switched central resource) and the other two ports are brought out externally. Each of the external Ethernet ports support the modes shown in

Table 6-77 .

DESCRIPTION

10Base-T

100Base-T

1000Base-T

Table 6-77. Ethernet Operating Modes

DATA RATE

10 Mbits/second (Mbps)



OPERATING MODE

half- or full-duplex half- or full-duplex full-duplex

The Ethernet Subsystem provides these functions:

• Ethernet communication/routing by way of two dedicated 10/100/1000 ports with SGMII interfaces

– Wire-rate switching (802.1d), non-blocking switch fabric

– Four priority levels of QoS TX support (802.1p) in hardware

– Programmable interrupt pacing on RX/TX plus interrupt threshold on RX

– Supports forwarding frame sizes of 64-2020 bytes

• Address Lookup

– 1024 total address lookup engine (ALE) entries of VLANs and/or MAC addresses

– L2 address lock and L2 filtering support

– Multicast/broadcast filtering and forwarding state control

– Receive-based or destination-based multicast and broadcast rate limits

– MAC address blocking

– Source port locking

– OUI (Vendor ID) host accept/deny feature

– Host controlled time-based aging

– MAC authentication (802.1x)

– Remapping of priority level of VLAN or ports

– Multiple spanning tree support (spanning tree per VLAN)

162






TMS320DM647



• VLAN support

– 802.1Q compliant

• Auto add port VLAN for untagged frames on ingress

• Auto VLAN removal on egress and auto pad to minimum frame size

– Flow control (IEEE 802.3x)

– Programmable priority escalation to specify delivery of lower priority level packets in the event of over-subscribed TX high priority traffic

– Host pass CRC mode (enables CRC protection through host)

– Write-protect option for Ethernet module registers (3PGSW, CPPI RAM, MDIO, SGMII0, SGMII1, control)

– Ethernet statistics:

• EtherStats and 802.3 Stats RMON statistics gathering (shared)

• Programmable statistics interrupt mask when a statistic is above one half its 32-bit value

– MDIO module for PHY management

– SGMII gigabit current mode logic (CML) differential SERializer/DESerializer (SerDes) I/O receiver/transmitters

• Adaptive active equalization for superior data dependent jitter tolerance in the presence of a lossy channel

• Loss of signal detector with programmable threshold levels in receive channels

• Integrated receiver and transmitter termination

• IEEE 802.3 gigabit Ethernet conformant

6.19.1 Ethernet Subsystem Functions

Configuration

Bus

Peripheral

Bus

Configuration

Registers

Host DMA

Controller

Buffer

Descriptor

Memory

3-port

Gigabit

Switch

Gigabit

MAC 0

GMII port 0 SGMII 0

Addr Lookup

Engine

Gigabit

MAC 1

GMII port 1

SGMII 1

(A)

2

2

SGMII

Port 0

2

REFCLK

2

2

SGMII

Port 1

DSP

Interrupt

Controller

Configuration

Bus

MDIO

MII

Serial

Mgmt

A.

SGMII port 1 is not available on DM647.

Figure 6-51. Ethernet Subsystem Block Diagram






163

TMS320DM647

TMS320DM648


www.ti.com

The Ethernet Subsystem conforms to the IEEE 802.3-2002 standard. Deviating from this standard, the

GMAC module does not use the transmit coding error signal MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the GMAC generates an incorrect checksum by inverting the frame CRC, so that the transmitted frame will be detected as an error by the network.

In networking systems, packet transmission and reception are critical tasks. The communications port programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software and communications modules. The CPPI block contains 2048 words of 32-bit buffer descriptor memory that holds up to 512 buffer descriptors.

After reset, initialization, configuration, and auto-negotiation, the host C64x+ DSP may initiate Ethernet transmit and receive operations.

• Transmit operations are initiated by C64x+ DSP writes to the appropriate transmit channel head descriptor pointer contained in the CPDMA block. The CPDMA TX controller then fetches the first packet in the packet chain from memory in accordance with the CPPI protocol for the GMAC to process before sending to the SGMII.

• Receive operations are initiated by C64x+ DSP writes to the appropriate receive channel head descriptor pointer. The CPDMA RX controller then writes packets to memory in accordance with the

CPPI protocol.

DSP writes may be write-protected to the Ethernet Subsystem configuration registers from addresses

0x02D0 0000 - 0x02D0 4FFF (3PGSW, MDIO, SGMII0, SGMII1, control), and the CPPI RAM. The

Ethernet Subsystem setting in the PSC is also write-protected. A specific 32-bit lock code (0x4C6F436B) and a 32-bit unlock code (0x6F50654E) written to ESS_LOCK register will activate or clear this option, respectively. See

Section 3.2.5

and

Section 3.2.7

The 3-port gigabit switch block contains the following functions:

• 3-port gigabit switch: performs packet forwarding and routing functions, one port is internally connected to the C64x+ DSP and two ports are brought out externally

• CPDMA: performs high-speed DMA transfers with RX and TX CPPI buffers in local memory, including channel setup and channel teardown

• GMAC (Gigabit Ethernet MAC):

– Uses Rx packet FIFO, and a TX packet FIFO to improve data transfer efficiency

– Handles processing of Ethernet packet data, frames, and headers

– Includes flow control

– Provides statistics collection and reporting

• The address lookup engine (ALE) processes all received packets to determine where (that is, which packet location) to forward the packet. The ALE uses the incoming packet received port number, destination address, source address, length/type, and VLAN information to determine how the packet should be forwarded. The ALE outputs the port mask to the switch fabric that indicates to which port(s) the packet should be forwarded.

6.19.2 Interrupt Controller and Pacing Interrupts

The interrupt control block selects the interrupts from the 3-port gigabit switch and MDIO modules for output to the C64x+ DSP. The miscellaneous interrupt is an immediate (non-paced) interrupt selected from the miscellaneous interrupts (host error level, statistics level, MDIO User [2], MDIO link [2]).

The eight RX interrupts and eight TX interrupts can be paced. The 8 RX threshold interrupts and the miscellaneous interrupts are not paced. The interrupt pacing feature limits the number of interrupts that occur during a given period of time. For heavily loaded systems in which interrupts can occur at a very high rate, the performance benefit is significant due to minimizing the overhead associated with servicing each interrupt. Interrupt pacing increases the C64x+ DSP cache hit ratio by minimizing the number of times that large interrupt service routines are moved to and from the DSP instruction cache.

MDIO

164






TMS320DM647



The MDIO module manages the PHY configuration and monitors status. For a list of supported registers and register fields, see

Table 6-79 . In 10/100 mode, the GMII_MTXD(7:0) data bus uses only the lower

nibble.

SGMII

The SGMII/SerDes module contains:

• Gigabit differential current mode logic (CML) receiver/transmitters

• An integrated RX/TX PLL to provide the required high-quality/high-speed internal clocks

• Phase-interpolator-based clock/data recovery

• A bandgap reference for transmitter swing settings

• Parallel-to-serial converter

• Serial-to-parallel converter

• Integrated receiver and transmitter termination

• Configuration logic

• 802.3 auto-negotiation functionality (as defined in Clause 37 of the IEEE Specification 802.3)

The SGMII receive interface converts the encoded receive signals from the differential receive input terminals (SGMII0RXN: SGMII0RXP, SGMII1RXN: SGMII1RXP) into the required GMAC GMII signals.

The SGMII transmit interface converts the GMAC GMII data into the required encoded differential transmit output terminals (SGMII0TXN: SGMII0TXP, SGMII1TXN: SGMII1TXP). The GMAC does not source the transmit error signal. Any transmit frame from the GMAC with an error (ie., underrun) will be indicated as an error by an error CRC.

NOTE

SGMII1 is pinned out only in the DM648 device. The DM647 device has only one SGMII port

(SGMII0).

6.19.3 Peripheral Register Description(s)

Table 6-78

through

Table 6-81

list the registers.


0x02D0 3000

0x02D0 3004

0x02D0 3008

0x02D0 300C

0x02D0 3010

0x02D0 3014

0x02D0 3018

0x02D0 301C

0x02D0 3020

0x02D0 3024

0x02D0 3028

0x02D0 302C

0x02D0 3030

0x02D0 3034

0x02D0 3038

0x02D0 303C

0x02D0 3040

Table 6-78. Ethernet Switch Registers


CPSW_ID_VER

CPSW_CONTROL

CPSW_SOFT_RESET

CPSW_STAT_PORT_EN

CPSW_PTYPE

P0_MAX_BLKS

P0_BLK_CNT

P0_FLOW_THRESH

P0_PORT_VLAN

P0_TX_PRI_MAP

GMAC0_GAP_THRESH

GMAC0_SA_LO

GMAC0_SA_HI

P1_MAX_BLKS

P1_BLK_CNT

P1_FLOW_THRESH

P1_PORT_VLAN

DESCRIPTION

CPSW Identification and Version Register

CPSW Switch Control Register

CPSW Soft Reset Register

CPSW Statistics Port Enable Register

CPSW Transmit Priority Type Register

CPSW Port 0 Maximum FIFO blocks Register

CPSW Port 0 FIFO Block Usage Count Register (read only)

CPSW Port 0 Flow Control Threshold Register

CPSW Port 0 VLAN Register

CPSW Port 0 Tx Header Pri to Switch Pri Mapping Register

CPSW GMAC0 Short Gap Threshold Register

CPSW GMAC0 Source Address Low Register

CPSW GMAC0 Source Address High Register










165

TMS320DM647

TMS320DM648


www.ti.com


0x02D0 3044

0x02D0 3048

0x02D0 304C

0x02D0 3050

0x02D0 3054

0x02D0 3058

0x02D0 305C

0x02D0 3060

0x02D0 3064

0x02D0 3068

0x02D0 306C

0x02D0 3070 - 0x02D0 307C

0x02D0 3080

0x02D0 3084

0x02D0 3088

0x02D0 308C

0x02D0 3090

0x02D0 3094

0x02D0 3098

0x02D0 309C

0x02D0 30A0

0x02D0 30A4

0x02D0 30A8 - 0x02D0 30BC

0x02D0 30C0

0x02D0 30C4

0x02D0 30C8

0x02D0 30CC

0x02D0 30D0

0x02D0 30D4

0x02D0 30D8

0x02D0 30DC

0x02D0 30E0

0x02D0 30E4

0x02D0 30E8 - 0x02D0 30FC

0x02D0 3100

0x02D0 3104

0x02D0 3108

0x02D0 310C

0x02D0 3110

0x02D0 3114

0x02D0 3118

0x02D0 311C

0x02D0 3120

0x02D0 3124

Table 6-78. Ethernet Switch Registers (continued)


P1_TX_PRI_MAP

GMAC1_GAP_THRESH

GMAC1_SA_LO

GMAC1_SA_HI

P2_MAX_BLKS

P2_BLK_CNT

P2_FLOW_THRESH

P2_PORT_VLAN

P2_TX_PRI_MAP

CPDMA_TX_PRI_MAP

CPDMA_RX_CH_MAP

DESCRIPTION

CPSW Port 1 Tx Header Priority to Switch Pri Mapping

Register

CPSW GMAC1 Short Gap Threshold Register

CPSW GMAC1 Source Address Low Register

CPSW GMAC1 Source Address High Register





CPSW Port 2 Tx (CPDMA Rx) Header Priority to Switch Pri

Mapping Register

CPSW CPDMA Tx (Port 2 Rx) Pkt Priority to Header Priority

Mapping Register

CPSW CPDMA Rx (Port 2 Tx) Switch Priority to DMA channel Mapping Register reserved

GMAC0_IDVER

GMAC0_MACCONTROL

GMAC0_MACSTATUS

GMAC0_SOFT_RESET

GMAC0_RX_MAXLEN

GMAC0_BOFFTEST reserved reserved

GMAC0_EMCONTROL

GMAC0_RX_PRI_MAP reserved

GMAC1_IDVER

GMAC1_MACCONTROL

GMAC1_MACSTATUS

GMAC1_SOFT_RESET

GMAC1_RX_MAXLEN

GMAC1_BOFFTEST reserved reserved

GMAC1_EMCONTROL

GMAC1_RX_PRI_MAP reserved

TX_IDVER

TX_CONTROL

TX_TEARDOWN reserved

RX_IDVER

RX_CONTROL

RX_TEARDOWN

SOFT_RESET

DMACONTROL

DMASTATUS

GMAC0 Identification and Version Register

GMAC0 Mac Control Register

GMAC0 Mac Status Register

GMAC0 Soft Reset Register

GMAC0 RX Maximum Length Register

GMAC0 Backoff Test Register

GMAC0 Emulation Control Register

GMAC0 Rx Pkt Priority to Header Priority Mapping Register

GMAC1 Identification and Version Register

GMAC1 Mac Control Register

GMAC1 Mac Status Register

GMAC1 Soft Reset Register

GMAC1 RX Maximum Length Register

GMAC1 Backoff Test Register

GMAC1 Emulation Control Register

GMAC1 Rx Pkt Priority to Header Priority Mapping Register

CPDMA Tx Identification and Version Register

CPDMA Tx Control Register

CPDMA Tx Teardown Register

CPDMA Rx Identification and Version Register

CPDMA Rx Control Register

CPDMA Rx Teardown Register

CPDMA Soft Reset Register

CPDMA Control Register

CPDMA Status Register

166






TMS320DM647



0x02D0 31CC

0x02D0 31D0

0x02D0 31D4

0x02D0 31D8

0x02D0 31DC

0x02D0 31E0

0x02D0 31E4

0x02D0 31E8

0x02D0 31EC

0x02D0 31F0

0x02D0 31F4

0x02D0 31F8

0x02D0 31FC

0x02D0 3200

0x02D0 3204

0x02D0 3208

0x02D0 320C

0x02D0 3210

0x02D0 3214

0x02D0 3218

0x02D0 321C

0x02D0 3220

0x02D0 3224

0x02D0 3228

0x02D0 322C

0x02D0 3230


0x02D0 3128

0x02D0 312C

0x02D0 3130 - 0x02D0 317C

0x02D0 3180

0x02D0 3184

0x02D0 3188

0x02D0 318C

0x02D0 3190

0x02D0 3194

0x02D0 3198 - 0x02D0 319C

0x02D0 31A0

0x02D0 31A4

0x02D0 31A8

0x02D0 31AC

0x02D0 31B0

0x02D0 31B4

0x02D0 31B8

0x02D0 31BC

0x02D0 31C0

0x02D0 31C4

0x02D0 31C8


RX3_PENDTHRESH

RX4_PENDTHRESH

RX5_PENDTHRESH

RX6_PENDTHRESH

RX7_PENDTHRESH

RX0_FREEBUFFER

RX1_FREEBUFFER

RX2_FREEBUFFER

RX3_FREEBUFFER

RX4_FREEBUFFER

RX5_FREEBUFFER

RX6_FREEBUFFER

RX7_FREEBUFFER

TX0_HDP

TX1_HDP

TX2_HDP

TX3_HDP

TX4_HDP

TX5_HDP

TX6_HDP

TX7_HDP

RX0_HDP

RX1_HDP

RX2_HDP

RX3_HDP

RX4_HDP


RX_BUFFER_OFFSET

EMCONTROL reserved

TX_INTSTAT_RAW

TX_INTSTAT_MASKED

TX_INTMASK_SET

TX_INTMASK_CLEAR

CPDMA_IN_VECTOR

CPDMA_EOI_VECTOR reserved

RX_INTSTAT_RAW

RX_INTSTAT_MASKED

RX_INTMASK_SET

RX_INTMASK_CLEAR

DMA_INTSTAT_RAW

DMA_INTSTAT_MASKED

DMA_INTMASK_SET

DMA_INTMASK_CLEAR

RX0_PENDTHRESH

RX1_PENDTHRESH

RX2_PENDTHRESH

DESCRIPTION

CPDMA Rx Buffer Offset Register

CPDMA Emulation Control Register

CPDMA Tx interrupt Status Register (raw value)

CPDMA Tx Interrupt Status Register (masked value)

CPDMA Tx Interrupt Mask Set Register

CPDMA Tx Interrupt Mask Clear Register

CPDMA Input Vector Register (read only)

CPDMA End Of Interrupt Vector Register

CPDMA Rx Interrupt Status Register (raw value)

CPDMA Rx Interrupt Status Register (masked value)

CPDMA Rx Interrupt Mask Set Register

CPDMA Rx Interrupt Mask Clear Register

CPDMA DMA Interrupt Status Register (raw value)

CPDMA DMA Interrupt Status Register (masked value)

CPDMA DMA Interrupt Mask Set Register

CPDMA DMA Interrupt Mask Clear Register

CPDMA Rx Threshold Pending Register Channel 0








CPDMA Rx Free Buffer Register Channel 0








CPDMA Tx Channel 0 Head Desc Pointer








CPDMA Rx 0 Channel 0 Head Desc Pointer










167

TMS320DM647

TMS320DM648


www.ti.com


0x02D0 3234

0x02D0 3238

0x02D0 323C

0x02D0 3240

0x02D0 3244

0x02D0 3248

0x02D0 324C

0x02D0 3250

0x02D0 3254

0x02D0 3258

0x02D0 325C

0x02D0 3260

0x02D0 3264

0x02D0 3268

0x02D0 326C

0x02D0 3270

0x02D0 3274

0x02D0 3278

0x02D0 327C

0x02D0 3280 - 0x02D0 32BF

0x02D0 32C0 - 0x02D0 32FC

0x02D0 3300 - 0x02D0 337C

0x02D0 3380 - 0x02D0 33FC

0x02D0 3400

0x02D0 3404

0x02D0 3408

0x02D0 340C

0x02D0 3410

0x02D0 3414

0x02D0 3418

0x02D0 341C

0x02D0 3420

0x02D0 3424

0x02D0 3428

0x02D0 342C

0x02D0 3430

0x02D0 3434

0x02D0 3438

0x02D0 343C

0x02D0 3440

0x02D0 3444

0x02D0 3448

0x02D0 344C

0x02D0 3450



RX5_HDP

RX6_HDP

RX7_HDP

TX0_CP

TX1_CP

TX2_CP

TX3_CP

TX4_CP

TX5_CP

TX6_CP

TX7_CP

RX0_CP

RX1_CP

RX2_CP

RX3_CP

RX4_CP

RX5_CP

RX6_CP

RX7_CP reserved reserved reserved reserved

RXGOODFRAMES

RXBROADCASTFRAMES

DESCRIPTION




CPDMA Tx Channel 0 Completion Pointer Register








CPDMA Rx Channel 0 Completion Pointer Register








RXMULTICASTFRAMES

RXPAUSEFRAMES

RXCRCERRORS

RXALIGNCODEERRORS

RXOVERSIZEDFRAMES

RXJABBERFRAMES

RXUNDERSIZEDFRAMES

RXFRAGMENTS reserved reserved

RXOCTETS

CPSW_STATS Total number of good frames received

CPSW_STATS Total number of good broadcast frames received

CPSW_STATS Total number of good multicast frames received

CPSW_STATS PauseRxFrames

CPSW_STATS Total number of CRC errors frames received

CPSW_STATS Total number of alignment/code errors received

CPSW_STATS Total number of oversized frames received

CPSW_STATS Total number of jabber frames received

CPSW_STATS Total number of undersized frames received

CPSW_STATS RxFragments received

TXGOODFRAMES

TXBROADCASTFRAMES

TXMULTICASTFRAMES

TXPAUSEFRAMES

TXDEFERREDFRAMES

TXCOLLISIONFRAMES

TXSINGLECOLLFRAMES

TXMULTCOLLFRAMES

CPSW_STATS Total number of received bytes in good frames

CPSW_STATS GoodTxFrames

CPSW_STATS BroadcastTxFrames

CPSW_STATS MulticastTxFrames

CPSW_STATS PauseTxFrames

CPSW_STATS Deferred Frames

CPSW_STATS Collisions

CPSW_STATS SingleCollisionTxFrames

CPSW_STATS MultipleCollisionTxFrames

168






TMS320DM647




0x02D0 3454

0x02D0 3458

0x02D0 345C

0x02D0 3460

0x02D0 3464

0x02D0 3468

0x02D0 346C

0x02D0 3470

0x02D0 3474

0x02D0 3478

0x02D0 347C

0x02D0 3480

0x02D0 3484

0x02D0 3488

0x02D0 348C

0x02D0 3490 - 0x02D0 34FC

0x02D0 3500

0x02D0 3504

0x02D0 3508

0x02D0 350C

0x02D0 3510

0x02D0 3514

0x02D0 3518

0x02D0 351C

0x02D0 3520

0x02D0 3524 - 0x02D0 3530

0x02D0 3534

0x02D0 3538

0x02D0 353C

0x02D0 3540

0x02D0 3544

0x02D0 3548

0x02D0 354C - 0x02D0 37FF



TXEXCESSIVECOLLISIONS

DESCRIPTION

CPSW_STATS ExcessiveCollisions

TXLATECOLLISIONS CPSW_STATS LateCollisions

TXUNDERRUN CPSW_STATS Transmit Underrun Error

TXCARRIERSENSEERRORS CPSW_STATS CarrierSenseErrors

TXOCTETS

OCTETFRAMES64

CPSW_STATS TxOctets

CPSW_STATS 64octetFrames

OCTETFRAMES65T127

OCTETFRAMES128T255

OCTETFRAMES256T511

OCTETFRAMES512T1023

OCTETFRAMES1024TUP

NETOCTETS

RXSOFOVERRUNS

RXMOFOVERRUNS

RXDMAOVERRUNS

CPSW_STATS 65-127octetFrames





CPSW_STATS NetOctets

CPSW_STATS Receive FIFO or DMA Start of Frame

Overruns

CPSW_STATS Receive FIFO or DMA Mid of Frame

Overruns

CPSW_STATS Receive DMA Start of Frame and Middle of

Frame Overruns reserved

ALE_IDVER reserved

ALE_CONTROL reserved

ALE_PRESCALE reserved

ALE_UNKNOWN_VLAN reserved

ALE_TBLCTL reserved

ALE_TBLW2

ALE_TBLW1

ALE_TBLW0

ALE_PORTCTL0

ALE_PORTCTL1

ALE_PORTCTL2 reserved

ALE Identification and Version Register

ALE Control Register

ALE Prescale Register

ALE Unknown VLAN Register

ALE Table Control Register

ALE Table Word 2 Register



ALE Port 0 Control Register




0x02D0 2000

0x02D0 2004

0x02D0 2008

0x02D0 200C

0x02D0 2010

0x02D0 2014

0x02D0 2018

0x02D0 201C

0x02D0 2020

Table 6-79. Ethernet Subsystem Registers


IDVER

SOFT_RESET

EM_CONTROL

INT_CONTROL

RX_THRESH_EN

RX_EN

TX_EN

MISC_EN

RX_THRESH_STAT

DESCRIPTION

Identification and Version Register

Soft Reset Register

Emulation Control Register

Interrupt Control Register

Receive Threshold Interrupt Enable Register

Receive Interrupt Enable Register

Transmit Interrupt Enable Register

Misc Interrupt Enable Register

Receive Threshold Masked Interrupt Status Register






169

TMS320DM647

TMS320DM648



0x02D0 2024

0x02D0 2028

0x02D0 202C

0x02D0 2030

0x02D0 2034

Table 6-79. Ethernet Subsystem Registers (continued)


RX_STAT

TX_STAT

MISC_STAT

RX_IMAX

TX_IMAX

DESCRIPTION

Receive Interrupt Masked Interrupt Status Register

Transmit Interrupt Masked Interrupt Status Register

Misc Interrupt Masked Interrupt Status Register

Receive Interrupts Per Millisecond

Transmit Interrupts Per Millisecond

www.ti.com


0x02D0 4800

0x02D0 4804

0x02D0 4808 - 0x02D0 480C

0x02D0 4810

0x02D0 4814

0x02D0 4818

0x02D0 481C

0x02D0 4820

0x02D0 4824

0x02D0 4828 - 0x02D0 482C

0x02D0 4830

0x02D0 4834

0x02D0 4838

0x02D0 483C

0x02D0 4840

0x02D0 4844

0x02D0 4848

0x02D0 484C - 0x02D0 487F

Table 6-80. SGMII0 Registers

REGISTER NAME

IDVER

SOFT_RESET

Reserved

CONTROL

STATUS

MR_ADV_ABILITY

MR_NP_TX

MR_LP_ADV_ABILITY

MR_NP_RX

Reserved

Reserved

Reserved

Reserved

Reserved

DIAG_CLEAR

DIAG_CONTROL

DIAG_STATUS

Reserved

DESCRIPTION


Soft Reset Register

Reserved

Control Register

Status Register (read only)

Advertised Ability Register

Transmit Next Page Register

Link Partner Advertised Ability (read only)

Link Partner Receive Next Page Register (read only)

Reserved

Reserved

Reserved

Reserved

Reserved

Diagnostics Clear Register

Diagnostics Control Register

Diagnostics Status Register (read only)

Reserved

170


0x02D0 4C00

0x02D0 4C04

0x02D0 4C08 - 0x02D0 4C0C

0x02D0 4C10

0x02D0 4C14

0x02D0 4C18

0x02D0 4C1C

0x02D0 4C20

0x02D0 4C24

0x02D0 4C28 - 0x02D0 4C2C

0x02D0 4C30

0x02D0 4C34

0x02D0 4C38

0x02D0 4C3C

0x02D0 4C40

0x02D0 4C44

0x02D0 4C48

0x02D0 4C4C - 0x02D0 4C7F

Table 6-81. SGMII1 Registers

REGISTER NAME

IDVER

SOFT_RESET

Reserved

CONTROL

STATUS

MR_ADV_ABILITY

MR_NP_TX

MR_LP_ADV_ABILITY

MR_NP_RX

Reserved

Reserved

Reserved

Reserved

Reserved

DIAG_CLEAR

DIAG_CONTROL

DIAG_STATUS

Reserved

DESCRIPTION


Soft Reset Register

Reserved

Control Register

Status Register (read only)

Advertised Ability Register

Transmit Next Page Register

Link Partner Advertised Ability (read only)

Link Partner Receive Next Page Register (read only)

Reserved

Reserved

Reserved

Reserved

Reserved

Diagnostics Clear Register

Diagnostics Control Register

Diagnostics Status Register (read only)

Reserved






TMS320DM647



6.19.4 Ethernet Subsystem Timing

t

01

Table 6-82. Ethernet Subsystem Timing Requirements

PARAMETER

(1)

REFCLKP/N period, mode

MIN NOM

x 10 mode x 20 mode x 25 mode

8

16

20 t

02 t

03 t

04 t

05

REFCLKP/N duty cycle

REFCLKP/N rise/fall

PLL Clock Period, x n Mode

PLL power up

(1) C = REFCLKP/N period in μ s.

40

700 t

01

/ n

MAX

60

1 + 200 * C

UNITS

ns ns ns

% ps ns

μ s

REFCLKP/N Jitter and PLL Loop Bandwidth

Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby impairing system performance. A good quality, low jitter reference clock is necessary to achieve compliance with most if not all physical layer standards (see

Table 6-83

).

Standard

Gigabit Ethernet

Table 6-83. REFCLKP/N Jitter Requirements for Standards Compliance

Line Rate (Gbps)

1.25

Total REFCLKP/N Jitter (within PLL bandwidth)

50 ps pk-pk






171

TMS320DM647

TMS320DM648


www.ti.com

6.20 Management Data Input/Output (MDIO)

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system. It contains two user access registers to control and monitor up to two PHYs simultaneously.

The MDIO module implements the 802.3 serial management interface to interrogate and control two

Ethernet PHYs simultaneously using a shared two-wire bus.

6.20.1 MII Management Interface

Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the Ethernet Switch Subsystem, retrieve the negotiation results, and configure required parameters in the Ethernet Switch Subsystem module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. Only a maximum of two PHYs may be connected at any given time.

For more detailed information on the Ethernet Switch Subsystem, see the TMS320DM647/DM648 DSP

Ethernet Subsystem User's Guide Reference Guide (literature number SPRUF57 ). For a list of supported registers and register fields, see

Table 6-84

.

6.20.2 MDIO Register Descriptions


0x02D0 4000

0x02D0 4004

0x02D0 4008

0x02D0 400C

0x02D0 4010

Table 6-84. MDIO Registers


MDIOVER

MDIOCONTROL

MDIOALIVE

MDIOLINK

MDIOLINKINTRAW

0x02D0 4014 MDIOLINKINTMASKED

DESCRIPTION

Module version register

Module control register

PHY acknowledge status register

PHY link status register

Link status change interrupt register (raw value)

Link status change interrupt register (masked value)

0x02D0 4018 - 0x02D0 401C

0x02D0 4020 reserved

MDIOUSERINTRAW

0x02D0 4024 MDIOUSERINTMASKED

User command complete interrupt register

(raw value)

User command complete interrupt register

(masked value)

User interrupt mask set register

User interrupt mask clear register

0x02D0 4028

0x02D0 402C

0x02D0 4030 - 0x02D0 407C

0x02D0 4080

0x02D0 4084

0x02D0 4088

0x02D0 408C

0x02D0 4090 - 0x02D0 40FF

MDIOUSERINTMASKSET

MDIOUSERINTMASKCLR reserved

MDIOUSERACCESS0

MDIOUSERPHYSEL0

MDIOUSERACCESS1

MDIOUSERPHYSEL1 reserved

User access register0

User PHY select register0

User access register1

User PHY select register1

172






TMS320DM647



6.21 Timers

The device has four 64-bit general-purpose timers of which only Timer 0 and Timer 1 have external input/output. The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the EDMA3 channel controller.

6.21.1 General-Purpose Timers

Each timer can be programmed as a 64-bit timer or as two separate 32-bit timers. Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low counter. The high counter does not have any external device pins.

For more detailed information, see the TMS320DM647DM648 DSP 64-Bit Timer User's Guide (literature number SPRUEL0 ).

6.21.2 Timer Peripheral Register Descriptions


0x0204 4400

0x0204 4404

0x0204 4410

0x0204 4414

0x0204 4418

0x0204 441C

0x0204 4420

0x0204 4424

0x0x0204 4428 - 0x0204 44FF

Table 6-85. Timer 0 Registers

ACRONYM

PID12

EMUMGT_CLKSPD

TIM12

TIM34

PRD12

PRD34

TCR

TGCR

-

DESCRIPTION


Timer 0 Emulation Management/Clock Speed Register

Timer 0 Counter Register 12


Timer 0 Period Register 12


Timer 0 Control Register

Timer 0 Global Control Register

Reserved


0x0204 4800

0x0204 4804

0x0204 4810

0x0204 4814

0x0204 4818

0x0204 481C

0x0204 4820

0x0204 4824

0x0204 4828 - 0x0204 48FF


ACRONYM

PID12

EMUMGT_CLKSPD

TIM12

TIM34

PRD12

PRD34

TCR

TGCR

-

DESCRIPTION









Reserved


0x0204 4C00

0x0204 4C04

0x0204 4C10

0x0204 4C14

0x0204 4C18

0x0204 4C1C

0x0204 4C20

0x0204 4C24

0x0204 4C28 - 0x0204 4CFF


ACRONYM

PID12

EMUMGT_CLKSPD

TIM12

TIM34

PRD12

PRD34

TCR

TGCR

-

DESCRIPTION









Reserved






173

TMS320DM647

TMS320DM648



0x0204 5000

0x0204 5004

0x0204 5010

0x0204 5014

0x0204 5018

0x0204 501C

0x0204 5020

0x0204 5024

0x0204 5028 - 0x0204 50FF

www.ti.com


ACRONYM

PID12

EMUMGT_CLKSPD

TIM12

TIM34

PRD12

PRD34

TCR

TGCR

-

DESCRIPTION









Reserved

6.21.3 Timer Electrical Data/Timing

NO.

Table 6-89. Timing Requirements for Timer Input

(1)

(see

Figure 6-52

)

1

2 t w(TIMIxH) t w(TIMIxL)

Pulse duration, TIMIxH high

Pulse duration, TIMIxL low

(1) P = 1/CPU clock frequency in ns.

720, 800, 900,

1100

MIN

12P

(1)

MAX

12P

UNIT

ns ns

Table 6-90. Switching Characteristics for Timer Output

over operating free-air temperature range (unless otherwise noted)

NO.

PARAMETER

3

4 t w(TIMOxH) t w(TIMOxL)

Pulse duration, TIMOxH high

Pulse duration, TIMOxL low

(1) P = 1/CPU clock frequency in ns.

720, 800, 900, 1100

MIN

12P

(1)

TYP MAX

12P

2

1

TINPLx

4

UNIT

3

TOUTLx

Figure 6-52. Timer Timing

174






TMS320DM647



6.22 VLYNQ Peripheral

6.22.1 VLYNQ Device-Specific Information

The VLYNQ peripheral conforms to the VLYNQ Module Specification (revision 2.x). By default, the VLYNQ peripheral is initialized with a device ID of 0x22.

6.22.2 VLYNQ Peripheral Register Descriptions


0x3800 0000

0x3800 0004

0x3800 0008

0x3800 000C

0x3800 0010

0x3800 0014

0x3800 0018

0x3800 001C

0x3800 0020

0x3800 0024

0x3800 0028

0x3800 002C

0x3800 0030

0x3800 0034

0x3800 0038

0x3800 003C

0x3800 0040

0x3800 0044

0x3800 0048

0x3800 004C

0x3800 0050 - 0x3800 005C

0x3800 0060

0x3800 0064

0x3800 0068 - 0x3800 007C

0x3800 0080

0x3800 0084

0x3800 0088

0x3800 008C

0x3800 0090

0x3800 0094

0x3800 0098

0x3800 009C

0x3800 00A0

0x3800 00A4

0x3800 00A8

0x3800 00AC

0x3800 00B0

0x3800 00B4

0x3800 00B8

0x3800 00BC

Table 6-91. VLYNQ Registers

ACRONYM

-

CTRL

STAT

INTPRI

Reserved

VLYNQ Local Control Register

REGISTER NAME

VLYNQ Local Status Register

VLYNQ Local Interrupt Priority Vector Status/Clear Register

INTSTATCLR VLYNQ Local Interrupt Status/Clear Register

INTPENDSET VLYNQ Local Interrupt Pending/Set Register

INTPTR VLYNQ Local Interrupt Pointer Register

XAM

RAMS1

VLYNQ Local Transmit Address Map

VLYNQ Local Receive Address Map Size 1

RAMO1

RAMS2

RAMO2

RAMS3

RAMO3

RAMS4

RAMO4

CHIPVER

AUTNGO

MANNGO

VLYNQ Local Receive Address Map Offset 1







VLYNQ Local Chip Version Register

VLYNQ Local Auto Negotiation Register

VLYNQ Local Manual Negotiation Register

NGOSTAT

-

INTVEC0

INTVEC1

-

VLYNQ Local Negotiation Status Register

Reserved

VLYNQ Local Interrupt Vector 3 - 0

VLYNQ Local Interrupt Vector 7 - 4

Reserved for future use [Local Interrupt Vectors 8 - 31]

RREVID

RCTRL

RSTAT

VLYNQ Remote Revision Register

VLYNQ Remote Control Register

VLYNQ Remote Status Register

RINTPRI VLYNQ Remote Interrupt Priority Vector Status/Clear Register

RINTSTATCLR VLYNQ Remote Interrupt Status/Clear Register

RINTPENDSET VLYNQ Remote Interrupt Pending/Set Register

RINTPTR

RXAM

VLYNQ Remote Interrupt Pointer Register

VLYNQ Remote Transmit Address Map

RRAMS1

RRAMO1

VLYNQ Remote Receive Address Map Size 1

VLYNQ Remote Receive Address Map Offset 1

RRAMS2

RRAMO2

RRAMS3

RRAMO3

RRAMS4

RRAMO4












175

TMS320DM647

TMS320DM648



0x3800 00C0

0x3800 00C4

0x3800 00C8

0x3800 00CC

0x3800 00D0 - 0x3800 00DC

0x3800 00E0

0x3800 00E4

0x3800 00E8 - 0x3800 00FC

Table 6-91. VLYNQ Registers (continued)

ACRONYM

RCHIPVER

RAUTNGO

RMANNGO

RNGOSTAT

-

RINTVEC0

RINTVEC1

-

REGISTER NAME

VLYNQ Remote Chip Version Register

VLYNQ Remote Auto Negotiation Register

VLYNQ Remote Manual Negotiation Register

VLYNQ Remote Negotiation Status Register

Reserved

VLYNQ Remote Interrupt Vector 3 - 0

VYLNQ Remote Interrupt Vector 7 - 4

Reserved for future use [Remote Interrupt Vectors 8 - 31]

6.22.3 VLYNQ Electrical Data/Timing

www.ti.com

NO.

1

2

3

4 t c(VCLK) t w(VCLKH) t w(VCLKL) t t(VCLK)

Table 6-92. Timing Requirements for VCLK for VLYNQ (see

Figure 6-53

)

Cycle time, VCLK

Pulse duration, VCLK high, VCLK Input

Pulse duration, VCLK high, VCLK Output

Pulse duration, VCLK low, VCLK Input

Pulse duration, VCLK low, VCLK Output

Transition time, VCLK

720, 800, 900, 1100

MIN MAX

8

2

3

2

3

UNIT

ns ns ns ns ns ns

1

4

2

VCLK

4

3

Figure 6-53. VCLK Timing for VLYNQ

176






TMS320DM647



Table 6-93. Switching Characteristics

Over Recommended Operating Conditions for Transmit Data for the VLYNQ Module (see

Figure 6-54

)

NO.

1

1

2 t d(VCLKH-TXDI) t d(VCLKH-TXDI) t d(VCLKH-TXDV)

PARAMETER

Delay time, VCLK high to VTXD[3:0] invalid [SLOW Mode]

Delay time, VCLK high to VTXD[3:0] invalid [FAST Mode]

Delay time, VCLK to VTXD[3:0] valid

720, 800, 900, 1100

MIN MAX

2.25

0.86

6.85

UNIT

ns ns ns

NO.

3

4

Table 6-94. Timing Requirements for Receive Data for the VLYNQ Module (see

Figure 6-54 )

t su(RXDV-VCLKH) t h(VCLKH-RXDV)

Setup time, VRXD[3:0] valid before VCLK high

RTM disabled

RTM enabled, RXD Flop = 0








RTM disabled




Hold time, VRXD[3:0] valid after VCLK high RTM enabled, RXD Flop = 3





720, 800, 900, 1100

MIN MAX

0.2

1.25

0.91

0.64

0.36

0.09

-0.18

-0.44

-0.69

2

0.95

1.33

1.72

2.15

2.58

3.03

3.46

3.89

UNIT

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

1

VCLK

2

VTXD[3:0]

VRXD[3:0]

Data

3

4

Data

Figure 6-54. VLYNQ Transmit/Receive Timing






177

TMS320DM647

TMS320DM648


www.ti.com

6.23 General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.

When configured as an output, a write to an internal register can control the state driven on the output pin.

When configured as an input, the state of the input is detectable by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.

The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).

The GPIO peripheral supports the following:

• Up to 3.3-V GPIO pins

• Interrupts:

– Up to 16 unique GPIO[0:15] interrupts from Bank 0

– One GPIO bank (aggregated) interrupt signal from the GPIOs in Bank 1

– Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO signal

• DMA events:

– Up to 10 unique GPIO DMA events from Bank 0

• Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to anther process during GPIO programming).

• Separate Input/Output registers

• Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can be toggled by direct write to the output register(s).

• Output register, when read, reflects output drive status. This, in addition to the input register reflecting pin status and open-drain I/O cell, allows wired logic be implemented.

The memory map for the GPIO registers is shown in

Table 6-95

.

For more detailed information on GPIOs, see the TMS320DM647/DM648 DSP General-Purpose

Input/Output (GPIO) User's Guide (literature number SPRUEK7 ).

6.23.1 GPIO Peripheral Register Descriptions


0x0204 8000

0x0204 8004

0x0204 8008

0x0204 800C

0x0204 8010

0x0204 8014

0x0204 8018

0x0204 801C

0x0204 8020

0x0204 8024

0x0204 8028

0x0204 802C

0x0204 8030

0x0204 8034

Table 6-95. GPIO Registers

ACRONYM

PID

-

BINTEN

REGISTER NAME


Reserved

GPIO interrupt per-bank enable

GPIO Banks 0 and 1

Reserved -

DIR

OUT_DATA

SET_DATA

CLR_DATA

IN_DATA

GPIO Banks 0 and 1 Direction Register (GPIO[0:31])

GPIO Banks 0 and 1 Output Data Register (GPIO[0:31])

GPIO Banks 0 and 1 Set Data Register (GPIO[0:31])

GPIO Banks 0 and 1 Clear data for banks 0 and 1 (GPIO[0:31])

GPIO Banks 0 and 1 Input Data Register (GPIO[0:31])

SET_RIS_TRIG GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (GPIO[0:31])

CLR_RIS_TRIG GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (GPIO[0:31])

SET_FAL_TRIG GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (GPIO[0:31])

CLR_FAL_TRIG GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (GPIO[0:31])

INSTAT GPIO Banks 0 and 1 Interrupt Status Register (GPIO[0:31])

178






TMS320DM647


6.23.2 GPIO Peripheral Input/Output Electrical Data/Timing


Table 6-96. Timing Requirements for GPIO Inputs

(1)

(see

Figure 6-55 )

NO.

720, 800, 900,

1100

UNIT

1

2 t w(GPIH) t w(GPIL)

Pulse duration, GPIx high

Pulse duration, GPIx low

MIN MAX

12P

12P

(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device enough time to access the GPIO register through the internal bus. P = 1/CPU clock frequency in ns.

ns ns

Table 6-97. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs

(see

Figure 6-55 )

NO.

3

4 t w(GPOH) t w(GPOL)

PARAMETER

Pulse duration, GPOx high

Pulse duration, GPOx low

720, 800, 900, 1100

MIN

6P

6P

(1)

(1)

MAX

UNIT

ns ns

(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the

GPIO is dependent upon internal bus activity. P = 1/CPU clock frequency in ns.

2

1

GPIx

4

3

GPOx

Figure 6-55. GPIO Port Timing






179

TMS320DM647

TMS320DM648


www.ti.com

6.24 Emulation Features and Capability

6.24.1 Advanced Event Triggering (AET)

The device supports Advanced Event Triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications. AET provides the following capabilities:

• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture.

• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate events such as halting the processor or triggering the trace capture.

• Counters: count the occurrence of an event or cycles for performance monitoring.

• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences.

For more information on AET, see the following documents:

•

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs Application Report

(literature number SPRA753 )

•

Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded

Microprocessor Systems Application Report (literature number SPRA387 )

6.24.2 Trace

The device supports Trace. Trace is a debug technology that provides a detailed, historical account of application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information for analysis. Trace works in real-time and does not impact the execution of the system.

For more information on board design guidelines for Trace Advanced Emulation, see the Emulation and

Trace Headers Technical Reference Manual (literature number SPRU655 ).

180






TMS320DM647



6.25 IEEE 1149.1 JTAG

The JTAG

(2) interface is used for BSDL testing and emulation of the device.

TRST needs to be released only when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by

TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.

For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to make certain that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

6.25.1 JTAG Peripheral Register Description(s) - JTAG ID Register

Table 6-98. JTAG ID Register


0x0204 9018

ACRONYM

JTAGID

REGISTER NAME

JTAG Identification Register

COMMENTS

Read-only. Provides 32-bit

JTAG ID of the device.

(2) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. The JTAG

ID register resides at address location 0x0204 9018. The register hex value is: 0x0B77 A02F . For the actual register bit names and their associated bit field descriptions, see

Figure 6-56

and

Table 6-99 .

Figure 6-56. JTAGID Register (0x0204 9018)

31-28

VERSION

27-12

PART NUMBER (16-Bit)

R-0001 R-1011 0111 0111 1010

LEGEND: R = Read, W = Write, n = value at reset

11-1

MANUFACTURER (11-Bit)

R-0000 0010 111

0

LSB

R-1

BIT

31:28

27:12

11-1

0

Table 6-99. JTAGID Register Selection Bit Descriptions

NAME

VERSION

PART NUMBER

Silicon version value: 0001.

DESCRIPTION

Part Number (16-Bit) value: 1011 0111 0111 1010.

MANUFACTURER Manufacturer (11-Bit) value: 0000 0010 111.

LSB LSB. This bit is read as a 1.

6.25.2 JTAG Electrical Data/Timing

NO.

1

3

4 t c(TCK) t su(TDIV-TCKH) t h(TCKH-TDIV)

Table 6-100. Timing Requirements for JTAG Test Port (see

Figure 6-57 )

Cycle time, TCK

Setup time, TDI/TMS/TRST valid before TCK high

Hold time, TDI/TMS/TRST valid after TCK high

720, 800, 900, 1100

MIN MAX

35

2

0

UNIT

ns ns ns






181

TMS320DM647

TMS320DM648


www.ti.com

Table 6-101. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port

(see

Figure 6-57 )

NO.

2 t d(TCKL-TDOV)

PARAMETER

Delay time, TCK low to TDO valid

720, 800, 900, 1100

MIN MAX

0 0.25 × t c(TCK)

UNIT

ns

1

TCK

2

2

TDO

4

3

TDI/TMS/TRST

Figure 6-57. JTAG Test-Port Timing

182






TMS320DM647



7 Mechanical Data

The following table(s) show the thermal resistance characteristics for the ZUT mechanical package.

7.1

Thermal Data for ZUT

Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZUT]

R Θ

R Θ

R

ψ

ψ i

Θ

JT

JC

JB

JA

JB

R

R

R

ψ

ψ

Θ

Θ

Θ

JC Junction-to-case

JB Junction-to-board

JA Junction-to-free air

JT Junction-to-package top

JB Junction-to-board

°C/W

(1)

1.7

8.6

17.2

13.7

12.4

11.5

0.6

0.6

0.6

0.7

8.4

7.4

7.0

6.7

AIR FLOW (m/s)

N/A

N/A

0.0

1.0

2.0

3.0

0.0

1.0

2.0

3.0

0.0

1.0

2.0

3.0

(2)

(1) The junction-to-case measurement was conducted in a JEDEC defined 1S0P system. Other measurements were conducted in a JEDEC defined 1S2P system and will change based on environment as well as application.

For more information, see these three EIA/JEDEC standards:

• EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)

• EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) m/s = meters per second





Mechanical Data

183

TMS320DM647

TMS320DM648


www.ti.com

7.2

Packaging Information

The following packaging information and addendum reflects the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document.

184

Mechanical Data





PACKAGE OPTION ADDENDUM

www.ti.com

12-Mar-2016

PACKAGING INFORMATION

Orderable Device

TMS320DM647CUT7

Status

(1)

PREVIEW

Package Type Package

Drawing

Pins Package

Qty

FCBGA CUT 529 84

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

TMS320DM647CUT9 PREVIEW FCBGA CUT 529 84 Green (RoHS

& no Sb/Br)

TMS320DM647CUTA6

TMS320DM647CUTA8

TMS320DM647CUTD1

NRND

PREVIEW

LIFEBUY

FCBGA

FCBGA

FCBGA

CUT

CUT

CUT

529

529

529

84

TBD

TBD

TBD

Lead/Ball Finish

(6)

SNAGCU

SNAGCU

Call TI

Call TI

Call TI

MSL Peak Temp

(3)

Level-4-245C-72HR

Op Temp (°C)

0 to 90

Level-4-245C-72HR

Call TI

Call TI

Call TI

0 to 90

-40 to 105

-40 to 90

TMS320DM647CUTD7 PREVIEW FCBGA

TMS320DM647CUTD9

TMS320DM647ZUT1 OBSOLETE FCBGA

TMS320DM647ZUT7

TMS320DM647ZUT9

TMS320DM647ZUTA8 OBSOLETE FCBGA

TMS320DM647ZUTD7

NRND

NRND

NRND

NRND

FCBGA

FCBGA

FCBGA

FCBGA

TMS320DM648CUT1 OBSOLETE FCBGA

CUT 529 84

CUT

ZUT

529

529

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TBD

ZUT 529

ZUT 529

ZUT 529

84 Pb-Free (RoHS

Exempt)

84 Pb-Free (RoHS

Exempt)

TBD

ZUT 529

CUT 529

84 Pb-Free (RoHS

Exempt)

TBD

SNAGCU

SNAGCU

Call TI

SNAGCU

SNAGCU

Call TI

SNAGCU

Call TI

Level-4-245C-72HR -40 to 90

Level-4-245C-72HR -40 to 90

Call TI

Level-4-245C-72HR 0 to 90

Level-4-245C-72HR 0 to 90

Call TI

Level-4-245C-72HR -40 to 90

Call TI

0 to 90

-40 to 105

0 to 90

Device Marking

(4/5)

TMS320DM647CUT

@2007 TI

720MHZ

TMS320DM647CUT

@2007 TI

900MHZ

TMS320DM647CUT

@2007 TI

D1.1GHZ

TMS320DM647CUT

@2007 TI

D720MHZ

TMS320DM647CUT

@2007 TI

D900MHZ

TMS320DM647ZUT

@2007 TI

1.1GHZ

TMS320DM647ZUT

@2007 TI

720MHZ

TMS320DM647ZUT

@2007 TI

900MHZ

TMS320DM647ZUT

@2007 TI

A800MHZ

TMS320DM647ZUT

@2007 TI

D720MHZ

TMS320DM648CUT

@2007 TI

1.1GHZ

Addendum-Page 1

Samples


www.ti.com

12-Mar-2016


TMS320DM648CUT7

TMS320DM648CUT9

TMS320DM648CUTA6

TMS320DM648CUTA8

TMS320DM648CUTD1

Status

(1)

NRND


Drawing

Pins Package

Qty

FCBGA CUT 529 84

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

ACTIVE FCBGA CUT 529 84

NRND FCBGA CUT 529

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

NRND FCBGA CUT 529 84 Green (RoHS

& no Sb/Br)

OBSOLETE FCBGA CUT 529 TBD


(6)

SNAGCU

SNAGCU

SNAGCU

SNAGCU

Call TI

MSL Peak Temp

(3)

Level-4-245C-72HR

Op Temp (°C)

0 to 90

Level-4-245C-72HR

Level-4-245C-72HR -40 to 105

Level-4-245C-72HR -40 to 105

Call TI

0 to 90

-40 to 90

TMS320DM648CUTD7

TMS320DM648CUTD9

TMS320DM648ZUT1

TMS320DM648ZUT7

TMS320DM648ZUT9

TMS320DM648ZUTA6

TMS320DM648ZUTA8

TMS320DM648ZUTD1

NRND

NRND

OBSOLETE

NRND

NRND

NRND

NRND

OBSOLETE

FCBGA

FCBGA

FCBGA

FCBGA

FCBGA

FCBGA

FCBGA

FCBGA

CUT

CUT

ZUT

ZUT

ZUT

ZUT

ZUT

ZUT

529

529

529

529

529

529

529

529

84 Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Pb-Free (RoHS

Exempt)

84 Pb-Free (RoHS

Exempt)

84 Pb-Free (RoHS

Exempt)

84 Pb-Free (RoHS

Exempt)

84 Pb-Free (RoHS

Exempt)

TBD

SNAGCU

SNAGCU

SNAGCU

SNAGCU

SNAGCU

SNAGCU

SNAGCU

Call TI

Level-4-245C-72HR

Level-4-245C-72HR

Level-4-245C-72HR

Level-4-245C-72HR

Level-4-245C-72HR

Level-4-245C-72HR

Level-4-245C-72HR

Call TI

-40 to 90

-40 to 90

0 to 90

0 to 90

0 to 90

-40 to 105

-40 to 105

-40 to 90

Device Marking

(4/5)

TMS320DM648CUT

@2007 TI

720MHZ

TMS320DM648CUT

@2007 TI

900MHZ

TMS320DM648CUT

@2007 TI

A600MHZ

TMS320DM648CUT

@2007 TI

A800MHZ

TMS320DM648CUT

@2007 TI

D1.1GHZ

TMS320DM648CUT

@2007 TI

D720MHZ

TMS320DM648CUT

@2007 TI

D900MHZ

TMS320DM648ZUT

@2007 TI

1.1GHZ

TMS320DM648ZUT

@2007 TI

720MHZ

TMS320DM648ZUT

@2007 TI

900MHZ

TMS320DM648ZUT

@2007 TI

A600MHZ

TMS320DM648ZUT

@2007 TI

A800MHZ

TMS320DM648ZUT

@2007 TI

Addendum-Page 2

Samples


www.ti.com

12-Mar-2016


TMS320DM648ZUTD7

TMS320DM648ZUTD9

TNETV2685FIBZUT11

TNETV2685FIBZUTA11

Status

(1)

NRND


Drawing

FCBGA ZUT

Pins Package

Qty

529

Eco Plan

(2)

84 Pb-Free (RoHS

Exempt)


(6)

SNAGCU

NRND FCBGA ZUT 529 SNAGCU

OBSOLETE FCBGA ZUT 529

84 Pb-Free (RoHS

Exempt)

Pb-Free (RoHS

Exempt)

SNAGCU

OBSOLETE FCBGA ZUT 529 TBD Call TI

MSL Peak Temp

(3)

Op Temp (°C)

Level-4-245C-72HR -40 to 90

Level-4-245C-72HR

Level-4-245C-72HR

Call TI

-40 to 90

0 to 90

-40 to 90

TNETV2685FIDZUT11

TNETV2685FIDZUTA11

TNETV2685VIDZUT11

TNETV2685VIDZUTA11

TNETV2685ZUT11

TNETV2685ZUTA11

OBSOLETE

OBSOLETE

OBSOLETE

OBSOLETE

OBSOLETE

OBSOLETE

FCBGA

FCBGA

FCBGA

FCBGA

FCBGA

FCBGA

ZUT

ZUT

ZUT

ZUT

ZUT

ZUT

529

529

529

529

529

529

Pb-Free (RoHS

Exempt)

TBD

Pb-Free (RoHS

Exempt)

TBD

Pb-Free (RoHS

Exempt)

TBD

SNAGCU

Call TI

SNAGCU

Call TI

SNAGCU

Call TI

Level-4-245C-72HR

Call TI

Level-4-245C-72HR

Call TI

Level-4-245C-72HR

Call TI

0 to 90

-40 to 90

0 to 90

-40 to 90

0 to 90

-40 to 90

Device Marking

(4/5)

D1.1GHZ

TMS320DM648ZUT

@2007 TI

D720MHZ

TMS320DM648ZUT

@2007 TI

D900MHZ

TMS320DM648ZUT

@2007 TI

1.1GHZ

TMS320DM648ZUT

@2007 TI

D1.1GHZ

TMS320DM648ZUT

@2007 TI

1.1GHZ

TMS320DM648ZUT

@2007 TI

D1.1GHZ

TMS320DM648ZUT

@2007 TI

1.1GHZ

TMS320DM648ZUT

@2007 TI

D1.1GHZ

TMS320DM648ZUT

@2007 TI

1.1GHZ

TMS320DM648ZUT

@2007 TI

D1.1GHZ

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 3

Samples


www.ti.com

12-Mar-2016

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 4

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Audio

Amplifiers

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

Logic

Power Mgmt

Microcontrollers

RFID

OMAP Applications Processors

Wireless Connectivity www.ti.com/audio amplifier.ti.com

dataconverter.ti.com

www.dlp.com

dsp.ti.com

www.ti.com/clocks interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

Applications

Automotive and Transportation

Communications and Telecom

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

Medical

Security

Space, Avionics and Defense

Video and Imaging www.ti-rfid.com

www.ti.com/omap

TI E2E Community

www.ti.com/wirelessconnectivity www.ti.com/automotive www.ti.com/communications www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/video e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2016, Texas Instruments Incorporated