STM32L4 Peripheral USB

STM32L4 Peripheral USB
Hello, and welcome to this presentation of the
STM32L4’s USB interface. It covers the features of this
IP, which is widely used to connect either a PC or a USB
device to the microcontroller.
This figure shows the connections between an STM32L4
microcontroller and a USB connector.
The STM32L4 features a Full-speed USB
communication interface, allowing the microcontroller to
communicate typically with a PC or a USB storage
device. The simplest implementation is a USB peripheral
device but the STM32L4 also supports USB “On-TheGo” functions.
The USB implementation includes low-power features
allowing the use of a low-speed crystal oscillator, OnThe-Go host or device functions, and quicker battery
This slide summarizes the key features of this full-speed
USB interface, which is a USB specification 2.0
compliant interface operating at a 12 Megabits per
second bit rate.
In the simplest form, a full-speed USB device can be
Its built-in support for Link Power Management adds
enhanced power modes on top of the USB 2.0
In addition, the On-The-Go or “OTG” function enables
the implementation of an OTG product or an embedded
host, both of which have the capacity to behave as a
targeted host.
The battery charger detection feature allows for
increased current to be drawn from BC1.2 compliant
chargers up to 1.5 A.
In this block diagram, the OTG Full-speed USB controller
core is shown in the center with its data FIFOs below. On
its right side, the physical layer handles the analog signal
levels including the detection of many specific levels
relating to the On-The-Go and Battery Charger Detection
functions. The USB interrupt is connected to the Cortex
processor to signal various USB events. The AHB
peripheral bus enables read and write access of the
controller registers as well as the Power and Clock
control block.
Depending on the use case (i.e. either device only or as
an OTG device), a low-or high-speed crystal oscillator is
necessary to provide an accurate timing reference for the
USB block.
At any given time, one of the two operating modes will be
in operation:
Peripheral mode, used for a regular device or an OTG
Targeted host mode, used for an embedded host or an
OTG device.
A large number of events or state changes are able to
generate interrupts from this USB block.
This slide and the following three slides show all the
events that can generate an interrupt. As can be seen,
these interrupt sources are diverse; they range from
events related to low-power management and OTG, to
events related to normal host behavior and regular USB
reset and disconnect events.
Note in slide: Reset detected: In Device mode, this
interrupt is asserted when a reset is detected on the USB
in partial power-down mode when the device is in
Suspend mode.
In this second slide showing interrupts, another diverse
set of sources is described.
In this third slide describing interrupt sources, many
SUSPEND, OTG functions and FIFO status events are
listed as well as a general register access error.
In this final slide describing interrupt sources, the three
interrupts relating to the OTG feature “Attach detection
protocol” are listed.
Now let us take a brief look at the various low-power
modes of the physical layer and the controller.
For the physical layer, Power-down mode can be used,
for example, when there is no VBUS present and the
current session is identified as not OTG; it is also
possible to disable VBUS sensing related to OTG (Aand B- sessions) if the OTG function is not used.
During Suspend mode, there is no dynamic signaling
occurring over the USB interface, so three different
controls are offered to lower the power consumption as
desired by the application.
Within the USB module, dedicated bits are implemented
to provide some debug functions for USB applications.
They relate to FIFO status and contents, the ADP aspect
of OTG and the scheduling of periodic queues in Host
Additional details of these debug bits are listed in this
Here is an application example of a low-power device.
Power is drawn directly from the USB VBUS signal.
A single low-speed crystal oscillator at 32.768 kHz is
needed outside. A scheme is implemented inside the
microcontroller using this low-speed crystal oscillator to
trim the internal 48 MHz oscillator, thus giving the
required frequency accuracy to comply with the USB
For complete USB specification documents, please refer
The USB2.0 document home page has a ZIP file
containing the USB2.0 and OTG2.0 specifications and
an ECN for LPM
The USB device class documents page has the battery
charger specification.
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