DC and Switching Characteristics

DC and Switching Characteristics
4. DC and Switching
Characteristics
SIIGX51006-4.6
Operating
Conditions
Stratix® II GX devices are offered in both commercial and industrial
grades. Industrial devices are offered in -4 speed grade and commercial
devices are offered in -3 (fastest), -4, and -5 speed grades.
Tables 4–1 through 4–51 provide information on absolute maximum
ratings, recommended operating conditions, DC electrical characteristics,
and other specifications for Stratix II GX devices.
Absolute Maximum Ratings
Table 4–1 contains the absolute maximum ratings for the Stratix II GX
device family.
Table 4–1. Stratix II GX Device Absolute Maximum Ratings
Symbol
Parameter
Notes (1), (2),(3)
Conditions
Minimum
Maximum
Unit
VCCINT
Supply voltage
With respect to ground
–0.5
1.8
V
VCCIO
Supply voltage
With respect to ground
–0.5
4.6
V
VCCPD
Supply voltage
With respect to ground
–0.5
4.6
V
VI
DC input voltage (4)
–0.5
4.6
V
IOUT
DC output current, per pin
–25
40
mA
TSTG
Storage temperature
No bias
–65
150
C
TJ
Junction temperature
BGA packages under bias
–55
125
C
Notes to Table 4–1:
(1)
(2)
(3)
(4)
See the Operating Requirements for Altera Devices Data Sheet for more information.
Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle.
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
Altera Corporation
June 2009
4–1
Operating Conditions
Table 4–2. Maximum Duty Cycles in Voltage Transitions
Symbol
Parameter
Condition
Maximum Duty Cycles
(%) (1)
VI
Maximum duty cycles
in voltage transitions
VI = 4.0 V
100
VI = 4.1 V
90
VI = 4.2 V
50
VI = 4.3 V
30
VI = 4.4 V
17
VI = 4.5 V
10
Note to Table 4–2:
(1)
During transition, the inputs may overshoot to the voltages shown based on the
input duty cycle. The duty cycle case is equivalent to 100% duty cycle.
Recommended Operating Conditions
Table 4–3 contains the Stratix II GX device family recommended
operating conditions.
Table 4–3. Stratix II GX Device Recommended Operating Conditions (Part 1 of 2)
Symbol
Parameter
Conditions
Note (1)
Minimum
Maximum
Unit
1.15
1.25
V
100 μs ≤rise time ≤100 ms (3), (6)
3.135
(3.00)
3.465
(3.60)
V
Supply voltage for output
buffers, 2.5-V operation
100 μs ≤rise time ≤100 ms (3)
2.375
2.625
V
Supply voltage for output
buffers, 1.8-V operation
100 μs ≤rise time ≤100 ms (3)
1.71
1.89
V
Supply voltage for output
buffers, 1.5-V operation
100 μs ≤rise time ≤100 ms (3)
1.425
1.575
V
Supply voltage for output
buffers, 1.2-V operation
100 μs ≤rise time ≤100 ms (3)
1.15
1.25
V
VCCPD
Supply voltage for pre-drivers as 100 μs ≤rise time ≤100 ms (4)
well as configuration and JTAG
I/O buffers.
3.135
3.465
V
VI
Input voltage (see Table 4–2)
–0.5
4.0
V
VO
Output voltage
0
VCCIO
V
VCCINT
Supply voltage for internal logic
and input buffers
100 μs ≤rise time ≤100 ms (3)
VCCIO
Supply voltage for output
buffers, 3.3-V operation
4–2
Stratix II GX Device Handbook, Volume 1
(2), (5)
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–3. Stratix II GX Device Recommended Operating Conditions (Part 2 of 2)
Symbol
TJ
Parameter
Operating junction temperature
Conditions
Minimum
Maximum
Unit
0
85
C
–40
100
C
For commercial use
For industrial use
Note (1)
Notes to Table 4–3:
(1)
(2)
(3)
(4)
(5)
(6)
Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle.
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
Maximum VCC rise time is 100 ms, and VCC must rise monotonically from ground to VCC.
VCCPD must ramp-up from 0 V to 3.3 V within 100 μs to 100 ms. If VCCPD is not ramped up within this specified
time, the Stratix II GX device will not configure successfully. If the system does not allow for a VCCPD ramp-up time
of 100 ms or less, hold nCONFIG low until all power supplies are reliable.
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT, VCCPD, and VCCIO
are powered.
VCCIO maximum and minimum conditions for PCI and PCI-X are shown in parentheses.
Transceiver Block Characteristics
Tables 4–4 through 4–6 contain transceiver block specifications.
Table 4–4. Stratix II GX Transceiver Block Absolute Maximum Ratings
Symbol
Parameter
Conditions
Note (1)
Minimum Maximum
Units
VCCA
Transceiver block supply
voltage
Commercial and
industrial
–0.5
4.6
V
VCCP
Transceiver block supply
voltage
Commercial and
industrial
–0.5
1.8
V
VCCR
Transceiver block supply
Voltage
Commercial and
industrial
–0.5
1.8
V
VCCT
Transceiver block supply
voltage
Commercial and
industrial
–0.5
1.8
V
VCCT_B
Transceiver block supply
voltage
Commercial and
industrial
–0.5
1.8
V
VCCL
Transceiver block supply
voltage
Commercial and
industrial
–0.5
1.8
V
VCCH_B
Transceiver block supply
voltage
Commercial and
industrial
–0.5
2.4
V
Note to Table 4–4:
(1)
The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is
not violated.
Altera Corporation
June 2009
4–3
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–5. Stratix II GX Transceiver Block Operating Conditions
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCA
Transceiver block supply
voltage
Commercial
and industrial
3.135
3.3
3.465
V
VCCP
Transceiver block supply
voltage
Commercial
and industrial
1.15
1.2
1.25
V
VCCR
Transceiver block supply
voltage
Commercial
and industrial
1.15
1.2
1.25
V
VCCT
Transceiver block supply
voltage
Commercial
and industrial
1.15
1.2
1.25
V
VCCT_B
Transceiver block supply
voltage
Commercial
and industrial
1.15
1.2
1.25
V
VCCL
Transceiver block supply
voltage
Commercial
and industrial
1.15
1.2
1.25
V
VCCH_B (2)
Transceiver block supply
voltage
Commercial
and industrial
1.15
1.2
1.25
V
RREF (1)
Reference resistor
Commercial
and industrial
1.425
1.5
1.575
V
2000 –1%
2000
2000 +1%
Ω
Notes to Table 4–5:
(1)
(2)
The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin.
Refer to the Stratix II GX Device Handbook, volume 2, for more information.
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 1 of 6)
Symbol /
Description
Conditions
-3 Speed Commercial
Speed Grade
-4 Speed Commercial
and Industrial Speed
Grade
-5 Speed Commercial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Input
frequency from
REFCLK input
50
-
622.08
50
-
622.08
50
-
622.08
MHz
Input
frequency from
PLD input
50
-
325
50
-
325
50
-
325
MHz
3.3
V
Reference clock
Input clock
jitter
Absolute VM A X
for a REFCLK
pin (12)
Refer to Table 4–20 on page 4–36 for the input jitter specifications for the
reference clock.
-
4–4
Stratix II GX Device Handbook, Volume 1
-
3.3
-
-
3.3
-
-
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 2 of 6)
Symbol /
Description
Conditions
-3 Speed Commercial
Speed Grade
-4 Speed Commercial
and Industrial Speed
Grade
-5 Speed Commercial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
-0.3
-
-
-0.3
-
-
-0.3
-
-
V
-
0.2
-
-
0.2
-
-
0.2
-
UI
Duty cycle
40
-
60
40
-
60
40
-
60
%
Peak-to-peak
differential
input voltage
200
-
2000
200
-
2000
200
-
2000
mV
30
0 to
-0.5%
-
33
0 to
-0.5%
30
0 to
-0.5%
-
33
0 to
-0.5%
30
0 to
-0.5%
-
33
0 to
-0.5%
kHz
Absolute VM I N
for a REFCLK
pin (12)
Rise/fall time
Spreadspectrum
clocking
On-chip
termination
resistors
115 ±20%
115 ±20%
115 ±20%
Ω
VI C M (AC
coupled) (12)
1200 ±5%
1200 ±5%
1200 ±5%
mV
VI C M (DC
coupled) (4)
0.25
Rref
-
0.55
0.25
2000 ±1%
-
0.55
0.25
2000 ±1%
-
0.55
V
Ω
2000 ±1%
Transceiver Clocks
Calibration
block clock
frequency
10
-
125
10
-
125
10
-
125
MHz
Calibration
block minimum
power-down
pulse width
30
-
-
30
-
-
30
-
-
ns
Time taken for
one-time
calibration
-
-
8
-
-
8
-
-
8
ms
PCI Express
Receiver
Detect
-
125
-
-
125
-
-
125
-
MHz
Adaptive
Equalization
(AEQ)
2.5
-
125
2.5
-
125
-
-
-
MHz
fixedclk
clock
frequency
Altera Corporation
June 2009
4–5
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 3 of 6)
Symbol /
Description
Conditions
reconfig_c
lk clock
-3 Speed Commercial
Speed Grade
-4 Speed Commercial
and Industrial Speed
Grade
-5 Speed Commercial
Speed Grade
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
2.5
-
50
2.5
-
50
2.5
-
50
100
-
-
100
-
-
100
-
-
Unit
MHz
frequency
Transceiver
block minimum
power-down
pulse width
ns
Receiver
Data rate
600
-
6375
600
-
5000
600
-
4250
Mbps
Absolute VM A X
for a receiver
pin (1)
-
-
2.0
-
-
2.0
-
-
2.0
V
Absolute VM I N
for a receiver
pin
-0.4
-
-
-0.4
-
-
-0.4
-
-
V
Maximum
peak-to-peak
differential
input voltage
VI D (diff p-p)
VC M = 0.85 V
-
-
3.3
-
-
3.3
-
-
3.3
V
Minimum
peak-to-peak
differential
input voltage
VI D (diff p-p)
VC M = 0.85 V
DC Gain =
≥ 3 dB
160
-
-
160
-
-
160
-
-
mV
VI C M
VI C M = 0.85
V setting
850±10%
850±10%
850±10%
mV
VI C M = 1.2 V
setting (11)
1200±10%
1200±10%
1200±10%
mV
100 Ω setting
100±15%
100±15%
100±15%
Ω
120 Ω setting
120±15%
120±15%
120±15%
Ω
150 Ω setting
150±15%
150±15%
150±15%
Ω
On-chip
termination
resistors
Bandwidth at
6.375 Gbps
BW = Low
-
20
-
-
-
-
-
-
-
MHz
BW = Med
-
35
-
-
-
-
-
-
-
MHz
BW = High
-
45
-
-
-
-
-
-
-
MHz
4–6
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 4 of 6)
Symbol /
Description
Bandwidth at
3.125 Gbps
Bandwidth at
2.5 Gbps
Conditions
-3 Speed Commercial
Speed Grade
-4 Speed Commercial
and Industrial Speed
Grade
-5 Speed Commercial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
BW = Low
-
30
-
-
30
-
-
30
-
MHz
BW = Med
-
40
-
-
40
-
-
40
-
MHz
BW = High
-
50
-
-
50
-
-
50
-
MHz
BW = Low
-
35
-
-
35
-
-
35
-
MHz
BW = Med
-
50
-
-
50
-
-
50
-
MHz
BW = High
-
60
-
-
60
-
-
60
-
MHz
Return loss
differential
mode
100 MHz to 2.5 GHz (XAUI): -10 dB
50 MHz to 1.25 GHz (PCI-E): -10 dB
100 MHz to 4.875 GHz (OIF/CEI): -8dB
4.875 GHz to 10 GHz (OIF/CEI): 16.6 dB/decade slope
Return loss
common mode
100 MHz to 2.5 GHz (XAUI): -6 dB
50 MHz to 1.25 GHz (PCI-E): -6 dB
100 MHz to 4.875 GHz (OIF/CEI): -6dB
4.875 GHz to 10 GHz (OIF/CEI): 16.6 dB/decade slope
Programmable
PPM detector
(2)
±62.5, 100, 125, 200,
250, 300,
500, 1000
±62.5, 100, 125, 200,
250, 300,
500, 1000
±62.5, 100, 125, 200,
250, 300,
500, 1000
ppm
Run length (3),
(9)
80
80
80
UI
Programmable
equalization
-
-
16
-
-
16
-
-
16
dB
65
-
175
65
-
175
65
-
175
mV
CDR LTR TIme
(5), (9)
-
-
75
-
-
75
-
-
75
us
CDR Minimum
T1b (6), (9)
15
-
-
15
-
-
15
-
-
us
LTD lock time
(7), (9)
0
100
4000
0
100
4000
0
100
4000
ns
Data lock time
from
-
-
4
-
-
4
-
-
4
us
Signal
detect/loss
threshold (4)
rx_freqloc
ked (8), (9)
Programmable
DC gain
0, 3, 6
0, 3, 6
0, 3, 6
Transmitter
Altera Corporation
June 2009
4–7
Stratix II GX Device Handbook, Volume 1
dB
Operating Conditions
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 5 of 6)
Symbol /
Description
Conditions
Data rate
VO C M
On-chip
termination
resistors
-3 Speed Commercial
Speed Grade
-4 Speed Commercial
and Industrial Speed
Grade
-5 Speed Commercial
Speed Grade
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
600
-
6375
600
-
5000
600
-
4250
Unit
Mbps
VO C M = 0.6 V
setting
580±10%
580±10%
580±10%
mV
VO C M = 0.7 V
setting
680±10%
680±10%
680±10%
mV
100 Ω setting
108±10%
108±10%
108±10%
Ω
120 Ω setting
125±10%
125±10%
125±10%
Ω
150 Ω setting
152±10%
152±10%
152±10%
Ω
Return loss
differential
mode
312 MHz to 625 MHz (XAUI): -10 dB
625 MHz to 3.125 GHz (XAUI): -10 dB/decade slope
50 MHz to 1.25 GHz (PCI-E): -10dB
100 MHz to 4.875 GHz (OIF/CEI): -8db
4.875 GHz to 10 GHz (OIF/CEI): 16.6 dB/decade slope
Return loss
common mode
50 MHz to 1.25 GHz (PCI-E): -6dB
100 MHz to 4.875 GHz (OIF/CEI): -6db
4.875 GHz to 10 GHz (OIF/CEI): 16.6 dB/decade slope
Rise time
35
-
65
35
-
65
35
-
65
ps
Fall time
35
-
65
35
-
65
35
-
65
ps
-
-
15
-
-
15
-
-
15
ps
Intratransceiver
block skew (x4)
-
-
100
-
-
100
-
-
100
ps
Intertransceiver
block skew (x8)
-
-
300
-
-
300
-
-
300
ps
VCO
frequency
range (low
gear)
500
-
1562.5
500
-
1562.5
500
-
1562.5
MHz
VCO
frequency
range (high
gear)
1562.5
3187.5
1562.5
2500
1562.
5
-
2125
MHz
Intra
differential pair
skew
VOD =
800 mV
TXPLL (TXPLL0 and TXPLL1)
4–8
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 6 of 6)
Symbol /
Description
Bandwidth at
6.375 Gbps
Bandwidth at
3.125 Gbps
Bandwidth at
2.5 Gbps
Conditions
BW = Low
-3 Speed Commercial
Speed Grade
-4 Speed Commercial
and Industrial Speed
Grade
-5 Speed Commercial
Speed Grade
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
-
2
-
-
-
-
-
-
-
Unit
MHz
BW = Med
-
3
-
-
-
-
-
-
-
MHz
BW = High
-
7
-
-
-
-
-
-
-
MHz
BW = Low
-
3
-
-
3
-
-
3
-
MHz
BW = Med
-
5
-
-
5
-
-
5
-
MHz
BW = High
-
9
-
-
9
-
-
9
-
MHz
BW = Low
-
1
-
-
1
-
-
1
-
MHz
BW = Med
-
2
-
-
2
--
-
2
-
MHz
BW = High
-
4
-
-
4
-
-
4
-
MHz
-
-
100
-
-
100
-
-
100
us
25
-
250
25
-
250
25
-
200
MHz
TX PLL lock
time from
gxb_
powerdown
deassertion
(9), (10)
PLD-Transceiver Interface
Interface
speed
Digital Reset
Pulse Width
Minimum is 2 parallel clock cycles
Notes to Table 4–6:
(1)
(2)
(3)
(4)
(5)
(6)
The device cannot tolerate prolonged operation at this absolute maximum. Refer to Figure 4–5 for more information.
The rate matcher supports only up to +/-300 ppm.
This parameter is measured by embedding the run length data in a PRBS sequence.
This feature is only available in PCI-Express (PIPE) mode.
Time taken to rx_pll_locked goes high from rx_analogreset deassertion. Refer to Figure 4–1.
This is how long GXB needs to stay in LTR mode after rx_pll_locked is asserted and before rx_locktodata is
asserted in manual mode. Refer to Figure 4–1.
(7) Time taken to recover valid data from GXB after rx_locktodata signal is asserted in manual mode. Measurement
results are based on PRBS31, for native data rates only. Refer to Figure 4–1.
(8) Time taken to recover valid data from GXB after rx_freqlocked signal goes high in automatic mode. Measurement
results are based on PRBS31, for native data rates only. Refer to Figure 4–1.
(9) Please refer to the Protocol Characterization documents for lock times specific to the protocols.
(10) Time taken to lock TX PLL from gxb_powerdown deassertion.
(11) The 1.2 V RX VICM setting is intended for DC-coupled LVDS links.
(12) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Make sure that input
specifications are not violated during this period.
Altera Corporation
June 2009
4–9
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Figure 4–1 shows the lock time parameters in manual mode, Figure 4–2
shows the lock time parameters in automatic mode.
1
LTD = Lock to data
LTR = Lock to reference clock
Figure 4–1. Lock Time Parameters for Manual Mode
r x_analogreset
CDR status
LTR
LTD
r x_pll_locked
r x_locktodata
Invalid Data
Valid data
r x_dataout
CDR LTR Time
LTD lock time
CDR Minimum T1b
4–10
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Figure 4–2. Lock Time Parameters for Automatic Mode
LTR
CDR status
LTD
r x_freqlocked
Invalid
r x_dataout
Valid
data
data
Data lock time from rx_freqlocked
Figures 4–3 and 4–4 show differential receiver input and transmitter
output waveforms, respectively.
Figure 4–3. Receiver Input Waveform
Single-Ended Waveform
Positive Channel (p)
VID
Negative Channel (n)
VCM
Ground
Differential Waveform
VID (diff peak-peak) = 2 x VID (single-ended)
VID
p−n=0V
VID
Altera Corporation
June 2009
4–11
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Figure 4–4. Transmitter Output Waveform
Single-Ended Waveform
Positive Channel (p)
VOD
Negative Channel (n)
VCM
Ground
Differential Waveform
VOD (diff peak-peak) = 2 x VOD (single-ended)
VOD
p−n=0V
VOD
Figure 4–5. Maximum Receiver Input Pin Voltage
Single-Ended Waveform
Positive Channel (p)
V(single-ended p-p)max = 3.3 V/2
Negative Channel (n)
VCM = 0.85 V
Ground
VMAX = VCM + V(single-ended p-p)max = 0.85 + 0.825 = 1.675 V (1)
2
Note to Figure 4–5:
(1)
The absolute VMAX that the receiver input pins can tolerate is 2 V.
Tables 4–7 through 4–12 show the typical VOD for data rates from
600 Mbps to 6.375 Gbps. The specification is for measurement at the
package ball.
Table 4–7. Typical VOD Setting, TX Term = 100 Ω Note (1)
VC C H TX = 1.5 V
VOD Typical (mV)
VOD Setting (mV)
200
400
600
800
1000
1200
1400
220
430
625
830
1020
1200
1350
Note to Table 4–7:
(1)
Applicable to data rates from 600 Mbps to 6.375 Gbps. Specification is for measurement at the package ball.
4–12
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–8. Typical VOD Setting, TX Term = 120 Ω Note (1)
VC C H TX = 1.5 V
VOD Typical (mV)
VOD Setting (mV)
240
480
720
960
1200
260
510
750
975
1200
Note to Table 4–8:
(1)
Applicable to data rates from 600 Mbps to 6.375 Gbps. Specification is for
measurement at the package ball.
Table 4–9. Typical VOD Setting, TX Term = 150 Ω Note (1)
VC C H TX = 1.5 V
VOD Typical (mV)
VOD Setting (mV)
300
600
900
1200
325
625
920
1200
Note to Table 4–9:
(1)
Applicable to data rates from 600 Mbps to 6.375 Gbps. Specification is for
measurement at the package ball.
Table 4–10. Typical VOD Setting, TX Term = 100 Ω Note (1)
VC C H TX = 1.2 V
VOD Typical (mV)
VOD Setting (mV)
320
480
640
800
960
344
500
664
816
960
Note to Table 4–10:
(1)
Altera Corporation
June 2009
Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for
measurement at the package ball.
4–13
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–11. Typical VOD Setting, TX Term = 120 Ω Note (1)
VC C H TX = 1.2 V
VOD Setting (mV)
VOD Typical (mV)
192
384
576
768
960
210
410
600
780
960
Note to Table 4–11:
(1)
Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for
measurement at the package ball.
Table 4–12. Typical VOD Setting, TX Term = 150 Ω Note (1)
VC C H TX = 1.2 V
VOD Setting (mV)
VOD Typical (mV)
240
480
720
960
260
500
730
960
Note to Table 4–12:
(1)
Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for
measurement at the package ball.
Tables 4–13 through 4–18 show the typical first post-tap pre-emphasis.
Table 4–13. Typical Pre-Emphasis (First Post-Tap), Note (1) (Part 1 of 2)
VC C H TX
= 1.5 V
VOD
Setting
(mV)
First Post Tap Pre-Emphasis Level
1
2
3
4
5
6
7
8
9
457%
10
11
12
TX Term = 100 Ω
400
62%
112%
184%
600
24%
31%
56%
86%
800
20%
122%
168%
230%
329%
35%
53%
73%
96%
123%
156%
196%
237%
312%
387%
1000
23%
36%
49%
64%
79%
97%
118%
141%
165%
200%
1200
17%
25%
35%
45%
56%
68%
82%
95%
110%
125%
4–14
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–13. Typical Pre-Emphasis (First Post-Tap), Note (1) (Part 2 of 2)
VC C H TX
= 1.5 V
VOD
Setting
(mV)
First Post Tap Pre-Emphasis Level
1
2
3
1400
4
5
6
7
8
9
10
11
12
20%
26%
33%
41%
51%
58%
67%
77%
86%
Note to Table 4–13:
(1)
Applicable to data rates from 600 Mbps to 6.375 Gbps. Specification is for measurement at the package ball.
Table 4–14. Typical Pre-Emphasis (First Post-Tap), Note (1)
VC C H TX
= 1.5 V
VOD
Setting
(mV)
First Post Tap Pre-Emphasis Level
1
2
3
4
5
6
7
8
9
10
11
12
179%
226%
280%
405%
477%
TX Term = 120 Ω
240
45%
480
41%
76%
114%
166%
257%
355%
720
23%
38%
55%
84%
108%
137%
960
15%
1200
24%
36%
47%
64%
80%
97%
122%
140%
170%
196%
18%
22%
30%
41%
51%
63%
77%
86%
98%
116%
Note to Table 4–14:
(1)
Applicable to data rates from 600 Mbps to 6.375 Gbps. Specification is for measurement at the package ball.
Table 4–15. Typical Pre-Emphasis (First Post-Tap), Note (1) (Part 1 of 2)
VC C H TX
= 1.5 V
VOD
Setting
(mV)
First Post Tap Pre-Emphasis Level
1
2
3
4
5
6
7
8
9
10
11
12
TX Term = 150 Ω
300
32%
Altera Corporation
June 2009
85%
4–15
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–15. Typical Pre-Emphasis (First Post-Tap), Note (1) (Part 2 of 2)
VC C H TX
= 1.5 V
VOD
Setting
(mV)
First Post Tap Pre-Emphasis Level
1
2
3
4
5
6
7
8
9
600
33%
53%
80%
115%
157%
195%
294%
386%
900
19%
28%
38%
56%
70%
86%
113%
17%
22%
31%
40%
52%
62%
1200
10
11
12
133%
168%
196%
242%
75%
86%
96%
112%
Note to Table 4–15:
(1)
Applicable to data rates from 600 Mbps to 6.375 Gbps. Specification is for measurement at the package ball.
Table 4–16. Typical Pre-Emphasis (First Post-Tap), Note (1)
VC C H TX
= 1.2 V
VOD
Setting
(mV)
First Post Tap Pre-Emphasis Level
1
2
3
4
5
6
7
8
9
10
11
12
24%
61%
114%
480
31%
55%
86%
121%
170%
232%
333%
640
20%
35%
54%
72%
95%
124%
157%
195%
233%
307%
373%
800
23%
36%
49%
64%
960
18%
25%
35%
44%
81%
97%
117%
140%
161%
195%
57%
69%
82%
94%
108%
127%
TX Term = 100 Ω
320
Note to Table 4–16:
(1)
Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.
4–16
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–17. Typical Pre-Emphasis (First Post-Tap), Note (1)
VC C H TX
= 1.2 V
VOD
Setting
(mV)
First Post Tap Pre-Emphasis Level
1
2
3
4
5
6
7
8
9
10
11
12
TX Term = 120 Ω
192
45%
384
41%
76%
114%
166%
257%
355%
576
23%
38%
55%
84%
108%
137%
179%
226%
280%
405%
477%
768
15%
24%
36%
47%
64%
80%
97%
122%
140%
170%
196%
18%
22%
30%
41%
51%
63%
77%
86%
98%
116%
960
Note to Table 4–17:
(1)
Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.
Table 4–18. Typical Pre-Emphasis (First Post-Tap), Note (1)
VC C H TX
= 1.2 V
VOD
Setting
(mV)
First Post Tap Pre-Emphasis Level
1
2
31%
85%
3
4
5
6
7
8
9
10
11
12
TX Term = 150 Ω
240
480
32%
52%
78%
112%
152%
195%
275%
720
19%
28%
37%
56%
68%
86%
108%
133%
169%
194%
239%
17%
22%
30%
39%
51%
59%
75%
85%
94%
109%
960
Note to Table 4–18:
(1)
Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.
Altera Corporation
June 2009
4–17
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–19 shows the Stratix II GX transceiver block AC specifications.
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 1 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
-4 Speed
Commercial and
Industrial Speed
Grade
-5 Speed
Commercial Speed
Grade
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
SONET/SDH Transmit Jitter Generation (7)
Peak-to-peak jitter REFCLK =
at 622.08 Mbps
77.76 MHz
Pattern = PRBS23
VOD = 800 mV
No Pre-emphasis
-
-
0.1
-
-
0.1
-
-
0.1
UI
RMS jitter at
622.08 Mbps
REFCLK =
77.76 MHz
Pattern = PRBS23
VOD = 800 mV
No Pre-emphasis
-
-
0.01
-
-
0.01
-
-
0.01
UI
Peak-to-peak jitter REFCLK =
at 2488.32 Mbps
155.52 MHz
Pattern = PRBS23
VOD = 800 mV
No Pre-emphasis
-
-
0.1
-
-
0.1
-
-
0.1
UI
RMS jitter at
2488.32 Mbps
-
-
0.01
-
-
0.01
-
-
0.01
UI
REFCLK =
155.52 MHz
Pattern = PRBS23
VOD = 800 mV
No Pre-emphasis
4–18
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 2 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
SONET/SDH Receiver Jitter Tolerance (7)
Jitter tolerance at
622.08 Mbps
Jitter tolerance at
2488.32 MBps
Altera Corporation
June 2009
Jitter frequency =
0.03 KHz
Pattern = PRBS23
No Equalization
DC Gain = 0 dB
> 15
> 15
> 15
UI
Jitter frequency = 25
KHZ Pattern =
PRBS23
No Equalization
DC Gain = 0 dB
> 1.5
> 1.5
> 1.5
UI
Jitter frequency =
250 KHz Pattern =
PRBS23
No Equalization
DC Gain = 0 dB
> 0.15
> 0.15
> 0.15
UI
Jitter frequency =
0.06 KHz
Pattern = PRBS23
No Equalization
DC Gain = 0 dB
> 15
> 15
> 15
UI
Jitter frequency =
100 KHZ
Pattern = PRBS23
No Equalization
DC Gain = 0 dB
> 1.5
> 1.5
> 1.5
UI
Jitter frequency =
1 MHz
Pattern = PRBS23
No Equalization
DC Gain = 0 dB
> 0.15
> 0.15
> 0.15
UI
Jitter frequency = 10
MHz
Pattern = PRBS23
No Equalization
DC Gain = 0 dB
> 0.15
> 0.15
> 0.15
UI
4–19
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 3 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
-4 Speed
Commercial and
Industrial Speed
Grade
-5 Speed
Commercial Speed
Grade
Max
Min
Typ
Max
Min
Typ
Max
Unit
Fibre Channel Transmit Jitter Generation (8), (17)
Total jitter FC-1
REFCLK =
106.25 MHz
Pattern = CRPAT
VOD = 800 mV
No Pre-emphasis
-
-
0.23
-
-
0.23
-
-
0.23
UI
Deterministic jitter
FC-1
REFCLK =
106.25 MHz
Pattern = CRPAT
VOD = 800 mV
No Pre-emphasis
-
-
0.11
-
-
0.11
-
-
0.11
UI
Total jitter FC-2
REFCLK =
106.25 MHz
Pattern = CRPAT
VOD = 800 mV
No Pre-emphasis
-
-
0.33
-
-
0.33
-
-
0.33
UI
Deterministic jitter
FC-2
REFCLK =
106.25 MHz
Pattern = CRPAT
VOD = 800 mV
No Pre-emphasis
-
-
0.2
-
-
0.2
-
-
0.2
UI
Total jitter FC-4
REFCLK =
106.25 MHz
Pattern = CRPAT
VOD = 800 mV
No Pre-emphasis
-
-
0.52
-
-
0.52
-
-
0.52
UI
Deterministic jitter
FC-4
REFCLK =
106.25 MHz
Pattern = CRPAT
VOD = 800 mV
No Pre-emphasis
-
-
0.33
-
-
0.33
-
-
0.33
UI
Fibre Channel Receiver Jitter Tolerance (8), (18)
Deterministic jitter
FC-1
Pattern = CJTPAT
No Equalization
DC Gain = 0 dB
> 0.37
> 0.37
> 0.37
UI
Random jitter FC1
Pattern = CJTPAT
No Equalization
DC Gain = 0 dB
> 0.31
> 0.31
> 0.31
UI
4–20
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 4 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
Sinusoidal jitter
FC-1
Fc/25000
Fc/1667
> 0.1
Deterministic jitter
FC-2
Pattern = CJTPAT
No Equalization
DC Gain = 0 dB
> 0.33
Random jitter FC2
Pattern = CJTPAT
No Equalization
DC Gain = 0 dB
> 0.29
Sinusoidal jitter
FC-2
Fc/25000
> 1.5
Fc/1667
> 0.1
Deterministic jitter
FC-4
Pattern = CJTPAT
No Equalization
DC Gain = 0 dB
> 0.33
Random jitter FC4
Pattern = CJTPAT
No Equalization
DC Gain = 0 dB
> 0.29
Sinusoidal jitter
FC-4
Fc/25000
Fc/1667
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
> 1.5
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
> 1.5
Typ
Unit
Max
> 1.5
UI
> 0.1
> 0.1
UI
> 0.33
> 0.33
UI
> 0.29
> 0.29
UI
> 1.5
> 1.5
UI
> 0.1
> 0.1
UI
> 0.33
> 0.33
UI
> 0.29
> 0.29
UI
> 1.5
> 1.5
> 1.5
UI
> 0.1
> 0.1
> 0.1
UI
XAUI Transmit Jitter Generation (9)
Total jitter at
3.125 Gbps
REFCLK =
156.25 MHz
Pattern = CJPAT
VOD = 1200 mV
No Pre-emphasis
-
-
0.3
-
-
0.3
-
-
0.3
UI
Deterministic jitter
at 3.125 Gbps
REFCLK =
156.25 MHz
Pattern = CJPAT
VOD = 1200 mV
No Pre-emphasis
-
-
0.17
-
-
0.17
-
-
0.17
UI
XAUI Receiver Jitter Tolerance (9)
Total jitter
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
> 0.65
> 0.65
> 0.65
UI
Deterministic jitter
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
> 0.37
> 0.37
> 0.37
UI
Altera Corporation
June 2009
4–21
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 5 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
Peak-to-peak jitter Jitter frequency =
22.1 KHz
> 8.5
> 8.5
> 8.5
UI
Peak-to-peak jitter Jitter frequency =
1.875 MHz
> 0.1
> 0.1
> 0.1
UI
Peak-to-peak jitter Jitter frequency = 20
MHz
> 0.1
> 0.1
> 0.1
UI
PCI Express Transmit Jitter Generation (10)
Total jitter at 2.5
Gbps
Compliance pattern
VOD = 800 mV
Pre-emphasis
(1st post-tap) =
Setting 5
-
-
0.25
-
-
0.25
-
-
0.25
UI
PCI Express Receiver Jitter Tolerance (10)
Total jitter at 2.5
Gbps
> 0.6
Compliance pattern
No Equalization
DC gain = 3 dB
> 0.6
> 0.6
UI
Serial RapidIO Transmit Jitter Generation (11)
Deterministic Jitter Data Rate = 1.25,
(peak-to-peak)
2.5, 3.125 Gbps
REFCLK = 125 MHz
Pattern = CJPAT
VOD = 800 mV
No Pre-emphasis
-
-
0.17
-
-
0.17
-
-
0.17
UI
Total Jitter
(peak-to-peak)
-
-
0.35
-
-
0.35
-
-
0.35
UI
Data Rate = 1.25,
2.5, 3.125 Gbps
REFCLK = 125 MHz
Pattern = CJPAT
VOD = 800 mV
No Pre-emphasis
4–22
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 6 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
Serial RapidIO Receiver Jitter Tolerance (11)
Deterministic Jitter Data Rate = 1.25,
2.5, 3.125 Gbps
Tolerance
(peak-to-peak)
REFCLK = 125 MHz
Pattern = CJPAT
Equalizer Setting =
0 for 1.25 Gbps
Equalizer Setting =
6 for 2.5 Gbps
Equalizer Setting =
6 for 3.125 Gbps
> 0.37
> 0.37
> 0.37
UI
Data Rate = 1.25,
2.5, 3.125 Gbps
REFCLK = 125 MHz
Pattern = CJPAT
Equalizer Setting =
0 for 1.25 Gbps
Equalizer Setting =
6 for 2.5 Gbps
Equalizer Setting =
6 for 3.125 Gbps
> 0.55
> 0.55
> 0.55
UI
Combined
Deterministic and
Random Jitter
Tolerance
(peak-to-peak)
Altera Corporation
June 2009
4–23
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 7 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Sinusoidal Jitter
Tolerance
(peak-to-peak)
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
Jitter Frequency =
22.1 KHz
Data Rate = 1.25,
2.5, 3.125 Gbps
REFCLK = 125 MHz
Pattern = CJPAT
Equalizer Setting =
0 for 1.25 Gbps
Equalizer Setting =
6 for 2.5 Gbps
Equalizer Setting =
6 for 3.125 Gbps
> 8.5
> 8.5
> 8.5
UI
Jitter Frequency =
1.875 MHz
Data Rate = 1.25,
2.5, 3.125 Gbps
REFCLK = 125 MHz
Pattern = CJPAT
Equalizer Setting =
0 for 1.25 Gbps
Equalizer Setting =
6 for 2.5 Gbps
Equalizer Setting =
6 for 3.125 Gbps
> 0.1
> 0.1
> 0.1
UI
Jitter Frequency =
20 MHz
Data Rate = 1.25,
2.5, 3.125 Gbps
REFCLK = 125 MHz
Pattern = CJPAT
Equalizer Setting =
0 for 1.25 Gbps
Equalizer Setting =
6 for 2.5 Gbps
Equalizer Setting =
6 for 3.125 Gbps
> 0.1
> 0.1
> 0.1
UI
4–24
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 8 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
-4 Speed
Commercial and
Industrial Speed
Grade
-5 Speed
Commercial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Deterministic Jitter Data Rate =
(peak-to-peak)
1.25 Gbps
REFCLK = 125 MHz
Pattern = CRPAT
VOD = 1400 mV
No Pre-emphasis
-
-
0.14
-
-
0.14
-
-
0.14
UI
Total Jitter
(peak-to-peak)
-
-
0.279
-
-
0.279
-
-
0.279
UI
GIGE Transmit Jitter Generation (12)
Data Rate =
1.25 Gbps
REFCLK = 125 MHz
Pattern = CRPAT
VOD = 1400 mV
No Pre-emphasis
GIGE Receiver Jitter Tolerance (12)
Deterministic Jitter Data Rate =
1.25 Gbps
Tolerance
(peak-to-peak)
REFCLK = 125 MHz
Pattern = CJPAT
No Equalization
> 0.4
> 0.4
> 0.4
UI
Data Rate =
1.25 Gbps
REFCLK = 125 MHz
Pattern = CJPAT
No Equalization
> 0.66
> 0.66
> 0.66
UI
Combined
Deterministic and
Random Jitter
Tolerance
(peak-to-peak)
HiGig Transmit Jitter Generation (4), (13)
Deterministic Jitter Data Rate =
(peak-to-peak)
3.75 Gbps
REFCLK =
187.5 MHz
Pattern = CJPAT
VOD = 1200 mV
No Pre-emphasis
-
-
0.17
-
UI
Total Jitter
(peak-to-peak)
-
-
0.35
-
UI
Altera Corporation
June 2009
Data Rate =
3.75 Gbps
REFCLK =
187.5 MHz
Pattern = CJPAT
VOD = 1200 mV
No Pre-emphasis
4–25
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 9 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
HiGig Receiver Jitter Tolerance (13)
Deterministic Jitter Data Rate =
3.75 Gbps
Tolerance
(peak-to-peak)
REFCLK =
187.5 MHz
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
> 0.37
-
-
UI
Data Rate =
3.75 Gbps
REFCLK =
187.5 MHz
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
> 0.65
-
-
UI
Jitter Frequency =
22.1 KHz
Data Rate =
3.75 Gbps
REFCLK =
187.5 MHz
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
> 8.5
-
-
UI
Combined
Deterministic and
Random Jitter
Tolerance
(peak-to-peak)
4–26
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 10 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Sinusoidal Jitter
Tolerance
(peak-to-peak)
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
Jitter Frequency =
1.875 MHz
Data Rate =
3.75 Gbps
REFCLK =
187.5 MHz
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
> 0.1
-
-
UI
Jitter Frequency =
20 MHz
Data Rate =
3.75 Gbps
REFCLK =
187.5 MHz
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
> 0.1
-
-
UI
(OIF) CEI Transmitter Jitter Generation (14)
Total Jitter
(peak-to-peak)
Data Rate =
6.375 Gbps
REFCLK =
318.75 MHz
Pattern = PRBS15
Vod=1000 mV (5)
No Pre-emphasis
BER = 10-12
0.3
N/A
N/A
UI
(OIF) CEI Receiver Jitter Tolerance (14)
Deterministic Jitter Data Rate =
6.375 Gbps
Tolerance
Pattern = PRBS31
(peak-to-peak)
Equalizer Setting =
15
DC Gain = 0 dB
BER = 10-12
Altera Corporation
June 2009
> 0.675
N/A
N/A
UI
4–27
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 11 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Combined
Deterministic and
Random Jitter
Tolerance
(peak-to-peak)
Sinusoidal Jitter
Tolerance
(peak-to-peak)
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
Data Rate =
6.375 Gbps
Pattern = PRBS31
Equalizer Setting =
15
DC Gain = 0 dB
BER = 10-12
> 0.988
N/A
N/A
UI
Jitter Frequency =
38.2 KHz
Data Rate =
6.375 Gbps
Pattern = PRBS31
Equalizer Setting =
15
DC Gain = 0 dB
BER = 10-12
>5
N/A
N/A
UI
Jitter Frequency =
3.82 MHz
Data
Rate = 6.375 Gbps
Pattern = PRBS31
Equalizer Setting =
15
DC Gain = 0 dB
BER = 10-12
> 0.05
N/A
N/A
UI
Jitter Frequency =
20 MHz
Data Rate =
6.375 Gbps
Pattern = PRBS31
Equalizer Setting =
15
DC Gain = 0 dB
BER = 10-12
> 0.05
N/A
N/A
UI
4–28
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 12 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
CPRI Transmitter Jitter Generation (15)
Deterministic Jitter Data Rate =
(peak-to-peak)
614.4 Mbps,
1.2288 Gbps,
2.4576 Gbps
REFCLK =
61.44 MHz for
614.4 Mbps and
1.2288 Gbps
REFCLK =
122.88 MHz for
2.4576 Gbps
Pattern = CJPAT
Vod = 1400 mV
No Pre-emphasis
0.14
0.14
N/A
UI
Total Jitter
(peak-to-peak)
0.279
0.279
N/A
UI
Altera Corporation
June 2009
Data Rate =
614.4 Mbps,
1.2288 Gbps,
2.4576 Gbps
REFCLK =
61.44 MHz for
614.4 Mbps and
1.2288 Gbps
REFCLK =
122.88 MHz for
2.4576 Gbps
Pattern = CJPAT
Vod = 1400 mV
No Pre-emphasis
4–29
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 13 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
CPRI Receiver Jitter Tolerance (15)
Deterministic Jitter Data Rate =
614.4 Mbps,
Tolerance
1.2288 Gbps,
(peak-to-peak)
2.4576 Gbps
REFCLK =
61.44 MHz for
614.4 Mbps
REFCLK =
122.88 MHz for
1.2288 Gbps and
2.4576 Gbps
Pattern = CJPAT
Equalizer Setting =
6
DC Gain = 0 dB
> 0.4
> 0.4
N/A
UI
Data Rate =
614.4 Mbps,
1.2288 Gbps,
2.4576 Gbps
REFCLK =
61.44 MHz for
614.4 Mbps
REFCLK =
122.88 MHz for
1.2288 Gbps and
2.4576 Gbps
Pattern = CJPAT
Equalizer Setting =
6
DC Gain = 0 dB
> 0.66
> 0.66
N/A
UI
Combined
Deterministic and
Random Jitter
Tolerance
(peak-to-peak)
4–30
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 14 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Sinusoidal Jitter
Tolerance
(peak-to-peak) (6)
Altera Corporation
June 2009
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
Jitter Frequency =
22.1 KHz
Data Rate =
614.4 Mbps,
1.2288 Gbps,
2.4576 Gbps
REFCLK =
61.44 MHz for
614.4 Mbps
REFCLK =
122.88 MHz for
1.2288 Gbps and
2.4576 Gbps
Pattern = CJPAT
Equalizer Setting =
6
DC Gain = 0 dB
> 8.5
> 8.5
N/A
UI
Jitter Frequency =
1.875 MHz
Data Rate =
614.4 Mbps,
1.2288 Gbps,
2.4576 Gbps
REFCLK =
61.44 MHz for
614.4 Mbps
REFCLK =
122.88 MHz for
1.2288 Gbps and
2.4576 Gbps
Pattern = CJPAT
Equalizer Setting =
6
DC Gain = 0 dB
> 0.1
> 0.1
N/A
UI
4–31
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 15 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Jitter Frequency =
20 MHz
Data Rate =
614.4 Mbps,
1.2288 Gbps,
2.4576 Gbps
REFCLK =
61.44 MHz for
614.4 Mbps
REFCLK =
122.88 MHz for
1.2288 Gbps and
2.4576 Gbps
Pattern = CJPAT
Equalizer Setting =
6
DC Gain = 0 dB
Typ
> 0.1
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
> 0.1
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
N/A
Unit
Max
UI
Sinusoidal Jitter
Tolerance
(peak-to-peak) (6)
(cont.)
4–32
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 16 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
SDI Transmitter Jitter Generation (16)
Data Rate =
1.485 Gbps (HD)
REFCLK =
74.25 MHz
Pattern = ColorBar
Vod = 800 mV
No Pre-emphasis
Low-Frequency
Roll-Off = 100 KHz
0.2
0.2
0.2
UI
Data Rate =
2.97 Gbps (3G)
REFCLK =
148.5 MHz
Pattern = ColorBar
Vod = 800 mV
No Pre-emphasis
Low-Frequency
Roll-Off = 100 KHz
0.3
0.3
0.3
UI
Alignment Jitter
(peak-to-peak)
Altera Corporation
June 2009
4–33
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 17 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
SDI Receiver Jitter Tolerance (16)
Sinusoidal Jitter
Tolerance
(peak-to-peak)
Jitter Frequency =
15 KHz
Data Rate =
2.97 Gbps (3G)
REFCLK =
148.5 MHz
Pattern = Single
Line Scramble Color
Bar
No Equalization
DC Gain = 0 dB
>2
>2
>2
UI
Jitter Frequency =
100 KHz
Data Rate =
2.97 Gbps (3G)
REFCLK =
148.5 MHz
Pattern = Single
Line Scramble Color
Bar
No Equalization
DC Gain = 0 dB
> 0.3
> 0.3
> 0.3
UI
Jitter Frequency =
148.5 MHz
Data Rate =
2.97 Gbps (3G)
REFCLK =
148.5 MHz
Pattern = Single
Line Scramble Color
Bar
No Equalization
DC Gain = 0 dB
> 0.3
> 0.3
> 0.3
UI
4–34
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 18 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Sinusoidal Jitter
Tolerance
(peak-to-peak)
Altera Corporation
June 2009
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
Jitter Frequency =
20 KHz
Data Rate =
1.485 Gbps (HD)
REFCLK =
74.25 MHz
Pattern = 75% Color
Bar
No Equalization
DC Gain = 0 dB
>1
>1
>1
UI
Jitter Frequency =
100 KHz
Data Rate =
1.485 Gbps (HD)
REFCLK =
74.25 MHz
Pattern = 75% Color
Bar
No Equalization
DC Gain = 0 dB
> 0.2
> 0.2
> 0.2
UI
Jitter Frequency =
148.5 MHz
Data Rate =
1.485 Gbps (HD)
REFCLK =
74.25 MHz
Pattern = 75% Color
Bar
No Equalization
DC Gain = 0 dB
> 0.2
> 0.2
> 0.2
UI
4–35
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 19 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
Min
Typ
Max
-4 Speed
Commercial and
Industrial Speed
Grade
Min
Typ
Max
-5 Speed
Commercial Speed
Grade
Min
Typ
Unit
Max
Notes to Table 4–19:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
Dedicated REFCLK pins were used to drive the input reference clocks.
Jitter numbers specified are valid for the stated conditions only.
Refer to the protocol characterization documents for detailed information.
HiGig configuration is available in a -3 speed grade only. For more information, refer to the Stratix II GX Transceiver
Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook.
Stratix II GX transceivers meet CEI jitter generation specification of 0.3 UI for a VOD range of 400 mV to 1000 mV.
The Sinusoidal Jitter Tolerance Mask is defined only for low voltage (LV) variant of CPRI.
The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.
The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.
The jitter numbers for CPRI are compliant to the CPRI Specification V2.1.
The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
The Fibre Channel transmitter jitter generation numbers are compliant to the specification at βT interoperability point.
The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at βR interoperability point.
Table 4–20 provides information on recommended input clock jitter for
each mode.
Table 4–20. Recommended Input Clock Jitter (Part 1 of 2)
Mode
PCI-E
(OIF) CEI
PHY
Reference
Clock (MHz)
Vectron
LVPECL XO
Type/Model
RMS Jitter
Frequency
(12 kHz to 20
Range (MHz)
MHz) (ps)
Period Jitter
(Peak to
Peak) (ps)
Phase Noise
at 1 MHz
(dB c/Hz)
100
VCC6-Q/R
10 to 270
0.3
23
-149.9957
156.25
VCC6-Q/R
10 to 270
0.3
23
-146.2169
622.08
VCC6-Q
270 to 800
2
30
Not available
GIGE
62.5
VCC6-Q/R
10 to 270
0.3
23
-149.9957
125
VCC6-Q/R
10 to 270
0.3
23
-146.9957
XAUI
156.25
VCC6-Q/R
10 to 270
0.3
23
-146.2169
4–36
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–20. Recommended Input Clock Jitter (Part 2 of 2)
Mode
Reference
Clock (MHz)
Vectron
LVPECL XO
Type/Model
SONET/SDH
OC-48
SONET/SDH
OC-12
RMS Jitter
Frequency
(12 kHz to 20
Range (MHz)
MHz) (ps)
Period Jitter
(Peak to
Peak) (ps)
Phase Noise
at 1 MHz
(dB c/Hz)
77.76
VCC6-Q/R
10 to 270
0.3
23
-149.5476
155.52
VCC6-Q/R
10 to 270
0.3
23
-149.1903
311.04
VCC6-Q
270 to 800
2
30
Not available
622.08
VCC6-Q
270 to 800
2
30
Not available
62.2
VCC6-Q/R
10 to 270
0.3
23
-149.6289
311
VCC6-Q
270 to 800
2
30
Not available
77.76
VCC6-Q/R
10 to 270
0.3
23
-149.5476
155.52
VCC6-Q/R
10 to 270
0.3
23
-149.1903
622.08
VCC6-Q
270 to 800
2
30
Not available
Tables 4–21 and 4–22 show the transmitter and receiver PCS latency for
each mode, respectively.
Table 4–21. PCS Latency (Part 1 of 2) Note (1)
Transmitter PCS Latency
Functional Mode
XAUI
PIPE
Sum (2)
-
2-3
1
0.5
0.5
4-5
3-4
1
-
1
6-7
×1, ×4, ×8
16-bit channel
width
1
3-4
1
-
0.5
6-7
-
2-3
1
-
1
4-5
OC-12
-
2-3
1
-
1
4-5
OC-48
-
2-3
1
-
0.5
4-5
OC-96
Altera Corporation
June 2009
8B/10B
Encoder
1
-
2-3
1
-
0.5
4-5
-
2-3
1
-
0.5
4-5
614 Mbps,
1.228 Gbps
-
2
1
-
1
4
2.456 Gbps
-
2-3
1
-
1
4-5
(OIF) CEI PHY
CPRI (3)
Byte
TX State
Serializer Machine
×1, ×4, ×8
8-bit channel
width
GIGE
SONET/SDH
TX PIPE
TX
Phase
Comp
FIFO
Configuration
4–37
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–21. PCS Latency (Part 2 of 2) Note (1)
Transmitter PCS Latency
Functional Mode
Serial RapidIO
SDI
BASIC Single
Width
BASIC Double
Width
TX PIPE
TX
Phase
Comp
FIFO
1.25 Gbps,
2.5 Gbps,
3.125 Gbps
-
2-3
1
HD
10-bit channel
width
-
2-3
HD, 3G
20-bit channel
width
-
8-bit/10-bit
channel width
Configuration
Byte
TX State
Serializer Machine
8B/10B
Encoder
Sum (2)
-
0.5
4-5
1
-
1
4-5
2-3
1
-
0.5
4-5
-
2-3
1
-
1
4-5
16-bit/20-bit
channel width
-
2-3
1
-
0.5
4-5
16-bit/20-bit
channel width
-
2-3
1
-
1
4-5
32-bit/40-bit
channel width
-
2-3
1
-
0.5
4-5
Parallel
Loopback/
BIST
-
2-3
1
-
1
4-5
Notes to Table 4–21:
(1)
(2)
(3)
The latency numbers are with respect to the PLD-transceiver interface clock cycles.
The total latency number is rounded off in the Sum column.
For CPRI 614 Mbps and 1.228 Gbps data rates, the Quartus II software customizes the PLD-transceiver
interface clocking to achieve zero clock cycle uncertainty in the transmitter phase compensation FIFO
latency. For more details, refer to the CPRI Mode section in the Stratix II GX Transceiver Architecture Overview
chapter in volume 2 of the Stratix II GX Device Handbook.
4–38
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–22. PCS Latency (Part 1 of 3) Note (1)
Receiver PCS Latency
Functional
Mode
Word
Aligner
Deskew
FIFO
Rate
Matcher
(3)
8B/10B
Decoder
Receiver
State
Machine
Byte
Deserializer
Byte
Order
Receiver
Phase
Comp
FIFO
Receiver
PIPE
Sum
(2)
2-2.5
2-2.5
5.5-6.5
0.5
1
1
1
1-2
-
14-17
×1, ×4, ×8
8-bit
channel
width
4-5
-
11-13
1
-
1
1
2-3
1
21-25
×1, ×4, ×8
16-bit
channel
width
2-2.5
-
5.5-6.5
0.5
-
1
1
2-3
1
13-16
4-5
-
11-13
1
-
1
1
1-2
-
19-23
OC-12
6-7
-
-
1
-
1
1
1-2
-
10-12
Configuration
XAUI
PIPE
GIGE
SONET/
SDH
OC-48
3-3.5
-
-
0.5
-
1
1-2
1-2
-
7-9
OC-96
2-2.5
-
-
0.5
-
1
1
1-2
-
6-7
2.5
-
-
0.5
-
1
1
1-2
-
6-7
614 Mbps,
1.228 Gbps
4-5
-
-
1
-
1
1
1
-
8-9
2.456 Gbps
4-5
-
-
1
-
1
1
1-2
-
8-10
1.25 Gbps,
2.5 Gbps,
3.125 Gbps
2-2.5
-
-
0.5
-
1
1
1-2
-
6-7
HD
10-bit
channel
width
5
-
-
1
-
1
1
1-2
-
9-10
HD, 3G
20-bit
channel
width
2.5
-
-
0.5
-
1
1
1-2
-
6-7
(OIF)
CEI
PHY
CPRI
(4)
Serial
RapidIO
SDI
Altera Corporation
June 2009
4–39
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–22. PCS Latency (Part 2 of 3) Note (1)
Receiver PCS Latency
Functional
Mode
BASIC
Single
Width
Word
Aligner
Deskew
FIFO
Rate
Matcher
(3)
8B/10B
Decoder
Receiver
State
Machine
Byte
Deserializer
Byte
Order
Receiver
Phase
Comp
FIFO
Receiver
PIPE
Sum
(2)
8/10-bit
channel
width;
with Rate
Matcher
4-5
-
11-13
1
-
1
1
1-2
1
19-23
8/10-bit
channel
width;
without
Rate
Matcher
4-5
-
-
1
-
1
1
1-2
-
8-10
16/20-bit
channel
width;
with Rate
Matcher
2-2.5
-
5.5-6.5
0.5
-
1
1
1-2
-
11-14
16/20-bit
channel
width;
without
Rate
Matcher
2-2.5
-
-
0.5
-
1
1
1-2
-
6-7
Configuration
4–40
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–22. PCS Latency (Part 3 of 3) Note (1)
Receiver PCS Latency
Functional
Mode
BASIC
Double
Width
Word
Aligner
Deskew
FIFO
Rate
Matcher
(3)
8B/10B
Decoder
Receiver
State
Machine
Byte
Deserializer
Byte
Order
Receiver
Phase
Comp
FIFO
Receiver
PIPE
Sum
(2)
16/20-bit
channel
width; with
Rate
Matcher
4-5
-
11-13
1
-
1
1
1-2
-
19-23
16/20-bit
channel
width;
without
Rate
Matcher
4-5
-
-
1
-
1
1
1-2
-
8-10
32/40-bit
channel
width; with
Rate
Matcher
2-2.5
-
5.5-6.5
0.5
-
1
1
1-2
-
11-14
32/40-bit
channel
width;
without
Rate
Matcher
2-2.5
-
-
0.5
-
1
1-3
1-2
-
6-9
Configuration
Notes to Table 4–21:
(1)
(2)
(3)
(4)
The latency numbers are with respect to the PLD-transceiver interface clock cycles.
The total latency number is rounded off in the Sum column.
The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set
gap allowed by the protocol, actual PPM difference between the reference clocks, and so forth.
For CPRI 614 Mbps and 1.228 Gbps data rates, the Quartus II software customizes the PLD-transceiver interface clocking
to achieve zero clock cycle uncertainty in the receiver phase compensation FIFO latency. For more details, refer to the CPRI
Mode section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook
Altera Corporation
June 2009
4–41
Stratix II GX Device Handbook, Volume 1
Operating Conditions
DC Electrical Characteristics
Table 4–23 shows the Stratix II GX device family DC electrical
characteristics.
Table 4–23. Stratix II GX Device DC Operating Conditions (Part 1 of 2)
Symbol
Parameter
Conditions
Device
Note (1)
Minimum Typical Maximum
Unit
II
Input pin leakage
current
VI = VCCIOmax to
0 V (2)
All
–10
10
μA
IOZ
Tri-stated I/O pin
leakage current
VO = VCCIOmax to
0 V (2)
All
–10
10
μA
ICCINT0
VCCINT supply current
(standby)
VI = ground, no
load, no toggling
inputs
TJ = 25 °C
EP2SGX30
0.30
(3)
A
EP2SGX60
0.50
(3)
A
EP2SGX90
0.62
(3)
A
ICCPD0
ICCI00
VCCPD supply current
(standby)
VCCIO supply current
(standby)
EP2SGX130
0.82
(3)
A
VI = ground, no
load, no toggling
inputs
TJ = 25 °C,
VCCPD = 3.3V
EP2SGX30
2.7
(3)
mA
EP2SGX60
3.6
(3)
mA
EP2SGX90
4.3
(3)
mA
EP2SGX130
5.4
(3)
mA
VI = ground, no
load, no toggling
inputs
TJ = 25 °C
EP2SGX30
4.0
(3)
mA
EP2SGX60
4.0
(3)
mA
EP2SGX90
4.0
(3)
mA
EP2SGX130
4.0
(3)
mA
4–42
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–23. Stratix II GX Device DC Operating Conditions (Part 2 of 2)
Symbol
RCONF
(4)
Parameter
Conditions
Value of I/O pin pull-up
resistor before and
during configuration
Device
Note (1)
Minimum Typical Maximum
Unit
Vi = 0, VCCIO =
3.3 V
10
25
50
KOhm
Vi = 0, VCCIO =
2.5 V
15
35
70
KOhm
Vi = 0, VCCIO =
1.8 V
30
50
100
KOhm
Vi = 0, VCCIO =
1.5 V
40
75
150
KOhm
Vi = 0, VCCIO =
1.2 V
50
90
170
KOhm
1
2
KOhm
Recommended value of
I/O pin external
pull-down resistor
before and during
configuration
Notes to Table 4–23:
(1)
(2)
(3)
(4)
Typical values are for TA = 25 °C, VCCINT = 1.2 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO
settings (3.3, 2.5, 1.8, and 1.5 V).
Maximum values depend on the actual TJ and design utilization. See PowerPlay Early Power Estimator (EPE) and
Power Analyzer or the Quartus II PowerPlay Power Analyzer and Optimization Technology (available at www.altera.com)
for maximum values. See the section “Power Consumption” on page 4–59 for more information.
Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
I/O Standard Specifications
Tables 4–24 through 4–47 show the Stratix II GX device family I/O
standard specifications.
Table 4–24. LVTTL Specifications (Part 1 of 2)
Symbol
Parameter
VCCIO (1)
Output supply voltage
Conditions
Minimum
Maximum
Unit
3.135
3.465
V
VIH
High-level input voltage
1.7
4.0
V
VIL
Low-level input voltage
–0.3
0.8
V
VOH
High-level output voltage
Altera Corporation
June 2009
IOH = –4 mA (2)
2.4
V
4–43
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–24. LVTTL Specifications (Part 2 of 2)
Symbol
VOL
Parameter
Low-level output voltage
Conditions
Minimum
IOL = 4 mA (2)
Maximum
Unit
0.45
V
Notes to Table 4–24:
(1)
(2)
Stratix II GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
JESD8-B.
This specification is supported across all the programmable drive strength settings available for this I/O standard
as shown in the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Table 4–25. LVCMOS Specifications
Symbol
Parameter
Note (1)
Minimum
Maximum
Unit
3.135
3.465
V
High-level input voltage
1.7
4.0
V
VIL
Low-level input voltage
–0.3
0.8
V
VOH
High-level output voltage
VCCIO = 3.0, IOH = –0.1 mA (2)
VOL
Low-level output voltage
VCCIO = 3.0, IOL = 0.1 mA (2)
VCCIO(1)
Output supply voltage
VIH
Conditions
VCCIO – 0.2
V
0.2
V
Notes to Table 4–25:
(1)
(2)
Stratix II GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
JESD8-B.
This specification is supported across all the programmable drive strength available for this I/O standard as shown
in Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Table 4–26. 2.5-V I/O Specifications
Symbol
Parameter
Conditions
VCCIO (1)
Output supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –1 mA (2)
VOL
Low-level output voltage
IOL = 1 mA (2)
Minimum
Maximum
Unit
2.375
2.625
V
1.7
4.0
V
–0.3
0.7
2.0
V
V
0.4
V
Notes to Table 4–26:
(1)
(2)
The Stratix II GX device VCCIO voltage level support of 2.5 to 5% is narrower than defined in the Normal Range of
the EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
4–44
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–27. 1.8-V I/O Specifications
Symbol
Parameter
VCCIO (1)
Output supply voltage
VIH
High-level input voltage
Conditions
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –2 mA (2)
VOL
Low-level output voltage
IOL = 2 mA (2)
Minimum
Maximum
Unit
1.71
1.89
V
0.65 × VCCIO
2.25
V
–0.3
0.35 × VCCIO
VCCIO – 0.45
V
V
0.45
V
Notes to Table 4–27:
(1)
(2)
The Stratix II GX device VCCIO voltage level support of 1.8 to 5% is narrower than defined in the Normal Range of
the EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Table 4–28. 1.5-V I/O Specifications
Symbol
Parameter
VCCIO (1)
Output supply voltage
VIH
High-level input voltage
Conditions
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –2 mA (2)
VOL
Low-level output voltage
IOL = 2 mA (2)
Minimum
Maximum
Unit
1.425
1.575
V
0.65 VCCIO
VCCIO + 0.3
V
–0.3
0.35 VCCIO
V
0.75 VCCIO
V
0.25 VCCIO
V
Notes to Table 4–28:
(1)
(2)
The Stratix II GX device VCCIO voltage level support of 1.5 to 5% is narrower than defined in the Normal Range of
the EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Altera Corporation
June 2009
4–45
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Figures 4–6 and 4–7 show receiver input and transmitter output
waveforms, respectively, for all differential I/O standards (LVDS and
LVPECL).
Figure 4–6. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
VID
p−n=0V
VID (Peak-to-Peak)
VID
Figure 4–7. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
VOD
p−n=0V
VOD
4–46
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–29. 2.5-V LVDS I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
VCCIO
I/O supply voltage for left and
right I/O banks (1, 2, 5, and
6)
VID
Input differential voltage
swing (single-ended)
100
350
900
mV
VICM
Input common mode voltage
200
1,250
1,800
mV
VOD
Output differential voltage
(single-ended)
RL = 100 Ω
250
450
mV
VOCM
Output common mode
voltage
RL = 100 Ω
1.125
1.375
V
RL
Receiver differential input
discrete resistor (external to
Stratix II GX devices)
90
100
110
Ω
Minimum
Typical
Maximum
Unit
3.135
3.3
3.465
V
Table 4–30. 3.3-V LVDS I/O Specifications
Symbol
Parameter
Conditions
VCCIO (1)
I/O supply voltage for top and
bottom PLL banks (9, 10, 11,
and 12)
VID
Input differential voltage
swing (single-ended)
100
350
900
mV
VICM
Input common mode voltage
200
1,250
1,800
mV
VOD
Output differential voltage
(single-ended)
RL = 100 Ω
250
710
mV
VOCM
Output common mode
voltage
RL = 100 Ω
840
1,570
mV
RL
Receiver differential input
discrete resistor (external to
Stratix II GX devices)
110
Ω
90
100
Note to Table 4–30:
(1)
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Altera Corporation
June 2009
4–47
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–31. PCML Specifications Note (1)
Symbol
Parameter
References
Reference Clock
3.3-V PCML
1.5-V PCML
1.2-V PCML
Reference clock supported
PCML standards
VID
Peak-to-peak differential input
voltage
VICM
Input common mode voltage
R
On-chip termination resistors
The specifications are located in the Reference Clock section
of Table 4–6 on page 4–4.
The specifications listed in Table 4–6 are applicable to PCML
input standards.
Receiver
3.3-V PCML
1.5-V PCML
1.2-V PCML
Receiver supported PCML
standards
VID
Peak-to-peak differential input
voltage
VICM
Input common mode voltage
R
On-chip termination resistors
The specifications are located in the Receiver section of
Table 4–6 on page 4–4.
The specifications listed in Table 4–6 are applicable to PCML
input standards.
Transmitter
1.5-V PCML
1.2-V PCML
Transmitter supported PCML
standards
VCCH
Output buffer supply voltage
The specifications are located in Table 4–5 on page 4–4.
VOD
Peak-to-peak differential output
voltage
The specifications are located in Tables 4–7, 4–8, 4–9, 4–10,
4–11, and 4–12.
The specifications listed in these tables are applicable to
PCML output standards.
VOCM
Output common mode voltage
R
On-chip termination resistors
The specifications are located in the Transmitter section of
Table 4–6 on page 4–4.
The specifications listed in Table 4–6 are applicable to PCML
output standards.
Note to Table 4–31:
(1)
Stratix II GX devices support PCML input and output on GXB banks 13, 14, 15, 16, and 17. This table references
Stratix II GX PCML specifications that are located in other sections of the Stratix II GX Device Handbook.
4–48
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–32. LVPECL Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
3.135
3.3
3.465
V
600
1,000
mV
VCCIO (1)
I/O supply voltage
VID
Input differential voltage
swing (single-ended)
300
VICM
Input common mode voltage
1.0
2.5
V
VOD
Output differential voltage
(single-ended)
RL = 100 Ω
525
970
mV
VOCM
Output common mode
voltage
RL = 100 Ω
1,650
2,250
mV
RL
Receiver differential input
resistor
110
Ω
90
100
Note to Table 4–32:
(1)
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Table 4–33. 3.3-V PCI Specifications
Symbol
Parameter
VCCIO
Output supply voltage
Conditions
Minimum
Typical
Maximum
Unit
3.0
3.3
3.6
V
VIH
High-level input voltage
0.5 VCCIO
VCCIO + 0.5
V
VIL
Low-level input voltage
–0.3
0.3 VCCIO
V
VOH
High-level output voltage
IOUT = –500 μA
VOL
Low-level output voltage
IOUT = 1,500 μA
0.9 VCCIO
V
0.1 VCCIO
V
Maximum
Unit
3.0
3.6
V
Table 4–34. PCI-X Mode 1 Specifications
Symbol
Parameter
VCCIO
Output supply voltage
Conditions
Minimum
Typical
VIH
High-level input voltage
0.5 VCCIO
VCCIO + 0.5
V
VIL
Low-level input voltage
–0.3
0.35 VCCIO
V
VIPU
Input pull-up voltage
VOH
High-level output voltage
IOUT = –500 μA
VOL
Low-level output voltage
IOUT = 1,500 μA
Altera Corporation
June 2009
0.7 VCCIO
V
0.9 VCCIO
V
0.1 VCCIO
V
4–49
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–35. SSTL-18 Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.8
1.89
V
VREF
Reference voltage
0.855
0.9
0.945
V
VTT
Termination voltage
VREF – 0.04
VREF
VREF + 0.04
V
VIH (DC)
High-level DC input voltage
VREF + 0.125
VIL (DC)
Low-level DC input voltage
VIH (AC)
High-level AC input voltage
V
VREF – 0.125
VREF + 0.25
VIL (AC)
Low-level AC input voltage
VOH
High-level output voltage
IOH = –6.7 mA (1)
VOL
Low-level output voltage
IOL = 6.7 mA (1)
V
V
VREF – 0.25
VTT + 0.475
V
V
VTT – 0.475
V
Note to Table 4–35:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Table 4–36. SSTL-18 Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.8
1.89
V
VREF
Reference voltage
0.855
0.9
0.945
V
VTT
Termination voltage
VREF – 0.04
VREF
VREF + 0.04
V
VIH (DC) High-level DC input voltage
VREF + 0.125
VIL (DC) Low-level DC input voltage
VIH (AC) High-level AC input voltage
V
VREF – 0.125
V
VREF – 0.25
V
VREF + 0.25
VIL (AC) Low-level AC input voltage
VOH
High-level output voltage
IOH = –13.4 mA (1)
VOL
Low-level output voltage
IOL = 13.4 mA (1)
V
VCCIO – 0.28
V
0.28
V
Note to Table 4–36:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
4–50
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–37. SSTL-18 Class I and II Differential Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.8
1.89
V
VCCIO
Output supply voltage
1.71
VSWING
(DC)
DC differential input voltage
0.25
VX (AC)
AC differential input cross
point voltage
VSWING
(AC)
AC differential input voltage
VISO
Input clock signal offset
voltage
0.5 VCCIO
V
ΔVISO
Input clock signal offset
voltage variation
200
mV
VOX (AC)
AC differential cross point
voltage
V
(VCCIO/2) – 0.175
(VCCIO/2) + 0.175
0.5
V
V
(VCCIO/2) – 0.125
(VCCIO/2) + 0.125
V
Table 4–38. SSTL-2 Class I Specifications
Symbol
Parameter
VCCIO
Output supply voltage
VTT
Termination voltage
VREF
Reference voltage
VIH (DC)
High-level DC input voltage
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
VREF – 0.04
VREF
VREF + 0.04
V
1.188
1.25
1.313
V
VREF + 0.18
3.0
V
VREF – 0.18
VIL (DC)
Low-level DC input voltage
–0.3
VIH (AC)
High-level AC input voltage
VREF + 0.35
VIL (AC)
Low-level AC input voltage
VOH
High-level output voltage
IOH = –8.1 mA (1)
VOL
Low-level output voltage
IOL = 8.1 mA (1)
V
V
VREF – 0.35
VTT + 0.57
V
V
VTT – 0.57
V
Note to Table 4–38:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Table 4–39. SSTL-2 Class II Specifications
Symbol
Parameter
VCCIO
Output supply voltage
VTT
Termination voltage
VREF
Reference voltage
Altera Corporation
June 2009
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
VREF – 0.04
VREF
VREF + 0.04
V
1.188
1.25
1.313
V
4–51
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–39. SSTL-2 Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VIH (DC)
High-level DC input voltage
VREF + 0.18
VCCIO + 0.3
V
VIL (DC)
Low-level DC input voltage
–0.3
VREF – 0.18
V
VREF + 0.35
VREF – 0.35
V
VIH (AC)
High-level AC input voltage
VIL (AC)
Low-level AC input voltage
VOH
High-level output voltage
IOH = –16.4 mA (1)
VOL
Low-level output voltage
IOL = 16.4 mA (1)
V
VTT + 0.76
V
VTT – 0.76
V
Note to Table 4–39:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Table 4–40. SSTL-2 Class I and II Differential Specifications
Symbol
VCCIO
Parameter
Conditions
Output supply voltage
VSWING (DC) DC differential input voltage
VX (AC)
AC differential input cross
point voltage
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
0.36
V
(VCCIO/2) – 0.2
VSWING (AC) AC differential input voltage
(VCCIO/2) + 0.2
0.7
V
V
VISO
Input clock signal offset
voltage
0.5 VCCIO
V
ΔVISO
Input clock signal offset
voltage variation
200
mV
VOX (AC)
AC differential output cross
point voltage
(VCCIO/2) – 0.2
(VCCIO/2) + 0.2
V
Maximum
Unit
Table 4–41. 1.2-V HSTL Specifications
Symbol
Parameter
Conditions
Minimum
Typical
VCCIO
Output supply voltage
1.14
1.2
1.26
V
VREF
Reference voltage
0.48 VCCIO
0.5 VCCIO
0.52 VCCIO
V
VIH (DC) High-level DC input voltage
VREF + 0.08
VCCIO + 0.15
V
VIL (DC) Low-level DC input voltage
–0.15
VREF – 0.08
V
VIH (AC) High-level AC input voltage
VREF + 0.15
VCCIO + 0.24
V
VIL (AC) Low-level AC input voltage
–0.24
VREF – 0.15
V
4–52
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–41. 1.2-V HSTL Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VOH
High-level output voltage
IOH = 8 mA
VREF + 0.15
VCCIO + 0.15
V
VOL
Low-level output voltage
IOH = –8 mA
–0.15
VREF – 0.15
V
Table 4–42. 1.5-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.425
1.5
1.575
V
VREF
Input reference voltage
0.713
0.75
0.788
V
VTT
Termination voltage
0.713
0.75
0.788
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 8 mA (1)
VOL
Low-level output voltage
IOH = –8 mA (1)
V
V
VREF – 0.1
V
VREF – 0.2
V
V
VCCIO – 0.4
V
0.4
V
Note to Table 4–42:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Table 4–43. 1.5-V HSTL Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.425
1.50
1.575
V
VREF
Input reference voltage
0.713
0.75
0.788
V
VTT
Termination voltage
0.713
0.75
0.788
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 16 mA (1)
VOL
Low-level output voltage
IOH = –16 mA (1)
V
V
VREF – 0.1
V
VREF – 0.2
V
V
VCCIO – 0.4
V
0.4
V
Note to Table 4–43:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Altera Corporation
June 2009
4–53
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–44. 1.5-V HSTL Class I and II Differential Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.425
1.5
1.575
V
VCCIO
I/O supply voltage
VDIF (DC)
DC input differential voltage
0.2
VCM (DC)
DC common mode input
voltage
0.68
VDIF (AC)
AC differential input voltage
0.4
VOX (AC)
AC differential cross point
voltage
0.68
V
0.9
V
V
0.9
V
Table 4–45. 1.8-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.80
1.89
V
VREF
Input reference voltage
0.85
0.90
0.95
V
VTT
Termination voltage
0.85
0.90
0.95
V
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 8 mA (1)
VOL
Low-level output voltage
IOH = –8 mA (1)
V
VREF – 0.1
V
V
VREF – 0.2
VCCIO – 0.4
V
V
0.4
V
Note to Table 4–45:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
4–54
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–46. 1.8-V HSTL Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.80
1.89
V
VREF
Input reference voltage
0.85
0.90
0.95
V
VTT
Termination voltage
0.85
0.90
0.95
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 16 mA (1)
VOL
Low-level output voltage
IOH = –16 mA (1)
V
V
VREF – 0.1
V
V
VREF – 0.2
VCCIO – 0.4
V
V
0.4
V
Note to Table 4–46:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Table 4–47. 1.8-V HSTL Class I and II Differential Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.80
1.89
V
VCCIO
I/O supply voltage
1.71
VDIF (DC)
DC input differential voltage
0.2
VCM (DC)
DC common mode input
voltage
0.78
VDIF (AC)
AC differential input voltage
0.4
VOX (AC)
AC differential cross point
voltage
0.68
Altera Corporation
June 2009
V
1.12
V
V
0.9
V
4–55
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Bus Hold Specifications
Table 4–48 shows the Stratix II GX device family bus hold specifications.
Table 4–48. Bus Hold Parameters
VCCIO Level
Parameter
Conditions
1.2 V
Min
Max
1.5 V
Min
Max
1.8 V
Min
2.5 V
Max
Min
Max
3.3 V
Min
Unit
Max
Low
sustaining
current
VIN > VIL
(maximum)
22.5
25
30
50
70
μA
High
sustaining
current
VIN < VIH
(minimum)
–22.5
–25
–30
–50
–70
μA
Low
overdrive
current
0 V < VIN <
VCCIO
120
160
200
300
500
μA
High
overdrive
current
0 V < VIN <
VCCIO
–120
–160
–200
–300
–500
μA
2.0
V
Bus-hold
trip point
0.45
0.95
0.5
1.0
0.68
1.07
0.7
1.7
0.8
On-Chip Termination Specifications
Tables 4–49 and 4–50 define the specification for internal termination
resistance tolerance when using series or differential on-chip termination.
Table 4–49. On-Chip Termination Specification for Top and Bottom I/O Banks (Part 1 of 2) Notes (1), (2)
Resistance Tolerance
Symbol
25-Ω RS
3.3/2.5
50-Ω RS
3.3/2.5
Description
Conditions
Commercial
Max
Industrial
Max
Unit
Internal series termination with
calibration (25-Ω setting)
VCCIO = 3.3/2.5 V
±5
±10
%
Internal series termination without
calibration (25-Ω setting)
VCCIO = 3.3/2.5 V
±30
±30
%
Internal series termination with
calibration (50-Ω setting)
VCCIO = 3.3/2.5 V
±5
±10
%
Internal series termination without
calibration (50-Ω setting)
VCCIO = 3.3/2.5 V
±30
± 30
%
4–56
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–49. On-Chip Termination Specification for Top and Bottom I/O Banks (Part 2 of 2) Notes (1), (2)
Resistance Tolerance
Symbol
Description
Conditions
Commercial
Max
Industrial
Max
Unit
50-Ω RT
2.5
Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.8 V
±30
± 30
%
25-Ω RS
1.8
Internal series termination with
calibration (25-Ω setting)
VCCIO = 1.8 V
±5
±10
%
Internal series termination without
calibration (25-Ω setting)
VCCIO = 1.8 V
±30
±30
%
Internal series termination with
calibration (50-Ω setting)
VCCIO = 1.8 V
±5
±10
%
Internal series termination without
calibration (50-Ω setting)
VCCIO = 1.8 V
±30
±30
%
50-Ω RT
1.8
Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.8 V
±10
±15
%
50-Ω RS
1.5
Internal series termination with
calibration (50-Ω setting)
VCCIO = 1.5 V
±8
±10
%
Internal series termination without
calibration (50-Ω setting)
VCCIO = 1.5 V
±36
±36
%
50-Ω RT
1.5
Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.5 V
±10
±15
%
50-Ω RS
1.2
Internal series termination with
calibration (50-Ω setting)
VCCIO = 1.2 V
±8
±10
%
Internal series termination without
calibration (50-Ω setting)
VCCIO = 1.2 V
±50
±50
%
Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.2 V
±10
±15
%
50-Ω RS
1.8
50-Ω RT
1.2
Note for Table 4–49:
(1)
(2)
The resistance tolerance for calibrated SOCT is for the moment of calibration. If the temperature or voltage changes
over time, the tolerance may also change.
On-chip parallel termination with calibration is only supported for input pins.
Altera Corporation
June 2009
4–57
Stratix II GX Device Handbook, Volume 1
Operating Conditions
Table 4–50. Series and Differential On-Chip Termination Specification for Left I/O Banks Note (1)
Resistance Tolerance
Symbol
Description
Conditions
Commercial Industrial
Max
Max
Unit
25-Ω RS
3.3/2.5
Internal series termination without
calibration (25-Ω setting)
VCCIO = 3.3/2.5V
±30
±30
%
50-Ω RS
3.3/2.5/1.8
Internal series termination without
calibration (50-Ω setting)
VCCIO = 3.3/2.5/1.8V
±30
±30
%
50-Ω RS 1.5
Internal series termination without
calibration (50-Ω setting)
VCCIO = 1.5V
±36
±36
%
RD
Internal differential termination for
LVDS (100-Ω setting)
VCCIO = 2.5 V
±20
±25
%
Note to Table 4–50:
(1)
On-chip parallel termination with calibration is only supported for input pins.
Pin Capacitance
Table 4–51 shows the Stratix II GX device family pin capacitance.
Table 4–51. Stratix II GX Device Capacitance
Symbol
Note (1)
Typical
Unit
CIOTB
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
Parameter
5.0
pF
CIOL
Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed
differential receiver and transmitter pins.
6.1
pF
CCLKTB
Input capacitance on top/bottom clock input pins: CLK[4..7] and
CLK[12..15].
6.0
pF
CCLKL
Input capacitance on left clock inputs: CLK0 and CLK2.
6.1
pF
CCLKL+
Input capacitance on left clock inputs: CLK1 and CLK3.
3.3
pF
COUTFB
Input capacitance on dual-purpose clock output/feedback pins in PLL
banks 11 and 12.
6.7
pF
Note to Table 4–51:
(1)
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5 pF.
4–58
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Power
Consumption
Altera offers two ways to calculate power for a design: the Excel-based
PowerPlay early power estimator power calculator and the Quartus® II
PowerPlay power analyzer feature.
The interactive Excel-based PowerPlay early power estimator is typically
used prior to designing the FPGA in order to get an estimate of device
power. The Quartus II PowerPlay power analyzer provides better quality
estimates based on the specifics of the design after place-and-route is
complete. The power analyzer can apply a combination of user-entered,
simulation-derived and estimated signal activities which, combined with
detailed circuit models, can yield very accurate power estimates.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
f
For more information on PowerPlay tools, refer to the PowerPlay Early
Power Estimators (EPE) and Power Analyzer, the Quartus II PowerPlay
Analysis and Optimization Technology, and the PowerPlay Power Analyzer
chapter in volume 3 of the Quartus II Handbook. The PowerPlay early
power estimators are available on the Altera web site at
www.altera. com.
1
Timing Model
See Table 4–23 on page 42 for typical ICC standby specifications.
The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix II GX device densities and speed grades. This
section describes and specifies the performance, internal, external, and
PLL timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary. Table 4–52 shows the status of the
Stratix II GX device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Altera Corporation
June 2009
4–59
Stratix II GX Device Handbook, Volume 1
Timing Model
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
Table 4–52. Stratix II GX Device Timing Model Status
Device
Preliminary
Final
EP2SGX30
v
EP2SGX60
v
EP2SGX90
v
EP2SGX130
v
I/O Timing Measurement Methodology
Different I/O standards require different baseline loading techniques for
reporting timing delays. Altera characterizes timing delays with the
required termination for each I/O standard and with 0 pF (except for PCI
and PCI-X which use 10 pF) loading and the timing is specified up to the
output pin of the FPGA device. The Quartus II software calculates the
I/O timing for each I/O standard with a default baseline loading as
specified by the I/O standards.
The following measurements are made during device characterization.
Altera measures clock-to-output delays (tCO) at worst-case process,
minimum voltage, and maximum temperature (PVT) for default loading
conditions shown in Table 4–53. Use the following equations to calculate
clock pin to output pin timing for Stratix II GX devices.
tCO from clock pin to I/O pin = delay from clock pad to I/O output
register + IOE output register clock-to-output delay + delay
from output register to output pin + I/O output delay
txz/tzx from clock pin to I/O pin = delay from clock pad to I/O
output register + IOE output register clock-to-output delay +
delay from output register to output pin + I/O output delay +
output enable pin delay
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1.
Simulate the output driver of choice into the generalized test setup,
using values from Table 4–53.
2.
Record the time to VMEAS.
4–60
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
3.
Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS model or capacitance value to
represent the load.
4.
Record the time to VMEAS.
5.
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 4–53 using the above equation. Figure 4–8 shows the model of the
circuit that is represented by the output timing of the Quartus II software.
Figure 4–8. Output Delay Timing Reporting Setup Modeled by Quartus II
VTT
VCCIO
Outputp
RT
Output
Buffer
RS
Output
VMEAS
GND
Outputn
CL
RD
GND
Notes to Figure 4–8:
(1)
(2)
(3)
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
VCCPD is 3.085 V unless otherwise specified.
VCCINT is 1.12 V unless otherwise specified.
Table 4–53. Output Timing Measurement Methodology for Output Pins (Part 1 of 2) Notes (1), (2), (3)
Measurement
Point
Loading and Termination
I/O Standard
RS (Ω)
LVTTL (4)
RD (Ω)
RT (Ω)
VCCIO (V)
3.135
VTT (V)
CL (pF)
VMEAS (V)
0
1.5675
LVCMOS (4)
3.135
0
1.5675
2.5 V (4)
2.375
0
1.1875
1.8 V (4)
1.710
0
0.855
1.5 V (4)
1.425
0
0.7125
Altera Corporation
June 2009
4–61
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–53. Output Timing Measurement Methodology for Output Pins (Part 2 of 2) Notes (1), (2), (3)
Measurement
Point
Loading and Termination
I/O Standard
RS (Ω)
RD (Ω)
RT (Ω)
VCCIO (V)
VTT (V)
CL (pF)
VMEAS (V)
PCI (5)
2.970
10
1.485
PCI-X (5)
2.970
10
1.485
SSTL-2 Class I
25
50
2.325
1.123
0
1.1625
SSTL-2 Class II
25
25
2.325
1.123
0
1.1625
SSTL-18 Class I
25
50
1.660
0.790
0
0.83
SSTL-18 Class II
25
25
1.660
0.790
0
0.83
1.8-V HSTL Class I
50
1.660
0.790
0
0.83
1.8-V HSTL Class II
25
1.660
0.790
0
0.83
1.5-V HSTL Class I
50
1.375
0.648
0
0.6875
1.5-V HSTL Class II
25
1.375
0.648
0
0.6875
1.2-V HSTL with OCT
Differential SSTL-2 Class I
1.140
25
50
2.325
1.123
0
0.570
0
1.1625
Differential SSTL-2 Class II
25
25
2.325
1.123
0
1.1625
Differential SSTL-18 Class I
50
50
1.660
0.790
0
0.83
Differential SSTL-18 Class II
25
25
1.660
0.790
0
0.83
1.5-V differential HSTL Class I
50
1.375
0.648
0
0.6875
1.5-V differential HSTL Class II
25
1.375
0.648
0
0.6875
1.8-V differential HSTL Class I
50
1.660
0.790
0
0.83
25
1.660
0.790
1.8-V differential HSTL Class II
0
0.83
LVDS
100
2.325
0
1.1625
LVPECL
100
3.135
0
1.5675
Notes to Table 4–53:
(1)
(2)
(3)
(4)
(5)
Input measurement point at internal node is 0.5 VCCINT.
Output measuring point for VMEAS at buffer output is 0.5 VCCIO.
Input stimulus edge rate is 0 to VCC in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple.
VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V.
4–62
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Figures 4–9 and 4–10 show the measurement setup for output disable and
output enable timing.
Figure 4–9. Measurement Setup for txz
Note (1)
tXZ, Driving High to Tristate
Enable
OE
OE
½ VCCINT
Dout
Din
100 Ω
Disable
“1”
Din
100 mv
Dout
thz
GND
tXZ, Driving Low to Tristate
Enable
OE
100 Ω
Disable
½ VCCINT
OE
Dout
Din
Din
Dout
“0”
tlz
VCCIO
100 mv
Note to Figure 4–9:
(1)
Altera Corporation
June 2009
VCCINT is 1.12 V for this measurement.
4–63
Stratix II GX Device Handbook, Volume 1
Timing Model
Figure 4–10. Measurement Setup for tzx
tZX, Tristate to Driving High
Disable
OE
OE
Enable
½ VCCINT
Dout
Din
“1”
Din
1 MΩ
tzh
Dout
½ VCCIO
tZX, Tristate to Driving Low
Disable
Enable
½ VCCINT
OE
1 MΩ
OE
Dout
Din
“0”
Din
½ VCCIO
tzl
Dout
Table 4–54 specifies the input timing measurement setup.
Table 4–54. Timing Measurement Methodology for Input Pins (Part 1 of 2)
Notes (1), (2), (3), (4)
Measurement Conditions
Measurement Point
I/O Standard
VCCIO (V)
LVTTL (5)
VREF (V)
3.135
Edge Rate (ns)
VMEAS (V)
3.135
1.5675
LVCMOS (5)
3.135
3.135
1.5675
2.5 V (5)
2.375
2.375
1.1875
1.8 V (5)
1.710
1.710
0.855
1.5 V (5)
1.425
1.425
0.7125
PCI (6)
2.970
2.970
1.485
PCI-X (6)
2.970
2.970
1.485
SSTL-2 Class I
2.325
1.163
2.325
1.1625
SSTL-2 Class II
2.325
1.163
2.325
1.1625
SSTL-18 Class I
1.660
0.830
1.660
0.83
SSTL-18 Class II
1.660
0.830
1.660
0.83
1.8-V HSTL Class I
1.660
0.830
1.660
0.83
4–64
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–54. Timing Measurement Methodology for Input Pins (Part 2 of 2)
Notes (1), (2), (3), (4)
Measurement Conditions
Measurement Point
I/O Standard
VCCIO (V)
VREF (V)
Edge Rate (ns)
VMEAS (V)
1.8-V HSTL Class II
1.660
0.830
1.660
0.83
1.5-V HSTL Class I
1.375
0.688
1.375
0.6875
1.5-V HSTL Class II
1.375
0.688
1.375
0.6875
1.2-V HSTL with OCT
1.140
0.570
1.140
0.570
Differential SSTL-2 Class I
2.325
1.163
2.325
1.1625
Differential SSTL-2 Class II
2.325
1.163
2.325
1.1625
Differential SSTL-18 Class I
1.660
0.830
1.660
0.83
Differential SSTL-18 Class II
1.660
0.830
1.660
0.83
1.5-V differential HSTL Class I
1.375
0.688
1.375
0.6875
1.5-V differential HSTL Class II
1.375
0.688
1.375
0.6875
1.8-V differential HSTL Class I
1.660
0.830
1.660
0.83
1.8-V differential HSTL Class II
1.660
0.830
1.660
0.83
LVDS
2.325
0.100
1.1625
LVPECL
3.135
0.100
1.5675
Notes to Table 4–54:
(1)
(2)
(3)
(4)
(5)
(6)
Input buffer sees no load at buffer input.
Input measuring point at buffer input is 0.5 VCCIO.
Output measuring point is 0.5 VCC at internal node.
Input edge rate is 1 V/ns.
Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple.
VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V.
Altera Corporation
June 2009
4–65
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–55 shows the Stratix II GX performance for some common
designs. All performance values were obtained with the Quartus II
software compilation of LPM or MegaCore functions for FIR and FFT
designs.
Table 4–55. Stratix II GX Performance Notes (Part 1 of 3)
Note (1)
Resources Used
Performance
ALUTs
TriMatrix
Memory
Blocks
DSP
Blocks
-3 Speed
Grade
(2)
-3
Speed
Grade
(3)
-4 Speed
Grade
-5
Speed
Grade
Units
16-to-1
multiplexer (4)
21
0
0
657.03
620.73
589.62
477.09
MHz
32-to-1
multiplexer (4)
38
0
0
534.75
517.33
472.81
369.27
MHz
16-bit counter
16
0
0
568.18
539.66
507.61
422.47
MHz
64-bit counter
64
0
0
242.54
231.0
217.77
180.31
MHz
Simple
dual-port RAM
32 x 18bit
0
1
0
500.0
476.19
447.22
373.13
MHz
FIFO 32 x 18 bit
22
1
0
500.00
476.19
460.82
373.13
MHz
Simple dualTriMatrix
port RAM 128 x
Memory
M4K block 36bit
0
1
0
540.54
515.46
483.09
401.6
MHz
True dual-port
RAM 128 x 18bit
0
1
0
540.54
515.46
483.09
401.6
MHz
FIFO 128 x 36
bit
22
1
0
524.10
500.25
466.41
381.38
MHz
Applications
LE
TriMatrix
Memory
M512
block
4–66
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–55. Stratix II GX Performance Notes (Part 2 of 3)
Note (1)
Resources Used
Performance
ALUTs
TriMatrix
Memory
Blocks
DSP
Blocks
-3 Speed
Grade
(2)
-3
Speed
Grade
(3)
-4 Speed
Grade
-5
Speed
Grade
Units
Single port
TriMatrix
RAM 4K x
Memory
MegaRAM 144bit
block
Simple dualport RAM 4K x
144bit
0
1
0
349.65
333.33
313.47
261.09
MHz
0
1
0
420.16
400.0
375.93
313.47
MHz
True dual-port
RAM 4K x 144
bit
0
1
0
349.65
333.33
313.47
261.09
MHz
Single port
RAM 8K x 72 bit
0
1
0
354.6
337.83
317.46
263.85
MHz
Simple dualport RAM 8K x
72 bit
0
1
0
420.16
400.0
375.93
313.47
MHz
True dual-port
RAM 8K x 72 bit
0
1
0
349.65
333.33
313.47
261.09
MHz
Single port
RAM 16K x 36
bit
0
1
0
364.96
347.22
325.73
271.73
MHz
Simple dualport RAM 16K x
36 bit
0
1
0
420.16
400.0
375.93
313.47
MHz
True dual-port
RAM 16K x 36
bit
0
1
0
359.71
342.46
322.58
268.09
MHz
Single port
RAM 32K x 18
bit
0
1
0
364.96
347.22
325.73
271.73
MHz
Simple dualport RAM 32K x
18 bit
0
1
0
420.16
400.0
375.93
313.47
MHz
True dual-port
RAM 32K x 18
bit
0
1
0
359.71
342.46
322.58
268.09
MHz
Applications
Altera Corporation
June 2009
4–67
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–55. Stratix II GX Performance Notes (Part 3 of 3)
Note (1)
Resources Used
Performance
ALUTs
TriMatrix
Memory
Blocks
DSP
Blocks
-3 Speed
Grade
(2)
-3
Speed
Grade
(3)
-4 Speed
Grade
-5
Speed
Grade
Units
Single port RAM
TriMatrix
64K x 9 bit
Memory
MegaRAM Simple
block
dual-port RAM
(cont.)
64K x 9 bit
0
1
0
364.96
347.22
325.73
271.73
MHz
0
1
0
420.16
400.0
375.93
313.47
MHz
True dual-port
RAM 64K x 9 bit
0
1
0
359.71
342.46
322.58
268.09
MHz
9 x 9-bit
multiplier (5)
0
0
1
430.29
409.16
385.2
320.1
MHz
18 x 18-bit
multiplier (5)
0
0
1
410.17
390.01
367.1
305.06
MHz
18 x 18-bit
multiplier (7)
0
0
1
450.04
428.08
403.22
335.12
MHz
36 x 36-bit
multiplier (5)
0
0
1
250.0
238.15
224.01
186.6
MHz
36 x 36-bit
multiplier (6)
0
0
1
410.17
390.01
367.1
305.06
MHz
18-bit, 4-tap FIR
filter
0
0
1
410.17
390.01
367.1
305.06
MHz
Applications
DSP
block
Notes to Table 4–55:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
These design performance numbers were obtained using the Quartus II software.
This column refers to -3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to -3 speed grades for EP2SGX130 devices.
This application uses registered inputs and outputs.
This application uses registered multiplier input and output stages within the DSP block.
This application uses registered multiplier input, pipeline, and output stages within the DSP block.
This application uses registered multiplier inputs with outputs of the multiplier stage feeding the accumulator or
subtractor within the DSP block.
4–68
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Internal Timing Parameters
Refer to Tables 4–56 through 4–61 for internal timing parameters.
Table 4–56. LE_FF Internal Timing Microparameters
Symbol
-3 Speed
Grade (1)
Parameter
Min
-3 Speed
Grade (2)
Max
Min
-4 Speed Grade
Max
Min
Max
-5 Speed
Grade
Min
Unit
Max
tSU
LE register setup time
before clock
90
95
101
121
ps
tH
LE register hold time after
clock
149
157
167
200
ps
tCO
LE register
clock-to-output delay
62
tCLR
Minimum clear pulse
width
204
214
227
273
ps
tPRE
Minimum preset pulse
width
204
214
227
273
ps
tCLKL
Minimum clock low time
612
642
683
820
ps
tCLKH
Minimum clock high time
612
642
683
820
ps
94
62
99
62
105
62
127
tL U T
170
378
170
397
170
422
170
507
tA D D E R
372
619
372
650
372
691
372
829
ps
Notes to Table 4–56:
(1)
(2)
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Table 4–57. IOE Internal Timing Microparameters (Part 1 of 2)
Symbol
Parameter
-3 Speed
Grade (1)
Min
Max
-3 Speed
Grade (2)
Min
Max
-4 Speed
Grade
Min
Max
-5 Speed
Grade
Min
Unit
Max
tSU
IOE input and output
register setup time
before clock
122
128
136
163
ps
tH
IOE input and output
register hold time after
clock
72
75
80
96
ps
tCO
IOE input and output
register clock-to-output
delay
101
Altera Corporation
June 2009
169
101
177
101
188
101
226
ps
4–69
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–57. IOE Internal Timing Microparameters (Part 2 of 2)
Symbol
-3 Speed
Grade (1)
Parameter
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tPIN2COMBOUT_R Row input pin to IOE
combinational output
410
760
410
798
410
848
410
1018
ps
tPIN2COMBOUT_C Column input pin to
IOE combinational
output
428
787
428
825
428
878
428
1054
ps
tCOMBIN2PIN_R
Row IOE data input to
combinational output
pin
1101
2026
1101
2127
1101
2261
1101
2439
ps
tCOMBIN2PIN_C
Column IOE data input
to combinational output
pin
991
1854
991
1946
991
2069
991
2246
ps
tCLR
Minimum clear pulse
width
200
210
223
268
ps
tPRE
Minimum preset pulse
width
200
210
223
268
ps
tCLKL
Minimum clock low
time
600
630
669
804
ps
tCLKH
Minimum clock high
time
600
630
669
804
ps
Notes to Table 4–57:
(1)
(2)
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Table 4–58. DSP Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Parameter
-3 Speed
Grade (1)
Min
Max
-3 Speed
Grade (2)
Min
Max
-4 Speed
Grade
Min
Max
-5 Speed
Grade
Min
Unit
Max
tSU
Input, pipeline, and
output register setup
time before clock
50
52
55
67
ps
tH
Input, pipeline, and
output register hold
time after clock
180
189
200
241
ps
tCO
Input, pipeline, and
output register
clock-to-output
delay
0
4–70
Stratix II GX Device Handbook, Volume 1
0
0
0
0
0
0
0
ps
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–58. DSP Block Internal Timing Microparameters (Part 2 of 2)
Symbol
Parameter
-3 Speed
Grade (1)
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tINREG2PIPE9
Input register to
DSP block pipeline
register in 9 × 9-bit
mode
1312
2030
1312
2131
1312
2266
1312
2720
ps
tINREG2PIPE18
Input register to
DSP block pipeline
register in 18 × 18bit mode
1302
2010
1302
2110
1302
2244
1302
2693
ps
tINREG2PIPE36
Input register to
DSP block pipeline
register in 36 × 36bit mode
1302
2010
1302
2110
1302
2244
1302
2693
ps
tPIPE2OUTREG2ADD DSP block pipeline
register to output
register delay in
two-multipliers
adder mode
924
1450
924
1522
924
1618
924
1943
ps
tPIPE2OUTREG4ADD DSP block pipeline
register to output
register delay in
four-multipliers
adder mode
1134
1850
1134
1942
1134
2065
1134
2479
ps
tPD9
Combinational input
to output delay for
9×9
2100
2880
2100
3024
2100
3214
2100
3859
ps
tPD18
Combinational input
to output delay for
18 × 18
2110
2990
2110
3139
2110
3337
2110
4006
ps
tPD36
Combinational input
to output delay for
36 × 36
2939
4450
2939
4672
2939
4967
2939
5962
ps
tCLR
Minimum clear pulse
width
2212
2322
2469
2964
ps
tCLKL
Minimum clock low
time
1190
1249
1328
1594
ps
tCLKH
Minimum clock high
time
1190
1249
1328
1594
ps
Notes to Table 4–58:
(1)
(2)
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Altera Corporation
June 2009
4–71
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–59. M512 Block Internal Timing Microparameters (Part 1 of 2)
Symbol
-3 Speed
Grade(2)
Parameter
-3 Speed Grade
-4 Speed Grade -5 Speed Grade
(3)
Unit
Min
Max
Min
Max
Min
Max
Min
Max
2318
2089
2433
2089
2587
2089
3104
tM512RC
Synchronous
read cycle time
2089
tM512WERESU
Write or read
enable setup
time before clock
22
23
24
29
ps
tM512WEREH
Write or read
enable hold time
after clock
203
213
226
272
ps
tM512DATASU
Data setup time
before clock
22
23
24
29
ps
tM512DATAH
Data hold time
after clock
203
213
226
272
ps
tM512WADDRSU Write address
setup time before
clock
22
23
24
29
ps
tM512WADDRH
Write address
hold time after
clock
203
213
226
272
ps
tM512RADDRSU
Read address
setup time before
clock
22
23
24
29
ps
tM512RADDRH
Read address
hold time after
clock
203
213
226
272
ps
tM512DATACO1
Clock-to-output
delay when using
output registers
298
478
298
501
298
533
298
640
ps
tM512DATACO2
Clock-to-output
delay without
output registers
2102
2345
2102
2461
2102
2616
2102
3141
ps
tM512CLKL
Minimum clock
low time
1315
1380
1468
1762
ps
tM512CLKH
Minimum clock
high time
1315
1380
1468
1762
ps
4–72
Stratix II GX Device Handbook, Volume 1
ps
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–59. M512 Block Internal Timing Microparameters (Part 2 of 2)
Symbol
Parameter
-3 Speed
Grade(2)
Min
tM512CLR
Minimum clear
pulse width
Max
144
-3 Speed Grade
-4 Speed Grade -5 Speed Grade
(3)
Unit
Min
Max
151
Min
Max
160
Min
Max
192
ps
Notes to Table 4–59:
(1)
(2)
(3)
The M512 block fMAX obtained using the Quartus II software does not necessarily equal to 1/TM512RC.
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Table 4–60. M4K Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Parameter
Note (1)
-3 Speed Grade -3 Speed Grade
-4 Speed Grade -5 Speed Grade
(2)
(3)
Unit
Min
Max
Min
Max
Min
Max
Min
Max
1462
2240
1462
2351
1462
2500
1462
3000
tM4KRC
Synchronous
read cycle time
tM4KWERESU
Write or read
enable setup
time before clock
22
23
24
29
ps
tM4KWEREH
Write or read
enable hold time
after clock
203
213
226
272
ps
tM4KBESU
Byte enable
setup time before
clock
22
23
24
29
ps
tM4KBEH
Byte enable hold
time after clock
203
213
226
272
ps
tM4KDATAASU
A port data setup
time before clock
22
23
24
29
ps
tM4KDATAAH
A port data hold
time after clock
203
213
226
272
ps
tM4KADDRASU
A port address
setup time before
clock
22
23
24
29
ps
tM4KADDRAH
A port address
hold time after
clock
203
213
226
272
ps
tM4KDATABSU
B port data setup
time before clock
22
23
24
29
ps
Altera Corporation
June 2009
ps
4–73
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–60. M4K Block Internal Timing Microparameters (Part 2 of 2)
Symbol
Parameter
-3 Speed Grade -3 Speed Grade
-4 Speed Grade -5 Speed Grade
(2)
(3)
Unit
Min
tM4KDATABH
Note (1)
B port data hold
time after clock
Max
Min
Max
Min
Max
Min
Max
203
213
226
272
ps
tM4KRADDRBSU B port address
setup time before
clock
22
23
24
29
ps
tM4KRADDRBH
B port address
hold time after
clock
203
213
226
272
ps
tM4KDATACO1
Clock-to-output
delay when using
output registers
334
524
334
549
334
584
334
701
ps
tM4KDATACO2
Clock-to-output
delay without
output registers
1616
2453
1616
2574
1616
2737
1616
3286
ps
tM4KCLKH
Minimum clock
high time
1250
1312
1395
1675
ps
tM4KCLKL
Minimum clock
low time
1250
1312
1395
1675
ps
tM4KCLR
Minimum clear
pulse width
144
151
160
192
ps
Notes to Table 4–60:
(1)
(2)
(3)
The M512 block fMAX obtained using the Quartus II software does not necessarily equal to 1/TM4KRC.
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Table 4–61. M-RAM Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Parameter
-3 Speed
Grade (2)
-3 Speed
Grade (3)
Note (1)
-4 Speed
Grade
-5 Speed
Grade
Min
Max
Min
Max
Min
Max
Min
Max
1866
2774
1866
2911
1866
3096
1866
3716
Unit
tMEGARC
Synchronous read
cycle time
tMEGAWERESU
Write or read enable
setup time before
clock
144
151
160
192
ps
tMEGAWEREH
Write or read enable
hold time after clock
39
40
43
52
ps
4–74
Stratix II GX Device Handbook, Volume 1
ps
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–61. M-RAM Block Internal Timing Microparameters (Part 2 of 2)
Symbol
Parameter
-3 Speed
Grade (2)
Min
Max
-3 Speed
Grade (3)
Min
Max
Note (1)
-4 Speed
Grade
Min
Max
-5 Speed
Grade
Min
Unit
Max
tMEGABESU
Byte enable setup time
before clock
-9
-10
-11
-13
ps
tMEGABEH
Byte enable hold time
after clock
39
40
43
52
ps
tMEGADATAASU
A port data setup time
before clock
50
52
55
67
ps
tMEGADATAAH
A port data hold time
after clock
243
255
271
325
ps
tMEGAADDRASU A port address setup
time before clock
589
618
657
789
ps
tMEGAADDRAH
A port address hold
time after clock
-347
-365
-388
-465
ps
tMEGADATABSU
B port setup time
before clock
50
52
55
67
ps
tMEGADATABH
B port hold time after
clock
243
255
271
325
ps
tMEGAADDRBSU B port address setup
time before clock
589
618
657
789
ps
tMEGAADDRBH
B port address hold
time after clock
-347
-365
-388
-465
ps
tMEGADATACO1
Clock-to-output delay
when using output
registers
480
715
480
749
480
797
480
957
ps
tMEGADATACO2
Clock-to-output delay
without output
registers
1950
2899
1950
3042
1950
3235
1950
3884
ps
tMEGACLKL
Minimum clock low
time
1250
1312
1395
1675
ps
tMEGACLKH
Minimum clock high
time
1250
1312
1395
1675
ps
tMEGACLR
Minimum clear pulse
width
144
151
160
192
ps
Notes to Table 4–61:
(1)
(2)
(3)
The M512 block fMAX obtained using the Quartus II software does not necessarily equal to 1/TMEGARC.
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Altera Corporation
June 2009
4–75
Stratix II GX Device Handbook, Volume 1
Timing Model
Stratix II GX Clock Timing Parameters
See Tables 4–62 through 4–78 for Stratix II GX clock timing parameters.
Table 4–62. Stratix II GX Clock Timing Parameters
Symbol
Parameter
tCIN
Delay from clock pad to I/O input register
tCOUT
Delay from clock pad to I/O output register
tPLLCIN
Delay from PLL inclk pad to I/O input register
tPLLCOUT
Delay from PLL inclk pad to I/O output register
EP2SGX30 Clock Timing Parameters
Tables 4–63 through 4–66 show the maximum clock timing parameters
for EP2SGX30 devices.
Table 4–63. EP2SGX30 Column Pins Global Clock Timing Parameters
Fast Corner
Commercial
-3 Speed
Grade
-4 Speed
Grade
-5 Speed
Grade
Units
Industrial
tC I N
1.615
1.633
2.669
2.968
3.552
ns
tC O U T
1.450
1.468
2.427
2.698
3.228
ns
Parameter
tP L L C I N
tP L L C O U T
0.11
0.129
0.428
0.466
0.547
ns
-0.055
-0.036
0.186
0.196
0.223
ns
Table 4–64. EP2SGX30 Row Pins Global Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
1.365
1.382
2.280
Parameter
tC I N
-4 Speed
Grade
-5 Speed
Grade
Units
2.535
3.033
ns
tC O U T
1.370
1.387
2.276
2.531
3.028
ns
tP L L C I N
-0.151
-0.136
0.043
0.037
0.032
ns
tP L L C O U T
-0.146
-0.131
0.039
0.033
0.027
ns
4–76
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–65. EP2SGX30 Column Pins Regional Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
tC I N
1.493
1.507
2.522
tC O U T
1.353
1.372
2.525
2.809
3.364
ns
tP L L C I N
0.087
0.104
0.237
0.253
0.292
ns
tP L L C O U T
-0.078
-0.061
0.237
0.253
0.29
ns
Parameter
-4 Speed
Grade
-5 Speed
Grade
Units
2.806
3.364
ns
Table 4–66. EP2SGX30 Row Pins Regional Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
tC I N
1.246
1.262
2.437
2.712
3.246
ns
tC O U T
1.251
1.267
2.437
2.712
3.246
ns
tP L L C I N
-0.18
-0.167
0.215
0.229
0.263
ns
tP L L C O U T
-0.175
-0.162
0.215
0.229
0.263
ns
Parameter
-4 Speed
Grade
-5 Speed
Grade
Units
EP2SGX60 Clock Timing Parameters
Tables 4–67 through 4–70 show the maximum clock timing parameters
for EP2SGX60 devices.
Table 4–67. EP2SGX60 Column Pins Global Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
tC I N
1.722
1.736
2.940
3.275
3.919
ns
tC O U T
1.557
1.571
2.698
3.005
3.595
ns
tP L L C I N
0.037
0.051
0.474
0.521
0.613
ns
tP L L C O U T
-0.128
-0.114
0.232
0.251
0.289
ns
Parameter
Altera Corporation
June 2009
-4 Speed
Grade
-5 Speed
Grade
Units
4–77
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–68. EP2SGX60 Row Pins Global Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
1.494
1.508
2.582
Parameter
tC I N
-4 Speed
Grade
-5 Speed
Grade
Units
2.875
3.441
ns
tC O U T
1.499
1.513
2.578
2.871
3.436
ns
tP L L C I N
-0.183
-0.168
0.116
0.122
0.135
ns
tP L L C O U T
-0.178
-0.163
0.112
0.118
0.13
ns
Table 4–69. EP2SGX60 Column Pins Regional Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
tC I N
1.577
1.591
2.736
3.048
3.648
ns
tC O U T
1.412
1.426
2.740
3.052
3.653
ns
tP L L C I N
0.065
0.08
0.334
0.361
0.423
ns
-0.1
-0.085
0.334
0.361
0.423
ns
Parameter
tP L L C O U T
-4 Speed
Grade
-5 Speed
Grade
Units
Table 4–70. EP2SGX60 Row Pins Regional Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
tC I N
1.342
1.355
2.716
3.024
3.622
ns
tC O U T
1.347
1.360
2.716
3.024
3.622
ns
tP L L C I N
-0.18
-0.166
0.326
0.352
0.412
ns
tP L L C O U T
-0.175
-0.161
0.334
0.361
0.423
ns
Parameter
4–78
Stratix II GX Device Handbook, Volume 1
-4 Speed
Grade
-5 Speed
Grade
Units
Altera Corporation
June 2009
DC and Switching Characteristics
EP2SGX90 Clock Timing Parameters
Tables 4–71 through 4–74 show the maximum clock timing parameters
for EP2SGX90 devices.
Table 4–71. EP2SGX90 Column Pins Global Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
tC I N
1.861
1.878
3.115
3.465
4.143
ns
tC O U T
1.696
1.713
2.873
3.195
3.819
ns
tP L L C I N
-0.254
-0.237
0.171
0.179
0.206
ns
tP L L C O U T
-0.419
-0.402
-0.071
-0.091
-0.118
ns
Parameter
-4 Speed
Grade
-5 Speed
Grade
Units
Table 4–72. EP2SGX90 Row Pins Global Clock Timing Parameters
Fast Corner
Commercial
-3 Speed
Grade
-4 Speed
Grade
-5 Speed
Grade
Units
Industrial
tC I N
1.634
1.650
2.768
3.076
3.678
ns
tC O U T
1.639
1.655
2.764
3.072
3.673
ns
tP L L C I N
-0.481
-0.465
-0.189
-0.223
-0.279
ns
tP L L C O U T
-0.476
-0.46
-0.193
-0.227
-0.284
ns
Parameter
Table 4–73. EP2SGX90 Column Pins Regional Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
1.688
1.702
2.896
Parameter
tC I N
-4 Speed
Grade
-5 Speed
Grade
Units
3.224
3.856
ns
tC O U T
1.551
1.569
2.893
3.220
3.851
ns
tP L L C I N
-0.105
-0.089
0.224
0.241
0.254
ns
tP L L C O U T
-0.27
-0.254
0.224
0.241
0.254
ns
Altera Corporation
June 2009
4–79
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–74. EP2SGX90 Row Pins Regional Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
1.444
1.461
2.792
Parameter
tC I N
-4 Speed
Grade
-5 Speed
Grade
Units
3.108
3.716
ns
tC O U T
1.449
1.466
2.792
3.108
3.716
ns
tP L L C I N
-0.348
-0.333
0.204
0.217
0.243
ns
tP L L C O U T
-0.343
-0.328
0.212
0.217
0.254
ns
EP2SGX130 Clock Timing Parameters
Tables 4–75 through 4–78 show the maximum clock timing parameters
for EP2SGX130 devices.
Table 4–75. EP2SGX130 Column Pins Global Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
tC I N
1.980
1.998
3.491
3.706
4.434
ns
tC O U T
1.815
1.833
3.237
3.436
4.110
ns
tP L L C I N
-0.027
-0.009
0.307
0.322
0.376
ns
tP L L C O U T
-0.192
-0.174
0.053
0.052
0.052
ns
Parameter
-4 Speed
Grade
-5 Speed
Grade
Units
Table 4–76. EP2SGX130 Row Pins Global Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
tC I N
1.741
1.759
3.112
3.303
3.950
ns
tC O U T
1.746
1.764
3.108
3.299
3.945
ns
tP L L C I N
-0.261
-0.243
-0.089
-0.099
-0.129
ns
tP L L C O U T
-0.256
-0.238
-0.093
-0.103
-0.134
ns
Parameter
4–80
Stratix II GX Device Handbook, Volume 1
-4 Speed
Grade
-5 Speed
Grade
Units
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–77. EP2SGX130 Column Pins Regional Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
tC I N
1.815
1.834
3.218
3.417
4.087
ns
tC O U T
1.650
1.669
3.218
3.417
4.087
ns
tP L L C I N
0.116
0.134
0.349
0.364
0.426
ns
tP L L C O U T
-0.049
-0.031
0.361
0.378
0.444
ns
Parameter
-4 Speed
Grade
-5 Speed
Grade
Units
Table 4–78. EP2SGX130 Row Pins Regional Clock Timing Parameters
Fast Corner
Industrial
Commercial
-3 Speed
Grade
tC I N
1.544
1.560
3.195
3.395
4.060
ns
tC O U T
1.549
1.565
3.195
3.395
4.060
ns
tP L L C I N
-0.149
-0.132
0.34
0.356
0.417
ns
tP L L C O U T
-0.144
-0.127
0.342
0.356
0.417
ns
Parameter
-4 Speed
Grade
-5 Speed
Grade
Units
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, the intra-clock network
skew adder is not specified. Table 4–79 specifies the intra-clock skew
between any two clock networks driving any registers in the Stratix II GX
device.
Table 4–79. Clock Network Specifications
Name
(Part 1 of 2)
Max
Unit
Clock skew adder
EP2SGX30 (1)
Inter-clock network, same side
±50
ps
Inter-clock network, entire chip
±100
ps
Clock skew adder
EP2SGX60 (1)
Inter-clock network, same side
±50
ps
Inter-clock network, entire chip
±100
ps
Clock skew adder
EP2SGX90 (1)
Inter-clock network, same side
±55
ps
Inter-clock network, entire chip
±110
ps
Altera Corporation
June 2009
Description
Min
Typ
4–81
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–79. Clock Network Specifications
Name
Clock skew adder
EP2SGX130 (1)
(Part 2 of 2)
Description
Min
Typ
Max
Unit
Inter-clock network, same side
±63
ps
Inter-clock network, entire chip
±125
ps
Note to Table 4–79:
(1)
This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
IOE Programmable Delay
See Tables 4–80 and 4–81 for IOE programmable delay.
Table 4–80. Stratix II GX IOE Programmable Delay on Column Pins
Parameter
Input
delay from
pin to
internal
cells
Paths
Affected
Available
Settings
Pad to
I/O
dataout
to core
Pad to
Input
delay from I/O input
register
pin to
input
register
Delay
from
output
register to
output pin
I/O
output
register
to pad
tXZ, tZX
Output
enable pin
delay
Minimum
Timing
-3 Speed
Grade (2)
Note (1)
-3 Speed
Grade (3)
-4 Speed Grade
-5 Speed
Grade
Unit
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
8
0
1781
0
2881
0
3025
0
3217
0
3,860
ps
64
0
2053
0
3275
0
3439
0
3657
0
4388
ps
2
0
332
0
500
0
525
0
559
0
670
ps
2
0
320
0
483
0
507
0
539
0
647
ps
Notes to Table 4–80:
(1)
(2)
(3)
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the latest
version of the Quartus II software.
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
4–82
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–81. Stratix II GX IOE Programmable Delay on Row Pins
Minimum
Timing
Paths
Affected
Available
Settings
Input delay
from pin to
internal
cells
Pad to I/O
dataout to
logic array
8
0
1782
Input delay
from pin to
input
register
Pad to I/O
input
register
64
0
Delay from
output
register to
output pin
I/O output
register to
pad
2
Output
enable pin
delay
tXZ, tZX
2
Parameter
-3 Speed
Grade
Note (1)
-3 Speed
Grade
-4 Speed
Grade
-5 Speed
Grade
Unit
Min
Max
Offset Offset
Min
Offset
Max
Min
Offset Offset
Max
Offset
Min
Max
Min
Max
Offset Offset Offset Offset
0
2876
0
3020
0
3212
0
3853
ps
2054
0
3270
0
3434
0
3652
0
4381
ps
0
332
0
500
0
525
0
559
0
670
ps
0
320
0
483
0
507
0
539
0
647
ps
Notes to Table 4–81:
(1)
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the latest
version of the Quartus II software.
Default Capacitive Loading of Different I/O Standards
See Table 4–82 for default capacitive loading of different I/O standards.
Table 4–82. Default Loading of Different I/O Standards for Stratix II GX
Devices (Part 1 of 2)
I/O Standard
Altera Corporation
June 2009
Capacitive Load
Unit
LVTTL
0
pF
LVCMOS
0
pF
2.5 V
0
pF
1.8 V
0
pF
1.5 V
0
pF
PCI
10
pF
PCI-X
10
pF
SSTL-2 Class I
0
pF
SSTL-2 Class II
0
pF
4–83
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–82. Default Loading of Different I/O Standards for Stratix II GX
Devices (Part 2 of 2)
I/O Standard
Capacitive Load
Unit
SSTL-18 Class I
0
pF
SSTL-18 Class II
0
pF
1.5-V HSTL Class I
0
pF
1.5-V HSTL Class II
0
pF
1.8-V HSTL Class I
0
pF
1.8-V HSTL Class II
0
pF
Differential SSTL-2 Class I
0
pF
Differential SSTL-2 Class II
0
pF
Differential SSTL-18 Class I
0
pF
Differential SSTL-18 Class II
0
pF
1.5-V differential HSTL Class I
0
pF
1.5-V differential HSTL Class II
0
pF
1.8-V differential HSTL Class I
0
pF
1.8-V differential HSTL Class II
0
pF
LVDS
0
pF
I/O Delays
See Tables 4–83 through 4–87 for I/O delays.
Table 4–83. I/O Delay Parameters
Symbol
Parameter
tDIP
Delay from I/O datain to output pad
tOP
Delay from I/O output register to output pad
tPCOUT
Delay from input pad to I/O dataout to core
tPI
Delay from input pad to I/O input register
Table 4–84. Stratix II GX I/O Input Delay for Column Pins (Part 1 of 3)
I/O Standard
LVTTL
Parameter
Fast Corner
Industrial/
Commercial
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
tPI
707
1223
1282
1364
1637
ps
tPCOUT
428
787
825
878
1054
ps
4–84
Stratix II GX Device Handbook, Volume 1
-5 Speed
Unit
Grade
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–84. Stratix II GX I/O Input Delay for Column Pins (Part 2 of 3)
I/O Standard
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
PCI
PCI-X
Differential SSTL-2
Class I (1)
Altera Corporation
June 2009
Parameter
Fast Corner
Industrial/
Commercial
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
tPI
717
1210
1269
1349
1619
ps
tPCOUT
438
774
812
863
1036
ps
tPI
783
1366
1433
1523
1829
ps
tPCOUT
504
930
976
1037
1246
ps
-5 Speed
Unit
Grade
tPI
786
1436
1506
1602
1922
ps
tPCOUT
507
1000
1049
1116
1339
ps
tPI
707
1223
1282
1364
1637
ps
tPCOUT
428
787
825
878
1054
ps
tPI
530
818
857
912
1094
ps
tPCOUT
251
382
400
426
511
ps
tPI
530
818
857
912
1094
ps
tPCOUT
251
382
400
426
511
ps
tPI
569
898
941
1001
1201
ps
tPCOUT
290
462
484
515
618
ps
tPI
569
898
941
1001
1201
ps
tPCOUT
290
462
484
515
618
ps
tPI
587
993
1041
1107
1329
ps
tPCOUT
308
557
584
621
746
ps
tPI
587
993
1041
1107
1329
ps
tPCOUT
308
557
584
621
746
ps
tPI
569
898
941
1001
1201
ps
tPCOUT
290
462
484
515
618
ps
tPI
569
898
941
1001
1201
ps
tPCOUT
290
462
484
515
618
ps
tPI
712
1214
1273
1354
1625
ps
tPCOUT
433
778
816
868
1042
ps
tP I
712
1214
1273
1354
1625
ps
tPCOUT
433
778
816
868
1042
ps
tPI
530
818
857
912
1094
ps
tPCOUT
251
382
400
426
511
ps
4–85
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–84. Stratix II GX I/O Input Delay for Column Pins (Part 3 of 3)
I/O Standard
Differential SSTL-2
Class II (1)
Differential SSTL-18
Class I (1)
Differential SSTL-18
Class II (1)
1.8-V differential HSTL
Class I (1)
1.8-V differential HSTL
Class II (1)
1.5-V differential HSTL
Class I (1)
1.5-V differential HSTL
Class II (1)
Parameter
Fast Corner
Industrial/
Commercial
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
tPI
530
818
857
912
tPCOUT
251
382
400
tPI
569
898
941
tPCOUT
290
462
484
-5 Speed
Unit
Grade
1094
ps
426
511
ps
1001
1201
ps
515
618
ps
tPI
569
898
941
1001
1201
ps
tPCOUT
290
462
484
515
618
ps
tPI
569
898
941
1001
1201
ps
tPCOUT
290
462
484
515
618
ps
tPI
569
898
941
1001
1201
ps
tPCOUT
290
462
484
515
618
ps
tPI
587
993
1041
1107
1329
ps
tPCOUT
308
557
584
621
746
ps
tPI
587
993
1041
1107
1329
ps
tPCOUT
308
557
584
621
746
ps
Notes for Table 4–84:
(1)
(2)
(3)
These I/O standards are only supported on DQS pins.
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Table 4–85. Stratix II GX I/O Input Delay for Row Pins (Part 1 of 3)
I/O Standard
LVTTL
2.5 V
1.8 V
1.5 V
Parameter
Fast Corner
Industrial/
Commercial
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Unit
tPI
749
1287
1350
1435
1723
ps
tPCOUT
410
760
798
848
1018
ps
tPI
761
1273
1335
1419
1704
ps
tPCOUT
422
746
783
832
999
ps
tPI
827
1427
1497
1591
1911
ps
tPCOUT
488
900
945
1004
1206
ps
tPI
830
1498
1571
1671
2006
ps
tPCOUT
491
971
1019
1084
1301
ps
4–86
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–85. Stratix II GX I/O Input Delay for Row Pins (Part 2 of 3)
I/O Standard
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
PCI
PCI-X
LVDS (1)
HyperTransport
Differential SSTL-2
Class I
Differential SSTL-2
Class II
Altera Corporation
June 2009
Parameter
Fast Corner
Industrial/
Commercial
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Unit
tPI
749
1287
1350
1435
1723
ps
tPCOUT
410
760
798
848
1018
ps
tPI
573
879
921
980
1176
ps
tPCOUT
234
352
369
393
471
ps
tPI
573
879
921
980
1176
ps
tPCOUT
234
352
369
393
471
ps
tPI
605
960
1006
1070
1285
ps
tPCOUT
266
433
454
483
580
ps
tPI
605
960
1006
1070
1285
ps
tPCOUT
266
433
454
483
580
ps
tPI
631
1056
1107
1177
1413
ps
tPCOUT
292
529
555
590
708
ps
tPI
631
1056
1107
1177
1413
ps
tPCOUT
292
529
555
590
708
ps
tPI
605
960
1006
1070
1285
ps
tPCOUT
266
433
454
483
580
ps
tPI
605
960
1006
1070
1285
ps
tPCOUT
266
433
454
483
580
ps
tPI
830
1498
1571
1671
2006
ps
tPCOUT
491
971
1019
1084
1301
ps
tPI
830
1498
1571
1671
2006
ps
tPCOUT
491
971
1019
1084
1301
ps
tPI
540
948
994
1057
1269
ps
tPCOUT
201
421
442
470
564
ps
tPI
540
948
994
1057
1269
ps
tPCOUT
201
421
442
470
564
ps
tPI
573
879
921
980
1176
ps
tPCOUT
234
352
369
393
471
ps
tPI
573
879
921
980
1176
ps
tPCOUT
234
352
369
393
471
ps
4–87
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–85. Stratix II GX I/O Input Delay for Row Pins (Part 3 of 3)
I/O Standard
Differential SSTL-18
Class I
Differential SSTL-18
Class II
1.8-V differential HSTL
Class I
1.8-V differential HSTL
Class II
1.5-V differential HSTL
Class I
1.5-V differential HSTL
Class II
Parameter
Fast Corner
Industrial/
Commercial
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Unit
tPI
605
960
1006
1070
1285
ps
tPCOUT
266
433
454
483
580
ps
tPI
605
960
1006
1070
1285
ps
tPCOUT
266
433
454
483
580
ps
tPI
605
960
1006
1070
1285
ps
tPCOUT
266
433
454
483
580
ps
tPI
605
960
1006
1070
1285
ps
tPCOUT
266
433
454
483
580
ps
tPI
631
1056
1107
1177
1413
ps
tPCOUT
292
529
555
590
708
ps
tPI
631
1056
1107
1177
1413
ps
tPCOUT
292
529
555
590
708
ps
Notes to Table 4–85:
(1)
(2)
(3)
The parameters are only available on the left side of the device.
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
4–88
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–86. Stratix II GX I/O Output Delay for Column Pins (Part 1 of 7)
I/O Standard
LVTTL
Drive
Parameter
Strength
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA (1)
LVCMOS
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA (1)
Altera Corporation
June 2009
Fast Corner
-3 Speed
Industrial/
Grade (3)
Commercial
-3 Speed
Grade (4)
-4 Speed
Grade
-5 Speed
Grade
Unit
tOP
1236
2351
2467
2624
2820
ps
tDIP
1258
2417
2537
2698
2910
ps
tOP
1091
2036
2136
2272
2448
ps
tDIP
1113
2102
2206
2346
2538
ps
tOP
1024
2036
2136
2272
2448
ps
tDIP
1046
2102
2206
2346
2538
ps
tOP
998
1893
1986
2112
2279
ps
tDIP
1020
1959
2056
2186
2369
ps
tOP
976
1787
1875
1994
2154
ps
tDIP
998
1853
1945
2068
2244
ps
tOP
969
1788
1876
1995
2156
ps
tDIP
991
1854
1946
2069
2246
ps
tOP
1091
2036
2136
2272
2448
ps
tDIP
1113
2102
2206
2346
2538
ps
tOP
999
1786
1874
1993
2153
ps
tDIP
1021
1852
1944
2067
2243
ps
tOP
971
1720
1805
1919
2075
ps
tDIP
993
1786
1875
1993
2165
ps
tOP
978
1693
1776
1889
2043
ps
tDIP
1000
1759
1846
1963
2133
ps
tOP
965
1677
1759
1871
2025
ps
tDIP
987
1743
1829
1945
2115
ps
tOP
954
1659
1741
1851
2003
ps
tDIP
976
1725
1811
1925
2093
ps
4–89
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–86. Stratix II GX I/O Output Delay for Column Pins (Part 2 of 7)
I/O Standard
2.5 V
Drive
Parameter
Strength
4 mA
8 mA
12 mA
16 mA (1)
1.8 V
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA (1)
1.5 V
2 mA
4 mA
6 mA
8 mA (1)
Fast Corner
-3 Speed
Industrial/
Grade (3)
Commercial
-3 Speed
Grade (4)
-4 Speed
Grade
-5 Speed
Grade
Unit
tOP
1053
2063
2165
2302
2480
ps
tDIP
1075
2129
2235
2376
2570
ps
tOP
1001
1841
1932
2054
2218
ps
tDIP
1023
1907
2002
2128
2308
ps
tOP
980
1742
1828
1944
2101
ps
tDIP
1002
1808
1898
2018
2191
ps
tOP
962
1679
1762
1873
2027
ps
tDIP
984
1745
1832
1947
2117
ps
tOP
1093
2904
3048
3241
3472
ps
tDIP
1115
2970
3118
3315
3562
ps
tOP
1098
2248
2359
2509
2698
ps
tDIP
1120
2314
2429
2583
2788
ps
tOP
1022
2024
2124
2258
2434
ps
tDIP
1044
2090
2194
2332
2524
ps
tOP
1024
1947
2043
2172
2343
ps
tDIP
1046
2013
2113
2246
2433
ps
tOP
978
1882
1975
2100
2266
ps
tDIP
1000
1948
2045
2174
2356
ps
tOP
979
1833
1923
2045
2209
ps
tDIP
1001
1899
1993
2119
2299
ps
tOP
1073
2505
2629
2795
3002
ps
tDIP
1095
2571
2699
2869
3092
ps
tOP
1009
2023
2123
2257
2433
ps
tDIP
1031
2089
2193
2331
2523
ps
tOP
1012
1923
2018
2146
2315
ps
tDIP
1034
1989
2088
2220
2405
ps
tOP
971
1878
1970
2095
2262
ps
tDIP
993
1944
2040
2169
2352
ps
4–90
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–86. Stratix II GX I/O Output Delay for Column Pins (Part 3 of 7)
I/O Standard
SSTL-2 Class I
Drive
Parameter
Strength
8 mA
12 mA (1)
SSTL-2 Class II
16 mA
20 mA
24 mA (1)
SSTL-18 Class I
4 mA
6 mA
8 mA
10 mA
12 mA (1)
SSTL-18 Class II
8 mA
16 mA
18 mA
20 mA (1)
Altera Corporation
June 2009
Fast Corner
-3 Speed
Industrial/
Grade (3)
Commercial
-3 Speed
Grade (4)
-4 Speed
Grade
-5 Speed
Grade
Unit
tOP
957
1715
1799
1913
2041
ps
tDIP
979
1781
1869
1987
2131
ps
tOP
940
1672
1754
1865
1991
ps
tDIP
962
1738
1824
1939
2081
ps
tOP
918
1609
1688
1795
1918
ps
tDIP
940
1675
1758
1869
2008
ps
tOP
919
1598
1676
1783
1905
ps
tDIP
941
1664
1746
1857
1995
ps
tOP
915
1596
1674
1781
1903
ps
tDIP
937
1662
1744
1855
1993
ps
tOP
953
1690
1773
1886
2012
ps
tDIP
975
1756
1843
1960
2102
ps
tOP
958
1656
1737
1848
1973
ps
tDIP
980
1722
1807
1922
2063
ps
tOP
937
1640
1721
1830
1954
ps
tDIP
959
1706
1791
1904
2044
ps
tOP
942
1638
1718
1827
1952
ps
tDIP
964
1704
1788
1901
2042
ps
tOP
936
1626
1706
1814
1938
ps
tDIP
958
1692
1776
1888
2028
ps
tOP
925
1597
1675
1782
1904
ps
tDIP
947
1663
1745
1856
1994
ps
tOP
937
1578
1655
1761
1882
ps
tDIP
959
1644
1725
1835
1972
ps
tOP
933
1585
1663
1768
1890
ps
tDIP
955
1651
1733
1842
1980
ps
tOP
933
1583
1661
1766
1888
ps
tDIP
955
1649
1731
1840
1978
ps
4–91
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–86. Stratix II GX I/O Output Delay for Column Pins (Part 4 of 7)
I/O Standard
1.8-V HSTL
Class I
Drive
Parameter
Strength
4 mA
6 mA
8 mA
10 mA
12 mA (1)
1.8-V HSTL
Class II
16 mA
18 mA
20 mA (1)
1.5-V HSTL
Class I
4 mA
6 mA
8 mA
10 mA
12 mA (1)
Fast Corner
-3 Speed
Industrial/
Grade (3)
Commercial
-3 Speed
Grade (4)
-4 Speed
Grade
-5 Speed
Grade
Unit
tOP
956
1608
1687
1794
1943
ps
tDIP
978
1674
1757
1868
2033
ps
tOP
962
1595
1673
1779
1928
ps
tDIP
984
1661
1743
1853
2018
ps
tOP
940
1586
1664
1769
1917
ps
tDIP
962
1652
1734
1843
2007
ps
tOP
944
1591
1669
1775
1923
ps
tDIP
966
1657
1739
1849
2013
ps
tOP
936
1585
1663
1768
1916
ps
tDIP
958
1651
1733
1842
2006
ps
tOP
919
1385
1453
1545
1680
ps
tDIP
941
1451
1523
1619
1770
ps
tOP
921
1394
1462
1555
1691
ps
tDIP
943
1460
1532
1629
1781
ps
tOP
921
1402
1471
1564
1700
ps
tDIP
943
1468
1541
1638
1790
ps
tOP
956
1607
1686
1793
1942
ps
tDIP
978
1673
1756
1867
2032
ps
tOP
961
1588
1666
1772
1920
ps
tDIP
983
1654
1736
1846
2010
ps
tOP
943
1590
1668
1774
1922
ps
tDIP
965
1656
1738
1848
2012
ps
tOP
943
1592
1670
1776
1924
ps
tDIP
965
1658
1740
1850
2014
ps
tOP
937
1590
1668
1774
1922
ps
tDIP
959
1656
1738
1848
2012
ps
4–92
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–86. Stratix II GX I/O Output Delay for Column Pins (Part 5 of 7)
I/O Standard
1.5-V HSTL
Class II
Drive
Parameter
Strength
16 mA
18 mA
20 mA (1)
PCI
-
PCI-X
-
Differential SSTL2 Class I (2)
8 mA
12 mA
Differential
SSTL-2 Class II (2)
16 mA
20 mA
24 mA
Differential
SSTL-18 Class I
(2)
4 mA
6 mA
8 mA
10 mA
12 mA
Altera Corporation
June 2009
Fast Corner
-3 Speed
Industrial/
Grade (3)
Commercial
-3 Speed
Grade (4)
-4 Speed
Grade
-5 Speed
Grade
Unit
tOP
924
1431
1501
1596
1734
ps
tDIP
946
1497
1571
1670
1824
ps
tOP
927
1439
1510
1605
1744
ps
tDIP
949
1505
1580
1679
1834
ps
tOP
929
1450
1521
1618
1757
ps
tDIP
951
1516
1591
1692
1847
ps
tOP
1082
1956
2051
2176
2070
ps
tDIP
1104
2022
2121
2250
2160
ps
tOP
1082
1956
2051
2176
2070
ps
tDIP
1104
2022
2121
2250
2160
ps
tOP
957
1715
1799
1913
2041
ps
tDIP
979
1781
1869
1987
2131
ps
tOP
940
1672
1754
1865
1991
ps
tDIP
962
1738
1824
1939
2081
ps
tOP
918
1609
1688
1795
1918
ps
tDIP
940
1675
1758
1869
2008
ps
tOP
919
1598
1676
1783
1905
ps
tDIP
941
1664
1746
1857
1995
ps
tOP
915
1596
1674
1781
1903
ps
tDIP
937
1662
1744
1855
1993
ps
tOP
953
1690
1773
1886
2012
ps
tDIP
975
1756
1843
1960
2102
ps
tOP
958
1656
1737
1848
1973
ps
tDIP
980
1722
1807
1922
2063
ps
tOP
937
1640
1721
1830
1954
ps
tDIP
959
1706
1791
1904
2044
ps
tOP
942
1638
1718
1827
1952
ps
tDIP
964
1704
1788
1901
2042
ps
tOP
936
1626
1706
1814
1938
ps
tDIP
958
1692
1776
1888
2028
ps
4–93
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–86. Stratix II GX I/O Output Delay for Column Pins (Part 6 of 7)
I/O Standard
Differential
SSTL-18 Class II
(2)
Drive
Parameter
Strength
8 mA
16 mA
18 mA
20 mA
1.8-V differential
HSTL Class I (2)
4 mA
6 mA
8 mA
10 mA
12 mA
1.8-V differential
HSTL Class II (2)
16 mA
18 mA
20 mA
Fast Corner
-3 Speed
Industrial/
Grade (3)
Commercial
-3 Speed
Grade (4)
-4 Speed
Grade
-5 Speed
Grade
Unit
tOP
925
1597
1675
1782
1904
ps
tDIP
947
1663
1745
1856
1994
ps
tOP
937
1578
1655
1761
1882
ps
tDIP
959
1644
1725
1835
1972
ps
tOP
933
1585
1663
1768
1890
ps
tDIP
955
1651
1733
1842
1980
ps
tOP
933
1583
1661
1766
1888
ps
tDIP
955
1649
1731
1840
1978
ps
tOP
956
1608
1687
1794
1943
ps
tDIP
978
1674
1757
1868
2033
ps
tOP
962
1595
1673
1779
1928
ps
tDIP
984
1661
1743
1853
2018
ps
tOP
940
1586
1664
1769
1917
ps
tDIP
962
1652
1734
1843
2007
ps
tOP
944
1591
1669
1775
1923
ps
tDIP
966
1657
1739
1849
2013
ps
tOP
936
1585
1663
1768
1916
ps
tDIP
958
1651
1733
1842
2006
ps
tOP
919
1385
1453
1545
1680
ps
tDIP
941
1451
1523
1619
1770
ps
tOP
921
1394
1462
1555
1691
ps
tDIP
943
1460
1532
1629
1781
ps
tOP
921
1402
1471
1564
1700
ps
tDIP
943
1468
1541
1638
1790
ps
4–94
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–86. Stratix II GX I/O Output Delay for Column Pins (Part 7 of 7)
Drive
Parameter
Strength
I/O Standard
1.5-V differential
HSTL Class I (2)
4 mA
6 mA
8 mA
10 mA
12 mA
1.5-V differential
HSTL Class II (2)
16 mA
18 mA
20 mA
Fast Corner
-3 Speed
Industrial/
Grade (3)
Commercial
-3 Speed
Grade (4)
-4 Speed
Grade
-5 Speed
Grade
Unit
tOP
956
1607
1686
1793
1942
ps
tDIP
978
1673
1756
1867
2032
ps
tOP
961
1588
1666
1772
1920
ps
tDIP
983
1654
1736
1846
2010
ps
tOP
943
1590
1668
1774
1922
ps
tDIP
965
1656
1738
1848
2012
ps
tOP
943
1592
1670
1776
1924
ps
tDIP
965
1658
1740
1850
2014
ps
tOP
937
1590
1668
1774
1922
ps
tDIP
959
1656
1738
1848
2012
ps
tOP
924
1431
1501
1596
1734
ps
tDIP
946
1497
1571
1670
1824
ps
tOP
927
1439
1510
1605
1744
ps
tDIP
949
1505
1580
1679
1834
ps
tOP
929
1450
1521
1618
1757
ps
tDIP
951
1516
1591
1692
1847
ps
Notes to Table 4–86:
(1)
(2)
(3)
(4)
This is the default setting in the Quartus II software.
These I/O standards are only supported on DQS pins.
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Table 4–87. Stratix II GX I/O Output Delay for Row Pins (Part 1 of 4)
I/O Standard
Drive
Strength
Parameter
Fast Corner
Industrial/
Commercial
-3 Speed
Grade (3)
-3 Speed
Grade (4)
-4 Speed
Grade
4 mA
tOP
1328
2655
2786
2962
3189
ps
tDIP
1285
2600
2729
2902
3116
ps
tOP
1200
2113
2217
2357
2549
ps
tDIP
1157
2058
2160
2297
2476
ps
tOP
1144
2081
2184
2321
2512
ps
tDIP
1101
2026
2127
2261
2439
ps
LVTTL
8 mA
12 mA (1)
Altera Corporation
June 2009
-5 Speed
Unit
Grade
4–95
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–87. Stratix II GX I/O Output Delay for Row Pins (Part 2 of 4)
I/O Standard
LVCMOS
Drive
Strength
Parameter
Fast Corner
Industrial/
Commercial
-3 Speed
Grade (3)
-3 Speed
Grade (4)
-4 Speed
Grade
4 mA
tOP
1200
2113
2217
2357
2549
ps
tDIP
1157
2058
2160
2297
2476
ps
tOP
1094
1853
1944
2067
2243
ps
tDIP
1051
1798
1887
2007
2170
ps
8 mA (1)
12 mA (1)
2.5 V
4 mA
8 mA
12 mA (1)
1.8 V
2 mA
4 mA
6 mA
8 mA (1)
1.5 V
2 mA
4 mA (1)
SSTL-2 Class I
8 mA
12 mA (1)
SSTL-2 Class II 16 mA (1)
-5 Speed
Unit
Grade
tOP
1061
1723
1808
1922
2089
ps
tDIP
1018
1668
1751
1862
2016
ps
tOP
1183
2091
2194
2332
2523
ps
tDIP
1140
2036
2137
2272
2450
ps
tOP
1080
1872
1964
2088
2265
ps
tDIP
1037
1817
1907
2028
2192
ps
tOP
1061
1775
1862
1980
2151
ps
tDIP
1018
1720
1805
1920
2078
ps
tOP
1253
2954
3100
3296
3542
ps
tDIP
1210
2899
3043
3236
3469
ps
tOP
1242
2294
2407
2559
2763
ps
tDIP
1199
2239
2350
2499
2690
ps
tOP
1131
2039
2140
2274
2462
ps
tDIP
1088
1984
2083
2214
2389
ps
tOP
1100
1942
2038
2166
2348
ps
tDIP
1057
1887
1981
2106
2275
ps
tOP
1213
2530
2655
2823
3041
ps
tDIP
1170
2475
2598
2763
2968
ps
tOP
1106
2020
2120
2253
2440
ps
tDIP
1063
1965
2063
2193
2367
ps
tOP
1050
1759
1846
1962
2104
ps
tDIP
1007
1704
1789
1902
2031
ps
tOP
1026
1694
1777
1889
2028
ps
tDIP
983
1639
1720
1829
1955
ps
tOP
992
1581
1659
1763
1897
ps
tDIP
949
1526
1602
1703
1824
ps
4–96
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–87. Stratix II GX I/O Output Delay for Row Pins (Part 3 of 4)
I/O Standard
Drive
Strength
Parameter
Fast Corner
Industrial/
Commercial
-3 Speed
Grade (3)
-3 Speed
Grade (4)
-4 Speed
Grade
4 mA
tOP
1038
1709
1793
1906
2046
ps
tDIP
995
1654
1736
1846
1973
ps
tOP
1042
1648
1729
1838
1975
ps
tDIP
999
1593
1672
1778
1902
ps
SSTL-18
Class I
6 mA
8 mA
10 mA (1)
1.8-V HSTL
Class I
4 mA
6 mA
8 mA
10 mA
12 mA (1)
1.5-V HSTL
Class I
4 mA
6 mA
8 mA (1)
Differential
SSTL-2 Class I
8 mA
12 mA
Differential
SSTL-2 Class II
Altera Corporation
June 2009
16 mA
-5 Speed
Unit
Grade
tOP
1018
1633
1713
1821
1958
ps
tDIP
975
1578
1656
1761
1885
ps
tOP
1021
1615
1694
1801
1937
ps
tDIP
978
1560
1637
1741
1864
ps
tOP
1019
1610
1689
1795
1956
ps
tDIP
976
1555
1632
1735
1883
ps
tOP
1022
1580
1658
1762
1920
ps
tDIP
979
1525
1601
1702
1847
ps
tOP
1004
1576
1653
1757
1916
ps
tDIP
961
1521
1596
1697
1843
ps
tOP
1008
1567
1644
1747
1905
ps
tDIP
965
1512
1587
1687
1832
ps
tOP
999
1566
1643
1746
1904
ps
tDIP
956
1511
1586
1686
1831
ps
tOP
1018
1591
1669
1774
1933
ps
tDIP
975
1536
1612
1714
1860
ps
tOP
1021
1579
1657
1761
1919
ps
tDIP
978
1524
1600
1701
1846
ps
tOP
1006
1572
1649
1753
1911
ps
tDIP
963
1517
1592
1693
1838
ps
tOP
1050
1759
1846
1962
2104
ps
tDIP
1007
1704
1789
1902
2031
ps
tOP
1026
1694
1777
1889
2028
ps
tDIP
983
1639
1720
1829
1955
ps
tOP
992
1581
1659
1763
1897
ps
tDIP
949
1526
1602
1703
1824
ps
4–97
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–87. Stratix II GX I/O Output Delay for Row Pins (Part 4 of 4)
I/O Standard
Drive
Strength
Parameter
Fast Corner
Industrial/
Commercial
-3 Speed
Grade (3)
-3 Speed
Grade (4)
-4 Speed
Grade
4 mA
tOP
1038
1709
1793
1906
2046
ps
tDIP
995
1654
1736
1846
1973
ps
tOP
1042
1648
1729
1838
1975
ps
tDIP
999
1593
1672
1778
1902
ps
Differential
SSTL-18 Class I
6 mA
8 mA
10 mA
LVDS (2)
HyperTransport
-
-
-5 Speed
Unit
Grade
tOP
1018
1633
1713
1821
1958
ps
tDIP
975
1578
1656
1761
1885
ps
tOP
1021
1615
1694
1801
1937
ps
tDIP
978
1560
1637
1741
1864
ps
tOP
1067
1723
1808
1922
2089
ps
tDIP
1024
1668
1751
1862
2016
ps
tOP
1053
1723
1808
1922
2089
ps
tDIP
1010
1668
1751
1862
2016
ps
Notes to Table 4–87:
(1)
(2)
(3)
(4)
This is the default setting in the Quartus II software.
The parameters are only available on the left side of the device.
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Maximum Input and Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Tables 4–88 through 4–90 specify the maximum input clock toggle rates.
Tables 4–91 through 4–96 specify the maximum output clock toggle rates
at 0 pF load. Table 4–97 specifies the derating factors for the output clock
toggle rate for a non 0 pF load.
4–98
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
To calculate the output toggle rate for a non 0 pF load, use this formula:
The toggle rate for a non 0 pF load
= 1,000 / (1,000/ toggle rate at 0 pF load + derating factor × load
value in pF /1,000)
For example, the output toggle rate at 0 pF load for SSTL-18 Class II
20 mA I/O standard is 550 MHz on a -3 device clock output pin. The
derating factor is 94 ps/pF. For a 10 pF load the toggle rate is calculated
as:
1,000 / (1,000/550 + 94 × 10 /1,000) = 363 (MHz)
Table 4–88 shows the maximum input clock toggle rates for Stratix II GX
device column pins.
Table 4–88. Stratix II GX Maximum Input Clock Rate for Column I/O Pins (Part 1 of 2)
I/O Standard
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
LVTTL
500
500
450
MHz
2.5 V
500
500
450
MHz
1.8 V
500
500
450
MHz
1.5 V
500
500
450
MHz
LVCMOS
500
500
450
MHz
SSTL-2 Class I
500
500
500
MHz
SSTL-2 Class II
500
500
500
MHz
SSTL-18 Class I
500
500
500
MHz
SSTL-18 Class I I
500
500
500
MHz
1.5-V HSTL Class I
500
500
500
MHz
1.5-V HSTL Class I I
500
500
500
MHz
1.8-V HSTL Class I
500
500
500
MHz
1.8-V HSTL Class II
500
500
500
MHz
PCI
500
500
450
MHz
PCI-X
500
500
450
MHz
Differential SSTL-2
Class I
500
500
500
MHz
Differential SSTL-2
Class II
500
500
500
MHz
Differential SSTL-18
Class I
500
500
500
MHz
Altera Corporation
June 2009
4–99
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–88. Stratix II GX Maximum Input Clock Rate for Column I/O Pins (Part 2 of 2)
I/O Standard
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
Differential SSTL-18
Class I I
500
500
500
MHz
1.8-V differential
HSTL Class I
500
500
500
MHz
1.8-V differential
HSTL Class II
500
500
500
MHz
1.5-V differential
HSTL Class I
500
500
500
MHz
1.5-V differential
HSTL Class I I
500
500
500
MHz
1.2-V HSTL
280
250
250
MHz
1.2-V differential
HSTL
280
250
250
MHz
Table 4–89 shows the maximum input clock toggle rates for Stratix II GX
device row pins.
Table 4–89. Stratix II GX Maximum Input Clock Rate for Row I/O Pins (Part 1 of 2)
I/O Standard
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
LVTTL
500
500
450
MHz
2.5 V
500
500
450
MHz
1.8 V
500
500
450
MHz
1.5 V
500
500
450
MHz
LVCMOS
500
500
450
MHz
SSTL-2 Class I
500
500
500
MHz
SSTL-2 Class II
500
500
500
MHz
SSTL-18 Class I
500
500
500
MHz
SSTL-18 Class II
500
500
500
MHz
1.5-V HSTL Class I
500
500
500
MHz
1.5-V HSTL Class II
500
500
500
MHz
1.8-V HSTL Class I
500
500
500
MHz
1.8-V HSTL Class II
500
500
500
MHz
PCI
500
500
425
MHz
PCI-X
500
500
425
MHz
Differential SSTL-2
Class I
500
500
500
MHz
4–100
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–89. Stratix II GX Maximum Input Clock Rate for Row I/O Pins (Part 2 of 2)
I/O Standard
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
Differential SSTL-2
Class II
500
500
500
MHz
Differential SSTL-18
Class I
500
500
500
MHz
Differential SSTL-18
Class I I
500
500
500
MHz
1.8-V differential
HSTL Class I
500
500
500
MHz
1.8-V differential
HSTL Class I I
500
500
500
MHz
1.5-V differential
HSTL Class I
500
500
500
MHz
1.5-V differential
HSTL Class II
500
500
500
MHz
LVDS (1)
520
520
420
MHz
HyperTransport
520
520
420
MHz
Note to Table 4–89:
(1)
The parameters are only available on the left side of the device.
Table 4–90 shows the maximum input clock toggle rates for Stratix II GX
device dedicated clock pins.
Table 4–90. Stratix II GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 1 of 2)
I/O Standard
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
LVTTL
500
500
400
MHz
2.5 V
500
500
400
MHz
1.8 V
500
500
400
MHz
1.5 V
500
500
400
MHz
LVCMOS
500
500
400
MHz
SSTL-2 Class I
500
500
500
MHz
SSTL-2 Class II
500
500
500
MHz
SSTL-18 Class I
500
500
500
MHz
SSTL-18 Class II
500
500
500
MHz
1.5-V HSTL Class I
500
500
500
MHz
1.5-V HSTL Class II
500
500
500
MHz
1.8-V HSTL CLass I
500
500
500
MHz
Altera Corporation
June 2009
4–101
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–90. Stratix II GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 2 of 2)
I/O Standard
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
1.8-V HSTL CLass I
500
500
500
MHz
PCI
500
500
400
MHz
PCI-X
500
500
400
MHz
Differential SSTL-2
Class I
500
500
500
MHz
Differential SSTL-2
Class II
500
500
500
MHz
Differential SSTL-18
Class I
500
500
500
MHz
Differential SSTL-18
Class II
500
500
500
MHz
1.8-V differential
HSTL Class I
500
500
500
MHz
1.8-V differential
HSTL Class II
500
500
500
MHz
1.5-V differential
HSTL Class I
500
500
500
MHz
1.5-V differential
HSTL Class I I
500
500
500
MHz
HyperTransport (1)
LVPECL (1), (2)
LVDS (1)
717
717
640
MHz
450
450
400
MHz
717
717
640
MHz
450
450
400
MHz
717
717
640
MHz
450
450
400
MHz
Notes to Table 4–90:
(1)
(2)
The first set of numbers refers to the HIO dedicated clock pins. The second set of numbers refers to the VIO
dedicated clock pins.
LVPECL is only supported on column clock pins.
4–102
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–91 shows the maximum output clock toggle rates for Stratix II GX
device column pins.
Table 4–91. Stratix II GX Maximum Output Clock Rate for Column Pins (Part 1 of 3)
I/O Standard
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 Class I
SSTL-2 Class II
Altera Corporation
June 2009
Drive Strength
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
4 mA
270
225
210
MHz
8 mA
435
355
325
MHz
12 mA
580
475
420
MHz
16 mA
720
594
520
MHz
20 mA
875
700
610
MHz
24 mA (1)
1030
794
670
MHz
4 mA
290
250
230
MHz
8 mA
565
480
440
MHz
12 mA
790
710
670
MHz
16 mA
1020
925
875
MHz
20 mA
1066
985
935
MHz
24 mA (1)
1100
1040
1000
MHz
4 mA
230
194
180
MHz
8 mA
430
380
380
MHz
12 mA
630
575
550
MHz
16 mA (1)
930
845
820
MHz
2 mA
120
109
104
MHz
4 mA
285
250
230
MHz
6 mA
450
390
360
MHz
8 mA
660
570
520
MHz
10 mA
905
805
755
MHz
12 mA (1)
1131
1040
990
MHz
2 mA
244
200
180
MHz
4 mA
470
370
325
MHz
6 mA
550
430
375
MHz
8 mA (1)
625
495
420
MHz
8 mA
400
300
300
MHz
12 mA (1)
400
400
350
MHz
16 mA
350
350
300
MHz
20 mA
400
350
350
MHz
24 mA (1)
400
400
350
MHz
4–103
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–91. Stratix II GX Maximum Output Clock Rate for Column Pins (Part 2 of 3)
I/O Standard
Drive Strength
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
SSTL-18 Class I
4 mA
200
150
150
MHz
6 mA
350
250
200
MHz
8 mA
450
300
300
MHz
10 mA
500
400
400
MHz
12 mA (1)
700
550
400
MHz
SSTL-18 Class II
1.8-V HSTL
Class I
1.8-V HSTL
Class II
1.5-V HSTL
Class I
1.5-V HSTL
Class II
8 mA
200
200
150
MHz
16 mA
400
350
350
MHz
18 mA
450
400
400
MHz
20 mA (1)
550
500
450
MHz
4 mA
300
300
300
MHz
6 mA
500
450
450
MHz
8 mA
650
600
600
MHz
10 mA
700
650
600
MHz
12 mA (1)
700
700
650
MHz
16 mA
500
500
450
MHz
18 mA
550
500
500
MHz
20 mA (1)
650
550
550
MHz
4 mA
350
300
300
MHz
6 mA
500
500
450
MHz
8 mA
700
650
600
MHz
10 mA
700
700
650
MHz
12 mA (1)
700
700
700
MHz
16 mA
600
600
550
MHz
18 mA
650
600
600
MHz
20 mA (1)
700
650
600
MHz
PCI
-
1000
790
670
MHz
PCI-X
-
1000
790
670
MHz
Differential
SSTL-2 Class I
Differential
SSTL-2 Class II
8 mA
400
300
300
MHz
12 mA
400
400
350
MHz
16 mA
350
350
300
MHz
20 mA
400
350
350
MHz
24 mA
400
400
350
MHz
4–104
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–91. Stratix II GX Maximum Output Clock Rate for Column Pins (Part 3 of 3)
I/O Standard
Drive Strength
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
Differential
SSTL-18 Class I
4 mA
200
150
150
MHz
6 mA
350
250
200
MHz
8 mA
450
300
300
MHz
10 mA
500
400
400
MHz
12 mA
700
550
400
MHz
Differential
SSTL-18 Class II
1.8-V HSTL
differential
Class I
1.8-V HSTL
differential
Class II
1.5-V HSTL
differential
Class I
1.5-V HSTL
differential
Class II
8 mA
200
200
150
MHz
16 mA
400
350
350
MHz
18 mA
450
400
400
MHz
20 mA
550
500
450
MHz
4 mA
300
300
300
MHz
6 mA
500
450
450
MHz
8 mA
650
600
600
MHz
10 mA
700
650
600
MHz
12 mA
700
700
650
MHz
16 mA
500
500
450
MHz
18 mA
550
500
500
MHz
20 mA
650
550
550
MHz
4 mA
350
300
300
MHz
6 mA
500
500
450
MHz
8 mA
700
650
600
MHz
10 mA
700
700
650
MHz
12 mA
700
700
700
MHz
16 mA
600
600
550
MHz
18 mA
650
600
600
MHz
20 mA
700
650
600
MHz
Note to Table 4–91:
(1)
This is the default setting in the Quartus II software.
Altera Corporation
June 2009
4–105
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–92 shows the maximum output clock toggle rates for Stratix II GX
device row pins.
Table 4–92. Stratix II GX Maximum Output Clock Rate for Row Pins (Part 1 of 2)
I/O Standard
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL
Class I
1.5-V HSTL
Class I
Drive Strength
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
4 mA
270
225
210
MHz
8 mA
435
355
325
MHz
12 mA (1)
580
475
420
MHz
4 mA
290
250
230
MHz
8 mA
565
480
440
MHz
12 mA (1)
350
350
297
MHz
4 mA
230
194
180
MHz
8 mA
430
380
380
MHz
12 mA (1)
630
575
550
MHz
2 mA
120
109
104
MHz
4 mA
285
250
230
MHz
6 mA
450
390
360
MHz
8 mA (1)
660
570
520
MHz
2 mA
244
200
180
MHz
4 mA (1)
470
370
325
MHz
8 mA
400
300
300
MHz
12 mA (1)
400
400
350
MHz
16 mA
350
350
300
MHz
20 mA (1)
350
350
297
MHz
4 mA
200
150
150
MHz
6 mA
350
250
200
MHz
8 mA
450
300
300
MHz
10 mA
500
400
400
MHz
12 mA (1)
350
350
297
MHz
4 mA
300
300
300
MHz
6 mA
500
450
450
MHz
8 mA
650
600
600
MHz
10 mA
700
650
600
MHz
12 mA (1)
700
700
650
MHz
4 mA
350
300
300
MHz
6 mA
500
500
450
MHz
8 mA (1)
700
650
600
MHz
4–106
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–92. Stratix II GX Maximum Output Clock Rate for Row Pins (Part 2 of 2)
I/O Standard
Differential
SSTL-2 Class I
Drive Strength
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
8 mA
400
300
300
MHz
12 mA
400
400
350
MHz
Differential
SSTL-2 Class II
16 mA (1)
350
350
300
MHz
Differential
SSTL-18 Class I
4 mA
200
150
150
MHz
6 mA
350
250
200
MHz
8 mA
450
300
300
MHz
10 mA (1)
500
400
400
MHz
LVDS
-
717
717
640
MHz
HyperTransport
-
717
717
640
MHz
Note to Table 4–92:
(1)
This is the default setting in Quartus II software.
Table 4–93 shows the maximum output clock toggle rate for Stratix II GX
device dedicated clock pins.
Table 4–93. Stratix II GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 1 of 4)
I/O Standard
LVTTL
LVCMOS
Altera Corporation
June 2009
Drive Strength
-3 Speed
Grade
-4 Speed
Grade
-5 Speed
Grade
4 mA
270
225
210
MHz
Unit
8 mA
435
355
325
MHz
12 mA
580
475
420
MHz
16 mA
720
594
520
MHz
20 mA
875
700
610
MHz
24 mA (1)
1030
794
670
MHz
4 mA
290
250
230
MHz
8 mA
565
480
440
MHz
12 mA
790
710
670
MHz
16 mA
1020
925
875
MHz
20 mA
1066
985
935
MHz
24 mA (1)
1100
1040
1000
MHz
4–107
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–93. Stratix II GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 2 of 4)
I/O Standard
2.5 V
1.8 V
1.5 V
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
Drive Strength
-3 Speed
Grade
-4 Speed
Grade
-5 Speed
Grade
Unit
4 mA
230
194
180
MHz
8 mA
430
380
380
MHz
12 mA
630
575
550
MHz
16 mA (1)
930
845
820
MHz
2 mA
120
109
104
MHz
4 mA
285
250
230
MHz
6 mA
450
390
360
MHz
8 mA
660
570
520
MHz
10 mA
905
805
755
MHz
12 mA (1)
1131
1040
990
MHz
2 mA
244
200
180
MHz
4 mA
470
370
325
MHz
6 mA
550
430
375
MHz
8 mA (1)
625
495
420
MHz
8 mA
400
300
300
MHz
12 mA (1)
400
400
350
MHz
16 mA
350
350
300
MHz
20 mA
400
350
350
MHz
24 mA (1)
400
400
350
MHz
4 mA
200
150
150
MHz
6 mA
350
250
200
MHz
8 mA
450
300
300
MHz
10 mA
500
400
400
MHz
12 mA (1)
650
550
400
MHz
8 mA
200
200
150
MHz
16 mA
400
350
350
MHz
18 mA
450
400
400
MHz
20 mA (1)
550
500
450
MHz
4 mA
300
300
300
MHz
6 mA
500
450
450
MHz
8 mA
650
600
600
MHz
10 mA
700
650
600
MHz
12 mA (1)
700
700
650
MHz
4–108
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–93. Stratix II GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 3 of 4)
I/O Standard
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
Drive Strength
-3 Speed
Grade
-4 Speed
Grade
-5 Speed
Grade
Unit
16 mA
500
500
450
MHz
18 mA
550
500
500
MHz
20 mA (1)
550
550
550
MHz
4 mA
350
300
300
MHz
6 mA
500
500
450
MHz
8 mA
700
650
600
MHz
10 mA
700
700
650
MHz
12 mA (1)
700
700
700
MHz
16 mA
600
600
550
MHz
18 mA
650
600
600
MHz
20 mA (1)
700
650
600
MHz
PCI
-
1000
790
670
MHz
PCI-X
-
1000
790
670
MHz
Differential SSTL-2
Class I
Differential SSTL-2
Class II
Differential SSTL-18
Class I
Differential SSTL-18
Class II
1.8-V differential Class I
Altera Corporation
June 2009
8 mA
400
300
300
MHz
12 mA
400
400
350
MHz
16 mA
350
350
300
MHz
20 mA
400
350
350
MHz
24 mA
400
400
350
MHz
4 mA
200
150
150
MHz
6 mA
350
250
200
MHz
8 mA
450
300
300
MHz
10 mA
500
400
400
MHz
12 mA
650
550
400
MHz
8 mA
200
200
150
MHz
16 mA
400
350
350
MHz
18 mA
450
400
400
MHz
20 mA
550
500
450
MHz
4 mA
300
300
300
MHz
6 mA
500
450
450
MHz
8 mA
650
600
600
MHz
10 mA
700
650
600
MHz
12 mA
700
700
650
MHz
4–109
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–93. Stratix II GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 4 of 4)
I/O Standard
1.8-V differential
Class II
1.5-V differential Class I
1.5-V differential
Class II
Drive Strength
-3 Speed
Grade
-4 Speed
Grade
-5 Speed
Grade
Unit
16 mA
500
500
450
MHz
18 mA
550
500
500
MHz
20 mA
550
550
550
MHz
4 mA
350
300
300
MHz
6 mA
500
500
450
MHz
8 mA
700
650
600
MHz
10 mA
700
700
650
MHz
12 mA
700
700
700
MHz
16 mA
600
600
550
MHz
18 mA
650
600
600
MHz
20 mA
700
650
600
MHz
HyperTransport
-
300
250
125
MHz
LVPECL
-
450
400
300
MHz
Note to Table 4–93:
(1)
This is the default setting in Quartus II software.
Table 4–94 shows the maximum output clock toggle rate for Stratix II GX
device series-terminated column pins.
Table 4–94. Stratix II GX Maximum Output Clock Rate for Column Pins (Series Termination) (Part 1
of 2)
I/O Standard
Drive Strength
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
LVTTL
OCT_25_OHMS
400
400
350
MHz
OCT_50_OHMS
400
400
350
MHz
LVCMOS
OCT_25_OHMS
350
350
300
MHz
OCT_50_OHMS
350
350
300
MHz
OCT_25_OHMS
350
350
300
MHz
OCT_50_OHMS
350
350
300
MHz
OCT_25_OHMS
700
550
450
MHz
2.5 V
1.8 V
OCT_50_OHMS
700
550
450
MHz
1.5 V
OCT_50_OHMS
550
450
400
MHz
SSTL-2 Class I
OCT_50_OHMS
600
500
500
MHz
SSTL-2 Class II
OCT_25_OHMS
600
550
500
MHz
4–110
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–94. Stratix II GX Maximum Output Clock Rate for Column Pins (Series Termination) (Part 2
of 2)
I/O Standard
Drive Strength
SSTL-18 Class I OCT_50_OHMS
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
560
400
350
MHz
SSTL-18 Class II OCT_25_OHMS
550
500
450
MHz
1.5-V HSTL
Class I
OCT_50_OHMS
600
550
500
MHz
1.8-V HSTL
Class I
OCT_50_OHMS
650
600
600
MHz
1.8-V HSTL
Class II
OCT_25_OHMS
500
500
450
MHz
Differential
SSTL-2 Class I
OCT_50_OHMS
600
500
500
MHz
Differential
SSTL-2 Class II
OCT_25_OHMS
600
550
500
MHz
Differential
OCT_50_OHMS
SSTL-18 Class I
560
400
350
MHz
Differential
OCT_25_OHMS
SSTL-18 Class II
550
500
450
MHz
1.8-V differential
HSTL Class I
OCT_50_OHMS
650
600
600
MHz
1.8-V differential
HSTL Class II
OCT_25_OHMS
500
500
450
MHz
1.5-V differential
HSTL Class I
OCT_50_OHMS
600
550
500
MHz
Table 4–95 shows the maximum output clock toggle rate for Stratix II GX
device series-terminated row pins.
Table 4–95. Stratix II GX Maximum Output Clock Rate for Row Pins (Series Termination) (Part 1 of 2)
I/O Standard
LVTTL
LVCMOS
2.5 V
Drive Strength
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
OCT_25_OHMS
400
400
350
MHz
OCT_50_OHMS
400
400
350
MHz
OCT_25_OHMS
350
350
300
MHz
OCT_50_OHMS
350
350
300
MHz
OCT_25_OHMS
350
350
300
MHz
OCT_50_OHMS
350
350
300
MHz
1.8 V
OCT_50_OHMS
700
550
450
MHz
1.5 V
OCT_50_OHMS
550
450
400
MHz
Altera Corporation
June 2009
4–111
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–95. Stratix II GX Maximum Output Clock Rate for Row Pins (Series Termination) (Part 2 of 2)
I/O Standard
Drive Strength
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
SSTL-2 Class I
OCT_50_OHMS
600
500
500
MHz
SSTL-2 Class II
OCT_25_OHMS
600
550
500
MHz
SSTL-18 Class I OCT_50_OHMS
590
400
350
MHz
1.5-V HSTL
Class I
OCT_50_OHMS
600
550
500
MHz
1.8-V HSTL
Class I
OCT_50_OHMS
650
600
600
MHz
Differential
SSTL-2 Class I
OCT_50_OHMS
600
500
500
MHz
Differential
SSTL-2 Class II
OCT_25_OHMS
600
550
500
MHz
Differential
OCT_50_OHMS
SSTL-18 Class I
590
400
350
MHz
Differential
OCT_50_OHMS
HSTL-18 Class I
650
600
600
MHz
Differential
OCT_50_OHMS
HSTL-15 Class I
600
550
500
Table 4–96 shows the maximum output clock toggle rate for Stratix II GX
device series-terminated dedicated clock pins.
Table 4–96. Stratix II GX Maximum Output Clock Rate for Dedicated Clock Pins (Series Termination) (Part
1 of 2)
I/O Standard
Drive Strength
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
LVTTL
OCT_25_OHMS
400
400
350
MHz
OCT_50_OHMS
400
400
350
MHz
LVCMOS
OCT_25_OHMS
350
350
300
MHz
OCT_50_OHMS
350
350
300
MHz
OCT_25_OHMS
350
350
300
MHz
OCT_50_OHMS
350
350
300
MHz
OCT_25_OHMS
700
550
450
MHz
2.5 V
1.8 V
OCT_50_OHMS
700
550
450
MHz
1.5 V
OCT_50_OHMS
550
450
400
MHz
SSTL-2 Class I
OCT_50_OHMS
600
500
500
MHz
SSTL-2 Class II
OCT_25_OHMS
600
550
500
MHz
SSTL-18 Class I OCT_50_OHMS
450
400
350
MHz
4–112
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–96. Stratix II GX Maximum Output Clock Rate for Dedicated Clock Pins (Series Termination) (Part
2 of 2)
I/O Standard
Drive Strength
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Unit
SSTL-18 Class II OCT_25_OHMS
550
500
450
MHz
1.5-V HSTL
Class I
OCT_50_OHMS
600
550
500
MHz
1.8-V HSTL
Class I
OCT_50_OHMS
650
600
600
MHz
1.8-V HSTL
Class II
OCT_25_OHMS
500
500
450
MHz
DIfferential
SSTL-2 Class I
OCT_50_OHMS
600
500
500
MHz
DIfferential
SSTL-2 Class II
OCT_25_OHMS
600
550
500
MHz
DIfferential
OCT_50_OHMS
SSTL-18 Class I
560
400
350
MHz
DIfferential
OCT_25_OHMS
SSTL-18 Class II
550
500
450
MHz
1.8-V differential
HSTL Class I
OCT_50_OHMS
650
600
600
MHz
1.8-V differential
HSTL Class II
OCT_25_OHMS
500
500
450
MHz
1.5-V differential
HSTL Class I
OCT_50_OHMS
600
550
500
MHz
Table 4–97 specifies the derating factors for the output clock toggle rate
for a non 0 pF load.
Table 4–97. Maximum Output Clock Toggle Rate Derating Factors (Part 1 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
Drive
Strength
Column I/O Pins
-3
3.3-V LVTTL
Altera Corporation
June 2009
Dedicated Clock
Outputs
Row I/O Pins
-4
-5
-3
-4
-5
-3
-4
-5
4 mA
478
510
510
478
510
510
466
510
510
8 mA
260
333
333
260
333
333
291
333
333
12 mA
213
247
247
213
247
247
211
247
247
16 mA
136
197
197
-
-
-
166
197
197
20 mA
138
187
187
-
-
-
154
187
187
24 mA
134
177
177
-
-
-
143
177
177
4–113
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–97. Maximum Output Clock Toggle Rate Derating Factors (Part 2 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
3.3-V LVCMOS
2.5-V LVTTL/
LVCMOS
1.8-V LVTTL/
LVCMOS
1.5-V LVTTL/
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
Drive
Strength
4 mA
Column I/O Pins
Dedicated Clock
Outputs
Row I/O Pins
-3
-4
-5
-3
-4
-5
-3
-4
-5
377
391
391
377
391
391
377
391
391
8 mA
206
212
212
206
212
212
178
212
212
12 mA
141
145
145
-
-
-
115
145
145
16 mA
108
111
111
-
-
-
86
111
111
20 mA
83
88
88
-
-
-
79
88
88
24 mA
65
72
72
-
-
-
74
72
72
4 mA
387
427
427
387
427
427
391
427
427
8 mA
163
224
224
163
224
224
170
224
224
12 mA
142
203
203
142
203
203
152
203
203
16 mA
120
182
182
-
-
-
134
182
182
2 mA
951
1,421
1,421
951
1,421
1,421
904
1,421
1,421
4 mA
405
516
516
405
516
516
393
516
516
6 mA
261
325
325
261
325
325
253
325
325
8 mA
223
274
274
223
274
274
224
274
274
10 mA
194
236
236
-
-
-
199
236
236
12 mA
174
209
209
-
-
-
180
209
209
2 mA
652
963
963
652
963
963
618
963
963
4 mA
333
347
347
333
347
347
270
347
347
6 mA
182
247
247
-
-
-
198
247
247
8 mA
135
194
194
-
-
-
155
194
194
8 mA
364
680
680
364
680
680
350
680
680
12 mA
163
207
207
163
207
207
188
207
207
16 mA
118
147
147
118
147
147
94
147
147
20 mA
99
122
122
-
-
-
87
122
122
24 mA
91
116
116
-
-
-
85
116
116
4 mA
458
570
570
458
570
570
505
570
570
6 mA
305
380
380
305
380
380
336
380
380
8 mA
225
282
282
225
282
282
248
282
282
10 mA
167
220
220
167
220
220
190
220
220
12 mA
129
175
175
-
-
-
148
175
175
4–114
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–97. Maximum Output Clock Toggle Rate Derating Factors (Part 3 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
SSTL-18 Class II
2.5-V SSTL-2
Class I
2.5-V SSTL-2
Class II
1.8-V SSTL-18
Class I
1.8-V SSTL-18
Class II
1.8-V HSTL Class I
1.8-V HSTL
Class II
1.5-V HSTL Class I
Altera Corporation
June 2009
Drive
Strength
Column I/O Pins
Dedicated Clock
Outputs
Row I/O Pins
-3
-4
-5
-3
-4
-5
-3
-4
-5
8 mA
173
206
206
-
-
-
155
206
206
16 mA
150
160
160
-
-
-
140
160
160
18 mA
120
130
130
-
-
-
110
130
130
20 mA
109
127
127
-
-
-
94
127
127
8 mA
364
680
680
364
680
680
350
680
680
12 mA
163
207
207
163
207
207
188
207
207
16 mA
118
147
147
118
147
147
94
147
147
20 mA
99
122
122
-
-
-
87
122
122
24 mA
91
116
116
-
-
-
85
116
116
4 mA
458
570
570
458
570
570
505
570
570
6 mA
305
380
380
305
380
380
336
380
380
8 mA
225
282
282
225
282
282
248
282
282
10 mA
167
220
220
167
220
220
190
220
220
12 mA
129
175
175
-
-
-
148
175
175
8 mA
173
206
206
-
-
-
155
206
206
16 mA
150
160
160
-
-
-
140
160
160
18 mA
120
130
130
-
-
-
110
130
130
20 mA
109
127
127
-
-
-
94
127
127
4 mA
245
282
282
245
282
282
229
282
282
6 mA
164
188
188
164
188
188
153
188
188
8 mA
123
140
140
123
140
140
114
140
140
10 mA
110
124
124
110
124
124
108
124
124
12 mA
97
110
110
97
110
110
104
110
110
16 mA
101
104
104
-
-
-
99
104
104
18 mA
98
102
102
-
-
-
93
102
102
20 mA
93
99
99
-
-
-
88
99
99
4 mA
168
196
196
168
196
196
188
196
196
6 mA
112
131
131
112
131
131
125
131
131
8 mA
84
99
99
84
99
99
95
99
99
10 mA
87
98
98
-
-
-
90
98
98
12 mA
86
98
98
-
-
-
87
98
98
4–115
Stratix II GX Device Handbook, Volume 1
Timing Model
Table 4–97. Maximum Output Clock Toggle Rate Derating Factors (Part 4 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
1.5-V HSTL
Class II
2.5-V differential
SSTL Class II (3)
1.8-V differential
SSTL Class I (3)
1.8-V differential
SSTL Class II (3)
1.8-V differential
HSTL Class I (3)
1.8-V differential
HSTL Class II (3)
1.5-V differential
HSTL Class I (3)
Drive
Strength
Column I/O Pins
Dedicated Clock
Outputs
Row I/O Pins
-3
-4
-5
-3
-4
-5
-3
-4
-5
16 mA
95
101
101
-
-
-
96
101
101
18 mA
95
100
100
-
-
-
101
100
100
20 mA
94
101
101
-
-
-
104
101
101
8 mA
364
680
680
-
-
-
350
680
680
12 mA
163
207
207
-
-
-
188
207
207
16 mA
118
147
147
-
-
-
94
147
147
20 mA
99
122
122
-
-
-
87
122
122
24 mA
91
116
116
-
-
-
85
116
116
4 mA
458
570
570
-
-
-
505
570
570
6 mA
305
380
380
-
-
-
336
380
380
8 mA
225
282
282
-
-
-
248
282
282
10 mA
167
220
220
-
-
-
190
220
220
12 mA
129
175
175
-
-
-
148
175
175
8 mA
173
206
206
-
-
-
155
206
206
16 mA
150
160
160
-
-
-
140
160
160
18 mA
120
130
130
-
-
-
110
130
130
20 mA
109
127
127
-
-
-
94
127
127
4 mA
245
282
282
-
-
-
229
282
282
6 mA
164
188
188
-
-
-
153
188
188
8 mA
123
140
140
-
-
-
114
140
140
10 mA
110
124
124
-
-
-
108
124
124
12 mA
97
110
110
-
-
-
104
110
110
16 mA
101
104
104
-
-
-
99
104
104
18 mA
98
102
102
-
-
-
93
102
102
20 mA
93
99
99
-
-
-
88
99
99
4 mA
168
196
196
-
-
-
188
196
196
6 mA
112
131
131
-
-
-
125
131
131
8 mA
84
99
99
-
-
-
95
99
99
10 mA
87
98
98
-
-
-
90
98
98
12 mA
86
98
98
-
-
-
87
98
98
4–116
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–97. Maximum Output Clock Toggle Rate Derating Factors (Part 5 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
1.5-V differential
HSTL Class II (3)
Drive
Strength
Column I/O Pins
Dedicated Clock
Outputs
Row I/O Pins
-3
-4
-5
-3
-4
-5
-3
-4
-5
16 mA
95
101
101
-
-
-
96
101
101
18 mA
95
100
100
-
-
-
101
100
100
20 mA
94
101
101
-
-
-
104
101
101
3.3-V PCI
134
177
177
-
-
-
143
177
177
3.3-V PCI-X
134
177
177
-
-
-
143
177
177
-
-
-
155 (1)
155
(1)
155
(1)
134
134
134
LVDS
LVPECL (4)
3.3-V LVTTL
OCT 50 Ω
-
-
-
-
-
-
134
134
134
133
152
152
133
152
152
147
152
152
2.5-V LVTTL
OCT 50 Ω
207
274
274
207
274
274
235
274
274
1.8-V LVTTL
OCT 50 Ω
151
165
165
151
165
165
153
165
165
3.3-V LVCMOS
OCT 50 Ω
300
316
316
300
316
316
263
316
316
1.5-V LVCMOS
OCT 50 Ω
157
171
171
157
171
171
174
171
171
SSTL-2 Class I
OCT 50 Ω
121
134
134
121
134
134
77
134
134
SSTL-2 Class II
OCT 25 Ω
56
101
101
56
101
101
58
101
101
SSTL-18 Class I
OCT 50 Ω
100
123
123
100
123
123
106
123
123
SSTL-18 Class II
OCT 25 Ω
61
110
110
-
-
-
59
110
110
1.2-V HSTL (2)
OCT 50 Ω
95
-
-
-
-
-
95
-
-
Notes to Table 4–97:
(1)
(2)
(3)
(4)
For LVDS output on row I/O pins the toggle rate derating factors apply to loads larger than 5 pF. In the derating
calculation, subtract 5 pF from the intended load value in pF for the correct result. For a load less than or equal to
5 pF, refer to Tables 4–91 through 4–95 for output toggle rates.
1.2-V HSTL is only supported on column I/O pins on -3 devices.
Differential HSTL and SSTL is only supported on column clock and DQS outputs.
LVPECL is only supported on column clock outputs.
Altera Corporation
June 2009
4–117
Stratix II GX Device Handbook, Volume 1
Duty Cycle Distortion
Duty Cycle
Distortion
Duty cycle distortion (DCD) describes how much the falling edge of a
clock is off from its ideal position. The ideal position is when both the
clock high time (CLKH) and the clock low time (CLKL) equal half of the
clock period (T), as shown in Figure 4–11. DCD is the deviation of the
non-ideal falling edge from the ideal falling edge, such as D1 for the
falling edge A and D2 for the falling edge B (see Figure 4–11). The
maximum DCD for a clock is the larger value of D1 and D2.
Figure 4–11. Duty Cycle Distortion
Ideal Falling Edge
CLKH = T/2
CLKL = T/2
D1
Falling Edge A
D2
Falling Edge B
Clock Period (T)
DCD expressed in absolution derivation, for example, D1 or D2 in
Figure 4–11, is clock-period independent. DCD can also be expressed as a
percentage, and the percentage number is clock-period dependent. DCD
as a percentage is defined as:
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions (Figure 4–12). Therefore, any
DCD present on the input clock signal or caused by the clock input buffer
or different input I/O standard does not transfer to the output signal.
4–118
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Figure 4–12. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions (Figure 4–13). Therefore, any distortion on the input
clock and the input clock buffer affect the output DCD.
Figure 4–13. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Altera Corporation
June 2009
4–119
Stratix II GX Device Handbook, Volume 1
Duty Cycle Distortion
Tables 4–98 through 4–105 show the maximum DCD in absolution
derivation for different I/O standards on Stratix II GX devices. Examples
are also provided that show how to calculate DCD as a percentage.
Table 4–98. Maximum DCD for Non-DDIO Output on Row I/O Pins
Maximum DCD (ps) for Non-DDIO Output
Row I/O Output Standard
-3 Devices
-4 and -5 Devices
Unit
3.3-V LVTTTL
245
275
ps
3.3-V LVCMOS
125
155
ps
2.5 V
105
135
ps
1.8 V
180
180
ps
1.5-V LVCMOS
165
195
ps
SSTL-2 Class I
115
145
ps
SSTL-2 Class II
95
125
ps
SSTL-18 Class I
55
85
ps
1.8-V HSTL Class I
80
100
ps
1.5-V HSTL Class I
85
115
ps
LVDS
55
80
ps
Here is an example for calculating the DCD as a percentage for a
non-DDIO output on a row I/O on a -3 device:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum
DCD is 95 ps (see Table 4–99). If the clock frequency is 267 MHz, the clock
period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (3,745 ps/2 – 95 ps) / 3,745 ps = 47.5% (for low
boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 95 ps) / 3,745 ps = 52.5% (for high
boundary)
4–120
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Therefore, the DCD percentage for the output clock at 267 MHz is from
47.5% to 52.5%.
Table 4–99. Maximum DCD for Non-DDIO Output on Column I/O Pins
Column I/O Output
Standard I/O
Standard
Altera Corporation
June 2009
Maximum DCD (ps) for Non-DDIO
Output
-3 Devices
Unit
-4 and -5 Devices
3.3-V LVTTL
190
220
ps
3.3-V LVCMOS
140
175
ps
2.5 V
125
155
ps
1.8 V
80
110
ps
1.5-V LVCMOS
185
215
ps
SSTL-2 Class I
105
135
ps
SSTL-2 Class II
100
130
ps
SSTL-18 Class I
90
115
ps
SSTL-18 Class II
70
100
ps
1.8-V HSTL
Class I
80
110
ps
1.8-V HSTL
Class II
80
110
ps
1.5-V HSTL
Class I
85
115
ps
1.5-V HSTL
Class II
50
80
ps
1.2-V HSTL-12
170
200
ps
LVPECL
55
80
ps
4–121
Stratix II GX Device Handbook, Volume 1
Duty Cycle Distortion
Table 4–100. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3 Devices
Note (1)
Input I/O Standard (No PLL in Clock Path)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS
2.5 V
1.8 and
1.5 V
3.3 V
Unit
3.3 and
2.5 V
1.8 and
1.5 V
3.3-V LVTTL
260
380
145
145
110
ps
3.3-V LVCMOS
210
330
100
100
65
ps
2.5 V
195
315
85
85
75
ps
1.8 V
150
265
85
85
120
ps
1.5-V LVCMOS
255
370
140
140
105
ps
SSTL-2 Class I
175
295
65
65
70
ps
SSTL-2 Class II
170
290
60
60
75
ps
SSTL-18 Class I
155
275
55
50
90
ps
1.8-V HSTL Class I
150
270
60
60
95
ps
1.5-V HSTL Class I
150
270
55
55
90
ps
LVDS
180
180
180
180
180
ps
Note to Table 4–100:
(1)
The information in Table 4–100 assumes the input clock has zero DCD.
Here is an example for calculating the DCD in percentage for a DDIO
output on a row I/O on a -3 device:
If the input I/O standard is 2.5-V SSTL-2 and the DDIO output I/O
standard is SSTL-2 Class= II, the maximum DCD is 60 ps (see
Table 4–100). If the clock frequency is 267 MHz, the clock period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
Calculate the DCD as a percentage:
(T/2 – DCD) / T = (3,745 ps/2 – 60 ps) / 3745 ps = 48.4% (for low
boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 60 ps) / 3745 ps = 51.6% (for high
boundary)
4–122
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Therefore, the DCD percentage for the output clock is from 48.4% to
51.6%.
Table 4–101. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 and -5
Devices
Note (1)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
3.3-V LVTTL
Input I/O Standard (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS
Unit
3.3/2.5V
1.8/1.5V
2.5V
1.8/1.5V
3.3V
440
495
170
160
105
ps
3.3-V LVCMOS
390
450
120
110
75
ps
2.5 V
375
430
105
95
90
ps
1.8 V
325
385
90
100
135
ps
1.5-V LVCMOS
430
490
160
155
100
ps
SSTL-2 Class I
355
410
85
75
85
ps
SSTL-2 Class II
350
405
80
70
90
ps
SSTL-18 Class I
335
390
65
65
105
ps
1.8-V HSTL Class I
330
385
60
70
110
ps
1.5-V HSTL Class I
330
390
60
70
105
ps
LVDS
180
180
180
180
180
ps
Note to Table 4–101:
(1)
Table 4–101 assumes the input clock has zero DCD.
Table 4–102. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 1 of 2)
Note (1)
Maximum DCD (ps) for
DDIO Column Output I/O
Standard
Input IO Standard (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
SSTL/HSTL
HSTL12
1.8/1.5V
1.2V
Unit
3.3/2.5V
1.8/1.5V
2.5V
3.3-V LVTTL
260
380
145
145
145
ps
3.3-V LVCMOS
210
330
100
100
100
ps
2.5 V
195
315
85
85
85
ps
1.8 V
150
265
85
85
85
ps
1.5-V LVCMOS
255
370
140
140
140
ps
SSTL-2 Class I
175
295
65
65
65
ps
SSTL-2 Class II
170
290
60
60
60
ps
SSTL-18 Class I
155
275
55
50
50
ps
Altera Corporation
June 2009
4–123
Stratix II GX Device Handbook, Volume 1
Duty Cycle Distortion
Table 4–102. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2)
Note (1)
Maximum DCD (ps) for
DDIO Column Output I/O
Standard
Input IO Standard (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
SSTL/HSTL
HSTL12
Unit
3.3/2.5V
1.8/1.5V
2.5V
1.8/1.5V
1.2V
SSTL-18 Class II
140
260
70
70
70
ps
1.8-V HSTL Class I
150
270
60
60
60
ps
1.8-V HSTL Class II
150
270
60
60
60
ps
1.5-V HSTL Class I
150
270
55
55
55
ps
1.5-V HSTL Class II
125
240
85
85
85
ps
1.2-V HSTL
240
360
155
155
155
ps
LVPECL
180
180
180
180
180
ps
Note to Table 4–102:
(1)
Table 4–102 assumes the input clock has zero DCD.
Table 4–103. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 and
-5 Devices
Note (1)
Maximum DCD (ps) for
DDIO Column Output I/O
Standard
Input IO Standard (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
SSTL/HSTL
Unit
3.3/2.5V
1.8/1.5V
2.5V
1.8/1.5V
3.3-V LVTTL
440
495
170
160
ps
3.3-V LVCMOS
390
450
120
110
ps
2.5 V
375
430
105
95
ps
1.8 V
325
385
90
100
ps
1.5-V LVCMOS
430
490
160
155
ps
SSTL-2 Class I
355
410
85
75
ps
SSTL-2 Class II
350
405
80
70
ps
SSTL-18 Class I
335
390
65
65
ps
SSTL-18 Class II
320
375
70
80
ps
1.8-V HSTL Class I
330
385
60
70
ps
1.8-V HSTL Class II
330
385
60
70
ps
1.5-V HSTL Class I
330
390
60
70
ps
1.5-V HSTL Class II
330
360
90
100
ps
LVPECL
180
180
180
180
ps
Note to Table 4–103:
(1)
Table 4–103 assumes the input clock has zero DCD.
4–124
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–104. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the
Clock Path
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
3.3-V LVTTL
Stratix II GX Devices (PLL Output Feeding
DDIO)
-3 Device
-4 and -5 Device
110
105
Unit
ps
3.3-V LVCMOS
65
75
ps
2.5V
75
90
ps
1.8V
85
100
ps
1.5-V LVCMOS
105
100
ps
SSTL-2 Class I
65
75
ps
SSTL-2 Class II
60
70
ps
SSTL-18 Class I
50
65
ps
1.8-V HSTL Class I
50
70
ps
1.5-V HSTL Class I
55
70
ps
LVDS
180
180
ps
Table 4–105. Maximum DCD for DDIO Output on Column I/O Pins With PLL in
the Clock Path (Part 1 of 2)
Maximum DCD (ps) for
Column DDIO Output I/O
Standard
Altera Corporation
June 2009
Stratix II GX Devices (PLL Output Feeding
DDIO)
Unit
-3 Device
-4 and -5 Device
3.3-V LVTTL
145
160
ps
3.3-V LVCMOS
100
110
ps
2.5V
85
95
ps
1.8V
85
100
ps
1.5-V LVCMOS
140
155
ps
SSTL-2 Class I
65
75
ps
SSTL-2 Class II
60
70
ps
SSTL-18 Class I
50
65
ps
SSTL-18 Class II
70
80
ps
1.8-V HSTL Class I
60
70
ps
1.8-V HSTL Class II
60
70
ps
1.5-V HSTL Class I
55
70
ps
1.5-V HSTL Class II
85
100
ps
4–125
Stratix II GX Device Handbook, Volume 1
High-Speed I/O Specifications
Table 4–105. Maximum DCD for DDIO Output on Column I/O Pins With PLL in
the Clock Path (Part 2 of 2)
Maximum DCD (ps) for
Column DDIO Output I/O
Standard
High-Speed I/O
Specifications
Stratix II GX Devices (PLL Output Feeding
DDIO)
Unit
-3 Device
-4 and -5 Device
1.2-V HSTL
155
155
ps
LVPECL
180
180
ps
Table 4–106 provides high-speed timing specifications definitions.
Table 4–106. High-Speed Timing Specifications and Definitions
High-Speed Timing Specifications
Definitions
tC
High-speed receiver/transmitter input and output clock period.
fH S C L K
High-speed receiver/transmitter input and output clock frequency.
J
Deserialization factor (width of parallel data bus).
W
PLL multiplication factor.
tR I S E
Low-to-high transmission time.
tF A L L
High-to-low transmission time.
Timing unit interval (TUI)
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC /w).
fIN
Fast PLL input clock frequency
fH S D R
Maximum/minimum LVDS data transfer rate (fH S D R = 1/TUI), non-DPA.
fH S D R D P A
Maximum/minimum LVDS data transfer rate (fH S D R D PA = 1/TUI), DPA.
Channel-to-channel skew (TCCS)
The timing difference between the fastest and the slowest output edges
including tCO variation and clock skew across channels driven by the
same fast PLL. The clock is included in the TCCS measurement.
Sampling window (SW)
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Input jitter
Peak-to-peak input jitter on high-speed PLLs.
Output jitter
Peak-to-peak output jitter on high-speed PLLs.
tDUTY
Duty cycle on high-speed transmitter output clock.
tL O C K
Lock time for high-speed transmitter and receiver PLLs.
4–126
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–107 shows the high-speed I/O timing specifications for -3 speed
grade Stratix II GX devices.
Table 4–107. High-Speed I/O Specifications for -3 Speed Grade
Notes (1), (2)
-3 Speed Grade
Symbol
Conditions
Unit
Min
fI N = f H S D R / W
fH S D R (data rate)
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
Typ
Max
16
520
MHz
W = 1 (SERDES bypass, LVDS only)
16
500
MHz
W = 1 (SERDES used, LVDS only)
150
717
MHz
J = 4 to 10 (LVDS, HyperTransport technology)
150
1,040
Mbps
J = 2 (LVDS, HyperTransport technology)
(4)
760
Mbps
J = 1 (LVDS only)
fH S D R D PA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
(4)
500
Mbps
150
1,040
Mbps
200
ps
TCCS
All differential standards
-
SW
All differential standards
330
Output jitter
-
ps
190
ps
Output tR I S E
All differential I/O standards
160
ps
Output tFA L L
All differential I/O standards
180
ps
55
%
tDUTY
45
DPA run length
DPA jitter tolerance (5)
DPA lock time
50
6,400
Data channel peak-to-peak jitter
Standard
SPI-4
Parallel Rapid I/O
Miscellaneous
0.44
Training
Pattern
Transition
Density
0000000000
1111111111
10%
256
00001111
25%
256
10010000
50%
256
10101010
100%
256
01010101
UI
UI
Number of
repetitions
256
Notes to Table 4–107:
(1)
(2)
(3)
(4)
(5)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤input clock
frequency × W ≤1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
For setup details, refer to the characterization report.
Altera Corporation
June 2009
4–127
Stratix II GX Device Handbook, Volume 1
High-Speed I/O Specifications
Table 4–108 shows the high-speed I/O timing specifications for -4 speed
grade Stratix II GX devices.
Table 4–108. High-Speed I/O Specifications for -4 Speed Grade
Notes (1), (2)
-4 Speed Grade
Symbol
Conditions
Unit
Min
fI N = f H S D R / W
fH S D R (data rate)
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
Typ
Max
16
520
MHz
W = 1 (SERDES bypass, LVDS only)
16
500
MHz
W = 1 (SERDES used, LVDS only)
150
717
MHz
J = 4 to 10 (LVDS, HyperTransport technology)
150
1,040
Mbps
J = 2 (LVDS, HyperTransport technology)
(4)
760
Mbps
J = 1 (LVDS only)
fH S D R D PA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
(4)
500
Mbps
150
1,040
Mbps
200
ps
TCCS
All differential standards
-
SW
All differential standards
330
Output jitter
-
ps
190
ps
Output tR I S E
All differential I/O standards
160
ps
Output tFA L L
All differential I/O standards
180
ps
55
%
6,400
UI
tDUTY
45
DPA run length
DPA jitter tolerance
DPA lock time
Data channel peak-to-peak jitter
0.44
Standard
Training
Pattern
Transition
Density
SPI-4
0000000000
1111111111
10%
256
Parallel Rapid I/O
00001111
25%
256
10010000
50%
256
10101010
100%
256
Miscellaneous
01010101
50
UI
Number of
repetitions
256
Notes to Table 4–108:
(1)
(2)
(3)
(4)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤input clock
frequency × W ≤1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
4–128
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–109 shows the high-speed I/O timing specifications for -5 speed
grade Stratix II GX devices.
Table 4–109. High-Speed I/O Specifications for -5 Speed Grade
Notes (1), (2)
-5 Speed Grade
Symbol
Conditions
Unit
Min
fI N = f H S D R / W
fH S D R (data rate)
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
Typ
Max
16
420
MHz
W = 1 (SERDES bypass, LVDS only)
16
500
MHz
W = 1 (SERDES used, LVDS only)
150
640
MHz
J = 4 to 10 (LVDS, HyperTransport technology)
150
840
Mbps
J = 2 (LVDS, HyperTransport technology)
(4)
700
Mbps
J = 1 (LVDS only)
fH S D R D PA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
(4)
500
Mbps
150
840
Mbps
200
ps
TCCS
All differential I/O standards
-
SW
All differential I/O standards
440
Output jitter
-
ps
190
ps
Output tR I S E
All differential I/O standards
290
ps
Output tFA L L
All differential I/O standards
290
ps
55
%
6,400
UI
tDUTY
45
DPA run length
DPA jitter tolerance
DPA lock time
Data channel peak-to-peak jitter
Standard
SPI-4
Parallel Rapid I/O
Miscellaneous
0.44
Training
Pattern
Transition
Density
0000000000
1111111111
10%
256
00001111
25%
256
10010000
50%
256
10101010
100%
256
01010101
50
UI
Number of
repetitions
256
Notes to Table 4–109:
(1)
(2)
(3)
(4)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤input clock
frequency × W ≤840.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
Altera Corporation
June 2009
4–129
Stratix II GX Device Handbook, Volume 1
PLL Timing Specifications
PLL Timing
Specifications
Tables 4–110 and 4–111 describe the Stratix II GX PLL specifications when
operating in both the commercial junction temperature range (0 to 85 C)
and the industrial junction temperature range (–40 to 100 C), except for
the clock switchover and phase-shift stepping features. These two
features are only supported from the 0 to 100 C junction temperature
range.
Table 4–110. Enhanced PLL Specifications (Part 1 of 2)
Name
Description
Min
Typ
Max
Unit
fIN
Input clock frequency
4
500
MHz
fINPFD
Input frequency to the PFD
4
420
MHz
fINDUTY
Input clock duty cycle
40
60
%
fENDUTY
External feedback input clock duty
cycle
40
60
%
tINJITTER
Input or external feedback clock input
jitter tolerance in terms of period jitter.
Bandwidth ≤0.85 MHz
0.5
ns (peakto-peak)
Input or external feedback clock input
jitter tolerance in terms of period jitter.
Bandwidth > 0.85 MHz
1.0
ns (peakto-peak)
tOUTJITTER
Dedicated clock output period jitter
tFCOMP
External feedback compensation time
fOUT
Output frequency for internal global or
regional clock
fOUTDUTY
Duty cycle for external clock output
fSCANCLK
Scanclk frequency
tCONFIGEPLL
Time required to reconfigure scan
chains for EPLLs
fOUT_EXT
PLL external clock output frequency
tLOCK
Time required for the PLL to lock from
the time it is enabled or the end of
device configuration
tDLOCK
Time required for the PLL to lock
dynamically after automatic clock
switchover between two identical clock
frequencies
fSWITCHOVER
Frequency range where the clock
switchover performs properly
1.5
fCLBW
PLL closed-loop bandwidth
0.13
4–130
Stratix II GX Device Handbook, Volume 1
1.5 (2)
45
50
250 ps for ≥
100 MHz outclk
25 mUI for <
100 MHz outclk
ps or mUI
(p-p)
10
ns
550
MHz
55
%
100
MHz
174/fSCANCLK
1.5 (2)
ns
(1)
MHz
1
ms
1
ms
1
500
MHz
1.2
16.9
MHz
0.03
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–110. Enhanced PLL Specifications (Part 2 of 2)
Name
fVCO
Description
Min
Typ
Max
Unit
PLL VCO operating range for –3 and
–4 speed grade devices
300
1,040
MHz
PLL VCO operating range for –5 speed
grade devices
300
840
MHz
fSS
Spread-spectrum modulation
frequency
100
500
kHz
% spread
Percent down spread for a given clock
frequency
0.4
0.6
%
tP L L _ P S E R R
Accuracy of PLL phase shift
±30
ps
tARESET
Minimum pulse width on areset
signal.
10
ns
tARESET_RECONFIG
Minimum pulse width on the areset
signal when using PLL reconfiguration.
Reset the PLL after scandone goes
high.
500
ns
tRECONFIGWAIT
The time required for the wait after the
reconfiguration is done and the areset
is applied.
0.5
2
us
Notes to Table 4–110:
(1)
(2)
This is limited by the I/O fMAX. See Tables 4–91 through 4–95 for the maximum.
If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
Table 4–111. Fast PLL Specifications (Part 1 of 2)
Name
fIN
Description
Min
Typ
Max
Unit
Input clock frequency (for -3 and -4 speed
grade devices)
16
717
MHz
Input clock frequency (for -5 speed grade
devices)
16
640
MHz
fINPFD
Input frequency to the PFD
16
500
MHz
fINDUTY
Input clock duty cycle
40
60
%
tINJITTER
Input clock jitter tolerance in terms of period
jitter. Bandwidth ≤2 MHz
0.5
ns (p-p)
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 0.2 MHz
1.0
ns (p-p)
Altera Corporation
June 2009
4–131
Stratix II GX Device Handbook, Volume 1
External Memory Interface Specifications
Table 4–111. Fast PLL Specifications (Part 2 of 2)
Name
fVCO
fOUT
Description
Min
Upper VCO frequency range for –3 and –4
speed grades
Max
Unit
300
1,040
MHz
Upper VCO frequency range for –5 speed
grades
300
840
MHz
Lower VCO frequency range for –3 and –4
speed grades
150
520
MHz
Lower VCO frequency range for –5 speed
grades
150
420
MHz
4.6875
550
MHz
150
1,040
MHz
4.6875
(1)
MHz
PLL output frequency to GCLK or RCLK
PLL output frequency to LVDS or DPA clock
Typ
fOUT_EXT
PLL clock output frequency to regular I/O
tCONFIGPLL
Time required to reconfigure scan chains for
fast PLLs
fCLBW
PLL closed-loop bandwidth
tLOCK
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
tPLL_PSERR
Accuracy of PLL phase shift
tARESET
Minimum pulse width on areset signal.
10
ns
tARESET_RECONFIG
Minimum pulse width on the areset signal
when using PLL reconfiguration. Reset the
PLL after scandone goes high.
500
ns
75/fSCANCLK
1.16
ns
5
28
MHz
0.03
1
ms
±30
ps
Notes to Table 4–111:
(1)
This is limited by the I/O fMAX. See Tables 4–91 through 4–95 for the maximum.
External
Memory
Interface
Specifications
Tables 4–112 through 4–116 contain Stratix II GX device specifications for
the dedicated circuitry used for interfacing with external memory
devices.
Table 4–112. DLL Frequency Range Specifications (Part 1 of 2)
Frequency Mode
Frequency Range (MHz)
Resolution
(Degrees)
0
100 to 175
30
1
2
4–132
Stratix II GX Device Handbook, Volume 1
150 to 230
22.5
200 to 350 (–3 speed grade)
30
200 to 310 (–4 and –5 speed grade)
30
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–112. DLL Frequency Range Specifications (Part 2 of 2)
Frequency Range (MHz)
Resolution
(Degrees)
240 to 400 (–3 speed grade)
36
240 to 350 (–4 and –5 speed grade)
36
Frequency Mode
3
Table 4–113. DQS Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER)
Note (1)
Number of DQS Delay Buffer Stages
(2)
Commercial (ps)
Industrial (ps)
1
80
110
2
110
130
3
130
180
4
160
210
Notes to Table 4–113:
(1)
(2)
Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on
two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps.
Delay stages used for requested DQS phase shift are reported in a project’s
Compilation Report in the Quartus II software.
Table 4–114. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR)
Number of DQS Delay Buffer Stages (1) –3 Speed Grade (ps) –4 Speed Grade (ps) –5 Speed Grade (ps)
1
25
30
35
2
50
60
70
3
75
90
105
4
100
120
140
Note to Table 4–114:
(1)
Delay stages used for request DQS phase shift are reported in a project’s Compilation Report in the Quartus II
software. For example, phase-shift error on two delay stages under -3 conditions is 50 ps peak-to-peak or 25 ps.
Altera Corporation
June 2009
4–133
Stratix II GX Device Handbook, Volume 1
JTAG Timing Specifications
Table 4–115. DQS Bus Clock Skew Adder Specifications
(tDQS_CLOCK_SKEW_ADDER)
Mode
DQS Clock Skew Adder (ps) (1)
4 DQ per DQS
40
9 DQ per DQS
70
18 DQ per DQS
75
36 DQ per DQS
95
Note to Table 4–115:
(1)
This skew specification is the absolute maximum and minimum skew. For
example, skew on a 40 DQ group is 40 ps or 20 ps.
Table 4–116. DQS Phase Offset Delay Per Stage (ps)
Positive Offset
Notes (1), (2), (3)
Negative Offset
Speed Grade
Min
Max
Min
Max
-3
10
15
8
11
-4
10
15
8
11
-5
10
16
8
12
Notes to Table 4–116:
(1)
(2)
(3)
JTAG Timing
Specifications
The delay settings are linear.
The valid settings for phase offset are -32 to +31.
The typical value equals the average of the minimum and maximum values.
Figure 4–14 shows the timing requirements for the JTAG signals
4–134
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Figure 4–14. Stratix II GX JTAG Waveforms.
TMS
TDI
t JCP
t JCH
t JCL
t JPH
t JPSU
TCK
tJPZX
t JPXZ
t JPCO
TDO
tJSSU
Signal
to be
Captured
Signal
to be
Driven
tJSZX
tJSH
tJSCO
tJSXZ
Table 4–117 shows the JTAG timing parameters and values for
Stratix II GX devices.
Table 4–117. Stratix II GX JTAG Timing Parameters and Values
Symbol
Altera Corporation
June 2009
Parameter
Min Max Unit
tJCP
TCK clock period
30
ns
tJCH
TCK clock high time
12
ns
tJCL
TCK clock low time
12
ns
tJPSU
JTAG port setup time
4
ns
tJPH
JTAG port hold time
5
tJPCO
JTAG port clock to output
9
ns
tJPZX
JTAG port high impedance to valid output
9
ns
tJPXZ
JTAG port valid output to high impedance
9
ns
tJSSU
Capture register setup time
4
ns
tJSH
Capture register hold time
5
ns
tJSCO
Update register clock to output
tJSZX
Update register high impedance to valid output
12
ns
tJSXZ
Update register valid output to high impedance
12
ns
ns
12
ns
4–135
Stratix II GX Device Handbook, Volume 1
Referenced Documents
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
■
■
Operating Requirements for Altera Devices Data Sheet
PowerPlay Power Analyzer chapter in volume 3 of the Quartus II
Handbook.
PowerPlay Early Power Estimator (EPE) and Power Analyzer
Quartus II PowerPlay Analysis and Optimization Technology
Stratix II GX Architecture chapter in volume 1 of the Stratix II
GX Device Handbook
Stratix II GX Transceiver Architecture Overview chapter in volume 2 of
the Stratix II GX Device Handbook
Volume 2, Stratix II GX Device Handbook
4–136
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Document
Revision History
Table 6–105 shows the revision history for this chapter.
Table 4–118. Document Revision History (Part 1 of 5)
Date and
Document
Version
June 2009
v4.6
October 2007
v4.5
Changes Made
Summary of Changes
Replaced Table 4–31
Updated:
● Table 4–5
● Table 4–6
● Table 4–7
● Table 4–8
● Table 4–9
● Table 4–10
● Table 4–11
● Table 4–12
● Table 4–13
● Table 4–14
● Table 4–15
● Table 4–16
● Table 4–17
● Table 4–18
● Table 4–20
● Table 4–50
● Table 4–95
● Table 4–105
● Table 4–110
● Table 4–111
Updated:
Table 4–3
● Table 4–6
● Table 4–16
● Table 4–19
● Table 4–20
● Table 4–21
● Table 4–22
● Table 4–55
● Table 4–106
● Table 4–107
● Table 4–108
● Table 4–109
● Table 4–112
●
Updated title only in Tables 4–88 and 4–89.
Minor text edits.
Altera Corporation
June 2009
4–137
Stratix II GX Device Handbook, Volume 1
Document Revision History
Table 4–118. Document Revision History (Part 2 of 5)
Date and
Document
Version
August 2007
v4.4
Changes Made
Summary of Changes
Removed note “The data in this table is preliminary.
Altera will provide a report upon completion of
characterization of the Stratix II GX devices.
Conditions for testing the silicon have not been
determined.” from each table.
Removed note “The data in Tables xxx through xxx
is preliminary. Altera will provide a report upon
completion of characterization of the Stratix II GX
devices. Conditions for testing the silicon have not
been determined.” in the clock timing parameters
sections.
Updated clock timing parameter Tables 4–63
through 4–78 (Table 4–75 was unchanged).
Updated Table 4–21 and added new Table 4–22.
Updated:
Table 4–6
● Table 4–16
● Table 4–19
● Table 4–49
● Table 4–52
● Table 4–107
●
Added note to Table 4–50.
Added:
● Figure 4–3
● Figure 4–4
● Figure 4–5
Added the “Referenced Documents” section.
May 2007 v4.3
Changed 1.875 KHz to 1.875 MHz in Table 4–19,
XAUI Receiver Jitter Tolerance section.
4–138
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–118. Document Revision History (Part 3 of 5)
Date and
Document
Version
February 2007
v4.2
Changes Made
Summary of Changes
Added the “Document Revision History” section to
this chapter.
Added support information for the
Stratix II GX device.
Updated Table 4–5:
Removed last three lines
● Removed note 1
● Added new note 4
●
Deleted table 6-6.
Replaced Table 4–6 with all new information.
Added Figures 4–1 and 4–2.
Added Tables 4–7 through 4–19.
Removed Figures 6-1 through 6-4.
Updated Table 4–22:
● Changed RCONF information.
Updated Table 4–52
● SSTL-18 Class I, column 1: changed 25 to 50.
Updated:
● Table 4–54
● Table 4–87
● Table 4–91
● Table 4–94
Updated Tables 4–62 through 4–77
Updated Tables 4–79 and 4–80
● Added “units” column
Updated Tables 4–83 through 4–86
● Changed column title to “Fast Corner
Industrial/Commercial”.
Updated Table 4–109.
● Added a new line to the bottom of the table.
August 2006
v4.1
Update Table 6–75, Table 6–84, and Table 6–90.
Altera Corporation
June 2009
4–139
Stratix II GX Device Handbook, Volume 1
Document Revision History
Table 4–118. Document Revision History (Part 4 of 5)
Date and
Document
Version
June 2006, v4.0
Changes Made
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Updated Table 6–5.
Updated Table 6–6.
Updated all values in Table 6–7.
Added Tables 6–8 and 6–9.
Added Figures 6–1 through 6–4.
Updated Table 6–18.
Updated Tables 6–85 through 6–96.
Added Table 6–80, Stratix II GX Maximum
Output Clock Rate for Dedicated Clock Pins.
Updated Table 6–100.
In “I/O Timing Measurement Methodology”
section, updated Table 6–42.
In “Internal Timing Parameters” section,
updated Tables 6–43 through 6–48.
In “Stratix II GX Clock Timing Parameters”
section, updated Tables 6–50 through 6–65.
In “IOE Programmable Delay” section, updated
Tables 6–67 and 6–68.
In “I/O Delays” section, updated Tables 6–71
through 6–74.
In “Maximum Input & Output Clock Toggle Rate”
section, updated Tables 6–75 through 6–83.
In “DCD Measurement Techniques” section,
updated Tables 6–85 through 6–92.
In “High-Speed I/O Specifications” section,
updated Tables 6–94 through 6–96.
In “External Memory Interface Specifications”
section, updated Table 6–100.
4–140
Stratix II GX Device Handbook, Volume 1
Summary of Changes
●
●
●
●
Removed rows for VI D , VO D, VI C M ,
and VO C M from Table 6–5.
Updated values for rx, tx, and
refclkb in Table 6–6.
Removed table containing 1.2-V
PCML I/O information. That
information is in Table 6–7.
Added values to Table 6–100.
Altera Corporation
June 2009
DC and Switching Characteristics
Table 4–118. Document Revision History (Part 5 of 5)
Date and
Document
Version
April 2006, v3.0
Changes Made
●
●
●
●
●
●
●
●
●
February 2006,
v2.1
●
●
Summary of Changes
Updated Table 6–3.
Updated Table 6–5.
Updated Table 6–7.
Added Table 6–42.
Updated “Internal Timing Parameters” section
(Tables 6–43 through 6–48).
Updated “Stratix II GX Clock Timing
Parameters” section (Tables 6–49 through
6–65).
Updated “IOE Programmable Delay” section
(Tables 6–67 and 6–68)
Updated “I/O Delays” section (Tables 6–71
through 6–74.
Updated “Maximum Input & Output Clock Toggle
Rate” section. Replaced tables 6-73 and 6-74
with Tables 6–75 through 6–83. Input and output
clock rates for row, column, and dedicated clock
pins are now in separate tables.
Updated Tables 6–4 and 6–5.
Updated Tables 6–49 through 6–65 (removed
column designations for industrial/commercial
and removed industrial numbers).
December 2005, Updated timing numbers.
v2.0
October 2005
v1.1
●
●
●
●
October 2005
v1.0
Updated Table 6–7.
Updated Table 6–38.
Updated 3.3-V PCML information and notes to
Tables 6–73 through 6–76.
Minor textual changes throughout the
document.
Added chapter to the Stratix II GX Device
Handbook.
Altera Corporation
June 2009
4–141
Stratix II GX Device Handbook, Volume 1
Document Revision History
4–142
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement