Low Power, Precision Analog Microcontroller, Dual Sigma-Delta ADCs ADuC7060/ADuC7061 Silicon Anomaly This anomaly list describes the known bugs, anomalies, and workarounds for the ADuC7060/ADuC7061 MicroConverter® Revision D silicon. The anomalies listed apply to all ADuC7060/ADuC7061 packaged material that is branded as follows: First Line Third Line ADuC7060/ADuC7061 D30 or newer (revision identifier) Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended workarounds outlined here. ADuC7060/ADuC7061 FUNCTIONALITY ISSUES Silicon Revision Identifier D Kernel Revision Identifier 0 Chip Marking All silicon branded D30 Silicon Status Release Anomaly Sheet Rev. B No. of Reported Anomalies 6 Silicon Status Release Anomaly Sheet Rev. B No. of Reported Anomalies 0 Anomaly Sheet Rev. B No. of Reported Anomalies 0 ADuC7060/ADuC7061 PERFORMANCE ISSUES Silicon Revision Identifier D Kernel Revision Identifier 0 Chip Marking All silicon branded D30 ADuC7060/ADuC7061 SILICON FUTURE ENHANCEMENTS Silicon Revision Identifier D Rev. B Kernel Revision Identifier 0 Chip Marking All silicon branded D30 Silicon Status Release Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuC7060/ADuC7061 Silicon Anomaly FUNCTIONALITY ISSUES Table 1. External IRQ When Configured as Level Sensitive [er002] Background Issue Workaround Related Issues There are four external interrupt sources on the ADuC7060/ADuC7061 parts. These can be configured as edge triggered (rising or falling) or level triggered (active high or active low). When any of the external interrupt sources are configured as level triggered, either active high or active low, the external pin must remain at the active level until the program vectors to the interrupt vector handler for that external interrupt. If the external pin is activated, triggering an interrupt, but subsequently goes to an inactive level before the program vectors to the interrupt handler, the appropriate IRQSTA bit for the external interrupt may not be set. This results in the interrupt handler not knowing what interrupt source caused the part to vector to the interrupt vector. Edge triggered interrupts do not have this problem. A fix is pending for this issue. None. Table 2. DAC Output Limited to AVDD − 250 mV [er005] Background Issue Workaround Related Issues The DAC output range can be configured to four different settings: • 0 V to VREF (1.2 V) range (internal reference source) • VREF− to VREF+ • ADC5/EXT_REF2IN− to ADC4/EXT_REF2IN+ • 0 V to AVDD The DAC output buffer is limited in the maximum output voltage in that it can drive to AVDD − 250 mV. This is less than the data sheet specification of AVDD. A fix is pending for this issue. None. Table 3. Disabling I2C Interface in Slave Mode When a Transfer Is in Progress [er006] Background Issue Workaround Related Issues Bit 0 (I2CSEN) of the I2CSCON register enables/disables the I2C slave interface. Bit 6 (I2CBUSY) of the I2CSSTA register indicates if the I2C slave interface is busy or not. If I2C slave mode is enabled (I2CSCON[0] = 1), and a transfer is in progress with the master, then I2CSCON[0] should not be cleared to 0 to disable the I2C slave interface until Bit 6 of I2CSSTA (I2CBUSY, the I2C slave busy status bit) is cleared. When I2CSCON[0] is cleared to 0 and the I2C slave busy status bit is still set, the ADuC7060/ADuC7061 may drive the SDA pin low indefinitely. When this condition occurs, the ADuC7060/ADuC7061 does not release the SDA unless a hardware reset condition occurs. When disabling I2C slave mode by writing to I2CSCON[0], first set Bit 0 (I2CMEN) of the I2CMCON register = 1 to enable master mode. Then disable the slave mode by clearing I2CSCON[0]. Finally, clear I2CMCON[0]. None. Table 4. Operation of SPI in Slave Mode [er007] Background Issue Workaround Related Issues When in SPI slave mode, the ADuC7060/ADuC7061 expects the number of clock pulses from the master to be divisible by 8 when the slave chip select pin (SS) is active. The internal bit shift counter does not reset when the chip select pin is deasserted. If the number of clocks from the master is not divisible by 8 when the chip select (SS) is active, this can result in incorrect data being received or transmitted by the ADuC7060/ADuC7061 because the internal bit shift counter will not be at 0 for subsequent transfers. The internal bit shift counter for the transmit or receive buffers can only be reset by a hardware, software, or watchdog reset condition. Always ensure that the number of SPI clocks are divisible by 8 when the ADuC7060/ADuC7061 chip select (SS) is active. None. Rev. B | Page 2 of 4 Silicon Anomaly ADuC7060/ADuC7061 Table 5. I2C Slave Not Releasing the Bus [er008] Background Issue Workaround Related Issues When an I2C read request happens, if the slave’s Tx FIFO is empty, the slave should NACK the masters’ request. Then it should release the bus, allowing the master to generate a stop condition. If the slave’s Tx FIFO is loaded with a byte who’s MSB is 0 just on the rising edge of SCL for the ACK/NACK, the slave will pull the SDA low and hold the line until the device is reset. Make sure the Tx FIFO is always loaded on time by preloading Tx FIFO in the preceding Rx interrupt. None. Table 6. I2C Clock Stretch Issue [er009] Background Issue Workaround Related Issues Clock stretching is a feature that allows a device to halt the I2C bus temporarily by holding SCL low. Bit 6 of the I2CxSCON register enables clock stretching in slave mode. Bit 3 of the I2CxMCON register enables clock stretching in master mode. Writing to I2CxSCON Bit 6 or to I2CxMCON Bit 3 on the rising edge of SCL can cause a glitch that may be interpreted by other devices as a real clock edge and might hang the bus. Do not enable clock stretching. None. SECTION 1. ADuC7060/ADuC7061 FUNCTIONALITY ISSUES Reference Number er001 er002 er003 er004 er005 er006 er007 er008 er009 Description Power-down mode issue External IRQ when configured as level sensitive SPI issue in slave mode when the SPI serial clock phase mode bit (SPICH) is set Primary ADC self-gain calibration mode DAC output limited to AVDD − 250 mV Disabling the I2C interface in slave mode when a transfer is in progress Operation of SPI in slave mode I2C slave not releasing the bus I2C clock stretch issue Status Fixed on Revision C and later silicon Open Fixed on Revision C and later silicon Fixed on Revision C and later silicon Open Open Open Open Open SECTION 2. ADuC7060/ADuC7061 PERFORMANCE ISSUES Reference Number pr001 Description DAC relative accuracy when the output range is greater than 0 V to 1.2 V Status Fixed on Revision C and later silicon SECTION 3. ADuC7060/ADuC7061 SILICON FUTURE ENHANCEMENTS Reference Number fe001 Description Primary ADC input buffer bypass Status Fixed on Revision C and later silicon Rev. B | Page 3 of 4 ADuC7060/ADuC7061 Silicon Anomaly NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2009–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. S08477-0-9/14(B) Rev. B | Page 4 of 4
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