Arria 10 GX, GT, and SX Schematic Review Worksheet

Arria 10 GX, GT, and SX Schematic Review Worksheet

<Project Name> <Date>

Arria® 10 GX, GT, and SX Device Schematic Review Worksheet

This document is intended to help you review your schematic and compare the pin usage against the

Arria 10 GX, GT, and SX Device Family Pin

Connection Guidelines (PDF) version 1.5 and other referenced literature for this device family. The technical content is divided into focus areas such as FPGA power supplies, transceiver power supplies and pin usage, configuration, and FPGA I/O, and external memory interfaces.

Within each focus area, there is a table that contains the voltage or pin name for all of the dedicated and dual purpose pins for the device family.

In some cases, the device density and package combination may not include some of the pins shown in this worksheet, you should cross reference with the pin-out file for your specific device. Links to the device pin-out files are provided at the top of each section.

Before you begin using this worksheet to review your schematic and commit to board layout, Altera highly recommends:

1) Review the latest version of the Errata Sheet and Guidelines for Arria 10 ES Devices (PDF), Errata Sheet for Arria 10 Devices (PDF), and the

Knowledge Database for Arria 10 Device Known Issues and Arria 10 Device Handbook Known Issues.

2) Compile your design in the Quartus® II software to completion.

For example, there are many I/O related placement restrictions and VCCIO requirements for the I/O standards used in the device. If you do not have a complete project, then at a minimum a top level project should be used with all I/O pins defined, placed, and apply all of the configurable options that you plan to use. All I/O related IP should also be included in the minimal project, including, but not limited to, external memory interfaces, transceiver IP, PLLs, and source synchronous SERDES. You can use the I/O Analysis tool in the Quartus II Pin Planner to validate the pinout in Quartus II software to assure there are no conflicts with the device rules and guidelines.

When using the I/O Analysis tool you must ensure there are no errors with your pinout. Additionally, you should check all warning and critical warning messages to evaluate their impact on your design. You can right click your mouse over any warning or critical warning message and select “Help”. This will bring open a new Help window with further information on the cause of the warning, and the action that is required.

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For example, the following warning is generated when a PLL is driven by a global network where the source is a valid dedicated clock input pin, but the pin is not one dedicated to the particular PLL:

Warning: PLL "<PLL Instance Name>" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

Info: Input port INCLK[0] of node "<PLL Instance Name>" is driven by clock~clkctrl which is OUTCLK output port of Clock Control Block type node clock~clkctrl

The help file provides the following:

CAUSE: The specified PLL's input clock is not driven by a dedicated input pin. As a result, the input clock delay will not be fully compensated by the PLL. Additionally, jitter performance depends on the switching rate of other design elements. This can also occur if a global signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.

ACTION: If you want compensation of the specified input clock or better jitter performance, connect the input clock only to an input pin, or assign the input pin only to a dedicated input clock location for the PLL. If you do not want compensation of the specified input clock, then set the PLL to No Compensation mode.

When assigning the input pin to the proper dedicated clock pin location, refer to Clock Networks and PLLs in Arria 10 Devices (PDF) for the proper port mapping of dedicated clock input pins to PLLs.

There are many reports available for use after a successful compilation or I/O analysis. For example, you can use the “All Package Pins” and “I/O

Bank Usag e” reports within the Compilation – Fitter – Resource Section to see all of the I/O standards and I/O configurable options that are assigned to all of the pins in your design, as well as view the required VCCIO for each I/O bank. These reports must match your schematic pin connections.

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The review table has the following heading:

Plane/Signal Schematic Name Connection Guidelines Comments / Issues

The first column (Plane/Signal) lists the FPGA voltage or signal pin name. You should only edit this column to remove dedicated or dual purpose pin names that are not available for your device density and package option.

The second column (Schematic Name) is for you to enter your schematic name(s) for the signal(s) or plane connected to the FPGA pin(s).

The t hird column (Connection Guidelines) should be considered “read only” as this contains Altera’s recommended connection guidelines for the voltage plane or signal.

The fourth column (Comments/Issues) is an area provided as a “notepad” for you to comment on any deviations from the connection guidelines, and to verify guidelines are met. In many cases there are notes that provide further information and detail that complement the connection guidelines.

Here is an example of how the worksheet can be used:

Plane/Signal Schematic Name

<Plane / Signal name provided by Altera>

VCC

<user entered text>

+0.85V

Connection Guidelines

<Device Specific Guidelines provided by

Altera>

Comments / Issues

<user entered text>

Connected to +0.85V plane, no isolation is necessary.

Missing low and medium range decoupling, check PDN.

See Notes (1-1) (1-2) .

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Legal Note:

PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THIS SCHEMATIC REVIEW WORKSHEET

(“WORKSHEET”) PROVIDED TO YOU. BY USING THIS WORKSHEET, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND

CONDITIONS, WHICH CONSTITUTE THE LICENSE AGREEMENT ("AGREEMENT") BETWEEN YOU AND ALTERA CORPORATION OR ITS

APPLICABLE SUBSIDIARIES ("ALTERA").

1. Subject to the terms and conditions of this Agreement, Altera grants to you, for no additional fee, a non-exclusive and non-transferable right to use this Worksheet for the sole purpose of verifying the validity of the pin connections of an Altera programmable logic device-based design. You may not use this Worksheet for any other purpose. There are no implied licenses granted under this Agreement, and all rights, except for those granted under this Agreement, remain with Altera.

2. Altera does not guarantee or imply the reliability, or serviceability, of this Worksheet or other items provided as part of this Worksheet. This

Worksheet is provided 'AS IS'. ALTERA DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. ALTERA HAS NO OBLIGATION TO PROVIDE

YOU WITH ANY SUPPORT OR MAINTENANCE.

3. In no event shall the aggregate liability of Altera relating to this Agreement or the subject matter hereof under any legal theory (whether in tort, contract, or otherwise), exceed One Hundred US Dollars (US$100.00). In no event shall Altera be liable for any lost revenue, lost profits, or other consequential, indirect, or special damages caused by your use of this Worksheet even if advised of the possibility of such damages.

4. This Agreement may be terminated by either party for any reason at any time upon 30days’ prior written notice. This Agreement shall be governed by the laws of the State of California, without regard to conflict of law or choice of law principles. You agree to submit to the exclusive jurisdiction of the courts in the County of Santa Clara, State of California for the resolution of any dispute or claim arising out of or relating to this

Agreement. The parties hereby agree that the party who is not the substantially prevailing party with respect to a dispute, claim, or controversy relating to this Agreement shall pay the costs actually incurred by the substantially prevailing party in relation to such dispute, claim, or controversy, including attorneys' fees. Failure to enforce any term or condition of this Agreement shall not be deemed a waiver of the right to later enforce such term or condition or any other term or condition of the Agreement.

BY USING THIS WORKSHEET, YOU ACKNOWLEDGE THAT YOU HAVE READ THIS AGREEMENT, UNDERSTAND IT, AND AGREE TO BE

BOUND BY ITS TERMS AND CONDITIONS. YOU AND ALTERA FURTHER AGREE THAT IT IS THE COMPLETE AND EXCLUSIVE

STATEMENT OF THE AGREEMENT BETWEEN YOU AND ALTERA, WHICH SUPERSEDES ANY PROPOSAL OR PRIOR AGREEMENT,

ORAL OR WRITTEN, AND ANY OTHER COMMUNICATIONS BETWEEN YOU AND ALTERA RELATING TO THE SUBJECT MATTER OF THIS

AGREEMENT.

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Index

Section I:

Section II:

Section III:

Section IV: a: b: c: d:

Section V: a: b: c: d:

Power

Configuration

Transceiver

I/O

Clock Pins

HPS

Dedicated and Dual Purpose Pins

Dual Purpose Differential I/O pins

External Memory Interface Pins

DDR3 Interface Pins

DDR3 Termination Guidelines

DDR4 Interface Pins

DDR4 Termination Guidelines

e. RLDRAM3 Interface Guidelines

f. RLDRAM3 Termination Guidelines

g.

QDRII/II+/II+ Xtreme SRAM Interface Guidelines

h. QDRII/II+/II+ Xtreme SRAM Termination Guidelines

i.

QDRIV SRAM Interface Guidelines

j.

QDRIV SRAM Termination Guidelines

Document Revision History

Section VI:

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Section I: Power

Documentation: Arria 10 Devices

Arria 10 Pin Out Files

Arria 10 GX, GT and SX Device Family Pin Connection Guidelines (PDF)

PowerPlay Power Analyzer Support Resources

Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)

AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (PDF)

AN 597: Getting Started Flow for Board Designs (PDF)

Known Arria 10 Issues

Index

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Plane/Signal

VCC

Index

Top of Section

Schematic Name Connection Guidelines

VCC supplies power to the core.

If the VCC PowerManager or SmartVID feature is not used, VCC, VCCP, and VCCERAM must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator.

You can operate -1 and -2 speed grade devices at

0.9V or 0.95V typical value. You can operate -3 speed grade device at only 0.9V typical value.

Operating at 0.95V results in higher core performance and higher power consumption. For more information about the performance and power consumption, refer to the Quartus II software timing reports and Arria 10 Early Power Estimator (EPE).

You have the option to source VCCR_GXB,

VCCT_GXB and VCCERAM from the same regulator as VCC when the power rails require the same voltage level. If the VCC PowerManager or SmartVID feature is used, VCCR_GXB, VCCT_GXB and

VCCERAM cannot be sourced from the same regulator.

Use the Arria 10 Early Power Estimator to determine the current requirements for VCC and other power supplies.

This supply may share power planes across multiple

Arria 10 devices.

For more information on the recommended operating conditions, refer to the Electrical Characteristics in the Arria 10 Device Datasheet (PDF).

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-4) (1-5) .

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Plane/Signal

VCCP

Schematic Name Connection Guidelines

VCCP supplies power to the periphery.

If the VCC

PowerManager or SmartVID feature is not used, VCC,

VCCP, and VCCERAM must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator.

You can operate -1 and -2 speed grade devices at 0.9V or 0.95V typical value. You can operate -3 speed grade device at only 0.9V typical value. Operating at 0.95V results in higher core performance and higher power consumption. For more information about the performance and power consumption, refer to the

Quartus II software timing reports and Arria 10 Early

Power Estimator (EPE).

You have the option to source VCCR_GXB, VCCT_GXB and VCCERAM from the same regulator as VCC when the power rails require the same voltage level. If the

VCC PowerManager or SmartVID feature is used,

VCCR_GXB, VCCT_GXB and VCCERAM cannot be sourced from the same regulator.

Use the Arria 10 Early Power Estimator to determine the current requirements for VCC and other power supplies.

This supply may share power planes across multiple

Arria 10 devices.

For more information on the recommended operating conditions, refer to the Electrical Characteristics in the

Arria 10 Device Datasheet (PDF).

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-4) (1-5) .

Index

Top of Section

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Plane/Signal

VCCIO([2][A,F,G,H,I,J,

K,L,AF,KL],

[3][A,

B,C,D,E,F,G,H,AB,GH])

(not all pins are available in each device

/ package combination)

Schematic Name Connection Guidelines

Connect these pins to 1.2V, 1.25V, 1.35V, 1.5V,

1.8V, 2.5V, or 3.0V supplies, depending on the I/O standard required by the specified bank.

2.5V and 3.0V is supported in specific device and package combinations. Not all I/O banks support

2.5V or 3.0V supplies. Not all devices support 3.0V

I/O standard.

When these pins require the same voltage level as

VCCPGM, you have the option to tie them to the same regulator as VCCPGM.

Not all I/O banks support 2.5V or 3.0V supplies.

Refer to

I/O and High Speed I/O in Arria 10 Devices

(PDF) for details.

This supply may share power planes across multiple

Arria 10 devices.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-4) (1-5) .

Index

Top of Section

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Plane/Signal

VCCPT

Schematic Name

VCCPGM

Connection Guidelines

Connect VCCPT to a 1.8V low noise switching regulator. You have the option to source the following from the same regulator as VCCPT:

• VCCH_GXB, VCCA_PLL with proper isolation filtering

• VCCBAT if it is using the same voltage level and the design security key feature is not required.

If you are not using HPS, do not share VCCPLL_HPS and

VCCIOREF_HPS with VCCPT.

This supply may share power planes across multiple

Arria 10 devices.

Provide a minimum decoupling of 1uF for the

VCCPT power rail near the VCCPT pin.

Connect these pins to a 1.2V, 1.5V, or 1.8V power supply. When dual-purpose configuration pins are used for configuration, tie VCCIO of the bank to the same regulator as VCCPGM, ranging from 1.2V, 1.5V, or 1.8V. When you do not use dual-purpose configuration pins for configuration, connect VCCIO to 1.2V, 1.25V, 1.35V, 1.5V, or

1.8V.

When these pins require the same voltage level as VCCIO, you have the option to tie them to the same regulator as VCCIO.

This supply may share power planes across multiple

Arria 10 devices.

Provide a minimum decoupling of 47nF for the

VCCPGM power rail near the VCCPGM pin.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-3) (1-5) .

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-5) .

Index

Top of Section

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Plane/Signal

VCCBAT

Schematic Name

VCCA_PLL

VCCERAM

Connection Guidelines

When using the design security volatile key, connect this pin to a non-volatile battery power source in the range of 1.2V - 1.8V.

When not using the volatile key, tie this pin to a supply ranging from more than 1.5V to 1.8V. If

1.8V is selected when the design security key is unused, you have the option to source this pin from the same regulator as VCCPT.

This pin must be properly powered as per the recommended voltage range as the POR circuitry of the Arria 10 devices monitors VCCBAT.

Provide a minimum decoupling of 47nF for the

VCCBAT power rail near the VCCBAT pin.

Connect VCCA_PLL to a 1.8V low noise switching regulator. With proper isolation filtering, you have the option to source VCCA_PLL from the same regulator as VCCPT.

This supply may share power planes across multiple

Arria 10 devices.

Connect all VCCERAM pins to a 0.9V or 0.95V linear or low noise switching power supply.

VCC, VCCP, and VCCERAM must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. When sharing the same regulator for VCCERAM, VCC, and

VCCP, the SmartVID or VCC Power Manager feature is not available. If you use the SmartVID feature, then VCC and VCCP need to be sourced by a dedicated regulator that is separate from the VCCERAM regulator.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-3) (1-5) .

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-3) (1-5) .

Index

Top of Section

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Plane/Signal

VREFB[[2][A,F,G,H,I,J,

K, L], [3][A,

B,C,D,E,F,G, H]]N0

(not all pins are available in each device / package combination)

Schematic Name Connection Guidelines

Input reference voltage for each I/O bank. If a bank uses a voltage referenced I/O standard, then these pins are used as the voltage-reference pins for the

I/O bank.

If VREF pins are not used, you should connect them to either the VCCIO in the bank where the pin resides or GND.

The following lists the four pairs of VREF pins that are shorted in the RF40 package of the Arria

10 GX devices that must be connected to the same voltage source:

• VREFB2AN0 and VREFB2FN0

• VREFB2KN0 and VREFB2LN0

• VREFB3AN0 and VREFB3BN0

• VREFB3GN0 and VREFB3HN0

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-5) .

Index

Top of Section

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Plane/Signal

VCCLSENSE

GNDSENSE

Index

Top of Section

Schematic Name Connection Guidelines

VCCLSENSE and GNDSENSE are differential remote sense pins for the VCC power.

Connect your regulators’ differential remote sense lines to the respective VCCLSENSE and

GNDSENSE pins. This compensates for the DC IR drop associated with the PCB and device package from the VCC power. Route these connections as differential pair traces and keep them isolated from any other noise source.

Connect VCCLSENSE and GNDSENSE lines to the regulator’s remote sense inputs when ICC current

>30A or when SmartVID and/or VCC Power

Manager feature is used.

VCCLSENSE and GNDSENSE line connections are optional if ICC current <=30A and both SmartVID and VCC Power Manager features are not used.

However, Altera recommends connecting the

VCCLSENSE and GNDSENSE for regulators that support remote sense line feature.

If not using the SmartVID or VCC Power Manager feature, leave VCCLSENSE and GNDSENSE pins unconnected.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

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Plane/Signal

VREFP_ADC

VREFN_ADC

Index

Top of Section

Schematic Name

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Connection Guidelines

Dedicated precision analog voltage reference.

Tie VREFP_ADC to an external 1.25V accurate reference source (+/- 0.2%) for better ADC performance. Treat VREFP_ADC as an analog signal that together with the

VREFN_ADC signal provides a differential

1.25V voltage. If no external reference is supplied, always connect VREFP_ADC to

GND. An on-chip reference source (+/-5%) is activated by connecting this pin to GND.

Do not drive VREFP_ADC pins until the

VCCA_PLL power rail has reached 1.62V to prevent damage.

Tie VREFN_ADC to the GND pin of an external 1.25V accurate reference source (+/-

0.2%) for better ADC performance. Treat

VREFN_ADC as an analog signal that together with the VREFP_ADC signal provides a differential 1.25V voltage. If no external reference is supplied, always connect

VREFN_ADC to GND.

Do not drive VREFN_ADC pins until the

VCCA_PLL power rail has reached 1.62V to prevent damage.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

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Plane/Signal

VSIGP_[0,1]

VSIGN_[0,1]

Schematic Name

Index

Top of Section

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Connection Guidelines

2 pairs of analog differential inputs pins used with the voltage sensor inside the FPGA to monitor external analog voltages.

Tie these pins to GND if not used.

Do not drive VSIGP and VSIGN pins until the

VCCA_PLL power rail has reached 1.62V to prevent damage.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

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Plane/Signal

RZQ_[#],

VID_EN

Schematic Name

Index

Top of Section

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Connection Guidelines

Calibrated on chip termination reference pins for I/O banks. The RZQ pins share the same

VCCIO with the I/O bank where they are located. The external precision resistor must be connected to the designated pin within the bank.

When using calibrated OCT, tie these pins to

GND through either a 240-

Ω or 100-Ω resistor, depending on the desired OCT impedance. Refer to I/O Features in Arria 10

Devices (PDF) for the OCT impedance options for the desired OCT scheme.

If not required for its dedicated function, this pin can be used as a regular I/O pin.

When not used as dedicated input for the external precision resistor or as an I/O, connect this pin to GND.

The VID_EN pin is not a physical pin.

The VID_EN pin is a multi-function shared pin with the RZQ_2A pin.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Page 16 of 142

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Plane/Signal

GND

Schematic Name

ADCGND

Index

Top of Section

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Connection Guidelines

All GND pins must be connected to the board ground plane.

Dedicated quiet ground.

If you are using voltage sensor, you must connect

ADCGND plane to board GND through a proper isolation filter with ferrite bead. Select the ferrite bead according to the frequency of the noise profile when it shows the maximum noise level.

If you are not using voltage sensor, isolation filter with ferrite bead is optional on GND rail.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 17 of 142

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Plane/Signal

VCCL_HPS

Schematic Name

VCCIO_HPS

Connection Guidelines

VCCL_HPS supplies power to the HPS core.

Connect all VCCL_HPS pins to a 0.9V/0.95V low noise switching regulator. Power up VCCL_HPS at

0.9V to support HPS processor speed at 1.2GHz or

0.95V to support HPS processor speed at 1.5GHz.

If you are not using HPS, do not share power with

FPGA. If you are not using HPS, you must connect

VCCL_HPS to GND.

This supply may share power planes across multiple

Arria 10 devices.

Connect these pins to a 1.8V, 2.5V, or 3.0V power supply, depending on the I/O standard required by the specified bank. If these pins have the same voltage requirement as VCCIO and VCCPGM, you have the option to source VCCIO_HPS pins from the same regulator as VCCIO and VCCPGM. If you are not using HPS, do not share power with FPGA.

If you are not using HPS, you must connect

VCCIO_HPS to GND.

This supply may share power planes across multiple

Arria 10 devices.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-5) (1-7) .

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-5) (1-6) .

Index

Top of Section

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Plane/Signal

VCCPLL_HPS

VCCIOREF_HPS

Schematic Name Connection Guidelines

VCCPLL_HPS supplies analog power to the HPS core PLLs.

Connect these pins to a 1.8V low noise switching power supply through a proper isolation filter. Share

VCCPLL_HPS with the same regulator as VCCPT when all power rails require 1.8V but only with a proper isolation filter. If you are not using HPS, do not share power with FPGA. If you are not using

HPS, you must connect VCCPLL_HPS to GND.

This supply may share power planes across multiple

Arria 10 devices.

HPS power supply for I/O pre-drivers.

The VCCIOREF_HPS pins require 1.8V. When these pins have the same voltage requirements as

VCCIO_HPS, you have the option to tie them to the same regulator. If these pins have the same voltage requirement as VCCPT, you have the option to tie them to the same regulator. If you are not using

HPS, do not share power with FPGA. If you are not using HPS, you must connect VCCIOREF_HPS to

GND.

This supply may share power planes across multiple

Arria 10 devices.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-3) (1-5) .

Verify Guidelines have been met or list required actions for compliance.

See Notes

(1-1)

(1-2) (1-5) (1-6) .

Index

Top of Section

Notes:

1-1. This worksheet does not calculate required decoupling, it is expected the designer will select decoupling based on analysis of power required and impedance of power path required based on static and switching current val ues. Refer to Altera’s

Power Delivery Network (PDN) Tool for

Arria 10 Devices for further information.

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Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and voltage drop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling.

1-2. This worksheet does not include power estimation for the different power supplies provided. Ensure each power supply is adequate for the device current requirements

. Refer to Altera’s

Early Power Estimation Tools and PowerPlay Power Analyzer Support Resources for further guidance.

Use

Altera’s

Early Power Estimation Tools to ensure the junction temperature of the device is within operating specifications based on your design activity.

1-3. Low Noise Switching Regulator is defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800kHz and 1MHz and has a fast transient response. The switching range is not an Altera requirement. However, Altera does require the Line Regulation and Load Regulation meet the following specifications:

Line Regulation < 0.4%.

Load Regulation < 1.2%

1-4. Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.

1-5. Decoupling for these pins depends on the decoupling requirements of the specific board.

1-6. The number of modular I/O banks on Arria 10 devices depends on the device density. For the indexes available for a specific device, refer to the I/O Bank section in the Arria 10 handbook.

1-7. Examples 6, Example 7 and Figures 6 and Figure 7 in the Arria 10 GX, GT and SX Device Family Pin Connection Guidelines (PDF) illustrate power supply sharing guidelines for the Arria 10 SX devices.

1-8. Examples 11 and Figures 11 in the Arria 10 GX, GT and SX Device Family Pin Connection Guidelines (PDF) illustrate power supply sharing guidelines using the SmartVID feature.

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Additional Comments:

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Section II: Configuration

Arria 10 Recommended Reference Literature/Tool List

Arria 10 Pin Out Files

Arria 10 GX, GT and SX Device Family Pin Connection Guidelines (PDF)

Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices (PDF)

JTAG Boundary-Scan Testing in Arria 10 Devices (PDF)

USB-Blaster Download Cable User Guide (PDF)

ByteBlaster II Download Cable User Guide (PDF)

EthernetBlaster II Communications Cable User Guide (PDF)

AN 597: Getting Started Flow for Board Designs (PDF)

Index

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Configuration Scheme

Plane/Signal Schematic Name

nIO_PULLUP

Configuration Voltage

Connection Guidelines

Dedicated input pin that determines the internal pull-ups on user I/O pins and dual-purpose I/O pins

(DATA[0:31], CLKUSR, INIT_DONE, DEV_OE, and DEV_CLRn) are on or off before and during configuration. A logic high turns off the weak pullup, while a logic low turns on the weak pull-up.

Tie the nIO-PULLUP pin directly to VCCPGM using a 1 kΩ pull-up resistor, or directly to GND. This pin has an internal 25kΩ pull-down.

If you tie this pin to VCCPGM, ensure all user I/O pins and dual-purpose I/O pins are at a valid logic

(0 or 1) before and during configuration.

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Plane/Signal

MSEL[0:2]

Schematic Name

nCE

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Connection Guidelines

These pins are internally connected through a

25kΩ resistor to GND. Do not leave these pins floating.

When these pins are unused connect them to

GND.

Depending on the configuration scheme used these pins should be tied to VCCPGM or

GND. Refer to

Configuration, Design Security, and Remote System Upgrades in Arria10

Devices (PDF) for the configuration scheme options.

If only JTAG configuration is used, connect these pins to ground.

Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled.

In multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the nCE of the next device in the chain. In single device configuration and JTAG programming, nCE should be connected to

GND or through a 10kΩ pull-down to GND if using an Active Serial header.

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Plane/Signal

nCONFIG

Schematic Name

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Connection Guidelines

Dedicated configuration control input. Pulling this pin low during user-mode will cause the

FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level will initiate reconfiguration. nCONFIG should be connected directly to the configuration controller when the FPGA uses a passive configuration scheme, or through a

10kΩ resistor tied to VCCPGM when using an active serial configuration scheme.

If this pin is not used, it requires a connection directly or through a 10kΩ resistor to

VCCPGM.

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Plane/Signal

CONF_DONE

Schematic Name Connection Guidelines

This is a dedicated configuration done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts,

CONF_DONE is released. As a status input,

CONF_DONE goes high after all data is received. Then the device initializes and enters user mode.

It is not available as a user I/O pin.

Use an external 10kΩ pull-up resistor to

VCCPGM.

Connect an external 10kΩ pull-up resistors to

VCCPGM. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host.

When using passive configuration schemes this pin should also be monitored by the configuration controller.

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Plane/Signal

nCEO

Schematic Name

nSTATUS

Connection Guidelines

During multi-device configuration, this pin feeds the nCE pin of a subsequent device.

Connect this pin to an external 10kΩ pull-up resistor to VCCPGM. During single device configuration, this pin may be left floating.

This pin is not available for regular I/O usage in multi-device configuration mode, see rd04132011_29 .

This is a dedicated configuration status pin.

The FPGA drives nSTATUS low immediately after power-up and releases it after POR time.

As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin.

Connect an external 10kΩ pull-up resistors to

VCCPGM. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host.

When using Passive configuration schemes this pin should also be monitored by the configuration controller.

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Plane/Signal

TCK

Schematic Name

TMS

TDI

Connection Guidelines

Connect this pin to a 1kΩ pull-down resistor to GND. This pin has an internal 25kΩ pulldown.

Do not drive voltage higher than 1.8-, 1.5-, or

1.2-V VCCPGM supply for the TCK pin. The

TCK input pin is powered by the VCCPGM supply.

Treat this signal like a clock and follow typical clock routing guidelines.

Connect this pin to a 1kΩ - 10-kΩ pull-up resistor to VCCPGM.

If the JTAG interface is not used, connect the

TMS pin to VCCPGM using a 1kΩ resistor.

This pin has an internal 25kΩ pull-up.

Do not drive voltage higher than 1.8-, 1.5-, or

1.2-V VCCPGM supply for the TMS pin. The

TMS input pin is powered by the VCCPGM supply.

Connect this pin to a 1kΩ - 10-kΩ pull-up resistor to VCCPGM.

If the JTAG interface is not used, connect the

TDI pin to VCCPGM using a 1kΩ resistor.

This pin has an internal 25kΩ pull-up.

Do not drive voltage higher than 1.8-, 1.5-, or

1.2-V VCCPGM supply for the TDI pin. The

TDI input pin is powered by the VCCPGM supply.

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Plane/Signal

TDO

Schematic Name

TRST

Connection Guidelines

If the JTAG interface is not used, leave the TDO pin unconnected.

In cases where TDO uses VCCPGM = 1.8 V to drive a 3.3V JTAG interface, there may be leakage current in the TDI input buffer of the interfacing devices. An external pull-up resistor tied to 3.3 V on their TDI pin may be used to eliminate the leakage current if needed.

Utilization of the TRST pin is optional. If you do not use this pin, tie this pin through a 1-k

Ω pull-up resistor to VCCPGM.

When you use this pin, ensure that the TMS pin is held high or the TCK pin is static when the TRST pin is changing from low to high.

To disable the JTAG circuitry, tie this pin to

GND. This pin has an internal 25kΩ pull-up.

Do not drive voltage higher than 1.8-, 1.5-, or

1.2-V VCCPGM supply for the TRST pin. The

TRST input pin is powered by the VCCPGM supply.

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Optional Dual Purpose Pins

Plane/Signal

nCSO[0:2]

DCLK

Schematic Name Connection Guidelines Comments / Issues

Dedicated output control signal from the

FPGA to the EPCQ-L device in AS configuration scheme that enables the

EPCQ-L device.

When you are not programming the FPGA in the AS configuration scheme, the nCSO pin is not used. When you do not use this pin as an output pin, leave this pin unconnected.

Dedicated configuration clock pin. In PS and

FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In AS mode, DCLK is an output from the FPGA that provides timing for the configuration interface.

Do not leave this pin floating. Drive this pin either high or low.

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Plane/Signal

CRC_ERROR

Schematic Name Connection Guidelines

Active high signal indicates the error detection circuit has detected errors in the configuration

RAM (CRAM) bits.

Falling edge of this signal indicates the information about the error location and type are available in the error message register

(EMR).

This dual-purpose pin is only used when you enable error detection in user mode.

This pin can be used as a user I/O pin.

When using as optionally open-drain output dual-purpose CRC_ERROR pin, connect this pin to an external 10kΩ pull-up resistor to

VCCPGM.

When not using as the dual-purpose

CRC_ERROR pin, and when not using as a user I/O, connect this pin as defined in the

Quartus II software.

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External Memory

Interface Pins

Plane/Signal

AS_DATA0 / ASDO

AS_DATA[1:3]

Schematic Name

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Connection Guidelines

Dedicated AS configuration pin. When using an EPCQ-L device (x1 mode) this is the

ASDO pin and used to send address and control signals between the FPGA and the

EPCQ-L.

When not programming the device in AS mode ASDO is not used. Also, when this pin is not used it is recommended to leave the pin unconnected.

Dedicated AS configuration data pins.

Configuration data is transported on these pins when connected to the EPCQ-L devices.

When this pin is not used it is recommended to leave the pin unconnected.

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Partial Reconfiguration

Pins

Plane/Signal

PR_REQUEST

PR_READY

PR_ERROR

Schematic Name

Index

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Connection Guidelines

Partial Reconfiguration Request pin. Drive this pin high to start partial reconfiguration. Drive this pin low to end reconfiguration. This pin can only be used in Partial Reconfiguration using external host mode in FPP x16 configuration scheme.

When the dedicated input PR_REQUEST is not used and this pin is not used as an I/O, then it is recommended to tie this pin to GND.

When using as optionally open-drain output dedicated PR_READY pin, connect this pin to an external 10kΩ pull-up resistor to

VCCPGM. When not using as the dedicated

PR_READY optionally open-drain output, and when this pin is not used as an I/O pin, then connect this pin as defined in the Quartus II software.

When using as optionally open-drain output dedicated PR_ERROR pin, connect this pin to an external 10kΩ pull-up resistor to

VCCPGM. When not using as the dedicated

PR_ERROR optionally open-drain output, and when this pin is not used as an I/O pin, then connect this pin as defined in the Quartus II software.

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Plane/Signal

PR_DONE

Schematic Name

CvP_CONFDONE

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Connection Guidelines

When using as optionally open-drain output dedicated PR_DONE pin, connect this pin to an external 10kΩ pull-up resistor to

VCCPGM. When not using as the dedicated

PR_DONE optionally open-drain output, and when this pin is not used as an I/O pin, then connect this pin as defined in the Quartus II software.

When using as optionally open-drain output dedicated CvP_CONFDONE pin, connect this pin to an external 10kΩ pullup resistor to

VCCPGM. When not using as the dedicated

CvP_CONFDONE optionally open-drain output, and when this pin is not used as an

I/O pin, then connect this pin as defined in the

Quartus II software.

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Plane/Signal

DEV_CLRn

Schematic Name

DEV_OE

DATA0

DATA[1:31]

Connection Guidelines

This pin is optional and allows you to override all clears on all device registers. When the dual-purpose input DEV_CLRn is not used and this pin is not used as an I/O then it is recommended to tie this pin to ground.

This pin is optional and allows you to override all tri-states on the device. When the dualpurpose input DEV_OE is not used and this pin is not used as an I/O then it is recommended to tie this pin to ground.

Dual-purpose configuration data input pin.

The DATA0 pin can be used for PS or FPP configuration or as an I/O pin after configuration is complete.

When the dedicated input for DATA[0] is not used and this pin is not used as an I/O then it is recommended to leave this pin unconnected.

Dual-purpose configuration input data pins and user I/O pins after configuration.

For FPP x8 use DATA[1:7]

For FPP x16 use DATA[1:15]

For FPP x32 use DATA[1:31]When the dualpurpose inputs for DATA[1:31] are not used and these pins are not used as an I/O then it is recommended to leave these pins unconnected.

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Plane/Signal

INIT_DONE

Schematic Name Connection Guidelines

This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE.

When using as optionally open-drain output dedicated INIT_DONE pin, a transition from low to high at the pin indicates when the device has entered user mode. The

INIT_DONE pin cannot be used as a user I/O pin after configuration. Connect this pin to an external 10kΩ pull-up resistor to VCCPGM.

When using in an AS or PS multi-device configuration mode ensure INIT_DONE is enabled in the Quartus II design.

When not using as the dedicated INIT_DONE pin, and when this pin is not used as an I/O pin, then connect this pin as defined in the

Quartus II software.

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Plane/Signal

CLKUSR

Schematic Name Connection Guidelines

This pin is used as the clock for transceiver calibration, and is a mandatory requirement when using transceivers.

This pin is optionally used for EMIF HMC calibration, as well as a configuration clock input for synchronizing the initialization of more than one device.

This pin can be used as a user I/O pin only if you are not using transceivers, not using EMIF HMC, and not using this pin as a usersupplied configuration clock.

If you are using the CLKUSR pin for configuration and transceiver calibration, you must supply an external free running and stable clock to the CLKUSR pin at start of device configuration. If the clock is not present at device powerup,transceiver calibration will be delayed until the clock is available. This may impact protocol compliance. You need to ensure supplying the CLKUSR pin with a common clock frequency that is applicable for both the configuration mode and transceiver calibration.

If you are not using the CLKUSR pin for configuration but using the CLKUSR pin for transceiver calibration, you must supply an external free running and stable clock to the

CLKUSR pin at start of device configuration. If the clock is not present at device power-up, transceiver calibration will be delayed until the clock is available. This may impact protocol compliance.

If you are using the CLKUSR pin for configuration but not using the CLKUSR pin for transceiver calibration, you must use a user-supplied clock input. For more information, refer to the Configuration, Design Security, and Remote System

Upgrades for Arria 10 Devices chapter.

Connect the CLKUSR pin to GND if you are not using the

CLKUSR pin for any of configuration clock input, transceiver/EMIF HMC calibration clock or an I/O pin.

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Plane/Signal

JTAG Header

Schematic Name Connection Guidelines

Power the EthernetBlaster II, ByteBlaster II or

USB-

Blaster cable’s VCC (pin 4 of the header) with VCCPT.

For multi-device JTAG chains with different

VCCIO voltages, voltage translators may be required to meet the I/O voltages for the devices in the chain and JTAG header.

The EthernetBlaster II, ByteBlaster II and

USB-Blaster cables do not support a target supply voltage of 1.2 V. For the target supply voltage value, refer to the EthernetBlaster II

Communications Cable User Guide,

ByteBlaster II Download Cable User Guide and the USB-Blaster Download Cable User

Guide.

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HPS Configuration

Plane/Signal

BOOTSEL[2:0]

(Arria 10 SX device variants only)

HPS_CLK1

(Arria 10 SX device variants only)

Index

Top of Section

Schematic Name Connection Guidelines

During a cold reset this signal is sampled as a boot select input.

These pins can be used as slow speed interface signals or GPIO after HPS boot-up. Please verify the connection by Quartus II project with HPS in Qsys.

Connect a pull-up or pull-down resistor such as 4.7kΩ to select the desired boot select values. This resistor will not interfere with the slow speed interface signals that could share this pin.

Refer to the Booting and Configuration appendix in the

Arria 10 Device Handbook for Boot Select values.

Ensure the selected boot device is present on the schematic.

Dedicated clock input pin that drives the main PLL.

This provides clocks to the MPU, L3/L4 sub-systems, debug sub-system and the Flash controllers. It can also be programmed to drive the peripheral.

Connect a single-ended clock source to this pin. The

I/O standard of the clock source must be compatible with VCCIO_HPS. Refer to the valid frequency range of the clock source in Arria 10 Device Datasheet. The input clock must be present at this pin for HPS operation.

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Plane/Signal

HPS_nPOR

(Arria 10 SX device variants only)

Index

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Schematic Name Connection Guidelines

Cold reset to the HPS block. Active low input that will reset all HPS logics that can be reset.

Places the HPS in a default state sufficient for software to boot. This pin has a dedicated internal 25kΩ pull-up resistor.

Connect this pin through a 1kΩ - 10-kΩ pull-up resistor to VCCIO_HPS.

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Additional Comments:

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Section III: Transceiver

Arria 10 Recommended Reference Literature

Index

Arria 10 Pin Out Files

Arria 10 GX, GT and SX Device Family Pin Connection Guidelines (PDF)

Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)

AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (PDF)

AN 597: Getting Started Flow for Board Designs (PDF)

Known Arria 10 Issues

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Plane/Signal

VCCH_GXB[L,R]

Schematic Name Connection Guidelines

Analog power, block level TX buffers.

Connect VCCH_GXB to 1.8V low noise switching regulator. With a proper isolation filtering, you have the option to source

VCCH_GXB from the same regulator as

VCCPT.

VCCH_GXB is side-based power rail. When you do not use the whole side of the transceiver banks, VCCH_GXB can be grounded only if related I/O banks do not use

LVDS, DDR, PLL and I/O calibration features.

If you need to use PLL, VCCH_GXB cannot be grounded.

Provide a minimum decoupling of 2.2nF for the VCCH_GXB power rail near the

VCCH_GXB pin.

When implementing a filtered supply topology, you must consider the IR drop across the filter. For designs that have high-current for

VCCH_GXB you should consider the IR drop through the supply planes and compensate for it.

Comments / Issues

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See Notes ( 3-1 ) ( 3-2 ) ( 3-3 ) ( 3-4 ) ( 3-6 )

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Plane/Signal

VCCT_GXB[L1,R4][C,D,E,F

,G,H,I,J]

(not all pins are available in each device / package combination)

Schematic Name Connection Guidelines

Analog power, transmitter, specific to the left (L) side or right (R) side of the device.

Connect VCCT_GXB pins to a 0.9V, 1.0V, or 1.1V low noise switching regulator. For transceivers data rates in

respect to each voltage level, refer to the

Notes to Power

Supply Sharing Guidelines

at the end of this section.

With a proper isolation filtering, VCCT_GXB can be shared with VCCP and VCC power when these voltages are at the same level. When VCCT_GXB is shared with

VCC and VCCP, the VCC Power Manager and SmartVID features cannot be used.

For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30dB of VCCT_GXB[L,R] isolation for a 1MHz to 100MHz bandwidth. When

VCCT_GXB is shared with VCC and VCCP, the VCC

Power Manager and SmartVID features cannot be used.

VCCR_GXB and VCCT_GXB pins in the same bank of the device must have the same voltage. Most

VCCR_GXB and VCCT_GXB pins that are associated with unused transceiver channels can be connected to GND on a per side basis. To minimize power consumption of your specific design, Altera recommends connecting these pins to GND according to the Quartus II Pin-Out File Report for your project.

Contact Altera Service for details.

When implementing a filtered supply topology, you must consider the IR drop across the filter. For designs that have high-current for VCCT_GXB you should consider the IR drop through the supply planes and compensate for it.

Comments / Issues

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See Notes ( 3-1 ) ( 3-2 ) ( 3-3 )

( 3-4 ) ( 3-6 )

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Decoupling for these pins depends on the design decoupling requirements of the specific board design.

Page 45 of 142

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Plane/Signal

VCCR_GXB[L1,R4][C,D,E,

F,G,H,I,J]

(not all pins are available in each device / package combination)

Schematic Name Connection Guidelines

Analog power, receiver, specific to the left (L) side or right (R) side of the device.

Connect VCCR_GXB pins to a 0.9V, 1.0V, or 1.1V low noise switching regulator. For transceivers data rates in

respect to each voltage level, refer to the

Notes to Power

Supply Sharing Guidelines

at the end of this section.

With a proper isolation filtering, VCCR_GXB can be shared with VCCP and VCC power when these voltages are at the same level. When VCCR_GXB is shared with

VCC and VCCP, the VCC Power Manager and SmartVID features cannot be used.

For better performance and in order to meet PCIe Gen 3 jitter specifications, isolate VCCR_GXB and VCCT_GXB from each other with at least 30dB of VCCT_GXB[L,R] isolation for a 1MHz to 100MHz bandwidth. When

VCCR_GXB is shared with VCC and VCCP, the VCC

Power Manager and SmartVID features cannot be used.

VCCR_GXB and VCCT_GXB pins in the same bank of the device must have the same voltage. Most

VCCR_GXB and VCCT_GXB pins that are associated with unused transceiver channels can be connected to

GND on a per side basis. To minimize power consumption of your specific design, Altera recommends connecting these pins to GND according to the Quartus II

Pin-Out File Report for your project. Contact Altera

Service for details.

When implementing a filtered supply topology, you must consider the IR drop across the filter. For designs that have high-current for VCCH_GXB you should consider the IR drop through the supply planes and compensate for it.

Decoupling for these pins depends on the design decoupling requirements of the specific board design.

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See Notes ( 3-1 ) ( 3-2 ) ( 3-3 )

( 3-4 ) ( 3-6 )

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Plane/Signal

REFCLK_GXB[L1,R4][C,D,E,

F,G,H,I,J]_CH[B,T]p/n

(not all pins are available in each device / package combination)

Schematic Name Connection Guidelines

High speed differential reference clock positive and negative receiver pins, specific to the left (L) side or right (R) side of the device.

These pins should be AC-coupled or DC-coupled when used. For HCSL I/O standard, it only supports

DC coupling. . In the PCI Express configuration, DCcoupling is allowed on the REFCLK if the selected

REFCLK I/O standard is HCSL

REFCLK_GXB can be used as dedicated clock input pins with fPLL for core clock generation even when the transceiver channel is not available.

Connect all unused pins either individually to GND or tie all unused pins together through a single 10kΩ resistor to GND. Ensure that the traces from the pins to the resistor(s) are as short as possible.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

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3-5

)

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Plane/Signal

GXB[L1,R4][C,D,E,F,G,H,I,J]_

RX_[0:5]p/n,

GXB[L1,R4][C,D,E,F,G,H,I,J]_

REFCLK_CH[0:5]p/n

(not all pins are available in each device / package combination)

Schematic Name Connection Guidelines

High speed positive and negative differential receiver or differential reference clock channels. Specific to the left

(L) side or right (R) side of the device

These pins may be AC-coupled or DC-coupled when used.

Connect all unused GXB_RXp pins directly to GND,

VCCR_GXB, or VCCT_GXB pins.

Connect all unused GXB_RXn pins directly to GND.

Comments/ Issues

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)

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Plane/Signal

GXB[L1,R4][C,D,E,F,G,H,I,J]_TX

_CH[0:5]p

/n

(not all pins are available in each device / package combination)

Schematic Name Connection Guidelines

High speed positive or negative differential transmitter channels. Specific to the left (L) side or right (R) side of the device.

Leave all unused GXB_TX pins floating.

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Plane/Signal

RREF_[T,B][L,R]

Schematic Name Connection Guidelines

Reference resistor for fPLL, IOPLL, and

Transceiver. Connect these pins via individual 2kΩ +/- 1% resistor to GND.

If any REFCLK pin or transceiver channel on one side (left or right) of the device is used, you must connect each RREF pin on that side of the device to its own individual 2kΩ resistor to GND.

Otherwise, you can connect each RREF pin on that side of the device directly to GND.

In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals.

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Plane/Signal

CLKUSR

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Schematic Name Connection Guidelines

This pin is used as the clock for transceiver calibration, and is a mandatory requirement when using transceivers.

This pin is optionally used for EMIF HMC calibration, as well as a configuration clock input for synchronizing the initialization of more than one device.

This pin can be used as a user I/O pin only if you are not using transceivers, not using EMIF HMC, and not using this pin as a usersupplied configuration clock.

If you are using the CLKUSR pin for configuration and transceiver calibration, you must supply an external free running and stable clock to the CLKUSR pin at start of device configuration. If the clock is not present at device power-up,transceiver calibration will be delayed until the clock is available. This may impact protocol compliance.

You need to ensure supplying the CLKUSR pin with a common clock frequency that is applicable for both the configuration mode and transceiver calibration.

If you are not using the CLKUSR pin for configuration but using the CLKUSR pin for transceiver calibration, you must supply an external free running and stable clock to the

CLKUSR pin at start of device configuration. If the clock is not present at device power-up, transceiver calibration will be delayed until the clock is available. This may impact protocol compliance.

If you are using the CLKUSR pin for configuration but not using the CLKUSR pin for transceiver calibration, you must use a user-supplied clock input. For more information, refer to the Configuration, Design Security, and Remote System

Upgrades for Arria 10 Devices chapter.

Connect the CLKUSR pin to GND if you are not using the

CLKUSR pin for any of configuration clock input, transceiver/EMIF HMC calibration clock or an I/O pin.

Comments / Issues

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Plane/Signal

nPERST[L,R][0:1]

Schematic Name Connection Guidelines

Dual-purpose fundamental reset pin is only available when used in conjunction with PCIe

HIP. One nPERST pin is used per PCIe HIP.

When the pin is low, the transceivers are in reset. When the pin is high, the transceivers are out of reset. When this pin is not used as the fundamental reset, this pin may be used as a user I/O pin. Connect this pin as defined in the Quartus II software.

This pin is powered by 1.8V supply and must be driven by 1.8V compatible I/O standards.

Connect the PCIe nPERST pin to a level translator to shift down the voltage from 3.3V

LVTTL to 1.8V to interface with this pin.

Only one nPERST pin is used per PCIe HIP.

4 pins are listed here, but some specific component might only have 2 PCIe HIPs. nPERSTL0 = Bottom Left PCIe HIP & CvP; nPERSTL1 = Top Left PCIe HIP (When available); nPERSTR0 = Bottom Right PCIe HIP (When available); nPERSTR1 = Top Right PCIe HIP (When available);

For maximum compatibility, always use the bottom left PCIe HIP first, as this is the only location that supports Configuration via

Protocol (CvP) using the PCIe link.

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Notes:

3-1. Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and voltage droop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages.

Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To assist in decoupling analysis, Altera's Power Delivery Network (PDN) Tool for Arria 10 Devices serves as an excellent decoupling analysis tool.

3-2. Use the Early Power Estimation Tools to determine the current requirements for VCC and other power supplies. Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via.

3-3. These supplies may share power planes across multiple Stratix V devices.

3-4. Low Noise Switching Regulator - defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800kHz and 1MHz and has fast transient response. The switching range is not an Altera requirement. However, Altera does require the Line Regulation and Load Regulation meet the following specifications:

Line Regulation < 0.4%.

Load Regulation < 1.2%.

3-5. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires the AC-coupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.

3-6. Examples 1 - 10 and Figures 1 - 8 in the Arria 10 GX, GT and SX Device Family Pin Connection Guidelines (PDF) illustrate power supply sharing guidelines that are data rate dependent.

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Notes to Power Supply Sharing Guidelines:

1.VCCR_GXB and VCCT_GXB must be at least 0.9V for the following transceiver data rates:

• Arria 10 GX(**) and SX(**) devices: ≤10.3125 Gbps/6.5536 Gbps for backplane applications and ≤11.3 Gbps/8 Gbps for chip-to-chip applications.

• Arria 10 GT(***) devices: ≤10.3125 Gbps for backplane applications and ≤11.3 Gbps for chip-to-chip applications.

When VCCR_GXB and VCCT_GXB is 0.9V, they may share the same regulator as VCC and VCCP with proper filtering, if VCC and VCCP is at the same voltage level.

2. Assumes VCCIO, VCCPGM are 1.8V. Only if these power rails share the same regulator as VCCPT can their power sequence ramp with VCCPT in Group 2. If any of these rails are other than 1.8V, then these rails must be separately regulated and must follow the power sequence requirement in Group 3. For more information about the power sequence requirements, refer to the

Power Management for Arria 10 Devices

chapter.

3. The VCC Power Manager and SmartVID features are supported for VCC and VCCP. In these cases, VCC and VCCP can be 0.83V-0.9V depending on the device requirements. The VCC Power Manager and SmartVID features are not supported when VCCR_GXB and VCCT_GXB are shared with VCC and VCCP.

4. VCCR_GXB and VCCT_GXB must be at least 1.0V for the following transceiver data rates:

• Arria 10 GX(**) and SX(**) devices: 10.3125 Gbps/6.5536 Gbps < data rate ≤ 16.0 Gbps/14.2 Gbps/12.5 Gbps/8 Gbps for backplane applications and 11.3

Gbps/8 Gbps < data rate ≤ 17.4 Gbps/15 Gbps/14.2 Gbps/12.5 Gbps/8 Gbps for chip-to-chip applications.

• Arria 10 GT(***) devices: 10.3125 Gbps < data rate ≤ 14.2 Gbps/12.5 Gbps for backplane applications and 11.3 Gbps < data rate ≤ 15 Gbps/14.2 Gbps/12.5

Gbps for chip-to-chip applications.

5. The Arria 10 GT devices with transceiver data rate ≤ 11.3 Gbps for chip-to-chip applications (10.3125 Gbps for backplane applications) and transceiver data rate

11.3 Gbps < data rate ≤ 15 Gbps/14.2 Gbps/12.5 Gbps for chip-to-chip applications (10.3125 Gbps < data rate ≤ 14.2 Gbps/12.5 Gbps for backplane applications), the maximum transceiver channel supported on non 28.3 Gbps transceiver side is 48 channels.

6. VCCR_GXB and VCCT_GXB must be at least 1.1V for the following transceiver data rates (applicable only to Arria 10 GT devices):

• For 15 Gbps/14.2 Gbps/12.5 Gbps < data rate ≤ 17.4 Gbps/15 Gbps for chip-to-chip applications, the maximum transceiver channel supported is 80 channels.

• For 15 Gbps/14.2 Gbps/12.5 Gbps < data rate ≤ 28.3 Gbps/26 Gbps/20 Gbps for chip-to-chip applications, the maximum transceiver channel supported is 16 channels.

• For 14.2 Gbps/12.5 Gbps/10.3125 Gbps < data rate ≤ 17.4 Gbps/14.2 Gbps for backplane applications, the maximum transceiver channel supported is 96 channels.

(**)Actual transceiver data rate for the Arria 10 GX and SX devic es is dependent on the device’s transceiver speed grade and core speed grade. Valid combinations of transceiver and core speed grades are as follows:

• For -1 transceiver and -1 core speed grades

– the maximum data rate is 17.4 Gbps for chip-to-chip applications and 16 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.0V.

– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.

• For -2 transceiver and -1 core speed grades

– the maximum data rate is 15 Gbps for chip-to-chip applications and 14.2 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.0V.

– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.

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• For -3 transceiver and -2 core speed grades

– the maximum data rate is 14.2 Gbps for chip-to-chip applications and 12.5 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.0V.

– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.

• For -4 transceiver and -3 core speed grades

– the maximum data rate is 12.5 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.0V.

– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.

• For -5 transceiver and -3 core speed grades

– the maximum data rate is 8 Gbps for chip-to-chip applications and 6.5536 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.0V/0.9V.

(***)Actual transceiver data rate for the Arria 10 GT device is dependent on the device’s transceiver speed grade and core speed grade. Valid combinations of transceiver and core speed grades are as follows:

• For -2 transceiver and -1 core speed grades

– the maximum data rate is 28.3 Gbps for chip-to-chip applications and 17.4 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.1V.

– the maximum data rate is 15 Gbps for chip-to-chip applications and 14.2 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.0V.

– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.

• For -3 transceiver and -2 core speed grades

– the maximum data rate is 26 Gbps for chip-to-chip applications and 14.2 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.1V.

– the maximum data rate is 14.2 Gbps for chip-to-chip applications and 12.5 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.0V.

– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.

• For -4 transceiver and -3 core speed grades

– the maximum data rate is 20 Gbps for chip-to-chip applications and 14.2 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.1V.

– the maximum data rate is 12.5 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 1.0V.

– the maximum data rate is 11.3 Gbps for chip-to-chip applications and 10.3125 Gbps for backplane applications when VCCR_GXB/VCCT_GXB is 0.9V.

The voltage level for each power rail is preliminary.

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Reviewed against Errata Sheet for Arria 10 Devices (PDF) version:

Additional Comments:

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Section IV: I/O

Literature: Arria 10 Devices

Index

Arria 10 Pin Out Files

Arria 10 GX, GT and SX Device Family Pin Connection Guidelines (PDF)

Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)

Known Arria 10 Issues

AN 597: Getting Started Flow for Board Designs (PDF)

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Part A: Clock Pins

Plane/Signal

CLK_[2,3][A,B,C,D,E,F,G,

H,I,J,K,L]_[0,1]p

(not all pins are available in each device / package combination)

Schematic Name Connection Guidelines

Multi-purpose pins with the following functionality:

- Dedicated high speed positive differential clock or differential data input with OCT Rd support.

- Single ended clock or data input with OCT Rt support.

- Single ended output with OCT Rs support.

Use dedicated clock pins to drive clocks into the device. These pins can connect to the device

PLLs using dedicated routing paths or global networks. Refer to

Clock Networks and PLLs in

Arria 10 devices (PDF) for further information on dedicated routing of clock pins to PLLs.

Unused pins can be tied to GND or left unconnected. If unconnected, use the Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

Comments / Issues

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See Note (4-1) .

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Plane/Signal

CLK_[2,3][A,B,C,D,E,F,G,

H,I,J,K,L]_[0,1]n

(not all pins are available in each device / package combination)

Schematic Name Connection Guidelines

Multi-purpose pins with the following functionality:

- Dedicated high speed negative differential clock or differential data input with OCT Rd support.

- Single ended clock or data input with OCT Rt support.

- Single ended output with OCT Rs support.

The programmable weak pull up resistor is available for single ended I/O usage.

Use dedicated clock pins to drive clocks into the device. When used as single ended clock inputs, these pins can connect to the device PLLs using global networks. These pins do not have dedicated routing paths to the PLLs. Refer to

Clock Networks and PLLs in Arria 10 devices

(PDF) for further information on dedicated routing of clock pins to PLLs.

Unused pins can be tied to GND or left unconnected. If unconnected, use the Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

Comments / Issues

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See Note (4-1) .

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Plane/Signal

PLL_[2,3][A,B,C,D,E,F

,G,H,I,J,K,L]_FB[0,1]

(not all pins are available in each device / package combination)

Schematic Name Connection Guidelines

Dual purpose I/O pins that can be used as single-ended external feedback input pin.

If not used for dedicated PLL feedback input, these pins are available for regular singleended I/O usage.

Unused pins can be tied to GND or left unconnected. If unconnected, use the

Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

Comments / Issues

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See Note

(4-1) .

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Plane/Signal

PLL_[2,3][A,B,C,D,E,F

,G,H,I,J,K,L]_CLKOUT

[0:1],

PLL_[2,3][A,B,C,D,E,F

,G,H,I,J,K,L]_CLKOUT

[0,1]p

(not all pins are available in each device / package combination)

PLL_[2,3][A,B,C,D,E,F

,G,H,I,J,K,L]_CLKOUT

[0,1]n

(not all pins are available in each device / package combination)

Schematic Name

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Dual purpose I/O pins that can be used as:

Two single ended clock output pins, or

One differential clock output pair

If not used for their dedicated PLL feedback input or output functionality, these pins are available for regular single ended I/O usage, or as a differential transmitter/receiver.

Unused pins can be tied to GND or left unconnected. If unconnected, use the

Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

Comments / Issues

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(4-1) .

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Additional Comments:

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Part B: Dedicated and Dual Purpose Pins

Plane/Signal

RZQ_[#],

VID_EN

Schematic Name

(number of RZQ pins is device / package combination specific)

Connection Guidelines

Calibrated on chip termination reference pins for I/O banks. The RZQ pins share the same

VCCIO with the I/O bank where they are located. The external precision resistor must be connected to the designated pin within the bank.

When using calibrated OCT, tie these pins to

GND through either a 240-

Ω or 100-Ω resistor, depending on the desired OCT impedance. Refer to I/O Features in Arria 10

Devices (PDF) for the OCT impedance options for the desired OCT scheme.

If not required for its dedicated function, this pin can be used as a regular I/O pin.

When not used as dedicated input for the external precision resistor or as an I/O, connect this pin to GND.

The VID_EN pin is not a physical pin.

The VID_EN pin is a multi-function shared pin with the RZQ_2A pin.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(4-1) .

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Plane/Signal

DNU

Schematic Name

NC

TEMPDIODEp

TEMPDIODEn

Additional Comments:

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Connection Guidelines

Do not connect to power or ground or any other signal; these pins must be left unconnected.

Do not drive signals into these pins.

When designing for device migration these pins may be connected to power, ground, or a signal trace depending on the pin assignment of the devices selected migration. However, if device migration is not a concern leave these pins unconnected. See Knowledge Database solution rd03132006_933 .

Pins used in conjunction with the temperaturesensing diode inside the Stratix V device.

TEMPDIODEp is the bias-high input,

TEMPDIODEn is the bias-low input.

If the temperature-sensing diode is not used with an external temperature sensing device, connect these pins to GND.

Refer to

Power Management in Arria 10

Devices (PDF) for a list of external temperature sensing devices that are compatible with the temperature sensing diode.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

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Part C: Dual Purpose Differential I/O pins

Plane/Signal

LVDS[2,3][A,B,C,D,E,

F,G,H,I,J,K,L]_[1:24]p,

Schematic Name

LVDS[2,3][A,B,C,D,E,

F,G,H,I,J,K,L]_[1:24]n

(Refer to the device

Pin Table for number of channels based on device selected)

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Connection Guidelines

These are true LVDS receiver/transmitter channels on column I/O banks. Each I/O pair can be configured as LVDS receiver or

LVDS transmitter.

Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel.

If not used for differential signaling, these pins are available as single ended user I/O pins.

Unused pins can be tied to GND or unconnected. If unconnected, use

Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(4-1) .

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Notes:

4-1. Refer to Knowledge Database solution rd12102002_3281 for further information regarding the concerns when I/O pins are left floating with no internal or external bias. Ensure there are no conflicts between the Quartus II software device wide default configuration for unused I/Os and the board level connection. Altera recommends setting unused I/O pins on a project wide basis to behave as inputs tri-state with weak pull up resistor enabled. Individual unused pins can be reserved with specific behavior such as output driving ground or as output driving VCC to comply with the

PCB level connection.

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Part D: HPS I/O Pins

This section is used to review the HPS I/O pins for the SoC variants of the Arria 10 device family (SX). In order for the HPS to operate, the

HPS_CLK1 and BOOTSEL[2..0] pins must be connected correctly. For HPS external memory interface pin usage, refer to the External Memory

Interfaces section of this review document.

A Quartus II project archive that includes all SoC hard peripherals configured and pinned out as they are intended to be used must be provided for this section of the review.

Each of the HPS I/O pins have multiple dedicated peripheral functions which are listed for each pin in the I/O section of this review. The I/O pin function on the schematic will be cross referenced to the Quartus II project usage to verify there are no conflicts. The peripheral pins are programmable through pin multiplexors. Each pin may have up to seven functions, Refer to the

Arria 10 GX, GT, and SX Device Family Pin

Connection Guidelines (PDF) for peripheral usage pin function sharing. Configuration of each pin is done during HPS configuration.

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HPS peripheral usage

Peripheral

TRACE

I2C0

I2C1

Pin multiplexing

UART0

UART1

SPIM0

SPIM1

SPIS0

SPIS1

SDMMC/MDIO

QSPI

NAND

USB0

USB1

EMAC0

EMAC1

EMAC2

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Mode

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Plane/Signal

HPS_CLK1

(Arria 10 SX device variants only)

HPS_nRST

(Arria 10 SX device variants only)

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Schematic Name Connection Guidelines

Dedicated clock input pin that drives the main PLL.

This provides clocks to the MPU, L3/L4 sub-systems, debug sub-system and the Flash controllers. It can also be programmed to drive the peripheral.

Connect a single-ended clock source to this pin. The

I/O standard of the clock source must be compatible with VCCIO_HPS. Refer to the valid frequency range of the clock source in Arria 10 Device Datasheet. The input clock must be present at this pin for HPS operation.

Warm reset to the HPS block.

Active low bi-directional pin. When driven from the board the system reset domains which allow debugging to operate is affected. HPS pulls down the output during the duration of cold reset and may pull down the output during the duration of warm reset.

Connect this pin through a 1kΩ pull-up resistor to

VCCIO_HPS.

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Page 69 of 142

<Project Name> <Date>

TRACE

Plane/Signal

TRACE_CLK

TRACE_D[3:0]

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

TRACE port.

Output trace clk.

Output trace data.

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Comments / Issues

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Page 70 of 142

<Project Name> <Date>

I2C0

Plane/Signal

I2C0_SDA

I2C0_SCL

Schematic Name Connection Guidelines

I

2

C controller pins.

Bidirectional Serial Data.

Bidirectional Serial Clock.

I2C1

Plane/Signal

I2C1_SDA

I2C1_SCL

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

I

2

C controller pins.

Bidirectional Serial Data.

Bidirectional Serial Clock.

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

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Page 71 of 142

<Project Name> <Date>

UART0

Plane/Signal

UART0_RX

UART0_TX

UART0_CTS

UART0_RTS

Schematic Name Connection Guidelines

UART controller pins.

Input UART receive data.

Output UART transmit data.

Input UART Clear To Send signal (cts_n).

Output UART Ready To Send signal (rts_n).

UART1

Plane/Signal

UART1_RX

Schematic Name Connection Guidelines

UART controller pins.

Input UART receive data.

UART1_TX

UART1_CTS

UART1_RTS

Index

Top of Section

HPS Peripheral Table

Output UART transmit data.

Input UART Clear To Send signal (cts_n).

Output UART Ready To Send signal (rts_n).

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Comments / Issues

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Page 72 of 142

<Project Name> <Date>

SPIM0

Plane/Signal

SPIM0_CLK

SPIM0_MOSI

SPIM0_MISO

SPIM0_SS0

SPIM0_SS1

Schematic Name Connection Guidelines

SPI master controller pins.

Output SPI clock.

Output SPI Master Out Slave In Data.

Input SPI Master In Slave Out Data.

Output SPI Slave Select 0.

Output SPI Slave Select 1.

SPIM1

Plane/Signal

SPIM1_CLK

SPIM1_MOSI

SPIM1_MISO

SPIM1_SS0

SPIM1_SS1

Schematic Name Connection Guidelines

SPI master controller pins.

Output SPI clock.

Output SPI Master Out Slave In Data.

Input SPI Master In Slave Out Data.

Output SPI Slave Select 0.

Output SPI Slave Select 1.

Index

Top of Section

HPS Peripheral Table

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Comments / Issues

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Page 73 of 142

<Project Name> <Date>

SPIS0

Plane/Signal

SPIS0_CLK

SPIS0_MOSI

SPIS0_MISO

Schematic Name Connection Guidelines

SPI slave controller pins.

Input SPI clock.

Input SPI Master Out Slave In Data.

Output SPI Master In Slave Out Data.

Input SPI Slave Select. SPIS0_SS0

SPIS1

Plane/Signal

SPIS1_CLK

SPIS1_MOSI

SPIS1_MISO

Schematic Name Connection Guidelines

SPI slave controller pins.

Input SPI clock.

Input SPI Master Out Slave In Data.

Output SPI Master In Slave Out Data.

Input SPI Slave Select. SPIS1_SS0

Index

Top of Section

HPS Peripheral Table

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Comments / Issues

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Page 74 of 142

<Project Name> <Date>

SDMMC/MDIO

Plane/Signal

SDMMC_CMD

SDMMC_PWREN

SDMMC_D[7:0]

SDMMC_CLK_IN

SDMMC_CLK

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

Where the SD/MMC controller is used these pins form an SD/MMC/CE-ATA interface.

Bidirectional card command.

Output external power enable.

Bidirectional card data.

Input clock to SD/MMC controller CIU.

Output clock to card.

Comments / Issues

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DS-01041-1.2

Page 75 of 142

<Project Name> <Date>

QSPI

Plane/Signal

QSPI_SS[3:0]

QSPI_IO[0]

QSPI_IO[1]

QSPI_IO[2]

QSPI_IO[3]

QSPI_CLK

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

QSPI controller pins.

Output slave select signals.

Extended SPI mode:

Output Data.

Dual or quad IO mode:

Bidirectional data.

Extended SPI mode:

Input Data.

Dual or Quad IO mode:

Bidirectional data.

Extended SPI mode and dual IO mode:

Output write protect.

Quad IO mode:

Bidirectional data.

Quad IO mode:

Bidirectional data.

Output clock.

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Comments / Issues

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Page 76 of 142

<Project Name> <Date>

NAND Controller

Plane/Signal

NAND_ALE

NAND_CE

NAND_CLE

NAND_RE

NAND_RB

NAND_DQ[7:0]

NAND_WP

NAND_WE

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

If the NAND flash controller is used, these pins form the ONFI to a NAND flash device.

Output address latch enable.

Output chip enable.

Output command latch enable.

Output read enable.

Input ready/busy.

Bidirectional command, address, data.

Output write protect.

Output write enable.

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Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 77 of 142

<Project Name> <Date>

USB0

Plane/Signal

USB0_D[7:0]

USB0_CLK

USB0_STP

USB0_DIR

USB0_NXT

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

If USB0 is used these pins form the ULPI to a USB

PHY.

Bidirectional data driven low by the controller during idle.

Input clock receives the 60MHz clock from the ULPI

PHY.

Output stop data control.

Input data bus control.

Input next data control.

Comments / Issues

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Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 78 of 142

<Project Name> <Date>

USB1

Plane/Signal

USB1_D[7:0]

USB1_CLK

USB1_STP

USB1_DIR

USB1_NXT

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

If USB1 is used these pins form the ULPI to a USB

PHY.

Bidirectional data driven low by the controller during idle.

Input clock receives the 60MHz clock from the ULPI

PHY.

Output stop data control.

Input data bus control.

Input next data control.

Comments / Issues

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DS-01041-1.2

Page 79 of 142

<Project Name> <Date>

EMAC0

Plane/Signal

RGMII0_TX_CLK

RGMII0_RX_CLK

RGMII0_TXD[3:0]

RGMII0_TXCTL

RGMII0_RXD[3:0]

RGMII0_RXCTL

RGMII0_MDC

RGMII0_MDIO

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

If EMAC0 is used, these pins form the RGMII to an

Ethernet PHY or switch.

Input transmit clock.

Input Receive clock.

Output transmit data.

Output transmit control.

Input Receive data.

Input Receive control.

Output management clock.

Bidirectional management data.

Comments / Issues

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DS-01041-1.2

Page 80 of 142

<Project Name> <Date>

EMAC1

Plane/Signal

RGMII1_TX_CLK

RGMII1_RX_CLK

RGMII1_TXD[3:0]

RGMII1_TXCTL

RGMII1_RXD[3:0]

RGMII1_RXCTL

RGMII1_MDC

RGMII1_MDIO

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

If EMAC1 is used, these pins form the RGMII to an

Ethernet PHY or switch.

Input transmit clock.

Input Receive clock.

Output transmit data.

Output transmit control.

Input Receive data.

Input Receive control.

Output management clock.

Bidirectional management data.

Comments / Issues

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DS-01041-1.2

Page 81 of 142

<Project Name> <Date>

EMAC2

Plane/Signal

RGMII2_TX_CLK

RGMII2_RX_CLK

RGMII2_TXD[3:0]

RGMII2_TXCTL

RGMII2_RXD[3:0]

RGMII2_RXCTL

RGMII2_MDC

RGMII2_MDIO

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

If EMAC2 is used, these pins form the RGMII to an

Ethernet PHY or switch.

Input transmit clock.

Input Receive clock.

Output transmit data.

Output transmit control.

Input Receive data.

Input Receive control.

Output management clock.

Bidirectional management data.

Comments / Issues

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Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 82 of 142

<Project Name> <Date>

GPIO

Plane/Signal

GPIO0[23:0]

GPIO1[23:0]

GPIO2[13:0]

Schematic Name

Index

Top of Section

HPS Peripheral Table

Connection Guidelines

Pins which are not used for one of the peripheral functions may be used as GPIO.

Unused pins can be tied to GND or unconnected. If unconnected, use Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND.

Comments / Issues

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Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 83 of 142

<Project Name> <Date>

Reviewed against Errata Sheet for Arria 10 Devices (PDF) version:

Additional Comments:

Index

Top of Section

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DS-01041-1.2

Page 84 of 142

<Project Name> <Date>

Section V: External Memory Interfaces

Index

Arria 10 Literature

Arria 10 Recommended Reference Literature/Tool List

Arria 10 Pin Out Files

Arria 10 GX, GT and SX Device Family Pin Connection Guidelines (PDF)

Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)

External Memory Interface Literature

External Memory Interfaces in Arria 10 Devices (PDF)

External Memory Interface Pin Information for Arria 10 Devices

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 85 of 142

<Project Name> <Date>

Part A: DDR3

Interface Pins

Plane/Signal

Data pin - DQ

Data strobe -

DQS/DQSn

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place it on DQ pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Place it on DQS and DQSn pins as specified in the <variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

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See Note

(5-1) .

Page 86 of 142

<Project Name> <Date>

Plane/Signal

DM

Schematic Name

mem_clk and mem_clk_n

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place it on data mask pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

DM pins must be paired off with a DQ pin

(from same DQS group) for proper functionality. Valid pairs in an IO_12 lane are

0/1, 2/3, 4/5, 6/7, 8/9, and 10/11.

Place it on CK/CK_N pins as specified in the

<variation_name>_readme.txt file which is generated with your I

Comments / Issues

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Page 87 of 142

<Project Name> <Date>

Plane/Signal

clock_source

Schematic Name

Address [BA, A]

Command [CKE, ODT,

CS_N, RAS, CAS,

WE_N]

Index

Top of Section

Connection Guidelines

Place it on PLL reference clock pin as specified in the <variation_name>_readme.txt file which is generated with your IP.

Altera does not check these but here are important recommendations for the clock source: 1) Use one of the recommended frequencies shown in the IP (IP General tab -

> Clocks), 2) Use a low jitter clock source.

See the recommendations for Memory Output

Clock Jitter in the Arria 10 Datasheet

Place it on address pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Place it on command pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

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Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 88 of 142

<Project Name> <Date>

Plane/Signal

Reset for DDR3

Memory

Reset

RZQ_[#]

Schematic Name

Notes:

5-1. DDR3 only supports differential DQS signaling.

Index

Top of Section

Connection Guidelines

Place it on mem_reset_n pin as specified in the <variation_name>_readme.txt file which is generated with your IP.

Any user IO pins. The reset pin can alternatively be generated internally.

Used when calibrated OCT for the memory interface pins is implemented.

Place it on RZQ pin as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

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DS-01041-1.2

Page 89 of 142

<Project Name> <Date>

Check vendor datasheet to make sure x4 DQS configuration is not being used since it is currently not supported.

Additional Comments:

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 90 of 142

<Project Name> <Date>

Part B: DDR3

Interface Termination

Guidelines

Plane/Signal

Memory [email protected]

Memory

Schematic Name

Memory [email protected]

FPGA

DQS @ Memory

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Fly by termination scheme. Clock signals are already terminated on the DIMM. No need to put any termination on the board.

Discrete Devices

– Fly by termination scheme. Differential termination resistor needs to be included in the design.

Depending on your board stack-up and layout requirements, you choose your differential termination resistor value.

Use series output termination with calibration.

Check the termination value in the .qip file which is generated with your IP.

Comments / Issues

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See Note

(5-2) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-2) .

Use ODT. Verify Guidelines have been met or list required actions for compliance.

See Note

(5-2) .

Page 91 of 142

<Project Name> <Date>

Plane/Signal

DQS @ FPGA

Schematic Name

DQ @ Memory

DQ @ FPGA

[email protected] Memory

DM @ FPGA

Index

Top of Section

Connection Guidelines

Use series output termination with calibration and parallel input termination with calibration

Check the termination value in the .qip file which is generated with your IP.

Use ODT.

Use series output termination with calibration and parallel input termination with calibration

Check the termination value in the .qip file which is generated with your IP.

Use ODT.

If DM pins are unused, refer to the

DDR3/DDR3L manufacturer's data sheet for connection recommendations. Typically they must be tied low using a resistor no greater than 4*Rtt (the nominal ODT value used on the memory device).

Use series output termination with calibration.

Check the termination value in the .qip file which is generated with your IP.

Comments / Issues

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See Note

(5-2) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-2) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-2) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-2) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-2) .

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 92 of 142

<Project Name> <Date>

Plane/Signal

Address [BA, A] @

Memory

Address [BA, A] @

FPGA

Command [CKE, ODT,

CS_N, RAS, CAS,

WE_N] @ Memory

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

DIMM - Fly by termination scheme. Address signals are already terminated on the DIMM.

No need to put any termination on the board.

Discrete Device

– Fly by termination scheme.

Terminated at the device.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-2) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-2) .

Use fast slew rate and serial output termination with calibration.

Check the termination value in the .qip file which is generated with your IP.

DIMM implementation - Fly by termination scheme. Command signals are already terminated on the DIMM. No need to put any termination on the board.

Discrete Device

– Fly by termination scheme.

Terminated at the device.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-2) .

Page 93 of 142

<Project Name> <Date>

Plane/Signal

Reset for DDR3

Memory

Schematic Name Connection Guidelines

For DDR3, Use 1.5V and fast slew rate.

Also use serial output termination with calibration for SSTL-15 DDR3.

For DDR3L, use SSTL-135, fast slew rate and serial output termination.

Check the FPGA termination value in the .qip file which is generated with your IP.

It is not recommended to externally terminate this reset to Vtt.

Use fast slew rate and serial output termination with calibration.

Check the termination value in the .qip file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Command [CKE, ODT,

CS_N, RAS, CAS,

WE_N] @ FPGA

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-2) .

Notes:

5-2. The termination schemes suggested in the table are general guidelines. You should do board level simulation for your particular system/board to determine optimal termination scheme.

Additional Comments:

Index

Top of Section

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DS-01041-1.2

Page 94 of 142

<Project Name> <Date>

Miscellaneous

Pin Description

Vref

Vtt

RZQ_[#]

Schematic Name

Additional Comments:

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Use a voltage regulator to generate this voltage.

Use a voltage regulator to generate this voltage.

Typically DDR3 DIMMS have decoupling capacitors connected between VTT and VDD

(1.5V) and it is recommended that designers follow this approach.

RZQ pin is connected to GND through an external 240-

Ω or 100-Ω ±1% resistor. Refer to I/O and High Speed I/O in Arria 10 Devices for the OCT impedance options for the desired OCT scheme.

Comments / Issues

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Page 95 of 142

<Project Name> <Date>

Part C: DDR4

Interface Pins

Plane/Signal

Data pin - DQ

Data strobe -

DQS/DQSn mem_clk and mem_clk_n

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place it on DQ pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Place it on DQS and DQSn pins as specified in the <variation_name>_readme.txt file which is generated with your IP.

Place it on CK/CK_N pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

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Verify Guidelines have been met or list required actions for compliance.

See Note (5-3) .

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Page 96 of 142

<Project Name> <Date>

Plane/Signal

clock_source

Schematic Name

DBI_n

Address [BA,BG, A]

Command [CKE, ODT,

CS_N, ACT_n, PAR]

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place it on PLL reference clock pin as specified in the <variation_name>_readme.txt file which is generated with your IP.

Altera does not check these but here are important recommendations for the clock source: 1) Use one of the recommended frequencies shown in the IP (IP General tab -

> Clocks), 2) Use a low jitter clock source.

See the recommendations for Memory Output

Clock Jitter in the Arria 10 Datasheet

Place it on DBI_n pin as specified in the

<variation_name>_readme.txt file which is generated with your IP.

DM pins must be paired off with a DQ pin

(from same DQS group) for proper functionality

when Mode Register 5 DM pins are enabled.

Valid pairs in an IO_12 lane are

0/1, 2/3, 4/5, 6/7, 8/9, and 10/11.

Place it on address pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Place it on command pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 97 of 142

<Project Name> <Date>

Plane/Signal

ALERT_n

Reset for DDR4

Memory

Reset for DDR4 controller

RZQ_[#]

Schematic Name

Notes:

5-3 DDR4 only supports differential DQS signaling.

Index

Top of Section

Connection Guidelines

Place it on mem_alert_n pin as specified in the <variation_name>_readme.txt file which is generated with your IP.

Place it on mem_reset_n pin as specified in the <variation_name>_readme.txt file which is generated with your IP.

Any user IO pins. The reset pin can alternatively be generated internally.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Used when calibrated OCT for the memory interface pins is implemented.

Place it on RZQ pin as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 98 of 142

<Project Name> <Date>

Check vendor datasheet to make sure x4 DQS configuration is not being used since it is currently not supported.

Additional Comments:

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 99 of 142

<Project Name> <Date>

Part D: DDR4

Interface Termination

Guidelines

Plane/Signal

Memory [email protected]

Memory

Schematic Name

Memory [email protected]

FPGA

DQS @ Memory

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Fly by termination scheme. Clock signals are already terminated on the DIMM. No need to put any termination on the board.

Devices

– Fly by termination scheme. differential termination resistor needs to be included in the design. Depending on your board stackup and layout requirements, you choose your differential termination resistor value.

Use series output termination with calibration.

Check the termination value in the .qip file which is generated with your IP.

Use ODT.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Page 100 of 142

<Project Name> <Date>

Plane/Signal

DQS @ FPGA

Schematic Name

DQ @ Memory

DQ @ FPGA

[email protected]

[email protected] FPGA

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Use series output termination with calibration and parallel input termination with calibration

Check the termination value in the .qip file which is generated with your IP.

Use ODT.

Use series output termination with calibration and parallel input termination with calibration

Check the termination value in the .qip file which is generated with your IP.

Use ODT.

Use series output termination with calibration.

Check the termination value in the .qip file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Page 101 of 142

<Project Name> <Date>

Plane/Signal

Address [BA,BG, A] @

Memory

Address [BA, BG, A]

@ FPGA

Command [CKE, ODT,

CS_N, ACT_n, PAR]

@ Memory

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

DIMM - Fly by termination scheme. Address signals are already terminated on the DIMM.

No need to put any termination on the board.

Discrete Device

– Fly by termination scheme.

Terminated at the device.

Use fast slew rate and serial output termination with calibration.

Check the termination value in the .qip file which is generated with your IP.

DIMM implementation - Fly by termination scheme. Command signals are already terminated on the DIMM. No need to put any termination on the board.

Discrete Device

– Fly by termination scheme.

Terminated at the device.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Page 102 of 142

<Project Name> <Date>

Plane/Signal

Reset for DDR4

Memory

Schematic Name Connection Guidelines

Use 1.2V I/O standard to meet the 1.2V

CMOS logic levels on the DDR4 device or

DIMM.

Check the termination value in the .qip file which is generated with your IP.

It is not recommended to terminate this reset to Vtt.

Use an external pullup resistor (typically 50 ohms) to VDD (1.2V).

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

ALERT_n

Command [CKE, ODT,

CS_N, ACT_n, PAR]

@ FPGA

Termination with calibration.

Check the termination value in the .qip file which is generated with your IP.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

See Note (5-4)

Notes:

5-4. The termination schemes suggested in the table are general guidelines. You should do board level simulation for your particular system/board to determine optimal termination scheme.

Additional Comments:

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 103 of 142

<Project Name> <Date>

Miscellaneous

Pin Description

Vref

Vtt

RZQ_[#]

Schematic Name

Additional Comments:

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Use a voltage regulator to generate this voltage.

The DDR4 memory device requires a Vref of

VDD/2 (0.6V) connected to its VREFCA pins.

The DDR4 memory device VREFDQ is generated internally.

The FPGA DDR4 interface IOBANKS Vref is generated internally for the DQ, DQS,DQS_n and DBI_n signals.

Use a voltage regulator to generate this voltage.

Typically DDR4 DIMMS have decoupling capacitors connected between VTT and VDD

(1.2V) and it is recommended that designers follow this approach.

RZQ pin is connected to GND through an external 240-

Ω or 100-Ω ±1% resistor. Refer to

I/O and High Speed I/O in Arria 10 Devices for the OCT impedance options for the desired OCT scheme.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 104 of 142

<Project Name> <Date>

Part E: RLDRAM II/3

Interface Pins

Plane/Signal

Data pin - DQ

Schematic Name

DM

QVLD

Connection Guidelines

Place it on DQ pins of the DQ/DQS group.

The order of the DQ bits within a designated

DQ group/bus is not important. Place the DQ pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Place on the DQ pins of the applicable

DQ/DQS pin group. Place it on DM pins as specified in the <variation_name>_readme.txt file which is generated with your IP.

Place on a DQ pin in the same bank as the read data. Altera IP does not use the QVLD pin.

You may leave this pin unconnected on your board. You may not be able to fit these pins in a

DQS group.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 105 of 142

<Project Name> <Date>

Plane/Signal

Read clock to the

FPGA - QK/QKn

Write clock from the

FPGA - DK/DKn

Memory clock

CK/CKn

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place on the corresponding DQS and DQSn pins of the DQ/DQS group. Please use the

<variation_name>_readme.txt file which is generated with your IP as a guideline.

Place DK pins in the same IO bank as the read clock (QK) pins & DQ pins in that byte lane.

Please use the

<variation_name>_readme.txt file which is generated with your IP as a guideline.

DK/DK# must use differential output-capable pins.

Place it on CK/CKn pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 106 of 142

<Project Name> <Date>

Plane/Signal

clock_source

Schematic Name

Address

A, BA

Command

CS#, REF#, WE#

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place it on “PLL_REF_CLK” pins as specified in the <variation_name>_readme.txt file which is generated with your IP.

Please use a frequency recommended by the

EMIF RLDRAM 3 IP GUI.

Place it on Address/ Bank Address pins as specified in the <variation_name>_readme.txt file which is generated with your IP.

Place it on Command pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 107 of 142

<Project Name> <Date>

Plane/Signal

Reset for RLDRAM

Memory

(RLDRAM 3 only)

Reset

RZQ

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place the RESET signal as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Any user IO pin. The reset pin can alternatively be generated internally.

Used when calibrated OCT for the memory interface pins is implemented.

Place it on RZQ pin as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 108 of 142

<Project Name> <Date>

Additional Comments:

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 109 of 142

<Project Name> <Date>

Part F: RLDRAM II/ 3

Interface Termination

Guidelines

Plane/Signal

Write Clock (DK/DKn)

@ FPGA

Schematic Name

Write Clock (DK/DKn)

@ Memory

Read Clock (QK/QKn)

@ FPGA

Read Clock (QK/QKn)

@ Memory

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Use series termination with calibration as output termination. Check the termination value in the .qip file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

RLDRAM 3 : Use ODT Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Use parallel termination with calibration as input termination.

Check the termination value in the .qip file which is generated with your IP.

Read clock output impedance is implemented with the help of the RLDRAM II /3 component

ZQ input pin on the memory device side. If not, you may need to put 50-

Ω series termination on the memory side.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Page 110 of 142

<Project Name> <Date>

Plane/Signal

Memory clocks @

Memory

Memory clocks @

FPGA

DQ @ Memory

DQ @ FPGA

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Use a differential termination.

Depending on your board stackup and layout requirements, choose your differential termination resistor value.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Use series output termination without calibration.

Check the termination value in the .qip file which is generated with your IP.

Use ODT.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Use Dynamic OCT which is parallel input termination with calibration and series output termination.

Check the termination value in the .qip file which is generated with your IP.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Page 111 of 142

<Project Name> <Date>

Plane/Signal

DM @ Memory

Schematic Name

DM @ FPGA

QVLD @ Memory

QVLD @ FPGA

Index

Top of Section

Connection Guidelines

Use ODT.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Use series output termination.

Check the termination value in the .qip file which is generated with your IP.

Read clock output impedance is implemented with the help of the RLDRAM II /3 component

ZQ input pin on the memory device side. If not, you may need to put 50-

Ω series termination on the memory side.

If connected, use parallel input termination with calibration.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 112 of 142

<Project Name> <Date>

Plane/Signal

Address [BA, A] @

Memory

Address [BA, A] @

FPGA

Command [CS#,WE#,

REF#] @ Memory

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Parallel termination to VTT is recommended.

Micron technical noteTN-44-01 (RLDRAM 3

Design Guide) indicates that it may be possible to achieve adequate signal integrity without signal terminations at lower frequencies and with short PCB traces.

Simulations should be performed to determine the termination requirements.

If there are multiple loads on certain FPGA output pins (for example, if the address bus is shared across several memory devices), use of maximum drive strength setting may be preferred over the series OCT setting. Use board level simulations to pick the optimal setting for best signal integrity.

REF#, WE# : Parallel termination to VTT is recommended.

CS# : Use either parallel termination to VTT or a pull-up to VDD. Refer to the memory vendor’s RLDRAM II/3 component data sheet for further information.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Page 113 of 142

<Project Name> <Date>

Plane/Signal

Command [CKE,

CS_N, RAS, CAS,

WE_N] @ FPGA

Reset for RLDRAM

Memory

(RLDRAM 3 only)

Schematic Name Connection Guidelines

If there are multiple loads on certain FPGA output pins (for example, if the address bus is shared across several memory devices), use of maximum drive strength setting may be preferred over the series OCT setting. Use board level simulations to pick the optimal setting for best signal integrity.

Use SSTL-12 Class I I/O standard to meet the

CMOS logic levels on the RLDRAM 3 device.

Use a pull-down resistor to GND.

Typical value is 10k

Ω, but you should select a suitable value for your implementation.

Refer to the memory vendor’s RLDRAM II/3 component data sheet for further information.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-5) .

Verify Guidelines have been met or list required actions for compliance.

Notes:

5-5. The termination schemes suggested in the table are general guidelines. You should do board level simulation for your particular system/board to determine optimal termination scheme.

Additional Comments:

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 114 of 142

<Project Name> <Date>

Miscellaneous

Pin Description

Vref

Vtt

RZQ

Schematic Name

Additional Comments:

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Use a voltage regulator to generate this voltage.

Use a voltage regulator to generate this voltage.

RZQ pin is connected to GND through an external 240-

Ω or 100-Ω ±1% resistor. Refer to

I/O and High Speed I/O in Arria 10 Devices for the OCT impedance options for the desired OCT scheme.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 115 of 142

<Project Name> <Date>

Part G: QDR II/II+/Xtreme

Interface Pins

Plane/Signal

Q

– Read data pins

Schematic Name

D

– Write data pins

Read clock to the FPGA -

CQ/CQn

Connection Guidelines

Place it on Q pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

The order of the Q bits within a designated

DQ group/bus is not important.

Place it on D pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

The order of the D bits within a designated

DQ group/bus is not important.

Place it on CQ/CQN pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 116 of 142

<Project Name> <Date>

Plane/Signal

Write clock from the

FPGA - K/Kn

Input clock for output data

– C and Cn

QVLD

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place it on K/KN pins as specified in the

<variation_name>_readme.txt file which is generated with your IP. Does not need to be placed on DQS/DQSn pins, but must use a differential pin pair.

Altera QDRII SRAM interface is implemented in single clock mode. Connect C and Cn high.

Also, look for the connection guidance in the memory device datasheet.

Altera QDRII+ and QDRII+ Xtreme SRAM interface does not use the QVLD signal. You can leave it unconnected on your board.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 117 of 142

<Project Name> <Date>

Plane/Signal

clock_source

Schematic Name

BWSn

Address [A]

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place it on PLL reference clock pin as specified in the <variation_name>_readme.txt file which is generated with your IP.

Altera does not check these but here are important recommendations for the clock source: 1) Use one of the recommended frequencies shown in the IP (IP General tab -

> Clocks), 2) Use a low jitter clock source.

See the recommendations for Memory Output

Clock Jitter in the Arria 10 Datasheet

Place it on BWSN pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Place it on address pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 118 of 142

<Project Name> <Date>

Plane/Signal

Command

[RPS_N, WPS_N]

Schematic Name

Reset for controller

DOFF_N

Index

Top of Section

Connection Guidelines

Place it on command pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Any user IO pins. The reset pin can alternatively be generated internally.

Place it on DOFF_N pin as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Page 119 of 142

<Project Name> <Date>

Plane/Signal

RZQ

Schematic Name

Additional Comments:

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Used when calibrated OCT for the memory interface pins is implemented.

Place it on RZQ pin as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Page 120 of 142

<Project Name> <Date>

Part H: QDRII/II+/II+

Xtreme Termination

Guidelines

Plane/Signal

Write Clock (K/Kn) @

FPGA

Schematic Name

Write Clock (K/Kn) @

Memory

Read Clock (CQ/CQn)

@ FPGA

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Default is HSTL Class I and series OCT 50-

Ω with calibration.

You can change output mode to current strength or no termination during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Write clock at the memory side should be terminated with class I Parallel termination at the memory side.

Default is HSTL Class I and parallel OCT 50-

Ω with calibration.

You can change input mode to no termination during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Page 121 of 142

<Project Name> <Date>

Plane/Signal

Read Clock (CQ/CQn)

@ Memory

Write data - D @

FPGA

Write data

Memory

– D @

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Read clock output impedance is implemented with the help of ZQ input pin on the memory device side. If not, you need to put 50-

Ω series OCT on the memory side.

Default is HSTL Class I and series OCT 50with calibration.

You can change output mode to current strength or no termination during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Write data at the memory side should be

Ω terminated with class I Parallel termination at the memory side.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Page 122 of 142

<Project Name> <Date>

Plane/Signal

Read data - Q @

FPGA

Read data - Q @

Memory

BWSn @ FPGA

BWSn @ Memory

QVLD @ FPGA

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Default is HSTL Class I and parallel OCT 50-

Ω with calibration.

You can change input mode to no termination during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Read data output impedance is implemented with the help of ZQ input pin on the memory device side. If not, you need to put 50-

Ω series OCT on the memory side.

Default is HSTL Class I and series OCT 50-

Ω with calibration.

You can also change output mode to current strength or no termination during IP generation.

Check the termination value in the .qip file which is generated with your IP.

BWSn at the memory side should be terminated with class I Parallel termination at the memory side.

Altera QDRII+ and QDRII+ Xtreme SRAM interface does not use the QVLD signal. You can leave it unconnected on your board.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Page 123 of 142

<Project Name> <Date>

Plane/Signal

Address [A] @ FPGA

Schematic Name

Address [A] @

Memory

Command[WPS_N,

RPS_N]@ FPGA

Command[WPS_N,

RPS_N]@ Memory

[email protected]

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Default is HSTL Class I and series OCT 50-

Ω with calibration.

You can also change output mode to current strength or no termination during IP generation.

Check the termination value in the .qip file which is generated with your IP.

On the memory side, Altera recommends the use of external parallel termination on input signals to the memory.

Default is HSTL Class I and series OCT 50-

Ω with calibration.

You can also change output mode to current strength or no termination during IP generation.

Check the termination value in the .qip file which is generated with your IP.

On the memory side, Altera recommends the use of external parallel termination on input signals to the memory.

On the memory side, pull down to GND via

10K-

Ω resistor.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Page 124 of 142

<Project Name> <Date>

Miscellaneous:

Pin Description

Vref

Schematic Name

Vtt

RZQ

Connection Guidelines

Use a voltage regulator to generate this voltage.

Use a voltage regulator to generate this voltage.

RZQ pin is connected to GND through an external 240-

Ω or 100-Ω ±1% resistor. Refer to

I/O and High Speed I/O in Arria 10 Devices for the OCT impedance options for the desired OCT scheme.

Comments/ Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-6) .

Verify Guidelines have been met or list required actions for compliance.

Index

Top of Section

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<Project Name> <Date>

Notes:

5-6. The termination schemes suggested in the table are general guidelines. You should do board level simulation for your particular system/board to determine optimal termination scheme.

Index

Top of Section

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<Project Name> <Date>

Part I: QDRIV

Interface Pins

Plane/Signal

Data pin

– DQA,DQB

Schematic Name

Data inversion pin

DINVA, DINVB

QVLD

Connection Guidelines

Place it on DQ pins of the DQ/DQS group.

The order of the DQ bits within a designated

DQ group/bus is not important. Place the

DQA/DQB pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Place it on the DQ pins of the DQ/DQS pin group. Place the DINVA/DINVB pins as specified in the <variation_name>_readme.txt file which is generated with your IP.

If “Data bus inversion” feature is turned off in

Altera IP, connect it to GND on your board.

Place on a DQ pin in the same bank as the read data. Altera IP does not use the QVLD pin.

You may leave this pin unconnected on your board. You may not be able to fit these pins in a

DQS group.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Index

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<Project Name> <Date>

Plane/Signal

Read clock to the

FPGA

– QKA/QKAn,

QKB/QKBn

Write clock from the

FPGA

– DKA/DKAn,

DKB/DKBn

Memory clock

CK/CKn

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place on the corresponding DQS and DQSn pins of the DQ/DQS group.

The polarity of QKB/QKBn must be swapped.

QKB pin on FPGA side must be placed on

DQSn pin and QKBn on memory side must be placed on DQS pin.

Please use the

<variation_name>_readme.txt file which is generated with your IP as a guideline.

Place DK pins in the same IO bank as the read clock (QK) pins & DQ pins in that byte lane.

Please use the

<variation_name>_readme.txt file which is generated with your IP as a guideline.

DK/DK# must use differential output-capable pins.

Place it on CK/CKn pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 128 of 142

<Project Name> <Date>

Plane/Signal

clock_source

Schematic Name

Address

A

AP

Address inversion pin

– AINV

Address parity input

Address parity error flag

– PE#

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Altera does not check these but here are important recommendations for the clock source: 1) Use one of the recommended frequencies shown in the IP (IP General tab -

> Clocks), 2) Use a low jitter clock source.

See the recommendations for Memory Output

Clock Jitter in the Arria 10 Datasheet

Place it on A pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Place it on AINV pin as specified in the

<variation_name>_readme.txt file which is generated with your IP.

If “Address bus inversion” feature is turned off in Altera IP, connect it to GND on your board.

Place it on AP pin as specified in the

<variation_name>_readme.txt file which is generated with your IP.

If “Use address parity bit” feature is turned off in Altera IP, connect it to GND on your board.

Place it on PE_N pin as specified in the

<variation_name>_readme.txt file which is

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 129 of 142

<Project Name> <Date>

Command

LDA#, LDB#,

RWA#,RWB#,CFG#,

LBK0#,LBK1#

Index

Top of Section

generated with your IP.

If “Use address parity bit” feature is turned off in Altera IP, you may leave this pin unconnected on your board.

Place it on Command pins as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Verify Guidelines have been met or list required actions for compliance.

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<Project Name> <Date>

Plane/Signal

Reset for QDRIV

Memory

RST#

Reset

RZQ

Schematic Name

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Place the RESET_N signal as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Any user IO pin. The reset pin can alternatively be generated internally.

Used when calibrated OCT for the memory interface pins is implemented.

Place it on RZQ pin as specified in the

<variation_name>_readme.txt file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 131 of 142

<Project Name> <Date>

Additional Comments:

Index

Top of Section

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<Project Name> <Date>

Part J: QDRIV

Interface Termination

Guidelines

Plane/Signal

Write Clock

(DKA/DKAn,

DKB/DKBn) @ FPGA

Schematic Name

Write Clock

(DKA/DKAn,

DKB/DKBn) @

Memory

Read Clock

(QKA/QKAn,

QKB/QKBn) @ FPGA

Read Clock

(QKA/QKAn,

QKB/QKBn) @

Memory

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Default is series OCT 34-

Ω with calibration.

You can change output mode to other termination value during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Use QDRIV ODT. Default is 25% of ZT. You can change it to ODT off or other termination value during IP generation.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7).

Default is parallel OCT 40-

Ω with calibration.

You can change input mode to other termination value during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Use QDRIV Impedance Control. Default is

25% of ZT. You can change it to other drive value during IP generation.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7

)

.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Page 133 of 142

<Project Name> <Date>

Plane/Signal

Memory clocks(CK/CKn) @

FPGA

Schematic Name Connection Guidelines

Default is series OCT 34-

Ω with calibration.

You can change output mode to other termination value during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Memory clocks(CK/CKn) @

Memory

Data(DQA,DQB) @

Memory

Data(DQA,DQB) @

FPGA

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Use QDRIV ODT. Default is 25% of ZT. You can change it to ODT off or other termination value during IP generation.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Use QDRIV ODT and Impedance Control.

Default is 25% of ZT. You can change it to other value during IP generation.

Use Dynamic OCT which is parallel input termination with calibration and series output termination.

Default is series OCT 34-

Ω with calibration and parallel OCT 40-

Ω with calibration.

You can change output mode/input mode to other termination value during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Page 134 of 142

<Project Name> <Date>

Plane/Signal

DINV( DINVA, DINVB)

@ Memory

Schematic Name

DINV( DINVA, DINVB)

@ FPGA

QVLD @ Memory

Connection Guidelines

Use QDRIV ODT. Default is 25% of ZT. You can change it to ODT off or other termination value during IP generation.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Default is series OCT 34-

Ω with calibration.

You can change output mode to other termination value during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Altera QDRIV SRAM interface does not use the QVLD signal. You can leave it unconnected on your board.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Index

Top of Section

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<Project Name> <Date>

Plane/Signal

Address (A) @Memory

Schematic Name

Address (A) @ FPGA

[email protected]

[email protected]

[email protected]

[email protected]

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Use QDRIV ODT. Default is 25% of ZT. You can change it to ODT off or other termination value during IP generation.

Default is series OCT 34-

Ω with calibration.

You can change output mode to other termination value during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Use QDRIV ODT. Default is 25% of ZT. You can change it to ODT off or other termination value during IP generation.

Default is series OCT 34-

Ω with calibration.

You can change output mode to other termination value during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Use QDRIV ODT. Default is 25% of ZT. You can change it to ODT off or other termination value during IP generation.

Default is series OCT 34-

Ω with calibration.

You can change output mode to other termination value during IP generation.

Check the termination value in the .qip file which is generated with your IP.

If “Use address parity bit” feature is turned off in Altera IP, connect it to GND on your board.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Page 136 of 142

<Project Name> <Date>

PE#@Memory

PE#@FPGA

Index

Top of Section

Use QDRIV Impedance Control. Default is

25% of ZT. You can change it to other drive value during IP generation.

Default is parallel OCT 40-

Ω with calibration.

You can change input mode to other termination value during IP generation.

Check the termination value in the .qip file which is generated with your IP.

If “Use address parity bit” feature is turned off in Altera IP, leave it unconnected on your board.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

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<Project Name> <Date>

Plane/Signal

Command (LDA#,

LDB#,

RWA#,RWB#,CFG#,

LBK0#,LBK1#) @

FPGA

Schematic Name Connection Guidelines

Default is series OCT 34-

Ω with calibration.

You can change output mode to other termination value during IP generation.

Check the termination value in the .qip file which is generated with your IP.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Command (LDA#,

LDB#,

RWA#,RWB#,CFG#,

LBK0#,LBK1#) @

Memory

Use QDRIV ODT. Default is 25% of ZT. You can change it to ODT off or other termination value during IP generation.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Reset for

[email protected]

Use 1.2V.

Use a pull-down resistor to GND.

Typical value is 10k

Ω, but you should select a suitable value for your implementation.

Refer to the memory vendor’s QDRIV component data sheet for further information.

Verify Guidelines have been met or list required actions for compliance.

See Note

(5-7) .

Notes:

5-7. The termination schemes suggested in the table are general guidelines. You should do board level simulation for your particular system/board to determine optimal termination scheme.

Additional Comments:

Index

Top of Section

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<Project Name> <Date>

Miscellaneous

Pin Description

Vref

Vtt

RZQ

Schematic Name

Additional Comments:

Index

Top of Section

Arria 10 GX, GT, and SX Schematic Review Report 1.2

DS-01041-1.2

Connection Guidelines

Use a voltage regulator to generate this voltage.

Use a voltage regulator to generate this voltage.

RZQ pin is connected to GND through an external 240-

Ω±1% resistor. Refer to

I/O and

High Speed I/O in Arria 10 Devices

for the OCT impedance options for the desired OCT scheme.

Comments / Issues

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Verify Guidelines have been met or list required actions for compliance.

Page 139 of 142

<Project Name> <Date>

Reviewed against Errata Sheet for Arria 10 Devices (PDF) version:

Additional Comments:

Index

Top of Section

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<Project Name> <Date>

Section VI: Document Revision History

Revision

V1.0

V1.1

Changes Made

Initial release, based on the Device Family Pin Connection Guidelines version 1.1.

Updated the connection guidelines for CLKUSR.

Updated the connection guidelines for PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_FB0.

Updated the connection guidelines for TCK, TDI, TMS, TDO, and TRST pins.

Updated the connection guidelines for VCCBAT, VCCERAM, VCCPGM, VCCPT.

Updated the transceiver data rate to 28.3 Gbps.

Updated the pin name and pin description of the PLL_[2,3][A,B,C,D,E,F,G,H,I,J,K,L]_FB[0,1] pins.

Updated the connection guidelines for the TCK, TMS, TDI, TDO, and TRST pins.

Updated the pin name and connection guidelines of the CRC_ERROR pin.

Updated the connection guidelines of the nPERST[L,R][0:1] pins.

Updated the connection guidelines of the VREFP_ADC and ADCGND pins.

Updated the connection guidelines of the VSIGP_[0,1] and VSIGN_[0,1] pins.

Updated the connection guidelines of the VCCP and VCC pins.

Updated the pin name of the VCCIO([2][A,F,G,H,I,J,K,L,AF,KL],[3][A,B,C,D,E,F,G,H,AB,GH]) pins.

Updated the connection guidelines of the VREFB([2][A,F,G,H,I,J,K,L],[3][A,B,C,D,E,F,G,H])N0 pins.

Updated the connection guidelines of the VCCLSENSE and GNDSENSE pins.

Updated the pin name, and pin connection guidelines of the VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J] and VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J] pins.

Updated the pin description and connection guidelines of the VCCH_GXB[L,R] pins.

Updated the pin name and connection guidelines of the GXB[L1,R4][C,D,E,F,G,H,I,J]_RX_[0:5]p/n,

GXB[L1,R4][C,D,E,F,G,H,I,J]_TX_CH[0:5]p/n, and

REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J]_CH[B,T]p/n pins.

Updated the pin description and connection guidelines for the RREF_[T,B][L,R] pins.

Updated the pin name and pin description of the RZQ_[#]/VID_EN.

Added DDR4 ALERT_n and PAR signal guidelines.

Clarified DDR4 VREF guidelines.

Updated the pin description of nIO_PULLUP.

Date

May 2014

August 2014

Arria 10 GX, GT, and SX Schematic Review Report 1.2

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<Project Name> <Date>

V1.2

Added the connection guidelines of HPS part.

Added QDRII/II+/II+Xtreme SRAM and QDRIV SRAM connection guidelines.

Updated the connection guidelines of CONF_DONE pin.

Updated the connection guidelines of nSTATUS pin.

Updated the connection guidelines of CRC_ERROR pin.

Updated the connection guidelines of DEV_CLRn, DEV_OE, nPERST[L,R][0:1] and DATA[1:31] pins.

Updated the connection guidelines of VREFP_ADC pin.

Updated the connection guidelines of VCC, VCCP, VCCERAM, ADCGND, VCCPT, VCCIO.

Updated the connection guidelines of VCCH_GXB, VCCR_GXB, VCCT_GXB pins.

Updated the pin name of mem_addr to A.

Febrary 2015

Index

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