CM-T54 reference guide

CM-T54 reference guide
CM-T54 CoM
Reference Guide
Introduction
© 2014 CompuLab Ltd.
All Rights Reserved. No part of this document may be photocopied, reproduced, stored in a retrieval
system, or transmitted, in any form or by any means whether, electronic, mechanical, or otherwise
without the prior written permission of CompuLab Ltd.
No warranty of accuracy is given concerning the contents of the information contained in this
publication. To the extent permitted by law no liability (including liability to any person by reason of
negligence) will be accepted by CompuLab Ltd., its subsidiaries or employees for any direct or
indirect loss or damage caused by omissions from or inaccuracies in this document.
CompuLab Ltd. reserves the right to change details in this publication without notice.
Product and company names herein may be the trademarks of their respective owners.
CompuLab Ltd.
P.O. Box 687 Yokneam Elite
20692 ISRAEL
Tel: +972 (4) 8290100
http://www.compulab.co.il
Fax: +972 (4) 8325251
Revised June 2014
CM-T54 Reference Guide
2
Table of Contents
Table of Contents
1
INTRODUCTION .............................................................................................................. 7
1.1
1.2
1.3
2
OVERVIEW ........................................................................................................................ 8
2.1
2.2
2.3
3
About This Document ...................................................................................................... 7
CM-T54 Part Number Legend ......................................................................................... 7
Related Documents .......................................................................................................... 7
Highlights ......................................................................................................................... 8
Block Diagram ................................................................................................................. 9
CM-T54 Features ........................................................................................................... 10
CORE SYSTEM COMPONENTS .................................................................................. 12
3.1 OMAP5432 SoC ............................................................................................................ 12
3.2 Multimedia System ........................................................................................................ 13
3.2.1 3D and 2D Acceleration ........................................................................................ 13
3.2.2 DSP subsystem ...................................................................................................... 13
3.2.3 IVA-HD Subsystem .............................................................................................. 14
3.3 Memory .......................................................................................................................... 14
3.3.1 DRAM................................................................................................................... 14
3.3.2 On-board eMMC storage ...................................................................................... 14
4
PERIPHERAL INTERFACES ....................................................................................... 15
4.1 Serial ATA Interface ...................................................................................................... 16
4.2 Display Interfaces........................................................................................................... 16
4.2.1 Parallel Display Interface (DPI) ............................................................................ 17
4.2.2 Remote Frame buffer interface (RFBI) ................................................................. 18
4.2.3 LVDS Display interface ........................................................................................ 18
4.2.4 MIPI Display Interface ......................................................................................... 20
4.2.5 HDMI port ............................................................................................................ 20
4.3 Camera Interfaces........................................................................................................... 21
4.3.1 Parallel Camera Interface ...................................................................................... 21
4.3.2 MIPI camera interfaces MIPI-CSI ........................................................................ 22
4.4 Audio Subsystem ........................................................................................................... 23
4.4.1 Analog Audio CODEC ......................................................................................... 23
4.4.2 Digital Audio Interfaces ........................................................................................ 25
4.4.2.1 McBSP interface .............................................................................................. 25
4.4.2.2 McASP interface ............................................................................................. 25
4.4.2.3 Digital Microphone Interface .......................................................................... 26
4.5 High-Definition Multimedia Interface (HDMI) ............................................................. 27
4.6 WLAN and Bluetooth .................................................................................................... 27
4.7 Ethernet .......................................................................................................................... 29
4.8 USB interfaces ............................................................................................................... 29
Revised June 2014
CM-T54 Reference Guide
3
Table of Contents
4.8.1 USB 3.0 On-The-Go ............................................................................................. 29
4.8.2 USB 2.0 Host ........................................................................................................ 30
4.9 UARTs ........................................................................................................................... 31
4.10
RS232 ........................................................................................................................ 32
4.11
MMC / SD / SDIO ..................................................................................................... 33
4.12
Touch-Screen ............................................................................................................. 34
4.13
Keypad ....................................................................................................................... 34
4.14
GPIO .......................................................................................................................... 35
4.15
I2C .............................................................................................................................. 37
4.16
SPI ............................................................................................................................. 38
4.17
General Purpose Timers and PWM ........................................................................... 38
4.18
HDQ / 1-Wire ............................................................................................................ 39
4.19
General Purpose ADC (GPADC) .............................................................................. 40
4.20
General purpose clock ............................................................................................... 40
4.21
JTAG ......................................................................................................................... 40
5
SYSTEM LOGIC .............................................................................................................. 42
5.1 Power Supply ................................................................................................................. 42
5.2 Power Management ........................................................................................................ 42
5.2.1 Power Resources & control signals. ..................................................................... 42
5.2.2 CM-T54 Power states ........................................................................................... 43
5.2.3 Power-On & Power-Off ........................................................................................ 44
5.2.3.1 ON, OFF requests and gating conditions ........................................................ 44
5.2.3.2 ON, OFF and gating signals active by default ................................................ 45
5.3 Reset ............................................................................................................................... 45
5.4 Boot Sequence................................................................................................................ 46
5.5 Battery & Charger signals .............................................................................................. 46
5.6 Signal Multiplexing Characteristics ............................................................................... 47
5.7 RTC ................................................................................................................................ 49
5.8 LED ................................................................................................................................ 49
6
CARRIER BOARD INTERFACE .................................................................................. 50
6.1
6.2
6.3
6.4
7
Connector Pinout............................................................................................................ 50
Mating Connectors ......................................................................................................... 54
Mechanical Drawings..................................................................................................... 55
Standoffs/Spacers ........................................................................................................... 56
OPERATIONAL CHARACTERISTICS ....................................................................... 57
7.1
7.2
7.3
7.4
7.5
Absolute Maximum Ratings .......................................................................................... 57
Recommended Operating Conditions ............................................................................ 57
DC Electrical Characteristics ......................................................................................... 57
ESD Performance ........................................................................................................... 57
Operating Temperature Ranges...................................................................................... 58
Revised June 2014
CM-T54 Reference Guide
4
Table of Contents
8
APPLICATION NOTES .................................................................................................. 59
8.1 Carrier Board Design Guidelines ................................................................................... 59
8.2 Carrier Board Troubleshooting ...................................................................................... 59
8.3 Ethernet Magnetics Implementation .............................................................................. 60
8.3.1 Magnetics Selection .............................................................................................. 60
8.3.2 Magnetics Connection .......................................................................................... 60
8.4 Heat-plate Integration..................................................................................................... 60
Revised June 2014
CM-T54 Reference Guide
5
Revision Information
Table 1
Date
Mar 2014
May 2014
June 2014
Revision Notes
Description
First release
Fixed PMIC_PWRON pin# to 165 instead of 162 in table 44.
Fixed Table 22 heading to “USB 3.0 OTG interface signals”
Table 51: CM-T54 connector implementation revised to “2-sides PCB
based SODIMM-204 edge connector”
Please check for a newer revision of this manual at the CompuLab web site
http://www.compulab.co.il/. Compare the revision notes of the updated manual from the web site
with those of the printed or electronic version you have.
Revised June 2014
CM-T54 Reference Guide
6
Introduction
1
INTRODUCTION
1.1
About This Document
This document is part of a set of reference documents providing information necessary to operate and
program CompuLab CM-T54 Computer-on-Module.
1.2
CM-T54 Part Number Legend
Please refer to the CompuLab website ‘Ordering information’ section to decode the CM-T54 part
number: http://compulab.co.il/products/computer-on-modules/CM-T54/#ordering.
1.3
Related Documents
For additional information, refer to the documents listed in Table 2.
Table 2
Related Documents
Document
CM-T54 Developer Resources
OMAP5432 Reference Manual
OMAP5432 Datasheet
Revised June 2014
Location
http://www.compulab.com/
http://www.ti.com/product/omap5432
http://www.ti.com/product/omap5432
CM-T54 Reference Guide
7
Overview
2
OVERVIEW
2.1
Highlights










Revised June 2014
Texas Instruments OMAP5 Dual core ARM Cortex-A15 MPCore processor capable of
speeds up to 1.5 GHz
ARM Cortex-M4 processors for low-power offload and real-time responsiveness.
Up to 4GB Dual Channel DDR3
Up to 32GB on-board eMMC storage
Multi-core POWERVR™ SGX544-MPx graphics accelerators
Dedicated TI 2D BitBlt graphics accelerator
IVA-HD hardware accelerators enable full HD, multi-standard video encode/decode as well
as stereoscopic 3D (S3D)
HDMI 1.4, LVDS, SATAII (3Gbps), USB3.0 Host + OTG x 1, USB2.0 Host x3, UART x4,
SDIO x3, ADC, Onboard WiFi 802.11b/g/n (2.4GHz), Bluetooth 3.0.
Miniature size: 72 x 68 x 5 mm
SB-T54 carrier board turns the CM-T54 module into SBC-T54 - a single board computer
CM-T54 Reference Guide
8
Overview
2.2
Block Diagram
Figure 1
CM-T54 Block Diagram
HDMI 1.4
LVDS
LVDS
xcvr.
Dual Core
ARM
Cortex-A15
Display
Controller
MIPI-DSI1
MIPI-DSI1 (optional bypass)
IVA-HD 1080p
Parallel 24-bit
display
parallel 24-bit display
16-bit parallel camera
3D
acceleration
(SGX544)
Parallel 16-bit
camera
2D
acceleration
(GC320)
3x multi-lane MIPI-CSI
204-pin SODIMM edge connector
3x I2C
I2S/McBSP
4 x SD/SDIO
105x GPIOs
9x9 keypad
5 x UART
2x SPI
2x MMC / SDIO
4 x McSPI
4x pwm
JTAG
2 x McBSP
1-wire
88W8787
WiFi+BT
9x9 keypad
SDIO3
RS-232 xcvr.
DDR3
ctrl-1
32 bit
DDR3
(up to 4GB)
DDR3
ctrl-2
32 bit
105 x GPIO
optional bypass
RS232
C64+
DSP core
Multiplexed signals
3 x CSI
camera
4x UART
UART4
8-bit
eMMC
5 x I2C
eMMC
4GB to 64GB
(primary boot)
optional bypass
Resistive
touch
TSC2046 touch
panel ctrl.
JTAG
SPI2
SmartReflex
optional bypass
100Mbit
Ethernet
LAN9730
Ethernet ctrl.
USB2.0
USB2.0
USB2.0
USB3503A
USB hub
ABE
subsystem
HSIC3
Mic-in
Revised June 2014
WM8731L
audio codec
TWL6035/37
PMIC
RTC
USB3.0
SATA-II (3Gbps)
optional bypass
Line-out
FDIF face
detection
USB2.0
HSIC2
USB3.0 OTG
Line-in
SmartReflex
1 x 1-wire
SATA
OMAP5432
McBSP3
I2C1
CM-T54 Reference Guide
I2C EEPROM
(board info)
9
Overview
2.3
CM-T54 Features
The "Option" column specifies the configuration code required to have the particular feature.
"+" means that the feature is always available. Strikethrough option means that the option must not be
chosen for the feature to be available.
Table 3
System and Graphics
Feature
Specifications
Texas Instruments OMAP5432 (dual-core ARM Cortex-A15 @ 1.5GHz)
with:
NEON™ SIMD Coprocessor with VFPv4 per ARM core
TMS320DM64 32-bit DSP,
512MB - 4GB, Dual Channel DDR3-1066 with 32-bit bus width.
On-board eMMC flash, 4GB to 32GB
Dedicated IVA-HD audio/video codecs with MPEG1/2/4, H264, H263, DivX,
RealVideo and more codecs support.
Dual Core PowerVR SGX544 3D GPU with API support for DirectX9,
OpenGL-ES1.1 and 2.0, OpenVG 1.1 and OpenCL 1.1 Embedded Profile.
Vivante GC320 2D GPU with API support for OpenWF, DirectFB,
GDI/DirectDraw and Adobe Flash.
CPU
RAM
Storage
Video
Processing Unit
Graphics
Acceleration
Units
Table 4
Display
USB2.0 Host
USB3.0 Host +
OTG
SATA
100Mbps
Ethernet
Serial Ports
(UARTs)
Audio
Camera
RTC
Resistive
Touchscreen
Controller
MMC/SD/SDIO
I2C
SPI
HDQ / 1-Wire
Revised June 2014
C1500
D
N
+
+
I/O
Feature
WiFi and
Bluetooth
Option
Specifications
1x HDMI display interface (with HDMI Audio support)
1x 24-bit Parallel RGB Display interface
1x Remote Frame Buffer interface
1x LVDS Display interface
1x MIPI-DSI Display interface
3x USB2.0 high-speed host ports, 480Mbps, implemented with SMSC
USB3503 USB2.0 Hub onboard
1x USB3.0 super-speed host + OTG port, 5Gbps (backwards compatible)
1x SATA II interface, 3.0 Gbps, integrated controller and PHY
1x 100Base-T Ethernet MAC+PHY onboard, implemented with SMSC
LAN9730 USB-to-LAN bridge.
1x RS-232 port - TX, RX Only, RS-232 levels. (UART4)
3x UART ports - TX, RX, CTS, RTS Only, 1.8V levels (UART1, UART2,
UART5).
1x UART / IrDA / CIR port - TX, RX, CTS, RTS Only, 1.8V levels.
(UART3)
1x On-board audio codec with analog stereo output, stereo input and electret
microphone support
1x I2S compliant interface (McBSP1)
1x I2S compliant interface (McBSP3)
1x Digital Microphone interface (DMIC)
1x Single Lane MIPI-CSI compatible serial camera interface (MIPI-CSI-C)
1x Dual Lane MIPI-CSI compatible serial camera interface (MIPI-CSI-B)
1x Quad Lane MIPI-CSI compatible serial camera interface (MIPI-CSI-A)
1x Parallel camera port (up to 16 bit)
Real time clock, powered by external lithium battery
TSC2046 touchscreen controller. Supports 4-wire resistive panels
2x MMC/SD/SDIO ports 1/4-bit transfer modes. (SDACRD – bootable,
SDIO4)
1x MMC/SD/SDIO port 1/4-bit transfer modes. (WLSDIO)
Implements 802.11b/g/n wireless connectivity standard
Based on Marvell 88W8787. On-board connector for external antenna
Bluetooth 3.0 + High Speed (HS) (also compliant with Bluetooth 2.1 + EDR)
3x I2C interfaces (I2C2, I2C3, I2C4)
2x SPI interfaces (SPI1, SPI3)
1x SPI interface (SPI2)
1x SPI interface (SPI4)
1x HDQ/1-Wire interface
CM-T54 Reference Guide
Option
+
+
+
L
NOT L
U4
U1
+
E
+
+
+
A
+
NOT A
NOT A
+
+
+
+
+
I
+
NOT WB
WB
+
+
NOT I
NOT WB
+
10
Overview
General
Purpose I/O
Keypad
Up to 106 multifunctional signals. Can be used as GPIOs (shared with other
functions)
1x Keypad interface with up-to 9x9 keys
Table 5
Electrical, Mechanical and Environmental Specifications
Supply Voltage
Active power
consumption
Standby/Sleep
consumption
Dimensions
Weight
MTBF
Operation temperature
(case)
Storage temperature
Relative humidity
Shock
Vibration
Connectors
Connector insertion /
removal
Revised June 2014
+
+
3.0V to 5.5V (min 3.2V needed to boot, may be lowered after boot)
TBD
TBD
72 x 68 x 8 mm
25 gram (w/o heat-plate)
> 100,000 hours
Commercial: 0o to 70o C
Extended: -20o to 70o C
Industrial:
-40o to 85o C
-40o to 85o C
10% to 90% (operation)
05% to 95% (storage)
50G / 20 ms
20G / 0 - 600 Hz
SODIMM-204
50 cycles
CM-T54 Reference Guide
11
Core system components
3
CORE SYSTEM COMPONENTS
3.1
OMAP5432 SoC
The Texas Instruments OMAP5432 SoC is a multimedia application device designed to provide bestin-class CPU performance, video, image and graphics processing for a broad range of multimediarich applications. The device includes comprehensive power management techniques required for
high performance mobile products. The device is composed of the following major subsystems:



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

Cortex-A15 microprocessor unit (MPU) subsystem, including two ARM Cortex-A15 cores.

ARMv7 ISA: standard ARM instruction set plus Thumb-2, Jazelle RCT, Java accelerator,
hardware virtualization support and large physical address extensions (LPAE).

Neon SIMD coprocessor and VFPv4 per CPU.

32-KiB instruction and 32-KiB data L1 cache per CPU.

Shared 2-MiB L2 cache.
Digital signal processor (DSP) subsystem
Image and video accelerator high-definition (IVA-HD) subsystem
Cortex-M4 image processing unit (IPU) subsystem, including two ARM Cortex-M4
microprocessors.
Display subsystem
Audio back-end (ABE) subsystem
Imaging subsystem (ISS) consisting of image processor (ISP) and still image coprocessor
(SIMCOP) block.
3D-graphics accelerator subsystem, including POWERVR SGX544 dual-core GPU.
Figure 2
Revised June 2014
OMAP5432 Block Diagram
CM-T54 Reference Guide
12
Core system components
3.2
Multimedia System
3.2.1
3D and 2D Acceleration
OMAP5432 incorporates separate accelerators for 3D and 2D graphics. The dual-core PowerVR
SGX544 GPU from Imagination Technologies is dedicated for 3D rendering tasks while the Vivante
corporation GC230 core is dedicated for 2D graphics acceleration.
The 3D dedicated PowerVR SGX544 GPU supports the following features:





API support for DirectX9, OpenGL-ES1.1 and 2.0, OpenVG 1.1 and OpenCL 1.1 Embedded
Profile.
Second generation universal scalable shader engines (USSE2), multithreaded engines
incorporating pixel and vertex shader functionality.
Programmable image antialiasing
Bilinear, trilinear and anisotropic texture filtering
RGB, ARGB, YUV422 and YUV420 surface formats
The 2D dedicated Vivante GC320 core supports the following features:









3.2.2
API support for OpenWF, DirectFB, GDI/DirectDraw, Adobe Flash.
BitBlt and StretchBlt
DirectFB HW acceleration
YUV-to-RGB color space rotation
Programmable display format conversion with 14source and 7 destination formats
32-phase filter for image and video scaling at 1080p
ROP2, ROP3 and ROP4 full alpha blending and transparency
90, 180, 270 degree rotation on every primitive
Monochrome expansion for text rendering
DSP subsystem
The DSP subsystem is based on a derivative of the TMS320DMC64x+ VLIW DSP core and contains
the following submodules:




Revised June 2014
TMS320DM64 32-bit fixed DSP core for audio processing and general purpose imaging and
video processing, backward compatible with existing C64x video codecs.

32-KiB L1 4-way associative cache

128-KiB L2 8-way associative cache
Dedicated DMA engine with 128 channels for video/audio data transfer between on-chip
memories and DDR3 / peripherals.
Dedicated Memory management unit (MMU) for virtual/physical address translation.
Interrupt controller with up to 128 IRQs.
CM-T54 Reference Guide
13
Core system components
3.2.3
IVA-HD Subsystem
The IVA-HD subsystem is a set of video encoder/decoder hardware accelerators which supports
resolutions up to 1080i/p with full performance of 60fps (or 120 fields), achievable for encode or
decode (not for simultaneous encode and decode). The IVA-HD subsystem supports the following
coder/decoder (codec) standards natively (all functional of these standards are accelerated without
intervention of the DSP).

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

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
H.264 BP/MP/HP encode and decode
H.264 fast profile/RCDO encode and decode
MPEG-4 SP/ASP encode and decode (no support for GMC)
DivX 5.02 and higher encode/decode (no lower versions such as 3.11 and 4.x).
H.263 P0 encode and decode, P3 decode.
Sorenson Spark V0 and V1 decode (no encode support).
MPEG-2 SP/MP encode/decode
MPEG-1 encode/decode
VC-1/WMV9/RTV SP/MP/AP encode and decode
On2 VP6.2/VP7 decode
RealVideo 8/9/10 decode
AVS 1.0 encode and decode
JPEG (also MJPEG) baseline encode and decode
H.264 Annex G (SVC) scalable baseline profile 480p-720p30
H.264 Annex H (MVC) up to 720p30
3.3
Memory
3.3.1
DRAM
CM-T54 is equipped with up to 4GB of onboard dual-channel DDR3 memory. Each DDR3 channel is
32-bits wide and operates at 533 MHz clock frequency (DDR3-1066).
NOTE: CM-T54 boards with 512MB of DRAM (D05 option) utilize only one DDR3 channel.
3.3.2
On-board eMMC storage
CM-T54 is available with an eMMC based onboard storage device. eMMC is the main non-volatile
memory of CM-T54. It is used for boot-loader, operating system and general purpose data storage.
CM-T54 (depending on board configuration) can be equipped with a 4GB, 8GB, 16GB or 32GB
eMMC device.
Revised June 2014
CM-T54 Reference Guide
14
Peripheral Interfaces
4
PERIPHERAL INTERFACES
CM-T54 implements a variety of peripheral interfaces through the SODIMM-204 carrier board
connector. The following notes apply to interfaces available through the SODIMM-204 interface:




Some interfaces/signals are available only with/without certain configuration options of the
CM-T54 CoM. The availability restrictions of each signal are described in the “Signals
description” table for each interface.
Many of the CM-T54 carrier board interface pins are multifunctional. Up-to 8 functions (ALT
modes) are accessible through each multifunctional pin. Multifunctional pins are denoted with
an asterisk (*). For additional details, please refer to chapter 5.6.
Only one multifunctional pin can be used for each function, configuring several
multifunctional pins to implement the same function will result in unexpected system
behavior.
All of the CM-T54 digital interfaces operate at 1.8V voltage levels, unless otherwise noted.
The signals for each interface are described in the “Signal description” table for the interface in
question. The following notes provide information on the “Signal description” tables:





“Signal name” – The name of each signal with regards to the discussed interface. The signal
name corresponds to the relevant function in cases where the carrier board pin in question is
multifunctional.
“Pin#” – The carrier board interface pin number where the discussed signal is available,
multifunctional pins are denoted with an asterisk.
“Type” – Signal type, see the definition of different signal types below
“Description” – Signal description with regards to the interface in question.
“Availability” – Depending on CM-T54 Configuration options, certain carrier board
interface pins are physically disconnected (floating) on-board CM-T54. The “Availability”
column summarizes configuration requirements for each signal. All the listed requirements
must be met (logical AND) for a signal to be “available” unless otherwise noted.
Each described signal can be one of the following types. Signal type is noted in the “Signal
description” tables. Multifunctional pin direction, pull resistor and open drain functionality is
software controlled. The “Type” column header for multifunctional pins refers to the recommended
pin configuration with regards to the discussed signal.













Revised June 2014
“AI” – Analog Input
“AO” – Analog Output
“AIO” – Analog Input/Output
“AP” – Analog Power Output
“I” – Digital Input
"O" – Digital Output
“IO” – Digital Input/Output
“OD” – Open Drain Signal (not pulled up on-board CM-T54 unless otherwise noted).
“P” – Power
“SPU” – Software controlled pull up to 1.8V
“SPD” – Software controlled pull down to GND
"PU18" – Always pulled up to 1.8V on-board CM-T54, (typ. 5KΩ-15KΩ).
"PD" - Always pulled down on-board CM-T54, (typ. 5KΩ-15KΩ).
CM-T54 Reference Guide
15
Peripheral Interfaces
4.1
Serial ATA Interface
The CM-T54 incorporates a single SATA-II port implemented with the OMAP5432 integrated
SATA controller and PHY. The interface supports the following main features:




SATA 1.5 Gb/s and SATA 3.0 Gb/s speed.
Support for all SATA power management features.
Hardware-assisted Native Command Queuing (NCQ) for up to 32 entries.
Activity LED
Table 6
SATA signals
Signal Name
Pin #
Type
SATA_RXM
SATA_RXP
SATA_TXM
SATA_TXP
SATA_ACTLED
29
27
23
21
60*
AI
AI
AO
AO
O
Description
SATA receive data pair
SATA transmit data pair
Activity led control signal
Availability
Always available
Always available
Always available
Always available
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.2
Display Interfaces
The CM-T54 display subsystem is responsible for grabbing an image from the system memory (frame
buffer) and displaying that image on an LCD panel or a TV set.
The subsystem can simultaneously display different pictures using 3 independent LCD outputs
(LCD1, LCD2 and LCD3) in addition a TV output. Each of the LCD outputs can be available through
one of the following CM-T54 interfaces:



Display serial interface ( DSI / MIPI-DSI )
Remote Frame Buffer interface (RFBI / MIPI DBI 2.0)
24 bit Parallel Display Interface (DPI)
The TV output can be available through one of the following CM-T54 interfaces:


24 bit Parallel Display Interface (DPI)
High-definition multimedia interface (HDMI)
Figure 3 summarizes the display sources, relevant interfaces and architecture of the CM-T54 display
subsystem.
Revised June 2014
CM-T54 Reference Guide
16
Peripheral Interfaces
CM-T54 Display subsystem
OMAP5432 SoC
CM-T54 BOARD
HDMI
CONTROLLER
& PHY
24-bit Parallel Display
Interface (DPI)
PIN MUX
mux
LCD3
HDMI
mux
LCD2
RFBI
RFBI
Interface
LCD1
MIPI DSI
CONTROLLER
& PHY
Display
Controller
(DISPC)
4.2.1
4 lane
MIPI-DSI
interface
DPI / RFBI
Interface
OMAP SoC BORDER
TV
Optional
DSI-to-LVDS
CONVERTER
LVDS Display
Interface
Optional
Bypass
CM-T54 SODIMM-204 Carrier board
interface
Figure 3
Parallel Display Interface (DPI)
The Parallel Display interface of CM-T54 can be used to drive data from any of the display sources
(LCD1, LCD2, LCD3 or TV) available with CM-T54 (see Figure 3 above). The interface is
compatible with MIPI DPI protocol.
When LCD1, LCD2 or LCD3 are accessed through the parallel display interface 12, 16, 18 and 24 bit
RGB modes are supported. The TV output is a 30-bit RGB interface, however only the MSB
(R[9:2],G[9:2],B[9:2]) are available through the parallel RGB interface. The following standards are
supported:
Table 7
Parallel Display Interface signals
Signal Name
Pin #
Type
Description
DISPC_PCLK
DISPC_HSYNC
DISPC_VSYNC
DISPC_DE
DISPC_FID
98*
100*
102*
104*
66*
O
O
O
O
O
Pixel clock
Horizontal synchronization
Vertical synchronization
Data validation/blank, data enable
The FID signal indicates the field identifier of
the LCD# output field:
0 means even
1 means odd
B0
B0
B0
B0
B2
B1
B1
B1
B1
B3
B2
B2
B2
B2
B4
B3
B3
B3
B3
B5
G0
B4
B4
B4
B6
G1
G0
B5
B5
B7
G2
G1
G0
B6
B8
G3
G2
G1
B7
B9
R0
G3
G2
G0
G2
R1
G4
G3
G1
G3
R2
G5
G4
G2
G4
R3
R0
G5
G3
G5
R1
R0
G4
G6
R2
R1
G5
G7
R3
R2
G6
G8
R4
R3
G7
G9
R4
R0
R2
R5
R1
R3
12-bit
DISPC_DATA0
DISPC_DATA1
DISPC_DATA2
DISPC_DATA3
DISPC_DATA4
DISPC_DATA5
DISPC_DATA6
DISPC_DATA7
DISPC_DATA8
DISPC_DATA9
DISPC_DATA10
DISPC_DATA11
DISPC_DATA12
DISPC_DATA13
DISPC_DATA14
DISPC_DATA15
DISPC_DATA16
DISPC_DATA17
Revised June 2014
106*
108*
110*
112*
116*
118*
120*
122*
124*
126*
128*
130*
134*
136*
138*
140*
94*
92*
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
16-bit
18-bit
CM-T54 Reference Guide
Availability
24-bit
30-bit
Always available
Always available
Always available
Always available
Without “I”
option
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
17
Peripheral Interfaces
DISPC_DATA18
DISPC_DATA19
DISPC_DATA20
DISPC_DATA21
DISPC_DATA22
DISPC_DATA23
142*
144*
146*
148*
74*
76*
O
O
O
O
O
O
R2
R3
R4
R5
R6
R7
R4
R5
R6
R7
R8
R9
Always available
Always available
Always available
Always available
Always available
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.2.2
Remote Frame buffer interface (RFBI)
The RFBI interface can be used to drive data from LCD1, LCD2 or LCD outputs of DISPC T54 (see
Figure 3 above). The interface supports the following features:




MIPI DBI protocol support.
8, 9, 12 and 16-bit parallel interface.
Programmable pixel memory formats
Programmable output formats on one or multiple cycles per pixel.
Please refer to OMAP5432 reference manual for detailed information on the RFBI interface.
Table 8
Parallel Display Interface signals
Signal Name
Pin #
Type
Description
Availability
RFBI_RE
RFBI_WE
RFBI_A0
RFBI_CS0
RFBI_TE_VSYNC0
98*
102*
104*
100*
94*
O
O
O
O
I
Always available
Always available
Always available
Always available
RFBI_HSYNC0
RFBI_DATA0
RFBI_DATA1
RFBI_DATA2
RFBI_DATA3
RFBI_DATA4
RFBI_DATA5
RFBI_DATA6
RFBI_DATA7
RFBI_DATA8
RFBI_DATA9
RFBI_DATA10
RFBI_DATA11
RFBI_DATA12
RFBI_DATA13
RFBI_DATA14
RFBI_DATA15
92*
106*
108*
110*
112*
116*
118*
120*
122*
124*
126*
128*
130*
134*
136*
138*
140*
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Read access signal
Write access signal
Command/Data selection signal
Chip select signal for LCD
Tearing effect synchronization signal (TE or
VSYNC for LCD panel 1)
HSYNC from LCD panel
RFBI I/O Data 0
RFBI I/O Data 1
RFBI I/O Data 2
RFBI I/O Data 3
RFBI I/O Data 4
RFBI I/O Data 5
RFBI I/O Data 6
RFBI I/O Data 7
RFBI I/O Data 8
RFBI I/O Data 9
RFBI I/O Data 10
RFBI I/O Data 11
RFBI I/O Data 12
RFBI I/O Data 13
RFBI I/O Data 14
RFBI I/O Data 15
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.2.3
LVDS Display interface
The LVDS interface can be used to transmit either LCD1 or LCD2 data of OMAP5432 DISPC (see
Figure 3 above). The LVDS interface available with CM-T54 is derived by converting the MIPI-DSI
data originating from OPMAP5432 into LVDS compatible data. The conversion is achieved by a
Revised June 2014
CM-T54 Reference Guide
18
Peripheral Interfaces
MIPI-DSI to LVDS bridge component populated onboard CM-T54. The bridge component supports
the following features:



Supports 18bpp and 24bpp DSI video packets with RGB666 and RGB888 formats.
Max resolution up to 60fps WUXGA 1920x1200 at 18bpp and 24bpp color with reduced
blanking.
LVDS output clock range of 25MHz – 154MHz.
The bridge component can send pixel data in one of the following formats (software configurable).
Figure 4
LVDS Data format A – 18bpp
cycle 'n-1'
cycle 'n'
LVDS Pair 0
G0
R5
R4
R3
R2
R1
R0
LVDS Pair 1
B1
B0
G5
G4
G3
G2
G1
LVDS Pair 2
DE
VS
HS
B5
B4
B3
B2
LVDS Pair 3
Figure 5
LVDS Data format B – 18bpp (24bpp source to 18bpp display)
cycle 'n-1'
cycle 'n'
LVDS Pair 0
G2
R7
R6
R5
R4
R3
R2
LVDS Pair 1
B3
B2
G7
G6
G5
G4
G3
LVDS Pair 2
DE
VS
HS
B7
B6
B5
B4
LVDS Pair 3
Figure 6
LVDS Data format C – 24bpp option 1
cycle 'n-1'
cycle 'n'
LVDS Pair 0
G2
R7
R6
R5
R4
R3
R2
LVDS Pair 1
B3
B2
G7
G6
G5
G4
G3
LVDS Pair 2
DE
VS
HS
B7
B6
B5
B4
LVDS Pair 3
0
B1
B0
G1
G0
R1
R0
Figure 7
LVDS Data format D – 24bpp option 2
cycle 'n-1'
G0
R5
R4
R3
R2
R1
R0
LVDS Pair 1
B1
B0
G5
G4
G3
G2
G1
LVDS Pair 2
DE
VS
HS
B5
B4
B3
B2
LVDS Pair 3
0
B7
B6
G7
G6
R7
R6
Table 9
Revised June 2014
cycle 'n'
LVDS Pair 0
LVDS Display Interfaces signals
CM-T54 Reference Guide
19
Peripheral Interfaces
4.2.4
Signal Name
Pin #
Type
LVDS_CLK_N
LVDS_CLK_P
LVDS_TX0_N
LVDS_TX0_P
LVDS_TX1_N
LVDS_TX1_P
LVDS_TX2_N
LVDS_TX2_P
LVDS_TX3_N
LVDS_TX3_P
35
33
41
39
47
45
53
51
59
57
AO
AO
AO
AO
AO
AO
AO
AO
AO
AO
Description
Availability
Differential clock pair
Only with “L” option
Differential data 0 pair
Only with “L” option
Differential data 1 pair
Only with “L” option
Differential data 2 pair
Only with “L” option
Differential data 3 pair
Only with “L” option
MIPI Display Interface
The MIPI Display interface included with CM-T54 is derived from the MIPI-DSI protocol engine and
the MIPI-DSI PHY integrated into the OMAP5432 SoC. The MIPI-DSI port can be used to transmit
either LCD1 or LCD2 data of OMAP5432 DISPC (see Figure 3 above). The MIPI DSI interface
supports the following main features:








Up-to four data-configurable lanes in addition to one clock lane.
Video mode and command mode support
Bidirectional data link support for command mode (only one data lane is used in reverse
direction)
RGB16, RGB18 nonpacked, and RGB24 format support for command mode
RGB16, RGB18 packed and nonpacked, and RGB24 format support for video mode.
Burst for video mode
Maximum data rate of 1256Mbps per data pair for four data lane configuration (627.75MHz)
Data splitter for 2, 3 and 4-date lane configurations.
Please refer to OMAP5432 reference manual for detailed information on the MIPI-DSI interface.
Table 10
MIPI Display Interface signals
Signal Name
Pin #
Type
DSIPORTA_LANE0Y
DSIPORTA_LANE0X
DSIPORTA_LANE1Y
DSIPORTA_LANE1X
DSIPORTA_LANE2Y
DSIPORTA_LANE2X
DSIPORTA_LANE3Y
DSIPORTA_LANE3X
DSIPORTA_LANE4Y
DSIPORTA_LANE4X
DSIPORTA_TE0
35
33
41
39
47
45
53
51
59
57
75*
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
Description
Availability
1 lane (serial data/clock)
Without “L” option
2nd lane (serial data/clock)
Without “L” option
3rd lane (serial data/clock)
Without “L” option
4th lane (serial data/clock)
Without “L” option
5th lane (serial data only)
Without “L” option
DSI1 tearing effect (TE) input 0
Always available
st
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.2.5
HDMI port
Please refer to chapter 4.5 of this document for detailed description of HDMI port.
Revised June 2014
CM-T54 Reference Guide
20
Peripheral Interfaces
4.3
Camera Interfaces
CM-T54 Camera interfaces are derived from the OMAP5432 imaging subsystem (ISS). The
OMAP5432 imaging subsystem deals with the processing of the pixel data coming from an external
image sensor, data from memory (image format encoding and decoding can be done to and from
memory) or from the IVA-HD subsystem. The ISS external image sensor interfaces include three
serial camera interfaces and a single parallel camera interface.
4.3.1
Parallel Camera Interface
The parallel camera interface available with CM-T54 supports the following features:




8bit, 12bit or 16bit input data bus.
Interface Clock frequency of up to 148.5MPix/s
Configurable pixel clock polarity
BT656 and SYNC mode (HS, VS, FIELD, WEN)
Please refer to OMAP5432 reference manual for detailed information on the parallel camera
interface.
Table 11
Parallel Camera Interface signals
Signal Name
CAM_STROBE
CAM_SHUTTER
CAM_GLOBALRESET
CPI_FID
CPI_PCLK
CPI_WEN
CPI_VSYNCIN
CPI_HSYNCIN
CPI_DATA0
CPI_DATA1
CPI_DATA2
CPI_DATA3
CPI_DATA4
CPI_DATA5
CPI_DATA6
CPI_DATA7
CPI_DATA8
CPI_DATA9
CPI_DATA10
CPI_DATA11
CPI_DATA12
CPI_DATA13
CPI_DATA14
CPI_DATA15
Pin #
Type
Description
Availability
93*
81*
O
Flash strobe control signal
O
Mechanical shutter control signal
99*
IO
IO
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Camera global reset release signal
Pixel clock field signal
Pixel clock input
Write enable signal input
Vertical frame synchronization
Horizontal frame synchronization
Input data 0
Input data 1
Input data 2
Input data 3
Input data 4
Input data 5
Input data 6
Input data 7
Input data 8
Input data 9
Input data 10
Input data 11
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
95*
97*
113*
115*
101*
103*
89*
91*
77*
79*
83*
85*
107*
109*
121*
119*
73*
131*
61*
133*
67*
127*
125*
194*
I
Input data 12
I
Input data 13
I
Input data 14
I
Input data 15
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
Revised June 2014
CM-T54 Reference Guide
21
Peripheral Interfaces
4.3.2
MIPI camera interfaces MIPI-CSI
OMAP5432 is equipped with three on-chip instances of MIPI D-PHY / SMIA CCP2 compliant PHY
receivers. Serial pixel data sourced from a compliant image sensor is sent over the MIPI-CSI
interface, de-serialized by the MIPI D-PHY receiver block and re-sent into the OMAP5432 ISS. The
following main features are supported:



Maximum data rate of 1.5Gbps per lane
Data merger for 2, 3 or 4 data lane configuration
All primary and secondary MIPI defined formats
Please refer to OMAP5432 reference manual for detailed information on the MIPI-CSI / SMIA CCP2
camera interfaces.
Table 12
MIPI Camera Interface signals
Signal Name
Pin #
Type
Description
CSIPORTA_LANE0X
CSIPORTA_LANE0Y
CSIPORTA_LANE1X
CSIPORTA_LANE1Y
CSIPORTA_LANE2X
CSIPORTA_LANE2Y
CSIPORTA_LANE3X
CSIPORTA_LANE3Y
CSIPORTA_LANE4X
CSIPORTA_LANE4Y
95*
97*
103*
101*
91*
89*
77*
79*
83*
85*
I
I
I
I
I
I
I
I
I
I
Differential clock positive input
Differential clock negative input
Differential data positive input
Differential data negative input
Differential data positive input
Differential data negative input
Differential data positive input
Differential data negative input
Differential data positive input
Differential data negative input
CSIPORTB_LANE0X
CSIPORTB_LANE0Y
CSIPORTB_LANE1X
CSIPORTB_LANE1Y
CSIPORTB_LANE2X
CSIPORTB_LANE2Y
131*
133*
125*
127*
113*
115*
I
I
I
I
I
I
Differential clock positive input
Differential clock negative input
Differential data positive input
Differential data negative input
Differential data positive input
Differential data negative input
CSIPORTC_LANE0X
CSIPORTC_LANE0Y
CSIPORTC_LANE1X
CSIPORTC_LANE1Y
109*
107*
119*
121*
I
I
I
I
Differential clock positive input
Differential clock negative input
Differential data positive input
Differential data negative input
Availability
MIPI-CSI-A
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
MIPI-CSI-B
Always available
Always available
Always available
Always available
Always available
Always available
MIPI-CSI-B
Always available
Always available
Always available
Always available
Discrete control signals (common to all camera interfaces)
CAM_STROBE
CAM_SHUTTER
CAM_GLOBALRESET
93*
81*
99*
O
Flash strobe control signal
O
Mechanical shutter control signal
IO
Camera global reset release signal
Always available
Always available
Always available
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
Revised June 2014
CM-T54 Reference Guide
22
Peripheral Interfaces
4.4
Audio Subsystem
The following audio interfaces are available with CM-T54:

Analog audio interface, including stereo in, stereo out and an analog microphone (Optional)
Dedicated digital audio interfaces including McBSP, McASP (partial) and Digital
microphone interface.
HDMI Audio.
Figure 8
Audio Subsystem
OMAP5432 SoC
CM-T54 BOARD
Non-Audio I/O
(GPIO/SPI)
Multifunctional I/O
OMAP SoC BORDER
PIN
MUX
DMIC
MCASP
MCBSP1
OMAP5432
Audio
subsystems
4.4.1
Analog / Multifunctional I/O
Optional
Bypass
PIN
MUX
MCBSP3
Optional
WM8731L
Analog Audio
Codec
Miltifunctional I/O
HDMI Audio
HDMI CONTROLLER
& PHY
CM-T54 SODIMM-204 Carrier board
interface


Analog Audio CODEC
The CM-T54 analog audio functionality is implemented by interfacing the Wolfson WM8731L audio
codec with OMAP5432 McBSP3 interface. The Wolfson WM8731L supports the following features:





Highly Efficient Headphone driver
Audio performance (‘A’ weighted): ADC SNR – 90dB, DAC SNR – 100dB.
Microphone input and electret bias with side tone mixer
ADC and DAC sampling frequency: 8kHz – 96kHz.
Selectable ADC high pass filter
The analog audio interface implementation is illustrated in Figure 8 above.
Table 13
Analog Audio Characteristics
Parameter
Test conditions
Min
Typ
Max
Unit
Stereo Headphone Output
0-dB full-scale output voltage
Maximum output power, PO
Rload = 32Ω
Rload = 16Ω
Signal-to-noise ratio, A-weighted,
(see Notes 1 and 2 below)
Total harmonic distortion
Revised June 2014
90
1kHz output,
Rload = 32Ω,
Pout = 10mW
rms (-5dB)
CM-T54 Reference Guide
1.0
30
50
Vrms
97
dB
0.056
-65
mW
0.1
60
%
dB
23
Peripheral Interfaces
Parameter
Test conditions
Pout = 20mW
rms (-2dB)
1 kHz, 100 mVp-p
20Hz – 20kHz, 100mVpp
1 kHz output
1 kHz
1 kHz output, 0dB
Power supply rejection ratio
Programmable gain
Programmable-gain step size
Mute attenuation
Min
-73
Typ
Max
Unit
0.56
-45
50
45
0
1
80
1.0
40
%
dB
dB
6
dB
dB
dB
Line Input to ADC
Input signal level (0 dB)
A-weighted, 0dB gain,
Fsample = 48 kHz.
A-weighted, 0dB gain,
Fsample = 96 kHz.
A-weighted, −60-dB full-scale
input
−1-dB input, 0-dB gain
Signal-to-noise ratio, (see Notes 1
and 2 below)
Dynamic range, (see note 3 below)
Total harmonic distortion
1 kHz, 100 mVp-p
20Hz – 20kHz, 100mVpp
1 kHz input tone
1 kHz input tone, Rsource<50Ω
Guaranteed Monotonic
0dB, 1 kHz input tone
12 dB input gain
0 dB input gain
Power supply rejection ratio
ADC Channel Separation
Programmable-gain
Programmable-gain step size
Mute attenuation
Input resistance
85
1.0
90
Vrms
dB
90
85
90
-34.5
-84
0.006
50
45
90
0
1.5
80
15
30
10
10
20
Input capacitance
dB
-74
0.02
dB
%
dB
+12
dB
dB
dB
dB
kΩ
pF
Microphone Input to ADC
Input signal level (0 dB)
Signal-to-noise ratio, (see Notes 1
and 2)
Dynamic range, (see Note 3)
1.0
85
A-weighted, 0-dB gain
A-weighted, −60-dB full-scale
input
0dB input, 0dB gain
1 kHz, 100 mVp-p
20Hz – 20kHz, 100mVpp
1kHz input, Rsource<50Ω,
MICBOOST bit is 1.
MICBOOST bit is 0,
Rsource<50Ω,
0dB, 1 kHz input tone
Total harmonic distortion,
Power supply rejection ratio
Programmable-gain Boost
Mic Path gain (MICBOOST gain is
additional to this nominal gain)
Mute attenuation
Vrms
dB
85
dB
-60
50
45
34
-55
dB
dB
14
dB
80
10
10
Input resistance
Input capacitance
dB
dB
kΩ
pF
Microphone Bias
Bias voltage
Bias-current source
Output noise voltage
2.375
1kHz to 20kHz
2.475
2.575
3
25
V
mA
nV/√Hz
For additional details, please refer to the Wolfson WM8731L datasheet.
Table 14
Signal Name
HP_OUT_R
HP_OUT_L
LINEIN_R
LINEIN_L
MIC_IN
MIC_BIAS
Revised June 2014
Analog Audio signals
Pin #
Type
201
203
197
199
193
191
AO
AO
AI
AI
AI
AP
Description
Right channel headphone output
Left channel headphone output
Right channel line input
Left channel line input
Microphone input
Electret microphone bias supply
CM-T54 Reference Guide
Availability
Only with “A” option
Only with “A” option
Only with “A” option
Only with “A” option
Only with “A” option
Only with “A” option
24
Peripheral Interfaces
NOTE: The analog audio codec and interface are only available with the ‘A’ configuration
option.
4.4.2
Digital Audio Interfaces
4.4.2.1
McBSP interface
CM-T54 is equipped with two Multi-channel Buffered Serial Ports (McBSP). The McBSP provides a
full-duplex direct serial interface between OMAP5432 and other application devices (such as a digital
base band), audio and voice codec, etc. McBSP can accommodate a wide range of peripherals and
clocked frame oriented protocols. The following main features are supported:







Full Duplex communication
Direct interface to I2S compliant, PCM and TDM bus devices
Support for 8, 12, 16, 20, 24 and 32 bit data sizes.
Bit Reordering support (send/receive LSB)
Independent clocking and framing for receive/transmit up to 48MHz.
External clock and frame sync signals support
Configurable frame sync and clock signals polarity
McBSP integration within CM-T54 is illustrated in Figure 8 above. Please refer to OMAP5432
reference manual for detailed information on the McBSP interface.
Table 15
McBSP signals
Signal Name
Pin #
Type
Description
Availability
McBSP1
McBSP1_CLKX/R
McBSP1_DR
McBSP1_DX
McBSP1_FSX/R
137*
IO
143*
139*
I
O
145*
IO
Transmit/Receive clock (direction is
software configurable)
Serial data receive
Serial data transmit
Transmit/Receive frame sync (direction is
configurable)
Always available
Always available
Always available
Always available
McBSP3
McBSP3_CLKX
McBSP3_DR
McBSP3_DX
McBSP3_FSX
199*
IO
203*
197*
I
O
201*
IO
Transmit/Receive clock (direction is
configurable)
Serial data receive
Serial data transmit
Transmit/Receive frame sync (direction is
software configurable)
Without “A” option
Without “A” option
Without “A” option
Without “A” option
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.4.2.2
McASP interface
CM-T54 features a partial implementation of the Multi-channel Audio Serial Port (McASP). The
McASP module can cooperate in both transmit and receive modes, it is useful for TDM, I2S and DIT
(digital audio interface transmission) data. McASP can also operate as an S/PDIF source PHY. The
following main features are supported:


Revised June 2014
A 32-bit buffer for transmit/receive operations (either receive or transmit at a time).
Dedicated transmit interrupt signal to MPU and DSP subsystems
CM-T54 Reference Guide
25
Peripheral Interfaces

Dedicated transmit DMA request signal to MPU and DSP subsystems
McASP integration within CM-T54 is illustrated in Figure 8 above . Please refer to OMAP5432
reference manual for detailed information on the McASP interface.
Table 16
McASP signals
Signal Name
Pin #
Type
Description
McASP_ACLKR
McASP_ACLKX
McASP_AFSR
McASP_AFSX
McASP_AHCLKR
McASP_AMUTEIN
143*
139*
137*
200*
201*
145*
191*
197*
IO
IO
IO
IO
IO
I
Receive bit clock
Transmit bit clock
Receive frame sync
Transmit frame sync
Receive high-frequency master clock
Mute in signal from external device
Audio transmit/receive data
(OMAP5432 channel 0)
McASP_AXR
IO
Availability
Always available
Always available
Always available
Always available
Without “A” option
Always available
Without “A” option
Without “A” option
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
NOTE: Part of McASP interface signals available with OMAP5432, are not accessible through
the CM-T54 carrier board interface.
4.4.2.3
Digital Microphone Interface
CM-T54 digital microphone interface is derived from the OMAP5432 DMIC module interface. The
DMIC module can support up to 6 digital microphones through the 6-wire DMIC serial interface. The
following main features are supported by the DMIC module:







3 clock signals (same frequency, individually gateable) for all digital microphones.
Up to 3 stereo or 6 mono digital microphones.
Each data signal can support two microphones (working in clock phase opposition).
Programmable output clock frequency (32×FS, 50×FS, 64×FS or 80×FS where FS=48KHz.)
Programmable data sampling sensibility (rising or falling edge).
One RX FIFO (16 words of 144bits)
IRQ & DMA access to MPU & DSP.
DMIC integration within CM-T54 is illustrated in Figure 8 above. Please refer to OMAP5432
reference manual for detailed information on the DMIC module.
Table 17
Signal Name
DMIC_CLK1
DMIC_CLK2
DMIC_CLK3
DMIC_DIN1
DMIC_DIN2
DMIC_DIN3
Digital Microphone signals
Pin #
Type
199*
145*
139*
201*
197*
203*
O
O
O
I
I
I
Description
Digital (stereo) microphone clock output 1
Digital (stereo) microphone clock output 2
Digital (stereo) microphone clock output 3
Digital (stereo) microphone data input 1
Digital (stereo) microphone data input 2
Digital (stereo) microphone data input 3
Availability
Without “A” option
Always available
Always available
Without “A” option
Without “A” option
Without “A” option
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
Revised June 2014
CM-T54 Reference Guide
26
Peripheral Interfaces
4.5
High-Definition Multimedia Interface (HDMI)
The HDMI interface available with CM-T54 is based on the HDMI module of the OMAP5432 SoC.
The video data sourced into the HDMI module from the DISPC TV port (see Figure 3 above). The
HDMI module supports the following standards & features:










HDMI 1.4, HDCP 1.4 and DVI 1.0 compliant, includes support for 3D stereoscopic framepacking formats of the HDMI v1.4 standard: 1080p24Hz, 720p50Hz, 720p60Hz + side-byside half structure: 1080p60Hz).
EIA/CEA-861-D video format support
VESA DMT video format support
Deep color mode support (12-bit and 10-bit deep-color component up to 1080p @60Hz).
Up to 148.5MHz pixel clock (1920 × 1080p @ 60Hz)
24/30/36-bit RGB/YCbCr 4:4:4 (deep color) and 16/20/24-bit YCbCr 4:2:2 video formats.
Uncompressed multichannel (up to 8 channels) audio (L-PCM) support
Master I2C interface for display data channel (DDC connection)
Consumer electronic control (CEC) interface
Integrated high-bandwidth digital content protection (DES_HDCP) encryption engine to
transmit protected content (authentication performed by SW).
Please refer to OMAP5432 reference manual for detailed information on the DMIC module.
Table 18
HDMI signals
Signal Name
Pin #
Type
HDMI_CLK_DX
HDMI_CLK_DY
HDMI_DATA0_DX
HDMI_DATA0_DY
HDMI_DATA1_DX
HDMI_DATA1_DY
HDMI_DATA2_DX
HDMI_DATA2_DY
HDMI_CEC
HDMI_HPD
HDMI_DDC_SCL
HDMI_DDC_SDA
30
32
36
38
42
44
48
50
34*
40*
25*
31*
AO
AO
AO
AO
AO
AO
AO
AO
IO
I
IO
IO
Description
TMDS clock pair
TMDS data 0 pair
TMDS data 1 pair
TMDS data 2 pair
Consumer Electronics Control signal
Hot Plug Detect signal, 5V tolerant.
VESA Data Display Channel clock signal
VESA Data Display Channel data signal
Availability
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.6
WLAN and Bluetooth
CM-T54 features 802.11b/g/n and Bluetooth 3.0 + HS wireless connectivity solution, implemented by
interfacing the AzureWave AW-NH387 WLAN + Bluetooth combo controller module with the
OMAP5432 WLSDIO (MMC-3) interface. The AW-NH387 is based on the Marvell 88W8787
chipset.
WLAN Standards supported:



Revised June 2014
802.11b: 1, 2, 5.5, 11Mbps
802.11g: 6, 9, 12, 18, 24, 36, 48, 54Mbps
802.11n up to 150Mbps
CM-T54 Reference Guide
27
Peripheral Interfaces
WLAN Security features:




WAPI
WEP 64-bit and 128-bit encryption with H/W TKIP processing
WPA/WPA2 (Wi-Fi Protected Access)
AES-CCMP hardware implementation as part of 802.11i security standard
Bluetooth standards supported:

Bluetooth 2.1+EDR data rates of 1, 2 and 3 Mbps
Co-Existence:

Bluetooth and cell phone(GSM/DCS/WCDMA/UMTS/3G) co-existence
Antenna Connection
The AW-NH387 requires a single 2.4GHz antenna for WIFI & Bluetooth. The antenna is connected
via the on-board UFL high frequency connector J1. Any type of 2.4GHz antenna can be used. Please
refer to section 6.3 for connector location.
Table 19
J1 connector data
Manufacturer
Mfg. P/N
Hirose
Mating Connector
U.FL-R-MT(10)
Table 20
Hirose U.FL-LP-040
802.11b/g (WLAN) RF system specifications
Feature
Frequency Band
Number of Channels
Modulation
Medium Access
Protocol
Description
2.4 GHz ISM radio band
802.11b:
USA, Canada and Taiwan – 11
Most European Countries – 13
France – 4, Japan – 14
802.11g:
USA, Canada and Taiwan – 11
Most European Countries – 13
Japan – 13
802.11n(HT20):
Channel 1~13(2412~2472)
802.11n(HT40):
Channel 3~11(2422~2462)
DSSS, OFDM, DBPSK, DQPSK, CCK, 16-QAM, 64-QAM for WLAN
GFSK (1Mbps), Π/4 DQPSK (2Mbps) and 8DPSK (3Mbps) for Bluetooth
CSMA/CA with ACK
WLAN:
802.11b: Minimum -86+-2dBm at 11Mbps
802.11g: Minimum -71+-2dBm at 54Mbps
802.11n: Minimum -68+-2dBm at HT20 MCS7
Minimum -65+-2dBm at HT40 MCS7
Receive Sensitivity
Bluetooth:
GFSK: typical -87dBm
Π/4 DQPSK: typical -88dBm
8DPSK: typical -81dBm
WLAN:
802.11b(Ch1~13): typical 17dBm +/- 2dBm
802.11b(Ch14): typical 10dBm +/- 2dBm
802.11g: typical 14dBm +/- 2dBm
802.11n: typical HT20 13dBm +/- 2dBm
HT40 12dBm +/- 2dBm
Output Power
Bluetooth
Bluetooth Class 1.5>1dBm
For additional details, please refer to the AzureWave AW-NH387 datasheet.
Revised June 2014
CM-T54 Reference Guide
28
Peripheral Interfaces
NOTE: The WLAN and Bluetooth module is available only with the ‘WB’ configuration option.
4.7
Ethernet
CM-T54 incorporates a full-featured 10/100 Ethernet interface. The interface is implemented with an
HSIC interfaced LAN9730 controller with from SMSC.
The CM-T54 Ethernet interface supports the following main features:










Fully compliant with IEEE 802.3/802.3u
10BASE-T and 100BASE-TX support.
TCP/UDP/IP/ICMP checksum offload support.
Full- and Half-duplex
Flexible address filtering modes
Wakeup packet support
PHY support for auto negotiation
PHY support for automatic polarity detection correction
PHY support for HP Auto-MDIX
Activity and speed indicator LED controls
Please refer to LAN9730 datasheet for additional information.
Table 21
Ethernet interface signals
Signal
Name
Pin #
Type
ETH_TXP
ETH_TXN
ETH_RXP
ETH_RXN
ETH_CTAP
8
6
14
12
2
AIO
AIO
AIO
AIO
P
ETH_LED1
4
OD^
ETH_LED2
16
OD^
ETH_LED3
22
OD^
Description
Differential transmit data pair
Differential receive data pair
Magnetics central TAP voltage
Driven low when link is detected.
When link activity is detected, drives
high pulse (80mS).
Driven low when link speed is 100Mbps,
Driven high during 10Mbps operation or
during line isolation.
Driven low when full duplex operation is
detected.
Availability
Only with “E” option
Only with “E” option
Only with “E” option
Only with “E” option
Only with “E” option
Only with “E” option
Only with “E” option
Only with “E” option
NOTE: For magnetics selection recommendations, please refer to section ‎8.3 of this document.
NOTE: Signal denoted with ^ are pulled to ETH_CTAP onboard CM-T54 with 50Ohm
resistors.
4.8
USB interfaces
4.8.1
USB 3.0 On-The-Go
The USB 3.0 OTG interface is implemented with the combination of OMAP5432 super-speed USB
OTG subsystem with the TWL6037 PMIC. The OMAP5432 integrated super-speed USB OTG
Revised June 2014
CM-T54 Reference Guide
29
Peripheral Interfaces
subsystem is comprised from a USB3.0 PHY compliant with USB3.0 specification rev1.0 and a
USB3.0 OTG dual-role-device (DRD) link controller supporting the following modes:




USB2.0 peripheral (function controller) in full and high speed (12 and 480 Mbps
respectively)
USB2.0 host in low, full and high-speed (1.5, 12 and 480 Mbps respectively) with one
downstream port with split transaction support (allows multiple ports through a hub).
USB3.0 peripheral (function controller) in super speed (5Gbps)
USB3.0 host in super speed with one downstream port (allows multiple ports through a hub).
CM-T54 implementation of the USB3.0 OTG interface allows a CM-T54 based system to boot upon
USB power source connection, draw system power from USB and charge the main battery from USB
(appropriate circuitry such as charger must be implemented on carrier board). For additional
information please refer to chapter 5.2.3 and 5.5 of this document.
Please refer to OMAP5432 reference manual for detailed information on the USB3 controller and
PHY.
NOTE: The OMAP5432 implementation of USB3.0 OTG subsystem does not support the
dynamic role switching, that is, OTG protocols HNP, SRP and ADP.
Table 22
USB 3.0 OTG interface signals
Signal Name
Pin #
Type
Description
Availability
USBD0_HS_DP
USBD0_HS_DM
USBD0_SS_RX
USBD0_SS_RY
USBD0_SS_TX
USBD0_SS_TY
USBOTG_ID
176*
178*
182
184
188
190
174*
AIO
AIO
AI
AI
AO
AO
AIO
Always available
Always available
Always available
Always available
Always available
Always available
Always available
VBUS_5V_OTG
180
P
USB2.0 OTG positive data
USB2.0 OTG negative data
USB3.0 OTG receive data positive
USB3.0 OTG receive data negative
USB3.0 OTG transmit data positive
USB3.0 OTG transmit data negative
USB OTG ID signal
VBUS Power input/output/sense.
When USB-OTG is in HOST mode, CM-T54
sources 5V (up to 500mA) at this pin.
When USB-OTG is in DEVICE mode, CMT54 draws VBUS power from the USB host
through this pin.
NOTE: CM-T54 can change power state
upon voltage sensed through this pin. If not
used, should be grounded.
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.8.2
USB 2.0 Host
The CM-T54 high-speed USB interface is implemented with an optional HSIC interfaced USB3503
USB Hub from SMSC. The USB hub supports the following main features:



Three USB 2.0 High Speed (480Mbps) compatible downstream ports
Supports either Single-TT or Multi-TT configurations for Full-Speed (12Mbps) and LowSpeed (1.5Mbps) connections
DP/DM ± 15kV ESD protection (air and contact discharge). IEC 61000-4-2 level 4 ESD
protection without external devices.
Please refer to USB3503 datasheet for additional information.
Revised June 2014
CM-T54 Reference Guide
30
Peripheral Interfaces
Table 23
Signal Name
USB 2.0 Host interface signals
Pin #
Type
Description
Availability
Host Port-1
USB1_DP
172
AIO
USB host port 1 positive data
USB1_DN
170
AIO
USB host port 1 negative data
Only with “U4”
option
Only with “U4”
option
Host Port-2
USB2_DP
166
AIO
USB host port 2 positive data
USB2_DN
164
AIO
USB host port 2 negative data
Only with “U4”
option
Only with “U4”
option
Host Port-3
USB3_DP
160
AIO
USB host port 3 positive data
USB3_DN
158
AIO
USB host port 3 negative data
Only with “U4”
option
Only with “U4”
option
Discrete control signals (common to all USB2.0 interfaces)
4.9
VBUS_EN_REQ
156
O
VBUS_nOVC
162
I
Active high port power control output.
Signals an external VBUS power supply to
enable/disable VBUS for all ports.
Active low over current sense input.
Indicates that an overcurrent condition is
detected by external VBUS supply.
Only with “U4”
option
Only with “U4”
option
UARTs
Up to 4 UART ports are available with CM-T54. All the UART ports are derived from the
OMAP5432 SoC integrated UARTs and support the following features:








16C750 compatibility.
64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter.
Programmable interrupt trigger levels for FIFOs.
Programmable baud rate up to 3.6864Mbps.
Programmable parity (even, odd, and no parity).
Programmable data size (5, 6, 7 or 8 bits)
Programmable stop bits (1, 1.5 or 2bits)
Hardware flow control (RTS/CTS) or software (XON/XOFF)
While all UART interfaces are similar, only UART3 module features IrDA and CIR modes operation
capabilities.
The following IrDA (UART3 only) features are supported:




IrDA 1.4 slow (SIP), medium (MIR) and fast infrared (FIR) communications.
Uplink/downlink CRC generation/detection
Asynchronous transparency (automatic insertion of break character)
Programmable baud rate up-to 4Mbps.
The following CIR (UART3 only) features are supported:




Revised June 2014
Transmit mode only (receive mode is not supported).
Free data forma (supports any remote-control private standards)
Selectable bit rate
Configurable carrier frequency
CM-T54 Reference Guide
31
Peripheral Interfaces

1/2, 5/2, 1/3 or 1/4 carrier duty cycle.
Please refer to OMAP5432 reference manual for detailed information on the integrated UART
controllers.
Table 24
UART signals
Signal Name
Pin #
Type
Description
UART1_TX
UART1_RX
UART1_CTS
UART1_RTS
73*
67*
61*
194*
O
I
O
I
UART-1 serial data transmit
UART-1 serial data receive
UART-1 clear to send.
UART-1 request to send.
UART2_TX
UART2_RX
UART2_CTS
UART2_RTS
3*
5*
7*
9*
O
I
O
I
UART-2 serial data transmit
UART-2 serial data receive
UART-2 clear to send.
UART-2 request to send
Availability
UART-1
Always available
Always available
Always available
Always available
UART-2
Always available
Always available
Always available
Always available
UART-3
UART3_TX_IRTX
UART3_CTS_RCTX
UART3_RTS_IRSD
178*
157*
110*
176*
147*
108*
60*
62*
UART5_TX
UART5_RX
UART5_CTS
UART5_RTS
151*
153*
155*
149*
UART3_RX_IRRX
O
UART-3 serial / IrDA data transmit
I
UART-3 serial / IrDA data receive
O
I
UART-3 clear to send / CIR RC
UART-3 request to send /CIR SD/MODE
O
I
O
I
UART-5 serial data transmit
UART-5 serial data receive
UART-5 clear to send.
UART-5 request to send.
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
UART-5
Always available
Always available
Always available
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.10
RS232
The CM-T54 incorporates a single RS232 port. The following features are supported:



Meets or Exceeds Requirements of TIA/EIA-232-F and ITU v.28 Standards
Programmable baud rate of up to 500 kbit/s
RS-232 bus-pin ESD protection exceeds ±15 kV using the Human-Body Model
The RS232 port is derived from UART-4 of OMAP5432.
Please refer to OMAP5432 reference manual for detailed information on UART4.
NOTE: The RS232 port operates at RS232 voltage levels.
Table 25
RS232 signals
Signal Name
RS232_TXD
RS232_RXD
Revised June 2014
Pin #
Type
117
111
O
I
Description
RS232 serial data out
RS232 serial data in
CM-T54 Reference Guide
Availability
Always available
Always available
32
Peripheral Interfaces
4.11
MMC / SD / SDIO
The CM-T54 features 3 MMC / SD / SDIO host interfaces implemented with the OMAP5432
integrated MMC/SDIO host controller modules. The following main features are supported by
MMC/SDIO modules:






Full compliance with SD command/response sets as defined in SD physical layer
specification V3.01.
Full compliance with SDIO command/response sets and interrupt/read-wait suspend-resume
operations as defined in the SD part E1 specification v3.00.
Full compliance with SD host controller standard specification sets as defined in the SD card
specification part A2 v3.00.
The interfaces support SD v3.0 data transfer rates of up to 48Mbps (at 1.8V).
Software configurable 3.3V and 1.8V operation (MMC-1 only).
Up-to 4-bit transfer modes.
Each MMC/SD/SDIO host controller can support a single MMC / SD / SDIO card or device.
The MMC-1 can operate in both 3.3V and 1.8V voltage levels (software configurable). This is a
bootable interface, meaning CM-T54 can download initial boot software (such as u-boot) from an
SD/MMC card over the MMC-1 interface.
The MMC-2 interface is used for the onboard eMMC storage and is not available through the CMT54 carrier board interface.
The MMC-3 operates only at 1.8V levels. The interface is (optionally) used for CM-T54 WLAN and
Bluetooth functionality (“WB” product option). In case the “WB” option is not populated on-board
CM-T54, the interface is accessible through the carrier board interface.
The MMC-4 operates only at 1.8V levels and is always accessible through the carrier board interface.
Please refer to OMAP5432 reference manual for detailed information on the integrated MMC/SDIO
host controller modules.
NOTE: MMC/SDIO modules implemented by OMAP5432 slightly differ from the SD card
specification. Please refer to OMAP5432 for full differences coverage.
NOTE: 33Ω serial resistors must be populated on the MMC-1 (SDCARD) interface signals if
used on the carrier board. Please refer to SB-T54 for SDCARD interface reference
design.
Table 26
MMC / SD / SDIO signals
Signal Name
Pin #
Type
Description
Availability
MMC-1 (SDCARD)
SDCARD_CLK
SDCARD_CMD
SDCARD_DATA0
SDCARD_DATA1
SDCARD_DATA2
SDCARD_DATA3
SDCARD_CD
SDCARD_WP
80*
82*
84*
86*
88*
90*
61*
67*
194*
O
IO
IO
IO
IO
IO
I
Interface clock
Command signal
Card data bit 0
Card data bit 1
Card data bit 2
Card data bit 3
Active low card detection signal
I
Active low write protection signal
54*
O
Interface clock
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
MMC-3 (WLSDIO)
WLSDIO_CLK
Revised June 2014
CM-T54 Reference Guide
Without “WB” option
33
Peripheral Interfaces
Signal Name
WLSDIO_CMD
WLSDIO_DATA0
WLSDIO_DATA1
WLSDIO_DATA2
WLSDIO_DATA3
Pin #
Type
56*
11*
13*
15*
17*
IO
IO
IO
IO
IO
Description
Availability
Without “WB” option
Without “WB” option
Without “WB” option
Without “WB” option
Without “WB” option
Command signal
Card data bit 0
Card data bit 1
Card data bit 2
Card data bit 3
MMC-4 (SDIO4)
SDIO4_CLK
SDIO4_CMD
SDIO4_DATA0
SDIO4_DATA1
SDIO4_DATA2
SDIO4_DATA3
157*
147*
155*
153*
151*
149*
O
IO
IO
IO
IO
IO
MMC3 Interface clock
Command signal
Card data bit 0
Card data bit 1
Card data bit 2
Card data bit 3
Always available
Always available
Always available
Always available
Always available
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.12
Touch-Screen
CM-T54 features an optional on-board resistive touch-screen controller. The controller is
communicating with the OMAP5432 SoC over the McSPI-2 interface. The interface supports 4-wire
touch panels and is available through the CM-T54 carrier board interface.
Table 27
Signal Name
TS_XP
TS_XN
TS_YP
TS_YN
4.13
Touch-screen signals
Pin #
Type
66
68
70
72
AIO
AIO
AIO
AIO
Description
Touch screen X+ (right)
Touch screen X- (left)
Touch screen Y+ (top)
Touch screen Y- (bottom)
Availability
Only with “I” option
Only with “I” option
Only with “I” option
Only with “I” option
Keypad
The CM-T54 CoM features a 9x9 matrix keypad interface derived from the keyboard module (KBD)
included with the OMAP5432 SoC. The KBD supports the following features:





Event detection on key press and key release
Multikey-press detection and decoding
Long-key detection on prolonged key press (duration of long-key press is reconfigurable onthe fly)
Key press repeat timing reconfigurable on-the-fly
Programmable interrupt generation on key events
Please refer to OMAP5432 reference manual for detailed information on the integrated keyboard
controller module.
Table 28
Signal Name
KBD_ROW0
KBD_ROW1
KBD_ROW2
KBD_ROW3
KBD_ROW4
KBD_ROW5
KBD_ROW6
KBD_ROW7
Revised June 2014
Keypad signals
Pin #
Type
148*
74*
76*
126*
104*
94*
134*
130*
SPU
SPU
SPU
SPU
SPU
SPU
SPU
SPU
Description
Row 0 feed
Row 1 feed
Row 2 feed
Row 3 feed
Row 4 feed
Row 5 feed
Row 6 feed
Row 7 feed
CM-T54 Reference Guide
Availability
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
34
Peripheral Interfaces
Signal Name
KBD_ROW8
KBD_COL0
KBD_COL1
KBD_COL2
KBD_COL3
KBD_COL4
KBD_COL5
KBD_COL6
KBD_COL7
KBD_COL8
Pin #
Type
128*
142*
144*
146*
124*
98*
92*
140*
138*
136*
SPU
O
O
O
O
O
O
O
O
O
Description
Row 8 feed
Column 0 feed, active low
Column 1 feed, active low
Column 2 feed, active low
Column 3 feed, active low
Column 4 feed, active low
Column 5 feed, active low
Column 6 feed, active low
Column 7 feed, active low
Column 8 feed, active low
Availability
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.14
GPIO
Up to 106 GPIO signals are available with CM-T54. Most of the available GPIOs are derived from
the OMAP5432 integrated General-Purpose Interface. OMAP5432 GPIOs are divided into 8 blocks
with 32 GPIOs in each block (a total of 8 x 32 = 256 GPIOs). The OMAP5432 GPIO signals can be
configured for the following applications:




Data input / output
Keyboard interface with a debounce cell
Interrupt generation (in ACTIVE power state)
Wake-up request generation when idle
Please refer to OMAP5432 reference manual for detailed information on the integrated GeneralPurpose Interface.
NOTE: GPIO[n]_WK[m] signals are “always-on” GPIOs, meaning these GPIO signals are
active even while the OMAP5432 is in low power state.
NOTE: Not all GPIO signals supported by the OMAP5432 SoC are available through the CMT54 carrier board interface.
Table 29
GPIO availability
Signal name
Pin #
Type
GPIO1_WK12
GPIO1_WK6
GPIO1_WK7
GPIO3_84
GPIO3_85
GPIO3_86
GPIO3_87
GPIO4_100
GPIO4_101
GPIO4_102
GPIO4_103
GPIO4_104
GPIO4_107
GPIO4_96
GPIO4_97
GPIO4_98
GPIO4_99
193*
152*
154*
9*
7*
5*
3*
199*
145*
139*
137*
143*
200*
191*
201*
197*
203*
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Revised June 2014
Availability
Without “A” option
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Without “A” option
Without “A” option
Without “A” option
Without “A” option
CM-T54 Reference Guide
Notes
Wakeable GPIO
Wakeable GPIO
Wakeable GPIO
35
Peripheral Interfaces
Signal name
Pin #
Type
GPIO5_128
GPIO5_129
GPIO5_130
GPIO5_131
GPIO5_132
GPIO5_133
GPIO5_134
GPIO5_135
GPIO5_136
GPIO5_137
GPIO5_138
GPIO5_139
GPIO5_140
GPIO5_141
GPIO5_142
GPIO5_143
GPIO5_144
GPIO5_153
GPIO5_154
GPIO5_155
GPIO5_156
GPIO6_160
GPIO6_161
GPIO6_162
GPIO6_163
GPIO6_164
GPIO6_165
GPIO6_166
GPIO6_167
GPIO6_168
GPIO6_169
GPIO6_170
GPIO6_171
GPIO6_172
GPIO6_173
GPIO6_174
GPIO6_175
GPIO6_176
GPIO6_177
GPIO6_178
GPIO6_179
GPIO6_180
GPIO6_181
GPIO6_182
GPIO6_183
GPIO6_184
GPIO6_185
GPIO6_186
GPIO6_187
GPIO6_189
GPIO7_192
GPIO7_193
GPIO7_194
GPIO7_195
GPIO7_196
GPIO7_197
GPIO7_198
GPIO7_199
GPIO7_200
GPIO7_201
GPIO8_224
GPIO8_225
GPIO8_226
GPIO8_227
GPIO8_228
GPIO8_229
GPIO8_230
54*
56*
11*
13*
15*
17*
153*
151*
155*
149*
43*
49*
69*
63*
65*
58*
52*
60*
62*
157*
147*
92*
94*
102*
100*
98*
104*
106*
108*
110*
112*
116*
118*
120*
122*
124*
126*
128*
130*
134*
136*
138*
140*
142*
144*
146*
148*
74*
76*
75*
34*
40*
25*
31*
68*
66*
70*
72*
161*
163*
81*
93*
99*
73*
61*
67*
194*
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Revised June 2014
Availability
Notes
Without “WB” option
Without “WB” option
Without “WB” option
Without “WB” option
Without “WB” option
Without “WB” option
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Without “I” option
Without “I” option
Without “I” option
Without “I” option
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
CM-T54 Reference Guide
36
Peripheral Interfaces
Signal name
Pin #
Type
GPIO8_231
GPIO8_232
GPIO8_IN236
GPIO8_IN237
GPIO8_IN238
GPIO8_IN239
GPIO8_IN240
GPIO8_IN241
GPIO8_IN242
GPIO8_IN243
GPIO8_IN244
GPIO8_IN245
GPIO8_IN246
GPIO8_IN247
GPIO8_IN248
GPIO8_IN249
GPIO8_IN250
GPIO8_IN251
GPIO8_IN252
GPIO8_IN253
GPIO8_IN254
GPIO8_IN255
129*
135*
95*
97*
101*
103*
89*
91*
77*
79*
83*
85*
131*
133*
127*
125*
115*
113*
107*
109*
121*
119*
IO
IO
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Availability
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Notes
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
Input Only
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.15
I 2C
The CM-T54 features three general purpose I2C interfaces. The following features are supported:





Compliance with Philips I2C specification version 2.1
Multiple-master operation
Support for standard mode (up to 100K bits/s), fast mode (up to 400K bits/s) and HS mode
(up to 3.4Mbps)
7-bit and 10-bit device addressing modes
Programmable multi-slave channel (responds to four separate addresses)
The I2C interfaces are implemented with OMAP5432 integrated HS I2C controllers. Please refer to
OMAP5432 reference manual for detailed information on the integrated HS I 2C controllers.
Table 30
Signal Name
2
I C signals
Pin #
Type
Description
Availability
I2C-2
I2C2_SDA
I2C2_SCL
49*
43*
SPU/SPD
SPU/SPD
2
I C serial data line
I2C serial clock line
Always available
Always available
I2C-3
I2C3_SDA
I2C3_SCL
135*
129*
SPU/SPD
SPU/SPD
I2C serial data line
I2C serial clock line
Always available
Always available
I2C-4
I2C4_SDA
I2C4_SCL
163*
161*
SPU/SPD
SPU/SPD
I2C serial data line
I2C serial clock line
Always available
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
Revised June 2014
CM-T54 Reference Guide
37
Peripheral Interfaces
4.16
SPI
CM-T54 features four SPI ports. All CM-T54 SPI ports are derived from the OMAP5432 integrated
Multichannel Serial Port Interface (McSPI). McSPI modules support the following main features:







Master/Slave operation support
Wide selection of SPI word lengths, ranging from 4 to 32 bits
Up to 2 master channels or a single slave channel per port
Full/Half duplex
Transmit only/receive only/transmit-and-receive modes
Two DMA requests per channel
Start-bit mode support
Please refer to OMAP5432 reference manual for detailed information on the integrated Multichannel
Serial Port Interfaces.
Table 31
Signal Name
SPI signals
Pin #
Type
Description
Availability
SPI-1
MCSPI1_CLK
MCSPI1_CS0
MCSPI1_CS1
MCSPI1_MOSI
MCSPI1_MISO
66*
58*
52*
65*
63*
IO
IO
IO
IO
IO
SPI-1 Master clock out; slave clock in
SPI-1 Chip select 0
SPI-1 Chip select 1
SPI-1 Master data out; slave data in
SPI-1 Master data in; slave data out
MCSPI2_CLK
MCSPI2_CS0
MCSPI2_CS1
MCSPI2_SIMO
MCSPI2_SOMI
66*
68*
140*
70*
72*
IO
IO
IO
IO
IO
SPI-2 Master clock out; slave clock in
SPI-2 Chip select 0
SPI-2 Chip select 1
SPI-2 Master data out; slave data in
SPI-2 Master data in; slave data out
Always available
Always available
Always available
Always available
Always available
SPI-2
Without “I” option
Without “I” option
Always available
Without “I” option
Without “I” option
SPI-3
MCSPI3_CLK
MCSPI3_CS0
MCSPI3_SIMO
MCSPI3_SOMI
3*
7*
5*
9*
IO
IO
IO
IO
SPI-3 Master clock out; slave clock in
SPI-3 Chip select 0
SPI-3 Master data out; slave data in
SPI-3 Master data in; slave data out
Always available
Always available
Always available
Always available
SPI-4
MCSPI4_CLK
MCSPI4_CS0
MCSPI4_SIMO
MCSPI4_SOMI
54*
15*
11*
13*
IO
IO
IO
IO
SPI-4 Master clock out; slave clock in
SPI-4 Chip select 0
SPI-4 Master data out; slave data in
SPI-4 Master data in; slave data out
Without “WB” option
Without “WB” option
Without “WB” option
Without “WB” option
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.17
General Purpose Timers and PWM
CM-T54 features 11 timers derived from the OMAP5432 integrated General-Purpose. The following
features are supported:



Revised June 2014
Dedicated input trigger for capture mode and dedicated output trigger/PWM signal.
Interrupts generated on overflow, compare and capture
Free-running 32-bit upward counter
CM-T54 Reference Guide
38
Peripheral Interfaces




Autoreload mode
Start/stop mode
Programmable divider clock source (1 to 256)
On-The-Fly read/write register (while counting)
Software can configure the timer signals available through CM-T54 carrier board interface to act as
either an “EVENT CAPTURE” input or a “PWM” output of the respective OMAP5432 timer.
Please refer to OMAP5432 reference manual for detailed information on the integrated General
Purpose timers.
NOTE: Not all timers available with OMAP5432 are accessible through the CM-T54 carrier
board interface.
Table 32
GP Timers and PWM signals
Signal Name
Pin #
Type
Description
TIMER5_PWM_EVT
61*
IO
Timer5 event capture (input) or PWM5 output
TIMER6_PWM_EVT
67*
IO
Timer6 event capture (input) or PWM6 output
TIMER8_PWM_EVT
73*
IO
Timer8 event capture (input) or PWM8 output
TIMER11_PWM_EVT
194*
IO
Timer11 event capture (input) or PWM11 output
Availability
Always
available
Always
available
Always
available
Always
available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.18
HDQ / 1-Wire
The HDQ/1-Wire interface available with CM-T54 is derived from the HDQ1W module integrated
into OMAP5432. The HDQ1W module implements the hardware protocol of the master functions of
the TI/Benchmarq HDQ and the Dallas Semiconductor 1-Wire® protocols.
The following main features are supported:





Benchmark HDQ protocol
Dallas Semiconductor 1-Wire® protocol
Power-down mode
5Kbps communication rate
128byte address space
Please refer to OMAP5432 reference manual for detailed information on the HDQ/1-Wire interface.
Revised June 2014
CM-T54 Reference Guide
39
Peripheral Interfaces
Table 33
HDQ / 1-Wire signals
Signal Name
Pin #
HDQ_SIO
Type
62*
Description
OD
Serial data input/output
Availability
Always available
NOTE: Pins denoted with "*" may be used for other interfaces. For details, please refer to
section ‎5.6 of this document.
4.19
General Purpose ADC (GPADC)
CM-T54 is equipped with a general purpose 12-bit sigma-delta ADC combined with a 16-input
analog multiplexer. The ADC functionality is derived from the GPADC module of TWL6037 power
management companion of OMAP5432. The GPADC allows CM-T54 to monitor a variety of analog
signals using analog-to-digital conversion on the input source. After the conversion completes, the
TWL6037 can inform OMAP5432 that data is ready by generating an interrupt.
Ten of the available inputs are used internally by the TWL6037. Three of the inputs are accessible
through the CM-T54 carrier board interface. The reference voltage GPADC_VREF is supplied to
external components to improve measurement accuracy.
Please refer to TWL6037 reference manual for detailed information on GPADC.
Table 34
GPADC signals
Signal Name
GPADC_VREF
GPADC_IN0
GPADC_IN1
GPADC_IN2
4.20
Pin #
Type
62
175
173
169
Description
P
AI
AI
AI
GPADC output reference voltage
GPADC input 0
GPADC input 1
GPADC input 2
Availability
Always available
Always available
Always available
Always available
General purpose clock
CM-T54 features a general purpose, software configurable clock output signal. The signal is derived
from the OMAP5432 SCRM module. The clock polarity, source frequency and divider are fully
configurable. Please refer to OMAP5432 reference manual for detailed information on the SCRM
module.
Table 35
General purpose clock signal
Signal Name
Pin #
Type
FREF_CLK0_OUT
193*
O
Description
Availability
OMAP5432 auxiliary clock output 0 signal.
Without “A” option
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
4.21
JTAG
The CM-T54 JTAG interface is derived from the OMAP5432 integrated Debug interface. The
following features and standards are supported:



Revised June 2014
Five standard IEEE1149.1 JTAG signals: nTRST, TCK, TMS, TDI and TDO.
Partial support for IEEE1149.7 features.
A return clock (RTCK) due to the clocking requirements of the ARM968 processor
CM-T54 Reference Guide
40
Peripheral Interfaces

Two EMU[1:0] TI extensions. For 14pin JTAG header.
Please refer to OMAP5432 reference manual for detailed information on the integrated debug
interface.
Table 36
Signal Name
JTAG_TCK
JTAG_RTCK
JTAG_TDO
JTAG_TDI
JTAG_TMSC
JTAG signals
Pin #
Type
Description
90*
80*
82*
84*
I
O
O
I
IO
Test clock (pulled down)
Returned test clock (synchronized)
Test data out (pulled up)
Test data in (pulled up)
TMS - Test mode select (pulled up)
TMSC - Test mode control and data scan
(pulled up)
Test reset (pulled down)
Emulation 0 (pulled up)
Emulation 1 (pulled up)
88*
JTAG_nTRST
DRM_EMU0
DRM_EMU1
86*
152*
154*
I
IO
IO
Availability
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
NOTE: Pins denoted with "*" are multifunctional. For details, please refer to section ‎5.6 of this
document.
Revised June 2014
CM-T54 Reference Guide
41
System Logic
5
SYSTEM LOGIC
CM-T54 allows access to several system logic related signals through the carrier board interface.
Please refer to chapter 4 of this document for signal description notes and legend.
5.1
Power Supply
The CM-T54 supports two power supply options:


Regulated DC supply (5V Typical).
Lithium-ion polymer battery.
CM-T54 does not feature an on-board Lithium-ion polymer battery charger. If required, such a
charger must be implemented on the carrier board.
Table 37
Signal Name
5.2
Power signals
Type
VSYS
P
PMID
P
VCC_RTC
P
GND
P
Description
Main power supply. Connect either to a regulated DC supply (5V Typ.) or
directly to a Lithium-ion polymer battery.
In a battery powered design where the TI BQ2xxxx series battery charges are
used, this pin should be connected to the charger PMID pin.
Otherwise this pin can be connected to VSYS.
RTC back-up battery power input. Connect to a 3V coin-cell lithium battery.
Short to GND if RTC back-up is not required.
Common ground.
Power Management
CM-T54 employs several power management techniques implemented by the combination of
OMAP5432 SoC with the TWL6037 onboard Power Management IC (PMIC). Software can control
power delivery to most of the CM-T54 onboard peripherals by communicating with the TWL6037
PMIC. The OMAP5432 internal power consumption is controlled by a dedicated on-chip Power,
Reset and Clock Management subsystem (PRCM) which is capable of gating power & clocks to onchip peripherals as well as controlling power and clock functions derived from TWL6037 PMIC
(through the integrated SmartReflex framework). The PRCM, based on the SmartReflex framework,
supports the following features:





5.2.1
Dynamic clock gating
Dynamic voltage and frequency scaling (DVFS)
Dynamic power switching (DPS)
Static leakage management (SLM)
Adaptive body bias (ABB)
Power Resources & control signals.
The term “power resource” refers to every power rail generated onboard CM-T54 as well as some of
the signals controlled by TWL6037 PMIC. Power rails generated by the carrier board can also be
considered as power resources provided their enable/disable logic is controlled by CM-T45 power
resource signal (PMIC_REGEN1). Most power resources are only used onboard the CM-T54 CoM
and are not accessible through the carrier board interface.
A power resource is always in one of three states:

Revised June 2014
OFF state - The power resource is not operating.
CM-T54 Reference Guide
42
System Logic


MODE_ACTIVE state - The power resource is operating in a mode defined by the
MODE_ACTIVE bits of the respective resource control register in TWL6037.
MODE_SLEEP state - The power resource is operating in a mode defined by the
MODE_SLEEP bits of the respective resource control register in TWL6037.
Transition of a power resource between MODE_SLEEP and MODE_ACTIVE states can only be
triggered when the resource is assigned (by software) to one or both control signals (all resources are
not assigned by default). When a resource is assigned to a control signal, the resource power-state
will follow the logical value of the control signal. A resource can be assigned to one or both control
signals. A resource assigned to both control signals will only enter MODE_SLEEP state in case both
signals request that, the resource will exit MODE_SLEEP when any of the control signals indicates
MODE_ACTIVE.
Table 38
Signal Name
Pin #
Type
Description
PMIC_ENABLE_1
171
I
NSLEEP
N/A
N/A
A power resource control signal allowing carrier board
components to control power-resources of TWL6037.
NOTE: no TWL6037 power resources are assigned to
PMIC_ENABLE_1 by default.
This signal is not available through the carrier board
interface. This signal is driven by OMAP5432 SoC and
sensed by (is an input to) TWL6037 PMIC, allowing
OMAP5432 to trigger TWL6037 power resources
transition into MODE_SLEEP state.
NOTE: no TWL6037 power resources are assigned to
NSLEEP by default.
Table 39
Signal Name
PMIC_REGEN1
5.2.2
Resource control signals
Availability
Always
available
Always
available
Power resource signals accessible from carrier board
Pin #
Type
Description
171
O
This signal is a TWL6037 power-resource. It can be
assigned to one/both resource control signals and be
used to enable/disable carrier board power supplies and
peripherals upon a request from carrier board, or when
CM-T54 transitions between power states. Leave
floating if not used.
Availability
Always
available
CM-T54 Power states
CM-T54 power state is defined by the state of all CM-T54 power-resources.
The following power states are supported by CM-T54 (derived from TWL6037 power states)
Table 40
CM-T54 Power States
CM-T54
State Name
Default Power
Resources state
NO SUPPLY
OFF
BACKUP
OFF
OFF
OFF
(except RTC power)
ACTIVE
MODE_ACTIVE
Revised June 2014
State Description
All of the following inputs are below valid voltage range
(threshold): VSYS, VCC_RTC, PMID, VAC_DETECT and
VBUS_5V_OTG.
CM-T54 is not powered by a valid supply (VSYS < 2.75V), while
any of the following conditions apply:
1. BKBAT > POR (POR threshold is between 2.0V and 2.5V)
2. VBUS_5V_OTG > VBUS_DET (VBUS_DET threshold is
between 2.9V and 3.6V).
3. VAC_DETECT > VAC_DET (VAC_DET threshold is
between 2.9V and 3.6V).
CM-T54 is powered by a valid supply (VSYS > 2.75V), and it is
waiting for an ON-request or condition. All CM-T54 power
resources (except RTC power) are in the OFF state.
CM-T54 is powered by a valid supply (VSYS > 2.75V), and CMT54 has transitioned to an ACTIVE state upon an ON-request or
NSLEEP signal negation. All CM-T54 power resources are in their
MODE_ACTIVE state.
CM-T54 Reference Guide
43
System Logic
CM-T54
State Name
Default Power
Resources state
SLEEP
5.2.3
MODE_ACTIVE
State Description
CM-T54 is powered by a valid supply (VSYS > 2.75V), and the
NSLEEP resource control signal assertion has triggered transition to
SLEEP mode.
Note: Power resources assigned to the NSLEEP resource control
signal (none by default) will enter MODE_SLEEP state.
Power-On & Power-Off
CM-T54 first boot sequence (first transition from OFF to ACTIVE state) starts as soon main power
rail (VSYS) becomes available.
5.2.3.1
ON, OFF requests and gating conditions
CM-T54 will transition from ACTIVE or SLEEP to OFF state upon an OFF request. An OFF request
is a condition upon which the TWL6037 PMIC executes a power-state transition sequence resulting
in CM-T54 transition to OFF state. Some OFF requests have software configurable parameters.
When CM-T54 is in OFF state, only a non-gated/non-masked ON-request will trigger transition to
ACTIVE state. Software can pre-define (mask/unmask and configure) some of the ON-requests
before CM-T54 transitions from ACTIVE or SLEEP states to OFF state.
Table 41
ON-requests effective by default.
Request Name
While CM-T54 is in the OFF state, This request is registered if the system senses a
short low pulse (Tpulse > 15mS) on the PMIC_PWRON pin of the carrier board
interface.
While CM-T54 is either in the ACTIVE or SLEEP states, This request is registered by
means of an interrupt when CM-T54 detects a falling edge on the PMIC_PWRON
signal of the carrier board interface.
Triggered when battery voltage crosses the 3.4V threshold. Battery voltage (vs. GND)
is monitored through the VBAT_SENSE pin of the carrier board interface.
Triggered when voltage on VAC_DETECT signal crosses (up/down) the VAC_DET
threshold. The VAC_DET threshold is between 2.9V and 3.6V when rising, between
2.8V and 3.3V when falling.
Triggered in case one or more of CM-T54 onboard power resources detects an overcurrent and under-voltage condition. A thermal event on some of the power resources
can also trigger this interrupt.
Triggered when voltage on VBUS_5V_OTG pin of carrier board interface rises above
VBUS_DET threshold. VBUS_DET threshold is between 2.9V and 3.6V when rising.
Note: Transition to ACTIVE state upon this request is delayed by 1 second during
which CM-T54 draws power only from the PMID carrier board pin.
Triggered upon an over-voltage condition on the VBUS_5V_OTG pin of carrier board
interface.
PWRON
VBAT_MON
VAC_OK
SHORT
VBUS
OTG_OVV_CH
Table 42
On-Request gating conditions.
Request Name
HOTDIE
RESET
OFF-requests effective by default.
Request Name
PWRON_LPK
Revised June 2014
Description
This conditions applies if the voltage available on the VSYS power rail is less than
3.2V
This condition applies if TWL6037 device temperature exceeds threshold. The
threshold is software selectable. Default value for the threshold is between 118ºC and
141ºC when rising, between 108ºC and 132ºC when falling.
This condition applies when the COLD_RESET_IN signal is asserted.
VSYS_HI
Table 43
Description
Description
A long (12sec by default) assertion of the PMIC_PWRON signal, causes CM-T54 to
transition into OFF state.
CM-T54 Reference Guide
44
System Logic
Request Name
Description
This condition applies if TWL6037 device temperature exceeds thermal shutdown
threshold. CM-T54 transitions into OFF state upon this request. Thermal shutdown
threshold is between 136ºC and 160ºC when rising, between 126ºC and 150ºC when
falling.
This condition applies when the COLD_RESET_IN signal is asserted. CM-T54
transitions into OFF state, and immediately executes transition to ACTIVE state,
effectively causing a cold reset to the system.
This condition applies whenever software writes a logic 1 into the SW_RST field of
TWL6037 FUNC_PMU_CONTROL register. By default, CM-T54 transitions into
OFF state, and immediately executes transition to ACTIVE state, effectively causing a
cold reset to the system.
This condition applies whenever software writes a logic 0 into the DEV_ON field of
TWL6037 FUNC_PMU_CONTROL register. By default, CM-T54 transitions into
OFF state.
This condition applies whenever voltage on the VSYS power rail is falling below
2.75V.
THERMAL
SHUTDOWN
RESET
SW_RST
DEV_ON
VSYS_LO
NOTE: Table 41 and Table 43 only describe requests effective by default. Software may change
effective requests, change thresholds and add additional requests. For detailed
information on start-up events and ON/OFF/SLEEP/WAKE requests please refer to
TWL6037 documentation.
5.2.3.2
ON, OFF and gating signals active by default
The following signals are sources of ON, OFF and gating conditions by default
Table 44
Signal Name
Pin #
Type
Description
COLD_RESET_IN
171
I
Active Low cold reset input signal.
If Asserted, serves as an ON Gating
condition.
VBAT_SENSE
179
AI
VAC_DETECT
181
AI
PMIC_PWRON
165
I
VBUS_5V_OTG
180
AI
multiple
P
VSYS
5.3
ON, OFF and Gating signals active by default
Allows CM-T54 to directly sense main
battery voltage. ON and OFF requests can
be triggered upon voltage sensed through
this signal.
NOTE: short to VSYS if not used.
Allows CM-T54 to directly sense DC power
source. ON and OFF requests can be
triggered upon voltage sensed through this
signal.
NOTE: short to GND if not used.
Pulled-Up Active low PWRON signal
(designed for an ON/OFF switch). ON and
OFF requests can be triggered upon voltage
sensed through this signal. VSYS referenced
logic.
NOTE: leave floating if not used.
VBUS Power input/output/sense. ON
requests can be triggered upon voltage
sensed through this signal.
NOTE: short to GND if not used.
Main system power input and sense. If
VSYS voltage is too low (<3.2V), serves
as an ON Gating condition
Availability
Always available
Always available
Always available
Always available
Always available
Always available
Reset
CM-T54 supports two reset signals: cold reset input (COLD_RESET_IN) and warm reset
input/output (SYS_nRESWARM).
Revised June 2014
CM-T54 Reference Guide
45
System Logic


Cold reset is an input to the TWL6037 PMIC, which triggers a full logic reset to CM-T54.
Cold reset is a global reset that affects every module on the device. The cold reset assertion
also causes SYS_nRESWARM assertion.
Warm reset is also a global reset, but it does not affect all the modules on the device. Usually,
the device does not require a complete reboot on a warm reset.
The COLD_RESET_IN signal should be used as the main system reset.
Table 45
5.4
Reset signals
Signal Name
Pin #
Type
COLD_RESET_IN
171
I
SYS_nRESWARM
187
IO
Description
Availability
Active Low cold reset input signal.
Should be used as main system reset
Active low reset signal, triggered by
asserting cold reset
Always available
Always available
Boot Sequence
CM-T54 boot sequence defines which interface/media is used by CM-T54 to load and execute the
initial software (such as U-boot). CM-T54 can load initial software from following interfaces/media:




The on-board eMMC device.
A USB host using the USB3.0 OTG port (CM-T54 acts as a USB device)
An external SATA drive using the SATA interface.
An external SD/MMC card using the MMC-1 (SDCARD) interface.
CM-T54 will query boot devices/interfaces for initial software in the order defined by the active boot
sequence. A total of two different boot sequences are supported by CM-T54:


Standard sequence: Designed for normal system operation with the on-board eMMC device
as the boot media.
Alternate sequence: Designed to bypass the eMMC device. Using the alternate sequence
allows CM-T54 to boot from external devices such as SATA drive and external SD card,
effectively bypassing the onboard eMMC.
The initial logic value of ALT_BOOT signal defines which of the supported boot sequences is used
by the system.
Table 46
Signal Name
ALT_BOOT
Table 47
5.5
Alternative Boot selection signal
Pin #
185
Type
I
Description
Availability
Boot sequence selector signal. Leave floating or low for
standard boot sequence.
Always
available
CM-T54 Boot sequences
Boot sequence
ALT_BOOT
First device
Second device
Third device
Standard
Alternate
Low or floating
High
Onboard eMMC
External SATA Drive
USB OTG Host
External SD card
N/A
USB OTG Host
Battery & Charger signals
CM-T54 can be used as part of a battery powered device. The signals described in this section define
system behavior in some of the special cases that apply to battery powered devices.
Using USB wall adapters to recharge the main battery is a very common approach. In many cases,
effective battery charging is possible only while the system is active (after boot). Charging the battery
in a scenario where the main battery is fully discharged and the system is powered off must be taken
Revised June 2014
CM-T54 Reference Guide
46
System Logic
into consideration. While CM-T54 requires more than 100mA current for successful boot, the USB
specification limits initial current from a USB host (before USB device initialization) to 100mA.
NOTE: Initial VBUS current limitation to 100mA (if desired) must be implemented on carrier
board
The PMID and USB_PSEL signals allow CM-T54 based designs to overcome the above scenario.
Once the USB charger is connected to the system, a VBUS On-request is detected by CM-T54. Upon
a VBUS On-request, CM-T54 delays system boot by 1sec. During this 1st second, CM-T54 draws
power only from the PMID pin.
This approach allows CM-T54 to enable only the USB charger detection subsystem before drawing
power from VSYS (which is sourced from the 100mA limited VBUS). In case a USB charger is
detected, CM-T54 can assert the USB_PSEL signal, to remove the 100mA current limit, allowing
CM-T54 to boot while still complying with the USB specification.
Figure 9
Booting upon VBUS detection with discharged battery (example)
CM-T54
carrier board
interface
Power Path & Battery Charger
main
Battery
VSYS
power
path
USB connector
(USB charger connected)
PMID
100mA
limit
USB_PSEL
USB
charger
detection
subsystem
VBUS_5V_OTG
USBD_0 differential data
CARRIER BOARD
Table 48
Signal Name
5.6
PMID & USB_PSEL signals
Pin #
Type
Description
PMID
196
PI
USB_PSEL
192
IO
Allow proper transition of CM-T54 from OFF to
ACTIVE state upon a USB charger connection to
the VBUS_5V_OTG signal (in case the main
battery is either discharged or disconnected).
NOTE: Leave USB_PSEL floating if not used.
NOTE: Short PMID to VSYS if not used.
Availability
Always
available
Always
available
Signal Multiplexing Characteristics
Up to 114 of the CM-T54 carrier board interface pins are multifunctional. Multifunctional pins enable
extensive functional flexibility of the CM-T54 CoM by allowing usage of a single carrier board
interface pin for one of several functions. Up-to 8 functions (MUX modes) are accessible through
each multifunctional carrier board interface pin. The multifunctional capabilities of CM-T54 pins are
derived from the OMAP5432 SoC control module.
Revised June 2014
CM-T54 Reference Guide
47
System Logic
NOTE: Pin function selection is controlled by software.
NOTE: Each pin can be used for a single function at a time.
NOTE: Only one pin can be used for each function (in case a function is available on more than
one carrier board interface pin).
NOTE: An empty MUX mode must be considered as a “RESERVED” function and must not be
used.
For additional details, please refer to the OAMP5432 reference manual.
Table 49
Pin #
MUX0
3
5
7
9
11
13
15
17
25
31
34
40
43
49
52
54
56
58
60
61
62
63
65
66
67
68
69
70
72
73
74
75
76
77
79
80
81
82
83
84
85
86
88
89
90
91
92
93
94
95
97
98
99
100
101
102
103
104
106
107
108
109
110
UART2_TX
UART2_RX
UART2_CTS
UART2_RTS
WLSDIO_DATA0
WLSDIO_DATA1
WLSDIO_DATA2
WLSDIO_DATA3
HDMI_DDC_SCL
HDMI_DDC_SDA
HDMI_CEC
HDMI_HPD
I2C2_SCL
I2C2_SDA
MCSPI1_CS1
WLSDIO_CLK
WLSDIO_CMD
MCSPI1_CS0
UART3_CTS_RCTX
TIMER5_PWM_EVT
UART3_RTS_IRSD
MCSPI1_SOMI
MCSPI1_SIMO
MCSPI2_CLK
TIMER6_PWM_EVT
MCSPI2_CS0
MCSPI1_CLK
MCSPI2_SIMO
MCSPI2_SOMI
TIMER11_PWM_EVT
GPIO6_186
DSIPORTA_TE0
GPIO6_187
CSIPORTA_LANE3X
CSIPORTA_LANE3Y
SDCARD_CLK
CAM_SHUTTER
SDCARD_CMD
CSIPORTA_LANE4X
SDCARD_DATA0
CSIPORTA_LANE4Y
SDCARD_DATA1
SDCARD_DATA2
CSIPORTA_LANE2Y
SDCARD_DATA3
CSIPORTA_LANE2X
RFBI_HSYNC0
CAM_STROBE
RFBI_TE_VSYNC0
CSIPORTA_LANE0X
CSIPORTA_LANE0Y
RFBI_RE
CAM_GLOBALRESET
RFBI_CS0
CSIPORTA_LANE1Y
RFBI_WE
CSIPORTA_LANE1X
RFBI_A0
RFBI_DATA0
CSIPORTC_LANE0Y
RFBI_DATA1
CSIPORTC_LANE0X
RFBI_DATA2
Revised June 2014
Multifunctional Signals
MUX1
MUX2
MUX3
MUX4
MCSPI3_CLK
MCSPI3_SIMO
MCSPI3_CS0
MCSPI3_SOMI
MCSPI4_SIMO
MCSPI4_SOMI
MCSPI4_CS0
MCSPI4_CLK
SATA_ACTLED
SDCARD_CD
UART1_CTS CPI_DATA13
HDQ_SIO
SDCARD_WP
UART1_RX CPI_DATA14
DISPC_FID
UART1_TX
CPI_DATA12
DISPC_DATA22
DISPC_DATA23
CPI_DATA4
CPI_DATA5
JTAG_RTCK
KBD_ROW1
KBD_ROW2
MUX5
MUX6
MUX7
Availability
GPIO3_87
GPIO3_86
GPIO3_85
GPIO3_84
GPIO5_130
GPIO5_131
GPIO5_132
GPIO5_133
GPIO7_194
GPIO7_195
GPIO7_192
GPIO7_193
GPIO5_138
GPIO5_139
GPIO5_144
GPIO5_128
GPIO5_129
GPIO5_143
GPIO5_153
GPIO8_228
GPIO5_154
GPIO5_141
GPIO5_142
GPIO7_197
GPIO8_229
GPIO7_196
GPIO5_140
GPIO7_198
GPIO7_199
GPIO8_227
GPIO6_186
GPIO6_189
GPIO6_187
GPIO8_IN242
GPIO8_IN243
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
Always available
Always available
Always available
Always available
Without “WB” option
Without “WB” option
Without “WB” option
Without “WB” option
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Without “WB” option
Without “WB” option
Always available
Always available
Always available
Always available
Always available
Always available
Without “I” option
Always available
Without “I” option
Always available
Without “I” option
Without “I” option
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
GPIO8_224
JTAG_TDO
CPI_DATA6
JTAG_TDI
CPI_DATA7
JTAG_NTRST
JTAG_TMSC
CPI_DATA2
JTAG_TCK
CPI_DATA3
DISPC_DATA17
CAM_SHUTTER
DISPC_DATA16
CPI_PCLK
CPI_WEN
DISPC_PCLK
CPI_FID
DISPC_HSYNC
CPI_DATA0
DISPC_VSYNC
CPI_DATA1
DISPC_DE
DISPC_DATA0
CPI_DATA8
DISPC_DATA1
CPI_DATA9
DISPC_DATA2
GPIO8_IN244
GPIO8_IN245
GPIO8_IN240
KBD_COL5
KBD_ROW5
KBD_COL4
KBD_ROW4
UART3_RX_IRRX
UART3_TX_IRTX
CM-T54 Reference Guide
GPIO8_IN241
GPIO6_160
GPIO8_225
GPIO6_161
GPIO8_IN236
GPIO8_IN237
GPIO6_164
GPIO8_226
GPIO6_163
GPIO8_IN238
GPIO6_162
GPIO8_IN239
GPIO6_165
GPIO6_166
GPIO8_IN252
GPIO6_167
GPIO8_IN253
GPIO6_168
48
System Logic
Pin #
112
113
115
116
118
119
120
121
122
124
125
126
127
128
129
130
131
133
134
135
136
137
138
139
140
142
143
144
145
146
147
148
149
151
152
153
154
155
157
161
163
176
178
191
193
194
197
199
200
201
203
5.7
MUX0
MUX1
RFBI_DATA3
CSIPORTB_LANE2X
CSIPORTB_LANE2Y
RFBI_DATA4
RFBI_DATA5
CSIPORTC_LANE1X
RFBI_DATA6
CSIPORTC_LANE1Y
RFBI_DATA7
RFBI_DATA8
CSIPORTB_LANE1X
RFBI_DATA9
CSIPORTB_LANE1Y
RFBI_DATA10
I2C3_SCL
RFBI_DATA11
CSIPORTB_LANE0X
CSIPORTB_LANE0Y
RFBI_DATA12
I2C3_SDA
RFBI_DATA13
MUX4
CPI_VSYNCIN
CPI_HSYNCIN
DISPC_DATA4
DISPC_DATA5
CPI_DATA11
DISPC_DATA6
CPI_DATA10
DISPC_DATA7
DISPC_DATA8
DISPC_DATA9
DISPC_DATA10
DISPC_DATA11
DISPC_DATA12
MCBSP1_DX
MCSPI2_CS1
MCBSP1_DR
GPIO6_183
DMIC_CLK2
GPIO6_184
UART3_RX_IRRX
GPIO6_185
UART5_RTS
UART5_TX
DRM_EMU0
UART5_RX
DRM_EMU1
UART5_CTS
UART3_TX_IRTX
I2C4_SCL
I2C4_SDA
USBD0_HS_DP
USBD0_HS_DM
MUX3
DISPC_DATA3
MCBSP1_CLKX
RFBI_DATA14
DMIC_CLK3
RFBI_DATA15
GPIO6_182
MUX2
MCBSP1_FSX
DISPC_DATA13
MCASP_AFSR
DISPC_DATA14
MCASP_ACLKX
DISPC_DATA15
DISPC_DATA18
MCASP_ACLKR
DISPC_DATA19
MCASP_AMUTEIN
DISPC_DATA20
DISPC_DATA21
KBD_COL3
CPI_DATA15
KBD_ROW3
CPI_DATA14
KBD_ROW8
KBD_ROW7
CPI_DATA12
CPI_DATA13
KBD_ROW6
KBD_COL8
KBD_COL7
KBD_COL6
KBD_COL0
KBD_COL1
KBD_COL2
SDIO4_CMD
KBD_ROW0
SDIO4_DATA3
SDIO4_DATA2
SDIO4_DATA1
SDIO4_DATA0
SDIO4_CLK
UART3_RX_IRRX
UART3_TX_IRTX
MCASP_AXR
FREF_CLK0_OUT
TIMER8_PWM_EVT
DMIC_DIN2
DMIC_CLK1
MCBSP2_FSX
DMIC_DIN1
DMIC_DIN3
SDCARD_WP
UART1_RTS CPI_DATA15
MCASP_AXR
MCASP_AFSX
MCASP_AHCLKR
MCBSP3_DX
MCBSP3_CLKX
MCBSP3_FSX
MCBSP3_DR
MUX5
MUX6
GPIO6_169
GPIO8_IN251
GPIO8_IN250
GPIO6_170
GPIO6_171
GPIO8_IN255
GPIO6_172
GPIO8_IN254
GPIO6_173
GPIO6_174
GPIO8_IN249
GPIO6_175
GPIO8_IN248
GPIO6_176
GPIO8_231
GPIO6_177
GPIO8_IN246
GPIO8_IN247
GPIO6_178
GPIO8_232
GPIO6_179
GPIO4_103
GPIO6_180
GPIO4_102
GPIO6_181
GPIO6_182
GPIO4_104
GPIO6_183
GPIO4_101
GPIO6_184
GPIO5_156
GPIO6_185
GPIO5_137
GPIO5_135
GPIO1_WK6
GPIO5_134
GPIO1_WK7
GPIO5_136
GPIO5_155
GPIO7_200
GPIO7_201
MUX7
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
SAFE_MODE
GPIO4_96
SAFE_MODE
GPIO1_WK12 SAFE_MODE
GPIO8_230
SAFE_MODE
GPIO4_98
SAFE_MODE
GPIO4_100
SAFE_MODE
GPIO4_107
SAFE_MODE
GPIO4_97
SAFE_MODE
GPIO4_99
SAFE_MODE
Availability
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Always available
Without “A” option
Without “A” option
Always available
Without “A” option
Without “A” option
Always available
Without “A” option
Without “A” option
RTC
The CM-T54 RTC is implemented with the internal RTC of the OMAP5432 SoC. The RTC provides
time and calendar information.
Additionally, a backup battery can keep the RTC running to maintain clock and time information
even if the main supply is not present. If the backup battery is rechargeable, the device also provides a
backup battery charger so it can be recharged when the main battery supply is present. The backup
battery should be connected to the VCC_RTC power input.
NOTE: VCC_RTC must remain valid at all times for proper operation of the on-board RTC.
5.8
LED
The CM-T54 features a single general purpose green LED controlled by GPIO3_80 signal of the
OMAP5432 SoC. The LED is ON when GPIO3_80 is set high.
Revised June 2014
CM-T54 Reference Guide
49
Carrier board Interface
6
CARRIER BOARD INTERFACE
The CM-T54 connects to the carrier board a SODIMM-204 edge connector.
6.1
Connector Pinout
Table 50
Pin #
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
Revised June 2014
Connector P1
CM-T54 Signal Name
Reference
Section
GND
MCSPI3_CLK
GPIO3_87
UART2_TX
MCSPI3_SIMO
UART2_RX
GPIO3_86
MCSPI3_CS0
UART2_CTS
GPIO3_85
MCSPI3_SOMI
UART2_RTS
GPIO3_84
MCSPI4_SIMO
WLSDIO_DATA0
GPIO5_130
MCSPI4_SOMI
WLSDIO_DATA1
GPIO5_131
MCSPI4_CS0
WLSDIO_DATA2
GPIO5_132
GPIO5_133
WLSDIO_DATA3
GND
SATA_TX
SATA_TY
HDMI_DDC_SCL
GPIO7_194
SATA_RX
SATA_RY
GPIO7_195
HDMI_DDC_SDA
LVDS_CLK_P
DSIPORTA_LANE0X
LVDS_CLK_N
DSIPORTA_LANE0Y
GND
LVDS_TX0_P
DSIPORTA_LANE1X
LVDS_TX0_N
DSIPORTA_LANE1Y
GPIO5_138
I2C2_SCL
LVDS_TX1_P
DSIPORTA_LANE2X
LVDS_TX1_N
DSIPORTA_LANE2Y
GPIO5_139
I2C2_SDA
LVDS_TX2_P
DSIPORTA_LANE3X
5.1
4.16
4.14
4.9
4.16
4.9
4.14
4.16
4.9
4.14
4.16
4.9
4.14
4.16
4.11
4.14
4.16
4.11
4.14
4.16
4.11
4.14
4.14
4.11
5.1
4.1
4.1
4.5
4.14
4.1
4.1
4.14
4.5
4.2.3
4.2.4
4.2.3
4.2.4
5.1
4.2.3
4.2.4
4.2.3
4.2.4
4.14
4.15
4.2.3
4.2.4
4.2.3
4.2.4
4.14
4.15
4.2.3
4.2.4
LVDS_TX2_N
DSIPORTA_LANE3Y
4.2.3
4.2.4
Pin #
CM-T54 Signal Name
Reference
Section
2
ETH_CTAP
4.7
4
ETH_LED1
4.7
6
ETH_TXN
4.7
8
ETH_TXP
4.7
10
VSYS
5.1
12
ETH_RXN
4.7
14
ETH_RXP
4.7
16
ETH_LED2
4.7
18
NOT CONNECTED
20
22
24
NOT CONNECTED
ETH_LED3
NOT CONNECTED
26
NOT CONNECTED
28
30
VSYS
HDMI_CLK_DX
32
HDMI_CLK_DY
4.5
34
GPIO7_192
HDMI_CEC
4.14
4.5
36
HDMI_DATA0_DX
4.5
38
HDMI_DATA0_DY
GPIO7_193
HDMI_HPD
4.5
4.14
4.5
42
HDMI_DATA1_DX
4.5
44
HDMI_DATA1_DY
4.5
46
VSYS
5.1
48
HDMI_DATA2_DX
4.5
50
HDMI_DATA2_DY
4.5
GPIO5_144
MCSPI1_CS1
GPIO5_128
MCSPI4_CLK
WLSDIO_CLK
4.14
4.16
4.14
4.16
4.11
40
52
54
CM-T54 Reference Guide
4.7
5.1
4.5
50
Carrier board Interface
Pin #
CM-T54 Signal Name
Reference
Section
Pin #
5.1
56
4.14
4.11
4.14
4.16
4.1
4.14
4.9
62
HDQ_SIO
GPIO5_154
UART3_RTS_IRSD
4.18
4.14
4.9
64
VSYS
5.1
4.14
4.12
4.16
GND
57
LVDS_TX3_P
DSIPORTA_LANE4X
4.2.3
4.2.4
58
59
LVDS_TX3_N
DSIPORTA_LANE4Y
4.2.3
4.2.4
60
CPI_DATA13
SDCARD_CD
TIMER5_PWM_EVT
GPIO8_228
UART1_CTS
GPIO5_141
MCSPI1_SOMI
4.3.1
4.11
4.17
4.14
4.9
4.14
4.16
63
Reference
Section
GPIO5_129
WLSDIO_CMD
GPIO5_143
MCSPI1_CS0
SATA_ACTLED
GPIO5_153
UART3_CTS_RCTX
55
61
CM-T54 Signal Name
65
GPIO5_142
MCSPI1_SIMO
4.14
4.16
66
GPIO7_197
TS_XP
MCSPI2_CLK
67
CPI_DATA14
GPIO8_229
SDCARD_WP
TIMER6_PWM_EVT
UART1_RX
4.3.1
4.14
4.11
4.17
4.9
68
DISPC_FID
MCSPI2_CS0
GPIO7_196
TS_XN
4.2.1
4.16
4.14
4.12
69
GPIO5_140
MCSPI1_CLK
4.14
4.16
70
71
GND
5.1
72
GPIO7_198
MCSPI2_SIMO
TS_YP
GPIO7_199
MCSPI2_SOMI
TS_YN
4.14
4.16
4.12
4.14
4.16
4.12
73
GPIO8_227
CPI_DATA12
TIMER11_PWM_EVT
UART1_TX
4.14
4.3.1
4.17
4.9
74
DISPC_DATA22
GPIO6_186
KBD_ROW1
4.2.1
4.14
4.13
75
GPIO6_189
DSIPORTA_TE0
4.14
4.2.4
76
GPIO6_187
DISPC_DATA23
KBD_ROW2
4.14
4.2.1
4.13
CPI_DATA4
GPIO8_IN242
CSIPORTA_LANE3X
CPI_DATA5
GPIO8_IN243
CSIPORTA_LANE3Y
GPIO8_224
CAM_SHUTTER
CPI_DATA6
GPIO8_IN244
CSIPORTA_LANE4X
CPI_DATA7
GPIO8_IN245
CSIPORTA_LANE4Y
4.3.1
4.14
4.3.2
4.3.1
4.14
4.3.2
4.14
4.3
4.3.1
4.14
4.3.2
4.3.1
4.14
4.3.2
78
VSYS
5.1
80
JTAG_RTCK
SDCARD_CLK
4.21
4.11
82
JTAG_TDO
SDCARD_CMD
4.21
4.11
84
JTAG_TDI
SDCARD_DATA0
4.21
4.11
86
JTAG_NTRST
SDCARD_DATA1
4.21
4.11
5.1
88
JTAG_TMSC
SDCARD_DATA2
4.21
4.11
JTAG_TCK
SDCARD_DATA3
4.21
4.11
DISPC_DATA17
KBD_COL5
GPIO6_160
RFBI_HSYNC0
DISPC_DATA16
KBD_ROW5
GPIO6_161
RFBI_TE_VSYNC0
4.2.1
4.13
4.14
4.2.2
4.2.1
4.13
4.14
4.2.2
77
79
81
83
85
87
GND
89
CPI_DATA2
GPIO8_IN240
CSIPORTA_LANE2Y
4.3.1
4.14
4.3.2
90
91
CPI_DATA3
GPIO8_IN241
CSIPORTA_LANE2X
4.3.1
4.14
4.3.2
92
93
GPIO8_225
CAM_STROBE
4.14
4.3
94
95
CPI_PCLK
GPIO8_IN236
CSIPORTA_LANE0X
4.3.1
4.14
4.3.2
96
VSYS
97
CPI_WEN
GPIO8_IN237
CSIPORTA_LANE0Y
4.3.1
4.14
4.3.2
98
DISPC_PCLK
GPIO6_164
KBD_COL4
RFBI_RE
Revised June 2014
CM-T54 Reference Guide
5.1
4.2.1
4.14
4.13
4.2.2
51
Carrier board Interface
CM-T54 Signal Name
Reference
Section
CAM_GLOBALRESET
GPIO8_226
CAM_SHUTTER
CPI_FID
CPI_DATA0
GPIO8_IN238
CSIPORTA_LANE1Y
4.3
4.14
4.3
4.3.1
4.3.1
4.14
4.3.2
103
CPI_DATA1
GPIO8_IN239
CSIPORTA_LANE1X
4.3.1
4.14
4.3.2
104
105
GND
5.1
106
107
CPI_DATA8
GPIO8_IN252
CSIPORTC_LANE0Y
4.3.1
4.14
4.3.2
108
109
CPI_DATA9
GPIO8_IN253
CSIPORTC_LANE0X
4.3.1
4.14
4.3.2
110
111
RS232_TXD
4.10
112
CPI_VSYNCIN
GPIO8_IN251
CSIPORTB_LANE2X
CPI_HSYNCIN
GPIO8_IN250
CSIPORTB_LANE2Y
4.3.1
4.14
4.3.2
4.3.1
4.14
4.3.2
RS232_RXD
4.10
CPI_DATA11
GPIO8_IN255
CSIPORTC_LANE1X
CPI_DATA10
GPIO8_IN254
CSIPORTC_LANE1Y
4.3.1
4.14
4.3.2
4.3.1
4.14
4.3.2
Pin #
99
101
113
115
117
119
121
123
GND
125
Pin #
100
102
114
116
118
120
122
5.1
124
CPI_DATA15
GPIO8_IN249
CSIPORTB_LANE1X
4.3.1
4.14
4.3.2
126
127
CPI_DATA14
GPIO8_IN248
CSIPORTB_LANE1Y
4.3.1
4.14
4.3.2
128
129
GPIO8_231
I2C3_SCL
4.14
4.15
130
131
CPI_DATA12
GPIO8_IN246
CSIPORTB_LANE0X
4.3.1
4.14
4.3.2
132
133
CPI_DATA13
GPIO8_IN247
CSIPORTB_LANE0Y
4.3.1
4.14
4.3.2
134
135
GPIO8_232
I2C3_SDA
4.14
4.15
136
Revised June 2014
CM-T54 Reference Guide
CM-T54 Signal Name
Reference
Section
GPIO6_163
DISPC_HSYNC
RFBI_CS0
4.14
4.2.1
4.2.2
DISPC_VSYNC
GPIO6_162
RFBI_WE
DISPC_DE
KBD_ROW4
GPIO6_165
RFBI_A0
DISPC_DATA0
GPIO6_166
RFBI_DATA0
DISPC_DATA1
RFBI_DATA1
GPIO6_167
UART3_RX_IRRX
DISPC_DATA2
RFBI_DATA2
GPIO6_168
UART3_TX_IRTX
DISPC_DATA3
GPIO6_169
RFBI_DATA3
4.2.1
4.14
4.2.2
4.2.1
4.13
4.14
4.2.2
4.2.1
4.14
4.2.2
4.2.1
4.2.2
4.14
4.9
4.2.1
4.2.2
4.14
4.9
4.2.1
4.14
4.2.2
VSYS
DISPC_DATA4
GPIO6_170
RFBI_DATA4
DISPC_DATA5
GPIO6_171
RFBI_DATA5
DISPC_DATA6
GPIO6_172
RFBI_DATA6
DISPC_DATA7
GPIO6_173
RFBI_DATA7
DISPC_DATA8
KBD_COL3
GPIO6_174
RFBI_DATA8
DISPC_DATA9
KBD_ROW3
GPIO6_175
RFBI_DATA9
DISPC_DATA10
KBD_ROW8
GPIO6_176
RFBI_DATA10
DISPC_DATA11
KBD_ROW7
GPIO6_177
RFBI_DATA11
VSYS
DISPC_DATA12
KBD_ROW6
GPIO6_178
RFBI_DATA12
DISPC_DATA13
KBD_COL8
GPIO6_179
RFBI_DATA13
5.1
4.2.1
4.14
4.2.2
4.2.1
4.14
4.2.2
4.2.1
4.14
4.2.2
4.2.1
4.14
4.2.2
4.2.1
4.13
4.14
4.2.2
4.2.1
4.13
4.14
4.2.2
4.2.1
4.13
4.14
4.2.2
4.2.1
4.13
4.14
4.2.2
5.1
4.2.1
4.13
4.14
4.2.2
4.2.1
4.13
4.14
4.2.2
52
Carrier board Interface
Pin #
CM-T54 Signal Name
Reference
Section
Pin #
4.2.1
4.13
4.14
4.2.2
4.2.1
4.13
4.16
4.14
4.2.2
4.2.1
4.14
4.13
4.2.1
4.14
4.13
146
DISPC_DATA20
GPIO6_184
KBD_COL2
4.2.1
4.14
4.13
148
DISPC_DATA21
GPIO6_185
KBD_ROW0
4.2.1
4.14
4.13
150
VSYS
5.1
152
GPIO1_WK6
DRM_EMU0
4.14
4.21
154
GPIO1_WK7
DRM_EMU1
4.14
4.21
156
VBUS_EN_REQ
4.8.2
158
USB3_DN
4.8.2
160
USB3_DP
4.8.2
162
VBUS_nOVC
4.8.2
164
USB2_DN
4.8.2
166
168
170
172
174
4.8.2
5.1
4.8.2
4.8.2
4.8.1
4.9
4.8.1
4.9
4.8.1
4.8.1
4.8.1
4.8.1
5.1
4.8.1
4.8.1
MCASP_AFSR
MCBSP1_CLKX
GPIO4_103
4.4.2.2
4.4.2.1
4.14
138
139
DMIC_CLK3
MCASP_ACLKX
GPIO4_102
MCBSP1_DX
4.4.2.3
4.4.2.2
4.14
4.4.2.1
140
141
GND
5.1
142
165
167
169
171
173
MCASP_ACLKR
MCBSP1_DR
GPIO4_104
DMIC_CLK2
GPIO4_101
MCASP_AMUTEIN
MCBSP1_FSX
SDIO4_CMD
GPIO5_156
UART3_RX_IRRX
SDIO4_DATA3
GPIO5_137
UART5_RTS
SDIO4_DATA2
GPIO5_135
UART5_TX
SDIO4_DATA1
GPIO5_134
UART5_RX
SDIO4_DATA0
GPIO5_136
UART5_CTS
SDIO4_CLK
GPIO5_155
UART3_TX_IRTX
GND
GPIO7_200
I2C4_SCL
GPIO7_201
I2C4_SDA
PMIC_PWRON
GPADC_VREF
GPADC_IN2
COLD_RESET_IN
GPADC_IN1
175
GPADC_IN0
177
GND
179
181
183
185
187
189
VBAT_SENSE
VAC_DETECT
VCC_RTC
ALT_BOOT
SYS_nRESWARM
RESERVED
MCASP_AXR
GPIO4_96
MIC_BIAS
193
FREF_CLK0_OUT
GPIO1_WK12
MIC_IN
4.20
4.14
4.4.1
194
195
GND
5.1
196
145
147
149
151
153
155
157
159
161
163
191
Revised June 2014
4.4.2.2
4.4.2.1
4.14
4.4.2.3
4.14
4.4.2.2
4.4.2.1
4.11
4.14
4.9
4.11
4.14
4.9
4.11
4.14
4.9
4.11
4.14
4.9
4.11
4.14
4.9
4.11
4.14
4.9
5.1
4.14
4.15
4.14
4.15
5.2.3.2
4.19
4.19
5.3
4.19
144
4.19
176
5.1
178
5.2.3.2
5.2.3.2
5.1
5.4
5.3
180
182
184
186
188
190
USB2_DP
VSYS
USB1_DN
USB1_DP
USBOTG_ID
UART3_RX_IRRX
USBD0_HS_DP
UART3_TX_IRTX
USBD0_HS_DM
VBUS_5V_OTG
USBD0_SS_RX
USBD0_SS_RY
VSYS
USBD0_SS_TX
USBD0_SS_TY
192
USB_PSEL
4.4.2.2
4.14
4.4.1
Reference
Section
DISPC_DATA14
KBD_COL7
GPIO6_180
RFBI_DATA14
DISPC_DATA15
KBD_COL6
MCSPI2_CS1
GPIO6_181
RFBI_DATA15
DISPC_DATA18
GPIO6_182
KBD_COL0
DISPC_DATA19
GPIO6_183
KBD_COL1
137
143
CM-T54 Signal Name
CM-T54 Reference Guide
CPI_DATA15
SDCARD_WP
TIMER8_PWM_EVT
GPIO8_230
UART1_RTS
PMID
5.5
4.3.1
4.11
4.17
4.14
4.9
5.1 / 5.5
53
Carrier board Interface
Pin #
Reference
Section
DMIC_DIN2
MCASP_AXR
GPIO4_98
MCBSP3_DX
LINEIN_R
DMIC_CLK1
GPIO4_100
MCBSP3_CLKX
LINEIN_L
DMIC_DIN1
MCASP_AHCLKR
GPIO4_97
MCBSP3_FSX
HP_OUT_R
DMIC_DIN3
MCBSP3_DR
GPIO4_99
HP_OUT_L
197
199
201
203
6.2
CM-T54 Signal Name
Pin #
4.4.2.3
4.4.2.2
4.14
4.4.2.1
4.4.1
4.4.2.3
4.14
4.4.2.1
4.4.1
4.4.2.3
4.4.2.2
4.14
4.4.2.1
4.4.1
4.4.2.3
4.4.2.1
4.14
4.4.1
CM-T54 Signal Name
Reference
Section
198
PMIC_ENABLE_1
5.2.1
200
MCASP_AFSX
GPIO4_107
4.4.2.2
4.14
202
PMIC_REGEN1
5.2.1
204
VSYS
5.1
Mating Connectors
Table 51
Connector type
CM-T54 connector
Carrier board (mating) connector P/N
Ref.
Implementation
Mfg.
P/N
P1
2-sides PCB based SODIMM-204 edge connector
Lotes
AAA-DDR-109-K01
Revised June 2014
CM-T54 Reference Guide
54
Carrier board Interface
6.3
Mechanical Drawings
Figure 10
Revised June 2014
CM-T54 Top
CM-T54 Reference Guide
55
Carrier board Interface
Figure 11
CM-T54 bottom (X-Ray view - as seen from top side)
1. All dimensions are in millimeters.
2. Height of all components is < 3.5mm.
3. Baseboard connectors provide 2mm board-to-board clearance.
4. Board thickness is 1.0mm.
Mechanical drawings are available in DXF format at http://compulab.co.il/products/computer-onmodules/CM-T54/#devres
6.4
Standoffs/Spacers
CM-T54 has four mounting holes to physically secure the CoM to the carrier board. Secure CM-T54
to the carrier board by mounting two spacers with any adequate screws and nuts. Spacers must
comply with the following specification:

Revised June 2014
M2x0.4 thread, 2.2±0.2 mm length
CM-T54 Reference Guide
56
Operational Characteristics
7
OPERATIONAL CHARACTERISTICS
7.1
Absolute Maximum Ratings
Table 52
Absolute Maximum ratings
Parameter
Limitations
Main power supply voltage (VSYS)
Backup battery supply voltage (VCC_RTC)
USB OTG VBUS
Min
Typ
Max
Unit
-0.3
2.8
-0.3
3.8/5.0
5.5
3.3
5.25
V
V
V
NOTE: Exceeding the absolute maximum ratings may damage the device.
7.2
Recommended Operating Conditions
Table 53
Recommended Operating Conditions
Parameter
Main power supply voltage (VSYS)
Backup battery supply voltage (VCC_RTC)
VBUS_5V_OTG
7.3
Limitations
Min
Typ
Max
Unit
Normal operation
During boot
3.0
3.3
2.8
4.4
3.8/5.0
3.8/5.0
3.0
5.5
5.5
3.3
5.25
V
V
V
V
If supplied externally
DC Electrical Characteristics
Table 54
DC Electrical Characteristics
Operating
Conditions
Parameter
Min
Typ
Max
Unit
2.3
0.54
V
V
V
V
Multifunctional Digital I/O
VIH
VIL
1.26
-0.5
1.35
VOH (2mA)
VOL (2mA)
0.45
SDCARD interface
1.8V mode
3.3V mode
1.8V mode
3.3V mode
1.8V mode
3.3V mode
1.8V mode
3.3V mode
VIH
VIL
VOH (2mA)
VOL (2mA)
1.27
2.07
0.45
0.42
V
V
V
V
V
V
V
V
5.5
25
V
V
0.58
0.75
1.4
2.25
RS232
TX Voltage Swing
RX Voltage Swing
7.4
-5.5
-25
ESD Performance
Table 55
Revised June 2014
ESD Performance
CM-T54 Reference Guide
57
Operational Characteristics
Interface
RS232
Multifunctional
pins
USB Host ports
(with U4 option)
7.5
ESD Performance
15kV using Human Body Model (HBM)
1kV using Human Body Model (HBM)
5kV using Human Body Model (HBM) (differential signals only)
Operating Temperature Ranges
The CM-T54 is available with three options of operating temperature range.
Table 56
CM-T54 Temperature Range Options
Range
Commercial
Temp.
o
o
0 to 70 C
Extended
-20o to 70o C
Industrial
-40o to 85o C
Revised June 2014
Description
Sample boards from each batch are tested for the lower and upper
temperature limits. Individual boards are not tested.
Every board undergoes a short test for the lower limit (-20o C)
qualification.
Every board is extensively tested for both lower and upper limits
and at several midpoints.
CM-T54 Reference Guide
58
Application Notes
8
APPLICATION NOTES
8.1
Carrier Board Design Guidelines









8.2
Ensure that all VSYS and GND power pins are connected.
Major power rails - VSYS and GND must be implemented by planes, rather than traces.
Using at least two planes is essential to ensure the system signal quality, because the planes
provide a current return path for all interface signals.
It is recommended to put several 100nF and 10/100uF capacitors between VSYS and GND
near the mating connectors.
It is recommended to connect the standoff holes of the carrier board to GND, in order to
improve EMC.
Except for a power connection, no other connection is mandatory for CM-T54 operation. All
power-up circuitry and all required pullups/pulldowns are available onboard CM-T54.
If for some reason you decide to place an external pullup or pulldown resistor on a certain
signal (for example - on the GPIOs), first check the documentation of that signal provided in
this manual. Certain signals have on-board pullup/pulldown resistors required for proper
initialization. Overriding their values by external components will disable board operation.
You must be familiar with signal interconnection design rules. There are many sensitive
groups of signals. For example:

Ethernet, SATA, USB and more signals must be routed in differential pairs and by a
controlled impedance trace.

Audio input must be decoupled from possible sources of carrier board noise.
Be careful when placing components under the CM-T54 module. The carrier board interface
connector provides 1mm mating height. Bear in mind that there are components on the
underside of the CM-T54.
Refer to the SB-T54 carrier board reference design schematics.
Carrier Board Troubleshooting






Revised June 2014
Using grease solvent and a soft brush, clean the contacts of the mating connectors of both the
module and the carrier board. Remnants of soldering paste can prevent proper contact. Take
care to let the connectors and the module dry entirely before re-applying power – otherwise
corrosion may occur.
Using an oscilloscope, check the voltage levels and quality of the VSYS power supply. It
should be as specified in section 0. Check that there is no excessive ripple or glitches. First
perform the measurements without plugging in the module. Then plug in the module and
measure again. Measurement should be performed on the pins of the mating connector.
Using an oscilloscope, verify that the GND pins of the mating connector are indeed at zero
voltage level and that there is no ground bouncing. The module must be plugged in during the
test.
Create a "minimum system" - only power, mating connectors, the module and a serial
interface.
Check if the system starts properly. In system larger than the minimum, possible sources of
disturbance could be:
Devices improperly driving the local bus
CM-T54 Reference Guide
59
Application Notes







External pullup/pulldown resistors overriding the module on-board values, or any other
component creating the same "overriding" effect
Faulty power supply
In order to avoid possible sources of disturbance, it is strongly recommended to start with a
minimal system and then to add/activate off-board devices one by one.
Check for the existence of soldering shorts between pins of mating connectors. Even if the
signals are not used on the carrier board, shorting them on the connectors can disable the
module operation. An initial check can be performed using a microscope. However, if
microscope inspection finds nothing, it is advisable to check using an X-ray, because often
solder bridges are deep beneath the connector body. Note that solder shorts are the most
probable factor to prevent a module from booting.
Check possible signal short circuits due to errors in carrier board PCB design or assembly.
Improper functioning of a customer carrier board can accidentally delete boot-up code from
CM-T54, or even damage the module hardware permanently. Before every new attempt of
activation, check that your module is still functional with CompuLab SB-T54 carrier board.
It is recommended to assemble more than one carrier board for prototyping, in order to ease
resolution of problems related to specific board assembly.
8.3
Ethernet Magnetics Implementation
8.3.1
Magnetics Selection
Refer to the table below for compatible magnetics. The list of “Qualified Magnetics” contains
magnetics verified for proper functional operation by CompuLab. Designers should test and qualify
all magnetics before using them in an application.
Table 57
8.3.2
Qualified Magnetics
Vendor
P/N
Package
UDE
PULSE
RTA-1D4B8V1A
J1011F01PNL
Integrated RJ45
Integrated RJ45
Magnetics Connection
For magnetic modules connection, please refer to the SB-T54 reference design schematics
8.4
Heat-plate Integration
To be added in a future revision of this document.
Revised June 2014
CM-T54 Reference Guide
60
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