Design Study on the Switched and Linear Operation of Broadband CMOS Class-E Power Amplifiers A thesis submitted to the Faculty of Electrical Engineering, Mathematics and Computer Sciences in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering at Delft University of Technology by Ronghui Zhang Thesis supervisors: Ir. Mustafa Acar Dr.-Ing. Mark P. van der Heijden P.D.Eng. Melina Apostolidou NXP Semiconductors Research Eindhoven, The Netherlands Dr.-Ing. Leo C.N. de Vreede Delft University of Technology Delft, The Netherlands August 2010 Abstract This research work aims to gain understanding of the power amplifier (PA) operating as a linear PA under low power drive conditions and as a switch-mode PA in high power drive conditions both with the same Class-E load. Two approaches were taken here. Firstly, an analytical approach was developed to investigate the switching operation of conventional Class-E amplifier. The model used in the analytical approach takes into account the non-ideal switch resistance, finite dc-feed inductance, finite loaded quality factor, and arbitrary switch duty-cycle. This approach presents an accurate closed-form expression for modeling Class-E power amplifier. Using this approach, the frequency response of conventional Class-E power amplifier was studied in detail and the impact of the loaded quality factor and finite dc-feed inductance on the broadband performance was analyzed. It shows that the Class-E PA with conventional load network cannot provide stable output power, efficiency, and reliable operating voltage conditions across a broad frequency band (∆B > 40%). In addition, study of the load impedances of the amplifier indicates that the Class-E PA is sensitive to the load phase angle at fundamental frequency. In the second approach, a purely linear voltage-control current source was constructed numerically as a way to represent the transistor. Based upon that model, the influence of non-ideal drive signal on the switching operation was studied. It shows that the power amplifier with finite dc-feed inductance is tolerant to a non-ideal drive signal. For the rise and fall times of 25%T, only 5% drop in drain efficiency was found for the optimum finite dc-feed inductance. The performance of that model in linear operation was also investigated. The results agree with the classical theory for linear power amplifiers. The linearity (intermodulation distortion and 1dB compression point) was analyzed by using a realistic transistor model (an extended drain NMOS). It shows that the Class-B biased PA with finite dc-feed inductance can provide not only similar IMD3 feature as the optimum ClassAB biased PA with RF choke does, but also high efficiency simultaneously. Based upon this device, a systematic design process was applied to implement a broadband high efficiency ClassE PA. The PCB for this broadband high efficiency Class-E PA was fabricated. Good agreement was found between the simulation and measurement. The measurements indicated that the PA achieves a drain efficiency > 67% and a PAE > 52% with a Pout > 30dBm from 560-1050MHz, where the output power variation is within 1.0dB and efficiency variation is within 13%. The highest efficiency is observed at 700MHz from a 5.0V supply with peak drain efficiency of 77% and peak PAE of 65% at 31dBm output power and 17dB power gain. When using dynamic supply modulation, the PA achieves a PAE of 40% and a drain efficiency of 60% at 10dB power back-off across the frequency band 500MHz to 1100MHz. Acknowledgements I would like to take the opportunity to acknowledge to all the people who helped me in my works and life. My sincere gratitude is directed to my daily supervisor Ir. Mustafa Acar at NXP Semiconductors Research. He actively instructed me through the entire project, shared the valuable knowledge with me, offered useful support at every stage of the project, and answered all my questions with great patience. I would like to thank my other two supervisors at NXP Semiconductors Research: Dr.-Ing. Mark P. van der Heijden and P.D. Eng. Melina Apostolidou for the fruitful discussions in daily work and the feedback during the monthly meetings. Also thanks Dr.-Ing. Agnese Bargagli for kind help in Cadence simulation. I am deeply grateful to my supervisor Dr.-Ing. Leo C.N. de Vreede at Delft University of Technology for providing me such a good opportunity to do this interesting research project at NXP, for visiting my progress presentations in Eindhoven, and for reviewing my thesis report. I also thank all the M.Sc. Thesis Committee members for reviewing this report. My thanks are extended to all engineers at NXP Nijmegen, especially Michel de Langen and Tennyson Nguty, for bonding the dies and assembling the boards. I would also like to express my appreciation for the support I received from Jan Vromans in doing the measurements with the Labview setup. I would like to acknowledge my friends and teachers at Delft University of Technology of the Netherlands who were kindly helping me during my course work and teaching me with the best of their knowledge. I owe my loving thanks to my parents, my sisters and friends in China. They supported me very much during my study abroad. Without their encouragement and understanding it would have been impossible for me to finish this work. Ronghui Zhang Eindhoven, The Netherlands August 15th, 2010 iv Contents Abstract iii Acknowledgements iv List of Figures vii List of Tables x Nomenclature xi 1 Introduction 1.1 Motivation . . . . . . . 1.2 Thesis Research Goal . 1.3 State of the Art Review 1.4 Thesis Organization . . . . . . 1 1 2 3 4 . . . . . . . . . 7 7 7 8 8 9 9 10 11 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Background 2.1 Parameters of Power Amplifiers . . 2.1.1 Output Power . . . . . . . . 2.1.2 Power Gain . . . . . . . . . 2.1.3 Efficiency . . . . . . . . . . 2.1.4 Power-Output Capability . . 2.1.5 Linearity . . . . . . . . . . 2.2 Power Amplifier Classification . . . 2.2.1 Linear Power Amplifier . . 2.2.2 Switching Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Switch-Mode Class-E Power Amplifier Analytical Modeling 3.1 Analytical Derivation of Class-E Power Amplifier Model . . . . . . . . . . . . 3.1.1 Circuit Description and Assumptions . . . . . . . . . . . . . . . . . . 3.1.2 Derivation of Class-E Amplifier Equations with Infinite Loaded Quality Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Derivation of Class-E Amplifier Equations with Finite Loaded Quality Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Analysis and Discussion of Class-E Power Amplifier Model . . . . . . . . . . 3.2.1 Accuracy Comparison between Analytical Approach and ADS Solution 3.2.2 Effects of Drain Load Impedances on Class-E Amplifier . . . . . . . . v 17 17 18 19 25 33 34 35 vi 3.3 3.2.3 Broadband Characteristics of Conventional Class-E Output Load Network 45 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4 Effects of Drive Signal and Linear Operation of Class-E Power Amplifier 4.1 Numerical Modeling of CMOS Transistor . . . . . . . . . . . . . . . . 4.2 Effects of Drive Signal on Class-E Power Amplifier . . . . . . . . . . . 4.3 Linear Operation of Class-E Power Amplifier . . . . . . . . . . . . . . 4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 5.1 Analysis of Switching and Linear Operation of ED-NMOS . . . . . . . . . 5.1.1 DC I-V Characteristics and Non-Linear Capacitances of ED-NMOS 5.1.2 Bondwires Simulation . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Switch-Mode Operation of ED-NMOS . . . . . . . . . . . . . . . 5.1.4 Linear Operation of ED-NMOS . . . . . . . . . . . . . . . . . . . 5.2 Broadband Class-E Power Amplifier Design . . . . . . . . . . . . . . . . 5.2.1 Optimum Load Design . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Broadband Output Load Network . . . . . . . . . . . . . . . . . . 5.3 Layout and Post-Layout Simulations . . . . . . . . . . . . . . . . . . . . . 5.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Measurements 6.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . 6.2.1 Comparison of Simulated and Measured Results . . 6.2.2 Dynamic Inverter Gate Bias . . . . . . . . . . . . . 6.2.3 Dynamic Supply Voltage for ED-NMOS and Inverter 6.2.4 Third-Order Intermodulation Distortion . . . . . . . 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 54 58 60 61 . . . . . . . . . . 65 65 65 70 71 71 75 77 82 86 96 . . . . . . . 97 97 98 98 101 102 103 106 7 Conclusions and Future Work 109 7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.2 Recommendations for Future Work . . . . . . . . . . . . . . . . . . . . . . . . 110 A Maple Code for Analytical Analysis 111 Bibliography 121 List of Figures 1.1 1.2 Mixed-mode outphasing amplifier . . . . . . . . . . . . . . . . . . . . . . . . Topologies of output load network for broadband Class-E power amplifiers . . 2.1 2.2 2.3 2.4 Block diagram of power amplifier . . . . . . . . . . . . . . . . . 3rd-order intercept point and 1dB compression point definitions. . Linear power amplifier schematic. . . . . . . . . . . . . . . . . . Waveforms of the gate-to-source voltage Vgs , and drain current Ids A, (b) Class B, (c) Class AB, (d) Class C. . . . . . . . . . . . . . Class-F power amplifier . . . . . . . . . . . . . . . . . . . . . . . Class-D power amplifier . . . . . . . . . . . . . . . . . . . . . . Class-E power amplifier . . . . . . . . . . . . . . . . . . . . . . . 2.5 2.6 2.7 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 . . . . . . . . . . . . . . . . . . . . . of (a) Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class-E amplifier. (a)Basic circuit. (b)Equivalent circuit. . . . . . . . . . . . . General drain voltage and current waveforms . . . . . . . . . . . . . . . . . . Class-E amplifier with finite loaded quality factor . . . . . . . . . . . . . . . . Analytical design flowchart of Class-E power amplifier at a single frequency. . Relations between the elements of the design set K . . . . . . . . . . . . . . . Class-E amplifier components design:(a) for a given device, (b) for a given supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class-E amplifier waveforms for analytical approach and ADS simulation . . . Class-E model in ADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Elements of the design set KP , KC , KL , KX as a function of q . . . . . . . . . . Drain efficiency and power-output capability as a function of q . . . . . . . . . Drain load impedances of Class-E PAs . . . . . . . . . . . . . . . . . . . . . . Equivalent drain load impedance as a function of q: (a)fundamental impedance in terms of resistance and reactance, (b)second and third harmonics impedance in terms of reactance, (c)fundamental impedance in terms of magnitude and phase Effects of load phase angle θ1 on: (a) drain efficiency and KP , (b) maximum drain-source voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms as a function of load phase angle θ1 : (a) drain-source voltage, (b) switch current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effects of magnitude |Z1 | on: (a) drain efficiency and KP , (b) maximum drainsource voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms as a function of |Z1 |: (a) drain-source voltage, (b) switch current . . Effects of load phase angle θ2 of second harmonic impedance: (a) drain efficiency and KP , (b) maximum drain-source voltage and current . . . . . . . . . Waveforms as a function of θ2 : (a) drain-source voltage, (b) switch current . . . Effects of magnitude |Z2 | of second harmonic impedance: (a) drain efficiency and KP , (b) maximum drain-source voltage and current . . . . . . . . . . . . . vii 2 5 7 10 11 12 13 14 15 18 19 26 32 33 33 34 35 36 37 37 38 39 39 40 40 42 42 42 viii 3.20 Waveforms as a function of |Z2 |: (a) drain-source voltage, (b) switch current . . 3.21 Effects of load phase angle θ3 of third harmonic impedance: (a) drain efficiency and KP , (b) maximum drain-source voltage and current . . . . . . . . . . . . . 3.22 Waveforms as a function of θ3 : (a) drain-source voltage, (b) switch current . . . 3.23 Effects of magnitude |Z3 | of third harmonic impedance: (a) drain efficiency and KP , (b) maximum drain-source voltage and current . . . . . . . . . . . . . . . 3.24 Waveforms as a function of |Z3 |: (a) drain-source voltage, (b) switch current . . 3.25 Fundamental impedance as a function of frequency for different Q0 . . . . . . . 3.26 Second harmonic impedance as a function of frequency for different Q0 . . . . 3.27 Effects of finite load quality factor on the wideband operation . . . . . . . . . . 3.28 Fundamental impedance as a function of frequency for different Q0 . . . . . . . 3.29 Effects of finite dc-feed inductance on the wideband operation . . . . . . . . . 3.30 Effects of duty-cycle on the wideband operation . . . . . . . . . . . . . . . . . 43 4.1 4.2 4.3 53 55 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 5.1 5.2 5.3 5.4 5.5 5.6 Simplified small-signal model of Class-E power amplifier . . . . . . . . . . . . 6th-order polynomial functions fitting measured I-V curves . . . . . . . . . . . I-V curves created by Eq. 4.4 for gm = 1, VT H = 0V, Imax = 1A, Vk = 0.05V and λ = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NMOS small-signal equivalent model . . . . . . . . . . . . . . . . . . . . . . S-parameters measured by Cadence and modeled S-parameters using extracted model parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Numerical model of Class-E power amplifier . . . . . . . . . . . . . . . . . . Simulation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test waveforms of drive signal to gate terminal . . . . . . . . . . . . . . . . . Effects of drive signal on the performance of Class-E power amplifier . . . . . Drain-source voltage and drain current waveforms as a function of rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output power and drain efficiency as a function of input power for linear operation Voltage and current waveforms of Class-A and B biasing at q = 1.41 . . . . . . Effects of dc-feed inductance for Class-E power amplifier at 1dB compression point with different gate bias voltages . . . . . . . . . . . . . . . . . . . . . . Waveforms at 1dB compression point for q = 1.41 . . . . . . . . . . . . . . . . Schematics of active device . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout of active device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC I-V measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured DC I-V curves for VBN=VBP=0V . . . . . . . . . . . . . . . . . . Schematics of active device with parasitic capacitance (red) extracted by Cadence ED-NMOS device capacitances obtained by Cadence simulation for different gate bias voltage Vgs : (a)Cds , (b)Cgd , (c)Cgs . . . . . . . . . . . . . . . . . . . . 5.7 Synthesized transistor model . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Bondwires illustrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Bondwires equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Switch-mode performance of ED-NMOS using synthesized model . . . . . . . 5.11 Large signal performance over power sweep at 1GHz for different gate bias and q 5.12 Simulated drain efficiency, power-output capability, 1dB compression point and power gain versus q for Class-A,AB,and B biases. . . . . . . . . . . . . . . . . 43 44 44 44 46 46 47 48 49 50 55 56 56 57 57 58 59 60 61 62 63 64 66 66 67 68 68 69 69 70 70 72 73 75 ix 5.13 3rd-order intermodulation distortion as a function of output power for different q at f0 = 1GHz with ∆ f = 100kHz. . . . . . . . . . . . . . . . . . . . . . . . 76 5.14 Simulated inverter output signal at 1GHz . . . . . . . . . . . . . . . . . . . . . 78 5.15 Calculated supply voltage and load resistance for Pout =31dBm . . . . . . . . . 79 5.16 Simulated results as a function of q for different α . . . . . . . . . . . . . . . . 80 5.17 Drain-source voltage and drain current waveforms for different α . . . . . . . . 81 5.18 Load impedance as a function of q for different α . . . . . . . . . . . . . . . . 82 5.19 Class-E power amplifier design flowchart . . . . . . . . . . . . . . . . . . . . 83 5.20 Effects of load phase angle θ1 on the performance of power amplifier . . . . . . 84 5.21 Optimum fundamental load impedances ZL1opt over frequency . . . . . . . . . 84 5.22 Ideal output power, drain efficiency and PAE for the ideal optimum load impedances 84 5.23 Broadband output load network for the PA . . . . . . . . . . . . . . . . . . . . 85 5.24 Synthesized drain load impedances as a function of frequency with ideal lumped elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.25 Power amplifier performance for the synthesized ideal lumped elements . . . . 87 5.26 Drain-source voltage waveforms at different frequencies for the synthesized ideal lumped elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.27 Final PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.28 Drain load impedances for final layout with Murata components . . . . . . . . 89 5.29 Post-layout simulation results of switch-mode operation over broad frequency range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.30 Drive signal waveforms tuning by gate bias voltages of NMOS and PMOS of inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.31 Effects of variations of duty-cycle on the performance of switch-mode . . . . . 92 5.32 DC static gate-source bias voltage as a function of VBN and VBP . . . . . . . . . 93 5.33 Post-layout simulation results of linear-mode operation at 0.7GHz. . . . . . . . 93 5.34 Post-layout simulation results of linear-mode operation at 0.8GHz. . . . . . . . 94 5.35 Post-layout simulation results of linear-mode operation at 0.9GHz. . . . . . . . 94 5.36 Post-layout simulation results of linear-mode operation at 1.0GHz. . . . . . . . 95 5.37 Post-layout simulation results of linear-mode operation at 1dB compression point 95 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Photograph of implemented broadband Class-E power amplifier . . . . . . . . Block diagram of the measurement setup for broadband Class-E power amplifier Comparison of simulated and measured performance of the proposed broadband Class-E PA as a function of frequency: (a) output power, (b) power gain, (c) drain efficiency, (d) power added efficiency. . . . . . . . . . . . . . . . . . . . Broadband measurement of dynamic inverter gate bias of Class-E PA: (a) output power, (b) power gain, (c) drain efficiency, (d) power added efficiency. . . . . . Measured RF input power sweep at 0.9GHz with inverter gate bias as a parameter: (a) output power, (b) power gain, (c) drain efficiency, (d) power added efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Broadband measurement of dynamic supply voltage for ED-NMOS: (a) output power, (b) drain efficiency, (c) power added efficiency. . . . . . . . . . . . . . Measured output power as a function of VDD2 at 900MHz with VDD1 as a parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency against output power for the supply modulation shown in Fig.6.7: (a) drain efficiency vs.Pout, (b) PAE vs. Pout. . . . . . . . . . . . . . . . . . . . . 97 98 99 101 102 103 104 104 x 6.9 Measured drain efficiency and PAE with optimum supplies of ED-NMOS and Inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Measured drain efficiency and PAE versus output power for the optimum supply voltages of ED-NMOS and Inverter at: (a) 0.5GHz, (b) 0.6GHz, (c) 0.7GHz, (d) 0.8GHz, (e) 1.0GHz, and (f) 1.1GHz. . . . . . . . . . . . . . . . . . . . . . . 6.11 Measured IMD3 with VBN=VBP as a parameter at 0.9GHz . . . . . . . . . . 6.12 Measured IMD3, drain efficiency and PAE versus output power at: (a) 0.5GHz, (b) 0.6GHz, (c) 0.7GHz, (d) 0.8GHz, (e) 0.9GHz, (f) 1.0GHz, (g) 1.1GHz, and (h) 1.2GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 105 106 107 List of Tables 1.1 Summary of published broadband Class-E PAs . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Input parameters for analytical model . . . . . . . . . . . . . . . . . . . . . . Results of analytical model and ADS based upon the parameters in Table3.1 . . Component Values at 1GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . Harmonic impedances for maximum output power and infinite dc-feed inductance Effects of loaded quality factor Q0 on the bandwidth . . . . . . . . . . . . . . Effects of dc-feed inductance on the bandwidth . . . . . . . . . . . . . . . . . Effects of duty-cycle on the bandwidth . . . . . . . . . . . . . . . . . . . . . . 34 34 35 39 48 49 50 4.1 Extracted small-signal model parameters of extended drain NMOS transistor in CMOS 65nm technology with W=3840 µm, L=0.28 µm, Vgs =0V, Vds =1V at 1GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.1 5.2 5.3 5.4 Bondwire equivalent inductance and parasitic resistance and capacitance at 1GHz Specifications for broadband Class-E power amplifier . . . . . . . . . . . . . . Ideal lumped element values for output load network . . . . . . . . . . . . . . Murata lumped element values for output load network . . . . . . . . . . . . . 71 76 85 87 6.1 6.2 Comparison broadband Class-E PAs . . . . . . . . . . . . . . . . . . . . . . . 100 Comparison CMOS Class-E PAs . . . . . . . . . . . . . . . . . . . . . . . . . 100 xi 5 Chapter 1 Introduction 1.1 Motivation In wireless communication systems, power amplifiers (PAs) are considered as key blocks which have a great influence on the power level, efficiency, linearity and cost of the transmitter system. High-efficiency and high-linearity power amplifiers are always of great interest for designers. Unfortunately, efficiency and linearity usually conflict with each other [1][2]. For example, conventional linear PAs such as Class-A, Class-AB, and Class-B PAs have good linearity but low efficiency no matter in terms of peak efficiency or average efficiency at power back-off. On the contrary, the switch-mode PAs like Class-D and Class-E have high efficiency, but they are usually nonlinear in nature. To overcome the conflict, various transmitter architectures with improved average efficiency and intermodulation distortion (IMD) have been proposed. At present, three architectures have already shown attractive results, namely, supply voltage modulationbased methods like envelope tracking (ET), envelope elimination and restoration (EER) and polar modulation, load modulation-based concepts like Doherty, and linear amplification using nonlinear components (LINC)-based concepts like outphasing. For the outphasing concept in [3], mixed-mode operation of Class-B PA was proposed to enhance the average efficiency in power back-off operation. Fig. 1.1 shows the efficiency as a function of normalized output voltage for a pure Class-B amplifier, outphasing amplifier, and a mixed-mode outphasing amplifier. For intermediate and high output power, saturated Class-B mode is used, while for the very low output power normal Class-B operation is employed to improve the efficiency. When the Class-B amplifier delivers the saturated output power, it can be regarded as a switch. Hence, the operation mode of this amplifier alternates between switch-mode and linear-mode in this system. 1 Chapter 1. Introduction 2 Figure 1.1: Mixed-mode outphasing amplifier In addition, the coexistence of various wireless communication standards requires that the user terminal can cover the multi-mode multi-frequency operations. For the systems using amplitudemodulation signals, for instance, wideband code division multiple access (WCDMA), the amplitudes of signals are modulated to carry more information. Linear power amplifiers are needed for these systems. In contrast, the global system for mobile communications (GSM) and general packet radio service (GPRS) systems apply constant amplitude signals [4]. Saturated power amplifiers are employed in these systems to increase the efficiency. Therefore, multi-mode multi-frequency power amplifiers operating as a linear amplifier for amplitude-modulation signals and at the same time as a saturated or switch-mode amplifier for constant amplitude signals are highly desired. These applications motivate us to investigate the hybrid-mode power amplifier which operates as linear-mode or switch-mode PA for different purposes in order to understand the trade-off between the linearity and efficiency. 1.2 Thesis Research Goal To analyze the performance of switch-mode power amplifier, simple switch models were usually used as a starting point to simplify the transistor model [5]. These simple models are helpful, but do not represent the real RF operating conditions due to many assumptions made at the very beginning. Therefore, many of the design trade-offs assumed based upon the simple models are not correct in practice. Furthermore, the simple switch models cannot be used to analyze the linear operation of the power amplifier because of the discontinuity of switch resistance in the models. Therefore, the main objectives in this thesis are Chapter 1. Introduction 3 1. to analyze the properties of Class-E power amplifier operating in switch-mode or linearmode, 2. to design broadband high efficiency CMOS power amplifier. The end product of this thesis will be a hardware that can demonstrate the high efficiency feature over a broad frequency band. 1.3 State of the Art Review To the best of the author’s knowledge, there is little published work on hybrid-mode power amplifier. In [4], a multi-mode Class-AB/F power amplifier was implemented to operate for both IS-95A CDMA and PCS 1900 GSM signals. The circuit topology is based upon that of the Class-F amplifier. The mode of operation is set by the base bias. An intermediate fundamental load is selected to achieve both the Class-AB and Class-F operations. However, the topology of Class-F amplifier is quite complex to implement. In [6], a dual-mode (CDMA/AMPS) power amplifier was implemented by using SiGe/Si HBT process. Some simulation and measurement results were given with very simple design approach. It seems that no work has been published on a comprehensive analysis of hybrid-mode power amplifier based on Class-E topology. It is worth investigating how the load impedances and gate bias voltage affect the linearity and efficiency. In this thesis, broadband Class-E power amplifier is also a very important subject. Recent works have demonstrated a high efficiency (more than 70%) Class-E power amplifier in broad frequency range (more than 20%). Many researchers have applied the reactance compensation technique to design the broadband Class-E amplifier. In [7], a drain efficiency of 74% at 8W operating power and power flatness of 0.7dB were achieved across bandwidth of 135 to 175 MHz with a supply voltage of 7.2V by using the conventional output load network. A low loaded quality factor was used to realize the broadband application. In fact, the load impedance used in this paper is one special case of many solutions, which corresponds to maximum output power (q = 1.412) [5]. In [8], a double reactance compensation load network was designed to provide a wider bandwidth. The simulation results show that an octave-band (100-200MHz) power amplifier, with 1dB output power flatness and drain efficiency of about 70% can be achieved. Jager applied this technique to design multi-band and multi-mode handset power amplifiers for DCS1800, PCS1900, CDMA2000, and WCDMA [9]. By using InGaP/GaAs HBT technology, a Class-E power amplifier with gain of 22.5dB, output power more than 30dBm and high power added efficiency (PAE> 50%) was obtained from 1.6GHz to more than 2GHz. Chapter 1. Introduction 4 In [10], Everard proposed a new topology placing an inductor in parallel with the shunt capacitor to present the constant load angle over a broad bandwidth. A 35% bandwidth with 60% drain efficiency over the band 130MHz to 180MHz was achieved. In [11], Lie compared and discussed the effects of high breakdown and high-fT SiGe transistors on the Class-E power amplifier. It shows that the output power of the high-fT PA at higher frequencies is 1-1.5dB larger than that of high-breakdown PA. The frequency responses of PAE and gain of the high-fT PA from 500MHz to 1200MHz are much flatter than that of high-breakdown PA. However, the peak PAE of high-breakdown PA is 4% higher than that of high-fT PA. In [12], a third-order Butterworth bandpass filter was applied to design broadband Class-E power amplifier from 600MHz to 1000MHz. The optimum load was obtained by using the load/sourcepull simulation. By using GaN HEMT transistor, more than 33W output power with drain efficiency of 66% or better was obtained over all the band. In [13], a cascode Class-E power amplifier has been introduced to allow a higher supply voltage without enhancing the device stress. To obtain a broad frequency range of operation, a relatively low quality factor has been used both in the driver and PA output network. The measured results show that a PAE of more than 60% over the 1.4-2GHz was achieved. In [14], Qin employed a broadband Class-E power amplifier by using a low cost PHEMT device. A 5% improvement in PAE was found for open circuit termination of 2nd, 3rd and 4th harmonics, as compared to using 50 ohm load. With the conventional Class-E output load network, a bandwidth of 34.8% was achieved from 1.52GHz to 2.16GHz with more than 50% PAE. The peak PAE of 72.1% was obtained at 1.95 GHz. The variation of PAE in the band is about 20%. In [15], a compact broadband Class-E power amplifier was implemented by using GaN HEMT transistor for base stations. It shows that the 2nd harmonic input tuning can improve drain efficiency by 8%. Good broadband performance is observed from 2.0GHz to 2.5GHz with drain efficiency of more than 74% and PAE > 71%. Table 1.1 summarizes the state-of-the-art in terms of flatness of output power, drain efficiency, power added efficiency and output power in radio frequencies band. The topologies of output load network used in these papers are shown in Fig. 1.2. 1.4 Thesis Organization This thesis is divided into two major parts: theory and implementations. Chapter 1. Introduction 5 Table 1.1: Summary of published broadband Class-E PAs Ref./Year BW ∆B ∆Pout Pout η PAE PAEPK (GHz) (%) (dB) (dBm) (%) (%) (%) [8] 2001 0.1-0.2 66.7 < 1.0 > 40 > 70 N.A. [11] 2006 0.5-1.2 82.3 < 3.0 > 17.2 N.A. [12] 2009 0.6-1.0 50 < 1.7 > 45.2 > 66 [13] 2005 1.4-2.0 35.3 < 1.0 > 22 N.A. > 60 [14] 2004 1.52-2.16 34.8 < 2.0 > 20 N.A. > 50 [9] 2003 1.6-2.0 22.2 < 1.0 > 30 N.A. > 50 [15] 2009 2.0-2.5 22.2 < 2.5 > 38 > 74 > 71 L1 Cds RON L Technology Topology N.A. LDMOS Fig.1.2(b) > 50 70 SiGe Fig.1.2(a) > 61.9 80.6 GaN Fig.1.2(d) 67 CMOS Fig.1.2(a) 72.1 PHEMT Fig.1.2(a) 55 InGaP/GaAs Fig.1.2(c) 74 GaN Fig.1.2(a) C1 L1 Cds RL RON ROFF Cds L2 RL (b) L1 L C1 L2 C2 Cds RL RON ROFF C2 L ROFF (a) RON C1 CM1 LM3 LS1 LM1 LM2 LS3 CS3 LP2 CP2 50 ohm ROFF (c) (d) Figure 1.2: Topologies of output load network for broadband Class-E power amplifiers • Chapter 2 aims to give a general overview of power amplifiers. It will introduce some important definitions that characterize a power amplifier. Then, a brief description of classification of RF power amplifiers is given. • Chapter 3 presents the comprehensive analytical derivation of general Class-E model. This analytical model takes into account the non-ideal switch resistance, finite dc-feed inductance, finite loaded quality factor, and arbitrary duty-cycle. The model combines all possible operation modes of Class-E power amplifier together: optimum and suboptimum operation. From the analytical solution, the required load impedance will be found. The influence of the load impedance on the efficiency, power-output capability and drain voltage and current waveforms will be discussed. In addition, the broadband characteristics of conventional Class-E output load network are investigated with the loaded quality factor, dc-feed inductance and duty-cycle as parameters. • Chapter 4 builds up a purely linear transistor model to link the input drive signal and transistor behavior. The effects of a non-ideal drive signal (i.e. square wave with 10% rise and fall times, sinusoidal wave) on the switch-mode operation are investigated with the Chapter 1. Introduction 6 dc-feed inductance as a parameter. Using this linear model, the effects of gate DC bias voltage on the 1dB compression point and efficiency of linear operation are analyzed. • Chapter 5 analyzes the switching and linear operation of a real transistor (extended drain NMOS). The effects of finite dc-feed inductance and gate bias voltage on the linearity are discussed. In addition, a systematic design approach for broadband Class-E power amplifier will be presented, and the post-layout simulation for the proposed broadband Class-E power amplifier will be shown here. • Chapter 6 presents the measurement setup and measurement results of proposed broadband Class-E power amplifier. The effects of dynamic supply modulation on the power added efficiency are verified. • Chapter 7 concludes the thesis by giving some suggestions on the future work. Chapter 2 Background This chapter presents the main fundamental concepts of RF power amplifiers. First, some key parameters of an RF power amplifier are defined, as they will frequently be used in the following chapters. Then, an overview of different power amplifier classes of operation is described. 2.1 Parameters of Power Amplifiers Power amplifiers are key elements to build a wireless communication system. They are used to amplify the signal being transmitted so that it can be received and decoded. The main performance parameters for a power amplifier are the output power that it can deliver, power gain, efficiency, and linearity [2][16][17][18][19]. 2.1.1 Output Power Consider the basic circuit of Fig.2.1, the output power is defined as the power delivered by the power amplifier and flowing into the load RL . VDD i dd L i out CB i ds Pin Input Network + + vds vgs - - Output load network + RL vout - Figure 2.1: Block diagram of power amplifier 7 Chapter 2. Background 8 The instantaneous output power is defined as pout (t) = vout (t) · iout (t). (2.1) The total or average output power Pout is defined as Pout,tot 1 = T Z T/2 pout (τ) dτ. (2.2) −T/2 In most cases, only the power at the fundamental frequency is desired and the harmonics power is suppressed to very low level. Thus, it is more meaningful to define a fundamental average output power, Pout, f0 . Assuming the fundamental output voltage is a sine wave with operation frequency f0 and amplitude of V0 , the fundamental average output power is defined as Pout, f0 V02 . = 2RL (2.3) The amplitude V0 can be obtained from the Fourier Series expansion of vout (t). In the following text, the general term output power, denoted as Pout , will be used to indicate the average output power at the fundamental frequency. 2.1.2 Power Gain To drive the power amplifier, a certain amount of RF input power at operation frequency f0 is needed. The power gain at operating frequency is defined as G P = 10log10 ( 2.1.3 Pout ). Pin (2.4) Efficiency A power amplifier is used to convert DC power from power source into RF power. Efficiency is a measure of how much of the DC power source is usefully applied to the amplifier’s output load. The DC power consumption PDC is defined as PDC = VDD · IDD . (2.5) where IDD is the dc component of Fourier Series expansion of idd (t). The drain or collector efficiency η is defined as Chapter 2. Background 9 η= Pout . PDC (2.6) To account for the power gain of the power amplifier, the Power Added Efficiency (PAE) is a more practical measure and it is defined as Pout − Pin PDC 1 = η(1 − ) GP PAE = (2.7) If the power gain is sufficiently high, the PAE defined in Eq.2.7 becomes equal to the drain efficiency. 2.1.4 Power-Output Capability The power-output capability c p is useful for comparing different types of amplifiers, and is defined as the output power produced when the device has a peak drain or collector voltage of 1 volt and a peak drain or collector current of 1 ampere. Assuming the maximum drain voltage in Fig.2.1 is VDS M and the maximum drain current is IDS M , the power-output capability is given by cp = 2.1.5 Pout . VDS M IDS M (2.8) Linearity In the communication systems (W-CDMA, WiMAX, W-LAN), the transmitted signals have varying envelopes. In order to amplify these signals, the power amplifiers must have sufficient amplitude linearity. The third-order intercept point (IP3), adjacent channel power ratio (ACPR), 1dB compression point, and harmonics suppression are various means of quantifying linearity of power amplifiers. The 1dB compression point (P1dB) of a power amplifier indicates the output power level that causes the gain to drop by 1dB from its small signal value. The 1dB compression point of the amplifier with a third-order nonlinearity is illustrated in Fig.2.2. The third-order intercept point (IP3) is the point where the third-order term as extrapolated from small-signal conditions crosses the extrapolated power of the fundamental. ACPR is defined as the ratio of power in a bandwidth Chapter 2. Background 10 Output power (dBm) OIP3 P1dB 1dB 1: 1 Fundamental 3 :1 Input power (dBm) IIP3 3rd-order distortion Figure 2.2: 3rd-order intercept point and 1dB compression point definitions. away from the main signal (the distortion product) to the power in a bandwidth within the main signal. 2.2 Power Amplifier Classification For the power amplifier shown in Fig.2.1, the MOS transistor can be operated [20] • as a dependent-current source; • as a switch. When a MOSFET is operated as a dependent-current source, the transistor must be operated in the active region or the saturation region. The drain-to-source voltage Vds must be larger than the overdrive voltage Vgs − VT H , where VT H is the transistor threshold voltage determined by the characteristics of the active device. The drain current Ids and the drain-to-source voltage Vds are determined by the gate-to-source voltage Vgs and the transistor biasing point. The magnitudes of Ids and Vds are nearly proportional to the magnitude of Vgs . The transistor produces an amplified replica of the input voltage or current waveform, and provides an accurate reproduction of both the envelope and the phase of the input signal. Therefore, this type of operation is suitable for linear power amplifier which is required to amplify amplitude modulated signals. When a MOSFET is operated as a switch, the transistor is operated in the triode region or linear region when the transistor is conducted and in the cutoff region when the transistor is shut down. To maintain the MOSFET in the triode region or linear region, the drain-to-source voltage Vds is less than the overdrive voltage Vgs − VT H . When the transistor is operated as a switch, the Chapter 2. Background 11 VDD i dd L i out CB i ds Pin Input Network + + vds vgs - - + C0 L0 RL vout - Figure 2.3: Linear power amplifier schematic. magnitude of Ids and Vds are independent of the magnitude of Vgs . The transistor output is represented as a non-ideal single-pole single throw switch: the ON-resistance may be non-zero, the OFF-resistance may be non-infinite, and the turn-on and turn-off switching times may be non-zero. As the switch is cyclically operated at the desired operation frequency, DC energy from the power supply is converted to RF energy at the switching frequency and harmonics. 2.2.1 Linear Power Amplifier For linear power amplifier, the MOSFET is operated as a dependent-current source. The classification of this type operation is based on the conduction angle of the drain current. Fig.2.3 shows the classical linear power amplifier topology. The optimum resistive load RL is in parallel with the harmonic trap (C0 and L0 ) which is used to remove the unwanted harmonic components. The dc-feed inductor is usually an RF choke, and capacitor C B is used for ac coupling. The DC gate bias voltage Vgs determines the conduction angle of the drain current. If the maximum linear input range is VGS M , the gate bias voltage Vgs = (VGS M + VT H )/2 corresponds to Class-A mode where the conduction angle of drain current is 360◦ . For Class-A mode, the gate-source voltage is always larger than the transistor threshold voltage so that the drain current is always greater than zero. When the transistor is biased at Vgs = VT H corresponding to Class-B mode, the drain current conducts only in half of one period, and is zero for the rest of time. Thus the conduction angle of drain current is 180◦ for Class-B mode. When the transistor is biased between (VGS M + VT H )/2 and VT H , the conduction angle is between 180◦ and 360◦ . This corresponds to Class-AB mode. For Class-C mode, the transistor is biased below VT H . The conduction angle is less than 180◦ . Fig.2.4 shows the Vgs and Ids waveforms of Class-A, B, AB, and C. The linear power amplifiers have been comprehensively illustrated in many literatures. Here the important conclusions will be described. From Class-A mode to Class-B mode, the conduction angle of drain current is reduced. The overlap of drain current and drain voltage is also reduced. This results in the increase in efficiency. For Class-A with optimum load, maximum efficiency of 50% can be achieved, while Chapter 2. Background 12 (a) (b) (c) (d) Figure 2.4: Waveforms of the gate-to-source voltage Vgs , and drain current Ids of (a) Class A, (b) Class B, (c) Class AB, (d) Class C. Chapter 2. Background 13 VDD IL IS L3 L + CB + C3 + Pin VDS - C0 L0 VGS RL vo - Figure 2.5: Class-F power amplifier maximum efficiency of 78.5% can be achieved for Class-B. The maximum output power for Class-A and Class-B is the same, but if the conduction angle is continuously reduced, the output power will decrease. In addition, as the conduction angle decreases, the harmonic content of the output signal increases. Class-AB represents a compromise between efficiency and linearity. Class-F is a special type of power amplifier. Class-F power amplifier has a load network which resonates at one or more harmonic frequencies in addition to the fundamental frequency[19]. The addition of harmonics to the fundamental shapes the drain voltage to become an approximate square wave rather than sine wave with a consequent improvement in both efficiency and output power. Fig. 2.5 shows the configuration of a Class-F amplifier with a third harmonic resonator. The transistor is biased at Class-B mode, thus the output current is a half sine wave. The resonator L3 and C3 resonates at 3 f0 , where f0 is the fundamental frequency. Therefore the third harmonic component is presented at the drain terminal which in turn leads to a rectangular voltage waveform across the drain-to-source. The product of the rectangular drain voltage and half sine wave drain current is the power losses of the transistor. Since the power losses are minimum due to the shapes of the drain current and drain voltage, the efficiency is relatively high. The theoretical efficiency of a Class-F with third-harmonic resonator is 88.4%. The major advantage of Class-F PAs is given by the low peak voltage and rms current, that is very beneficial from the device stress point of view. However, although Class-F PAs feature a 100% efficiency in the ideal case, Class-F power amplifier requires the complex output networks to provide open and short circuits at the harmonic frequencies. Consequently, it is generally used in fixed-frequency applications at UHF and microwave frequencies. Chapter 2. Background 14 VDD M1 C0 L0 + M2 Vds RL Figure 2.6: Class-D power amplifier 2.2.2 Switching Power Amplifier Switch-mode operation (Classes D, E, and F) of power amplifiers achieves high efficiency by utilizing the power transistors as switches rather than linear amplifiers. Class-D is an attractive power amplifier in low frequency. The schematic of a Class-D amplifier is shown in Fig.2.6. When M1 is turned on, M2 is turned off and vice versa. The output voltage across M2 alternates between the supply and ground that forms a square wave with a 50% duty cycle. The output load network L0 and C0 is tuned to the fundamental frequency to select the wanted component. The theoretical efficienct of Class-D is 100% because there is no voltage across the switch when conducting and no current through them when off. No power dissipates on the switches and hence all the power is supplied to the load. However, charging and discharging of each drain capacitances once per RF cycle causes a Class-D power amplifier to become less efficient as frequency increases. Consequently, the use of Class-D is generally limited to low frequencies. Class E power amplifier is a high-efficient amplifier used for RF applications. The basic circuit of a Class E amplifier is shown in Fig.2.7. The main idea of the Class E RF power amplifier is that the transistor turns on as a switch at zero voltage, resulting in zero switching loss and high efficiency. In fact, the parasitic capacitance of the switch can become part of C1 . In other words, the parasitic drain-source capacitance can become part of the amplifier circuit, which is a huge advantage, especially in CMOS. The combination of the dc-feed inductor L and the L-C-R series-resonant circuit acts as a current source whose current is IL − IR . When the switch is closed, the current IL − IR flows through the switch. When the switch is opened, the current IL − IR flows through the capacitor C1 , producing the voltage across the shunt capacitor C1 and the switch. Therefore, the shunt capacitor C1 shapes the voltage across the switch. For the Chapter 2. Background 15 VDD IL L Lo Co Lx IS + VDS - + IC IR C1 RL VGS + vo - Figure 2.7: Class-E power amplifier nominal or optimum operation, the zero voltage switching and zero slop switching conditions must be satisfied simultaneously: Vds (T ) = 0 dVds (t) = 0 dt t=T (2.9) (2.10) Class-E power amplifier has two main advantages: a) soft switching which reduces the losses, and b) simple circuit topology compared to other switch-mode PA classes. However, Class-E power amplifier also has disadvantages: the drain voltage has a high peak value due to charging the large output capacitance. But the sub-optimum mode can be applied to reduce the peak drain voltage at the cost of drop in efficiency. To maintain high efficiency, using a high voltage breakdown device is a good option to design the Class-E power amplifier. In summary, the gate bias voltage, input drive signal, and the output load network determines the class of operation of the power amplifier. For a given power amplifier, it can operate in any of the classical operating modes. For a small RF input signal, the amplifier works in Class-A, AB, B or C depending on the gate bias voltage. The efficiency can be improved by biasing the device near the threshold voltage but at the expense of higher harmonics. An alternative way to increase efficiency is to increase the input RF power so that the transistor works as a switch. But this leads to a non-linear amplifier in nature. Chapter 3 Switch-Mode Class-E Power Amplifier Analytical Modeling Since Sokal [21] published the literature on high-efficiency Class-E switch-mode tuned power amplifier, many analytical studies of this circuit have appeared. Early analyses assumed an ideal switch, an RF-choke in dc-feed network, an infinite loaded quality factor, and 50% switch dutycycle. The effects of switch resistance [22][23][24][25], finite dc-feed inductance [22][26][27], finite loaded quality factor [22][26][28], and arbitrary switch duty-cycle [23][24][28] on the output power and efficiency were investigated later. However, none of the abovementioned techniques include all aspects of the Class-E circuits in one analysis. Recently a new analytical modeling method for Class-E PAs was presented by M. Acar [5][29][30][31] and D.A.C. Cortés[32]. This method is based upon design equations, that make it possible to design a Class-E PA by only specifying the supply voltage, frequency, process and output power of the PA. In the analysis, the switch resistance, finite dc-feed inductance, finite loaded quality factor, and arbitrary switch duty-cycle can be all taken into account. In this chapter, a general model covering optimum Class-E mode [33] and sub-optimum modes (variable voltage [29] and variable slope [30]) will be developed based on this new method. This general model combines all the Acar’s and Cortés’ work and also expands by the bandwidth characteristic of conventional Class-E topology. Furthermore, it will show the required load impedances at fundamental and harmonic frequencies. Based upon this model, the effects of the variations of load impedances on the performance of switch-mode Class-E power amplifier will be given. 3.1 Analytical Derivation of Class-E Power Amplifier Model In this section, the detailed mathematical derivation of the Class-E power amplifier with infinite and finite loaded quality factors is presented. 17 Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 18 VDD VDD IL(t) L Lo C o X L Lo C o VC(t) I S(t) C I R(t) IC (t) RL RON (a) C RL ROFF (b) Figure 3.1: Class-E amplifier. (a)Basic circuit. (b)Equivalent circuit. 3.1.1 Circuit Description and Assumptions The general Class-E PA is given in Fig. 3.1. It consists of an active device operated as a switch at the switching frequency f0 , a series R-L-C circuit, a dc-feed inductor L, and a shunt capacitor C, which may be partly or wholly made up of the parasitic shunt capacitance of the device. The combination of L0 and C0 forms a harmonic filter that is tuned to the switching frequency of the amplifier. The value of the load resistance RL will mainly determine the output power level. The shunt capacitor C, dc-feed inductor L and excess reactance X will mainly determine the operation mode of Class-E amplifier. The analytical derivation of the equations considers the following assumptions[5]: 1. The real power dissipation in the circuit only occurs on switch resistances (RON and ROFF ) and load resistance RL . 2. The loaded quality factor Q0 of the series resonant circuit (L0 and C0 ) is high enough in order for the output current IR to be sinusoidal at the switching frequency. 3. In Fig. 3.2 the switching action of the active device is instantaneous. The switch is closed in the time interval 0 ≤ t < d · π/ω, whose resistance is RON . In the time interval d · π/ω ≤ t < 2π/ω the switch is opened whose resistance is ROFF . Note that the value of d determines the switch duty-cycle. For instance, d = 1 corresponds to conventional 50% switch duty-cycle. Analyses of the sub-optimum operation, Variable-Slope (Class-EVS ) and Variable-Voltage (ClassEVV ) Class-E amplifiers, are presented in [29] and [30]. In these literatures, it has been shown that the variable-slope Class-E operation of finite dc-feed inductance allows using significantly larger switch size while the variable-voltage Class-E operation can obtain lower peak drain voltage feature. To analyze sub-optimum operation and conventional operation simultaneously, the Class-E conditions become Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling Vc(t) Is(t) Vc(t) Is(t) 19 kωVDD αVDD Switch−ON 0 0 Switch−OFF dπ/ω 2π/ω Figure 3.2: General drain voltage and current waveforms VC ( 2π ) = αVDD ω dVC (t) = ωVDD k dt t=2π/ω (3.1) (3.2) where αVDD is the voltage of VC (t) at the moment the switch is closed; ωVDD k is the slope of VC (t) at the moment the switch is closed. For conventional Class-E operation, α = 0 and k = 0. For Variable-Voltage operation (Class-EVV ), α , 0 and k = 0. For Variable-Slope operation (Class-EVS ), k , 0 and α = 0. For α , 0 or k , 0, it is also known as the sub-optimum operation [33]. α and k are real values that can be selected freely and therefore give degrees of freedom in the design Class-E PA. The mathematical approach and the equations used to obtain the results given in this thesis are presented in following two sections. In Section 3.1.2 the equations of Class-E amplifier with infinite loaded quality factor will be derived 1 . For the case of finite loaded quality factor, the equations will be given in Section 3.1.3. 3.1.2 Derivation of Class-E Amplifier Equations with Infinite Loaded Quality Factor Since the loaded quality factor of the output series resonant circuit (L0 and C0 ) is assumed to be infinite, the output current IR is sinusoidal. 1 Section3.1.2 refers to the work in [5][32]. Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling IR (t) = IR sin(ωt + φ) 20 (3.3) In the time interval 0 ≤ t < d · π/ω, the switch is closed. Applying the Kirchhoff’s current law (KCL) at the switch, we can get IS on (t) = ILon (t) + IR (t) − ICon (t), (3.4) where IS on (t) = ILon (t) = 1 L Z VCon (t) RON (3.5) t 0 (VDD − VCon (τ)) dτ ICon (t) = C dVCon (t) . dt (3.6) (3.7) Substituting Eqs.3.3, 3.5 - 3.7 into Eq.3.4 and taking derivative we get d2 VCon (t) 1 dVCon (t) VDD − VCon (t) ωIR − − cos(ωt + φ) = 0. + 2 RON C dt LC C dt (3.8) In the time interval d · π/ω ≤ t < 2π/ω, the switch is opened. The current IL (t) flowing through the dc-feeding inductor L can be written as 1 ILo f f (t) = L Z t dπ/ω (VDD − VCo f f (τ)) dτ. (3.9) The current IS (t) flowing through the switch is IS o f f (t) = VCo f f (t) . ROFF (3.10) The current IC (t) flowing through the capacitor C is ICo f f (t) = C dVCo f f (t) . dt (3.11) Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 21 Substituting Eqs.3.3, 3.9 - 3.11 into Eq.3.4 and taking derivative we can get the differential equation when the switch is opened d2 VCo f f (t) 1 dVCo f f (t) VDD − VCo f f (t) ωIR + − − cos(ωt + φ) = 0. 2 ROFF C dt LC C dt (3.12) The two differential equations 3.8 and 3.12 describe the Class-E amplifier in terms of independent component values. To relate these components, new parameters are defined: mon = ωRON C (3.13) mo f f = ωROFF C (3.14) q= 1 √ ω LC (3.15) p= ωLIR . VDD (3.16) With the parameters defined in 3.13 to 3.16 the differential equations 3.8 and 3.12 can be rewritten as: ω dVCon (t) d2 VCon (t) − q2 ω2 (VDD − VCon (t)) − pq2 ω2 VDD cos(ωt + φ) = 0 + 2 mon dt dt (3.17) d2 VCo f f (t) ω dVCo f f (t) − q2 ω2 (VDD − VCo f f (t)) − pq2 ω2 VDD cos(ωt + φ) = 0. (3.18) + 2 m dt dt of f The equations of 3.17 and 3.18 are linear, nonhomogeneous, second-order differential equations. The their general solutions are given by: VCon (t) = Con1 e1/2 √ −1+ 1−4 q2 mon 2 ω t √ 1+ 1−4 q2 mon 2 ω t mon + Con2 e−1/2 + VDD + 2 2 VDD pq mon (mon q − 1 cos (ω t + φ) + sin (ω t + φ)) 1 + q4 − 2 q2 + 1 mon 2 mon (3.19) Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling VCo f f (t) = Coff1 e1/2 √ −1+ 1−4 q2 moff 2 ω t VDD pq2 moff √ 1+ 1−4 q2 moff 2 ω t moff + Coff2 e−1/2 + VDD + (moff q2 − 1 cos (ω t + φ) + sin (ω t + φ)) 1 + q4 − 2 q2 + 1 moff 2 moff 22 (3.20) As can be seen in 3.19 and 3.20 for each solution there are two unknown constants Con1, Con2 or Co f f 1, Co f f 2. These constants can be solved by using boundary conditions. When these constants are solved, the Class-E model will be described without the explicit component values. The properties of the Class-E amplifier (i.e. drain efficiency, output power, waveforms, ects) will be obtained without specifying any component value. This is one of advantages of this analytical modeling. The coefficients Con1 and Con2 in Eq.3.19 can be solved from the continuity of the capacitor charge and inductor flux at t = 0, C · VCon (t)|t=0 = C · VCo f f (t)t=2π/ω (3.21) L · ILon (t)|t=0 = L · ILo f f (t)t=2π/ω (3.22) Substituting the Class-E condition 3.1 into capacitor C charge continuity equation 3.21 yields VCon (t)|t=0 = αVDD (3.23) The inductor L flux continuity equation 3.22 can be simplified by substituting the equations 3.3 - 3.7, 3.10 - 3.11, and Class-E conditions 3.1 - 3.2 into the equation. It yields αVDD ω αVDD ω dVCon (t) = ωVDD k + − dt mo f f mon t=0 (3.24) By solving the above two equations, given by 3.23 and 3.24, the coefficients Con1 and Con2 can be found in terms of q, d, α, k, mon , mo f f , VDD , ω, p, and φ. Therefore, the expression of switch voltage VCon (t) in 3.19 can be also described by these parameters. Similarly,the coefficients Co f f 1 and Co f f 2 in Eq.3.20 can be solved from the Class-E conditions at t = 2π/ω, VCo f f ( 2π ) = αVDD ω (3.25) Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling dVCo f f (t) = ωVDD k. dt t=2π/ω 23 (3.26) Hence, the coefficients Co f f 1 and Co f f 2 can be found in terms of q, d, α, k, mon , mo f f , ω, VDD , p, and φ. The expression of switch voltage VCo f f (t) in Eq.3.20 can be also described by these parameters. So far, the switch voltages, VCon (t) and VCo f f (t), have been determined in terms of q, d, α, k, mon , mo f f , ω, VDD , p, and φ. The supply voltage VDD , the operating angular frequency ω , the technology-frequency related parameters mon and mo f f are assumed to be known a priori. The duty-cycle d, the variable-voltage parameter α, the variable-slope parameter k, and the normalized resonant frequency q have the physical meanings and could be set for the specific behavior. The initial phase φ and the parameter p are intermediate variables, and will be expressed as a function of the other parameters by using the continuity of the capacitor charge and inductor flux at t = dπ/ω, C · VCon (t)|t=dπ/ω = C · VCo f f (t)t=dπ/ω (3.27) L · ILon (t)|t=dπ/ω = L · ILo f f (t)t=dπ/ω . (3.28) All calculations of above equations are done by MAPLE. The detailed codes is presented in Appendix. To this point, the obtained analytical solutions for switch voltages are only related to the parameters of q, d, α, k, mon , mo f f , ω, and VDD . Infinite solutions are existing due to the freedom in the values of dc-feed inductor, the switch duty-cycle, the variable-voltage and variable-slope. For every real value of these parameters there is a solution for switch voltage. The analytical solution and the circuit component values of Class-E model are related by the design set K [5]. The elements of design set K are defined as: ωL RL = ωCRL POUT RL = 2 VDD X = RL KL = (3.29) KC (3.30) KP KX (3.31) (3.32) Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 24 The expression of KL can be derived by using the principle of power conservation, POUT + P switch = PDC , (3.33) where POUT is the output power delivered to the load RL ; P switch is the power loss in the switch; PDC is the power from the DC-supply. The output power POUT is equivalent to POUT = IR2 RL . 2 (3.34) The power loss in the switch P switch is equivalent to P switch ω = ( 2π Z dπ/ω 0 2 (t) VCon dt + RON Z 2π/ω dπ/ω 2 VCo f f (t) ROFF dt). (3.35) The DC-supply power PDC is equivalent to PDC = VDD I0 Z dπ/ω Z 2π/ω VCo f f (t) ω VCon (t) dt + dt). = VDD ( 2π 0 RON ROFF dπ/ω (3.36) (3.37) From the Eqs.3.34 - 3.37 the KL can be expressed as KL = = = ωL RL 2 p2 VDD 2ωLPOUT 2 p2 VDD 2ωL(PDC − P switch ) = ω( R dπ/ω 0 2 q2 π p2 VDD R 2π/ω 2 (t) VCon (t)VDD −VCon dt + dπ/ω mon 2 VCo f f (t)VDD −VCo (t) ff mo f f . (3.38) dt) The KC and KP can be expressed as function of KL . This is, KC = ωCRL = KP = 1 q2 K (3.39) L p2 POUT RL = 2 VDD 2KL2 (3.40) Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 25 The KX can be found by using the two fundamental quadrature Fourier components of VC (t) VR = VX = 1 ( π Z dπ/ω 1 ( π Z dπ/ω VCon (t) sin(ωt + φ) dt + 0 Z VCon (t) cos(ωt + φ) dt + 0 2π/ω dπ/ω Z 2π/ω VCo f f (t) sin(ωt + φ) dt) (3.41) VCo f f (t) cos(ωt + φ) dt) (3.42) dπ/ω KX = VX . VR (3.43) The drain efficiency η can be expressed as η = 1− = 1− P switch PDC R dπ/ω 2 (t) VCon mon 0 R dπ/ω V (t)V Con DD mon 0 dt + dt + 2 VCo f f (t) dt dπ/ω mo f f R 2π/ω VCo f f (t)VDD mo f f dπ/ω R 2π/ω (3.44) dt Since p and φ both are functions of q, d, α, k, mon , mo f f , ω, and VDD , KL , KC , KP , KX and η are functions of q, d, α, k, mon , mo f f , ω, and VDD . 3.1.3 Derivation of Class-E Amplifier Equations with Finite Loaded Quality Factor In Section 3.1.2, the loaded quality factor Q0 of output series resonant circuit L0 and C0 in Fig. 3.1 is assumed to be infinite. Only fundamental current is flowing through the load resistor. In this section, the analytical solution in the previous section is extended to cover the effect of the finite loaded quality factor as well. An extended model has been developed to allow more accurate prediction of effects of the finite loaded quality factor. The purpose of this section is to derive the analytical solutions of the Class-E amplifier at any Q0 . The circuit for this derivation is shown in Fig. 3.3. The excess reactance X in Fig. 3.1 has already been absorbed into L1 or C1 . If the KX solved by the Eq.3.38 is larger than zero, the X shows inductive reactance. It will be absorbed into the inductor L1 . For this case (KX ≥ 0), the loaded quality factor is defined as QL = ωL1 ω(L0 + LX ) = = Q0 + K X RL RL (3.45) Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 26 VDD + L VL(t) IL(t) - VC(t) I S(t) IC (t) RON L1 C1 + VL1(t) + VC1(t) C RL IR(t) + VR (t) - ROFF Figure 3.3: Class-E amplifier with finite loaded quality factor QC = 1 1 = = Q0 ωC1 RL ωC0 RL (3.46) where Q0 is a finite loaded quality factor of L0 or C0 . If the KX is smaller than zero, the X shows capacitive reactance. It will be absorbed into the capacitor C1 . For this case (KX < 0), the loaded quality factor is ωL1 ωL0 = = Q0 RL RL (3.47) 1 1 = = Q0 − K X ωC1 RL ω(C0 + C X )RL (3.48) QL = QC = Applying the Kirchhoff’s voltage law (KVL) at the switch, we can get VDD = VL (t) + VC (t) = VL (t) + (VL1 (t) + VC1 (t) + VR (t)). (3.49) Applying the KCL at the switch, we can get IL (t) = IS (t) + IC (t) + IR (t). (3.50) In the following derivation, the currents and voltages will all be expressed in terms of VC1 (t) in order to solve the Eqs.3.49 and 3.50. The current IR (t) flowing through the capacitor C1 is equal to IR (t) = dVC1 (t) dQC1 (t) = C1 . dt dt (3.51) Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 27 The voltage VL1 (t) across the output inductor L1 is equal to VL1 (t) = L1 d2 VC1 (t) dIR (t) = L1 C 1 . dt dt2 (3.52) The voltage VR (t) across the output resistor RL is equal to VR (t) = IR (t)RL = C1 RL dVC1 (t) . dt (3.53) Therefore the switch voltage VC (t) can be expressed as the summation of VL1 (t), VC1 and VR (t), VC (t) = VL1 (t) + VC1 (t) + VR (t) d2 VC1 (t) dVC1 (t) + VC1 (t) + C1 RL = L1 C 1 . 2 dt dt (3.54) The current IC (t) passing through the capacitor C can be found by taking derivative of VC (t) in Eq.3.54, dVC (t) dt d3 VC1 (t) dVC1 (t) d2 VC1 (t) = CL1C1 + C . + CC R 1 L dt dt3 dt2 IC (t) = C (3.55) The current IS (t) flowing through the switch resistance2 RS IS (t) = = VC (t) RS dVC1 (t) 1 d2 VC1 (t) + VC1 (t) + C1 RL (L1C1 ). 2 RS dt dt (3.56) Summation of IR (t), IC (t) and IS (t) will result in 2 We use RS to replace the RON or ROFF in derivation at the beginning. For different time interval, the RS will be replaced by corresponding switch resistance. Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling IL (t) = IR (t) + IC (t) + IS (t) d3 VC1 (t) L1C1 + CC1 RL RS d2 VC1 (t) ) = CL1C1 + ( RS dt3 dt2 C1 RL dVC1 (t) VC1 (t) + (C + C1 + ) + . RS dt RS 28 (3.57) Therefore the voltage VL (t) across dc-feed inductor L can be expressed as, VL (t) = L dIL (t) dt d4 VC1 (t) LL1C1 + LCC1 RL RS d3 VC1 (t) ) + ( RS dt4 dt3 LC1 RL d2 VC1 (t) L dVC1 (t) ) . + (LC + LC1 + + 2 RS R dt dt S = LCL1C1 (3.58) Substituting Eqs.3.52-3.54 and Eq.3.58 into Eq.3.49, we can get a linear, nonhomogeneous, forth-order differential equation. That is, d4 VC1 (t) LL1C1 + LCC1 RL RS d3 VC1 (t) ) + ( + RS dt4 dt3 d2 VC1 (t) RC1 L + LC + LC1 + L1C1 ) ( + RS dt2 L dVC1 (t) ) + VC1 (t) − VDD = 0 (RC1 + RS dt LCL1C1 (3.59) Eq.3.59 only contains one node voltage variable VC1 (t). Once the solution of VC1 (t) is obtained, all other voltages and currents will be known. To solve the equation, the parameters defined in Eqs.3.13 - 3.15, Eqs.3.29 - 3.32, and Eqs.3.45 - 3.46 will be used again. For the readers’ convenience, we re-write the definitions. Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 1 √ ω LC = ωRON C q = mon mo f f KL KC KP KX QL QC = ωROFF C ωL = RL = ωCRL POUT RL = 2 VDD X = RL ωL1 = RL 1 = ωC1 RL 29 (3.60) (3.61) (3.62) (3.63) (3.64) (3.65) (3.66) (3.67) (3.68) The following two equations will also be used in the derivation: RON RL ROFF RL = = mon KC mo f f KC (3.69) (3.70) In the time interval 0 ≤ t < d · π/ω, the switch is closed. The switch resistance RS in Eq.3.59 corresponds to RON . Substituting the above equations into Eq.3.59 and re-arranging the equation results in, d3 VC1on (t) 1 QL 1 QL 1 d4 VC1on (t) ) + ( + ) + QC q2 ω4 QC q2 ω3 mon QC q2 ω3 dt4 dt3 1 1 QL d2 VC1on (t) 1 + + + ) + ( QC q2 ω2 mon q2 ω2 QC q2 ω2 KC QC ω2 dt2 dVC1on (t) 1 1 ( ) + 2 + VC1on (t) − VDD = 0 QC ω q ωmon dt ( (3.71) Similarly, in the time interval d · π/ω ≤ t < 2π/ω the switch resistance RS corresponds to ROFF . Eq.3.59 can be re-written as, Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 30 4 d3 VC1o f f (t) 1 QL 1 QL 1 d VC1o f f (t) ) +( + ) + ( QC q2 ω4 QC q2 ω3 mo f f QC q2 ω3 dt4 dt3 2 1 1 QL d VC1o f f (t) 1 + + + ) + QC q2 ω2 mo f f q2 ω2 QC q2 ω2 KC QC ω2 dt2 dVC1o f f (t) 1 1 ( ) + 2 + VC1o f f (t) − VDD = 0 QC ω q ωmo f f dt ( (3.72) Here we use VC1on (t) and VC1o f f (t) to denote the different time intervals. To make the derivation clear and simple, we will define new symbols to replace the coefficients of above two differential equations. They are sa1 = sb1 = sc1 = sd1 = se1 = QL 1 QC q2 ω4 QL 1 1 + QC q2 ω3 mon QC q2 ω3 1 1 QL 1 + 2 2+ + 2 2 2 2 QC q ω mon q ω QC q ω KC QC ω2 1 1 + 2 QC ω q ωmon 1 (3.73) (3.74) (3.75) (3.76) (3.77) s f1 = −VDD QL 1 sa2 = QC q2 ω4 1 QL 1 + sb2 = QC q2 ω3 mo f f QC q2 ω3 1 1 1 QL sc2 = + 2 2+ + 2 2 2 2 QC q ω mo f f q ω QC q ω KC QC ω2 1 1 + sd2 = QC ω q2 ωmo f f se2 = 1 (3.78) s f2 = −VDD (3.84) (3.79) (3.80) (3.81) (3.82) (3.83) Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 31 then the Eqs.3.71 and 3.72 become d4 VC1on (t) d3 VC1on (t) d2 VC1on (t) + sb + sc + 1 1 dt4 dt3 dt2 dVC1on (t) + se1 VC1on (t) + s f1 = 0 sd1 dt d4 VC1o f f (t) d3 VC1o f f (t) d2 VC1o f f (t) sa2 + sb + sc + 2 2 dt4 dt3 dt2 dVC1o f f (t) + se2 VC1o f f (t) + s f 2 = 0 sd2 dt sa1 (3.85) (3.86) The general solutions of Eqs.3.85 and 3.86 are VC1on (t) = a1 eCa1 t + b1 eCb1 t + c1 eCc1 t + d1 eCd1 t − s f1 /se1 (3.87) VC1o f f (t) = a2 eCa2 t + b2 eCb2 t + c2 eCc2 t + d2 eCd2 t − s f2 /se2 (3.88) where the Ca1 , Cb1 , Cc1 , Cd1 are the roots of sa1 x4 + sb1 x3 + sc1 x2 + sd1 x + se1 = 0 while the Ca2 , Cb2 , Cc2 , Cd2 are the roots of sa2 x4 + sb2 x3 + sc2 x2 + sd2 x + se2 = 0. To find out the expressions of eight unknowns coefficients (i.e. a1 , b1 , c1 , d1 , a2 , b2 , c2 , d2 ), the continuity of capacitor charge and inductor flux will be applied to capacitors C, C1 and inductor L, L1 . CVC (t)|t=0 = CVC (t)|t=2π/ω CVC (t)|t=dπ/ω− = CVC (t)|t=dπ/ω+ C1 VC1 (t)|t=0 = C1 VC1 (t)|t=2π/ω C1 VC1 (t)|t=dπ/ω− = C1 VC1 (t)|t=dπ/ω+ LVL (t)|t=0 = LVL (t)|t=dπ/ω− = L1 VL1 (t)|t=0 = L1 VL1 (t)|t=dπ/ω− = (3.89) (3.90) (3.91) (3.92) LVL (t)|t=2π/ω (3.93) LVL (t)|t=dπ/ω+ (3.94) L1 VL1 (t)|t=2π/ω (3.95) L1 VL1 (t)|t=dπ/ω+ (3.96) By solving the above eight boundary conditions, the coefficients in Eqs.3.87 and 3.88 can be expressed in terms of parameters defined in Eqs.3.60-3.68. Therefore the capacitor voltage VC1 (t) is obtained and given in the terms of q, d, α, k, mon , mo f f , VDD , ω, Q0 . The rest of voltages and currents are also determined. The analytical expressions for the voltages and currents in Fig. 3.3 are very complex but can be computed numerically. The purpose of the derivations in Sections 3.1.2 and 3.1.3 is to present Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling Class-E amplifier design equations with infinite loaded quality factor 32 Class-E amplifier design equations with finite loaded quality factor Class-E circuit Class-E circuit 2nd-order differential equations with circuit elements 4th-order differential equations with circuit elements Infinite Q0 Elements Relations q,p,mon,moff KC, KL , KX Elements Relations q,mon,moff ,Q0 Differential equations with parameters q, p, mon, moff , d, f Differential equations with parameters q, mon, moff , d, f, KC, KX, KL , Q0 Solve differential equations Solve differential equations Satisfy Class-E conditions and continuity of inductor flux and capacitor charge Satisfy Class-E conditions and continuity of inductor flux and capacitor charge Calculate Design set K Calculate the real efficiency and drain voltage and current waveforms Calculate circuit elements Figure 3.4: Analytical design flowchart of Class-E power amplifier at a single frequency. the approach we used to model the Class-E amplifier. All those equations can be calculated by MAPLE. Fig.3.4 summarizes the analytical approach of systematical design of Class-E power amplifier. The starting point is to express the ideal Class-E circuit (infinite loaded quality factor) as time-domain 2nd-order differential equations in terms of circuit elements, then the higher level differential equations will be generated based upon the elements relations. After solving the 2ndorder differential equations by applying the boundary conditions and Class-E circuit conditions, the design set K can be obtained. If the actual loaded quality factor is given, the more realistic solutions of the Class-E amplifier can be found by solving 4th-order differential equations for the given quality factor and obtained design set K. For the obtained design set K, the relations between the circuit elements and design set K can be expressed in Fig.3.5. Each circuit element is placed in the corners of a triangle and the related design set element is shown in the inner part of the triangle [5]. In the triangles for KC , KL , KX two elements are shared by the other triangles,whereas in KP only one element RL is shared. Therefore, either VDD or POUT must be known in order to be able to make a uniquely defined Class-E PA design. Fig.3.6 shows two procedures to calculate the circuit elements. For a given Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 33 Figure 3.5: Relations between the elements of the design set K (a) (b) Figure 3.6: Class-E amplifier components design:(a) for a given device, (b) for a given supply voltage device, the device output capacitance C is fixed so that the load resistance RL can be found from KC , then the supply voltage will be known via KP . The dc-feed inductor L and excess reactance X can be obtained from KL and KX . It is similar to the case of given supply voltage. 3.2 Analysis and Discussion of Class-E Power Amplifier Model In Sections 3.1.2 and 3.1.3, the analytical approach is applied to model the Class-E power amplifiers. In this section, the validity of the analytical approach will be presented by an example. After that, the effects of variations of drain load impedances on the performance of Class-E power amplifiers will be discussed comprehensively. Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 34 Table 3.1: Input parameters for analytical model ω=1 q = 1.412 α=0 mon = 0.01 d=1 k=0 mo f f = 1000 VDD = 1 Q0 = 2 Table 3.2: Results of analytical model and ADS based upon the parameters in Table3.1 KL = 0.725 η|Q0 =∞ = 95.43% KC = 0.692 η|ADS (Q0 =∞) = 95.40% KP = 1.27 η|Q0 =2 = 91.94% q=1.412, d=0.5, mon=0.01, moff=1000, α=0, k=0 4 Anal.(Q0=inf.) 3 q=1.412, d=0.5, mon=0.01, moff=1000, α=0, k=0 3 Anal.(Q0=inf.) Anal.(Q0=2) Anal.(Q0=2) 2 ADS(Q =inf.) ADS(Q =2) 0 Is(t)/IDD Vds(t)/VDD 0 2 1 ADS(Q =inf.) 0 ADS(Q =2) 0 1 0 0 −1 0 KX = 0.0186 η|ADS (Q0 =2) = 91.80% 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T (a) Drain voltage Vds(t) 1 −1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T 1 (b) Drain current Is(t) Figure 3.7: Class-E amplifier waveforms for analytical approach and ADS simulation 3.2.1 Accuracy Comparison between Analytical Approach and ADS Solution In this section, an example is presented to compare the accuracy of the analytical approach with commercial circuit simulator (ADS). For analytical design equations, we assume that the amplifier operates at maximum output power mode3 (q = 1.412) with zero switching voltage (α = 0) and zero switching slope (k = 0). To simplify the computation, we choose VDD = 1, 50% duty-cycle (d = 1), ω = 1, and device technology parameters mon = 0.01 and mo f f = 1000. By substituting these input parameters summarized in Table 3.1 into the design equations shown in Section 3.1.2, we can get the ideal drain efficiency, design set K, and ideal drain current and voltage waveforms. Substituting the obtained design set K and finite quality factor Q0 = 2 into the design equations shown in Section 3.1.3, the real drain efficiency and drain voltage and current waveforms can be obtained. Table3.2 shows the design set K, and drain efficiency calculated by analytical approach for Q0 = 2 and Q0 = ∞. The drain current and voltage waveforms are shown in Fig.3.7. To verify the correctness of the analytical solutions, a Class-E circuit shown in Fig. 3.8 is built up in the ADS. Assuming the operating frequency f0 is 1GHz, the supply voltage VDD is 1V, and 3 In [5], the author has proved that the maximum output power is obtained when q = 1.412 for given R and VDD . Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling V_DC SRC1 Vdc=Vdd V I_Probe IL V I_Probe IR L L1 L=L1 H SwitchV_Model SWITCHVM1 R1=Ron Ohm V1=0.2 V R2=Roff Ohm V2=0.8 V AllParams= VtPulse SRC2 Vlow=0 V Vhigh=1 V t Delay=(50/Frq) sec Edge=linear Rise=(0*T2) sec Fall=0 nsec Width=(dutyc*T2-0*T2) sec Period=T2 sec 35 Vswitch vr I_Probe IS ctrl SwitchV SWITCHV1 Model=SWITCHVM1 R1=Roff Ohm V1=0.2 V R2=Ron Ohm V2=0.8 V V I_Probe IC L L2 L=L2 H C C3 C=C2 F R R1 R=RL Ohm C C2 C=C1 F Figure 3.8: Class-E model in ADS Table 3.3: Component Values at 1GHz Q0 = 2 Q0 = 100 KL RL L = ω = 0.1154nH KC = 110.14pF C = ωR L on = 0.0145Ohm RON = mωC mo f f ROFF = ωC = 1.445kOhm C1 = ωR1L Q0 = 79.577pF C1 = ωR1L Q0 = 1.59pF X )RL X )RL = 0.3213nH L1 = (Q0 +K = 15.9nH L1 = (Q0 +K ω ω the load resistor RL is 1Ω, the component values can be calculated based upon the given design set K and Eqs.3.29-3.32 and Eqs.3.45-3.46 (since KX > 0). Table3.3 shows the component values for Q0 = 2 and Q0 = 100. We can regard Q0 = 100 as infinite loaded quality factor. To make a fair comparison the rise and fall times of the drive signal in the ADS model is set to zero. By substituting the component values into the ADS model, we get the drain efficiency of 91.8% for Q0 = 2 and 95.4% for Q0 = ∞. All the results are summarized in Table. 3.2. One can observe that the results of analytical solution and ADS solution are almost the same. The drain voltage and current waveforms obtained from ADS simulation are also shown in Fig. 3.7. One can find that a very good agreement in the waveforms are observed between ADS and the analytical model. The results presented above indicate the analytical design solutions give reasonable accuracy. In addition, it is apparent that for a low Q0 value the efficiency decreases and peak drain voltage increases. This example also tells us that the quality factor Q0 affects the performance of Class-E amplifier. 3.2.2 Effects of Drain Load Impedances on Class-E Amplifier Since the sufficiently good accuracy, the general Class-E model derived in Sections 3.1.2 and 3.1.3 can be used to evaluate the performance of the Class-E power amplifier in a specified Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 1.8 0.9 1.6 0.8 1.4 0.7 1.2 0.6 C 1 KP 2 K 1 0.5 0.8 0.4 0.6 0.3 0.4 0.2 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 36 0 0 2 (a) KP 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 (b) KP d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 2 20 18 1 16 14 0 KX KL 12 10 −1 8 −2 6 4 −3 2 0 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 (c) KL −4 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 (d) KX Figure 3.9: Elements of the design set KP , KC , KL , KX as a function of q situation. In the following discussion, normalization to VDD = 1, RL = 1, design angular frequency ω0 = 1, and technology parameters mon = 0.005 and mo f f = 1000 have been used for convenience. In [34] and [35], a technique, which is based upon a finite number of harmonics, for analysis of Class-E power amplifiers is developed. The analysis shows the number of harmonics will determine the maximum achievable efficiency. The fundamental and harmonic impedances for ”optimum” Class-E PAs with infinite dc-feed inductance are also given in [34]. However the Class-E PAs with infinite dc-feed inductance might not be an ”optimum” PA. Fig.3.9 and 3.10 illustrate the drain efficiency, power-output capability and design set K as a function of q (varying the dc-feed inductance from infinite to finite values). It is observed that the power-output capability has a peak value when q = 1.412. The same conclusion can be also obtained from the design set KP which achieves a maximum value when q = 1.412. The efficiency remains constant for different dc-feed inductances. Therefore, for a given VDD and RL , the optimum Class-E operation is obtained when q = 1.412. Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling d=0.5, mon=0.005, moff=1000, α=0, k=0, Q =20 37 d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 0 1 0.12 Power−output capability 0.9 Drain efficiency 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.08 0.06 0.04 0.02 0.1 0 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 0 0 2 (a) Drain efficiency 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 (b) Power-output capability Figure 3.10: Drain efficiency and power-output capability as a function of q VDD Z1 =R1 +jX1 Z2 =jX2 L L1 C 1 Z3 =jX3 ... C RL Figure 3.11: Drain load impedances of Class-E PAs To enable the design of Class-E amplifiers a closer examination of the output load network is required. The drain load impedances Zk shown in Fig.3.11 consists of shunt capacitance, dc-feed inductance and output load network . The admittance of load network as a function of frequency is given as: Yk (ω)|ω=kω0 = jωC + 1 1 + . jωL RL + jωL1 + 1/ jωC1 (3.97) where k is a real number. When k is an integer, Yk describes the admittance at fundamental and harmonic frequencies. Substituting Eqs. 3.63, 3.64, 3.66-3.68 into Eq.3.97 and normalizing to RL we can get: Yk (ω)RL |ω=kω0 = ( ωω0 )2 Q12 C (1 − ( ωω0 )2 QQCL )2 + ( ωω0 Q1C )2 +j (1 +j ω 1 ω 2 QL ω0 QC (1 − ( ω0 ) QC ) − ( ωω0 )2 QQCL )2 + ( ωω0 Q1C )2 ( ωω0 )2 q12 − 1 KL ( ωω0 )2 (3.98) Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling d=0.5, mon=0.005, moff=1000, α=0, k=0, Q =20 d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 0 2 2 1.8 1.8 1.6 1.6 1.4 1.4 1 L −2 1 L 0.6 0.4 0.4 0.2 0.2 0.2 0.4 0.6 1 0.8 0.6 0 0 X /R 1 X /R → 0.8 0.8 −1 X3/RL → 1 q 1.2 1.4 1.6 1.8 −2 X2/RL L 1 −1 1.2 1 0 L 1.2 R /R 0 X3/RL ← R /R 38 ← X2/RL −3 −3 −4 0 2 −4 −5 0 0.2 0.4 0.6 0.8 1 q (a) 1.2 1.4 1.6 1.8 −5 2 (b) d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 2 40 1.8 38 1.6 36 34 32 30 0.8 θ1 → 0.6 28 26 0.4 24 0.2 22 0 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 1 ← |Z1|/RL θ (Degree) L 1 |Z |/R 1.2 1 1.4 20 2 (c) Figure 3.12: Equivalent drain load impedance as a function of q: (a)fundamental impedance in terms of resistance and reactance, (b)second and third harmonics impedance in terms of reactance, (c)fundamental impedance in terms of magnitude and phase then taking inverse of the admittance we can get the normalized impedance, Zk (ω) 1 = . RL Yk (ω)RL (3.99) The required drain load impedances Zk at fundamental, second and third harmonic frequencies are shown in Fig.3.12. The magnitude |Z1 | of drain load impedance at fundamental frequency reaches its minimum value when q = 1.412 which results in the maximum output power. For readers’ convenience the drain load impedances for maximum output power operation and for infinite dc-feed inductance are summarized in Table 3.4. In Table3.4, the required drain load impedances Zk at fundamental and harmonic frequencies are given. The effects of variations of drain load impedances at fundamental, second and third harmonic frequencies on drain efficiency, KP , and peak drain-source voltage and peak drain current are given in Figs.3.13-3.24. When investigating the effects of load phase angle θk (/magnitude Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 39 Table 3.4: Harmonic impedances for maximum output power and infinite dc-feed inductance k 1 2 3 4 5 6 7 8 9 10 Zk = Rk + jXk for RL = 1 q = 1.412 0.6831 + j0.4653 − j1.4571 − j0.6253 − j0.4170 − j0.3173 − j0.2576 − j0.2174 − j0.1884 − j0.1663 − j0.1490 Zk = |Zk |exp( jθk ) for RL = 1 q = 1.412 0.8265∠34.26 1.4571∠ − 90 0.6253∠ − 90 0.4170∠ − 90 0.3173∠ − 90 0.2576∠ − 90 0.2174∠ − 90 0.1884∠ − 90 0.1663∠ − 90 0.1490∠ − 90 Zk = Rk + jXk for RL = 1 q=0 1.5287 + j1.1254 − j2.7538 − j1.8338 − j1.3749 − j1.0998 − j0.9164 − j0.7855 − j0.6873 − j0.6109 − j0.5498 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 1 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 2 6 5 Vdspeak/VDD Drain efficiency KP Ispeak/IDD 0 0.4 −1 0.2 −2 0 −90 −60 −30 0 30 Load phase angle θ1 (Degree) 60 −3 90 5 4 4 3 3 2 2 −90 (a) −60 −30 0 30 Load phase angle θ1 (Degree) 60 Ispeak/IDD 0.6 Vdspeak/VDD 1 KP(dB) 0.8 Drain efficiency Zk = |Zk |exp( jθk ) for RL = 1 q=0 1.8983∠36.36 2.7538∠ − 90 1.8338∠ − 90 1.3749∠ − 90 1.0998∠ − 90 0.9164∠ − 90 0.7855∠ − 90 0.6873∠ − 90 0.6109∠ − 90 0.5498∠ − 90 1 90 (b) Figure 3.13: Effects of load phase angle θ1 on: (a) drain efficiency and KP , (b) maximum drain-source voltage and current q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 4 Vds(t) / VDD 3 2 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 5 θ1=−30° θ1=0° θ1=0° 3 ° θ1=35 θ1=60° 1 −1 −1 (a) 1 θ1=60° 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T θ1=35° 2 0 −2 0 θ1=−30° 4 Is(t) / IDD 5 −2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T (b) Figure 3.14: Waveforms as a function of load phase angle θ1 : (a) drain-source voltage, (b) switch current 1 Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 1 6 Drain efficiency K P 6 5 5 4 4 3 3 0.4 2 3 0.2 Ispeak/IDD 0.6 KP(dB) 4 Vdspeak/VDD 5 0.8 Drain efficiency 40 2 Vdspeak/VDD 1 Ispeak/IDD 0 0 1 2 3 4 0 5 2 0 |Z1|/RL 1 2 3 4 1 5 |Z1|/RL (a) (b) Figure 3.15: Effects of magnitude |Z1 | on: (a) drain efficiency and KP , (b) maximum drainsource voltage and current q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 6 5 4 |Z1|/RL=0.1 |Z1|/RL=1 3 |Z1|/RL=1 4 |Z1|/RL=3 2 |Z1|/RL=3 3 |Z1|/RL=5 1 |Z1|/RL=5 Vds(t) / VDD Is(t) / IDD |Z1|/RL=0.1 5 2 1 0 −1 −2 0 −3 −1 −4 −2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T (a) 1 −5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T 1 (b) Figure 3.16: Waveforms as a function of |Z1 |: (a) drain-source voltage, (b) switch current |Zk | of drain load impedance) at certain harmonics, the magnitudes |Zk | of drain load impedance (/load phase angles θk ) at this frequency and other frequencies are fixed at their required values. The effects of load phase angle θ1 of drain load impedance Z1 at fundamental frequency f0 on the performance of maximum output power operation are shown in Fig. 3.13, and the effects on drain-source voltage and current waveforms are shown in Fig. 3.14. The drain efficiency remains constant for load phase angles between about 10◦ and 40◦ . The KP keeps constant for load phase angles between about 0◦ and 35◦ . The load phase angles θ1 for constant efficiency and for constant output power are only overlapped in a narrow range (10◦ 35◦ ). Out of this range the efficiency and output power decrease very fast. The effect of variation can also be seen in the waveforms. For capacitive loading (θ1 < 0◦ ) or larger inductive loading (θ1 > 60◦ ), the drain-source voltage becomes large at the turn-on moment, resulting in low efficiency. We can also find out that the device should have negative current conducting capability when the Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 41 load phase angle θ1 is larger than 60◦ . For a large load phase angle θ1 , the peak drain voltage is beyond 4VDD which might lead to drain-source breakdown. Fig. 3.15 shows the effects of magnitude |Z1 | variation of drain load impedance Z1 at fundamental frequency f0 . It is apparent that comparing with the variation of θ1 the amplifier is tolerant of variations of |Z1 |, and maintains high efficiency for values between 0.25 and 2. As expected, KP increases with decreasing |Z1 | except for relatively small values of |Z1 |. Peak output power occurs at 0.1, but the corresponding efficiency is low and peak drain voltage is large. Therefore, |Z1 | should be larger than 0.1RL . From Eqs.3.61 and 3.64, one can obtain that: mon ωRON C RON = = . KC ωRLC RL (3.100) For q = 1.412, d=0.5, mon = 0.005, mo f f = 1000, α = 0, and k = 0, one can find KC = 0.6871. Therefore, |Z1 | > 13.7RON . (3.101) The above equation indicates that the magnitude |Z1 | should be at least 14 times larger than the ON-resistance. As the magnitude |Z1 | becomes very small, the ON-resistance of the switch draws more and more current than the load current causing low efficiency. For small values of |Z1 |, they give high conduction losses and low efficiencies. As the magnitude |Z1 | becomes very large, output power tends to become constant. The peak drain-source voltage Vds peak decreases as the magnitude |Z1 | increases, while peak switch current Is peak increases as |Z1 | increases. The effect of magnitude |Z1 | variation can also been found in the waveforms shown in Fig. 3.16. For |Z1 | = 0.1, the drain-source voltage at the turn-on moment is very large resulting in the large switch loss. For large values of |Z1 |, the waveforms are almost similar which indicates that the amplifier is quite tolerant of large magnitude |Z1 |. The effects caused by changes in load phase angle θ2 of drain load impedance Z2 at second harmonic frequency 2 f0 are shown in Fig. 3.17. It is obvious that the efficiency decreases as load phase angle θ2 varies from the pure capacitive loading (θ2 = −90◦ ) to the resistive and capacitive loading (−90◦ < θ2 < 0◦ ) resulting in the power loss at resistive load of second harmonic impedance. The KP keeps constant for capacitive loading (−90◦ ≤ θ2 ≤ 0◦ ) and increases for inductive loading because of second harmonic tuning. The drain-source voltage and drain current waveforms are shown in Fig.3.18. For inductive loading θ2 > 0◦ at 2 f0 , the peak drain-source voltages are larger than 4VDD although the drain-source voltages at turn-on moment are small. Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 42 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 1 3 6 5 Vdspeak/VDD 1 0.4 0 0.2 −1 Vdspeak / VDD 0.6 5 4 4 3 3 2 Ispeak / IDD Ispeak/IDD 2 KP(dB) Drain efficiency 0.8 Drain efficiency KP 0 −90 −60 −30 0 30 Load phase angle θ2 (Degree) −2 90 60 2 −90 −60 −30 0 30 Load phase angle θ2 (Degree) (a) 1 90 60 (b) Figure 3.17: Effects of load phase angle θ2 of second harmonic impedance: (a) drain efficiency and KP , (b) maximum drain-source voltage and current q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 6 θ2=−90° 5 Is(t) / IDD θ2=90° 2 1 θ2=60° θ2=90° 2 1 0 0 −1 −1 −2 0 θ2=0° 3 θ2=60° 3 θ2=−90° 4 θ2=0° 4 Vds(t) / VDD q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T −2 0 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T (a) (b) Figure 3.18: Waveforms as a function of θ2 : (a) drain-source voltage, (b) switch current q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 6 2 5 Vds /V peak Is 0.2 4 3 3 2 DD −1 4 /V 0.4 peak 0 5 Vds 0.6 /I peak DD 1 KP(dB) Drain efficiency 0.8 DD Ispeak/IDD 1 −2 Drain efficiency K P 0 0 1 2 3 4 5 |Z |/R 2 (a) L 6 7 8 9 −3 10 2 0 1 2 3 4 5 6 |Z2|/RL 7 8 9 1 10 (b) Figure 3.19: Effects of magnitude |Z2 | of second harmonic impedance: (a) drain efficiency and KP , (b) maximum drain-source voltage and current 1 Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 5 5 |Z2|/RL=0.1 4 3 |Z2|/RL=1 4 |Z2|/RL=3 3 |Z2|/RL=5 2 Is(t) / IDD Vds(t) / VDD 43 1 −1 −1 −2 0 1 |Z2|/RL=3 |Z2|/RL=5 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T |Z2|/RL=1 2 0 −2 0 |Z2|/RL=0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T (a) 1 (b) Figure 3.20: Waveforms as a function of |Z2 |: (a) drain-source voltage, (b) switch current q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 1 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 2 6 5 Vdspeak/VDD 0 0.4 −1 0.2 Vdspeak / VDD 0.6 5 4 4 3 3 2 Ispeak / IDD Ispeak/IDD 1 KP(dB) Drain efficiency 0.8 −2 Drain efficiency KP 0 −90 −60 −30 0 30 Load phase angle θ3 (Degree) 60 −3 90 2 −90 −60 −30 0 30 Load phase angle θ3 (Degree) (a) 60 1 90 (b) Figure 3.21: Effects of load phase angle θ3 of third harmonic impedance: (a) drain efficiency and KP , (b) maximum drain-source voltage and current Fig. 3.19 illustrates the effects of magnitude |Z2 | variation of drain load impedance Z2 at second harmonic frequency 2 f0 . It is apparent that the amplifier is very tolerant of variations of |Z2 | except for very small values, and maintains high efficiency and constant KP . The peak drainsource voltage for large values of |Z2 | is about 4.2VDD which is not beyond 4VDD too much. The effects of load phase angle θ3 of drain load impedance Z3 at third harmonic frequency 3 f0 are shown in Fig. 3.21. One can observe that the efficiency remains almost constant for capacitive loading (−90◦ ≤ θ3 ≤ 0◦ ), and decreases by 10% for inductive loading. The change of KP for all the variations of θ3 is less than 1dB. The peak drain-source voltage Vds peak keeps constant and is less than 4VDD for a very wide range of θ3 . In Figs. 3.23 and 3.24, the effects of magnitude |Z3 | variations are shown. It is obvious that the amplifier is almost independent on |Z3 | except for very small values. Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 5 Is(t) / IDD θ3=90° 1 −1 −1 −2 0 1 θ3=90° 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T θ3=30° 2 0 −2 0 θ3=0° 3 θ3=30° 2 θ3=−90° 4 θ3=0° 3 Vds(t) / VDD q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 5 θ3=−90° 4 44 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T (a) 1 (b) Figure 3.22: Waveforms as a function of θ3 : (a) drain-source voltage, (b) switch current q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 1 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 2 6 5 Vdspeak/VDD 0 0.4 −1 0.2 −2 Vdspeak/VDD 0.6 5 4 4 3 3 2 Ispeak/IDD Ispeak/IDD 1 KP(dB) Drain efficiency 0.8 Drain efficiency KP 0 0 1 2 3 4 5 6 |Z3|/RL 7 8 9 −3 10 2 0 (a) 1 2 3 4 5 6 |Z3|/RL 7 8 9 1 10 (b) Figure 3.23: Effects of magnitude |Z3 | of third harmonic impedance: (a) drain efficiency and KP , (b) maximum drain-source voltage and current q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 5 5 |Z3|/RL=0.1 4 4 |Z3|/RL=3 3 Is(t) / IDD Vds(t) / VDD 3 |Z3|/RL=1 2 1 −1 −1 (a) 1 |Z3|/RL=3 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T |Z3|/RL=1 2 0 −2 0 |Z3|/RL=0.1 −2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T (b) Figure 3.24: Waveforms as a function of |Z3 |: (a) drain-source voltage, (b) switch current 1 Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 45 Several remarks are needed here to understand the significance of these graphs. 1. For a high-efficient Class-E power amplifier, the load phase angle θ1 is the most important design parameter because the efficiency, KP and peak drain-source voltage all are very sensitive to it. The optimum range of load phase angle θ1 for high efficiency, high output power and low peak drain-source voltage operation is between 10◦ and 40◦ . 2. Decreasing magnitude |Z1 | can improve the output power, but magnitude |Z1 | should be at least 14 times larger than the ON-resistance RON . 3. To obtain high efficiency, the ideal impedances at harmonic frequencies should be open conditions. 4. It is apparent that a tune-up procedure must not be based on either drain efficiency or output power. A moderate efficiency and output power with reliable drain voltage would be a better tuning indicator. The methods developed in this section may be applied to any other problem that can be simplified to variations in load phase angle and magnitude. A straightforward example is prediction of performance with frequency variations which will be presented in the next section. This manifests itself as a set of values of θk (ω) and |Zk (ω)| corresponding to the value of frequency. 3.2.3 Broadband Characteristics of Conventional Class-E Output Load Network The usable bandwidth is an important aspect of power amplifier performance. In [36] Raab briefly analyzed the frequency variations of classical Class-E load network with infinite dcfeed inductance. The drain efficiency and output power are given for different loaded quality factor Q0 . Kumar designed a broadband Class-E PA with the classical load network by using reactance-compensation technique [7]. Actually the load network he used corresponds to the finite dc-feed inductance for q = 1.412. It seems that no work has been published on the comprehensive analysis of conventional Class-E load network across a broad bandwidth. In this section, the effects of loaded quality factor Q0 , finite dc-feed inductance q and duty-cycle d on drain efficiency, output power, peak drain-source voltage and peak drain current will be studied. The analytical design equations derived in Sections 3.1.2 and 3.1.3 aim at the conventional output load network of Class-E PAs shown in Fig.3.1. For a fixed-tuned output load network designed at frequency f0 , which means the design set K is fixed, the frequency variations can be modeled by scaling the frequency parameter ω in Section 3.1.3. By this method, the power amplifier performance as a function of frequency can be investigated. Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 3 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 90 Q0=1 70 Q0=5 θ1 (Degree) 2 |Z1|/RL 80 Q0=2 2.5 46 1.5 1 60 50 40 30 20 0.5 10 Q0=1 Q0=2 Q =5 0 0 0.4 0.6 0.8 1 ω / ω0 1.2 1.4 0 0.4 1.6 0.6 0.8 (a) 1 ω / ω0 1.2 1.4 1.6 (b) Figure 3.25: Fundamental impedance as a function of frequency for different Q0 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 18 Q0=1 16 Q0=1 Q0=2 14 θ2 (Degree) 10 8 6 4 Q0=2 60 Q0=5 12 |Z2|/RL q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 90 Q0=5 30 0 −30 −60 2 0 0.8 1.2 1.6 2 2ω / ω0 2.4 2.8 (a) 3.2 −90 0.8 1.2 1.6 2 2ω / ω0 2.4 2.8 3.2 (b) Figure 3.26: Second harmonic impedance as a function of frequency for different Q0 First the effects of loaded quality factor Q0 is investigated. Figs. 3.25 and 3.26 show the magnitudes and load phase angles of drain load impedance at fundamental and second harmonic frequencies for different loaded quality factor Q0 . The output load network is set for maximum output power (q = 1.412). We can predict the broadband performance based upon the results obtained in the Section3.2.2. The magnitude |Z1 | and load phase angle θ1 is more tolerant of frequency variations for low Q0 values than for high Q0 values. For example, the magnitude |Z1 | and load phase angle θ1 for Q0 = 1 is almost flat from ω = 0.8ω0 to ω = 1.2ω0 . This means it is possible to provide very flat drain efficiency and output power in this band. But the load phase angle θ2 for Q0 = 1 deviates from the required value of −90◦ and increases sharply as the frequency decreases which will result in the drain efficiency drop at low frequency. For Q0 = 5, the load phase angle θ2 is near −90◦ from ω = 0.85ω0 satisfying the required load phase angle at second harmonic frequency. This will show high efficiency in band. However since the change rate of the load phase angle θ1 is fast for Q0 = 5, the output power for Q0 = 5 will decrease sharply between ω = 0.8ω0 and ω = 1.2ω0 . Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 5 0.9 Q0=1 4 Q0=1 0.8 Q0=2 3 Q0=2 0.7 Q0=5 2 Q0=5 0.6 KP(dB) Drain efficiency q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 1 47 0.5 0.4 1 0 −1 0.3 −2 0.2 −3 0.1 −4 0 0.4 0.6 0.8 1 ω / ω0 1.2 1.4 −5 0.4 1.6 0.6 0.8 (a) Drain efficiency 1.2 1.4 1.6 (b) KP q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 22 20 Q0=1 18 Q0=2 16 Q0=5 q=1.412, d=0.5, mon=0.005, moff=1000, α=0, k=0 14 Q0=1 12 Ispeak / IDD Vdspeak / VDD 1 ω / ω0 14 12 10 8 6 10 Q0=2 Q0=5 8 6 4 4 2 0.4 0.6 0.8 1 ω / ω0 1.2 (c) Peak drain voltage 1.4 1.6 2 0.4 0.6 0.8 1 ω / ω0 1.2 1.4 1.6 (d) Peak drain current Figure 3.27: Effects of finite load quality factor on the wideband operation Fig. 3.27 presents the variation of efficiency, KP , peak drain-source voltage, and peak drain current as a function of frequency with Q0 as a parameter, and Table 3.5 summarizes the bandwidth for different criteria. The overlapping frequency range in Table 3.5-3.7 is the frequency range in which the drain efficiency is larger than 80%, and output power flatness is less than 1dB, and peak drain voltage is less than 4VDD . It is apparent that the bandwidth in terms of drain efficiency and output power is wider for low Q0 values than for high Q0 values. The large loaded quality factor Q0 can improve the peak drain efficiency, but reduce the usable bandwidth due to the dramatical variation of load phase angle in the band. The effect of large loaded quality factor is visible at ω = 1.1ω0 and ω = 0.85ω0 where the efficiency is decreasing faster due to load angle θ1 beyond 60◦ for Q0 = 5. These results agree very well with what we predicted based upon Figs.3.25 and 3.26. One must notice that the peak drain-source voltage might be larger than 4VDD even the drain efficiency is larger than 80% at some frequencies. The peak drainsource voltage decreases as the frequency increases. In summary, the bandwidth over which a given efficiency can be obtained is roughly inversely proportional to Q0 for moderate and large values of Q0 [36]. Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 48 Table 3.5: Effects of loaded quality factor Q0 on the bandwidth Frequency range for Frequency range for Frequency range for Overlapping drain efficiency≥ 80% ∆KP ≤ ±0.5dB Vds peak ≤4VDD frequency range Q0 =1 0.92ω0 ≤ ω ≤ 1.58ω0 0.82ω0 ≤ ω ≤ 1.24ω0 Q0 =2 0.82ω0 ≤ ω ≤ 1.46ω0 Q0 =5 0.86ω0 ≤ ω ≤ 1.30ω0 52.8% 56.1% 40.7% ω ≥ 0.96ω0 0.96ω0 ≤ ω ≤ 1.24ω0 0.78ω0 ≤ ω ≤ 1.16ω0 ω ≥ 0.92ω0 0.92ω0 ≤ ω ≤ 1.16ω0 0.96ω0 ≤ ω ≤ 1.08ω0 ω ≥ 0.88ω0 0.96ω0 ≤ ω ≤ 1.08ω0 40.8% 39.2% 11.8% d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=2 11.8% 90 q=0.01 q=1.21 q=1.41 q=1.61 80 2.5 70 θ1 (Degree) 2 |Z1|/RL 23.1% d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=2 3 1.5 1 q=0.01 q=1.21 q=1.41 q=1.61 0.5 0 0.4 25.5% 0.6 0.8 1 ω / ω0 (a) 1.2 1.4 1.6 60 50 40 30 20 10 0 0.4 0.6 0.8 1 ω / ω0 1.2 1.4 1.6 (b) Figure 3.28: Fundamental impedance as a function of frequency for different Q0 The effects of finite dc-feed inductance on the drain load impedance at fundamental frequency are shown in Fig. 3.28. As q increases, the center frequency moves to higher frequency. The variations of load phase angle θ1 and magnitude |Z1 | of finite dc-feed inductance (q = 1.61) is smaller than that of infinite dc-feed inductance (q = 0.01) so that the finite dc-feed inductance can improve the bandwidth in terms of drain efficiency and output power. Fig. 3.29 shows the broadband features of Class-E power amplifier for different dc-feed inductance when Q0 = 2. Table 3.6 summarizes the bandwidth for different q. One can observe that the bandwidth with an efficiency of 80% or better is 42.9% for q = 0.01 while it is 56.1% for q = 1.41. The bandwidth for a 80% drain efficiency is improved by 30.7% via finite dc-feed inductance. The bandwidth of 1dB output power flatness is 29.2% for q = 0.01 while it is 39.2% for q = 1.41. Meanwhile, the KP for q = 1.41 is 3dB larger than that for infinite dc-feed inductance. When the output load network is fixed, the duty-cycle is the only one parameter that the designer can tune with besides the supply voltage. The effects of duty-cycle variation can now be examined. Fig. 3.30 shows how drain efficiency , KP , peak drain-source voltage and peak drain current vary with duty-cycle in a broad frequency band, and Table 3.7 summarizes the bandwidth performance of the amplifier. One can observe that the frequency range for high efficiency shifts to the low frequency band as the duty-cycle increases. The bandwidth for high Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=2 d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=2 1 2 0.9 0 0.7 0.6 KP(dB) Drain efficiency q=0.01 q=1.21 q=1.41 q=1.61 1 0.8 0.5 0.4 0.3 0.1 0 0.4 0.6 0.8 1 ω / ω0 1.2 1.4 −1 −2 −3 q=0.01 q=1.21 q=1.41 q=1.61 0.2 −4 −5 0.4 1.6 0.6 0.8 (a) Drain efficiency 1 ω / ω0 1.2 1.4 1.6 (b) KP d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=2 d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=2 10 8 q=0.01 q=1.21 q=1.41 q=1.61 9 7 6 5 q=0.01 q=1.21 q=1.41 q=1.61 7 Ispeak / IDD 8 Vdspeak / VDD 49 6 5 4 4 3 3 2 0.4 0.6 0.8 1 ω / ω0 1.2 1.4 1.6 (c) Peak drain voltage 2 0.4 0.6 0.8 1 ω / ω0 1.2 1.4 1.6 (d) Peak drain current Figure 3.29: Effects of finite dc-feed inductance on the wideband operation Table 3.6: Effects of dc-feed inductance on the bandwidth q=0.01 Frequency range for Frequency range for Frequency range for Overlapping drain efficiency≥ 80% ∆KP ≤ ±0.5dB Vds peak ≤4VDD frequency range 0.88ω0 ≤ ω ≤ 1.36ω0 0.76ω0 ≤ ω ≤ 1.02ω0 ω ≥ 0.80ω0 0.88ω0 ≤ ω ≤ 1.02ω0 0.72ω0 ≤ ω ≤ 1.38ω0 0.84ω0 ≤ ω ≤ 1.06ω0 ω ≥ 0.70ω0 0.84ω0 ≤ ω ≤ 1.06ω0 0.82ω0 ≤ ω ≤ 1.46ω0 0.78ω0 ≤ ω ≤ 1.16ω0 ω ≥ 0.92ω0 0.92ω0 ≤ ω ≤ 1.16ω0 0.94ω0 ≤ ω ≤ 1.66ω0 1.04ω0 ≤ ω ≤ 1.32ω0 ω ≥ 1.02ω0 1.04ω0 ≤ ω ≤ 1.32ω0 42.9% q=1.21 62.9% q=1.41 56.1% q=1.61 55.4% 29.2% 23.2% 39.2% 23.7% 14.7% 23.2% 23.1% 23.7% Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling q=1.412, mon=0.005, moff=1000, α=0, k=0, Q0=2 q=1.412, mon=0.005, moff=1000, α=0, k=0, Q0=2 1 2 d=0.4 d=0.5 d=0.6 0.9 d=0.4 d=0.5 d=0.6 1 0 0.7 0.6 KP(dB) Drain efficiency 0.8 0.5 0.4 0.3 −1 −2 −3 0.2 −4 0.1 0 0.4 0.6 0.8 1 ω / ω0 1.2 1.4 −5 0.4 1.6 0.6 0.8 (a) Drain efficiency 1 ω / ω0 1.2 1.4 1.6 (b) KP q=1.412, mon=0.005, moff=1000, α=0, k=0, Q0=2 q=1.412, mon=0.005, moff=1000, α=0, k=0, Q0=2 10 8 d=0.4 d=0.5 d=0.6 9 7 6 5 d=0.4 d=0.5 d=0.6 7 Ispeak / IDD 8 Vdspeak / VDD 50 6 5 4 4 3 3 2 0.4 0.6 0.8 1 ω / ω0 1.2 1.4 1.6 2 0.4 0.6 (c) Peak drain voltage 0.8 1 ω / ω0 1.2 1.4 1.6 (d) Peak drain current Figure 3.30: Effects of duty-cycle on the wideband operation Table 3.7: Effects of duty-cycle on the bandwidth Frequency range for drain efficiency≥ 80% d=40% ∆KP ≤ ±0.5dB Vds peak ≤4VDD 0.96ω0 ≤ ω ≤ 1.22ω0 0.82ω0 ≤ ω ≤ 1.46ω0 0.82ω0 ≤ ω ≤ 1.26ω0 56.1% d=60% Frequency range for 0.94ω0 ≤ ω ≤ 1.60ω0 52.0% d=50% Frequency range for 42.3% Overlapping frequency range ω ≥ 0.76ω0 0.96ω0 ≤ ω ≤ 1.22ω0 0.78ω0 ≤ ω ≤ 1.16ω0 ω ≥ 0.92ω0 0.92ω0 ≤ ω ≤ 1.16ω0 0.86ω0 ≤ ω ≤ 1.14ω0 ω ≥ 0.92ω0 0.92ω0 ≤ ω ≤ 1.14ω0 23.9% 39.2% 28.0% 23.9% 23.1% 21.4% efficiency decreases as the duty-cycle increases from 50% to 60%. The usable frequency range for Vds peak ≤ 4VDD is extended to ω/ω0 = 0.76 when small duty-cycle (d = 40%) is applied, although the efficiency is less than 80% in the low frequency band. The device reliability is one of most important factors designers have to take into account. For broadband systems, we need the power amplifiers can have the characteristics of highefficiency, flat output power, low peak drain-source voltage (which is less than drain-source Chapter 3. Switch-Mode Class-E Power Amplifier Analytical Modeling 51 breakdown voltage BVds ) across broad frequency band. From the above results, one can conclude that the conventional Class-E output load network is not a good option which can provide the bandwidth of 40% or more. A broadband methodology must be deployed in order to keep good performance over a broad range of frequencies. In Section 5.2, the output load network for broadband application will be addressed. 3.3 Conclusion This chapter presents an analytical solution in the time domain for the Class-E power amplifiers taking into account the finite dc-feed inductance, non-ideal switch resistance, duty-cycle and finite loaded quality factor. The analysis in this chapter has provided means of determining the performance of a Class-E tuned power amplifier with arbitrary circuit parameters. The accuracy of the developed analytical model shows very good agreement with commercial circuit simulators such as Agilent ADS. A systematic study of the performance of Class-E amplifier upon the drain load impedance has been performed. The simulation shows that the performance of ClassE PA is very sensitive to the load phase angle θ1 . For the maximum output power operation (q = 1.412), the optimum range of θ1 is between 10◦ and 40◦ . Meanwhile, the magnitude |Z1 | should be at least 14 times larger than the device’s ON-resistance. In addition, the performance of conventional Class-E power amplifier in a broad frequency band is given with the loaded quality factor, finite dc-feed inductance, and duty-cycle as parameters. The study shows that the low loaded quality factor Q0 can improve the bandwidth, but the efficiency in-band is lower than that of the PA with high loaded quality factor. The study also indicates that the bandwidth of Class-E PA with finite dc-feed inductance (q = 1.412) is 8% wider than that of the PA with RF choke. It has been demonstrated that the power amplifier with conventional Class-E output load network is difficult to provide the characteristics of high efficiency, flat output power and low peak drain-source voltage over a very wide frequency band (∆B > 40%). So new output matching topologies for wideband class-E operation need to be investigated. Chapter 4 Effects of Drive Signal and Linear Operation of Class-E Power Amplifier In chapter 3, an analytical approach is used to model the Class-E power amplifier. In the model, the transistor is operated as a switch which only has two states: ON or OFF. However, the rise and fall times of drive signal to the Class-E amplifier, in practice, are usually not very sharp at high frequency; consequently, the switch resistance varies to ON-resistance or OFF-resistance gradually but not suddenly. Thus it is necessary to build up a model that can include the imperfections in the drive signal with the behavior of the transistor. Once having this model, the effects of the drive signal on the Class-E amplifier will be obtained. In addition, the performance of the Class-E amplifier operating in linear mode can also be investigated by using this model. Generally a NMOS transistor can be regarded as a voltage-controlled current source shown in Fig.4.1 The drain current can be expressed as [37]: VDD IL A sin ωt + ID Vgs gm Vgs L Vc IR L1 C1 Ic C RL Figure 4.1: Simplified small-signal model of Class-E power amplifier 53 Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier 54 in triode region or linear region (VDS ≤ VGS − VT H ) ID = W µnCox 2 [2(VGS − VT H )VDS − VDS ] L 2 (4.1) in saturation region (VDS > VGS − VT H ) ID = W µnCox 2 [2(VGS − VT H )VDS (sat) − VDS (sat)] L 2 (4.2) where VDS (sat) = VGS − VT H . Similar to the derivation in chapter 3, an equation only containing one unknown variable VC (t) can be found by applying Kirchhoffs current law at the circuit. However, an explicit analytical solution for VC (t) appears difficult because of terms such as VGS (t) = A sin(ωt) in the equation. Then, a more programmable approach based on the numerical computations in Cadence simulator is used to solve the circuit. In this chapter, a numerical model used for analyzing the Class-E amplifier will first be described. The effects of drive signal on the performance of Class-E amplifier will be discussed in Section 4.2. In Section 4.3, the linear operation of Class-E amplifier will be given. 4.1 Numerical Modeling of CMOS Transistor A CMOS transistor model mainly concerns transistor’s I/V relationships as a function of drive signal and device capacitance. For the measured I-V curves, the dependent-current source ID can be modeled via polynomial function for different Vgs : 2 3 + c3 Vds + ··· . IDn |Vgs =Vgsn = c0 + c1 Vds + c2 Vds (4.3) The coefficients cn can be obtained by curve fitting. The accuracy of the fitted curves is dependent on the order of polynomial function. Higher order polynomial function fitting always gives better results. Fig.4.2 shows an example using the 6th-order polynomial functions to fit the measured I-V curves. Good agreement is shown between the measured results and fitted curves. Besides using polynomial functions to fit the measured results, one could create desired I-V curves to model the wanted dependent-current source by defining current function: Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier 2 Measured I−V curves Polynomial fitting curves 1.5 Ids (A) 55 Vgs=2.0V Vgs=1.9V Vgs=1.8V Vgs=1.7V Vgs=1.6V Vgs=1.5V Vgs=1.4V Vgs=1.3V Vgs=1.2V Vgs=1.1V Vgs=1.0V 1 0.5 Vgs=0.9V Vgs=0.8V Vgs=0.7V 0 0 1 2 3 4 Vds (V) 5 6 Figure 4.2: 6th-order polynomial functions fitting measured I-V curves Ids=Vgs(1−exp(−Vds/0.05)) I =V (1−exp(−V /0.05)) gs ds 1 Vgs=1.0V 1 0.9 Vgs=0.9V 0.9 0.8 Vgs=0.8V 0.8 0.7 Vgs=0.7V 0.7 0.6 Vgs=0.6V 0.5 Vgs=0.5V 0.4 Vgs=0.4V 0.3 Vgs=0.3V 0.3 0.2 Vgs=0.2V 0.2 0.1 Vgs=0.1V 0.1 0 0 Vgs=0.0V 0.2 0.4 0.6 0.8 Vds (V) 1 1.2 Ids (A) Ids (A) ds Vds=0.05V Vds=0.1V Vds=0.2V Vds=0.3V 0.6 0.5 0.4 0 −0.2 (a) 0 0.2 0.4 0.6 Vgs (V) 0.8 1 1.2 (b) Figure 4.3: I-V curves created by Eq. 4.4 for gm = 1, VT H = 0V, Imax = 1A, Vk = 0.05V and λ=0 ID = gm (Vgs − VT H )Imax (1 − exp(− Vds ))(1 + λVds ) Vk (4.4) Here the gm , VT H , Imax , Vk and λ are user defined parameters. One can determine when the transistor is turned on beyond VT H , how sensitive the transistor is to Vgs by gm , the maximum drain current that the transistor can conduct by Imax , the channel-length modulation by λ, and the linear resistor by Vk . Fig.4.3 shows created I-V curves for gm = 1, VT H = 0V, Imax = 1A, Vk = 0.05V and λ = 0. The I-V relationships described by Eq.4.3 or 4.4 provide a reasonable model for understanding the ”dc” behavior of CMOS circuits. Moreover, the device capacitances must also be taken into account to predict the ”ac” behavior of the device. In [38], an approach to extract the Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier 56 Figure 4.4: NMOS small-signal equivalent model Table 4.1: Extracted small-signal model parameters of extended drain NMOS transistor in CMOS 65nm technology with W=3840 µm, L=0.28 µm, Vgs =0V, Vds =1V at 1GHz rg = 0.018Ω Cgs = 8.41pF rds = 42.265kΩ (a) S11 and S12 r s = 0.023Ω Cgd = 2.757pF gm = 2.559mS rd = 0.041Ω Cds = 3.244pF τ = −2.49 × 10−10 (b) S22 and S21 Figure 4.5: S-parameters measured by Cadence and modeled S-parameters using extracted model parameters small-signal model parameters of silicon MOSFETs is described. One can obtain the smallsignal model parameters only by S-parameter measurements. Fig.4.4 shows the schematic of the equivalent model used to characterize the small-signal behavior of NMOS transistor. An example is given to extract the small-signal model parameters of extended drain NMOS transistor in CMOS 65nm technology [39]. Table 4.1 shows the extracted parameters. In Fig.4.5, the S-parameters obtained by Cadence and modeled S-parameters using the extracted model parameters are given in Table 4.1 from 0.5 to 1.5 GHz. This demonstrates good accuracy for the technique developed in [38]. Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier 57 Capacitors obtained from extracted smallsignal model parameters or user defined VDD L Cgd Cgs L1 + V gs - gmxVgs rds C1 Cds RL Verilog-A module using equation 4.3 or 4.4 to describe the I-V curves and drain-source resistance Figure 4.6: Numerical model of Class-E power amplifier VDD L L1 + Vgs - C1 Cds=10pF RL Ids=Vgs[1-exp(-Vds/0.05)] Figure 4.7: Simulation model Fig.4.6 presents the methodology one can use to model a CMOS transistor. A Verilog-A module based upon Eq.4.3 or 4.4 is used to describe the ”dc” behavior of the device, and capacitors extracted by [38] or defined by user are used to describe the ”ac” behavior of the device. In the following sections, the I-V curves shown in Fig.4.3 are used to model the DC behavior of the device. For this current source, the ON-resistance RON at knee voltage Vk =0.05V for Vgs =1V is RON = Vk /ID = 0.079Ω. In Chapter 3, all the results are obtained for mon =0.005. For comparison purpose, the same mon is used here. Consequently the corresponding total output capacitance at 1GHz is C = mon /(ωRON ) = 10pF. To simplify the model, the Cgs and Cgd are neglected. Therefore the required drain-source capacitance is 10pF. Fig.4.7 shows the model will be used for investigating the effects of drive signal and linear operation. Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier 58 tr=tf=0 1 tr=tf=0.1T tr=tf=0.2T 0.8 Vgs(t) tr=tf=0.25T Sine wave 0.6 0.4 0.2 VTH=0V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t/T Figure 4.8: Test waveforms of drive signal to gate terminal 4.2 Effects of Drive Signal on Class-E Power Amplifier In this section the effects of drive signal on the performance of Class-E power amplifiers are presented. Fig.4.8 shows five different drive signal waveforms in this experiment: ideal square wave, square wave with rise and fall times1 of 0.1T, square wave with rise and fall times of 0.2T, triangular wave (tr =t f =0.25T), and sinusoidal wave. The duty cycles2 of these drive signals are all 50%. The effects of these drive signals on the drain efficiency, power-output capability, and KP are shown in Fig.4.9, and the effects of drive signals on drain-source voltage and drain current waveforms are shown in Fig.4.10 as a function of q. One can observe that the increase in the rise and fall times leads to the decrease of drain efficiency. However, the drain efficiency is more tolerant of variations of rise and fall times for finite dc-feed inductance than for infinite dc-feed inductance. For example, a 11% drop in drain efficiency can be seen for q = 0.01 (infinite dc-feed inductance) when the rise and fall times increase to 0.25T while only 5% decrease in drain efficiency is found for q = 1.81. The peak power-output capability shifts to a smaller dc-feed inductance (q = 1.61 ) when the drive signal is a non-ideal square wave. However, the maximum value of KP is still at q = 1.41 for different rise and fall times. The peak drain-source voltage decreases as the rise and fall times increase. For q = 0.01, the peak drain-source voltage reduces to 3.3VDD but the drain efficiency also reduces. Like drain efficiency, the output power is also more tolerant to the variations of rise and fall times for finite dc-feed inductance than for infinite dc-feed inductance. 1 The rise time tr refers to the time required for the drive signal to change from threshold voltage to the maximum gate voltage. In reverse, fall time t f is the time required for the drive signal to decrease from the maximum gate voltage to threshold voltage. 2 The duty cycle is defined as the proportion of time during which the gate-source voltage is larger than the threshold voltage VT H . Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier d=0.5, mon=0.005, moff=1000, α=0, k=0, Q =20 d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 0 1 0.12 0.8 t =t =0 r f t =t =0.1T r f t =t =0.2T 0.6 r f t =t =0.25T r 0.1 Power−output capability Drain efficiency 0.9 0.7 0.08 0.06 0.04 f 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 0 0 2 d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 r f 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 4 tr=tf=0 tr=tf=0 tr=tf=0.1T tr=tf=0.1T 3.5 tr=tf=0.2T 3 Sine wave Id Sine wave tr=tf=0.2T tr=tf=0.25T /I peak DD tr=tf=0.25T 3.5 3 0 2.5 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 0 2 (c) Peak drain-source voltage 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 (d) Peak drain current d=0.5, mon=0.005, moff=1000, α=0, k=0, Q =20 0 2 t =t =0 1 r 0 f t =t =0.1T r f t =t =0.2T r f t =t =0.25T KP(dB) Vdspeak/VDD t =t =0.25T (b) Power-output capability 5 4 tr=tf=0.1T Sine wave (a) Drain efficiency 4.5 tr=tf=0 tr=tf=0.2T 0.02 Sine wave 0.5 0 59 −1 r f Sine wave −2 −3 −4 −5 −6 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 (e) KP Figure 4.9: Effects of drive signal on the performance of Class-E power amplifier 2 Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier q=1.61, d=0.5, mon=0.005, moff=1000, α=0, k=0, Q0=20 q=1.61, d=0.5, mon=0.005, moff=1000, α=0, k=0, Q =20 0 4 3 tr=tf=0 t =t =0 r 3 r tr=tf=0.1T 2.5 f tr=tf=0.2T t =t =0.2T f t =t =0.25T r t =t =0.25T 2 f Ids(t)/IDD Vgs(t)/VDD f t =t =0.1T r 2 60 Sine wave 1 r f Sine wave 1.5 1 0 −1 0 0.5 0.2 0.4 0.6 0.8 1 0 0 0.2 0.4 t/T (a) 0.6 0.8 1 t/T (b) Figure 4.10: Drain-source voltage and drain current waveforms as a function of rise and fall time 4.3 Linear Operation of Class-E Power Amplifier In the above sections, the analyses are focused on switch-mode operation of Class-E power amplifier. The drive signals applied to the Class-E amplifier usually swing to the maximum allowed gate-source voltage sharply to avoid power loss at the transistor. However, the process of the amplitude changes in the drive signal is worth investigating. In this case, the drive signal is a sinusoidal wave based on a DC gate bias voltage, and the amplitude of the drive signal reaches the maximum gate-source voltage gradually and not suddenly. The Class-E power amplifier operates here in linear mode. In this section, the effects of gate bias on linear operation of Class-E amplifier is presented. For the linear operation, a sinusoidal wave is applied to the gate of the amplifier. The input signal is based upon a certain DC gate bias voltage. The amplitude increases from a very small value to a large value. For the created I-V curves shown in Fig.4.3, the linear input range is from 0 to 1V. Thus the DC gate bias voltage for Class-A operation is 0.5V, and 0V for Class-B operation. For Class-AB operation, the gate bias voltage can be chosen between 0V and 0.5V. Fig.4.11 shows the output power and drain efficiency as a function of input power for q = 1.41. One can see that the saturation power and corresponding efficiency for Class-A and Class-B biasing are almost the same, but the efficiency for a same output power (less than saturation power) is quite low for Class-A biasing compared with Class-B biasing. For example, when the amplifier delivers 16dBm output power, the drain efficiency for Class-A is only 10%, but 60% for Class-B biasing. One can get the same conclusion from the drain current and voltage waveforms shown in Fig.4.12. For a same input amplitude, the drain current for Class-B biasing only conducts at the first half of one cycle, but the transistor always conducts current for Class-A biasing. Therefore, the overlap between drain voltage and drain current is smaller for Class-B biasing Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier 22 1 20 0.9 20 0.9 18 0.8 18 0.8 16 0.7 16 0.7 14 0.6 14 0.6 12 0.5 12 0.5 10 0.4 10 0.4 8 0.3 8 0.3 6 0.2 4 Output power 0.1 Drain efficiency 2 −25 −20 −15 −10 −5 Input power (dBm) 0 0 5 Output power (dBm) 1 6 0.2 4 Output power 0.1 Drain efficiency 2 −25 −20 −15 −10 −5 Input power (dBm) (a) 0 Drain efficiency Class−B biasing (q=1.41) 22 Drain efficiency Output power (dBm) Class−A biasing (q=1.41) 61 0 5 (b) Figure 4.11: Output power and drain efficiency as a function of input power for linear operation than for Class-A biasing, which improves the drain efficiency. Since the created transistor only conducts current when the input signal is larger than 0V, the efficiency for Class-B biasing is still relatively high at 10dB power back-off. However, for the same output power, the input power of Class-B biasing must be 6dB larger than that of Class-A biasing. Fig.4.13 presents the effects of dc-feed inductance on the performance of Class-E amplifier, which is driven into 1dB compression point for different bias conditions. For comparison purpose, the results of switch-mode operation are shown on the same graphs. One can observe that the drain efficiency and power-output capability have peak values when q = 0. The output 1dB compression point and drain efficiency decrease as q increases. At 1dB compression point, the drain efficiency can be improved by shifting biasing voltage to threshold voltage or Class-B mode. The difference of output 1dB compression point between Class-A and Class-B biasing is about 1dB. These results agree with the classical linear amplifier theory. The effects of gate biasing on drain-source voltage and drain current waveforms are shown in Fig.4.14. The figure corresponds to q = 1.41 at 1dB compression point. It is apparent that the overlap between current through the transistor and voltage across the transistor is smallest when the amplifier is biased at Class-B mode. One can also observe that the peak drain voltage is more than 3VDD at 1dB compression point. It is different from the classical power amplifier theory which claims that the output swing is 2VDD for optimum load condition. This is due to that the Class-E load shapes the drain voltage waveform. 4.4 Conclusion A linear transistor model was created in this chapter by using numerical method in order to analyze the effects of drive signal on the Class-E amplifier and linear operation of Class-E amplifier. In this model, the drain current Ids is a linear function of gate-source voltage Vgs . The Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier Class−B biasing (q=1.41) Class−A biasing (q=1.41) 0.2 0.7 Pin=−20dBm Pin=−15dBm Pin=−10dBm Pin=−20dBm Pin=−15dBm Pin=−10dBm 0.65 0.1 0.6 0.55 Vgs(V) Vgs(V) 62 0.5 0 0.45 −0.1 0.4 0.35 0 0.2 0.4 0.6 0.8 −0.2 0 1 0.2 0.4 (a) Class−A biasing (q=1.41) Class−B biasing (q=1.41) Pin=−20dBm Pin=−15dBm Pin=−10dBm 0.15 Ids(A) Ids(A) Pin=−20dBm Pin=−15dBm Pin=−10dBm 0.5 0.4 0.1 0.05 0.3 0.2 0.4 0.6 0.8 0 0 1 0.2 0.4 t/T 0.8 1 0.8 1 (d) Class−A biasing (q=1.41) Class−B biasing (q=1.41) 3 3 Pin=−20dBm Pin=−15dBm Pin=−10dBm 2.5 Pin=−20dBm Pin=−15dBm Pin=−10dBm 2 Vds(V) 2 Vds(V) 0.6 t/T (c) 1.5 1.5 1 1 0.5 0.5 0 0 1 0.2 0.6 2.5 0.8 (b) 0.7 0.2 0 0.6 t/T t/T 0.2 0.4 0.6 0.8 1 0 0 0.2 0.4 t/T (e) 0.6 t/T (f) Figure 4.12: Voltage and current waveforms of Class-A and B biasing at q = 1.41 Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier 0 mon=0.005, moff=1000, α=0, k=0, Q0=20 Power−output capability @ Pout1dB Drain efficiency @ Pout1dB mon=0.005, moff=1000, α=0, k=0, Q0=20 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Class−A Class−B Class−AB Class−E 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 0.12 0.1 0.08 0.06 0.04 0.02 2 0 0 (a) Drain efficiency mon=0.005, moff=1000, α=0, k=0, Q0=20 1 q 1.2 1.4 1.6 1.8 2 mon=0.005, moff=1000, α=0, k=0, Q0=20 Pout1dB/(V2DD/RL) (dB) Pout1dB(dBm) 0.2 0.4 0.6 0.8 2 20 18 16 12 0 Class−A Class−B Class−AB Class−E (b) Power-output capability 22 14 63 Class−A Class−B Class−AB 0.2 0.4 0.6 0.8 1 q (c) Pout1dB 1.2 1.4 1.6 1.8 2 0 Class−A Class−B Class−AB Class−E −2 −4 −6 −8 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 (d) KP Figure 4.13: Effects of dc-feed inductance for Class-E power amplifier at 1dB compression point with different gate bias voltages transconductance gm and device capacitance Cds are constants which are independent of gatesource Vgs and drain-source voltage Vds . Based upon this transistor model, the effects of rise and fall times of drive signal were discussed. It has been demonstrated that the Class-E power amplifier with finite dc-feed inductance is more tolerant of the variations of drive signal. For the rise and fall times of 25%T , only 5% drop in drain efficiency was found for the PA with finite dc-feed inductance (q = 1.81) while 11% drop for the PA with the RF choke. For the Class-E power amplifier operating in linear mode, the DC gate bias voltage is a key design parameter which determines the efficiency, output 1dB compression point and power gain. The efficiency for Class-B biasing is higher, but the output 1dB compression point and power gain of Class-B biasing are smaller than that of Class-A biasing. The trade-off exists between these parameters. Designers should choose a suitable gate bias voltage to satisfy a given specification. The shortcoming of this model is that it is a purely linear model. The non-linearity of transconductance gm and device capacitances Cgs , Cds , Cgd are not taken into account. Therefore the linearity of the amplifier and intermodulation performance cannot be estimated directly by this model. In Chapter 4. Effects of Drive Signal and Linear Operation of Class-E Power Amplifier q=1.41, mon=0.005, moff=1000, α=0, k=0, Q =20 q=1.41, mon=0.005, moff=1000, α=0, k=0, Q =20 0 0 4 5 Class−A Class−B Class−AB Class−E DD Ids(t)/I Vds(t)/V 2 1 0 0 Class−A Class−B Class−AB Class−E 4 DD 3 64 3 2 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T 0 0 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T (a) 1 (b) q=1.41, mon=0.005, moff=1000, α=0, k=0, Q0=20 1 Class−A Class−B Class−AB Class−E 0.8 Vgs(t) 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t/T 1 (c) Figure 4.14: Waveforms at 1dB compression point for q = 1.41 the chapter 5, a real transistor model will be given, and the linearity for a given technology will be analyzed. Chapter 5 Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device In this chapter a broadband Class-E power amplifier was designed in order to verify the results obtained in the previous chapters. The broadband Class-E power amplifier was build with extended-drain NMOS (ED-NMOS) transistors in 65nm CMOS technology [39], which have higher breakdown voltage than the standard transistors. First the switching and linear operation of this device is studied in Section 5.1.1. In Section 5.2 a systematic design approach is applied to design a broadband Class-E power amplifier from 0.65GHz to 1.05GHz. The post-layout simulation results are presented in Section 5.3. 5.1 Analysis of Switching and Linear Operation of ED-NMOS 5.1.1 DC I-V Characteristics and Non-Linear Capacitances of ED-NMOS In [31] Acar has demonstrated that the drain efficiency is limited by transistor technology. Moreover, the design set K is as a function of transistor technology parameters mon and mo f f . Therefore it is necessary to know the transistor technology parameters in advanced. The transistor technology parameters consist of the ON-resistance, OFF-resistance, and the total output capacitance seen into drain node. The ON-resistance and OFF-resistance can be obtained by measuring the DC I-V characteristics. The output capacitance can be acquired by measuring the S-parameters for different gate-source and drain-source voltages. Unfortunately the PCB for S-parameters measurements was not ready when I started to design the power amplifier. Hence the output capacitance is obtained by simulating the device in Cadence, then extracting the small-signal model. 65 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device VB_P1 VB_P2 20ohm 66 S_P 20ohm D W/L=1280/0.28 RF_IN 339pF 15.34pF W/L=3480/0.28 INVERTER 15.34pF ED-NMOS W/L=1280/0.28 20ohm VB_N1 20ohm VB_N2 S S Figure 5.1: Schematics of active device Figure 5.2: Layout of active device The active device used in this design is an ED-NMOS transistor with a drive inverter in 65nm CMOS technology. It was designed by M. Acar. Fig. 5.1 shows the schematics of active device, and the layout is shown in Fig. 5.2. To measure DC I-V characteristics, a test setup was built up shown in Fig. 5.3. The die was mounted on a test PCB. The die and PCB was connected via bondwires which are not shown in the figure. The cable resistance of supply cable is 0.1Ω. During the test, the gate biasing V BN and V BP for the NMOS and PMOS of inverter are connected together. When the V BN, V BP and the supply voltage V DD1 of inverter are fixed, the gate bias voltage for the ED-NMOS is also fixed. Therefore the gate bias voltage of ED-NMOS is determined by inverter. Hence the DC I-V characteristics of the ED-NMOS can be obtained by setting different supply voltage Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 67 Figure 5.3: DC I-V measurement setup V DD2 for Vds of the ED-NMOS and different V DD1, V BN and V BP for Vgs of the ED-NMOS. Fig. 5.4 shows the measured results for VBN=VBP=0V. Since VBN=VBP=0V, the NMOS of inverter is always opened and the PMOS of inverter is always closed, the output node of inverter or the gate voltage of ED-NMOS is always equal to supply voltage V DD1. In Fig. 5.3, two parasitic source resistors RS 1 and RS 2 are added to the sources of inverter and ED-NMOS to take into account parasitic resistance of metal lines of layout. In Fig. 5.4, the simulation results obtained by using Cadence transistor model of ED-NMOS are also shown. The cable losses are taken into account in the simulation. To better model the chip, av-extraction was done in Cadence to extract the parasitic capacitances and resistances. The extraction shows that there is 0.02Ω parasitic resistance at the source node. However, the simulated DC I-V curves shown in Fig. 5.4(a) is larger than the measured results. This may be due to the error between the transistor library model and the real fabricated transistor. One can tune the source resistance RS 2 to make the simulation results close to the measured ones. Finally when RS 2 =0.14Ω, the simulation results are close to measured results which is shown in Fig. 5.4(b). Besides the transistor model in Cadence, the DC I-V curves can also be modeled by polynomial functions that were presented in Section 4.1. Fig. 4.2 shows the modeled I-V curves by 6th-order polynomial functions. The av-extraction in Cadence can extract the parasitic capacitances resulting from the metal lines of layout. Fig. 5.5 shows the parasitic capacitances (red) extracted by Cadence. In principle, S-parameter measurements were supposed to be done to extract the actual device capacitances. But since there is no pad on the die for probe measurement, we did not measure the actual S-parameters. The device capacitances are estimated by Cadence simulation using the same method mentioned in [38]. Since the efficiency is mainly related with final stage, only the Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device DC I−V curves DC I−V curves Measured results Cadence Lib. Model (Rs2=0.02Ω) 2.5 Ids2 (A) Ids2 (A) VDD1=2.2V VDD1=2.1V VDD1=2.0V VDD1=1.9V VDD1=1.8V VDD1=1.7V VDD1=1.6V VDD1=1.5V VDD1=1.4V VDD1=1.3V VDD1=1.2V VDD1=1.1V VDD1=1.0V VDD1=0.9V VDD1=0.8V VDD1=0.7V 1.5 1 0.5 0 1 2 3 4 Vdd2 (V) 5 Measured results Cadence Lib. Model (Rs2=0.14Ω) 2 2 0 68 VDD1=2.2V VDD1=2.1V VDD1=2.0V VDD1=1.9V VDD1=1.8V VDD1=1.7V VDD1=1.6V VDD1=1.5V VDD1=1.4V VDD1=1.3V VDD1=1.2V VDD1=1.1V VDD1=1.0V 1.5 1 0.5 VDD1=0.9V VDD1=0.8V VDD1=0.7V 0 6 0 1 2 (a) 3 4 Vdd2 (V) 5 6 (b) Figure 5.4: Measured DC I-V curves for VBN=VBP=0V VB_P1 20ohm VB_P2 S_P 20ohm ED-NMOS 0.7pF 1.5pF 1280/0.28 15.34pF 0.7pF 0.2pF RF_IN G 15.34pF D 339pF 3480/0.28 INVERTER 0.2pF 1280/0.28 1.2pF 5.3pF 1.6pF 20ohm VB_N1 0.14ohm 20ohm VB_N2 S S Figure 5.5: Schematics of active device with parasitic capacitance (red) extracted by Cadence capacitances of ED-NMOS are extracted. Fig. 5.6 shows the non-linear capacitances Cds , Cgd , and Cgs as a function of drain-source voltage Vds for different gate bias voltage Vgs . From the figure, one can observe that the non-linear capacitances Cds and Cgd for different Vgs are almost overlaid on each other. The capacitances Cds and Cgd can be expressed as: C(vds ) = C j0 (1 + vds /Vbi )n (5.1) where C j0 is the capacitance at zero voltage, Vbi is built-in potential, and n is the grading coefficient of the pn-junction [40]. For Cds , C j0 = 3.8pF , Vbi = 0.2V, and n = 0.2. For Cgd , C j0 = 5.5pF, Vbi = 0.2V, and n = 0.2. For the nonlinear gate-source capacitance Cgs , 15thorder polynomial functions are used to fit the curves. Fig. 5.7 summarizes the transistor model that will be used. Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 8 4 Vgs=0.7V Vgs=1.2V Vgs=1.8V Vgs=2.4V 3.5 6 Cgd (pF) 2.5 2 5 4 1.5 3 1 2 5 10 Vds (V) 15 1 0 20 5 (a) 10 Vds (V) 15 (b) 18 Vgs=0.7V Vgs=1.2V Vgs=1.8V Vgs=2.4V 16 Cgs (pF) Cds (pF) Vgs=0.7V Vgs=1.2V Vgs=1.8V Vgs=2.4V 7 3 0.5 0 69 14 12 10 8 0 5 10 Vds (V) 15 20 (c) Figure 5.6: ED-NMOS device capacitances obtained by Cadence simulation for different gate bias voltage Vgs : (a)Cds , (b)Cgd , (c)Cgs . Equation 5.1 Cgd Gate Cgs + Drain gmxV rds V Cds Source 15th -order polynomial functions 6th -order polynomial functions Figure 5.7: Synthesized transistor model 20 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device (a) 70 (b) Figure 5.8: Bondwires illustrations RL CL1 L CL2 Figure 5.9: Bondwires equivalent circuit 5.1.2 Bondwires Simulation Besides modeling of the device itself, the bondwires linking the die and PCB should be taken into account. Fig.5.8 shows the distributions of bondwires for this die: four bondwires connecting the drain terminal of ED-NMOS to PCB, two bondwires for the RFIN and PCB, three bondwires for power supply of inverter, one bondwire for each of gate bias of NMOS and PMOS of inverter, and six short bondwires for source to ground. A 3D model shown in Fig. 5.8(b) was built in ADS-EMDS to simulate the inductance and parasitic resistance and capacitance of the bondwires. In the model, the projection length d, the height H1 and H2 , and angles α and β have to be defined. Since the rough dimension of the PCB is given, the approximate projection length d could be obtained. However, from the experience, the height H1 and angles α and β are difficult to control in practice. Thus only estimated values are given for these parameters. For all the bondwires, we assumed α = 60◦ , β = 15◦ , and H1 ≈ 0.2d. The projection length d is shown in Table5.1. The equivalent circuit of bondwires is shown in Fig.5.9 which consists of bondwire inductance L, parasitic series resistance RL , and parasitic capacitances C L1 and C L2 to ground (e.g., bondwire capacitance and bond pads). By S-parameter simulation, the component values can be obtained. Table5.1 shows the component values for different bondwires at 1GHz. In the following sections, the simulation model takes into account the effects of the bondwires. Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 71 Table 5.1: Bondwire equivalent inductance and parasitic resistance and capacitance at 1GHz Drain-PCB (LB1 ) Source-PCB (LB2 ) RFIN-PCB (LB3 ) VBN/VBP-PCB (LB4 ) VDD1-PCB (LB5 ) 5.1.3 d (mm) 0.5 0.4 1.4 0.9 1.0 H1 (mm) 0.1 0.08 0.3 0.2 0.2 N 4 6 2 1 3 L (nH) 0.24 0.07 0.93 0.80 0.56 RL (Ω) 0.05 0.02 0.21 0.19 0.10 C L1 (fP) 16.9 8.8 22.0 15.0 23.4 C L2 (fP) 25.7 50.0 38.4 28.1 34.0 Switch-Mode Operation of ED-NMOS For this transistor, the measured ON-resistance for Vgs = 2.2V is equal to 0.76Ω. The simulated average output capacitance (Cds + Cgd ) is 4.14pF. Thus the technology parameter mon = ωCRON at 1GHz is equal to 0.02. The breakdown drain-source voltage BVds of ED-NMOS transistor is about 15V. To relieve the device stress, a lower breakdown drain-source voltage BVds = 12V is used in the simulation. Since the peak drain voltage is usually three to four times of supply voltage, a supply voltage of 4V was chosen at the beginning. Therefore, the switch-mode performance of this synthesized ED-NMOS transistor as a function of q can be investigated. Fig. 5.10 shows the simulation results for Q0 = 5 at 1.0GHz. From the figures, one can observe that the maximum drain efficiency of 93% is obtained at q ≈ 1.7, but the maximum output power of about 30dBm is obtained at infinite dc-feed inductance. The peak drain voltage for VDD = 4V is beyond BVds = 12V. To protect the device, the peak drain voltage must be reduced. One can derease the supply voltage to lower the peak drain voltage, but the output power will be decreased at the same time. In this case, variable-voltage operation is a good choice. For the same supply voltage, the peak drain voltage can be decreased by increasing parameter α. For example, the peak drain voltage decreases from 3.7VDD to 3VDD when the α increases from 0 to 1. The degradation of drain efficiency is only 2%. For comparison purpose, the results obtained by ED-NMOS Cadence library model are also shown on the same graph. The results are very close to that of the synthesized transistor model. 5.1.4 Linear Operation of ED-NMOS In the previous section, the switch-mode characteristics of ED-NMOS have been investigated. The linearity of ED-NMOS will be discussed in this section. Because of the convergence problem of the synthesized transistor model, the Cadence library model was used here to investigate the power amplifier. The transistor is biased at Vgs = 1.55V, Vgs = 1.2V, and Vgs = 0.7V, corresponding to Class-A, Class-AB, and Class-B modes respectively. A single-tone sinusoidal signal was fed into the gate of the transistor. Fig. 5.11 shows the large signal performance over power sweep at 1GHz for four different loads (q = 0.01, q = 1.21, q = 1.41 and q = 1.61). Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device d=0.5, mon=0.02, moff=1000, Q =5, V d=0.5, mon=0.02, moff=1000, Q =5, V =4.0V 0 DD 31 0.9 30 Output power (dBm) Drain efficiency 0 1 0.8 0.7 0.6 0.2 0.4 0.6 0.8 1 q 28 27 Cadence Lib. Model Synthesized Model 1.2 1.4 1.6 1.8 26 0 2 (a) 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 (b) d=0.5, mon=0.02, moff=1000, Q =5, V =4.0V d=0.5, mon=0.02, moff=1000, Q0=5, VDD=4.0V 0 DD 4 0.12 Cadence Lib. Model Synthesized Model 3.9 0.1 3.8 0.08 Vdspeak/VDD Power−output capability =4.0V DD 29 Cadence Lib. Model Synthesized Model 0.5 0 72 0.06 0.04 3.7 3.6 3.5 3.4 3.3 3.2 0.02 Cadence Lib. Model Synthesized Model 0 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 3.1 3 0 2 (c) 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 (d) q=1.61, d=0.5, mon=0.02, moff=1000, Q0=5, VDD=4.0V q=1.61, d=0.5, mon=0.02, moff=1000, Q0=5, VDD=4.0V 14 Cadence Lib. Model Synthesized Model Cadence Lib. Model Synthesized Model 1 0.8 12 Drain current Drain−source voltage (V) 16 10 8 6 0.6 0.4 0.2 4 0 2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 −9 t x 10 (e) −0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 −9 t x 10 (f) Figure 5.10: Switch-mode performance of ED-NMOS using synthesized model Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device Class−A mode Class−A mode 1 30 26 24 q=0.01 q=1.21 q=1.41 q=1.61 0.8 22 20 18 16 0.7 0.6 0.5 0.4 0.3 14 0.2 12 0.1 10 −5 0 q=0.01 q=1.21 q=1.41 q=1.61 0.9 Drain efficiency Output power (dBm) 28 5 10 Input power (dBm) 0 10 15 12 14 16 18 20 22 24 Output power (dBm) (a) q=0.01 q=1.21 q=1.41 q=1.61 0.8 20 18 16 0.7 5 10 Input power (dBm) 0 10 15 12 14 16 18 20 22 24 Output power (dBm) (c) 30 Class−B mode Class−B mode 1 q=0.01 q=1.21 q=1.41 q=1.61 0.8 22 20 18 16 0.7 0.6 0.5 0.4 0.3 14 0.2 12 0.1 5 q=0.01 q=1.21 q=1.41 q=1.61 0.9 Drain efficiency Output power (dBm) 28 (d) 30 10 0 26 0.3 0.1 24 30 0.4 0.2 26 28 0.5 12 28 26 0.6 14 0 q=0.01 q=1.21 q=1.41 q=1.61 0.9 22 10 −5 30 1 Drain efficiency Output power (dBm) 24 28 Class−AB mode Class−AB mode 26 26 (b) 30 28 73 10 15 Input power (dBm) (e) 20 0 10 12 14 16 18 20 22 24 Output power (dBm) (f) Figure 5.11: Large signal performance over power sweep at 1GHz for different gate bias and q Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 74 It is apparent that the output power of q = 0.01 is about 0.5-1dB larger than that of q ≥ 1.21 for the same input signal. For Class-A and Class-AB modes, the dc-feed inductance has little effect on the drain efficiency when output power is below the saturation power. The efficiency is dependent of the dc-feed inductance only when the power amplifier delivers the power that is near the saturation power. This is due to that the transistor is always turned on or conducting current for a small input signal when biasing at Class-A or Class-AB mode. The efficiency is higher for large q than for small q. One can also find that the efficiency is very sensitive to gate bias voltage. For the same output power, (i.e. 26dBm), the efficiency for Class-B mode is 35% larger than that of Class-AB, and 55% larger than that of Class-A, which is expected from the classical power amplifier theory. Fig. 5.12 shows the drain efficiency, output 1dB compression point, power-output capability and power gain as a function of q when the amplifier is driven into 1dB compression point. It can be observed that the maximum output 1dB compression point is obtained at q = 0.01 or RF choke. The output 1dB compression point decreases as q increases. The output 1dB compression point of Class-B is about 2dB larger than that of Class-A. For the Class-E load condition, the Class-B bias always shows better drain efficiency and power-output capability. One can also observe that the power gain of Class-B is about 6dB small than that of Class-A or Class-AB for q = 0.01. The power gain of Class-B is very tolerant of q, but that of Class-A or Class-AB decreases as q increases. The intermodulation distortion characteristic is an important parameter to evaluate the linearity of an amplifier. When applying a two-tone signal with equal amplitude to the amplifier, the intermodulation products can be found in the output spectrum. Fig. 5.13 shows the third-order intermodulation distortion (IMD3) as a function of total two-tone output power. For the power amplifier, we hope the device can deliver high output power with good linearity. In Fig.5.13, one can find that for Pout = 25dBm the smallest IMD3 of -35dBc can be obtained when the device is biased at Vgs = 1.2V with RF choke. As the gate bias voltage Vgs moves from the ClassA mode to Class-B mode, the IMD3 for the amplifier with the RF choke degrades gradually. When the device is biased at Class-B mode, the amplifier shows better IMD3 for finite dc-feed inductance than for RF choke. For example, IMD3 is equal to -30dBc for Pout = 25dBm when the amplifier is biased at 0.7V for q = 1.21, which is about 5dB worse than that of best value obtained at Vgs = 1.2V, but the efficiency is 20% higher than that of amplifier biased at 0.7V with RF choke. From the figure, the output third-order intercept point (OIP3) can be calculated. When q = 0.01, the OIP3 for Class-A is about 38dBm, while 39.5dBm for Class-AB. It is about 10 dB more than output 1dB compression point of Class-A and Class-AB. That agrees very well with the classical theory of OIP3 and P1dB, which is OIP3=P1dB+9.6dB. For the Class-B, the OIP3 is about 37dBm when q = 1.21, which is only 5dB larger than P1dB. Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device Drain efficiency @ Pout1dB 1 mon=0.02, moff=1000, α=0, k=0, Q0=5 Power−output capability @ Pout1dB mon=0.02, moff=1000, α=0, k=0, Q0=5 Class−A Class−B Class−AB 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 0.12 Class−A Class−B Class−AB 0.1 0.08 0.06 0.04 0.02 0 0 2 0.2 0.4 0.6 0.8 (a) mon=0.02, moff=1000, α=0, k=0, Q0=5 2 mon=0.02, moff=1000, α=0, k=0, Q0=5 Power gain @ Pout1dB Pout1dB(dBm) 1.2 1.4 1.6 1.8 20 28 26 24 20 0 1 q (b) 30 22 75 Class−A Class−B Class−AB 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 Class−A Class−B Class−AB 18 16 14 12 10 0 0.2 0.4 0.6 0.8 (c) 1 q 1.2 1.4 1.6 1.8 2 (d) Figure 5.12: Simulated drain efficiency, power-output capability, 1dB compression point and power gain versus q for Class-A,AB,and B biases. From above figures, one can conclude that to maintain high efficiency and high linearity at high output power for this device (ED-NMOS), the amplifier should be biased at Class-B mode with finite dc-feed inductance. 5.2 Broadband Class-E Power Amplifier Design In this section, the systematic design approach for broadband Class-E power amplifier will be described. The design approach is mainly divided into two parts: optimum load design at a single frequency and broadband output load network design. The specification for the final broadband Class-E power amplifier is shown in Table 5.2. Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device Class−A bias (Vgs=1.55V) Class−AB bias (Vgs=1.20V) −10 IMD3(dBc) −30 −10 q=0.01 q=1.21 q=1.41 q=1.61 −20 −30 IMD3(dBc) −20 −40 −50 −50 −60 −70 −70 5 10 15 Output power (dBm) 20 −80 0 25 q=0.01 q=1.21 q=1.41 q=1.61 −40 −60 −80 0 5 (a) Class−AB bias (Vgs=1.00V) 25 Class−B bias (Vgs=0.70V) q=0.01 q=1.21 q=1.41 q=1.61 −20 −30 −40 −50 −40 −50 −60 −60 −70 −70 −80 0 20 −10 IMD3(dBc) IMD3(dBc) −30 10 15 Output power (dBm) (b) −10 −20 76 5 10 15 Output power (dBm) 20 25 (c) −80 0 q=0.01 q=1.21 q=1.41 q=1.61 5 10 15 Output power (dBm) 20 (d) Figure 5.13: 3rd-order intermodulation distortion as a function of output power for different q at f0 = 1GHz with ∆ f = 100kHz. Table 5.2: Specifications for broadband Class-E power amplifier Specification Operation frequency Output Power Output power flatness Drain efficiency Power added efficiency Power gain Target value 650MHz-1050MHz ≥ 30dBm ≤ 3dB ≥ 70% ≥ 60% ≥ 20dB 25 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 5.2.1 77 Optimum Load Design First, an optimum load will be found at a single frequency. The power amplifier with this optimum load can satisfy the required specifications given in Table 5.2. The detailed steps are described as follows. • Step 1: Calculate the technology parameter mon = ωCRON and mo f f = ωCROFF . In Section5.1.3, we have known that the average total output capacitance C is 4.14pF and ONresistance RON is 0.75Ω. Since the technology parameter mon determines the maximum value of theoretical drain efficiency, it is wise to predict the worst theoretical drain efficiency this device can obtain. Because the mon is proportional to frequency, the maximum mon is obtained at the maximum operating frequency. For this design, the maximum operating frequency is about 1GHz. Thus the maximum mon is equal to 0.02. The minimum mo f f is equal to 300 corresponding to ROFF = 10kΩ. • Step 2: Calculate the duty-cycle d of the drive signal. The device used in this design includes an inverter which is used to drive the final stage. The simulated output signal waveform of the inverter at 1GHz is shown in Fig. 5.14. For the nominal operation, the gate bias voltages for both NMOS and PMOS are 1.2V, and the supply voltage is 2.4V. Since the threshold voltage of ED-NMOS is about 0.7V, the device can be regarded in an active state when Vgs > 0.7V. Thus the duty-cycle is defined as the ratio of time interval of Vgs > 0.7V to one period. From the figure, one can observe that the duty-cycle d is 56%, the rise time tr (from 0.7V to 2.1V) is 18%, and the fall time t f (from 2.1V to 0.7V) is 20%. • Step 3: Calculate the design set K in Maple based upon the input parameters mon , mo f f , d, ω, VDD , q, α, and k by analytical approach. The input parameters mon , mo f f , and d are determined by the device itself and the external drive signal. Generally, ω = 1 and VDD = 1. The parameter q, α, and k are user defined. The efficiency, output power, and drain voltage and current waveforms are dependent on these parameters. User can tune these parameters to meet a specific requirement. Usually, α and k are set to zero at the beginning so that the amplifier will operate at optimum Class-E condition (zero-voltage switching and zero-slope switching). Then one can sweep q to obtain the design set K. Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 78 Inverter output signal at 1GHz (VDD=2.4V, VBN=VBP=1.2V) 2.5 2 Vgs (V) 1.5 1 Vth=0.7 0.5 0 −0.5 0 0.2 0.4 0.6 0.8 1 t (ns) Figure 5.14: Simulated inverter output signal at 1GHz • Step 4: Calculate the supply voltage VDD , load resistance RL and passive components L, L1 , C1 based upon the design set K, loaded quality factor Q0 , and desired output power POUT . Since the total output capacitance C and design set Kc have been obtained in step 1 and 3, the load resistance can be found from Eq.3.64 RL = KC . ωC (5.2) KC POUT . KL ωC (5.3) The supply voltage can be obtained by VDD = r The passive component values L, L1 , and C1 are found in a way similar to the example shown in Section 3.2.1. The desired output power for this design is 1W or 30dBm. In Section 4.2, the effects of non-ideal drive signal on the output power and efficiency have already been discussed. For the drive signal of this device, the rise and fall times are about 20%. In Fig.4.9(e), one can observe that the ouptut power for 20% rise and fall times is about 1dB smaller than for ideal square wave signal. Accounting this effect, the output power in Eq.5.3 shoule be at least 1dB larger than the designed output power. For this design, POUT = 31dBm. Fig.5.15 shows the calculated supply voltage VDD and load resistance RL as a function of q. One can observe that for finite dc-feed inductance the required load resistance is larger than that for RF choke. This relieves the difficulty in the load resistance design. Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz 79 d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz 5 20 18 16 14 RL (ohm) VDD (V) 4.5 4 12 10 α=0, P0=31dBm 1 q 1.2 1.4 1.6 1.8 α=1.5, P0=31dBm 2 α=1.5, P0=30.4dBm 0.2 0.4 0.6 0.8 α=1, P0=31dBm 4 α=1.5, P0=31dBm 3 0 α=0, P0=31dBm 6 α=1, P0=31dBm 3.5 8 2 0 0 α=1.5, P0=30.4dBm 0.2 0.4 0.6 0.8 (a) 1 q 1.2 1.4 1.6 1.8 2 (b) Figure 5.15: Calculated supply voltage and load resistance for Pout =31dBm • Step 5: Substitute the calculated supply voltage, load resistance, passive component val- ues into the Class-E circuit in Cadence and simulate the circuit to evaluate the performance of the amplifier for different load impedances. Fig. 5.16 shows the drain efficiency, output power, power-output capability, and maximum drain voltage and current as a function of q. It is apparent that the output power for α = 0 is very near 30dBm that agrees very well with what we predicted in step 4. The peak drain-source voltage for α = 0 is about 4VDD which is also equal to theory value (i.e., 4VDD for d = 56%). • Step 6: Make decision based upon the simulation results. To assure a reasonable device life time, the device stress should be considered firstly. If the peak drain current is larger than the allowed maximum drain current, it means that the device cannot deliver the desired current. One has to reduce the desired output power to decrease the peak current. If the peak drain-source voltage is larger than the breakdown voltage, one can decrease it by modifying the amplifier operation mode from the optimum operation to suboptimum operation. For example, one can increase the switch voltage at the moment the switch is closed by increasing the parameter α. The absolute value of peak drain-source voltage for α = 0 shown in Fig. 5.16(e) is larger than breakdown voltage BVds = 12V. Thus we can increase α to decrease the peak drain-source voltage. On the same figure, the performance of the amplifier for α = 1 and α = 1.5 is shown. The drain-source voltage and drain current waveforms are shown in Fig. 5.17. The increase of switching voltage at the moment the switch is closed is very apparent in the figure. One can find that the peak drain-source voltage has decreased to 2.7VDD , but the absolute value is still larger than 12V. In this case, one has to adjust the desired output power level to decrease the supply voltage. Here, we decreased the output power from 30dBm to 29.4dBm, thus the output power in Eq.5.3 will be reduced to Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz 80 d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz 1 30 29.8 Output power (dBm) Drain efficiency 0.9 0.8 α=0, P0=31dBm 0.7 α=1, P0=31dBm α=1.5, P0=31dBm 0.6 0.2 0.4 0.6 0.8 1 q 29.4 29.2 29 28.8 α=1.5, P0=30.4dBm 0.5 0 29.6 1.2 1.4 1.6 1.8 2 28.6 0 (a) α=0, P0=31dBm α=1, P0=31dBm α=1.5, P0=31dBm α=1.5, P0=30.4dBm 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 (b) d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz 0.08 0.06 α=0, P0=31dBm 0.04 α=1, P0=31dBm 0.02 α=1.5, P0=31dBm α=1.5, P0=31dBm α=1.5, P0=30.4dBm 4 3.5 3 2.5 α=1.5, P0=30.4dBm 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 0 2 (c) 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 (d) d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz 3 α=0, P0=31dBm α=0, P0=31dBm 2.9 18 α=1, P0=31dBm 16 α=1.5, P0=30.4dBm α=1, P0=31dBm 2.8 α=1.5, P0=31dBm α=1.5, P0=31dBm 2.7 Idspeak/IDD Vdspeak (V) α=1, P0=31dBm 4.5 0.1 20 α=0, P0=31dBm 5 0.12 Vdspeak/VDD Power−output capability 0.14 0 0 2 14 α=1.5, P0=30.4dBm 2.6 2.5 2.4 2.3 12 2.2 2.1 10 0 0.2 0.4 0.6 0.8 (e) 1 q 1.2 1.4 1.6 1.8 2 2 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 (f) Figure 5.16: Simulated results as a function of q for different α 2 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device q=1.61, d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz 20 α=1, P0=31dBm 16 α=1.5, P0=31dBm 14 α=1.5, P0=30.4dBm α=0, P0=31dBm α=1, P0=31dBm 0.8 Drain current (A) Drain−source voltage (V) q=1.61, d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz 1 α=0, P0=31dBm 18 12 10 8 6 4 81 α=1.5, P0=31dBm α=1.5, P0=30.4dBm 0.6 0.4 0.2 0 2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t (ns) 1 −0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t (ns) (a) 1 (b) Figure 5.17: Drain-source voltage and drain current waveforms for different α 30.4dBm. The simulation results are also shown in Fig. 5.16. One can find that by decreasing the required output power the absolute value of drain-source voltage is below the breakdown voltage for q < 1. • Step 7: Select the optimum q and calculate the corresponding load impedance. Once the efficiency, output power, and peak drain-source voltage are all satisfied, the optimum load is obtained. The tunning procedure mentioned in step 6 will be ceased. For α = 1.5 and POUT = 30.4dBm, the peak drain efficiency of 85% is obtained at q = 0.01 or infinite dc-feed inductance. The peak output power of 29.2dBm is also obtained at q = 0.01. Therefore the optimum load is obtained at q = 0.01 for this device and this specifications. The optimum load impedances at fundamental and higher harmonic frequencies can be calculated. Fig.5.18 shows the load phase angle θ1 and load magnitude |Z1 | as a function of q for different α at the funda- mental frequency. It consists of the device output capacitance and output load network. The optimum load impedance for RF choke at fundamental, second, and third harmonic frequencies are Z1opt = 15.3∠20.8 Z2opt = 24.1∠ − 88.3 Z3opt = 13.8∠ − 89.7 Fig.5.19 summarizes the aforementioned design steps for Class-E power amplifier at a single frequency. Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz d=0.56, mon=0.02, moff=1000, Q0=5, f0=1GHz 20 α=0 α=1 α=1.5 80 70 Load magnitude |Z1| (ohm) Load phase angle θ1 (degree) 90 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 82 2 (a) 18 16 14 12 10 8 6 α=0 α=1 α=1.5 4 2 0 0 0.2 0.4 0.6 0.8 1 q 1.2 1.4 1.6 1.8 2 (b) Figure 5.18: Load impedance as a function of q for different α It is necessary to investigate the effects of load impedance variations on the performance of the power amplifier. Section 3.2.2 has shown that the amplifier is very sensitive to the load phase angle θ1 at fundamental frequency, and relatively tolerant to the load magnitude |Z1 | and other higher harmonic impedances. Thus only the effects of the variation of load phase angle θ1 on the efficiency, output power and device stress are shown in Fig.5.20. One can observe that to maintain the desired drain efficiency(>80%), output power(>29dBm), and peak drain-source voltage(<12V) the usable load phase angle range is between 0◦ to 20◦ . It also means that the load phase angle θ1 of broadband output load network should be in this range over the operation frequency range. 5.2.2 Broadband Output Load Network The optimum equivalent drain load impedances seen from the drain node have been given in the previous section. The optimum load impedances ZL1opt not including the device capacitance and bondwires for the operating frequencies are shown in Fig. 5.21. The ideal output performance is shown in Fig. 5.22 where the drain efficiency exceeds 85%, and the output power 29.3dBm. The peak drain-source voltage is almost constant around 12V, and the peak drain current around 0.65A over all the frequencies. The falling of PAE is due to the increase in the power dissipation of the inverter as the frequency increases. In order to achieve a wide bandwidth Class-E sub-optimum mode operation, a load network providing the correct load impedance over the bandwidth of operation is required. The proposed load network configuration using lumped elements is shown in Fig. 5.23. It consists of a series DC blocking capacitor Cblocking , followed by a network like second-order low-pass filter. The dc-feed inductor L is also a part of the output load network. Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device Device parameters extraction [ RON, R OFF, C ds, C gd ] Acquire duty cycle [d] m on, m off d Solve ideal Class -E equations for different q Calculate design sets KP(q), KC(q), KL(q),KX(q) Maple POUT, Q 0 Decrease POUT to decrease peak drain current and voltage Calculate V DD, R L, L, C 1, L 1, Solve real Class -E circuits for different q Cadence Idspeak <= Idsmax False True Vds peak <= Vds max False False True Select suitable q based upon P OUT, efficiency Calculate the optimum load impedance Figure 5.19: Class-E power amplifier design flowchart Increase alpha to decrease peak drain voltage Set alpha, k 83 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 1 14 29.6 0.9 13 Ispeak 29.4 0.85 12 0.7 29.2 0.8 11 0.6 10 0.5 9 0.4 Drain efficiency 0.95 PAE 29 0.75 Efficiency Output power Vdspeak (V) Output power (dBm) 15 1 Vdspeak 29.8 0.9 0.8 28.8 0.7 28.6 0.65 8 0.3 28.4 0.6 7 0.2 28.2 0.55 6 0.1 28 −30 −15 0 15 30 45 Load phase angle θ (degree) 5 −30 0.5 60 −15 1 0 15 30 Load phase angle θ1 (Degree) (a) Idspeak (A) 30 84 0 60 45 (b) Figure 5.20: Effects of load phase angle θ1 on the performance of power amplifier Optimum load impedance without device capacitance and bondwire 15 33 |ZL1|opt θL1opt 32 13 31 12 30 11 29 10 0.6 0.65 0.7 0.75 0.8 0.85 Frequency (GHz) 0.9 0.95 θL1opt (degree) |ZL1|opt (ohm) 14 28 1 Figure 5.21: Optimum fundamental load impedances ZL1opt over frequency 13 Drain efficiency 0.95 PAE 1 Vds peak 12.8 Ids peak 0.9 0.9 12.6 29.7 0.85 12.4 0.7 29.6 0.8 12.2 0.6 29.5 0.75 12 0.5 29.4 0.7 11.8 0.4 29.3 0.65 11.6 0.3 29.2 0.6 11.4 0.2 29.1 0.55 11.2 0.1 29 0.6 0.65 0.7 0.75 0.8 0.85 Frequency (GHz) (a) 0.9 0.95 0.5 1 Vds peak (V) 29.8 Efficiency Output power (dBm) 1 Output power 11 0.6 0.65 0.7 0.75 0.8 0.85 Frequency (GHz) 0.9 0.95 0.8 0 1 (b) Figure 5.22: Ideal output power, drain efficiency and PAE for the ideal optimum load impedances Idspeak (A) 30 29.9 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device VBP LB4 VDD1 LB5 Bondwire VB_P1 VB_P2 20ohm 20ohm S_P CMOS DIE 1280/0.28 15.34pF RF_IN 15.34pF 0.7pF 339pF L 1.5pF L2 3480/0.28 C1 C2 INVERTER 0.2pF 1280/0.28 LB4 L1 Cblocking LB1 5.3pF 1.2pF 0.14ohm 1.6pF VB_N1 Bondwire D 0.2pF G 20ohm VDD2 ED-NMOS 0.7pF LB3 ZL1opt ZL2opt ZL3opt Z1opt Z2opt Z3opt 85 Broadband output load network 20ohm VB_N2 S Bondwire S LB2 LB2 Bondwire VBN Figure 5.23: Broadband output load network for the PA Table 5.3: Ideal lumped element values for output load network L 12nH L1 4.5nH C1 7.8pF L2 7.5nH C2 3.3pF The output load network was synthesized by ADS optimizer. The optimization goals were set to the optimum load impedances at the operation frequencies. For this design it is the drain load phase angle θ1 < 20◦ , θ2 < −60◦ , and load magnitude |Z1 | ≈ 15. However, these goals cannot be satisfied at all operation frequencies. Table5.3 presents element values of the ideal lumped elements. The synthesized load impedances over the operation frequencies are shown in Fig.5.24. The synthesized load magnitude |Z1 | is around 20Ω that is larger than the optimum value of 15Ω. This will lead to lower output power. The ripple of |Z1 | is relatively small. The synthesized θ1 is below 20◦ from 0.7GHz to 1.1GHz, but θ2 of second harmonic load phase angle at 1.4GHz is larger than 0◦ which will lead to low drain efficiency. θ2 is smaller than -60◦ above 1.6GHz so that the usable frequency range is from 0.8GHz to 1.1GHz. The simulated amplifier performance for the synthesized output load network are shown in Fig5.25. One can observe that the output power is larger than 27dBm from 0.8GHz to 1.2GHz with 1dB flatness. The drain efficiency is above 80%, and PAE is about 60% from 0.8GHz to 1.2GHz. The peak drain efficiency is about 90%. The power gain is about 12dB with 1dB ripple. The peak drain-source voltage is below 12V except around 0.8GHz. It is 12.3V around 0.8GHz. We think that is acceptable. The drain-source voltage waveforms are shown in Fig.5.26 as a function of frequency. It is apparent that the operation mode is different at different frequencies dut to the different load impedances. 50 ohm Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 24 35 22 30 θ1 (degree) |Z1| (ohm) 20 18 16 14 12 10 0.7 0.9 1 Frequency (GHz) 1.1 25 20 15 10 Ideal magnitude Synthesized magnitude 0.8 Ideal phase Synthesized phase 5 0.7 1.2 0.8 (a) 1.1 1.2 90 Ideal phase Synthesized phase 60 θ2 (degree) 80 |Z2| (ohm) 0.9 1 Frequency (GHz) (b) 100 60 40 20 Ideal magnitude Synthesized magnitude 0 1.4 86 1.6 1.8 2 Frequency (GHz) 2.2 2.4 30 0 −30 −60 −90 1.4 (c) 1.6 1.8 2 Frequency (GHz) 2.2 2.4 (d) Figure 5.24: Synthesized drain load impedances as a function of frequency with ideal lumped elements 5.3 Layout and Post-Layout Simulations The layout was designed to implement the broadband Class-E power amplifier. Murata’s high Q inductors and capacitors were selected for the output load network. Since the effects of microstrip lines and parasitic resistances, capacitances and inductances of Murata’s components, the final passive component values are different from the ideal lumped elements given in Table 5.3. But the main design goal is still to realize the required load magnitudes and phase angles in the operation frequency band. The Murata component values are shown in Table5.4. The final layout is shown in Fig.5.27. In the figure, the resistor R stab and capacitor C stab at the input make the power amplifier unconditionally stable both at low and high frequencies. The final layout was simulated by Momentum, and imported into schematics to do post-layout simulations with Murata components. The synthesized drain load impedances are shown in Fig.5.28. One can see that the load phase angle θ1 is much flatter for C1 = 6.2pF than for C1 = 6.8pF. But this component of C1 = 6.2pF is out of stock, and can only be delivered after two months. We could not wait for so long time. Therefore in the final design, the component of C1 = 6.8pF Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device V DD2 =4.0V, V =2.4V, V =V DD1 BN V =1.2V, P =14dBm BP DD2 in DD1 =2.4V, V =V BN =1.2V, P =14dBm BP in 1 30 Output power 0.9 0.8 29 0.7 Efficiency Output power (dBm) =4.0V, V 28 27 0.6 0.5 0.4 0.3 0.2 26 Drain efficiency PAE 0.1 25 0.7 0.8 0.9 1 Frequency (GHz) 1.1 0 0.7 1.2 0.8 0.9 1 Frequency (GHz) (a) V DD2 =4.0V, V DD1 =2.4V, V =V BN 1.2 VDD2=4.0V, VDD1=2.4V, VBN=VBP=1.2V, Pin=14dBm =1.2V, P =14dBm BP in 15 Power gain Vdspeak 14 Vdspeak (V) 14 13 12 13 12 11 11 10 0.7 1.1 (b) 15 Power gain (dB) 87 0.8 0.9 1 Frequency (GHz) 1.1 1.2 10 0.7 0.8 0.9 1 Frequency (GHz) (c) 1.1 1.2 (d) Figure 5.25: Power amplifier performance for the synthesized ideal lumped elements Table 5.4: Murata lumped element values for output load network L 12nH L1 3.3nH C1 6.8pF L2 7.5nH C2 2.2pF was used. One can also find that the load phase angle θ2 at 1.2GHz (the second harmonics of 0.6GHz) is larger than 0◦ . This will lead to lower drain efficiency. The post-layout simulation results of switch-mode operation from 0.6GHz to 1.2GHz are presented in Fig.5.29. The power level of the input RF signal is 14dBm so that the power amplifier operates at switch-mode. The supply voltage for the final stage (ED-NMOS) is 4V, and 2.4V for inverter. The gate bias voltage for NMOS and PMOS of the inverter is 1.2V. One can observe that the output power is larger than 27dBm from 0.65GHz to 1.05GHz, but smaller than what we expected. This is because the synthesized load magnitude |Z1 | is larger than the optimum value of 15.3Ω. The flatness of the output power is less than 1dB from 0.65GHz to 1.05GHz. The drain efficiency is larger than 75% from 0.65GHz to 1.05GHz, and the power-added efficiency is above 50% in this range. The drain efficiency is smaller than the Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 12 12 f0=800MHz 10 8 Vds (V) Vds (V) 8 6 6 4 4 2 2 0 0 f0=900MHz 10 0.25 0.5 0.75 time (ns) 1 0 0 1.25 0.2 (a) 1 12 f0=1000MHz 10 f0=1100MHz 10 8 Vds (V) 8 Vds (V) 0.8 (b) 12 6 6 4 4 2 2 0 0 0.4 0.6 time (ns) 0.2 0.4 0.6 time (ns) 0.8 1 0 0 0.2 (c) 0.4 0.6 time (ns) 0.8 (d) Figure 5.26: Drain-source voltage waveforms at different frequencies for the synthesized ideal lumped elements Figure 5.27: Final PCB layout 88 30 50 25 40 15 10 20 10 0 Ideal magnitude Post−layout magnitude (C1=6.2pF) Post−layout magnitude (C1=6.8pF) 5 0 0.6 0.7 0.8 0.9 1 Frequency (GHz) 1.1 Ideal magnitude Post−layout magnitude (C1=6.2pF) Post−layout magnitude (C1=6.8pF) −10 −20 0.6 1.2 0.7 (a) 0.8 0.9 1 Frequency (GHz) 1.1 1.2 (b) 100 90 80 60 60 θ2 (degree) |Z2| (ohm) 89 30 20 θ1 (degree) |Z1| (ohm) Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 40 Ideal magnitude Post−layout magnitude (C1=6.2pF) Post−layout magnitude (C1=6.8pF) 30 0 −30 20 Ideal magnitude Post−layout magnitude (C1=6.2pF) Post−layout magnitude (C1=6.8pF) 0 1.2 1.4 1.6 1.8 2 Frequency (GHz) 2.2 2.4 −60 −90 1.2 (c) 1.4 1.6 1.8 2 Frequency (GHz) 2.2 2.4 (d) Figure 5.28: Drain load impedances for final layout with Murata components result obtained by ideal lumped elements. This is due to the loss at the parasitic resistances of passive components and metal loss of microstrip lines. The output power and drain efficiency are quite flat from 0.65GHz to 1.05GHz because of the flat load magnitude |Z1 | and small ripple in load phase angle θ1 over this range. The power gain is more than 13dB from 0.65GHz to 1.05GHz without input matching. The peak drain-source voltages at 0.65GHz and 1.05GHz are about 12.5V. We think the device can undertake this high drain voltage. Fig.5.29(e) shows that the amplifier is unconditionally stable from 0 to 5GHz. We are very interested in how the duty-cycle influences the performance of the broadband ClassE power amplifier. In this design, the duty cycle is adjusted by setting the different gate bias voltages of NMOS and PMOS of inverter. Fig 5.30 shows the waveforms of the drive signals to the final stage (ED-NMOS) tuning by VBN and VBP at 1GHz. The duty cycle decreases from 72.3% to 49.1% when the gate bias voltages VBN and VBP increases from 1.0V to 1.3V. The effects of variations of duty-cycle on the output power, drain efficiency, PAE, power gain, peak drain-source voltage and stability are shown in Fig.5.31. It is apparent that by increasing the duty cycle (decreasing VBN and VBP ) the output power can be improved, but the peak drainsource voltage will be increased simultaneously. The power gain is also increased by increasing Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device V DD2 =4.0V, V =2.4V, V =V DD1 BN V =1.2V, P =14dBm BP DD2 in DD1 =2.4V, V =V BN =1.2V, P =14dBm BP in 1 30 Output power 0.9 0.8 29 0.7 Efficiency Output power (dBm) =4.0V, V 28 27 0.6 0.5 0.4 0.3 0.2 26 Drain efficiency PAE 0.1 25 0.6 0.7 0.8 0.9 1 Frequency (GHz) 1.1 0 0.6 1.2 0.7 0.8 0.9 1 Frequency (GHz) (a) V DD2 =4.0V, V DD1 1.1 =2.4V, V =V BN VDD2=4.0V, VDD1=2.4V, VBN=VBP=1.2V, Pin=14dBm =1.2V, P =14dBm BP in 15 Power gain Vdspeak 14 Vdspeak (V) 14 13 12 13 12 11 11 10 0.6 0.7 0.8 0.9 1 Frequency (GHz) 1.1 10 0.6 1.2 0.7 0.8 0.9 1 Frequency (GHz) (c) V =4.0V, V DD2 =2.4V, V =V DD1 1.1 1.2 (d) BN =1.2V, P =14dBm BP V in =4.0V, V DD2 10 DD1 =2.4V, V =V BN =1.2V, P =14dBm BP in 12 stability factor 9 f =700MHz 0 10 8 f =800MHz 0 f =900MHz 7 0 8 6 Vds (V) stability factor K 1.2 (b) 15 Power gain (dB) 90 5 4 f0=1000MHz 6 4 3 2 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 Frequency (GHz) (e) 4 4.5 5 0 0 0.2 0.4 0.6 Normalized time 0.8 (f) Figure 5.29: Post-layout simulation results of switch-mode operation over broad frequency range. 1 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device V DD2 =4.0V, V DD1 =2.4V, P =14dBm, f =1GHz in VDD2=4.0V, VDD1=2.4V, Pin=14dBm, f0=1GHz 0 3 Vgs (V) 2 14 VBN=VBP=1.0V(d=72.3%) VBN=VBP=1.1V(d=61.6%) VBN=VBP=1.2V(d=55.8%) VBN=VBP=1.3V(d=49.1%) 10 1.5 1 VTH=0.7V 8 6 0.5 4 0 2 −0.5 0 0.2 0.4 0.6 time (ns) VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 12 Vds (V) 2.5 91 0.8 1 0 0 0.2 (a) 0.4 0.6 time (ns) 0.8 1 (b) Figure 5.30: Drive signal waveforms tuning by gate bias voltages of NMOS and PMOS of inverter. the duty-cycle. This agrees very well with the theory shown in [5]. The peak drain efficiency is improved by increasing the duty-cycle because of higher output power. However the fluctuation in drain efficiency for VBN = VBP = 1.0V is larger than that for VBN = VBP = 1.2V. This is because the amplifier is designed for duty cycle d = 56% or VBN = VBP = 1.2V. The required load impedances for d = 72.3% or VBN = VBP = 1.0V are different from that for d = 56% or VBN = VBP = 1.2V. The figure also shows that the amplifier is stable for all different dutycycles. Since the gate bias voltage affects the linear operation, it is necessary to investigate the DC gate bias voltage of ED-NMOS as a function of VBN = VBP . Fig.5.32 shows the relation between the these two voltages. For ED-NMOS, the threshold voltage is about 0.7V, and the maximum linear input voltage is 2.4V. Thus the gate bias voltage for Class-A mode is 1.55V, and 0.7V for Class-B mode. Fig.5.33-5.36 show the simulation results for linear-mode at 0.7GHz, 0.8GHz, 0.9GHz and 1.0GHz. In these figures, one can find that the small-signal power gain is only valid when gate bias voltage is larger than the threshold voltage. The small-signal power gain is about 25dB for VBN = VBP = 1.0V, and 29dB for VBN = VV P = 1.1V. For the same output power, the third-order intermodulation distortion (IMD3) for VBN = VBP = 1.0V is better than other bias voltages, but the drain efficiency is quite low for this bias voltage. Fig.5.37 shows the characteristics at 1dB compression point. It shows that for Class-A or B mode the small-signal power gain is much larger than that of Class-C mode, but the drain efficiency at 1dB compression point is quite low for Class-A or B mode compared with Class-C mode. Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device V DD2 =4.0V, V DD1 92 VDD2=4.0V, VDD1=2.4V, Pin=14dBm =2.4V, P =14dBm in 1 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 29 28 27 0.8 0.7 0.6 26 25 0.6 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.9 Drain Efficiency Output power (dBm) 30 0.7 0.8 0.9 1 Frequency (GHz) 1.1 0.5 0.6 1.2 0.7 0.8 0.9 1 Frequency (GHz) (a) V =4.0V, V DD2 =2.4V, P =14dBm DD1 VDD2=4.0V, VDD1=2.4V, Pin=14dBm in 16 Power gain (dB) Power added efficiency 15 0.6 0.5 0.4 0.2 0.6 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.7 0.8 0.9 1 Frequency (GHz) 1.1 1.2 14 13 12 11 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 10 0.6 0.7 0.8 0.9 1 Frequency (GHz) (c) 1.1 1.2 (d) VDD2=4.0V, VDD1=2.4V, Pin=14dBm VDD2=4.0V, VDD1=2.4V, Pin=14dBm 15 10 13 12 11 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 9 8 stability factor K VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 14 Vdspeak (V) 1.2 (b) 0.7 0.3 1.1 7 6 5 4 3 2 1 10 0.6 0.7 0.8 0.9 1 Frequency (GHz) (e) 1.1 1.2 0 0 0.5 1 1.5 2 2.5 3 3.5 Frequency (GHz) 4 (f) Figure 5.31: Effects of variations of duty-cycle on the performance of switch-mode 4.5 5 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 93 VDD2=4.0V, VDD1=2.4V 2.5 Vgs (V) 2 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 VBN=VBP (V) Figure 5.32: DC static gate-source bias voltage as a function of VBN and VBP . VDD2=4.0V, VDD1=2.4V, f0=0.7GHz V DD2 30 0.9 0.8 20 Drain efficiency Output power (dBm) 25 15 10 5 0 −5 −10 −20 =4.0V, V VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −15 =4.0V, V DD2 0.7 0.6 0.5 0.4 0.3 0.1 10 0 10 15 15 0 0 25 −10 20 −20 15 10 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −30 −40 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −50 −10 −5 0 5 Input power (dBm) (c) 30 VDD2=4.0V, VDD1=2.4V, f0=0.7GHz =2.4V, f =0.7GHz DD1 30 −15 20 25 Output power (dBm) (b) IMD3 (dBc) Power gain (dB) 0 0.2 −10 −5 0 5 Input power (dBm) V 0 −20 =2.4V, f =0.7GHz VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V (a) 5 DD1 1 10 15 −60 10 15 20 25 Output power (dBm) (d) Figure 5.33: Post-layout simulation results of linear-mode operation at 0.7GHz. 30 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device V =4.0V, V =2.4V, f =0.8GHz DD1 VDD2=4.0V, VDD1=2.4V, f0=0.8GHz 0 1 25 0.9 0.8 20 Drain efficiency Output power (dBm) DD2 30 15 10 5 0 −5 −10 −20 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −15 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.7 0.6 0.5 0.4 0.3 0.2 0.1 −10 −5 0 5 Input power (dBm) 10 0 10 15 15 (a) V =4.0V, V DD1 VDD2=4.0V, VDD1=2.4V, f0=0.8GHz =2.4V, f =0.8GHz 0 30 0 25 −10 20 −20 15 10 5 0 −20 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −15 30 (b) IMD3 (dBc) Power gain (dB) DD2 20 25 Output power (dBm) −30 −40 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −50 −10 −5 0 5 Input power (dBm) 10 −60 10 15 15 20 25 Output power (dBm) (c) 30 (d) Figure 5.34: Post-layout simulation results of linear-mode operation at 0.8GHz. VDD2=4.0V, VDD1=2.4V, f0=0.9GHz V DD2 30 0.9 0.8 20 Drain efficiency Output power (dBm) 25 15 10 5 0 −5 −10 −20 =4.0V, V VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −15 0.7 0.6 0.5 0.4 0.3 0.1 10 0 10 15 15 (a) DD1 25 −10 20 −20 15 10 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −10 −5 0 5 Input power (dBm) (c) =4.0V, V DD2 0 0 −15 20 25 Output power (dBm) 30 (b) V =2.4V, f =0.9GHz IMD3 (dBc) Power gain (dB) DD2 =4.0V, V 30 0 −20 0 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.2 −10 −5 0 5 Input power (dBm) V 5 =2.4V, f =0.9GHz DD1 1 DD1 15 0 −30 −40 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −50 10 =2.4V, f =0.9GHz −60 10 15 20 25 Output power (dBm) 30 (d) Figure 5.35: Post-layout simulation results of linear-mode operation at 0.9GHz. 94 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device V Output power (dBm) DD2 =4.0V, V =2.4V, f =1GHz DD1 VDD2=4.0V, VDD1=2.4V, f0=1GHz 0 30 1 25 0.9 0.8 Drain efficiency 20 15 10 5 0 −5 −10 −20 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −15 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.7 0.6 0.5 0.4 0.3 0.2 0.1 −10 −5 0 5 Input power (dBm) 10 0 10 15 15 20 25 Output power (dBm) (a) V =4.0V, V (b) VDD2=4.0V, VDD1=2.4V, f0=1GHz =2.4V, f =1GHz DD1 0 30 0 25 −10 20 −20 IMD3 (dBc) Power gain (dB) DD2 15 10 5 0 −20 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −15 30 −30 −40 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −50 −10 −5 0 5 Input power (dBm) 10 −60 10 15 15 20 25 Output power (dBm) (c) 30 (d) Figure 5.36: Post-layout simulation results of linear-mode operation at 1.0GHz. V =4.0V, V =2.4V VDD2=4.0V, VDD1=2.4V DD1 Input 1dB compression point (dBm) Output 1dB compression point (dBm) DD2 30 28 26 24 22 20 0.7 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.8 0.9 Frequency (GHz) 1 15 10 5 0 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −5 −10 0.7 0.8 0.9 Frequency (GHz) (a) 1 (b) VDD2=4.0V, VDD1=2.4V V =4.0V, V DD2 =2.4V DD1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.7 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.8 0.9 Frequency (GHz) (c) Linear gain @ P1dB (dB) Drain efficiency @ P1dB 30 1 25 20 15 10 VBN=VBP=1.0V VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 5 0 0.7 0.8 0.9 Frequency (GHz) 1 (d) Figure 5.37: Post-layout simulation results of linear-mode operation at 1dB compression point 95 Chapter 5. Broadband Class-E Power Amplifier Design Based Upon ED-NMOS Device 96 5.4 Conclusion In this chapter, the effects of load network and gate bias voltage on the linearity of ED-NMOS were investigated. It shows that the best IMD3 is obtained when the power amplifier is biased at Class-AB mode with RF choke. For the Class-B biasing condition, the finite dc-feed inductance can improve the IMD3 performance. In addition, a systematic design approach for broadband Class-E power amplifier was described, and a broadband Class-E power amplifier based upon an existing CMOS die was implemented from 0.65-1.05GHz. The post-layout simulation results for switch-mode show that the drain efficiency exceeds 75%, output power is larger than 27dBm from a 4.0V supply, and peak drain-source voltage is less than 12.5V. The output power flatness is less than 1dB. Chapter 6 Measurements To verify the performance of the proposed broadband output load network, a broadband Class-E power amplifier was implemented. Fig.6.1 shows a photo of the fabricated PCB of the proposed design. The PCB size is 35×25mm2 . The measurement results will be given in this chapter. 6.1 Test Setup The block diagram of the test setup is shown in Fig.6.2. The one-tone or two-tone signals are generated by Rohde & Schwarz SMIQ with AMIQ to drive the amplifier. The output of the broadband power amplifier is fed to the spectrum analyzer Rohde & Schwarz FSQ. To protect the spectrum analyzer, two 6-dB attenuators were inserted between the amplifier output and FSQ. All the equipments are controlled by the automatic test program in Labview. Figure 6.1: Photograph of implemented broadband Class-E power amplifier 97 Chapter 6. Measurements 98 Figure 6.2: Block diagram of the measurement setup for broadband Class-E power amplifier 6.2 Measurement Results 6.2.1 Comparison of Simulated and Measured Results Fig.6.3 shows the comparison between the simulated and measured output power, power gain, drain efficiency, and power added efficiency (PAE) values against frequency from 500 to 1200MHz. The device is biased at VDD1 = 2.4V, VDD2 = 5.0V, and VBN = VBP = 1.1V at RF input power of 14dBm. Close agreement is achieved between the simulated and measured output power and power gain between 0.6GHz and 1.0GHz. At high frequencies (i.e. 1.1GHz and 1.2GHz), the measured output power is 2dB larger than the simulated results. Fig.6.3(a) shows that the measured bandwidth for ∆Pout < 1dB is wider than the simulation result. But at f0 =1.0GHz, the maximum difference of 8% is found in drain efficiency. The difference between measurement and simulation might be due to the transistor models. The model of ED-NMOS is a first-round model which means the device was only measured and modelled once. The model was not developed after that. The DC I-V measurement shown in Fig.5.4 also implies that the ED-NMOS model in Cadence Library is different from the fabricated one. Besides the transistor model, the inaccurately modelled bondwires might also contribute to the difference, especially at high frequencies. Chapter 6. Measurements V DD2 =5.0V, V DD1 99 =2.4V, V =V BN =1.1V, P =14dBm BP V in DD2 32 Simulation Measurement DD1 30 29 28 BN =1.1V, P =14dBm BP in 16 15 14 13 27 0.5 0.6 0.7 0.8 0.9 1 Frequency (GHz) 1.1 Simulation Measurement 12 0.5 1.2 0.6 (a) 0.7 0.8 0.9 1 Frequency (GHz) 1.1 1.2 (b) VDD2=5.0V, VDD1=2.4V, VBN=VBP=1.1V, Pin=14dBm VDD2=5.0V, VDD1=2.4V, VBN=VBP=1.1V, Pin=14dBm 0.7 Simulation Measurement 0.9 0.8 0.7 0.6 Power added efficiency 1 Drain efficiency =2.4V, V =V 17 31 Power gain (dB) Output power (dBm) =5.0V, V 18 0.6 0.5 0.4 Simulation Measurement 0.5 0.5 0.6 0.7 0.8 0.9 1 Frequency (GHz) 1.1 1.2 0.3 0.5 0.6 (c) 0.7 0.8 0.9 1 Frequency (GHz) 1.1 1.2 (d) Figure 6.3: Comparison of simulated and measured performance of the proposed broadband Class-E PA as a function of frequency: (a) output power, (b) power gain, (c) drain efficiency, (d) power added efficiency. We only know the rough length of the bondwires, and do not know the height of the bondwires. This might lead to that difference. Measured output power indicates the flat characteristic associated with broadband design from 560MHz to 1050MHz, at a value of 30.5±0.5dBm. A power gain of between 16-17dB has been observed over the frequency band 560MHz to 1050MHz. The drain efficiency and PAE remain above 67% and 52% across the same bandwidth. The peak drain efficiency of 77% and peak PAE of 65% are measured at 700MHz with 31dBm output power. The fluctuations in drain efficiency and PAE over a bandwidth of 490MHz are less than 13%. Therefore the measured bandwidth1 for this CMOS Class-E power amplifier is about 60.9% with Pout ≥ 30dBm, η ≥ 67%, and PAE ≥ 52%. Since the equipment for the waveform measurement is not available for us at this moment, the drain voltage waveforms cannot be shown here. 1 Bandwidth: the frequency range for which the variation in the output power is less than 1.0dB. Chapter 6. Measurements 100 Table 6.1: Comparison broadband Class-E PAs Specifications Frequency [GHz] Bandwidth [%] Pout [dBm] ∆Pout [dB] Power Gain [dB] Drain Efficiency [%] PAE [%] PAE peak [%] Technology Topology Y. Qin 2005[42] 0.54-0.89 48.9 > 20 < 2.5 > 8.0 N.A. > 50 66.5 PHMET Single-stage D.Y.C. Lie 2006[11] 0.5-1.2 82.3 > 17.2 < 3.0 > 7.2 N.A. > 50 70 SiGe Single-stage J. Jang 2007[41] 0.8-0.94 16.1 > 31 < 0.5 > 30 N.A. > 55 62 CMOS Two-stage A.A. Tanany 2009[12] 0.6-1.0 50 > 45.2 < 1.7 > 10 > 66 > 62 80.6 GaN Single-stage This Work 2010 0.56-1.05 60.9 > 30 < 1.0 > 16 > 67 > 52 65 CMOS Two-stage Table 6.2: Comparison CMOS Class-E PAs Specifications Frequency [MHz] VDD [V] Pout [dBm] Power Gain [dB] Drain Efficiency [%] PAE [%] Technology Topology C. Yoo 2001[43] 900 1.8 29.5 N.A. 46 41 K.Mertens 2002[44] 700 2.2 30.0 18 N.A. 62 J. Ramos 2005[45] 855 2.3 30.0 20 67 66 J. Jang 2007[41] 875 3.3 31.7 30.3 N.A. 62 This Work 2010 700 5.0 31.0 17 77 65 0.25µm CMOS 0.35µm CMOS 0.35µm CMOS 0.18µm CMOS 65nm CMOS Two-stage Two-stage Two-stage Two-stage Two-stage single-ended PA differential PA differential PA differential PA single-ended PA Table 6.1 summarizes the published broadband Class-E power amplifiers around 1.0GHz. Compared with PHMET and SiGe technologies, this CMOS power amplifier can deliver higher output power because the breakdown voltage of the extended-drain NMOS is much higher. High supply voltage of 5.0V is applied to the final stage. Compared with the CMOS power amplifier in [41], the bandwidth of this work is much wider than that one. The peak PAE is less than the GaN power amplifier in [12]. However, the output power, drain efficiency and PAE of this work is relatively flat across a very broad frequency range. In Table 6.2, the performance of the proposed Class-E power amplifier is compared with that of other power amplifiers in CMOS technology at a single frequency. Since the purpose of this design is to implement a broadband Class-E PA, we designed a load network which has a relatively flat impedance over a broad frequency band although the magnitude of load impedance is large. In [39], Acar has already shown that 4W output power can be obtained with 70% PAE at 2.0GHz by using ED-NMOS device. Therefore, there is no doubt that when using the EDNMOS device to design a Class-E power amplifier higher output power could be achieved at a single frequency by using lower load impedance. Chapter 6. Measurements V =5.0V, V DD1 =2.4V, P =14dBm V in DD2 32 18 31 17 Power gain (dB) Output power (dBm) DD2 101 30 29 28 27 26 0.5 VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.6 1.1 VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.6 0.7 0.8 0.9 1 Frequency (GHz) 1.1 1.2 (b) VDD2=5.0V, VDD1=2.4V, Pin=14dBm VDD2=5.0V, VDD1=2.4V, Pin=14dBm 0.7 VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.9 0.8 0.7 0.6 0.6 0.7 0.8 0.9 1 Frequency (GHz) 1.1 1.2 (c) Power added efficiency 1 Drain efficiency in 14 (a) 0.5 0.5 =2.4V, P =14dBm 15 12 0.5 1.2 DD1 16 13 0.7 0.8 0.9 1 Frequency (GHz) =5.0V, V 0.6 0.5 0.4 0.3 0.5 VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.6 0.7 0.8 0.9 1 Frequency (GHz) 1.1 1.2 (d) Figure 6.4: Broadband measurement of dynamic inverter gate bias of Class-E PA: (a) output power, (b) power gain, (c) drain efficiency, (d) power added efficiency. 6.2.2 Dynamic Inverter Gate Bias In chapter 5, the effects of variations of inverter gate bias voltage has been studied in simulation. Fig.6.4 shows the measured results of variations of VBN = VBP from 1.1V to 1.3V. From Fig.5.32, one can observe that the gate bias voltage of ED-NMOS increases as the gate bias voltages (VBN and VBP ) of inverter decrease. Thus the device can deliver more output power to the load as the gate bias of inverter decreases. One can adjust the output power level by tuning the gate bias voltages of inverter. The fluctuation of efficiency between 500 to 1100MHz for these three bias voltages are relatively small. Fig.6.5 shows the output power, drain efficiency, and PAE as a function of input power at 900MHz for different gate bias voltages of inverter. It is apparent that the small-signal power gain only exists when the power amplifier is biased at Class-A or Class-AB mode. When the power amplifier is driven into switch-mode, the drain efficiency and PAE are less sensitive to the gate bias voltages. Chapter 6. Measurements 102 VDD2=5.0V, VDD1=2.4V, Freq.=0.9GHz 25 VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 25 Power gain (dB) Output power (dBm) 30 VDD2=5.0V, VDD1=2.4V, Freq.=0.9GHz 30 20 15 10 15 10 5 5 0 −20 20 −15 −10 −5 0 5 Input power (dBm) 10 0 −20 15 VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V −15 −10 −5 0 5 Input power (dBm) (a) V DD2 =5.0V, V =2.4V, Freq.=0.9GHz V DD1 DD2 VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.9 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 −20 =5.0V, V =2.4V, Freq.=0.9GHz DD1 1 Power added efficiency Drain efficiency 0.8 15 (b) 1 0.9 10 0.8 VBN=VBP=1.1V VBN=VBP=1.2V VBN=VBP=1.3V 0.7 0.6 0.5 0.4 0.3 0.2 0.1 −15 −10 −5 0 5 Input power (dBm) (c) 10 15 0 −20 −15 −10 −5 0 5 Input power (dBm) 10 15 (d) Figure 6.5: Measured RF input power sweep at 0.9GHz with inverter gate bias as a parameter: (a) output power, (b) power gain, (c) drain efficiency, (d) power added efficiency. 6.2.3 Dynamic Supply Voltage for ED-NMOS and Inverter For an envelope tracking amplifier, the average efficiency is improved by dynamically modulating the supply voltage of power amplifier. Fig.6.6 shows the output power, drain efficiency, and power added efficiency as a function of supply voltage (VDD2 ) of ED-NMOS across 500MHz to 1200MHz. The supply voltage of inverter is fixed at 2.4V, and the RF input power is also fixed at 14dBm. One can observe that when the supply voltage decreases from 5.0V to 1.0V, a 12dB output power drop is associated with that variation. The drain efficiency is quite tolerant to the changes of VDD2 . However, the power added efficiency decreases linearly as the supply voltage VDD2 decreases. To improve PAE at power back-off, supply modulation is applied to both of ED-NMOS and inverter. Fig.6.7 plots the output power at 0.9GHz as a function of supply voltage VDD2 of ED-NMOS with supply voltage VDD1 of inverter as a parameter. VDD2 changes from 1.0V to 5.0V. Meanwhile, VDD1 changes from 1.6V to 2.4V. A power variation of 16dB is found in Chapter 6. Measurements V DD1 =2.4V, V =V BN 103 V =1.1V, P =14dBm BP =2.4V, V =V DD1 in BN =1.1V, P =14dBm BP in 1 32 0.9 0.8 Drain efficiency Output power (dBm) 28 24 20 16 VDD2=1.0V VDD2=2.0V VDD2=3.0V VDD2=4.0V VDD2=5.0V 12 8 0.5 0.6 0.7 0.8 0.9 1 Frequency (GHz) 1.1 0.7 0.6 0.5 0.4 0.3 VDD2=1.0V VDD2=2.0V VDD2=3.0V VDD2=4.0V VDD2=5.0V 0.2 0.1 1.2 0 0.5 0.6 0.7 0.8 0.9 1 Frequency (GHz) (a) 1.1 1.2 (b) VDD1=2.4V, VBN=VBP=1.1V, Pin=14dBm 1 VDD2=1.0V VDD2=2.0V VDD2=3.0V VDD2=4.0V VDD2=5.0V Power added efficiency 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.5 0.6 0.7 0.8 0.9 1 Frequency (GHz) 1.1 1.2 (c) Figure 6.6: Broadband measurement of dynamic supply voltage for ED-NMOS: (a) output power, (b) drain efficiency, (c) power added efficiency. that figure. The corresponding drain efficiency and PAE against the output power are shown in Fig.6.8. From Fig.6.8(b), one can observe that the PAE can be improved by decreasing VDD1 for low output power. For example, the PAE is increased by 27% at output power of 18dBm when decreasing VDD1 from 2.4V to 1.6V. Fig.6.9 plots the drain efficiency and PAE for the optimum supply voltages of ED-NMOS and inverter for different output power. It shows that the PA exhibits a 45% PAE and a 68% drain efficiency at 10dB power back-off from 30.2dBm at 0.9GHz. Fig.6.10 shows the drain efficiency and PAE against the output power for optimum supply voltages at other frequencies. It shows the PAE exceeds 40% at 10dB power back-off across 500MHz to 1100MHz. 6.2.4 Third-Order Intermodulation Distortion The linearity of the proposed power amplifier is tested by feeding two-tone signals into the power amplifier and measuring the third-order intermodulation distortion (IMD3). Fig.6.11 shows the Chapter 6. Measurements 104 V =V BN =1.1V, P =14dBm, Freq.=0.9GHz BP in 32 Output power (dBm) 30 28 26 24 22 20 VDD1=1.6V VDD1=1.8V VDD1=2.0V VDD1=2.2V VDD1=2.4V 18 16 14 1 1.5 2 2.5 3 3.5 VDD2 (V) 4 4.5 5 Figure 6.7: Measured output power as a function of VDD2 at 900MHz with VDD1 as a parameter. VBN=VBP=1.1V, Pin=14dBm, Freq.=0.9GHz VBN=VBP=1.1V, Pin=14dBm, Freq.=0.9GHz 1 0.9 0.9 Power added efficiency 1 0.7 0.6 0.5 0.4 0.3 VDD1=1.6V VDD1=1.8V VDD1=2.0V VDD1=2.2V VDD1=2.4V 0.2 0.1 0 16 18 20 22 24 26 28 Output power (dBm) 30 0.8 0.7 0.6 0.5 0.4 0.3 VDD1=1.6V VDD1=1.8V VDD1=2.0V VDD1=2.2V VDD1=2.4V 0.2 0.1 32 0 16 18 20 22 24 26 28 Output power (dBm) (a) 30 (b) Figure 6.8: Efficiency against output power for the supply modulation shown in Fig.6.7: (a) drain efficiency vs.Pout, (b) PAE vs. Pout. VBN=VBP=1.1V, Pin=14dBm, Freq.=0.9GHz 1 0.9 V =2.0VV =2.4V VDD1=1.8V V =1.8VVDD1=4.0VVDD1=4.0V DD1 DD2 DD2 V =3.5V VDD2=2.5V DD2 0.8 ↓ ↓ ↓ 0.7 Efficiency Drain efficiency 0.8 0.6 ↑ 0.5 0.4 0.3 0.2 ↓ ↑ VDD1=1.6V V =2.0V ↑ VDD1=1.6V DD2 VDD2=1.5V Drain efficiency PAE 0.1 0 16 ↑ V =1.8V ↑ VDD1=1.8V VDD1=4.0V V =2.2VV ↑ =2.4V DD1 VDD2=3.0V DD2 VDD2=4.0V DD1 VDD2=5.0V 18 20 22 24 26 28 Output power (dBm) 30 32 Figure 6.9: Measured drain efficiency and PAE with optimum supplies of ED-NMOS and Inverter. 32 Chapter 6. Measurements V =V =1.1V, P =14dBm, Freq.=0.5GHz BP V in 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.5 0.4 0.3 =1.1V, P =14dBm, Freq.=0.6GHz BP 0.6 0.5 0.4 0.2 Drain efficiency PAE 0.1 18 20 22 24 26 28 Output power (dBm) 30 Drain efficiency PAE 0.1 0 16 32 18 20 (a) 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.5 0.4 0.3 32 0.6 0.5 0.4 0.3 0.2 0.2 Drain efficiency PAE 0.1 18 20 22 24 26 28 Output power (dBm) 30 Drain efficiency PAE 0.1 0 16 32 18 20 (c) 22 24 26 28 Output power (dBm) 30 32 (d) VBN=VBP=1.1V, Pin=14dBm, Freq.=1.0GHz VBN=VBP=1.1V, Pin=14dBm, Freq.=1.1GHz 1 1 0.9 0.9 0.8 0.8 0.7 0.7 Efficiency Efficiency 30 VBN=VBP=1.1V, Pin=14dBm, Freq.=0.8GHz 1 Efficiency Efficiency VBN=VBP=1.1V, Pin=14dBm, Freq.=0.7GHz 0.6 0.5 0.4 0.3 0.6 0.5 0.4 0.3 0.2 0.2 Drain efficiency PAE 0.1 0 16 22 24 26 28 Output power (dBm) (b) 1 0 16 in 0.3 0.2 0 16 =V BN 1 Efficiency Efficiency BN 105 18 20 22 24 26 28 Output power (dBm) (e) 30 32 Drain efficiency PAE 0.1 0 16 18 20 22 24 26 28 Output power (dBm) 30 (f) Figure 6.10: Measured drain efficiency and PAE versus output power for the optimum supply voltages of ED-NMOS and Inverter at: (a) 0.5GHz, (b) 0.6GHz, (c) 0.7GHz, (d) 0.8GHz, (e) 1.0GHz, and (f) 1.1GHz. 32 Chapter 6. Measurements 106 V =5.0V, V DD2 =2.4V, Freq.=0.9GHz DD1 0 IMD3 (dBc) −10 −20 −30 −40 VBN=VBP=1.10V VBN=VBP=1.12V VBN=VBP=1.14V VBN=VBP=1.16V VBN=VBP=1.18V VBN=VBP=1.20V −50 −60 0 5 10 15 20 25 Total output power (dBm) 30 Figure 6.11: Measured IMD3 with VBN=VBP as a parameter at 0.9GHz measured IMD3 at 0.9GHz as a function of total two-tone signal output power with gate bias of the inverter as a parameter. When the gate bias voltages (VBN and VBP ) of inverter increases from 1.1V to 1.2V, the gate bias voltage of ED-NMOS decreases to or under the threshold voltage, which has been shown in Fig.5.32. Thus, the device becomes a strong non-linear amplifier so that the IMD3 performance gets worse. The optimum IMD3 of -30dBc for Pout = 25dBm is obtained at VBN = VBP =1.12V. The IMD3, drain efficiency, and PAE versus total output power for Class-AB mode are shown in Fig.6.12 across 500MHz to 1200MHz. One can observe that the efficiency is less than 20% for IMD<-30dBc. To improve the linearity and efficiency, an advanced transmitter architecture, such as ET, LINC, or Doherty, should be implemented. 6.3 Conclusion In this chapter, the measurement of the proposed broadband CMOS Class-E power amplifier was done. The measured results are close to the simulation. The measurement showed that the amplifier, with a 5.0V supply for ED-NMOS, 2.4V supply for inverter, 1.1V gate bias for inverter, and 14dBm RF input power, was capable of delivering more than 30dBm output power with η ≥ 67% and PAE ≥ 52% over the band 560MHz to 1050MHz. The flatness of output power is less than 1.0dB, and the fluctuations in drain efficiency and PAE are less than 13% over the same band. The measurement also indicated that the output power, power gain and PAE can be improved by increasing the gate bias voltage of ED-NMOS through decreasing the gate bias of inverter. To understand the performance at power back-off, the supply voltages of EDNMOS and inverter were modulated. The measurement showed more than 40% PAE and 60% drain efficiency can be achieved at 10dB power back-off over the band 500MHz to 1100MHz. IMD3 measurement showed that the drain efficiency is less than 25% for Pout = 25dBm with I MD3 < −25dBc across the same frequency band. Chapter 6. Measurements =1.1V, Freq.=0.5GHz Drain efficiency PAE =2.4V, V =V DD1 0.6 IMD3 Drain efficiency PAE −20 0.4 −20 0.4 −30 0.3 −30 0.3 −40 0.2 −40 0.2 −50 0.1 −50 0.1 14 16 18 20 22 Total output power (dBm) 24 IMD3 (dBc) −10 0 26 −60 12 14 16 18 20 22 Total output power (dBm) (a) V =5.0V, V DD2 DD1 BN =1.1V, Freq.=0.7GHz BP Drain efficiency PAE =5.0V, V DD2 =2.4V, V =V DD1 BN 0 26 =1.1V, Freq.=0.8GHz BP 0.6 0 IMD3 Drain efficiency PAE −10 −20 0.4 −20 0.4 −30 0.3 −30 0.3 −40 0.2 −40 0.2 −50 0.1 −50 0.1 −60 12 14 16 18 20 22 Total output power (dBm) 24 IMD3 (dBc) 0.5 Efficiency −10 IMD3 (dBc) V 0.6 IMD3 24 0.5 (b) =2.4V, V =V 0 0 26 −60 12 14 (c) Drain efficiency PAE 0 26 0.6 0 IMD3 Drain efficiency PAE −10 −20 0.4 −20 0.4 −30 0.3 −30 0.3 −40 0.2 −40 0.2 −50 0.1 −50 0.1 −60 12 14 16 18 20 22 Total output power (dBm) 24 IMD3 (dBc) 0.5 Efficiency −10 24 VDD2=5.0V, VDD1=2.4V, VBN=VBP=1.1V, Freq.=1.0GHz 0.6 0 IMD3 16 18 20 22 Total output power (dBm) 0.5 (d) VDD2=5.0V, VDD1=2.4V, VBN=VBP=1.1V, Freq.=0.9GHz IMD3 (dBc) =1.1V, Freq.=0.6GHz BP 0.5 −60 12 0 26 −60 12 14 (e) Drain efficiency PAE 0 26 0.6 0 IMD3 Drain efficiency PAE −10 −20 0.4 −20 0.4 −30 0.3 −30 0.3 −40 0.2 −40 0.2 −50 0.1 −50 0.1 −60 12 14 16 18 20 22 Total output power (dBm) (g) 24 0 26 IMD3 (dBc) 0.5 Efficiency −10 24 VDD2=5.0V, VDD1=2.4V, VBN=VBP=1.1V, Freq.=1.2GHz 0.6 0 IMD3 16 18 20 22 Total output power (dBm) 0.5 (f) VDD2=5.0V, VDD1=2.4V, VBN=VBP=1.1V, Freq.=1.1GHz IMD3 (dBc) BN 0 Efficiency −10 =5.0V, V DD2 0.6 IMD3 IMD3 (dBc) V BP Efficiency BN Efficiency =2.4V, V =V DD1 Efficiency =5.0V, V DD2 0 −60 12 14 16 18 20 22 Total output power (dBm) 24 0.5 Efficiency V 107 0 26 (h) Figure 6.12: Measured IMD3, drain efficiency and PAE versus output power at: (a) 0.5GHz, (b) 0.6GHz, (c) 0.7GHz, (d) 0.8GHz, (e) 0.9GHz, (f) 1.0GHz, (g) 1.1GHz, and (h) 1.2GHz. Chapter 7 Conclusions and Future Work 7.1 Conclusions This project focused on analyzing the performance of an RF power amplifier with a Class-E like load for linear and switching operation. Meanwhile, the broadband characteristics of Class-E power amplifier is another subject. To understand the fundamental principles of the Class-E power amplifier, an analytical approach based upon mathematical derivations was applied to the conventional Class-E circuit. The non-ideal switch resistance, finite dc-feed inductance, finite loaded quality factor, and arbitrary switch duty-cycle were all taken into account to give a closed-form solution for the Class-E power amplifier. The mathematical derivations also take into account the different operation modes, such as variable voltage and variable slope. From the analytical solution, the required load impedances at fundamental and harmonic frequencies were obtained. The influence of the load impedance variation was studied. It shows that the load phase angle at fundamental frequency is the most important parameter to design. The amplifier is sensitive to that parameter. In addition, the broadband characteristics of the conventional ClassE power amplifier were discussed. Since the load phase angles of fundamental frequencies increase very fast as frequency varies, the conventional Class-E output load network cannot operate over a very broad frequency range (∆B > 40%). Other topologies have to be used for the broadband applications. To understand the impact of a non-ideal drive signal on the switched operation, numerical methods to represent the transistor were implemented. The simulation shows that the amplifier with finite dc-feed inductance is quite tolerant to the non-ideal drive signal. For 20% rise and fall times, the drain efficiecny is only degraded by 5% for q = 1.81, while for the RF choke this degradation is more than 10%. The developed transistor model was also used to analyze the linear operation of the amplifier. It showed that the gate bias voltage determines the power gain and drain efficiency when the amplifier is driven into 1dB compression point. 109 Chapter 7. Conclusions and Future Work 110 To analyze the linearity of the Class-E power amplifier when operating in the linear mode, a realistic compact CMOS transistor model (extended-drain NMOS) was used. The results indicated that for the Class-AB operation mode, the power amplifier with the RF choke has the best linearity or highest third-order intermodulation distortion suppression. As the gate bias voltage moves to Class-B operation, the power amplifier with finite dc-feed inductance can provide a similar IMD3 performance as the RF choke does. In addition, a broadband Class-E power amplifier based upon this CMOS device was designed and implemented to verify the developed systematic design approach. The measurements indicated a good broadband output power performance in the 560-1050MHz band, for which the output power is larger than 30dBm and output power variation is less than 1dB. The drain efficiency is between 67% and 77% and PAE is between 52% and 65% over the same band. When using the dynamic voltage supply for the ED-NMOS and inverter, the PA achieves a PAE of 40% and a drain efficiency of 60% at 10dB power back-off over the band 500MHz to 1100MHz. The IMD3 measurement shows the PA cannot provide an acceptable efficiency when requiring an IMD3 less than -30dBc. Clearly here a trade-off exists between the linearity and efficiency. To improve at this point, We could apply the envelope tracking, LINC or Doherty transmitter to achieve high efficiency and good linearity simultaneously. 7.2 Recommendations for Future Work • In chapter 5 and 6, one can observe that the power added efficiency for this device is not very good compared with the achieved drain efficiency. This is due to the large power consumption of inverter. To improve at this point, a low-power inverter should be developed. • To perform the digital pre-distortion, the memory effects and AM-AM and AM-PM conversion in this non-linear device should be studied. The impact of the finite dc-feed in- ductance on the memory effects and AM-PM conversion should be discussed. • In [46], M. v. Schie had designed the broadband power combining network for the outphasing amplifier based upon Class-E power amplifier. In that work, the power combining network has broadband characteristics. If the output load network for each branch ClassE power amplifier is also broadband, the frequency response of the whole outphasing amplifier will be more reasonable. Appendix A Maple Code for Analytical Analysis In this appendix the Maple code is shown for analytical analysis of conventional Class-E power amplifier introduced in chapter 3. restart : Digits :=10: with(plots ): with( DiscreteTransforms ): Counter :=0: NP :=41: Vdd :=’Vdd ’: q:=’q’: omega :=’omega ’: d:=’d’: p:=’p’: phi :=’phi ’: mon :=’mon ’: Con1 :=’Con1 ’: Con2 :=’Con2 ’: Coff1 :=’Coff1 ’: Coff2 :=’Coff2 ’: for j from 1 by 1 to NP do tvcon (j):=0: tvcoff (j):=0: tison (j):=0: tisoff (j):=0: ticon (j):=0: 111 Appendix. Maple Code for Analytical Analysis 112 ticoff (j):=0: tiron (j):=0: tiroff (j):=0: tilon (j):=0: tiloff (j):=0: ton(j):=0: toff(j):=0: od: ### Analytical solution for ideal Class -E power amplifier ( infinite loaded quality factor ) ### 2nd -order differential equations for ideal Class -E power amplifier in time - domain . ### Vcon(t) and Vcoff (t) are switch voltage at ON and OFF time intervals . #eqn [1]:= diff(x(t),t$2)+( omega /mon)*diff(x(t),t) -(Vdd -x(t))*qˆ2* omega ˆ2-p*Vdd*qˆ2* omega ˆ2* cos(omega *t+phi): # dsolve (eqn [1] ,x(t)): aon :=(1/2) *( -1+ sqrt (1 -4*qˆ2* mon ˆ2))/mon: bon := -(1/2) *(1+ sqrt (1 -4*qˆ2* mon ˆ2))/mon: Vcon(t):= Con1*exp(aon* omega *t)+Con2*exp(bon* omega *t)+Vdd+Vdd *(p*qˆ2* mon ˆ2*(q -1) *(q+1)* cos( omega *t+phi)+p*sin(omega *t+phi)*mon*qˆ2) /(1+( qˆ4 -2*q ˆ2+1) *mon ˆ2): #eqn [2]:= diff(y(t),t$2)+( omega /moff)*diff(y(t),t) -(Vdd -y(t))*qˆ2* omega ˆ2-p*Vdd*qˆ2* omega ˆ2* cos(omega *t+phi): # dsolve (eqn [2] ,y(t)): aoff :=(1/2) *( -1+ sqrt (1 -4*qˆ2* moff ˆ2))/moff: boff := -(1/2) *(1+ sqrt (1 -4*qˆ2* moff ˆ2))/moff: Vcoff (t):= Coff1 *exp(aoff*omega *t)+Coff2 *exp(boff*omega *t)+Vdd+Vdd *(p*qˆ2* moff ˆ2*(q -1) *(q+1)*cos(omega *t+phi)+p*sin( omega *t+phi)*moff*qˆ2) /(1+( qˆ4 -2*qˆ2+1) *moff ˆ2): ### using inductor current and capacitor voltage continuities at turn -on moment , we can find the Con1 ,Con2 in terms of p,q,phi ,d,omega ,mon ,moff ,alpha ,k. eqn1 := subs(t=0, Vcon(t))-alpha *Vdd: eqn2 := subs(t=0 ,(1/(p*Vdd*qˆ2* omega ))*diff(Vcon(t),t)+ alpha *Vdd /(p*Vdd*qˆ2* mon)-sin( omega *t+phi))-subs(t=2* Pi/omega ,( omega *Vdd*k/(p*Vdd*qˆ2* omega ))+alpha *Vdd /(p*Vdd*q ˆ2* moff)-sin( omega *t+phi)): sm1 := solve ({eqn1 ,eqn2 },{Con1 ,Con2 }): assign (sm1): Appendix. Maple Code for Analytical Analysis 113 ### using Class -E contidions at turn -off moment , we can find the Coff1 , Coff2 in terms of p,q,phi ,d,omega ,mon ,moff ,alpha ,k. eqn3 := subs(t=2* Pi/omega , Vcoff (t))-alpha *Vdd: eqn4 := subs(t=2* Pi/omega ,diff(Vcoff (t),t))-omega *Vdd*k: sm2 := solve ({eqn3 ,eqn4 },{Coff1 , Coff2 }): assign (sm2): ### using inductor current and capacitor voltage continuities at turn -off moment , we can find the p,phi in terms of q,d,omega ,mon , moff ,alpha ,k. eqn5 := subs(t=d*Pi/omega ,Vcon(t))-subs(t=d*Pi/omega ,Vcoff (t)): ILond := subs(t=d*Pi/omega ,diff(Vcon(t),t)/(p*Vdd*qˆ2* omega )+Vcon(t)/(p*Vdd*qˆ2* mon)-sin ( omega *t+phi)): ILoffd := subs(t=d*Pi/omega ,diff(Vcoff (t),t)/(p*Vdd*qˆ2* omega )+Vcoff (t)/(p*Vdd*qˆ2* moff) -sin(omega *t+phi)): eqn6 := ILond - ILoffd : ### express p and phi in terms of q,d,omega ,mon , moff ,alpha ,k. g1 := collect ( expand (eqn5) ,{p,sin(phi),cos(phi)}): g2 := coeff (g1 ,p ,1): a1 := coeff (g2 ,sin(phi)): b1 := coeff (g2 ,cos(phi)): c1 := coeff (g1 ,p ,0): g3 := collect ( expand (eqn6*p) ,{p,sin(phi),cos(phi)}): g4 := coeff (g3 ,p ,1): a2 := coeff (g4 ,sin(phi)): b2 := coeff (g4 ,cos(phi)): c2 := coeff (g3 ,p ,0): f [1]:= x*( ta1*sin(y)+tb1*cos(y))+tc1: f [2]:= x*( ta2*sin(y)+tb2*cos(y))+tc2: sm3 := solve ({f[1] ,f[2]} ,{x,y}): assign (sm3): ### set the values for input parameters Vdd , omega , d, q, mon , moff , alpha , k, loaded quality factor . Counter := Counter +1: Vdd :=1: omega :=1: Appendix. Maple Code for Analytical Analysis 114 d:=1: q :=1.412: mon :=0.01: moff :=1000: alpha :=0: k:=0: LoadedQ :=2: ### calculate the values of p and phi. ta1 := Re(evalf (a1)): tb1 := Re(evalf (b1)): tc1 := Re(evalf (c1)): ta2 := Re(evalf (a2)): tb2 := Re(evalf (b2)): tc2 := Re(evalf (c2)): tp := allvalues (x): tphi := allvalues (y): if Re(tp [1]) >0 then p:=Re(tp [1]): phi := Re(tphi [1]): elif Re(tp [2]) >0 then p:=Re(tp [2]): phi := Re(tphi [2]): end if: TCon1 := eval(Con1): TCon2 := eval(Con2): TCoff1 := eval( Coff1 ): TCoff2 := eval( Coff2 ): ### numerically express the switch voltage Vcon(t) and Vcoff (t). TVcon (t):= TCon1 *exp(aon* omega *t)+ TCon2 *exp(bon* omega *t)+Vdd+Vdd *(p*qˆ2* mon ˆ2*(q -1) *(q +1)*cos(omega *t+phi)+p*sin( omega *t+phi)*mon*qˆ2) /(1+( qˆ4 -2*qˆ2+1) *mon ˆ2): TVcoff (t):= TCoff1 *exp(aoff* omega *t)+ TCoff2 *exp(boff*omega *t)+Vdd+Vdd *(p*qˆ2* moff ˆ2*(q -1) *(q+1)*cos(omega *t+phi)+p*sin( omega *t+phi)*moff*qˆ2) /(1+( qˆ4 -2*qˆ2+1) *moff ˆ2): ### calculate the ideal drain efficiency and design set K. pswitch := int( TVcon (t)ˆ2/ mon ,t=0..d*Pi/ omega )+int( TVcoff (t)ˆ2/ moff ,t=d*Pi/ omega ..2* Pi/ omega ): pdc := Vdd *( int(TVcon (t)/mon ,t=0..d*Pi/omega )+int( TVcoff (t)/moff ,t=d*Pi/ omega ..2* Pi/ omega )): Appendix. Maple Code for Analytical Analysis 115 Idc := Re (( omega /(2* Pi)*( int( TVcon (t)/mon ,t=0..d*Pi/ omega )+int( TVcoff (t)/moff ,t=d*Pi/ omega ..2* Pi/omega )))): Tpswitch := Re( evalf ( pswitch )): Tpdc :=Re(evalf (pdc)): ieff :=1 - Tpswitch /Tpdc; inton1 := int( TVcon (t),t=0..d*Pi/omega ): inton2 := int( TVcon (t)ˆ2,t=0..d*Pi/ omega ): intoff1 := int( TVcoff (t),t=d*Pi/ omega ..2* Pi/ omega ): intoff2 := int( TVcoff (t)ˆ2,t=d*Pi/omega ..2* Pi/ omega ): kl := Re((p*Vdd*q)ˆ2* Pi /( omega *(( inton1 *Vdd/mon - inton2 /mon)+( intoff1 *Vdd/moff - intoff2 / moff)))); kc :=1/( qˆ2* kl); kp :=p ˆ2/(2* kl ˆ2); vr := int(TVcon (t)*sin( omega *t+phi),t=0..d*Pi/ omega )+int( TVcoff (t)*sin(omega *t+phi),t=d* Pi/omega ..2* Pi/omega ): vx := int(TVcon (t)*cos( omega *t+phi),t=0..d*Pi/ omega )+int( TVcoff (t)*cos(omega *t+phi),t=d* Pi/omega ..2* Pi/omega ): kx := Re(vx/vr); mr := evalf (kc/mon); # mr:=R/Ron: if evalf (kx) >=0 then QL := evalf ( LoadedQ +kx): QC := evalf ( LoadedQ ): elif evalf (kx) <0 then QL := evalf ( LoadedQ ): QC := evalf (LoadedQ -kx): end if: T:=2* Pi/omega : td :=d*T/2: ### Solve the 4th - order differential equations for Class -E power amplifier with finite loaded quality factor . # constants in the differential equations Ca1 :=’Ca1 ’: Cb1 :=’Cb1 ’: Appendix. Maple Code for Analytical Analysis 116 Cc1 :=’Cc1 ’: Cd1 :=’Cd1 ’: Ca2 :=’Ca2 ’: Cb2 :=’Cb2 ’: Cc2 :=’Cc2 ’: Cd2 :=’Cd2 ’: ca1 :=’ca1 ’: cb1 :=’cb1 ’: cc1 :=’cc1 ’: cd1 :=’cd1 ’: ca2 :=’ca2 ’: cb2 :=’cb2 ’: cc2 :=’cc2 ’: cd2 :=’cd2 ’: sa1 :=’sa1 ’: sb1 :=’sb1 ’: sc1 :=’sc1 ’: sd1 :=’sd1 ’: se1 :=’se1 ’: sf1 :=’sf1 ’: sa2 :=’sa2 ’: sb2 :=’sb2 ’: sc2 :=’sc2 ’: sd2 :=’sd2 ’: se2 :=’se2 ’: sf2 :=’sf2 ’: sa1 :=( QL/QC) *(1/( omega ˆ4*qˆ2)): sb1 :=( QL/QC)*(1/ omega ˆ3) *(1/( qˆ2* mon))+1/( QC* omega ˆ3*qˆ2): sc1 :=1/( QC*omega ˆ2*qˆ2* mon)+1/( omega ˆ2*qˆ2) +1/( omega ˆ2*qˆ2* QC*mr*mon)+( QL/QC)*(1/ omega ˆ2): sd1 :=1/( QC*omega )+1/( omega *qˆ2* mon): se1 :=1: sf1 :=- Vdd: sa2 :=( QL/QC) *(1/( omega ˆ4*qˆ2)): sb2 :=( QL/QC)*(1/ omega ˆ3) *(1/( qˆ2* moff))+1/( QC*omega ˆ3*qˆ2): sc2 :=1/( QC*omega ˆ2*qˆ2* moff)+1/( omega ˆ2*qˆ2) +1/( omega ˆ2*qˆ2* QC*mr*mon)+(QL/QC)*(1/ omega ˆ2): Appendix. Maple Code for Analytical Analysis 117 sd2 :=1/( QC*omega )+1/( omega *qˆ2* moff): se2 :=1: sf2 :=- Vdd: S11 := fsolve (sa1*_Z ˆ4+ sb1*_Z ˆ3+ sc1*_Z ˆ2+ sd1*_Z+se1 , _Z , complex ): ca1 := S11 [1]: cb1 := S11 [2]: cc1 := S11 [3]: cd1 := S11 [4]: S22 := fsolve (sa2*_Z ˆ4+ sb2*_Z ˆ3+ sc2*_Z ˆ2+ sd2*_Z+se2 , _Z , complex ): ca2 := S22 [1]: cb2 := S22 [2]: cc2 := S22 [3]: cd2 := S22 [4]: # Capacitor C1 voltage : RVc [1](t):= Ca1*exp(ca1*t)+Cb1*exp(cb1*t)+Cc1*exp(cc1*t)+Cd1*exp(cd1*t) -1/ se1*sf1: RVc [2](t):= Ca2*exp(ca2*t)+Cb2*exp(cb2*t)+Cc2*exp(cc2*t)+Cd2*exp(cd2*t) -1/ se2*sf2: # Inductor L1 voltage : RVL1 [1](t):=( QL/QC)*(1/ omega ˆ2)*diff(RVc [1](t),t$2): RVL1 [2](t):=( QL/QC)*(1/ omega ˆ2)*diff(RVc [2](t),t$2): # switch voltage : RVs [1](t):=( QL/QC)*(1/ omega ˆ2)*diff(RVc [1](t),t$2)+1/( QC*omega )*diff(RVc [1](t),t)+RVc [1](t): RVs [2](t):=( QL/QC)*(1/ omega ˆ2)*diff(RVc [2](t),t$2)+1/( QC*omega )*diff(RVc [2](t),t)+RVc [2](t): # Load resistor voltage : RVr [1](t) :=(1/( QC* omega ))*diff(RVc [1](t),t): RVr [2](t) :=(1/( QC* omega ))*diff(RVc [2](t),t): # Lnductor L voltage : RVl [1](t) :=(1/( QC* omega ))*diff(RVc [1](t),t)+( mr*mon/omega )*diff(RVs [1](t),t)+mr*RVs [1](t): RVl [2](t) :=(1/( QC* omega ))*diff(RVc [2](t),t)+( mr*mon/omega )*diff(RVs [2](t),t)+( mon/moff )*mr*RVs [2](t): ### using inductor current and capacitor voltage continuities at turn -on moment and t= td , we can find the values of Ca1 ,Cb1 ,Cc1 ,Cd1 ,Ca2 ,Cb2 ,Cc2 ,Cd2. # Capacitor charge continuity Appendix. Maple Code for Analytical Analysis 118 eq1 :=( subs(t=td ,RVc [1](t))-subs(t=td ,RVc [2](t))): eq2 :=( subs(t=0, RVc [1](t))-subs(t=T,RVc [2](t))): eq3 :=( subs(t=td ,RVs [1](t))-subs(t=td ,RVs [2](t))): eq4 :=( subs(t=0, RVs [1](t))-subs(t=T,RVs [2](t))): # Inductor flux continuity eq5 :=( subs(t=td ,RVr [1](t))-subs(t=td ,RVr [2](t))): eq6 :=( subs(t=0, RVr [1](t))-subs(t=T,RVr [2](t))): eq7 :=( subs(t=td ,RVl [1](t))-subs(t=td ,RVl [2](t))): eq8 :=( subs(t=0, RVl [1](t))-subs(t=T,RVl [2](t))): sm4 := fsolve ({eq1 ,eq2 ,eq3 ,eq4 ,eq5 ,eq6 ,eq7 ,eq8 },{Ca1 ,Cb1 ,Cc1 ,Cd1 ,Ca2 ,Cb2 ,Cc2 ,Cd2 }): assign (sm4): ### express the current and voltage in numbers . RVc [1](t):= Ca1*exp(ca1*t)+Cb1*exp(cb1*t)+Cc1*exp(cc1*t)+Cd1*exp(cd1*t) -1/ se1*sf1: RVc [2](t):= Ca2*exp(ca2*t)+Cb2*exp(cb2*t)+Cc2*exp(cc2*t)+Cd2*exp(cd2*t) -1/ se2*sf2: RVs [1](t):=( QL/QC)*(1/ omega ˆ2)*diff(RVc [1](t),t$2)+1/( QC*omega )*diff(RVc [1](t),t)+RVc [1](t): RVs [2](t):=( QL/QC)*(1/ omega ˆ2)*diff(RVc [2](t),t$2)+1/( QC*omega )*diff(RVc [2](t),t)+RVc [2](t): RVL1 [1](t):=( QL/QC)*(1/ omega ˆ2)*diff(RVc [1](t),t$2): RVL1 [2](t):=( QL/QC)*(1/ omega ˆ2)*diff(RVc [2](t),t$2): RVr [1](t) :=(1/( QC* omega ))*diff(RVc [1](t),t): RVr [2](t) :=(1/( QC* omega ))*diff(RVc [2](t),t): Idc :=Re(int ((1/( QC*mr*mon))*diff(RVc [1](t),t)+diff(RVs [1](t),t)+ omega *RVs [1](t)/mon ,t =0.. td)+int ((1/( QC*mr*mon))*diff(RVc [2](t),t)+diff(RVs [2](t),t)+omega *RVs [2](t)/ moff ,t=td..T))/T; Nir [1](t):= Re (1/( mr*QC*mon)*diff(RVc [1](t),t))/Idc: Nir [2](t):= Re (1/( mr*QC*mon)*diff(RVc [2](t),t))/Idc: Nic [1](t):= Re (1* diff(RVs [1](t),t))/Idc: Nic [2](t):= Re (1* diff(RVs [2](t),t))/Idc: Nis [1](t):= Re (1* omega /mon*RVs [1](t))/Idc: Nis [2](t):= Re (1* omega /moff*RVs [2](t))/Idc: ### calculate the DC power , switch power , and output power . Pdc := Vdd*Idc; Appendix. Maple Code for Analytical Analysis 119 Ps := Re( evalf (int(omega *RVs [1](t)ˆ2/ mon ,t=0.. td)+int(omega *RVs [2](t)ˆ2/ moff ,t=td ..T)))/ T; PL := Re( evalf (1/( mr*QC ˆ2* mon*omega )*( int(diff(RVc [1](t),t)ˆ2,t=0.. td)+int(diff(RVc [2](t ),t)ˆ2,t=td ..T))))/T; Vr0 :=(1/(2* Pi))*( int(RVr [1](t),t=0.. td)+int(RVr [2](t),t=td..T)): va1 :=(2/ T)*( int(RVr [1](t)*cos( omega *t),t=0.. td)+int(RVr [2](t)*cos(omega *t),t=td ..T)): vb1 :=(2/ T)*( int(RVr [1](t)*sin( omega *t),t=0.. td)+int(RVr [2](t)*sin(omega *t),t=td ..T)): Vr1(t):= va1*cos( omega *t)+vb1*sin( omega *t): va2 :=(2/ T)*( int(RVr [1](t)*cos (2* omega *t),t=0.. td)+int(RVr [2](t)*cos (2* omega *t),t=td ..T )): vb2 :=(2/ T)*( int(RVr [1](t)*sin (2* omega *t),t=0.. td)+int(RVr [2](t)*sin (2* omega *t),t=td ..T )): Vr2(t):= va2*cos (2* omega *t)+vb2*sin (2* omega *t): va3 :=(2/ T)*( int(RVr [1](t)*cos (3* omega *t),t=0.. td)+int(RVr [2](t)*cos (3* omega *t),t=td ..T )): vb3 :=(2/ T)*( int(RVr [1](t)*sin (3* omega *t),t=0.. td)+int(RVr [2](t)*sin (3* omega *t),t=td ..T )): Vr3(t):= va3*cos (3* omega *t)+vb3*sin (3* omega *t): Pr1 := Re(evalf (( omega /( mr*mon))*int(Vr1(t)ˆ2,t=0..T)))/T: Pr2 := Re(evalf (( omega /( mr*mon))*int(Vr2(t)ˆ2,t=0..T)))/T: Pr3 := Re(evalf (( omega /( mr*mon))*int(Vr3(t)ˆ2,t=0..T)))/T: ### calculate the real drain efficiency . eff := Pr1/Pdc; pvs1 := plot(Re(RVs [1](t)/Vdd),t=0..td ,title =" Switch Voltage ", labels =[’t’,’Vs(t)/VDD ’], thickness =3): pvs2 := plot(Re(RVs [2](t)/Vdd),t=td ..T,title =" Switch Voltage ", labels =[’t’,’Vs(t)/VDD ’], thickness =3): pis1 := plot(Re(Nis [1](t)),t=0..td , title =" Switch current ", labels =[’t’,’Is(t)/IDC ’], view =[0..T , -10..10] , thickness =3): pis2 := plot(Re(Nis [2](t)),t=td..T, title =" Switch current ", labels =[’t’,’Is(t)/IDC ’], view =[0..T , -10..10] , thickness =3): pir1 := plot(Re(Nir [1](t)),t=0..td , title =" Resistor current ",view =[0..T , -3..3] , labels =[’t ’,’Ir(t)/IDC ’], thickness =3): Appendix. Maple Code for Analytical Analysis 120 pir2 := plot(Re(Nir [2](t)),t=td..T, title =" Resistor current ",view =[0..T , -3..3] , labels =[’t ’,’Ir(t)/IDC ’], thickness =3): pic1 := plot(Re(Nic [1](t)),t=0..td , title =" Capacitor current ",view =[0..T , -10..10] , labels =[’t’,’Ic(t)/IDC ’], thickness =3): pic2 := plot(Re(Nic [2](t)),t=td..T, title =" Capacitor current ",view =[0..T , -10..10] , labels =[’t’,’Ic(t)/IDC ’], thickness =3): VSPLOT := display (pvs1 ,pvs2): ISPLOT := display (pis1 ,pis2): IRPLOT := display (pir1 ,pir2): ICPLOT := display (pic1 ,pic2): ### plot the current and voltage waveforms VSPLOT ; ISPLOT ; IRPLOT ; ICPLOT ; Bibliography [1] F. Raab, P. Asbeck, S. Cripps, P. Kenington, Z. Popovic, N. Pothecary, J. Sevic, and N. Sokal, “Power amplifiers and transmitters for RF and microwave,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 3, pp. 814–826, Mar. 2002. [2] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd ed. Artech House, 2006. [3] J. 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