CPU12RM

Reference Manual
A G R E E M E N T
CPU12
N O N - D I S C L O S U R E
HC12
R E Q U I R E D
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CPU12RM/AD
Rev. 1.0
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
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intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
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and hold Motorola and its officers, employees, subsidiaries, affiliates,
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was negligent regarding the design or manufacture of the part.
TABLE OF CONTENTS
Paragraph
Page
SECTION 1
INTRODUCTION
1.1
1.2
1.3
CPU12 Features .............................................................................................. 1-1
Readership....................................................................................................... 1-1
Symbols and Notation ...................................................................................... 1-2
SECTION 2
OVERVIEW
2.1
2.2
2.3
2.4
Programming Model......................................................................................... 2-1
Data Types....................................................................................................... 2-5
Memory Organization....................................................................................... 2-5
Instruction Queue............................................................................................. 2-5
SECTION 3
ADDRESSING MODES
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Mode Summary................................................................................................ 3-1
Effective Address ............................................................................................. 3-2
Inherent Addressing Mode ............................................................................... 3-2
Immediate Addressing Mode ........................................................................... 3-2
Direct Addressing Mode................................................................................... 3-3
Extended Addressing Mode ............................................................................. 3-3
Relative Addressing Mode ............................................................................... 3-4
Indexed Addressing Modes.............................................................................. 3-5
Instructions Using Multiple Modes ................................................................. 3-10
Addressing More than 64 Kbytes ................................................................... 3-12
SECTION 4
INSTRUCTION QUEUE
4.1
4.2
4.3
Queue Description ........................................................................................... 4-1
Data Movement in the Queue .......................................................................... 4-2
Changes in Execution Flow.............................................................................. 4-2
SECTION 5
INSTRUCTION SET OVERVIEW
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
Instruction Set Description ............................................................................... 5-1
Load and Store Instructions ............................................................................. 5-1
Transfer and Exchange Instructions ................................................................ 5-2
Move Instructions ............................................................................................. 5-3
Addition and Subtraction Instructions............................................................... 5-3
Binary Coded Decimal Instructions .................................................................. 5-4
Decrement and Increment Instructions ............................................................ 5-4
Compare and Test Instructions ........................................................................ 5-5
Boolean Logic Instructions ............................................................................... 5-6
Clear, Complement, and Negate Instructions .................................................. 5-6
CPU12
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MOTOROLA
iii
TABLE OF CONTENTS
Paragraph
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.24
5.25
5.26
5.27
Page
Multiplication and Division Instructions ............................................................ 5-7
Bit Test and Manipulation Instructions ............................................................. 5-7
Shift and Rotate Instructions ............................................................................ 5-8
Fuzzy Logic Instructions................................................................................... 5-9
Maximum and Minimum Instructions.............................................................. 5-11
Multiply and Accumulate Instruction............................................................... 5-11
Table Interpolation Instructions ...................................................................... 5-12
Branch Instructions ........................................................................................ 5-13
Loop Primitive Instructions ............................................................................. 5-16
Jump and Subroutine Instructions.................................................................. 5-17
Interrupt Instructions ...................................................................................... 5-18
Index Manipulation Instructions...................................................................... 5-19
Stacking Instructions ...................................................................................... 5-20
Pointer and Index Calculation Instructions..................................................... 5-20
Condition Code Instructions ........................................................................... 5-21
STOP and WAIT Instructions ......................................................................... 5-21
Background Mode and Null Operations ......................................................... 5-22
SECTION 6
INSTRUCTION GLOSSARY
6.1
6.2
6.3
6.4
6.5
6.6
Glossary Information ........................................................................................ 6-1
Condition Code Changes ................................................................................. 6-2
Object Code Notation....................................................................................... 6-2
Source Forms................................................................................................... 6-3
Cycle-by-Cycle Execution ................................................................................ 6-5
Glossary ........................................................................................................... 6-8
SECTION 7
EXCEPTION PROCESSING
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Types of Exceptions......................................................................................... 7-1
Exception Priority ............................................................................................. 7-2
Resets .............................................................................................................. 7-2
Interrupts .......................................................................................................... 7-3
Unimplemented Opcode Trap .......................................................................... 7-5
Software Interrupt Instruction ........................................................................... 7-6
Exception Processing Flow .............................................................................. 7-6
SECTION 8
DEVELOPMENT AND DEBUG SUPPORT
8.1
8.2
8.3
8.4
8.5
External Reconstruction of the Queue ............................................................. 8-1
Instruction Queue Status Signals..................................................................... 8-1
Implementing Queue Reconstruction............................................................... 8-3
Background Debug Mode ................................................................................ 8-6
Instruction Tagging......................................................................................... 8-13
MOTOROLA
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CPU12
REFERENCE MANUAL
TABLE OF CONTENTS
Paragraph
8.6
Page
Breakpoints .................................................................................................... 8-14
SECTION 9
FUZZY LOGIC SUPPORT
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Introduction ...................................................................................................... 9-1
Fuzzy Logic Basics .......................................................................................... 9-1
Example Inference Kernel................................................................................ 9-7
MEM Instruction Details ................................................................................... 9-9
REV, REVW Instruction Details ..................................................................... 9-13
WAV Instruction Details ................................................................................. 9-22
Custom Fuzzy Logic Programming ................................................................ 9-26
SECTION 10
MEMORY EXPANSION
10.1
10.2
10.3
10.4
10.5
10.6
Expansion System Description ...................................................................... 10-1
CALL and Return from Call Instructions......................................................... 10-3
Address Lines for Expansion Memory ........................................................... 10-4
Overlay Window Controls............................................................................... 10-4
Using Chip-Select Circuits ............................................................................. 10-5
System Notes................................................................................................. 10-7
APPENDIX A
INSTRUCTION REFERENCE
A.1
A.2
A.3
A.4
A.5
Instruction Set Summary..................................................................................A-1
Opcode Map.....................................................................................................A-1
Indexed Addressing Postbyte Encoding ..........................................................A-1
Transfer and Exchange Postbyte Encoding.....................................................A-1
Loop Primitive Postbyte Encoding ...................................................................A-1
APPENDIX B
M68HC11 TO M68HC12 UPGRADE PATH
B.1
B.2
B.3
B.4
B.5
B.6
B.7
CPU12 Design Goals .......................................................................................B-1
Source Code Compatibility...............................................................................B-1
Programmer’s Model and Stacking ..................................................................B-3
True 16-Bit Architecture ...................................................................................B-3
Improved Indexing............................................................................................B-6
Improved Performance.....................................................................................B-9
Additional Functions.......................................................................................B-11
APPENDIX C
HIGH-LEVEL LANGUAGE SUPPORT
C.1
C.2
C.3
Data Types...................................................................................................... C-1
Parameters and Variables............................................................................... C-1
Increment and Decrement Operators.............................................................. C-3
CPU12
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MOTOROLA
v
TABLE OF CONTENTS
Paragraph
C.4
C.5
C.6
C.7
C.8
C.9
Page
Higher Math Functions .................................................................................... C-3
Conditional If Constructs ................................................................................. C-4
Case and Switch Statements .......................................................................... C-4
Pointers ........................................................................................................... C-4
Function Calls ................................................................................................. C-4
Instruction Set Orthogonality........................................................................... C-5
APPENDIX D
ASSEMBLY LISTING
INDEX
SUMMARY OF CHANGES
MOTOROLA
vi
CPU12
REFERENCE MANUAL
LIST OF ILLUSTRATIONS
Figure
2-1
6-1
7-2
8-1
8-2
8-3
8-4
8-5
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
Page
Programming Model......................................................................................... 2-1
Example Glossary Page................................................................................... 6-1
Exception Processing Flow Diagram ............................................................... 7-7
Queue Status Signal Timing ............................................................................ 8-2
BDM Host to Target Serial Bit Timing .............................................................. 8-8
BDM Target to Host Serial Bit Timing (Logic 1) ............................................... 8-8
BDM Target to Host Serial Bit Timing (Logic 0) ............................................... 8-9
Tag Input Timing ............................................................................................ 8-13
Block Diagram of a Fuzzy Logic System.......................................................... 9-3
Fuzzification Using Membership Functions...................................................... 9-4
Fuzzy Inference Engine ................................................................................... 9-8
Defining a Normal Membership Function....................................................... 9-10
MEM Instruction Flow Diagram ...................................................................... 9-11
Abnormal Membership Function Case 1........................................................ 9-12
Abnormal Membership Function Case 2........................................................ 9-13
Abnormal Membership Function Case 3........................................................ 9-13
REV Instruction Flow Diagram ....................................................................... 9-16
REVW Instruction Flow Diagram.................................................................... 9-21
WAV and wavr Instruction Flow Diagram....................................................... 9-25
Endpoint Table Handling................................................................................ 9-28
CPU12
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MOTOROLA
vii
MOTOROLA
viii
CPU12
REFERENCE MANUAL
LIST OF TABLES
Table
3-1
3-2
3-3
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
7-1
7-2
8-1
8-2
8-3
8-4
8-5
10-1
A-1
A-2
A-3
A-4
Page
M68HC12 Addressing Mode Summary............................................................ 3-1
Summary of Indexed Operations ..................................................................... 3-6
PC Offsets for Move Instructions ................................................................... 3-11
Load and Store Instructions ............................................................................. 5-2
Transfer and Exchange Instructions ................................................................ 5-3
Move Instructions ............................................................................................. 5-3
Addition and Subtraction Instructions............................................................... 5-4
BCD Instructions .............................................................................................. 5-4
Decrement and Increment Instructions ............................................................ 5-5
Compare and Test Instructions ........................................................................ 5-5
Boolean Logic Instructions ............................................................................... 5-6
Clear, Complement, and Negate Instructions .................................................. 5-6
Multiplication and Division Instructions ............................................................ 5-7
Bit Test and Manipulation Instructions ............................................................. 5-7
Shift and Rotate Instructions ............................................................................ 5-8
Fuzzy Logic Instructions................................................................................. 5-10
Minimum and Maximum Instructions.............................................................. 5-11
Multiply and Accumulate Instructions............................................................. 5-12
Table Interpolation Instructions ...................................................................... 5-12
Short Branch Instructions............................................................................... 5-14
Long Branch Instructions ............................................................................... 5-15
Bit Condition Branch Instructions ................................................................... 5-16
Loop Primitive Instructions ............................................................................. 5-16
Jump and Subroutine Instructions.................................................................. 5-17
Interrupt Instructions ...................................................................................... 5-18
Index Manipulation Instructions...................................................................... 5-19
Stacking Instructions ...................................................................................... 5-20
Pointer and Index Calculation Instructions..................................................... 5-21
Condition Codes Instructions ......................................................................... 5-21
STOP and WAIT Instructions ......................................................................... 5-22
Background Mode and Null Operation Instructions........................................ 5-22
CPU12 Exception Vector Map ......................................................................... 7-1
Stacking Order on Entry to Interrupts............................................................... 7-5
IPIPE[1:0] Decoding......................................................................................... 8-2
BDM Commands Implemented in Hardware.................................................. 8-10
BDM Firmware Commands............................................................................ 8-11
BDM Register Mapping .................................................................................. 8-11
Tag Pin Function ............................................................................................ 8-13
Mapping Precedence ..................................................................................... 10-2
Instruction Set Summary..................................................................................A-2
CPU12 Opcode Map ......................................................................................A-20
Indexed Addressing Mode Summary .............................................................A-22
Indexed Addressing Mode Postbyte Encoding (xb) .......................................A-23
CPU12
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MOTOROLA
ix
LIST OF TABLES
A-5
A-6
B-1
B-2
B-3
B-4
Transfer and Exchange Postbyte Encoding...................................................A-24
Loop Primitive Postbyte Encoding (lb) ...........................................................A-25
Translated M68HC11 Mnemonics....................................................................B-2
Instructions with Smaller Object Code .............................................................B-3
Comparison of Math Instruction Speeds ........................................................B-10
New M68HC12 Instructions ...........................................................................B-11
MOTOROLA
x
CPU12
REFERENCE MANUAL
SECTION 1
INTRODUCTION
This manual describes the features and operation of the CPU12 processing unit used
in all M68HC12 microcontrollers.
1.1 CPU12 Features
The CPU12 is a high-speed, 16-bit processing unit that has a programming model
identical to that of the industry standard M68HC11 CPU. The CPU12 instruction set is
a proper superset of the M68HC11 instruction set, and M68HC11 source code is accepted by CPU12 assemblers with no changes.
The CPU12 has full 16-bit data paths and can perform arithmetic operations up to 20
bits wide for high-speed math execution.
Unlike many other 16-bit CPUs, the CPU12 allows instructions with odd byte counts,
including many single-byte instructions. This allows much more efficient use of ROM
space.
An instruction queue buffers program information so the CPU has immediate access
to at least three bytes of machine code at the start of every instruction.
In addition to the addressing modes found in other Motorola MCUs, the CPU12 offers
an extensive set of indexed addressing capabilities including:
•
•
•
•
•
•
Using the stack pointer as an index register in all indexed operations
Using the program counter as an index register in all but auto inc/dec mode
Accumulator offsets allowed using A, B, or D accumulators
Automatic pre- or post-increment or pre- or post-decrement (by –8 to +8)
5-bit, 9-bit, or 16-bit signed constant offsets
16-bit offset indexed-indirect and accumulator D offset indexed-indirect addressing
1.2 Readership
This manual is written for professionals and students in electronic design and software
development. The primary goal is to provide information necessary to implement control systems using M68HC12 devices. Basic knowledge of electronics, microprocessors, and assembly language programming is required to use the manual effectively.
Because the CPU12 has a great deal of commonality with the M68HC11 CPU, prior
knowledge of M68HC11 devices is helpful, but is not essential. The CPU12 also includes features that are new and unique. In these cases, there is supplementary material in the text to explain the new technology.
CPU12
REFERENCE MANUAL
INTRODUCTION
MOTOROLA
1-1
1.3 Symbols and Notation
The following symbols and notation are used throughout the manual. More specialized
usages that apply only to the instruction glossary are described at the beginning of that
section.
1.3.1 Abbreviations for System Resources
A
B
D
X
Y
SP
PC
CCR
—
—
—
—
—
—
—
—
Accumulator A
Accumulator B
Double accumulator D (A : B)
Index register X
Index register Y
Stack pointer
Program counter
Condition code register
S – STOP instruction control bit
X– Non-maskable interrupt control bit
H – Half-carry status bit
I – Maskable interrupt control bit
N – Negative status bit
Z – Zero status bit
V – Two’s complement overflow status bit
C – Carry/Borrow status bit
1.3.2 Memory and Addressing
M — 8-bit memory location pointed to by the effective address of the instruction
M : M+1 — 16-bit memory location. Consists of the location pointed to by the
effective address concatenated with the next higher memory location. The most significant byte is at location M.
M~M+3 — 32-bit memory location. Consists of the effective address of the
instruction concatenated with the next three higher memory
M(Y)~M(Y+3)
locations. The most significant byte is at location M or M(Y).
M(X) — Memory locations pointed to by index register X
M(SP) — Memory locations pointed to by the stack pointer
M(Y+3)
Memory locations pointed to by index register Y plus 3,
—
respectively.
PPAGE — Program overlay page (bank) number for extended memory
(>64K).
Page — Program overlay page
XH — High-order byte
XL — Low-order byte
( ) — Content of register or memory location
$ — Hexadecimal value
% — Binary value
MOTOROLA
1-2
INTRODUCTION
CPU12
REFERENCE MANUAL
1.3.3 Operators
+
–
•
+
⊕
×
÷
M
:
—
—
—
—
—
—
—
—
—
Addition
Subtraction
Logical AND
Logical OR (inclusive)
Logical exclusive OR
Multiplication
Division
Negation. One’s complement (invert each bit of M)
Concatenate
Example: A : B means: “The 16-bit value formed by concatenating 8-bit accumulator A with 8-bit accumulator B.”
A is in the high order position.
⇒ — Transfer
Example: (A) ⇒ M means: “The content of accumulator A is
transferred to memory location M.”
⇔ — Exchange
Example: D ⇔ X means: “Exchange the contents of D with those
of X.”
1.3.4 Conventions
Logic level one is the voltage that corresponds to the True (1) state.
Logic level zero is the voltage that corresponds to the False (0) state.
Set refers specifically to establishing logic level one on a bit or bits.
Cleared refers specifically to establishing logic level zero on a bit or bits.
Asserted means that a signal is in active logic state. An active low signal changes
from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one.
Negated means that an asserted signal changes logic state. An active low signal
changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero.
ADDR is the mnemonic for address bus.
DATA is the mnemonic for data bus.
LSB means least significant bit or bits; MSB, most significant bit or bits.
LSW means least significant word or words; MSW, most significant word or words.
A specific mnemonic within a range is referred to by mnemonic and number. A7 is
bit 7 of accumulator A. A range of mnemonics is referred to by mnemonic and the
numbers that define the range. DATA[15:8] form the high byte of the data bus.
CPU12
REFERENCE MANUAL
INTRODUCTION
MOTOROLA
1-3
MOTOROLA
1-4
INTRODUCTION
CPU12
REFERENCE MANUAL
SECTION 2
OVERVIEW
This section describes the CPU12 programming model, register set, the data types
used, and basic memory organization.
2.1 Programming Model
The CPU12 programming model, shown in Figure 2-1, is the same as that of the
M68HC11 CPU. The CPU has two 8-bit general-purpose accumulators (A and B) that
can be concatenated into a single 16-bit accumulator (D) for certain instructions. It also
has two index registers (X and Y), a 16-bit stack pointer (SP), a 16-bit program counter
(PC), and an 8-bit condition code register (CCR).
7
A
0 7
B
0
8-BIT ACCUMULATORS A AND B
OR
15
D
0
16-BIT DOUBLE ACCUMULATOR D
15
IX
0
INDEX REGISTER X
15
IY
0
INDEX REGISTER Y
15
SP
0
STACK POINTER
15
PC
0
PROGRAM COUNTER
S X H I N Z V C
CONDITION CODE REGISTER
HC12 PROG MODEL
Figure 2-1 Programming Model
2.1.1 Accumulators
General-purpose 8-bit accumulators A and B are used to hold operands and results of
operations. Some instructions treat the combination of these two 8-bit accumulators
(A : B) as a 16-bit double accumulator (D).
CPU12
REFERENCE MANUAL
OVERVIEW
MOTOROLA
2-1
Most operations can use accumulator A or B interchangeably. However, there are a
few exceptions. Add, subtract, and compare instructions involving both A and B (ABA,
SBA, and CBA) only operate in one direction, so it is important to make certain the correct operand is in the correct accumulator. The decimal adjust accumulator A (DAA)
instruction is used after binary-coded decimal (BCD) arithmetic operations. There is
no equivalent instruction to adjust accumulator B.
2.1.2 Index Registers
16-bit index registers X and Y are used for indexed addressing. In the indexed addressing modes, the contents of an index register are added to 5-bit, 9-bit, or 16-bit
constants or to the content of an accumulator to form the effective address of the instruction operand. The second index register is especially useful for moves and in
cases where operands from two separate tables are used in a calculation.
2.1.3 Stack Pointer
The CPU12 supports an automatic program stack. The stack is used to save system
context during subroutine calls and interrupts, and can also be used for temporary
data storage. The stack can be located anywhere in the standard 64-Kbyte address
space and can grow to any size up to the total amount of memory available in the system.
The stack pointer holds the 16-bit address of the last stack location used. Normally,
the SP is initialized by one of the first instructions in an application program. The stack
grows downward from the address pointed to by the SP. Each time a byte is pushed
onto the stack, the stack pointer is automatically decremented, and each time a byte
is pulled from the stack, the stack pointer is automatically incremented.
When a subroutine is called, the address of the instruction following the calling instruction is automatically calculated and pushed onto the stack. Normally, a return from
subroutine (RTS) or a return from call (RTC) instruction is executed at the end of a
subroutine. The return instruction loads the program counter with the previously
stacked return address and execution continues at that address.
When an interrupt occurs, the current instruction finishes execution (REV, REVW, and
WAV instructions can be interrupted, and resume execution once the interrupt has
been serviced), the address of the next instruction is calculated and pushed onto the
stack, all the CPU registers are pushed onto the stack, the program counter is loaded
with the address pointed to by the interrupt vector, and execution continues at that address. The stacked registers are referred to as an interrupt stack frame. The CPU12
stack frame is the same as that of the M68HC11.
2.1.4 Program Counter
The program counter (PC) is a 16-bit register that holds the address of the next instruction to be executed. It is automatically incremented each time an instruction is fetched.
MOTOROLA
2-2
OVERVIEW
CPU12
REFERENCE MANUAL
2.1.5 Condition Code Register
This register contains five status indicators, two interrupt masking bits, and a STOP
instruction control bit. It is named for the five status indicators.
The status bits reflect the results of CPU operation as it executes instructions. The five
flags are half carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The
half-carry flag is used only for BCD arithmetic operations. The N, Z, V, and C status
bits allow for branching based on the results of a previous operation.
In some architectures, only a few instructions affect condition codes, so that multiple
instructions must be executed in order to load and test a variable. Since most CPU12
instructions automatically update condition codes, it is rarely necessary to execute an
extra instruction for this purpose. The challenge in using the CPU12 lies in finding instructions that do not alter the condition codes. The most important of these instructions are pushes, pulls, transfers, and exchanges.
It is always a good idea to refer to an instruction set summary (see APPENDIX A INSTRUCTION REFERENCE) to check which condition codes are affected by a particular instruction.
The following paragraphs describe normal uses of the condition codes. There are other, more specialized uses. For instance, the C status bit is used to enable weighted
fuzzy logic rule evaluation. Specialized usages are described in the relevant portions
of this manual and in SECTION 6 INSTRUCTION GLOSSARY.
2.1.5.1 S Control Bit
Setting the S bit disables the STOP instruction. Execution of a STOP instruction causes the on-chip oscillator to stop. This may be undesirable in some applications. If the
CPU encounters a STOP instruction while the S bit is set, it is treated like a no-operation (NOP) instruction, and continues to the next instruction.
2.1.5.2 X Mask Bit
The XIRQ input is an updated version of the NMI input found on earlier generations of
MCUs. Non-maskable interrupts are typically used to deal with major system failures,
such as loss of power. However, enabling non-maskable interrupts before a system is
fully powered and initialized can lead to spurious interrupts. The X bit provides a mechanism for enabling non-maskable interrupts after a system is stable.
By default, the X bit is set to one during reset. As long as the X bit remains set, interrupt
service requests made via the XIRQ pin are not recognized. An instruction must clear
the X bit to enable non-maskable interrupt service requests made via the XIRQ pin.
Once the X bit has been cleared to zero, software cannot reset it to one by writing to
the CCR. The X bit is not affected by maskable interrupts.
When an XIRQ interrupt occurs after non-maskable interrupts are enabled, both the X
bit and the I bit are automatically set to prevent other interrupts from being recognized
during the interrupt service routine. The mask bits are set after the registers are
stacked, but before the interrupt vector is fetched.
CPU12
REFERENCE MANUAL
OVERVIEW
MOTOROLA
2-3
Normally, an RTI instruction at the end of the interrupt service routine restores register
values that were present before the interrupt occurred. Since the CCR is stacked before the X bit is set, the RTI normally clears the X bit, and thus re-enables nonmaskable interrupts. While it is possible to manipulate the stacked value of X so that
X is set after an RTI, there is no software method to re-set X (and disable NMI) once
X has been cleared.
2.1.5.3 H Status Bit
The H bit indicates a carry from accumulator A bit 3 during an addition operation. The
DAA instruction uses the value of the H bit to adjust a result in accumulator A to correct
BCD format. H is updated only by the ABA, ADD, and ADC instructions.
2.1.5.4 I Mask Bit
The I bit enables and disables maskable interrupt sources. By default, the I bit is set
to one during reset. An instruction must clear the I bit to enable maskable interrupts.
While the I bit is set, maskable interrupts can become pending and are remembered,
but operation continues uninterrupted until the I bit is cleared.
When an interrupt occurs after interrupts are enabled, the I bit is automatically set to
prevent other maskable interrupts during the interrupt service routine. The I bit is set
after the registers are stacked, but before the interrupt vector is fetched.
Normally, an RTI instruction at the end of the interrupt service routine restores register
values that were present before the interrupt occurred. Since the CCR is stacked before the I bit is set, the RTI normally clears the I bit, and thus re-enables interrupts.
Interrupts can be re-enabled by clearing the I bit within the service routine, but implementing a nested interrupt management scheme requires great care, and seldom improves system performance.
2.1.5.5 N Status Bit
The N bit shows the state of the MSB of the result. N is most commonly used in two’s
complement arithmetic, where the MSB of a negative number is one and the MSB of
a positive number is zero, but it has other uses. For instance, if the MSB of a register
or memory location is used as a status flag, the user can test status by loading an accumulator.
2.1.5.6 Z Status Bit
The Z bit is set when all the bits of the result are zeros. Compare instructions perform
an internal implied subtraction, and the condition codes, including Z, reflect the results
of that subtraction. The INX, DEX, INY, and DEY instructions affect the Z bit and no
other condition flags. These operations can only determine = and ≠.
2.1.5.7 V Status Bit
The V bit is set when two’s complement overflow occurs as a result of an operation.
MOTOROLA
2-4
OVERVIEW
CPU12
REFERENCE MANUAL
2.1.5.8 C Status Bit
The C bit is set when a carry occurs during addition or a borrow occurs during subtraction. The C bit also acts as an error flag for multiply and divide operations. Shift and
rotate instructions operate through the C bit to facilitate multiple-word shifts.
2.2 Data Types
The CPU12 uses the following types of data:
• Bits
• 5-bit signed integers
• 8-bit signed and unsigned integers
• 8-bit, 2-digit binary coded decimal numbers
• 9-bit signed integers
• 16-bit signed and unsigned integers
• 16-bit effective addresses
• 32-bit signed and unsigned integers
Negative integers are represented in two’s complement form.
Five-bit and 9-bit signed integers are used only as offsets for indexed addressing
modes.
Sixteen-bit effective addresses are formed during addressing mode computations.
Thirty-two-bit integer dividends are used by extended division instructions. Extended
multiply and extended multiply-and-accumulate instructions produce 32-bit products.
2.3 Memory Organization
The standard CPU12 address space is 64 Kbytes. Some M68HC12 devices support
a paged memory expansion scheme that increases the standard space by means of
predefined windows in address space. The CPU12 has special instructions that support use of expanded memory. See SECTION 10 MEMORY EXPANSION for more information.
Eight-bit values can be stored at any odd or even byte address in available memory.
Sixteen-bit values are stored in memory as two consecutive bytes; the high byte occupies the lowest address, but need not be aligned to an even boundary. Thirty-two-bit
values are stored in memory as four consecutive bytes; the high byte occupies the lowest address, but need not be aligned to an even boundary.
All I/O and all on-chip peripherals are memory-mapped. No special instruction syntax
is required to access these addresses. On-chip registers and memory are typically
grouped in blocks which can be relocated within the standard 64-Kbyte address
space. Refer to device documentation for specific information.
2.4 Instruction Queue
The CPU12 uses an instruction queue to buffer program information. The mechanism
is called a queue rather than a pipeline because a typical pipelined CPU executes
more than one instruction at the same time, while the CPU12 always finishes executing an instruction before beginning to execute another. Refer to SECTION 4 INSTRUCTION QUEUE for more information.
CPU12
REFERENCE MANUAL
OVERVIEW
MOTOROLA
2-5
MOTOROLA
2-6
OVERVIEW
CPU12
REFERENCE MANUAL
SECTION 3
ADDRESSING MODES
Addressing modes determine how the CPU accesses memory locations to be operated upon. This section discusses the various modes and how they are used.
3.1 Mode Summary
Addressing modes are an implicit part of CPU12 instructions. APPENDIX A INSTRUCTION REFERENCE shows the modes used by each instruction. All CPU12
addressing modes are shown in Table 3-1.
Table 3-1 M68HC12 Addressing Mode Summary
Addressing Mode
Source Format
Abbreviation
Description
Inherent
INST
(no externally supplied
operands)
INH
Operands (if any) are in CPU registers
Immediate
INST #opr8i
or
INST #opr16i
IMM
Operand is included in instruction stream
8- or 16-bit size implied by context
Direct
INST opr8a
DIR
Operand is the lower 8-bits of an address
in the range $0000 – $00FF
Extended
INST opr16a
EXT
Operand is a 16-bit address
Relative
INST rel8
or
INST rel16
REL
An 8-bit or 16-bit relative offset from the current
pc is supplied in the instruction
Indexed
(5-bit offset)
INST oprx5,xysp
IDX
5-bit signed constant offset from x, y, sp, or pc
Indexed
(pre-decrement)
INST oprx3,–xys
IDX
Auto pre-decrement x, y, or sp by 1 ~ 8
Indexed
(pre-increment)
INST oprx3,+xys
IDX
Auto pre-increment x, y, or sp by 1 ~ 8
Indexed
(post-decrement)
INST oprx3,xys–
IDX
Auto post-decrement x, y, or sp by 1 ~ 8
Indexed
(post-increment)
INST oprx3,xys+
IDX
Auto post-increment x, y, or sp by 1 ~ 8
Indexed
(accumulator offset)
INST abd,xysp
IDX
Indexed with 8-bit (A or B) or 16-bit (D)
accumulator offset from x, y, sp, or pc
Indexed
(9-bit offset)
INST oprx9,xysp
IDX1
9-bit signed constant offset from x, y, sp, or pc
(lower 8-bits of offset in one extension byte)
Indexed
(16-bit offset)
INST oprx16,xysp
IDX2
16-bit constant offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
Indexed-Indirect
(16-bit offset)
INST [oprx16,xysp]
[IDX2]
Pointer to operand is found at...
16-bit constant offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
Indexed-Indirect
(D accumulator
offset)
INST [D,xysp]
[D,IDX]
Pointer to operand is found at...
x, y, sp, or pc plus the value in D
CPU12
REFERENCE MANUAL
ADDRESSING MODES
MOTOROLA
3-1
The CPU12 uses all M68HC11 modes as well as new forms of indexed addressing.
Differences between M68HC11 and M68HC12 indexed modes are described in 3.8 Indexed Addressing Modes. Instructions that use more than one mode are discussed
in 3.9 Instructions Using Multiple Modes.
3.2 Effective Address
Each addressing mode except inherent mode generates a 16-bit effective address
which is used during the memory reference portion of the instruction. Effective address
computations do not require extra execution cycles.
3.3 Inherent Addressing Mode
Instructions that use this addressing mode either have no operands or all operands
are in internal CPU registers. In either case, the CPU does not need to access any
memory locations to complete the instruction.
Examples:
NOP
;this instruction has no operands
INX
;operand is a CPU register
3.4 Immediate Addressing Mode
Operands for immediate mode instructions are included in the instruction stream, and
are fetched into the instruction queue one 16-bit word at a time during normal program
fetch cycles. Since program data is read into the instruction queue several cycles before it is needed, when an immediate addressing mode operand is called for by an instruction, it is already present in the instruction queue.
The pound symbol (#) is used to indicate an immediate addressing mode operand.
One very common programming error is to accidentally omit the # symbol. This causes
the assembler to misinterpret the following expression as an address rather than explicitly provided data. For example LDAA #$55 means to load the immediate value $55
into the A accumulator, while LDAA $55 means to load the value from address $0055
into the A accumulator. Without the # symbol the instruction is erroneously interpreted
as a direct addressing mode instruction.
Examples:
LDAA
#$55
LDX
#$1234
LDY
#$67
These are common examples of 8-bit and 16-bit immediate addressing mode. The
size of the immediate operand is implied by the instruction context. In the third example, the instruction implies a 16-bit immediate value but only an 8-bit value is supplied.
In this case the assembler will generate the 16-bit value $0067 because the CPU expects a 16-bit value in the instruction stream.
BRSET
MOTOROLA
3-2
FOO,#$03,THERE
ADDRESSING MODES
CPU12
REFERENCE MANUAL
In this example, extended addressing mode is used to access the operand FOO,
immediate addressing mode is used to access the mask value $03, and relative addressing mode is used to identify the destination address of a branch in case the
branch-taken conditions are met. BRSET is listed as an extended mode instruction
even though immediate and relative modes are also used.
3.5 Direct Addressing Mode
This addressing mode is sometimes called zero-page addressing because it is used
to access operands in the address range $0000 through $00FF. Since these addresses always begin with $00, only the eight low-order bits of the address need to be included in the instruction, which saves program space and execution time. A system
can be optimized by placing the most commonly accessed data in this area of memory.
The eight low-order bits of the operand address are supplied with the instruction and
the eight high-order bits of the address are assumed to be zero.
Examples:
LDAA
$55
This is a very basic example of direct addressing. The value $55 is taken to be the
low-order half of an address in the range $0000 through $00FF. The high order half of
the address is assumed to be zero. During execution of this instruction, the CPU combines the value $55 from the instruction with the assumed value of $00 to form the address $0055, which is then used to access the data to be loaded into accumulator A.
LDX
$20
In this example, the value $20 is combined with the assumed value of $00 to form the
address $0020. Since the LDX instruction requires a 16-bit value, a 16-bit word of data
is read from addresses $0020 and $0021. After execution of this instruction, the X index register will have the value from address $0020 in its high-order half and the value
from address $0021 in its low-order half.
3.6 Extended Addressing Mode
In this addressing mode, the full 16-bit address of the memory location to be operated
on is provided in the instruction. This addressing mode can be used to access any location in the 64-Kbyte memory map.
Example:
LDAA
$F03B
This is a very basic example of extended addressing. The value from address $F03B
is loaded into the A accumulator.
CPU12
REFERENCE MANUAL
ADDRESSING MODES
MOTOROLA
3-3
3.7 Relative Addressing Mode
The relative addressing mode is used only by branch instructions. Short and long conditional branch instructions use relative addressing mode exclusively, but branching
versions of bit manipulation instructions (BRSET and BRCLR) use multiple addressing
modes, including relative mode. Refer to 3.9 Instructions Using Multiple Modes for
more information.
Short branch instructions consist of an 8-bit opcode and a signed 8-bit offset contained
in the byte that follows the opcode. Long branch instructions consist of an 8-bit prebyte, an 8-bit opcode and a signed 16-bit offset contained in the two bytes that follow
the opcode.
Each conditional branch instruction tests certain status bits in the condition code register. If the bits are in a specified state, the offset is added to the address of the next
memory location after the offset to form an effective address, and execution continues
at that address; if the bits are not in the specified state, execution continues with the
instruction immediately following the branch instruction.
Bit-condition branches test whether bits in a memory byte are in a specific state. Various addressing modes can be used to access the memory location. An 8-bit mask operand is used to test the bits. If each bit in memory that corresponds to a one in the
mask is either set (BRSET) or clear (BRCLR), an 8-bit offset is added to the address
of the next memory location after the offset to form an effective address, and execution
continues at that address; if all the bits in memory that correspond to a one in the mask
are not in the specified state, execution continues with the instruction immediately following the branch instruction.
Both 8-bit and 16-bit offsets are signed two’s complement numbers to support branching upward and downward in memory. The numeric range of short branch offset values is $80 (–128) to $7F (127). The numeric range of long branch offset values is
$8000 (–32768) to $7FFF (32767). If the offset is zero, the CPU executes the instruction immediately following the branch instruction, regardless of the test involved.
Since the offset is at the end of a branch instruction, using a negative offset value can
cause the PC to point to the opcode and initiate a loop. For instance, a branch always
(BRA) instruction consists of two bytes, so using an offset of $FE sets up an infinite
loop; the same is true of a long branch always (LBRA) instruction with an offset of
$FFFC.
An offset that points to the opcode can cause a bit-condition branch to repeat execution until the specified bit condition is satisfied. Since bit condition branches can consist of four, five, or six bytes depending on the addressing mode used to access the
byte in memory, the offset value that sets up a loop can vary. For instance, using an
offset of $FC with a BRCLR that accesses memory using an 8-bit indexed postbyte
sets up a loop that executes until all the bits in the specified memory byte that correspond to ones in the mask byte are cleared.
MOTOROLA
3-4
ADDRESSING MODES
CPU12
REFERENCE MANUAL
3.8 Indexed Addressing Modes
The CPU12 uses redefined versions of M68HC11 indexed modes that reduce execution time and eliminate code size penalties for using the Y index register. In most
cases, CPU12 code size for indexed operations is the same or is smaller than that for
the M68HC11. Execution time is shorter in all cases. Execution time improvements are
due to both a reduced number of cycles for all indexed instructions and to faster system clock speed.
The indexed addressing scheme uses a postbyte plus 0, 1, or 2 extension bytes after
the instruction opcode. The postbyte and extensions do the following tasks:
1. Specify which index register is used.
2. Determine whether a value in an accumulator is used as an offset.
3. Enable automatic pre or post increment or decrement.
4. Specify size of increment or decrement.
5. Specify use of 5-, 9-, or 16-bit signed offsets.
This approach eliminates the differences between X and Y register use while dramatically enhancing the indexed addressing capabilities.
Major advantages of the CPU12 indexed addressing scheme are:
•
•
The stack pointer can be used as an index register in all indexed operations.
The program counter can be used as an index register in all but autoincrement
and autodecrement modes.
• A, B, or D accumulators can be used for accumulator offsets.
• Automatic pre- or post-increment or pre- or post-decrement by –8 to +8
• A choice of 5-, 9-, or 16-bit signed constant offsets.
• Use of two new indexed-indirect modes.
— Indexed-indirect mode with 16-bit offset
— Indexed-indirect mode with accumulator D offset
Table 3-2 is a summary of indexed addressing mode capabilities and a description of
postbyte encoding. The postbyte is noted as xb in instruction descriptions. Detailed
descriptions of the indexed addressing mode variations follow the table.
All indexed addressing modes use a 16-bit CPU register and additional information to
create an effective address. In most cases the effective address specifies the memory
location affected by the operation. In some variations of indexed addressing, the effective address specifies the location of a value that points to the memory location affected by the operation.
Indexed addressing mode instructions use a postbyte to specify X, Y, SP, or PC as the
base index register and to further classify the way the effective address is formed. A
special group of instructions (LEAS, LEAX, and LEAY) cause this calculated effective
address to be loaded into an index register for further calculations.
CPU12
REFERENCE MANUAL
ADDRESSING MODES
MOTOROLA
3-5
Table 3-2 Summary of Indexed Operations
Postbyte
Code (xb)
Source Code
Syntax
,r
n,r
-n,r
rr0nnnnn
111rr0zs
n,r
-n,r
111rr011
[n,r]
rr1pnnnn
n,-r
n,+r
n,rn,r+
111rr1aa
A,r
B,r
D,r
111rr111
[D,r]
Comments
rr; 00 = X, 01 = Y, 10 = SP, 11 = PC
5-bit constant offset n = –16 to +15
r can specify X, Y, SP, or PC
Constant offset (9- or 16-bit signed)
z0 = 9-bit with sign in LSB of postbyte(s)
-256 < n < 255
1 = 16-bit
0 < n < 65,535
if z = s = 1, 16-bit offset indexed-indirect (see below)
r can specify X, Y, SP, or PC
16-bit offset indexed-indirect
rr can specify X, Y, SP, or PC
0 < n < 65,535
Auto pre-decrement/increment or Auto post-decrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
r can specify X, Y, or SP (PC not a valid choice)
+8 = 0111
…
+1 = 0000
-1 = 1111
…
-8 = 1000
Accumulator offset (unsigned 8-bit or 16-bit)
aa- 00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
r can specify X, Y, SP, or PC
Accumulator D offset indexed-indirect
r can specify X, Y, SP, or PC
3.8.1 5-Bit Constant Offset Indexed Addressing
This indexed addressing mode uses a 5-bit signed offset which is included in the instruction postbyte. This short offset is added to the base index register (X, Y, SP, or
PC) to form the effective address of the memory location that will be affected by the
instruction. This gives a range of –16 through +15 from the value in the base index register. Although other indexed addressing modes allow 9- or 16-bit offsets, those
modes also require additional extension bytes in the instruction for this extra information. The majority of indexed instructions in real programs use offsets that fit in the
shortest 5-bit form of indexed addressing.
Examples:
LDAA
0,X
STAB
–8,Y
For these examples, assume X has a value of $1000 and Y has a value of $2000 before execution. The 5-bit constant offset mode does not change the value in the index
register, so X will still be $1000 and Y will still be $2000 after execution of these instructions. In the first example, A will be loaded with the value from address $1000. In
the second example, the value from the B accumulator will be stored at address $1FF8
($2000 – $8).
MOTOROLA
3-6
ADDRESSING MODES
CPU12
REFERENCE MANUAL
3.8.2 9-Bit Constant Offset Indexed Addressing
This indexed addressing mode uses a 9-bit signed offset which is added to the base
index register (X, Y, SP, or PC) to form the effective address of the memory location
affected by the instruction. This gives a range of –256 through +255 from the value in
the base index register. The most significant bit (sign bit) of the offset is included in the
instruction postbyte and the remaining eight bits are provided as an extension byte after the instruction postbyte in the instruction flow.
Examples:
LDAA
$FF,X
LDAB
–20,Y
For these examples assume X is $1000 and Y is $2000 before execution of these instructions. (These instructions do not alter the index registers so they will still be $1000
and $2000 respectively after the instructions.) The first instruction will load A with the
value from address $10FF and the second instruction will load B with the value from
address $1FEC.
This variation of the indexed addressing mode in the CPU12 is similar to the M68HC11
indexed addressing mode, but is functionally enhanced. The M68HC11 CPU provides
for unsigned 8-bit constant offset indexing from X or Y, and use of Y requires an extra
instruction byte and thus, an extra execution cycle. The 9-bit signed offset used in the
CPU12 covers the same range of positive offsets as the M68HC11, and adds negative
offset capability. The CPU12 can use X, Y, SP or PC as the base index register.
3.8.3 16-Bit Constant Offset Indexed Addressing
This indexed addressing mode uses a 16-bit offset which is added to the base index
register (X, Y, SP, or PC) to form the effective address of the memory location affected
by the instruction. This allows access to any address in the 64-Kbyte address space.
Since the address bus and the offset are both 16 bits, it does not matter whether the
offset value is considered to be a signed or an unsigned value ($FFFF may be thought
of as +65,535 or as –1). The 16-bit offset is provided as two extension bytes after the
instruction postbyte in the instruction flow.
3.8.4 16-Bit Constant Indirect Indexed Addressing
This indexed addressing mode adds a 16-bit instruction-supplied offset to the base index register to form the address of a memory location that contains a pointer to the
memory location affected by the instruction. The instruction itself does not point to the
address of the memory location to be acted upon, but rather to the location of a pointer
to the address to be acted on. The square brackets distinguish this addressing mode
from 16-bit constant offset indexing.
Example:
LDAA
CPU12
REFERENCE MANUAL
[10,X]
ADDRESSING MODES
MOTOROLA
3-7
In this example, X holds the base address of a table of pointers. Assume that X has
an initial value of $1000, and that the value $2000 is stored at addresses $100A and
$100B. The instruction first adds the value 10 to the value in X to form the address
$100A. Next, an address pointer ($2000) is fetched from memory at $100A. Then, the
value stored in location $2000 is read and loaded into the A accumulator.
3.8.5 Auto Pre/Post Decrement/Increment Indexed Addressing
This indexed addressing mode provides four ways to automatically change the value
in a base index register as a part of instruction execution. The index register can be
incremented or decremented by an integer value either before or after indexing takes
place. The base index register may be X, Y, or SP (auto-modify modes would not
make sense on PC).
Pre decrement and pre increment versions of the addressing mode adjust the value of
the index register before accessing the memory location affected by the instruction —
the index register retains the changed value after the instruction executes. Post-decrement and post-increment versions of the addressing mode use the initial value in the
index register to access the memory location affected by the instruction, then change
the value of the index register.
The CPU12 allows the index register to be incremented or decremented by any integer
value in the ranges –8 through –1, or 1 through 8. The value need not be related to the
size of the operand for the current instruction. These instructions can be used to incorporate an index adjustment into an existing instruction rather than using an additional
instruction and increasing execution time. This addressing mode is also used to perform operations on a series of data structures in memory.
When an LEAS, LEAX, or LEAY instruction is executed using this addressing mode,
and the operation modifies the index register that is being loaded, the final value in the
register is the value that would have been used to access a memory operand (premodification is seen in the result but postmodification is not).
Examples:
STAA
1,–SP
;equivalent to PSHA
STX
2,–SP
;equivalent to PSHX
LDX
2,SP+
;equivalent to PULX
LDAA
1,SP+
;equivalent to PULA
For a “last-used” type of stack like the CPU12 stack, these four examples are equivalent to common push and pull instructions. For a “next-available” stack like the
M68HC11 stack, PSHA is equivalent to STAA 1,SP– and PULA is equivalent to LDAA
1,+SP. However, in the M68HC11, 16-bit operations like PSHX and PULX require multiple instructions to decrement the SP by one, then store X, then decrement SP by one
again.
MOTOROLA
3-8
ADDRESSING MODES
CPU12
REFERENCE MANUAL
In the STAA 1,–SP example, the stack pointer is pre-decremented by one and then A
is stored to the address contained in the stack pointer. Similarly the LDX 2,SP+ first
loads X from the address in the stack pointer, then post-increments SP by two.
Example:
MOVW
2,X+,4,+Y
This example demonstrates how to work with data structures larger than bytes and
words. With this instruction in a program loop, it is possible to move words of data from
a list having one word per entry into a second table that has four bytes per table element. In this example the source pointer is updated after the data is read from memory
(post-increment) while the destination pointer is updated before it is used to access
memory (pre-increment).
3.8.6 Accumulator Offset Indexed Addressing
In this indexed addressing mode, the effective address is the sum of the values in the
base index register and an unsigned offset in one of the accumulators. The value in
the index register itself is not changed. The index register can be X, Y, SP, or PC and
the accumulator can be either of the 8-bit accumulators (A or B) or the 16-bit D accumulator.
Example:
LDAA
B,X
This instruction internally adds B to X to form the address from which A will be loaded.
B and X are not changed by this instruction. This example is similar to the following
two-instruction combination in an M68HC11.
ABX
LDAA
0,X
However, this two-instruction sequence alters the index register. If this sequence was
part of a loop where B changed on each pass, the index register would have to be reloaded with the reference value on each loop pass. The use of LDAA B,X is more efficient in the CPU12.
3.8.7 Accumulator D Indirect Indexed Addressing
This indexed addressing mode adds the value in the D accumulator to the value in the
base index register to form the address of a memory location that contains a pointer
to the memory location affected by the instruction. The instruction operand does not
point to the address of the memory location to be acted upon, but rather to the location
of a pointer to the address to be acted upon. The square brackets distinguish this addressing mode from D accumulator offset indexing.
Example:
JMP
GO1
GO2
GO3
CPU12
REFERENCE MANUAL
[D,PC]
DC.W
DC.W
DC.W
PLACE1
PLACE2
PLACE3
ADDRESSING MODES
MOTOROLA
3-9
This example is a computed GOTO. The values beginning at GO1 are addresses of
potential destinations of the jump instruction. At the time the JMP [D,PC] instruction is
executed, PC points to the address GO1, and D holds one of the values $0000, $0002,
or $0004 (determined by the program some time before the JMP).
Assume that the value in D is $0002. The JMP instruction adds the values in D and
PC to form the address of GO2. Next the CPU reads the address PLACE2 from memory at GO2 and jumps to PLACE2. The locations of PLACE1 through PLACE3 were
known at the time of program assembly but the destination of the JMP depends upon
the value in D computed during program execution.
3.9 Instructions Using Multiple Modes
Several CPU12 instructions use more than one addressing mode in the course of execution.
3.9.1 Move Instructions
Move instructions use separate addressing modes to access the source and destination of a move. There are move variations for most combinations of immediate, extended, and indexed addressing modes.
The only combinations of addressing modes that are not allowed are those with an immediate mode destination (the operand of an immediate mode instruction is data, not
an address). For indexed moves, the reference index register may be X, Y, SP, or PC.
Move instructions do not support indirect modes, or 9- or 16-bit offset modes requiring
extra extension bytes. There are special considerations when using PC-relative addressing with move instructions.
PC-relative addressing uses the address of the location immediately following the last
byte of object code for the current instruction as a reference point. The CPU12 normally corrects for queue offset and for instruction alignment so that queue operation is
transparent to the user. However, move instructions pose three special problems:
1. Some moves use an indexed source and an indexed destination.
2. Some moves have object code that is too long to fit in the queue all at one time,
so the PC value changes during execution.
3. All moves do not have the indexed postbyte as the last byte of object code.
These cases are not handled by automatic queue pointer maintenance, but it is still
possible to use PC-relative indexing with move instructions by providing for PC offsets
in source code.
Table 3-3 shows PC offsets from the location immediately following the current instruction by addressing mode.
MOTOROLA
3-10
ADDRESSING MODES
CPU12
REFERENCE MANUAL
Table 3-3 PC Offsets for Move Instructions
MOVE Instruction Addressing Modes
MOVB
MOVW
Offset Value
IMM ⇒ IDX
+1
EXT ⇒ IDX
+2
IDX ⇒ EXT
–2
IDX ⇒ IDX
– 1 for 1st Operand
+ 1 for 2nd Operand
IMM ⇒ IDX
+2
EXT ⇒ IDX
+2
IDX ⇒ EXT
–2
IDX ⇒ IDX
– 1 for 1st Operand
+ 1 for 2nd Operand
Example:
1000
18 09 C2 20 00
MOVB
$2000 2,PC
Moves a byte of data from $2000 to $1009
The expected location of the PC = $1005. The offset = +2.
(1005 + 2 (for 2,PC) + 2 (for correction) = 1009)
$18 is the page pre-byte, 09 is the MOVB opcode for ext-idx, C2 is the indexed postbyte for 2,PC (without correction).
The Motorola MCUasm assembler produces corrected object code for PC-relative
moves (18 09 C0 20 00 for the example shown). Note that, instead of assembling the
2,PC as C2, the correction has been applied to make it C0. Check whether an assembler makes the correction before using PC-relative moves.
3.9.2 Bit Manipulation Instructions
Bit manipulation instructions use either a combination of two or a combination of three
addressing modes.
The BCLR and BSET instructions use an 8-bit mask to determine which bits in a memory byte are to be changed. The mask must be supplied with the instruction as an immediate mode value. The memory location to be modified can be specified by means
of direct, extended, or indexed addressing modes.
The BRCLR and BRSET instructions use an 8-bit mask to test the states of bits in a
memory byte. The mask is supplied with the instruction as an immediate mode value.
The memory location to be tested is specified by means of direct, extended, or indexed
addressing modes. Relative addressing mode is used to determine the branch address. A signed 8-bit offset must be supplied with the instruction.
CPU12
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3.10 Addressing More than 64 Kbytes
Some M68HC12 devices incorporate hardware that supports addressing a larger
memory space than the standard 64 Kbytes. The expanded memory system uses fast
on-chip logic to implement a transparent bank-switching scheme.
Increased code efficiency is the greatest advantage of using a switching scheme instead of a large linear address space. In systems with large linear address spaces, instructions require more bits of information to address a memory location, and CPU
overhead is greater. Other advantages include the ability to change the size of system
memory and the ability to use various types of external memory.
However, the add-on bank switching schemes used in other microcontrollers have
known weaknesses. These include the cost of external glue logic, increased programming overhead to change banks, and the need to disable interrupts while banks are
switched.
The M68HC12 system requires no external glue logic. Bank switching overhead is reduced by implementing control logic in the MCU. Interrupts do not need to be disabled
during switching because switching tasks are incorporated in special instructions that
greatly simplify program access to extended memory.
MCUs with expanded memory treat the 16 Kbytes of memory space from $8000 to
$BFFF as a program memory window. Expanded-memory devices also have an 8-bit
program page register (PPAGE), which allows up to 256 16-Kbyte program memory
pages to be switched into and out of the program memory window. This provides for
up to 4 Megabytes of paged program memory.
The CPU12 instruction set includes CALL and RTC (return from call) instructions,
which greatly simplify the use of expanded memory space. These instructions also execute correctly on devices that do not have expanded-memory addressing capability,
thus providing for portable code.
The CALL instruction is similar to the JSR instruction. When CALL is executed, the
current value in PPAGE is pushed onto the stack with a return address, and a new instruction-supplied value is written to PPAGE. This value selects the page the called
subroutine resides upon, and can be considered to be part of the effective address.
For all addressing mode variations except indexed indirect modes, the new page value
is provided by an immediate operand in the instruction. For indexed indirect variations
of CALL, a pointer specifies memory locations where the new page value and the address of the called subroutine are stored. Use of indirect addressing for both the page
value and the address within the page frees the program from keeping track of explicit
values for either address.
The RTC instruction restores the saved program page value and the return address
from the stack. This causes execution to resume at the next instruction after the original CALL instruction.
Refer to SECTION 10 MEMORY EXPANSION for a detailed discussion of memory expansion.
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SECTION 4
INSTRUCTION QUEUE
The CPU12 uses an instruction queue to increase execution speed. This section describes queue operation during normal program execution and changes in execution
flow. These concepts augment the descriptions of instructions and cycle-by-cycle instruction execution in subsequent sections, but it is important to note that queue operation is automatic, and generally transparent to the user.
The material in this section is general. SECTION 6 INSTRUCTION GLOSSARY contains detailed information concerning cycle-by-cycle execution of each instruction.
SECTION 8 DEVELOPMENT AND DEBUG SUPPORT contains detailed information
about tracking queue operation and instruction execution.
4.1 Queue Description
The fetching mechanism in the CPU12 is best described as a queue rather than as a
pipeline. Queue logic fetches program information and positions it for execution, but
instructions are executed sequentially. A typical pipelined CPU can execute more than
one instruction at the same time, but interactions between the prefetch and execution
mechanisms can make tracking and debugging difficult. The CPU12 thus gains the advantages of independent fetches, yet maintains a straightforward relationship between
bus and execution cycles.
There are two 16-bit queue stages and one 16-bit buffer. Program information is
fetched in aligned 16-bit words. Unless buffering is required, program information is
first queued into stage 1, then advanced to stage 2 for execution.
At least two words of program information are available to the CPU when execution
begins. The first byte of object code is in either the even or odd half of the word in stage
2, and at least two more bytes of object code are in the queue.
Queue logic manages the position of program information so that the CPU itself does
not deal with alignment. As it is executed, each instruction initiates at least enough program word fetches to replace its own object code in the queue.
The buffer is used when a program word arrives before the queue can advance. This
occurs during execution of single-byte and odd-aligned instructions. For instance, the
queue cannot advance after an aligned, single-byte instruction is executed, because
the first byte of the next instruction is also in stage 2. In these cases, information is
latched into the buffer until the queue can advance.
Two external pins, IPIPE[1:0], provide time-multiplexed information about data movement in the queue and instruction execution. Decoding and use of these signals is discussed in SECTION 8 DEVELOPMENT AND DEBUG SUPPORT.
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4.2 Data Movement in the Queue
All queue operations are combinations of four basic queue movement cycles. Descriptions of each of these cycles follows. Queue movement cycles are only one factor in
instruction execution time, and should not be confused with bus cycles.
4.2.1 No Movement
There is no data movement in the instruction queue during the cycle. This occurs during execution of instructions that must perform a number of internal operations, such
as division instructions.
4.2.2 Latch Data from Bus
All instructions initiate fetches to refill the queue as execution proceeds. However, a
number of conditions, including instruction alignment and the length of previous instructions, affect when the queue advances. If the queue is not ready to advance when
fetched information arrives, the information is latched into the buffer. Later, when the
queue does advance, stage 1 is refilled from the buffer. If more than one latch cycle
occurs before the queue advances, the buffer is filled on the first latch event and subsequent latch events are ignored until the queue advances.
4.2.3 Advance and Load from Data Bus
The content of queue stage 1 advances to stage 2, and stage 1 is loaded with a word
of program information from the data bus. The information was requested two bus cycles earlier but has only become available this cycle, due to access delay.
4.2.4 Advance and Load from Buffer
The content of queue stage 1 advances to stage 2, and stage 1 is loaded with a word
of program information from the buffer. The information in the buffer was latched from
the data bus during a previous cycle because the queue was not ready to advance
when it arrived.
4.3 Changes in Execution Flow
During normal instruction execution, queue operations proceed as a continuous sequence of queue movement cycles. However, situations arise which call for changes
in flow. These changes are categorized as resets, interrupts, subroutine calls, conditional branches, and jumps. Generally speaking, resets and interrupts are considered
to be related to events outside the current program context that require special processing, while subroutine calls, branches, and jumps are considered to be elements
of program structure.
During design, great care is taken to assure that the mechanism that increases instruction throughput during normal program execution does not cause bottlenecks
during changes of program flow, but internal queue operation is largely transparent to
the user. The following information is provided to enhance subsequent descriptions of
instruction execution.
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4.3.1 Exceptions
Exceptions are events that require processing outside the normal flow of instruction
execution. CPU12 exceptions include four types of resets, an unimplemented opcode
trap, a software interrupt instruction, X-bit interrupts, and I-bit interrupts. All exceptions
use the same microcode, but the CPU follows different execution paths for each type
of exception.
CPU12 exception handling is designed to minimize the effect of queue operation on
context switching. Thus, an exception vector fetch is the first part of exception processing, and fetches to refill the queue from the address pointed to by the vector are
interleaved with the stacking operations that preserve context, so that program access
time does not delay the switch. Refer to SECTION 7 EXCEPTION PROCESSING for
detailed information.
4.3.2 Subroutines
The CPU12 can branch to (BSR), jump to (JSR), or CALL subroutines. BSR and JSR
are used to access subroutines in the normal 64-Kbyte address space. The CALL instruction is intended for use in MCUs with expanded memory capability.
BSR uses relative addressing mode to generate the effective address of the subroutine, while JSR can use various other addressing modes. Both instructions calculate a
return address, stack the address, then perform three program word fetches to refill
the queue. The first two words fetched are queued during the second and third cycles
of the sequence. The third fetch cycle is performed in anticipation of a queue advance,
which may occur during the fourth cycle of the sequence. If the queue is not yet ready
to advance at that time, the third word of program information is held in the buffer.
Subroutines in the normal 64-Kbyte address space are terminated with a return from
subroutine (RTS) instruction. RTS unstacks the return address, then performs three
program word fetches from that address to refill the queue.
CALL is similar to JSR. MCUs with expanded memory treat 16 Kbytes of addresses
from $8000 to $BFFF as a memory window. An 8-bit PPAGE register switches memory pages into and out of the window. When CALL is executed, a return address is calculated, then it and the current PPAGE value are stacked, and a new instructionsupplied value is written to PPAGE. The subroutine address is calculated, then three
program word fetches are made from that address.
The RTC instruction is used to terminate subroutines in expanded memory. RTC unstacks the PPAGE value and the return address, then performs three program word
fetches from that address to refill the queue.
CALL and RTC execute correctly in the normal 64-Kbyte address space, thus providing for portable code. However, since extra execution cycles are required, routinely
substituting CALL/RTC for JSR/RTS is not recommended.
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4.3.3 Branches
Branch instructions cause execution flow to change when specific pre-conditions exist.
The CPU12 instruction set includes short conditional branches, long conditional
branches, and bit-condition branches. Types and conditions of branch instructions are
described in 5.18 Branch Instructions. All branch instructions affect the queue similarly, but there are differences in overall cycle counts between the various types. Loop
primitive instructions are a special type of branch instruction used to implement
counter-based loops.
Branch instructions have two execution cases. Either the branch condition is satisfied,
and a change of flow takes place, or the condition is not satisfied, and no change of
flow occurs.
4.3.3.1 Short Branches
The “not-taken” case for short branches is simple. Since the instruction consists of a
single word containing both an opcode and an 8-bit offset, the queue advances, another program word is fetched, and execution continues with the next instruction.
The “taken” case for short branches requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is
calculated using the relative offset in the instruction. Then, the address is loaded into
the program counter, and the CPU performs three program word fetches at the new
address. The first two words fetched are loaded into the instruction queue during the
second and third cycles of the sequence. The third fetch cycle is performed in anticipation of a queue advance, which may occur during the first cycle of the next instruction. If the queue is not yet ready to advance at that time, the third word of program
information is held in the buffer.
4.3.3.2 Long Branches
The “not-taken” case for all long branches requires three cycles, while the “taken” case
requires four cycles. This is due to differences in the amount of program information
needed to fill the queue.
Long branch instructions begin with a $18 prebyte which indicates that the opcode is
on page 2 of the opcode map. The CPU12 treats the prebyte as a special one-byte
instruction. If the prebyte is not aligned, the first cycle is used to perform a program
word access; if the prebyte is aligned, the first cycle is used to perform a free cycle.
The first cycle for the prebyte is executed whether or not the branch is taken.
The first cycle of the branch instruction is an optional cycle. Optional cycles make the
effects of byte-sized and misaligned instructions consistent with those of aligned wordlength instructions. Optional cycles are always performed, but serve different purposes determined by instruction alignment. Program information is always fetched as
aligned 16-bit words. When an instruction consists of an odd number of bytes, and the
first byte is aligned with an even byte boundary, an optional cycle is used to make an
additional program word access that maintains queue order. In all other cases, the optional cycle appears as a free cycle.
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In the “not-taken” case, the queue must advance so that execution can continue with
the next instruction. Two cycles are used to refill the queue. Alignment determines how
the second of these cycles is used.
In the “taken” case, the effective address of the branch is calculated using the 16-bit
relative offset contained in the second word of the instruction. This address is loaded
into the program counter, then the CPU performs three program word fetches at the
new address. The first two words fetched are loaded into the instruction queue during
the second and third cycles of the sequence. The third fetch cycle is performed in anticipation of a queue advance, which may occur during the first cycle of the next
instruction. If the queue is not yet ready to advance, the third word of program information is held in the buffer.
4.3.3.3 Bit Condition Branches
Bit-conditional branch instructions read a location in memory, and branch if the bits in
that location are in a certain state. These instructions can use direct, extended, or indexed addressing modes. Indexed operations require varying amounts of information
to determine the effective address, so instruction length varies according to the mode
used, which in turn affects the amount of program information fetched. In order to
shorten execution time, these branches perform one program word fetch in anticipation of the “taken” case. The data from this fetch is overwritten by subsequent fetches
in the “not-taken” case.
4.3.3.4 Loop Primitives
The loop primitive instructions test a counter value in a register or accumulator, and
branch to an address specified by a 9-bit relative offset contained in the instruction if
a specified pre-condition is met. There are auto-increment and auto-decrement versions of the instructions. The test and increment/decrement operations are performed
on internal CPU registers, and require no additional program information. In order to
shorten execution time, these branches perform one program word fetch in anticipation of the “taken” case. The data from this fetch is overwritten by subsequent fetches
in the “not-taken” case. The “taken” case performs two additional program word fetches at the new address. In the “not-taken” case, the queue must advance so that execution can continue with the next instruction. Two cycles are used to refill the queue.
4.3.4 Jumps
JMP is the simplest change of flow instruction. JMP can use extended or indexed addressing. Indexed operations require varying amounts of information to determine the
effective address, so instruction length varies according to the mode used, which in
turn affects the amount of program information fetched. All forms of JMP perform three
program word fetches at the new address. The first two words fetched are loaded into
the instruction queue during the second and third cycles of the sequence. The third
fetch cycle is performed in anticipation of a queue advance, which may occur during
the first cycle of the next instruction. If the queue is not yet ready to advance, the third
word of program information is held in the buffer.
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SECTION 5
INSTRUCTION SET OVERVIEW
This section contains general information about the CPU12 instruction set. It is organized into instruction categories grouped by function.
5.1 Instruction Set Description
CPU12 instructions are a superset of the M68HC11 instruction set. Code written for
an M68HC11 can be reassembled and run on a CPU12 with no changes. The CPU12
provides expanded functionality and increased code efficiency.
In the M68HC12 architecture, all memory and I/O are mapped in a common 64-Kbyte
address space (memory-mapped I/O). This allows the same set of instructions to be
used to access memory, I/O, and control registers. General-purpose load, store, transfer, exchange, and move instructions facilitate movement of data to and from memory
and peripherals.
The CPU12 has a full set of 8-bit and 16-bit mathematical instructions. There are instructions for signed and unsigned arithmetic, division and multiplication with 8-bit, 16bit, and some larger operands.
Special arithmetic and logic instructions aid stacking operations, indexing, BCD calculation, and condition code register manipulation. There are also dedicated instructions
for multiply and accumulate operations, table interpolation, and specialized fuzzy logic
operations that involve mathematical calculations.
Refer to SECTION 6 INSTRUCTION GLOSSARY for detailed information about individual instructions. APPENDIX A INSTRUCTION REFERENCE contains quick-reference material, including an opcode map and postbyte encoding for indexed
addressing, transfer/exchange instructions, and loop primitive instructions.
5.2 Load and Store Instructions
Load instructions copy memory content into an accumulator or register. Memory content is not changed by the operation. Load instructions (but not LEA_ instructions) affect condition code bits so no separate test instructions are needed to check the
loaded values for negative or zero conditions.
Store instructions copy the content of a CPU register to memory. Register/accumulator content is not changed by the operation. Store instructions automatically update
the N and Z condition code bits, which can eliminate the need for a separate test instruction in some programs.
Table 5-1 is a summary of load and store instructions.
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Table 5-1 Load and Store Instructions
Load Instructions
Mnemonic
Function
Operation
LDAA
Load A
(M) ⇒ A
LDAB
Load B
(M) ⇒ B
LDD
Load D
(M : M + 1) ⇒ (A:B)
LDS
Load SP
(M : M + 1) ⇒ SP
LDX
Load Index Register X
(M : M + 1) ⇒ X
LDY
Load Index Register Y
(M : M + 1) ⇒ Y
LEAS
Load Effective Address into SP
Effective Address ⇒ SP
LEAX
Load Effective Address into X
Effective Address ⇒ X
LEAY
Load Effective Address into Y
Effective Address ⇒ Y
Store Instructions
Mnemonic
Function
Operation
STAA
Store A
(A) ⇒ M
STAB
Store B
(B) ⇒ M
STD
Store D
(A) ⇒ M, (B) ⇒ M + 1
STS
Store SP
(SP) ⇒ M : M + 1
STX
Store X
(X) ⇒ M : M + 1
STY
Store Y
(Y) ⇒ M : M + 1
5.3 Transfer and Exchange Instructions
Transfer instructions copy the content of a register or accumulator into another register
or accumulator. Source content is not changed by the operation. TFR is a universal
transfer instruction, but other mnemonics are accepted for compatibility with the
M68HC11. The TAB and TBA instructions affect the N, Z, and V condition code bits in
the same way as M68HC11 instructions. The TFR instruction does not affect the condition code bits.
Exchange instructions exchange the contents of pairs of registers or accumulators.
The SEX instruction is a special case of the universal transfer instruction that is used
to sign-extend 8-bit two’s complement numbers so that they can be used in 16-bit operations. The 8-bit number is copied from accumulator A, accumulator B, or the condition codes register to accumulator D, the X index register, the Y index register, or the
stack pointer. All the bits in the upper byte of the 16-bit result are given the value of
the MSB of the 8-bit number.
SECTION 6 INSTRUCTION GLOSSARY contains information concerning other
transfers and exchanges between 8- and 16-bit registers.
Table 5-2 is a summary of transfer and exchange instructions.
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Table 5-2 Transfer and Exchange Instructions
Transfer Instructions
Mnemonic
Function
Operation
TAB
Transfer A to B
(A) ⇒ B
TAP
Transfer A to CCR
(A) ⇒ CCR
TBA
Transfer B to A
(B) ⇒ A
TFR
Transfer Register to Register
(A, B, CCR, D, X, Y, or SP) ⇒ A, B, CCR, D, X, Y, or SP
TPA
Transfer CCR to A
(CCR) ⇒ A
TSX
Transfer SP to X
(SP) ⇒ X
TSY
Transfer SP to Y
(SP) ⇒ Y
TXS
Transfer X to SP
(X) ⇒ SP
TYS
Transfer Y to SP
(Y) ⇒ SP
Exchange Instructions
Mnemonic
Function
Operation
EXG
Exchange Register to Register
(A, B, CCR, D, X, Y, or SP) ⇔ (A, B, CCR, D, X, Y, or SP)
XGDX
Exchange D with X
(D) ⇔ (X)
XGDY
Exchange D with Y
(D) ⇔ (Y)
Sign Extension Instruction
Mnemonic
Function
Operation
SEX
Sign Extend 8-Bit Operand
(A, B, CCR) ⇒ X, Y, or SP
5.4 Move Instructions
These instructions move data bytes or words from a source (M1, M : M +11) to a destination (M2, M : M +12) in memory. Six combinations of immediate, extended, and indexed addressing are allowed to specify source and destination addresses (IMM ⇒
EXT, IMM ⇒ IDX, EXT ⇒ EXT, EXT ⇒ IDX, IDX ⇒ EXT, IDX ⇒ IDX).
Table 5-3 shows byte and word move instructions.
Table 5-3 Move Instructions
Mnemonic
Function
Operation
MOVB
Move Byte (8-bit)
(M1) ⇒ M2
MOVW
Move Word (16-bit)
(M : M + 11) ⇒ M : M + 12
5.5 Addition and Subtraction Instructions
Signed and unsigned 8- and 16-bit addition can be performed between registers or between registers and memory. Special instructions support index calculation. Instructions that add the CCR carry bit facilitate multiple precision computation.
Signed and unsigned 8- and 16-bit subtraction can be performed between registers or
between registers and memory. Special instructions support index calculation. Instructions that subtract the CCR carry bit facilitate multiple precision computation. Refer to
Table 5-4 for addition and subtraction instructions.
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Table 5-4 Addition and Subtraction Instructions
Addition Instructions
Mnemonic
Function
Operation
ABA
Add A to B
(A) + (B) ⇒ A
ABX
Add B to X
(B) + (X) ⇒ X
ABY
Add B to Y
(B) + (Y) ⇒ Y
ADCA
Add with Carry to A
(A) + (M) + C ⇒ A
ADCB
Add with Carry to B
(B) + (M) + C ⇒ B
ADDA
Add without Carry to A
(A) + (M) ⇒ A
ADDB
Add without Carry to B
(B) + (M) ⇒ B
ADDD
Add to D
(A:B) + (M : M + 1) ⇒ A : B
Mnemonic
Function
Operation
SBA
Subtract B from A
(A) – (B) ⇒ A
SBCA
Subtract with Borrow from A
(A) – (M) – C ⇒ A
SBCB
Subtract with Borrow from B
(B) – (M) – C ⇒ B
SUBA
Subtract Memory from A
(A) – (M) ⇒ A
SUBB
Subtract Memory from B
(B) – (M) ⇒ B
SUBD
Subtract Memory from D (A:B)
(D) – (M : M + 1) ⇒ D
Subtraction Instructions
5.6 Binary Coded Decimal Instructions
To add binary coded decimal operands, use addition instructions that set the half-carry
bit in the CCR, then adjust the result with the DAA instruction. Table 5-5 is a summary
of instructions that can be used to perform BCD operations.
Table 5-5 BCD Instructions
Mnemonic
Function
Operation
ABA
Add B to A
(A) + (B) ⇒ A
ADCA
Add with Carry to A
(A) + (M) + C ⇒ A
ADCB
Add with Carry to B
(B) + (M) + C ⇒ B
ADDA
Add Memory to A
(A) + (M) ⇒ A
ADDB
Add Memory to B
(B) + (M) ⇒ B
DAA
Decimal Adjust A
(A)10
5.7 Decrement and Increment Instructions
These instructions are optimized 8- and 16-bit addition and subtraction operations.
They are generally used to implement counters. Because they do not affect the carry
bit in the CCR, they are particularly well suited for loop counters in multiple-precision
computation routines. Refer to 5.19 Loop Primitive Instructions for information concerning automatic counter branches. Table 5-6 is a summary of decrement and increment instructions.
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Table 5-6 Decrement and Increment Instructions
Decrement Instructions
Mnemonic
Function
Operation
DEC
Decrement Memory
(M) – $01 ⇒ M
DECA
Decrement A
(A) – $01 ⇒ A
DECB
Decrement B
(B) – $01 ⇒ B
DES
Decrement SP
(SP) – $0001 ⇒ SP
DEX
Decrement X
(X) – $0001 ⇒ X
DEY
Decrement Y
(Y) – $0001 ⇒ Y
Increment Instructions
Mnemonic
Function
Operation
INC
Increment Memory
(M) + $01 ⇒ M
INCA
Increment A
(A) + $01 ⇒ A
INCB
Increment B
(B) + $01 ⇒ B
INS
Increment SP
(SP) + $0001 ⇒ SP
INX
Increment X
(X) + $0001 ⇒ X
INY
Increment Y
(Y) + $0001 ⇒ Y
5.8 Compare and Test Instructions
Compare and test instructions perform subtraction between a pair of registers or between a register and memory. The result is not stored, but condition codes are set by
the operation. These instructions are generally used to establish conditions for branch
instructions. In this architecture, most instructions update condition code bits automatically, so it is often unnecessary to include separate test or compare instructions. Table 5-7 is a summary of compare and test instructions.
Table 5-7 Compare and Test Instructions
Compare Instructions
Mnemonic
Function
Operation
CBA
Compare A to B
(A) – (B)
CMPA
Compare A to Memory
(A) – (M)
CMPB
Compare B to Memory
(B) – (M)
CPD
Compare D to Memory (16-bit)
(A : B) – (M : M + 1)
CPS
Compare SP to Memory (16-bit)
(SP) – (M : M + 1)
CPX
Compare X to Memory (16-bit)
(X) – (M : M + 1)
CPY
Compare Y to Memory (16-bit)
(Y) – (M : M + 1)
Test Instructions
Mnemonic
Function
Operation
TST
Test Memory for Zero or Minus
(M) – $00
TSTA
Test A for Zero or Minus
(A) – $00
TSTB
Test B for Zero or Minus
(B) – $00
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5.9 Boolean Logic Instructions
These instructions perform a logic operation between an 8-bit accumulator or the CCR
and a memory value. AND, OR, and exclusive OR functions are supported. Table 58 summarizes logic instructions.
Table 5-8 Boolean Logic Instructions
Mnemonic
Function
Operation
ANDA
AND A with Memory
(A) • (M) ⇒ A
ANDB
AND B with Memory
(B) • (M) ⇒ B
ANDCC
AND CCR with Memory (Clear CCR Bits)
(CCR) • (M) ⇒ CCR
EORA
Exclusive OR A with Memory
(A) ⊕ (M) ⇒ A
EORB
Exclusive OR B with Memory
(B) ⊕ (M) ⇒ B
ORAA
OR A with Memory
(A) + (M) ⇒ A
ORAB
OR B with Memory
(B) + (M) ⇒ B
ORCC
OR CCR with Memory (Set CCR Bits)
(CCR) + (M) ⇒ CCR
5.10 Clear, Complement, and Negate Instructions
Each of these instructions performs a specific binary operation on a value in an accumulator or in memory. Clear operations clear the value to zero, complement operations replace the value with its one’s complement, and negate operations replace the
value with its two’s complement. Table 5-9 is a summary of clear, complement and
negate instructions.
Table 5-9 Clear, Complement, and Negate Instructions
Mnemonic
Function
Operation
CLC
Clear C Bit in CCR
0⇒C
CLI
Clear I Bit in CCR
0⇒I
CLR
Clear Memory
$00 ⇒ M
CLRA
Clear A
$00 ⇒ A
CLRB
Clear B
$00 ⇒ B
CLV
Clear V bit in CCR
0⇒V
COM
One’s Complement Memory
$FF – (M) ⇒ M or (M) ⇒ M
COMA
One’s Complement A
$FF – (A) ⇒ A or (A) ⇒ A
COMB
One’s Complement B
$FF – (B) ⇒ B or (B) ⇒ B
NEG
Two’s Complement Memory
$00 – (M) ⇒ M or (M) + 1 ⇒ M
NEGA
Two’s Complement A
$00 – (A) ⇒ A or (A) + 1 ⇒ A
NEGB
Two’s Complement B
$00 – (B) ⇒ B or (B) + 1 ⇒ B
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REFERENCE MANUAL
5.11 Multiplication and Division Instructions
There are instructions for signed and unsigned 8- and 16-bit multiplication. Eight-bit
multiplication operations have a 16-bit product. Sixteen-bit multiplication operations
have 32-bit products.
Integer and fractional division instructions have 16-bit dividend, divisor, quotient, and
remainder. Extended division instructions use a 32-bit dividend and a 16-bit divisor to
produce a 16-bit quotient and a 16-bit remainder.
Table 5-10 is a summary of multiplication and division instructions.
Table 5-10 Multiplication and Division Instructions
Multiplication Instructions
Mnemonic
Function
Operation
EMUL
16 by 16 Multiply (Unsigned)
(D) × (Y) ⇒ Y : D
EMULS
16 by 16 Multiply (Signed)
(D) × (Y) ⇒ Y : D
MUL
8 by 8 Multiply (Unsigned)
(A) × (B) ⇒ A : B
Division Instructions
Mnemonic
Function
Operation
EDIV
32 by 16 Divide (Unsigned)
(Y : D) ÷ (X)
Quotient ⇒ Y
Remainder ⇒ D
EDIVS
32 by 16 Divide (Signed)
(Y : D) ÷ (X)
Quotient ⇒ Y
Remainder ⇒ D
FDIV
16 by 16 Fractional Divide
(D) ÷ (X) ⇒ X
remainder ⇒ D
IDIV
16 by 16 Integer Divide (Unsigned)
(D) ÷ (X) ⇒ X
remainder ⇒ D
IDIVS
16 by 16 Integer Divide (Signed)
(D) ÷ (X) ⇒ X
remainder ⇒ D
5.12 Bit Test and Manipulation Instructions
These operations use a mask value to test or change the value of individual bits in an
accumulator or in memory. BITA and BITB provide a convenient means of testing bits
without altering the value of either operand. Table 5-11 is a summary of bit test and
manipulation instructions.
Table 5-11 Bit Test and Manipulation Instructions
Mnemonic
Function
Operation
BCLR
Clear Bits in Memory
(M) • (mm) ⇒ M
BITA
Bit Test A
(A) • (M)
BITB
Bit Test B
(B) • (M)
BSET
Set Bits in Memory
(M) + (mm) ⇒ M
CPU12
REFERENCE MANUAL
INSTRUCTION SET OVERVIEW
MOTOROLA
5-7
5.13 Shift and Rotate Instructions
There are shifts and rotates for all accumulators and for memory bytes. All pass the
shifted-out bit through the C status bit to facilitate multiple-byte operations. Because
logical and arithmetic left shifts are identical, there are no separate logical left shift operations. LSL mnemonics are assembled as ASL operations. Table 5-12 shows shift
and rotate instructions.
Table 5-12 Shift and Rotate Instructions
Logical Shifts
Mnemonic
Function
Operation
LSL
LSLA
LSLB
Logic Shift Left Memory
Logic Shift Left A
Logic Shift Left B
LSLD
Logic Shift Left D
0
C
b7
b7
A
b0
0
C
LSR
LSRA
LSRB
Logic Shift Right Memory
Logic Shift Right A
Logic Shift Right B
LSRD
Logic Shift Right D
b0
B
b0
b0
C
b7
0
b7
0
b0
A
b7
b7
b0
B
C
Arithmetic Shifts
Mnemonic
Function
Operation
ASL
ASLA
ASLB
Arithmetic Shift Left Memory
Arithmetic Shift Left A
Arithmetic Shift Left B
ASLD
Arithmetic Shift Left D
0
0
C
ASR
ASRA
ASRB
Arithmetic Shift Right Memory
Arithmetic Shift Right A
Arithmetic Shift Right B
b0
b7
C
b0
b7 A
b7
B
b0
b0
b7
C
Rotates
Mnemonic
Function
ROL
ROLA
ROLB
Rotate Left Memory Through Carry
Rotate Left A Through Carry
Rotate Left B Through Carry
ROR
RORA
RORB
Rotate Right Memory Through Carry
Rotate Right A Through Carry
Rotate Right B Through Carry
MOTOROLA
5-8
INSTRUCTION SET OVERVIEW
Operation
b0
b7
C
b7
b0
C
CPU12
REFERENCE MANUAL
5.14 Fuzzy Logic Instructions
The CPU12 instruction set includes instructions that support efficient processing of
fuzzy logic operations. The descriptions of fuzzy logic instructions that follow are functional overviews. Table 5-13 summarizes the fuzzy logic instructions. Refer to SECTION 9 FUZZY LOGIC SUPPORT for detailed discussion.
5.14.1 Fuzzy Logic Membership Instruction
The MEM instruction is used during the fuzzification process. During fuzzification, current system input values are compared against stored input membership functions to
determine the degree to which each label of each system input is true. This is accomplished by finding the y value for the current input on a trapezoidal membership function for each label of each system input. The MEM instruction performs this calculation
for one label of one system input. To perform the complete fuzzification task for a system, several MEM instructions must be executed, usually in a program loop structure.
5.14.2 Fuzzy Logic Rule Evaluation Instructions
The REV and REVW instructions perform MIN-MAX rule evaluations that are central
elements of a fuzzy logic inference program. Fuzzy input values are processed using
a list of rules from the knowledge base to produce a list of fuzzy outputs. The REV instruction treats all rules as equally important. The REVW instruction allows each rule
to have a separate weighting factor. The two rule evaluation instructions also differ in
the way rules are encoded into the knowledge base. Because they require a number
of cycles to execute, rule evaluation instructions can be interrupted. Once the interrupt
has been serviced, instruction execution resumes at the point the interrupt occurred.
5.14.3 Fuzzy Logic Averaging Instruction
The WAV instruction provides a facility for weighted average calculations. In order to
be usable, the fuzzy outputs produced by rule evaluation must be defuzzified to produce a single output value which represents the combined effect of all of the fuzzy outputs. Fuzzy outputs correspond to the labels of a system output and each is defined
by a membership function in the knowledge base. The CPU12 typically uses singletons for output membership functions rather than the trapezoidal shapes used for inputs. As with inputs, the x-axis represents the range of possible values for a system
output. Singleton membership functions consist of the x-axis position for a label of the
system output. Fuzzy outputs correspond to the y-axis height of the corresponding
output membership function. The WAV instruction calculates the numerator and denominator sums for a weighted average of the fuzzy outputs. Because WAV requires
a number of cycles to execute, it can be interrupted. The wavr pseudo-instruction
causes execution to resume at the point it was interrupted.
CPU12
REFERENCE MANUAL
INSTRUCTION SET OVERVIEW
MOTOROLA
5-9
Table 5-13 Fuzzy Logic Instructions
Mnemonic
Function
Operation
µ (grade) ⇒ M(Y)
(X) + 4 ⇒ X; (Y) + 1 ⇒ Y; A unchanged
if (A) < P1 or (A) > P2, then µ = 0, else
µ = MIN [((A) – P1) × S1, (P2 – (A)) × S2, $FF]
MEM
Membership Function
where:
A = current crisp input value
X points to a four byte data structure that describes a trapezoidal membership function as base intercept points
and slopes (P1, P2, S1, S2)
Y points at fuzzy input (RAM location)
See instruction details for special cases
Find smallest rule input (MIN)
Store to rule outputs unless fuzzy output is larger (MAX)
Rules are unweighted
REV
MIN-MAX Rule Evaluation
Each rule input is an 8-bit offset from a base address in Y
Each rule output is an 8-bit offset from a base address in Y
$FE separates rule inputs from rule outputs
$FF terminates the rule list
REV can be interrupted
Find smallest rule input (MIN)
Multiply by a rule weighting factor (optional)
Store to rule outputs unless fuzzy output is larger (MAX)
REVW
MIN-MAX Rule Evaluation
Each rule input is the 16-bit address of a fuzzy input
Each rule output is the 16-bit address of a fuzzy output
Address $FFFE separates rule inputs from rule outputs
$FFFF terminates the rule list
Weights are 8-bit values in a separate table
REVW can be interrupted
B
WAV
∑ S i F i ⇒ Y:D
Calculates Numerator (Sum of Products)
and Denominator (Sum of Weights) for
Weighted Average Calculation
Results Are Placed in Correct Registers
For EDIV immediately After WAV
i =1
B
∑ Fi ⇒ X
i =1
wavr
MOTOROLA
5-10
Resumes Execution of
Interrupted WAV Instruction
Recover immediate results from stack
rather than initializing them to zero.
INSTRUCTION SET OVERVIEW
CPU12
REFERENCE MANUAL
5.15 Maximum and Minimum Instructions
These instructions are used to make comparisons between an accumulator and a
memory location. These instructions can be used for linear programming operations,
such as Simplex-method optimization or for fuzzification.
MAX and MIN instructions use accumulator A to perform 8-bit comparisons, while
EMAX and EMIN instructions use accumulator D to perform 16-bit comparisons. The
result (maximum or minimum value) can be stored in the accumulator (EMAXD,
EMIND, MAXA, MINA) or the memory address (EMAXM, EMINM, MAXM, MINM).
Table 5-14 is a summary of minimum and maximum instructions.
Table 5-14 Minimum and Maximum Instructions
Minimum Instructions
Mnemonic
Function
Operation
EMIND
MIN of Two Unsigned 16-Bit Values
Result to Accumulator
MIN ((D), (M : M + 1)) ⇒ D
EMINM
MIN of Two Unsigned 16-Bit Values
Result to Memory
MIN ((D), (M : M + 1)) ⇒ M : M+1
MINA
MIN of Two Unsigned 8-Bit Values
Result to Accumulator
MIN ((A), (M)) ⇒ A
MINM
MIN of Two Unsigned 8-Bit Values
Result to Memory
MIN ((A), (M)) ⇒ M
Maximum Instructions
Mnemonic
Function
Operation
EMAXD
MAX of Two Unsigned 16-Bit Values
Result to Accumulator
MAX ((D), (M : M + 1)) ⇒ D
EMAXM
MAX of Two Unsigned 16-Bit Values
Result to Memory
MAX ((D), (M : M + 1)) ⇒ M : M + 1
MAXA
MAX of Two Unsigned 8-Bit Values
Result to Accumulator
MAX ((A), (M)) ⇒ A
MAXM
MAX of Two Unsigned 8-Bit Values
Result to Memory
MAX((A), (M)) ⇒ M
5.16 Multiply and Accumulate Instruction
The EMACS instruction multiplies two 16-bit operands stored in memory and accumulates the 32-bit result in a third memory location. EMACS can be used to implement
simple digital filters and defuzzification routines that use 16-bit operands. The WAV
instruction incorporates an 8- to 16-bit multiply and accumulate operation that obtains
a numerator for the weighted average calculation. The EMACS instruction can automate this portion of the averaging operation when 16-bit operands are used. Table 515 shows the EMACS instruction.
CPU12
REFERENCE MANUAL
INSTRUCTION SET OVERVIEW
MOTOROLA
5-11
Table 5-15 Multiply and Accumulate Instructions
Mnemonic
Function
Operation
EMACS
Multiply and Accumulate (Signed)
16 × 16 Bit ⇒ 32 Bit
((M(X):M(X+1)) × (M(Y):M(Y+1))) + (M ~ M + 3) ⇒ M ~ M + 3
5.17 Table Interpolation Instructions
The TBL and ETBL instructions interpolate values from tables stored in memory. Any
function that can be represented as a series of linear equations can be represented by
a table of appropriate size. Interpolation can be used for many purposes, including tabular fuzzy logic membership functions. TBL uses 8-bit table entries and returns an 8bit result; ETBL uses 16-bit table entries and returns a 16-bit result. Use of indexed
addressing mode provides great flexibility in structuring tables.
Consider each of the successive values stored in a table to be y-values for the endpoint of a line segment. The value in the B accumulator before instruction execution
begins represents change in x from the beginning of the line segment to the lookup
point divided by total change in x from the beginning to the end of the line segment. B
is treated as an 8-bit binary fraction with radix point left of the MSB, so each line segment is effectively divided into 256 smaller segments. During instruction execution, the
change in y between the beginning and end of the segment (a signed byte for TBL or
a signed word for ETBL) is multiplied by the content of the B accumulator to obtain an
intermediate delta-y term. The result (stored in the A accumulator by TBL, and in the
D accumulator by ETBL) is the y-value of the beginning point plus the signed intermediate delta-y value. Table 5-16 shows the table interpolation instructions.
Table 5-16 Table Interpolation Instructions
Mnemonic
Function
Operation
ETBL
16-Bit Table Lookup and Interpolate
(no indirect addressing modes allowed)
(M : M + 1) + [(B) × ((M + 2 : M + 3) – (M : M + 1))] ⇒ D
Initialize B, and index before ETBL.
<ea> points to the first table entry (M : M + 1)
B is fractional part of lookup value
TBL
8-Bit Table Lookup and Interpolate
(no indirect addressing modes allowed.)
(M) + [(B) × ((M + 1) – (M))] ⇒ A
Initialize B, and index before TBL.
<ea> points to the first 8-bit table entry (M)
B is fractional part of lookup value.
MOTOROLA
5-12
INSTRUCTION SET OVERVIEW
CPU12
REFERENCE MANUAL
5.18 Branch Instructions
Branch instructions cause sequence to change when specific conditions exist. The
CPU12 uses three kinds of branch instructions. These are short branches, long
branches, and bit-conditional branches.
Branch instructions can also be classified by the type of condition that must be satisfied in order for a branch to be taken. Some instructions belong to more than one classification.
Unary branch instructions always execute.
Simple branches are taken when a specific bit in the condition code register is in a
specific state as a result of a previous operation.
Unsigned branches are taken when comparison or test of unsigned quantities results in a specific combination of condition code register bits.
Signed branches are taken when comparison or test of signed quantities results in
a specific combination of condition code register bits.
5.18.1 Short Branch Instructions
Short branch instructions operate as follows. When a specified condition is met, a
signed 8-bit offset is added to the value in the program counter. Program execution
continues at the new address.
The numeric range of short branch offset values is $80 (–128) to $7F (127) from the
address of the next memory location after the offset value.
Table 5-17 is a summary of the short branch instructions.
5.18.2 Long Branch Instructions
Long branch instructions operate as follows. When a specified condition is met, a
signed 16-bit offset is added to the value in the program counter. Program execution
continues at the new address. Long branches are used when large displacements between decision-making steps are necessary.
The numeric range of long branch offset values is $8000 (–32,768) to $7FFF (32,767)
from the address of the next memory location after the offset value. This permits
branching from any location in the standard 64-Kbyte address map to any other location in the map.
Table 5-18 is a summary of the long branch instructions.
CPU12
REFERENCE MANUAL
INSTRUCTION SET OVERVIEW
MOTOROLA
5-13
Table 5-17 Short Branch Instructions
Unary Branches
Mnemonic
Function
Equation or Operation
BRA
Branch Always
1=1
BRN
Branch Never
1=0
Simple Branches
Mnemonic
Function
Equation or Operation
BCC
Branch if Carry Clear
C=0
BCS
Branch if Carry Set
C=1
BEQ
Branch if Equal
Z=1
BMI
Branch if Minus
N=1
BNE
Branch if Not Equal
Z=0
BPL
Branch if Plus
N=0
BVC
Branch if Overflow Clear
V=0
BVS
Branch if Overflow Set
V=1
Unsigned Branches
Mnemonic
Function
Relation
Equation or Operation
BHI
Branch if Higher
R>M
C+Z=0
BHS
Branch if Higher or Same
R≥M
C=0
BLO
Branch if Lower
R<M
C=1
BLS
Branch if Lower or Same
R≤M
C+Z=1
Signed Branches
Mnemonic
Function
Relation
BGE
Branch if Greater Than or Equal
R≥M
N⊕V=0
BGT
Branch if Greater Than
R>M
Z + (N ⊕ V) = 0
BLE
Branch if Less Than or Equal
R≤M
Z + (N ⊕ V) = 1
BLT
Branch if Less Than
R<M
N⊕V=1
MOTOROLA
5-14
INSTRUCTION SET OVERVIEW
Equation or Operation
CPU12
REFERENCE MANUAL
Table 5-18 Long Branch Instructions
Unary Branches
Mnemonic
Function
Equation or Operation
LBRA
Long Branch Always
1=1
LBRN
Long Branch Never
1=0
Simple Branches
Mnemonic
Function
Equation or Operation
LBCC
Long Branch if Carry Clear
C=0
LBCS
Long Branch if Carry Set
C=1
LBEQ
Long Branch if Equal
Z=1
LBMI
Long Branch if Minus
N=1
LBNE
Long Branch if Not Equal
Z=0
LBPL
Long Branch if Plus
N=0
LBVC
Long Branch if Overflow Clear
V=0
LBVS
Long Branch if Overflow Set
V=1
Unsigned Branches
Mnemonic
Function
Equation or Operation
LBHI
Long Branch if Higher
C+Z=0
LBHS
Long Branch if Higher or Same
C=0
LBLO
Long Branch if Lower
Z=1
LBLS
Long Branch if Lower or Same
C+Z=1
Signed Branches
Mnemonic
Function
LBGE
Long Branch if Greater Than or Equal
N⊕V=0
LBGT
Long Branch if Greater Than
Z + (N ⊕ V) = 0
LBLE
Long Branch if Less Than or Equal
Z + (N ⊕ V) = 1
LBLT
Long Branch if Less Than
N⊕V=1
CPU12
REFERENCE MANUAL
INSTRUCTION SET OVERVIEW
Equation or Operation
MOTOROLA
5-15
5.18.3 Bit Condition Branch Instructions
These branches are taken when bits in a memory byte are in a specific state. A mask
operand is used to test the location. If all bits in that location that correspond to ones
in the mask are set (BRSET) or cleared (BRCLR), the branch is taken.
The numeric range of 8-bit offset values is $80 (–128) to $7F (127) from the address
of the next memory location after the offset value. Table 5-19 is a summary of bit-condition branches.
Table 5-19 Bit Condition Branch Instructions
Mnemonic
Function
Equation or Operation
BRCLR
Branch if Selected Bits Clear
(M) • (mm) = 0
BRSET
Branch if Selected Bits Set
(M) • (mm) = 0
5.19 Loop Primitive Instructions
The loop primitives can also be thought of as counter branches. The instructions test
a counter value in a register or accumulator (A, B, D, X, Y, or SP) for zero or nonzero
value as a branch condition. There are predecrement, preincrement and test-only versions of these instructions.
The numeric range of 8-bit offset values is $80 (–128) to $7F (127) from the address
of the next memory location after the offset value. Table 5-20 is a summary of loop
primitive branches.
Table 5-20 Loop Primitive Instructions
Mnemonic
Function
Equation or Operation
DBEQ
Decrement counter and branch if = 0
(counter = A, B, D, X, Y, or SP)
(counter) – 1⇒ counter
If (counter) = 0, then branch
else continue to next instruction
DBNE
Decrement counter and branch if ≠ 0
(counter = A, B, D, X, Y, or SP)
(counter) – 1⇒ counter
If (counter) not = 0, then branch
else continue to next instruction
IBEQ
Increment counter and branch if = 0
(counter = A, B, D, X, Y, or SP)
(counter) + 1⇒ counter
If (counter) = 0, then branch
else continue to next instruction
IBNE
Increment counter and branch if ≠ 0
(counter = A, B, D, X, Y, or SP)
(counter) + 1⇒ counter
If (counter) not = 0, then branch
else continue to next instruction
TBEQ
Test counter and branch if = 0
(counter = A, B, D, X,Y, or SP)
If (counter) = 0, then branch
else continue to next instruction
TBNE
Test counter and branch if ≠ 0
(counter = A, B, D, X,Y, or SP)
If (counter) not = 0, then branch
else continue to next instruction
MOTOROLA
5-16
INSTRUCTION SET OVERVIEW
CPU12
REFERENCE MANUAL
5.20 Jump and Subroutine Instructions
Jump instructions cause immediate changes in sequence. The JMP instruction loads
the PC with an address in the 64-Kbyte memory map, and program execution continues at that address. The address can be provided as an absolute 16-bit address or
determined by various forms of indexed addressing.
Subroutine instructions optimize the process of transferring control to a code segment
that performs a particular task. A short branch (BSR), a jump (JSR), or an expandedmemory call (CALL) can be used to initiate subroutines. There is no LBSR instruction,
but a PC-relative JSR performs the same function. A return address is stacked, then
execution begins at the subroutine address. Subroutines in the normal 64-Kbyte address space are terminated with an RTS instruction. RTS unstacks the return address
so that execution resumes with the instruction after BSR or JSR.
The CALL instruction is intended for use with expanded memory. CALL stacks the value in the PPAGE register and the return address, then writes a new value to PPAGE
to select the memory page where the subroutine resides. The page value is an immediate operand in all addressing modes except indexed indirect modes; in these modes,
an operand points to locations in memory where the new page value and subroutine
address are stored. The RTC instruction is used to terminate subroutines in expanded
memory. RTC unstacks the PPAGE value and the return address so that execution
resumes with the next instruction after CALL. For software compatibility, CALL and
RTC execute correctly on devices that do not have expanded addressing capability.
Table 5-21 summarizes the jump and subroutine instructions.
Table 5-21 Jump and Subroutine Instructions
Mnemonic
Function
Operation
Branch to Subroutine
SP – 2 ⇒ SP
RTNH : RTNL ⇒ M(SP) : M(SP+1)
Subroutine address ⇒ PC
CALL
Call Subroutine in Expanded Memory
SP – 2 ⇒ SP
RTNH:RTNL⇒ M(SP) : M(SP+1)
SP – 1 ⇒ SP
(PPAGE) ⇒ M(SP)
Page ⇒ PPAGE
Subroutine address ⇒ PC
JMP
Jump
Subroutine Address ⇒ PC
JSR
Jump to Subroutine
SP – 2 ⇒ SP
RTNH : RTNL⇒ M(SP) : M(SP+1)
Subroutine address ⇒ PC
RTC
Return from Call
M(SP) : M(SP+1) ⇒ PCH : PCL
SP + 2 ⇒ SP
Return from Subroutine
M(SP) ⇒ PPAGE
SP + 1 ⇒ SP
M(SP) : M(SP+1) ⇒ PCH : PCL
SP + 2 ⇒ SP
BSR
RTS
CPU12
REFERENCE MANUAL
INSTRUCTION SET OVERVIEW
MOTOROLA
5-17
5.21 Interrupt Instructions
Interrupt instructions handle transfer of control to a routine that performs a critical task.
Software interrupts are a type of exception. SECTION 7 EXCEPTION PROCESSING
covers interrupt exception processing in detail.
The SWI instruction initiates synchronous exception processing. First, the return PC
value is stacked. After CPU context is stacked, execution continues at the address
pointed to by the SWI vector.
Execution of the SWI instruction causes an interrupt without an interrupt service request. SWI is not inhibited by global mask bits I and X in the CCR, and execution of
SWI sets the I mask bit. Once an SWI interrupt begins, maskable interrupts are inhibited until the I bit in the CCR is cleared. This typically occurs when an RTI instruction
at the end of the SWI service routine restores context.
The CPU12 uses the software interrupt for unimplemented opcode trapping. There are
opcodes in all 256 positions in the page 1 opcode map, but only 54 of the 256 positions
on page 2 of the opcode map are used. If the CPU attempts to execute one of the unimplemented opcodes on page 2, an opcode trap interrupt occurs. Traps are essentially interrupts that share the $FFF8:$FFF9 interrupt vector.
The RTI instruction is used to terminate all exception handlers, including interrupt service routines. RTI first restores the CCR, B:A, X, Y, and the return address from the
stack. If no other interrupt is pending, normal execution resumes with the instruction
following the last instruction that executed prior to interrupt.
Table 5-22 is a summary of interrupt instructions.
Table 5-22 Interrupt Instructions
Mnemonic
RTI
SWI
TRAP
MOTOROLA
5-18
Function
Operation
Return from Interrupt
(M(SP)) ⇒ CCR; (SP) + $0001 ⇒ SP
(M(SP) : M(SP+1)) ⇒ B : A; (SP) + $0002 ⇒ SP
(M(SP) : M(SP+1)) ⇒ XH : XL; (SP) + $0004 ⇒ SP
(M(SP) : M(SP+1)) ⇒ PCH : PCL; (SP) + $0002 ⇒ SP
(M(SP) : M(SP+1)) ⇒ YH : YL; (SP) + $0004 ⇒ SP
Software Interrupt
SP – 2 ⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; YH : YL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; XH : XL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; B : A ⇒ M(SP) : M(SP+1)
SP – 1 ⇒ SP; CCR ⇒ M(SP)
Software Interrupt
SP – 2 ⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; YH : YL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; XH : XL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; B : A ⇒ M(SP) : M(SP+1)
SP – 1 ⇒ SP; CCR ⇒ M(SP)
INSTRUCTION SET OVERVIEW
CPU12
REFERENCE MANUAL
5.22 Index Manipulation Instructions
These instructions perform 8- and 16-bit operations on the three index registers and
accumulators, other registers, or memory, as shown in Table 5-23.
Table 5-23 Index Manipulation Instructions
Addition Instructions
Mnemonic
Function
Operation
ABX
Add B to X
(B) + (X) ⇒ X
ABY
Add B to Y
(B) + (Y) ⇒ Y
Compare Instructions
Mnemonic
Function
Operation
CPS
Compare SP to Memory
(SP) – (M : M + 1)
CPX
Compare X to Memory
(X) – (M : M + 1)
CPY
Compare Y to Memory
(Y) – (M : M + 1)
Load Instructions
Mnemonic
Function
Operation
LDS
Load SP from Memory
M : M+1 ⇒ SP
LDX
Load X from Memory
(M : M + 1) ⇒ X
LDY
Load Y from Memory
(M : M + 1) ⇒ Y
LEAS
Load Effective Address into SP
Effective Address ⇒ SP
LEAX
Load Effective Address into X
Effective Address ⇒ X
LEAY
Load Effective Address into Y
Effective Address ⇒ Y
Store Instructions
Mnemonic
Function
Operation
STS
Store SP in Memory
(SP) ⇒ M:M+1
STX
Store X in Memory
(X) ⇒ M : M + 1
STY
Store Y in Memory
(Y) ⇒ M : M + 1
Mnemonic
Function
Operation
TFR
Transfer Register to Register
(A, B, CCR, D, X, Y, or SP) ⇒ A, B, CCR, D, X, Y, or SP
TSX
Transfer SP to X
(SP) ⇒ X
TSY
Transfer SP to Y
(SP) ⇒ Y
TXS
Transfer X to SP
(X) ⇒ SP
TYS
Transfer Y to SP
(Y) ⇒ SP
Transfer Instructions
Exchange Instructions
Mnemonic
Function
Operation
EXG
Exchange Register to Register
(A, B, CCR, D, X, Y, or SP) ⇔ (A, B, CCR, D, X, Y, or SP)
XGDX
EXchange D with X
(D) ⇔ (X)
XGDY
EXchange D with Y
(D) ⇔ (Y)
CPU12
REFERENCE MANUAL
INSTRUCTION SET OVERVIEW
MOTOROLA
5-19
5.23 Stacking Instructions
There are two types of stacking instructions, as shown in Table 5-24. Stack pointer
instructions use specialized forms of mathematical and data transfer instructions to
perform stack pointer manipulation. Stack operation instructions save information on
and retrieve information from the system stack.
Table 5-24 Stacking Instructions
Stack Pointer Instructions
Mnemonic
Function
Operation
CPS
Compare SP to Memory
(SP) – (M : M + 1)
DES
Decrement SP
(SP) – 1 ⇒ SP
INS
Increment SP
(SP) + 1 ⇒ SP
LDS
Load SP
(M : M + 1) ⇒ SP
LEAS
Load Effective Address into SP
Effective Address ⇒ SP
STS
Store SP
(SP) ⇒ M : M + 1
TSX
Transfer SP to X
(SP) ⇒ X
TSY
Transfer SP to Y
(SP) ⇒ Y
TXS
Transfer X to SP
(X) ⇒ SP
TYS
Transfer Y to SP
(Y) ⇒ SP
Stack Operation Instructions
Mnemonic
Function
Operation
PSHA
Push A
(SP) – 1 ⇒ SP; (A) ⇒ M(SP)
PSHB
Push B
(SP) – 1 ⇒ SP; (B) ⇒ M(SP)
PSHC
Push CCR
(SP) – 1 ⇒ SP; (A) ⇒ M(SP)
PSHD
Push D
(SP) – 2 ⇒ SP; (A : B) ⇒ M(SP) : M(SP+1)
PSHX
Push X
(SP) – 2 ⇒ SP; (X) ⇒ M(SP) : M(SP+1)
PSHY
Push Y
(SP) – 2 ⇒ SP; (Y) ⇒ M(SP) : M(SP+1)
PULA
Pull A
(M(SP)) ⇒ A; (SP) + 1 ⇒ SP
PULB
Pull B
(M(SP)) ⇒ B; (SP) + 1 ⇒ SP
PULC
Pull CCR
(M(SP)) ⇒ CCR; (SP) + 1 ⇒ SP
PULD
Pull D
(M(SP) : M(SP+1)) ⇒ A : B; (SP) + 2 ⇒ SP
PULX
Pull X
(M(SP) : M(SP+1)) ⇒ X; (SP) + 2 ⇒ SP
PULY
Pull Y
(M(SP) : M(SP+1)) ⇒ Y; (SP) + 2 ⇒ SP
5.24 Pointer and Index Calculation Instructions
The load effective address instructions allow 5-, 8-, or 16-bit constants, or the contents
of 8-bit accumulators A and B or 16-bit accumulator D to be added to the contents of
the X and Y index registers, the SP, or the PC. Table 5-25 is a summary of pointer and
index instructions.
MOTOROLA
5-20
INSTRUCTION SET OVERVIEW
CPU12
REFERENCE MANUAL
Table 5-25 Pointer and Index Calculation Instructions
Mnemonic
Function
Operation
LEAS
Load Result of Indexed Addressing Mode
Effective Address Calculation
into Stack Pointer
r ± Constant ⇒ SP or
(r) + (Accumulator) ⇒ SP
r = X, Y, SP, or PC
LEAX
Load Result of Indexed Addressing Mode
Effective Address Calculation
into X Index Register
r ± Constant ⇒X or
(r) + (Accumulator) ⇒X
r = X, Y, SP, or PC
LEAY
Load Result of Indexed Addressing Mode
Effective Address Calculation
into Y Index Register
r ± Constant ⇒Y or
(r) + (Accumulator) ⇒ Y
r = X, Y, SP, or PC
5.25 Condition Code Instructions
Condition code instructions are special forms of mathematical and data transfer instructions that can be used to change the condition code register. Table 5-26 shows
instructions that can be used to manipulate the CCR.
Table 5-26 Condition Codes Instructions
Mnemonic
Function
Operation
ANDCC
Logical AND CCR with Memory
(CCR) • (M) ⇒ CCR
CLC
Clear C Bit
0⇒C
CLI
Clear I Bit
0⇒I
CLV
Clear V Bit
0⇒V
ORCC
Logical OR CCR with Memory
(CCR) + (M) ⇒ CCR
PSHC
Push CCR onto Stack
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)
PULC
Pull CCR from Stack
(M(SP)) ⇒ CCR; (SP) + 1 ⇒ SP
SEC
Set C Bit
1⇒C
SEI
Set I Bit
1⇒I
SEV
Set V Bit
1⇒V
TAP
Transfer A to CCR
(A) ⇒ CCR
TPA
Transfer CCR to A
(CCR) ⇒ A
5.26 Stop and Wait Instructions
As shown in Table 5-27, there are two instructions that put the CPU12 in an inactive
state that reduces power consumption.
The stop instruction (STOP) stacks a return address and the contents of CPU registers
and accumulators, then halts all system clocks.
The wait instruction (WAI) stacks a return address and the contents of CPU registers
and accumulators, then waits for an interrupt service request; however, system clock
signals continue to run.
CPU12
REFERENCE MANUAL
INSTRUCTION SET OVERVIEW
MOTOROLA
5-21
Both STOP and WAI require that either an interrupt or a reset exception occur before
normal execution of instructions resumes. Although both instructions require the same
number of clock cycles to resume normal program execution after an interrupt service
request is made, restarting after a STOP requires extra time for the oscillator to reach
operating speed.
Table 5-27 Stop and Wait Instructions
Mnemonic
STOP
WAI
Function
Operation
Stop
SP – 2 ⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; YH : YL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; XH : XL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; B : A ⇒ M(SP) : M(SP+1)
SP – 1 ⇒ SP; CCR ⇒ M(SP)
STOP CPU Clocks
Wait for Interrupt
SP – 2 ⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; YH : YL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; XH : XL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; B : A ⇒ M(SP) : M(SP+1)
SP – 1 ⇒ SP; CCR ⇒ M(SP)
5.27 Background Mode and Null Operations
Background debug mode is a special CPU12 operating mode that is used for system
development and debugging. Executing BGND when BDM is enabled puts the CPU12
in this mode. For complete information refer to SECTION 8 DEVELOPMENT AND
DEBUG SUPPORT.
Null operations are often used to replace other instructions during software debugging.
Replacing conditional branch instructions with BRN, for instance, permits testing a decision-making routine without actually taking the branches.
Table 5-28 shows the BGND and NOP instructions.
Table 5-28 Background Mode and Null Operation Instructions
Mnemonic
Function
Operation
BGND
Enter Background Debug Mode
If BDM enabled, enter BDM;
else, resume normal processing
BRN
Branch Never
Does not branch
LBRN
Long Branch Never
Does not branch
NOP
Null operation
—
MOTOROLA
5-22
INSTRUCTION SET OVERVIEW
CPU12
REFERENCE MANUAL
SECTION 6
INSTRUCTION GLOSSARY
This section is a comprehensive reference to the CPU12 instruction set.
6.1 Glossary Information
The glossary contains an entry for each assembler mnemonic, in alphabetic order.
Figure 6-1 is a representation of a glossary page.
LDX
MNEMONIC
Load Inde
Operation:
(M : M + 1) ⇒ X
SYMBOLIC DESCRIPTION
OF OPERATION
Description:
Loads the most significa
memory at the addres
DETAILED DESCRIPTION
OF OPERATION
Condition Codes and Boolean Form
S
X
H
—
—
∆
N: Set if MSB of resu
Z: Set if result is $00
EFFECT ON
CONDITION CODE REGISTER
STATUS BITS
V: 0; Cleared.
Addressing Modes, Machine Code, an
DETAILED SYNTAX
AND
CYCLE-BY-CYCLE
OPERATION
Source Form
Address Mode
Obje
LDX #opr16i
LDX opr8a
LDX opr16a
LDX oprx0_xysp
LDX oprx9,xysp
LDX oprx16,xysp
LDX [D,xysp]
LDX [oprx16,xysp]
IMM
DIR
EXT
ID X
IDX1
IDX2
[D,IDX]
[IDX2]
CE jj
DE d
FE h
EE
E
E
EX GLO PG
Figure 6-1 Example Glossary Page
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-1
Each entry contains symbolic and textual descriptions of operation, information concerning the effect of operation on status bits in the condition code register, and a table
that describes assembler syntax, cycle count, and cycle-by-cycle execution of the instruction.
6.2 Condition Code Changes
The following special characters are used to describe the effects of instruction execution on the status bits in the condition codes register.
– — Status bit not affected by operation.
0 — Status bit cleared by operation.
1 — Status bit set by operation.
∆ — Status bit affected by operation.
⇓ — Status bit may be cleared or remain set, but is not set by operation.
⇑ — Status bit may be set or remain cleared, but is not cleared by operation.
? — Status bit may be changed by operation but the final state is not defined.
! — Status bit used for a special purpose.
6.3 Object Code Notation
The digits 0 to 9 and the upper case letters A to F are used to express hexadecimal
values. Pairs of lower case letters represent the 8-bit values as described below.
dd — 8-bit direct address $0000 to $00FF. (High byte assumed to be $00).
ee — High-order byte of a 16-bit constant offset for indexed addressing.
eb — Exchange/Transfer post-byte.
ff — Low-order eight bits of a 9-bit signed constant offset for indexed addressing, or
low-order byte of a 16-bit constant offset for indexed addressing.
hh — High-order byte of a 16-bit extended address.
ii — 8-bit immediate data value.
jj — High-order byte of a 16-bit immediate data value.
kk — Low-order byte of a 16-bit immediate data value.
lb — Loop primitive (DBNE) post-byte.
ll — Low-order byte of a 16-bit extended address.
mm — 8-bit immediate mask value for bit manipulation instructions.
Set bits indicate bits to be affected.
pg — Program overlay page (bank) number used in CALL instruction.
qq — High-order byte of a 16-bit relative offset for long branches.
tn — Trap number $30–$39 or $40–$FF.
rr — Signed relative offset $80 (–128) to $7F (+127).
Offset relative to the byte following the relative offset byte, or
low-order byte of a 16-bit relative offset for long branches.
xb — Indexed addressing post-byte.
MOTOROLA
6-2
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
6.4 Source Forms
The glossary pages provide only essential information about assembler source forms.
Assemblers generally support a number of assembler directives, allow definition of
program labels, and have special conventions for comments. For complete information about writing source files for a particular assembler, refer to the documentation
provided by the assembler vendor.
Assemblers are typically very flexible about the use of spaces and tabs. Often, any
number of spaces or tabs can be used where a single space is shown on the glossary
pages. Spaces and tabs are also normally allowed before and after commas. When
program labels are used, there must also be at least one tab or space before all instruction mnemonics. This required space is not apparent in the source forms.
Everything in the source forms columns, except expressions in italic characters, is literal information which must appear in the assembly source file exactly as shown. The
initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs
(#), parentheses, square brackets ( [ or ] ), plus signs (+), minus signs (–), and the register designation D (as in [D,... ), are literal characters.
Groups of italic characters in the columns represent variable information to be supplied by the programmer. These groups can include any alphanumeric character or the
underscore character, but cannot include a space or comma. For example, the groups
xysp and oprx0_xysp are both valid, but the two groups oprx0 xysp are not valid because there is a space between them. Permitted syntax is described below.
The definition of a legal label or expression varies from assembler to assembler. Assemblers also vary in the way CPU registers are specified. Refer to assembler documentation for detailed information. Recommended register designators are a, A, b, B,
ccr, CCR, d, D, x, X, y, Y, sp, SP, pc, and PC.
abc — Any one legal register designator for accumulators A or B or the CCR.
abcdxys — Any one legal register designator for accumulators A or B, the CCR, the double
accumulator D, index registers X or Y, or the SP. Some assemblers may accept
t2, T2, t3, or T3 codes in certain cases of transfer and exchange instructions, but
these forms are intended for Motorola use only.
abd — Any one legal register designator for accumulators A or B or the double accumulator D.
abdxys — Any one legal register designator for accumulators A or B, the double accumulator
D, index register X or Y, or the SP.
dxys — Any one legal register designation for the double accumulator D, index registers X
or Y, or the SP.
msk8 — Any label or expression that evaluates to an 8-bit value. Some assemblers require
a # symbol before this value.
opr8i — Any label or expression that evaluates to an 8-bit immediate value.
opr16i — Any label or expression that evaluates to a 16-bit immediate value.
opr8a — Any label or expression that evaluates to an 8-bit value. The instruction treats this
8-bit value as the low order 8-bits of an address in the direct page of the 64-Kbyte
address space ($00xx).
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-3
opr16a — Any label or expression that evaluates to a 16-bit value. The instruction treats this
value as an address in the 64-Kbyte address space.
oprx0_xysp — This word breaks down into one of the following alternative forms that assemble
to an 8-bit indexed addressing postbyte code. These forms generate the same object code except for the value of the postbyte code, which is designated as xb in
the object code columns of the glossary pages. As with the source forms, treat all
commas, plus signs, and minus signs as literal syntax elements. The italicized
words used in these forms are included in this key.
oprx5,xysp
oprx3,–xys
oprx3,+xys
oprx3,xys–
oprx3,xys+
abd,xysp
oprx3 — Any label or expression that evaluates to a value in the range +1 to +8.
oprx5 — Any label or expression that evaluates to a 5-bit value in the range –16 to +15.
oprx9 — Any label or expression that evaluates to a 9-bit value in the range –256 to +255.
oprx16 — Any label or expression that evaluates to a 16-bit value. Since the CPU12 has a
16-bit address bus, this can be either a signed or an unsigned value.
page — Any label or expression that evaluates to an 8-bit value. The CPU12 recognizes
up to an 8-bit page value for memory expansion but not all MCUs that include the
CPU12 implement all of these bits. It is the programmer’s responsibility to limit the
page value to legal values for the intended MCU system. Some assemblers require a # symbol before this value.
rel8 — Any label or expression that refers to an address that is within –256 to +255 locations from the next address after the last byte of object code for the current instruction. The assembler will calculate the 8-bit signed offset and include it in the object
code for this instruction.
rel9 — Any label or expression that refers to an address that is within –512 to +511 locations from the next address after the last byte of object code for the current instruction. The assembler will calculate the 9-bit signed offset and include it in the object
code for this instruction. The sign bit for this 9-bit value is encoded by the assembler as a bit in the looping postbyte (lb) of one of the loop control instructions
DBEQ, DBNE, IBEQ, IBNE, TBEQ, or TBNE. The remaining eight bits of the offset
are included as an extra byte of object code.
rel16 — Any label or expression that refers to an address anywhere in the 64-Kbyte address space. The assembler will calculate the 16-bit signed offset between this address and the next address after the last byte of object code for this instruction,
and include it in the object code for this instruction.
trapnum — Any label or expression that evaluates to an 8-bit number in the range $30–$39 or
$40–$FF. Used for TRAP instruction.
xys — Any one legal register designation for index registers X or Y or the SP.
xysp — Any one legal register designation for index registers X or Y, the SP, or the PC.
The reference point for PC relative instructions is the next address after the last
byte of object code for the current instruction.
MOTOROLA
6-4
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
6.5 Cycle-by-Cycle Execution
This information is found in the tables at the bottom of each instruction glossary page.
Entries show how many bytes of information are accessed from different areas of
memory during the course of instruction execution. With this information and knowledge of the type and speed of memory in the system, a user can determine the execution time for any instruction in any system.
A single letter code in the column represents a single CPU cycle. Upper case letters
indicate 16-bit access cycles. There are cycle codes for each addressing mode variation of each instruction. Simply count code letters to determine the execution time of
an instruction in a best-case system. An example of a best-case system is a singlechip 16-bit system with no 16-bit off-boundary data accesses to any locations other
than on-chip RAM.
Many conditions can cause one or more instruction cycles to be stretched, but the
CPU is not aware of the stretch delays because the clock to the CPU is temporarily
stopped during these delays.
The following paragraphs explain the cycle code letters used and note conditions that
can cause each type of cycle to be stretched.
f — Free cycle. This indicates a cycle where the CPU does not require use of the
system buses. An f cycle is always one cycle of the system bus clock. These
cycles can be used by a queue controller or the background debug system to
perform single cycle accesses without disturbing the CPU.
g — Read 8-bit PPAGE register. These cycles are only used with the CALL instruction to read the current value of the PPAGE register, and are not visible on the
external bus. Since the PPAGE register is an internal 8-bit register, these cycles
are never stretched.
I — Read indirect pointer. Indexed indirect instructions use this 16-bit pointer from
memory to address the operand for the instruction. These are always 16-bit
reads but they can be either aligned or misaligned. These cycles are extended
to two bus cycles if the MCU is operating with an 8-bit external data bus and the
corresponding data is stored in external memory. There can be additional
stretching when the address space is assigned to a chip-select circuit programmed for slow memory. These cycles are also stretched if they correspond
to misaligned access to a memory that is not designed for single-cycle misaligned access.
i — Read indirect PPAGE value. These cycles are only used with indexed indirect
versions of the CALL instruction, where the 8-bit value for the memory expansion page register of the CALL destination is fetched from an indirect memory
location. These cycles are stretched only when controlled by a chip-select circuit
that is programmed for slow memory.
n — Write 8-bit PPAGE register. These cycles are only used with the CALL and RTC
instructions to write the destination value of the PPAGE register and are not visible on the external bus. Since the PPAGE register is an internal 8-bit register,
these cycles are never stretched.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-5
O — Optional cycle. Program information is always fetched as aligned 16-bit words.
When an instruction consists of an odd number of bytes, and the first byte is misaligned, an O cycle is used to make an additional program word access (P) cycle
that maintains queue order. In all other cases, the O cycle appears as a free (f)
cycle. The $18 prebyte for page two opcodes is treated as a special one-byte
instruction. If the prebyte is misaligned, the O cycle is used as a program word
access for the prebyte; if the prebyte is aligned, the O cycle appears as a free
cycle. If the remainder of the instruction consists of an odd number of bytes, another O cycle is required some time before the instruction is completed. If the O
cycle for the prebyte is treated as a P cycle, any subsequent O cycle in the same
instruction is treated as an f cycle; if the O cycle for the prebyte is treated as an
f cycle, any subsequent O cycle in the same instruction is treated as a P cycle.
Optional cycles used for program word accesses can be extended to two bus
cycles if the MCU is operating with an 8-bit external data bus and the program
is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.
Optional cycles used as free cycles are never stretched.
P — Program word access. Program information is fetched as aligned 16-bit words.
These cycles are extended to two bus cycles if the MCU is operating with an 8bit external data bus and the program is stored externally. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.
r — 8-bit data read. These cycles are stretched only when controlled by a chip-select
circuit programmed for slow memory.
R — 16-bit data read. These cycles are extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in
external memory. There can be additional stretching when the address space is
assigned to a chip-select circuit programmed for slow memory. These cycles
are also stretched if they correspond to misaligned accesses to memory that is
not designed for single-cycle misaligned access.
s — Stack 8-bit data. These cycles are stretched only when controlled by a chip-select circuit programmed for slow memory.
S — Stack 16-bit data. These cycles are extended to two bus cycles if the MCU is
operating with an 8-bit external data bus and the SP is pointing to external memory. There can be additional stretching if the address space is assigned to a
chip-select circuit programmed for slow memory. These cycles are also
stretched if they correspond to misaligned accesses to a memory that is not designed for single cycle misaligned access. The internal RAM is designed to allow single cycle misaligned word access.
w — 8-bit data write. These cycles are stretched only when controlled by a chip-select circuit programmed for slow memory.
W — 16-bit data write. These cycles are extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in
external memory. There can be additional stretching when the address space is
assigned to a chip-select circuit programmed for slow memory. These cycles
are also stretched if they correspond to misaligned access to a memory that is
not designed for single-cycle misaligned access.
u — Unstack 8-bit data. These cycles are stretched only when controlled by a chipselect circuit programmed for slow memory.
MOTOROLA
6-6
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
U — Unstack 16-bit data. These cycles are extended to two bus cycles if the MCU is
operating with an 8-bit external data bus and the SP is pointing to external memory. There can be additional stretching when the address space is assigned to
a chip-select circuit programmed for slow memory. These cycles are also
stretched if they correspond to misaligned accesses to a memory that is not designed for single-cycle misaligned access. The internal RAM is designed to allow single-cycle misaligned word access.
V — Vector fetch. Vectors are always aligned 16-bit words. These cycles are extended to two bus cycles if the MCU is operating with an 8-bit external data bus and
the program is stored in external memory. There can be additional stretching
when the address space is assigned to a chip-select circuit programmed for
slow memory.
t — 8-bit conditional read. These cycles are either data read cycles or free cycles,
depending upon the data and flow of the REVW instruction. These cycles are
only stretched when controlled by a chip-select circuit programmed for slow
memory.
T — 16-bit conditional read. These cycles are either data read cycles or free cycles,
depending upon the data and flow of the REV or REVW instruction. These cycles are extended to two bus cycles if the MCU is operating with an 8-bit external
data bus and the corresponding data is stored in external memory. There can
be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. These cycles are also stretched if they correspond to misaligned accesses to a memory that is not designed for singlecycle misaligned access.
x — 8-bit conditional write. These cycles are either data write cycles or free cycles,
depending upon the data and flow of the REV or REVW instruction. These cycles are only stretched when controlled by a chip-select circuit programmed for
slow memory.
Special Notation for Branch Taken/Not Taken Cases
PPP/P — Short branches require three cycles if taken, one cycle if not taken. Since the
instruction consists of a single word containing both an opcode and an 8-bit offset, the not-taken case is simple — the queue advances, another program word
fetch is made, and execution continues with the next instruction. The taken case
requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU
performs three program word fetches from that address.
OPPP/OPO — Long branches require four cycles if taken, three cycles if not taken. Optional cycles are required because all long branches are page two opcodes, and thus
include the $18 prebyte. The CPU12 treats the prebyte as a special 1-byte instruction. If the prebyte is misaligned, the optional cycle is used to perform a program word access; if the prebyte is aligned, the optional cycle is used to perform
a free cycle. As a result, both the taken and not-taken cases use one optional
cycle for the prebyte. In the not-taken case, the queue must advance so that execution can continue with the next instruction, and another optional cycle is required to maintain the queue. The taken case requires that the queue be refilled
so that execution can continue at a new address. First, the effective address of
the destination is determined, then the CPU performs three program word fetches from that address.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-7
6.6 Glossary
ABA
ABA
Add Accumulator B To
Accumulator A
Operation:
(A) + (B) ⇒ A
Description:
Adds the content of accumulator B to the content of accumulator A and
places the result in A. The content of B is not changed. This instruction
affects the H status bit so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
∆
–
∆
∆
∆
∆
H:
A3 • B3 + B3 • R3 + R3 • A3
Set if there was a carry from bit 3; cleared otherwise.
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
A7 • B7 • R7 + A7 • B7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
A7 • B7 + B7 • R7 + R7 • A7
Set if there was a carry from the MSB of the result; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ABA
MOTOROLA
6-8
Address Mode
INH
Object Code
18 06
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
OO
CPU12
REFERENCE MANUAL
ABX
ABX
Add Accumulator B to
Index Register X
Operation:
(B) + (X) ⇒ X
Description:
Adds the 8-bit unsigned content of accumulator B to the content of index
register X considering the possible carry out of the low-order byte of X;
places the result in X. The content of B is not changed.
This mnemonic is implemented by the LEAX B,X instruction. The LEAX
instruction allows A, B, D, or a constant to be added to X. For compatibility with the M68HC11, the mnemonic ABX is translated into the LEAX
B,X instruction by the assembler.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
ABX translates to...
IDX
1A E5
2
PP1
LEAX B,X
Notes:
1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-9
ABY
ABY
Add Accumulator B to
Index Register Y
Operation:
(B) + (Y) ⇒ Y
Description:
Adds the 8-bit unsigned content of accumulator B to the content of index
register Y considering the possible carry out of the low-order byte of Y;
places the result in Y. The content of B is not changed.
This mnemonic is implemented by the LEAY B,Y instruction. The LEAY
instruction allows A, B, D, or a constant to be added to Y. For compatibility with the M68HC11, the mnemonic ABY is translated into the LEAY
B,Y instruction by the assembler.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
ABY translates to...
IDX
19 ED
2
PP1
LEAY B,Y
Notes:
1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
MOTOROLA
6-10
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
ADCA
ADCA
Add with Carry to A
Operation:
(A) + (M) + C ⇒ A
Description:
Adds the content of accumulator A to the content of memory location M,
then adds the value of the C bit and places the result in A. This instruction affects the H status bit, so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
∆
–
∆
∆
∆
∆
H:
X3 • M3 + M3 • R3 + R3 • X3
Set if there was a carry from bit 3; cleared otherwise.
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if two’s complement overflow resulted from the operation; cleared
otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if there was a carry from the MSB of the result; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ADCA #opr8i
ADCA opr8a
ADCA opr16a
ADCA oprx0_xysp
ADCA oprx9,xysp
ADCA oprx16,xysp
ADCA [D,xysp]
ADCA [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
89
99
B9
A9
A9
A9
A9
A9
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
MOTOROLA
6-11
ADCB
ADCB
Add with Carry to B
Operation:
(B) + (M) + C ⇒ B
Description:
Adds the content of accumulator B to the content of memory location M,
then adds the value of the C bit and places the result in B. This instruction affects the H status bit, so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
∆
–
∆
∆
∆
∆
H:
X3 • M3 + M3 • R3 + R3 • X3
Set if there was a carry from bit 3; cleared otherwise.
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if two’s complement overflow resulted from the operation; cleared
otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if there was a carry from the MSB of the result; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ADCB #opr8i
ADCB opr8a
ADCB opr16a
ADCB oprx0_xysp
ADCB oprx9,xysp
ADCB oprx16,xysp
ADCB [D,xysp]
ADCB [oprx16,xysp]
MOTOROLA
6-12
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
C9
D9
F9
E9
E9
E9
E9
E9
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
ADDA
ADDA
Add without Carry to A
Operation:
(A) + (M) ⇒ A
Description:
Adds the content of memory location M to accumulator A and places the
result in A. This instruction affects the H status bit, so it is suitable for use
in BCD arithmetic operations (see DAA instruction for additional information).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
∆
–
∆
∆
∆
∆
H:
X3 • M3 + M3 • R3 + R3 • X3
Set if there was a carry from bit 3; cleared otherwise.
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if two’s complement overflow resulted from the operation; cleared
otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if there was a carry from the MSB of the result; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ADDA #opr8i
ADDA opr8a
ADDA opr16a
ADDA oprx0_xysp
ADDA oprx9,xysp
ADDA oprx16,xysp
ADDA [D,xysp]
ADDA [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
8B
9B
BB
AB
AB
AB
AB
AB
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
MOTOROLA
6-13
ADDB
ADDB
Add without Carry to B
Operation:
(B) + (M) ⇒ B
Description:
Adds the content of memory location M to accumulator B and places the
result in B. This instruction affects the H status bit, so it is suitable for use
in BCD arithmetic operations (see DAA instruction for additional information).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
∆
–
∆
∆
∆
∆
H:
X3 • M3 + M3 • R3 + R3 • X3
Set if there was a carry from bit 3; cleared otherwise.
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if two’s complement overflow resulted from the operation; cleared
otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if there was a carry from the MSB of the result; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ADDB #opr8i
ADDB opr8a
ADDB opr16a
ADDB oprx0_xysp
ADDB oprx9,xysp
ADDB oprx16,xysp
ADDB [D,xysp]
ADDB [oprx16,xysp]
MOTOROLA
6-14
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
CB
DB
FB
EB
EB
EB
EB
EB
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
ADDD
ADDD
Add Double Accumulator
Operation:
(A : B) + (M : M+1) ⇒ A : B
Description:
Adds the content of memory location M concatenated with the content of
memory location M +1 to the content of double accumulator D and places the result in D. Accumulator A forms the high-order half of 16-bit double accumulator D; accumulator B forms the low-order half.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
D15 • M15 • R15 + D15 • M15 • R15
Set if two’s complement overflow resulted from the operation; cleared
otherwise.
C:
D15 • M15 + M15 • R15 + R15 • D15
Set if there was a carry from the MSB of the result; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ADDD #opr16i
ADDD opr8a
ADDD opr16a
ADDD oprx0_xysp
ADDD oprx9,xysp
ADDD oprx16,xysp
ADDD [D,xysp]
ADDD [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
C3
D3
F3
E3
E3
E3
E3
E3
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
3
3
3
4
6
6
Access Detail
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
MOTOROLA
6-15
ANDA
ANDA
Logical AND A
Operation:
(A) • (M) ⇒ A
Description:
Performs logical AND between the content of memory location M and
the content of accumulator A. The result is placed in A. After the operation is performed, each bit of A is the logical AND of the corresponding
bits of M and of A before the operation began.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ANDA #opr8i
ANDA opr8a
ANDA opr16a
ANDA oprx0_xysp
ANDA oprx9,xysp
ANDA oprx16,xysp
ANDA [D,xysp]
ANDA [oprx16,xysp]
MOTOROLA
6-16
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
84
94
B4
A4
A4
A4
A4
A4
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
ANDB
ANDB
Logical AND B
Operation:
(B) • (M) ⇒ B
Description:
Performs logical AND between the content of memory location M and
the content of accumulator B. The result is placed in B. After the operation is performed, each bit of B is the logical AND of the corresponding
bits of M and of B before the operation began.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ANDB #opr8i
ANDB opr8a
ANDB opr16a
ANDB oprx0_xysp
ANDB oprx9,xysp
ANDB oprx16,xysp
ANDB [D,xysp]
ANDB [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
C4
D4
F4
E4
E4
E4
E4
E4
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
MOTOROLA
6-17
ANDCC
Logical AND CCR with Mask
ANDCC
Operation:
(CCR) • (Mask) ⇒ CCR
Description:
Performs bitwise logical AND between the content of a mask operand
and the content of the CCR. The result is placed in the CCR. After the
operation is performed, each bit of the CCR is the result of a logical AND
with the corresponding bits of the mask. To clear CCR bits, clear the corresponding mask bits. CCR bits that correspond to ones in the mask are
not changed by the ANDCC operation.
If the I mask bit is cleared, there is a one cycle delay before the system
allows interrupt requests. This prevents interrupts from occurring between instructions in the sequences CLI, WAI and CLI, SEI (CLI is equivalent to ANDCC #$EF).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
⇓
⇓
⇓
⇓
⇓
⇓
⇓
⇓
Condition code bits are cleared if the corresponding bit was zero before
the operation or if the corresponding bit in the mask is zero.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ANDCC #opr8i
MOTOROLA
6-18
Address Mode
IMM
Object Code
10 ii
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
CPU12
REFERENCE MANUAL
ASL
ASL
Arithmetic Shift Left Memory
(same as LSL)
Operation:
C
Description:
b7 – – – – – – b0
0
Shifts all bits of memory location M one bit position to the left. Bit 0 is
loaded with a zero. The C status bit is loaded from the most significant
bit of M.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
M7
Set if the MSB of M was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ASL opr16a
ASL oprx0_xysp
ASL oprx9,xysp
ASL oprx16,xysp
ASL [D,xysp]
ASL [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
78
68
68
68
68
68
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
3
4
5
6
6
Access Detail
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
MOTOROLA
6-19
ASLA
ASLA
Arithmetic Shift Left A
(same as LSLA)
Operation:
C
Description:
b7 – – – – – – b0
0
Shifts all bits of accumulator A one bit position to the left. Bit 0 is loaded
with a zero. The C status bit is loaded from the most significant bit of A.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
A7
Set if the MSB of A was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ASLA
MOTOROLA
6-20
Address Mode
INH
Object Code
48
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
ASLB
ASLB
Arithmetic Shift Left B
(same as LSLB)
Operation:
C
Description:
b7 – – – – – – b0
0
Shifts all bits of accumulator B one bit position to the left. Bit 0 is loaded
with a zero. The C status bit is loaded from the most significant bit of B.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
B7
Set if the MSB of B was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ASLB
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
58
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-21
ASLD
ASLD
Arithmetic Shift Left Double Accumulator
(same as LSLD)
Operation:
b7 – – – – – – b0
A
C
Description:
b7 – – – – – – b0
B
0
Shifts all bits of double accumulator D one bit position to the left. Bit 0 is
loaded with a zero. The C status bit is loaded from the most significant
bit of D.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
D15
Set if the MSB of D was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ASLD
MOTOROLA
6-22
Address Mode
INH
Object Code
59
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
ASR
ASR
Arithmetic Shift Right Memory
Operation:
C
b7 – – – – – – b0
Description:
Shifts all bits of memory location M one place to the right. Bit 7 is held
constant. Bit 0 is loaded into the C status bit. This operation effectively
divides a two’s complement value by two without changing its sign. The
carry bit can be used to round the result.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
M0
Set if the LSB of M was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ASR opr16a
ASR oprx0_xysp
ASR oprx9,xysp
ASR oprx16,xysp
ASR [D,xysp]
ASR [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
77
67
67
67
67
67
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
3
4
5
6
6
Access Detail
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
MOTOROLA
6-23
ASRA
ASRA
Arithmetic Shift Right A
Operation:
C
b7 – – – – – – b0
Description:
Shifts all bits of accumulator A one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C status bit. This operation effectively divides a two’s complement value by two without changing its sign. The
carry bit can be used to round the result.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
A0
Set if the LSB of A was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ASRA
MOTOROLA
6-24
Address Mode
INH
Object Code
47
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
ASRB
ASRB
Arithmetic Shift Right B
Operation:
C
b7 – – – – – – b0
Description:
Shifts all bits of accumulator B one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C status bit. This operation effectively divides a two’s complement value by two without changing its sign. The
carry bit can be used to round the result.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
B0
Set if the LSB of B was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ASRB
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
57
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-25
BCC
Operation:
BCC
Branch if Carry Cleared
(Same as BHS)
If C = 0, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the C status bit and branches if C = 0.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BCC rel8
REL
24 rr
3 /1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
MOTOROLA
6-26
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
BCLR
BCLR
Clear Bits in Memory
Operation:
(M) • (Mask) ⇒ M
Description:
Clears bits in location M. To clear a bit, set the corresponding bit in the
mask byte. Bits in M that correspond to zeros in the mask byte are not
changed. Mask bytes can be located at PC + 2, PC + 3, or PC + 4, depending on addressing mode used.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode1
Object Code
4D dd mm
BCLR opr8a, msk8
DIR
1D hh ll mm
EXT
BCLR opr16a, msk8
0D xb mm
IDX
BCLR oprx0_xysp, msk8
0D xb ff mm
IDX1
BCLR oprx9,xysp, msk8
0D xb ee ff mm
IDX2
BCLR oprx16,xysp, msk8
Notes:
1. Indirect forms of indexed addressing cannot be used with this instruction.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
Cycles
4
4
4
4
6
Access Detail
rPOw
rPPw
rPOw
rPwP
frPwOP
MOTOROLA
6-27
BCS
Operation:
BCS
Branch if Carry Set
(Same as BLO)
If C = 1, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the C status bit and branches if C = 1.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BCS rel8
REL
25 rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
MOTOROLA
6-28
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
BEQ
Operation:
BEQ
Branch if Equal
If Z = 1, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the Z status bit and branches if Z = 1.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BEQ rel8
REL
27 rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-29
BGE
Operation:
BGE
Branch if Greater than or Equal to Zero
If N ⊕ V = 0, then (PC) + $0002 + Rel ⇒ PC
For signed two’s complement values
if (Accumulator) ≥ (Memory), then branch
Description:
If BGE is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the signed two’s complement number in the accumulator is greater than or equal to the signed two’s complement number in memory.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BGE rel8
REL
2C rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
MOTOROLA
6-30
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
BGND
Description:
BGND
Enter Background Debug Mode
BGND operates like a software interrupt, except that no registers are
stacked. First, the current PC value is stored in internal CPU register
TMP2. Next, the BDM ROM and background register block become active. The BDM ROM contains a substitute vector, mapped to the address
of the software interrupt vector, which points to routines in the BDM
ROM that control background operation. The substitute vector is
fetched, and execution continues from the address that it points to. Finally, the CPU checks the location that TMP2 points to. If the value
stored in that location is $00 (the BGND opcode), TMP2 is incremented,
so that the instruction that follows the BGND instruction is the first instruction executed when normal program execution resumes.
For all other types of BDM entry, the CPU performs the same sequence
of operations as for a BGND instruction, but the value stored in TMP2
already points to the instruction that would have executed next had BDM
not become active. If active BDM is triggered just as a BGND instruction
is about to execute, the BDM firmware does increment TMP2, but the
change does not affect resumption of normal execution.
While BDM is active, the CPU executes debugging commands received
via a special single-wire serial interface. BDM is terminated by the execution of specific debugging commands. Upon exit from BDM, the background/boot ROM and registers are disabled, the instruction queue is
refilled starting with the return address pointed to by TMP2, and normal
processing resumes.
BDM is normally disabled to avoid accidental entry. While BDM is disabled, BGND executes as described, but the firmware causes execution
to return to the user program. Refer to SECTION 8 DEVELOPMENT
AND DEBUG SUPPORT for more information concerning BDM.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
BGND
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
00
INSTRUCTION GLOSSARY
Cycles
5
Access Detail
VfPPP
MOTOROLA
6-31
BGT
Operation:
BGT
Branch if Greater than Zero
If Z + (N ⊕ V) = 0, then (PC) + $0002 + Rel ⇒ PC
For signed two’s complement values
if (Accumulator) > (Memory), then branch
Description:
If BGT is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the signed two’s complement number in the accumulator is greater than the signed two’s complement number in memory.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BGT rel8
REL
2E rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
MOTOROLA
6-32
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
BHI
Operation:
BHI
Branch if Higher
If C + Z = 0, then (PC) + $0002 + Rel ⇒ PC
For unsigned values, if (Accumulator) > (Memory), then branch
Description:
If BHI is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the unsigned binary number in the accumulator was greater than
the unsigned binary number in memory. Generally not useful after INC/
DEC, LD/ST, TST/CLR/COM because these instructions do not affect
the C status bit.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BHI rel8
REL
22 rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-33
BHS
Operation:
BHS
Branch if Higher or Same
(Same as BCC)
If C = 0, then (PC) + $0002 + Rel ⇒ PC
For unsigned values, if (Accumulator) ≥ (Memory), then branch
Description:
If BHS is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the unsigned binary number in the accumulator was greater than
the unsigned binary number in memory. Generally not useful after INC/
DEC, LD/ST, TST/CLR/COM because these instructions do not affect
the C status bit.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BHS rel8
REL
24 rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
MOTOROLA
6-34
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
BITA
BITA
Bit Test A
Operation:
(A) • (M)
Description:
Performs bitwise logical AND on the content of accumulator A and the
content of memory location M, and modifies the condition codes accordingly. Each bit of the result is the logical AND of the corresponding bits
of the accumulator and the memory location. Neither the content of the
accumulator nor the content of the memory location is affected.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
BITA #opr8i
BITA opr8a
BITA opr16a
BITA oprx0_xysp
BITA oprx9,xysp
BITA oprx16,xysp
BITA [D,xysp]
BITA [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
85
95
B5
A5
A5
A5
A5
A5
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
MOTOROLA
6-35
BITB
BITB
Bit Test B
Operation:
(B) • (M)
Description:
Performs bitwise logical AND on the content of accumulator B and the
content of memory location M, and modifies the condition codes accordingly. Each bit of the result is the logical AND of the corresponding bits
of the accumulator and the memory location. Neither the content of the
accumulator nor the content of the memory location is affected.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
BITB #opr8i
BITB opr8a
BITB opr16a
BITB oprx0_xysp
BITB oprx9,xysp
BITB oprx16,xysp
BITB [D,xysp]
BITB [oprx16,xysp]
MOTOROLA
6-36
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
C5
D5
F5
E5
E5
E5
E5
E5
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
BLE
Operation:
BLE
Branch if Less Than or Equal to Zero
If Z + (N ⊕ V) = 1, then (PC) + $0002 + Rel ⇒ PC
For signed two’s complement numbers
if (Accumulator) ≤ (Memory), then branch
Description:
If BLE is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the two’s complement number in the accumulator was less than
or equal to the two’s complement number in memory.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BLE rel8
REL
2F rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-37
BLO
Operation:
BLO
Branch if Lower
(Same as BCS)
If C = 1, then (PC) + $0002 + Rel ⇒ PC
For unsigned values, if (Accumulator) < (Memory), then branch
Description:
If BLO is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the unsigned binary number in the accumulator is less than the
unsigned binary number in memory. Generally not useful after INC/DEC,
LD/ST, TST/CLR/COM because these instructions do not affect the C
status bit.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BLO rel8
REL
25 rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
MOTOROLA
6-38
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
BLS
Operation:
BLS
Branch if Lower or Same
If C + Z = 1, then (PC) + $0002 + Rel ⇒ PC
For unsigned values, if (Accumulator) ≤ (Memory), then branch
Description:
If BLS is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the unsigned binary number in the accumulator is less than or
equal to the unsigned binary number in memory. Generally not useful
after INC/DEC, LD/ST, TST/CLR/COM because these instructions do
not affect the C status bit.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BLS rel8
REL
23 rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-39
BLT
Operation:
BLT
Branch if Less than Zero
If N ⊕ V = 1, then (PC) + $0002 + Rel ⇒ PC
For signed two’s complement numbers
if (Accumulator) < (Memory), then branch
Description:
If BLT is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the two’s complement number in the accumulator is less than the
two’s complement number in memory.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BLT rel8
REL
2D rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
MOTOROLA
6-40
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
BMI
Operation:
BMI
Branch if Minus
If N = 1, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the N status bit and branches if N = 1.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BMI rel8
REL
2B rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-41
BNE
Operation:
BNE
Branch if Not Equal to Zero
If Z = 0, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the Z status bit and branches if Z = 0.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BNE rel8
REL
26 rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
MOTOROLA
6-42
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
BPL
Operation:
BPL
Branch if Plus
If N = 0, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the N status bit and branches if N = 0.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BPL rel8
REL
2A rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-43
BRA
BRA
Branch Always
Operation:
(PC) + $0002 + Rel ⇒ PC
Description:
Unconditional branch to an address calculated as shown in the expression. Rel is a relative offset stored as a two’s complement number in the
second byte of the branch instruction.
Execution time is longer when a conditional branch is taken than when
it is not, because the instruction queue must be refilled before execution
resumes at the new address. Since the BRA branch condition is always
satisfied, the branch is always taken, and the instruction queue must always be refilled.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
BRA rel8
MOTOROLA
6-44
Address Mode
REL
Object Code
20 rr
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
PPP
CPU12
REFERENCE MANUAL
BRCLR
Branch if Bits Cleared
BRCLR
Operation:
If (M) • (Mask) = 0, then branch
Description:
Performs bitwise logical AND on memory location M and the mask supplied with the instruction, then branches if and only if all bits with a value
of one in the mask byte correspond to bits with a value of zero in the tested byte. Mask operands can be located at PC + 1, PC + 2, or PC + 4,
depending on addressing mode. The branch offset is referenced to the
next address after the relative offset (rr) which is the last byte of the instruction object code.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
BRCLR opr8a, msk8, rel8
BRCLR opr16a, msk8, rel8
BRCLR oprx0_xysp, msk8, rel8
BRCLR oprx9,xysp, msk8, rel8
BRCLR oprx16,xysp, msk8, rel8
Address Mode1
DIR
EXT
IDX
IDX1
IDX2
Object Code
4F
1F
0F
0F
0F
rr
dd
hh
xb
xb
xb
mm
ll
mm
ff
ee
rr
mm rr
rr
mm rr
ff mm
Cycles
4
5
4
6
8
Access
Detail
rPPP
rfPPP
rPPP
rffPPP
frPffPPP
Notes:
1. Indirect forms of indexed addressing cannot be used with this instruction.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-45
BRN
BRN
Branch Never
Operation:
(PC) + $0002 ⇒ PC
Description:
Never branches. BRN is effectively a 2-byte NOP that requires one cycle
to execute. BRN is included in the instruction set to provide a complement to the BRA instruction. The instruction is useful during program debug, to negate the effect of another branch instruction without disturbing
the offset byte. A complement for BRA is also useful in compiler implementations.
Execution time is longer when a conditional branch is taken than when
it is not, because the instruction queue must be refilled before execution
resumes at the new address. Since the BRN branch condition is never
satisfied, the branch is never taken, and only a single program fetch is
needed to update the instruction queue.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
BRN rel8
MOTOROLA
6-46
Address Mode
REL
Object Code
21 rr
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
CPU12
REFERENCE MANUAL
BRSET
BRSET
Branch if Bits Set
Operation:
If (M) • (Mask) = 0, then branch
Description:
Performs bitwise logical AND on the inverse of memory location M and
the mask supplied with the instruction, then branches if and only if all bits
with a value of one in the mask byte correspond to bits with a value of
one in the tested byte. Mask operands can be located at PC + 1, PC +
2, or PC + 4, depending on addressing mode. The branch offset is referenced to the next address after the relative offset (rr) which is the last
byte of the instruction object code.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
BRSET opr8a, msk8, rel8
BRSET opr16a, msk8, rel8
BRSET oprx0_xysp, msk8, rel8
BRSET oprx9,xysp, msk8, rel8
BRSET oprx16,xysp, msk8, rel8
Address Mode1
DIR
EXT
IDX
IDX1
IDX2
Object Code
4E
1E
0E
0E
0E
rr
dd
hh
xb
xb
xb
mm
ll
mm
ff
ee
rr
mm rr
rr
mm rr
ff mm
Cycles
4
5
4
6
8
Access
Detail
rPPP
rfPPP
rPPP
rffPPP
frPffPPP
Notes:
1. Indirect forms of indexed addressing cannot be used with this instruction.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-47
BSET
BSET
Set Bit(s) in Memory
Operation:
(M) + (Mask) ⇒ M
Description:
Sets bits in memory location M. To set a bit, set the corresponding bit in
the mask byte. All other bits in M are unchanged. The mask byte can be
located at PC + 2, PC + 3, or PC + 4, depending upon addressing mode.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode1
Object Code
4C dd mm
BSET opr8a, msk8
DIR
1C hh ll mm
EXT
BSET opr16a, msk8
0C xb mm
IDX
BSET oprx0_xysp, msk8
0C xb ff mm
IDX1
BSET oprx9,xysp, msk8
0C xb ee ff mm
IDX2
BSET oprx16,xysp, msk8
Notes:
1. Indirect forms of indexed addressing cannot be used with this instruction.
MOTOROLA
6-48
INSTRUCTION GLOSSARY
Cycles
4
4
4
4
6
Access Detail
rPOw
rPPw
rPOw
rPwP
frPwOP
CPU12
REFERENCE MANUAL
BSR
BSR
Branch to Subroutine
Operation:
(SP) – $0002 ⇒ SP
RTNH : RTNL ⇒ M(SP) : M(SP + 1)
(PC) + Rel ⇒ PC
Description:
Sets up conditions to return to normal program flow, then transfers control to a subroutine. Uses the address of the instruction after the BSR as
a return address.
Decrements the SP by two, to allow the two bytes of the return address to be stacked.
Stacks the return address (the SP points to the high order byte of the
return address).
Branches to a location determined by the branch offset.
Subroutines are normally terminated with an RTS instruction, which restores the return address from the stack.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
BSR rel8
CPU12
REFERENCE MANUAL
Address Mode
REL
Object Code
07 rr
INSTRUCTION GLOSSARY
Cycles
4
Access Detail
PPPS
MOTOROLA
6-49
BVC
Operation:
BVC
Branch if Overflow Cleared
If V = 0, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the V status bit and branches if V = 0.
BVC causes a branch when a previous operation on two’s complement
binary values does not cause an overflow. That is, when BVC follows a
two’s complement operation, a branch occurs when the result of the operation is valid.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BVC rel8
REL
28 rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
MOTOROLA
6-50
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
BVS
Operation:
BVS
Branch if Overflow Set
If V = 1, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the V status bit and branches if V = 1.
BVS causes a branch when a previous operation on two’s complement
binary values causes an overflow. That is, when BVS follows a two’s
complement operation, a branch occurs when the result of the operation
is invalid.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
BVS rel8
REL
29 rr
3/1
PPP/P1
Notes:
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one
program fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-51
CALL
CALL
Call Subroutine in Expanded Memory
Operation:
(SP) – $0002 ⇒ SP
RTNH : RTNL ⇒ M(SP) : M(SP + 1)
(SP) – $0001 ⇒ SP
(PPAGE) ⇒ M(SP)
page ⇒ PPAGE
Subroutine Address ⇒ PC
Description:
Sets up conditions to return to normal program flow, then transfers control to a subroutine in expanded memory. Uses the address of the instruction following the CALL as a return address. For code compatibility,
CALL also executes correctly in devices that do not have expanded
memory capability.
Decrements the SP by two, to allow the two bytes of the return address to be stacked.
Stacks the return address (the SP points to the high order byte of the
return address).
Decrements the SP by one, to allow the current memory page value
in the PPAGE register to be stacked.
Stacks the content of PPAGE.
Writes a new page value supplied by the instruction to PPAGE.
Transfers control to the subroutine.
In indexed-indirect modes, the subroutine address and the PPAGE
value are fetched from memory in the order M high byte, M low byte, and
new PPAGE value.
Expanded-memory subroutines must be terminated by an RTC instruction, which restores the return address and PPAGE value from the stack.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CALL opr16a, page
CALL oprx0_xysp, page
CALL oprx9,xysp, page
CALL oprx16,xysp, page
CALL [D,xysp]
CALL [oprx16,xysp]
MOTOROLA
6-52
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
4A
4B
4B
4B
4B
4B
hh
xb
xb
xb
xb
xb
ll pg
pg
ff pg
ee ff pg
ee ff
INSTRUCTION GLOSSARY
Cycles
8
8
8
9
10
10
Access Detail
gnfSsPPP
gnfSsPPP
gnfSsPPP
fgnfSsPPP
fIignSsPPP
fIignSsPPP
CPU12
REFERENCE MANUAL
CBA
CBA
Compare Accumulators
Operation:
(A) – (B)
Description:
Compares the content of accumulator A to the content of accumulator B
and sets the condition codes, which may then be used for arithmetic and
logical conditional branches. The contents of the accumulators are not
changed.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
A7 • B7 • R7 + A7 • B7 • R7
Set if a two’s complement overflow resulted from the operation; cleared
otherwise.
C:
A7 • B7 + B7 • R7 + R7 + A7
Set if there was a borrow from the MSB of the result; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CBA
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
18 17
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
OO
MOTOROLA
6-53
CLC
CLC
Clear Carry
Operation:
0 ⇒ C bit
Description:
Clears the C status bit. This instruction is assembled as ANDCC #$FE.
The ANDCC instruction can be used to clear any combination of bits in
the CCR in one operation.
CLC can be used to set up the C bit prior to a shift or rotate instruction
involving the C bit.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
0
C:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CLC translates to...
ANDCC #$FE
MOTOROLA
6-54
Address Mode
IMM
Object Code
10 FE
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
CPU12
REFERENCE MANUAL
CLI
CLI
Clear Interrupt Mask
Operation:
0 ⇒ I bit
Description:
Clears the I mask bit. This instruction is assembled as ANDCC #$EF.
The ANDCC instruction can be used to clear any combination of bits in
the CCR in one operation.
When the I bit is cleared, interrupts are enabled. There is a one cycle
(bus clock) delay in the clearing mechanism for the I bit so that, if interrupts were previously disabled, the next instruction after a CLI will
always be executed, even if there was an interrupt pending prior to execution of the CLI instruction.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
0
–
–
–
–
I:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CLI translates to...
ANDCC #$EF
CPU12
REFERENCE MANUAL
Address Mode
IMM
Object Code
10 EF
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
MOTOROLA
6-55
CLR
CLR
Clear Memory
Operation:
0⇒M
Description:
All bits in memory location M are cleared to zero.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
0
1
0
0
N:
0; Cleared.
Z:
1; Set.
V:
0; Cleared.
C:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CLR opr16a
CLR oprx0_xysp
CLR oprx9,xysp
CLR oprx16,xysp
CLR [D,xysp]
CLR [oprx16,xysp]
MOTOROLA
6-56
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
79
69
69
69
69
69
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
3
2
3
3
5
5
Access Detail
wOP
Pw
PwO
PwP
PIfPw
PIPPw
CPU12
REFERENCE MANUAL
CLRA
CLRA
Clear A
Operation:
0⇒A
Description:
All bits in accumulator A are cleared to zero.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
0
1
0
0
N:
0; Cleared.
Z:
1; Set.
V:
0; Cleared.
C:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CLRA
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
87
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-57
CLRB
CLRB
Clear B
Operation:
0⇒B
Description:
All bits in accumulator B are cleared to zero.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
0
1
0
0
N:
0; Cleared.
Z:
1; Set.
V:
0; Cleared.
C:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CLRB
MOTOROLA
6-58
Address Mode
INH
Object Code
C7
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
CLV
CLV
Clear Two’s Complement Overflow Bit
Operation:
0 ⇒ V bit
Description:
Clears the V status bit. This instruction is assembled as ANDCC #$FD.
The ANDCC instruction can be used to clear any combination of bits in
the CCR in one operation.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
0
–
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CLV translates to...
ANDCC #$FD
CPU12
REFERENCE MANUAL
Address Mode
IMM
Object Code
10 FD
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
MOTOROLA
6-59
CMPA
CMPA
Compare A
Operation:
(A) – (M)
Description:
Compares the content of accumulator A to the content of memory location M and sets the condition codes, which may then be used for arithmetic and logical conditional branching. The contents of A and location
M are not changed.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if a two’s complement overflow resulted from the operation; cleared
otherwise.
C:
X7 • M7 + M7 • R7 + R7 + X7
Set if there was a borrow from the MSB of the result; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CMPA #opr8i
CMPA opr8a
CMPA opr16a
CMPA oprx0_xysp
CMPA oprx9,xysp
CMPA oprx16,xysp
CMPA [D,xysp]
CMPA [oprx16,xysp]
MOTOROLA
6-60
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
81
91
B1
A1
A1
A1
A1
A1
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
CMPB
CMPB
Compare B
Operation:
(B) – (M)
Description:
Compares the content of accumulator B to the content of memory location M and sets the condition codes, which may then be used for arithmetic and logical conditional branching. The contents of B and location
M are not changed.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if a two’s complement overflow resulted from the operation; cleared
otherwise.
C:
X7 • M7 + M7 • R7 + R7 + X7
Set if there was a borrow from the MSB of the result; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CMPB #opr8i
CMPB opr8a
CMPB opr16a
CMPB oprx0_xysp
CMPB oprx9,xysp
CMPB oprx16,xysp
CMPB [D,xysp]
CMPB [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
C1
D1
F1
E1
E1
E1
E1
E1
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
MOTOROLA
6-61
COM
COM
Complement Memory
Operation:
(M) = $FF – (M) ⇒ M
Description:
Replaces the content of memory location M with its one’s complement.
Each bit of M is complemented. Immediately after a COM operation on
unsigned values, only the BEQ, BNE, LBEQ, and LBNE branches can
be expected to perform consistently. After operation on two’s complement values, all signed branches are available.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
1
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
C:
1; Set (for M6800 compatibility).
Addressing Modes, Machine Code, and Execution Times:
Source Form
COM opr16a
COM oprx0_xysp
COM oprx9,xysp
COM oprx16,xysp
COM [D,xysp]
COM [oprx16,xysp]
MOTOROLA
6-62
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
71
61
61
61
61
61
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
3
4
5
6
6
Access Detail
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
CPU12
REFERENCE MANUAL
COMA
Complement A
COMA
Operation:
(A) = $FF – (A) ⇒ A
Description:
Replaces the content of accumulator A with its one’s complement. Each
bit of A is complemented. Immediately after a COM operation on unsigned values, only the BEQ, BNE, LBEQ, and LBNE branches can be
expected to perform consistently. After operation on two’s complement
values, all signed branches are available.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
1
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
C:
1; Set (for M6800 compatibility).
Addressing Modes, Machine Code, and Execution Times:
Source Form
COMA
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
41
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-63
COMB
Complement B
COMB
Operation:
(B) = $FF – (B) ⇒ B
Description:
Replaces the content of accumulator B with its one’s complement. Each
bit of B is complemented. Immediately after a COM operation on unsigned values, only the BEQ, BNE, LBEQ, and LBNE branches can be
expected to perform consistently. After operation on two’s complement
values, all signed branches are available.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
1
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
C:
1; Set (for M6800 compatibility).
Addressing Modes, Machine Code, and Execution Times:
Source Form
COMB
MOTOROLA
6-64
Address Mode
INH
Object Code
51
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
CPD
CPD
Compare Double Accumulator
Operation:
(A : B) – (M : M + 1)
Description:
Compares the content of double accumulator D with a 16-bit value at the
address specified, and sets the condition codes accordingly. The compare is accomplished internally by a 16-bit subtract of (M : M + 1) from D
without modifying either D or (M : M + 1).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
D15 • M15 • R15 + D15 • M15 • R15
Set if two’s complement overflow resulted from the operation; cleared
otherwise.
C:
D15 • M15 + M15 • R15 + R15 + D15
Set if the absolute value of the content of memory is larger than the
absolute value of the accumulator; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CPD #opr16i
CPD opr8a
CPD opr16a
CPD oprx0_xysp
CPD oprx9,xysp
CPD oprx16,xysp
CPD [D,xysp]
CPD [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
8C
9C
BC
AC
AC
AC
AC
AC
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
3
3
3
4
6
6
Access Detail
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
MOTOROLA
6-65
CPS
CPS
Compare Stack Pointer
Operation:
(SP) – (M : M + 1)
Description:
Compares the content of the SP with a 16-bit value at the address specified, and sets the condition codes accordingly. The compare is accomplished internally by doing a 16-bit subtract of (M : M + 1) from the SP
without modifying either the SP or (M : M + 1).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
S15 • M15 • R15 + S15 • M15 • R15
Set if two’s complement overflow resulted from the operation; cleared
otherwise.
C:
S15 • M15 + M15 • R15 + R15 + S15
Set if the absolute value of the content of memory is larger than the
absolute value of the SP; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CPS #opr16i
CPS opr8a
CPS opr16a
CPS oprx0_xysp
CPS oprx9,xysp
CPS oprx16,xysp
CPS [D,xysp]
CPS [oprx16,xysp]
MOTOROLA
6-66
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
8F
9F
BF
AF
AF
AF
AF
AF
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
3
3
3
4
6
6
Access Detail
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
CPU12
REFERENCE MANUAL
CPX
CPX
Compare Index Register X
Operation:
(X) – (M : M + 1)
Description:
Compares the content of index register X with a 16-bit value at the address specified, and sets the condition codes accordingly. The compare
is accomplished internally by a 16-bit subtract of (M : M + 1) from index
register X without modifying either index register X or (M : M + 1).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
X15 • M15 • R15 + X15 • M15 • R15
Set if two’s complement overflow resulted from the operation; cleared
otherwise.
C:
X15 • M15 + M15 • R15 + R15 + X15
Set if the absolute value of the content of memory is larger than the
absolute value of the index register; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CPX #opr16i
CPX opr8a
CPX opr16a
CPX oprx0_xysp
CPX oprx9,xysp
CPX oprx16,xysp
CPX [D,xysp]
CPX [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
8E
9E
BE
AE
AE
AE
AE
AE
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
3
3
3
4
6
6
Access Detail
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
MOTOROLA
6-67
CPY
CPY
Compare Index Register Y
Operation:
(Y) – (M : M + 1)
Description:
Compares the content of index register Y to a 16-bit value at the address
specified, and sets the condition codes accordingly. The compare is accomplished internally by a 16-bit subtract of (M : M + 1) from Y without
modifying either Y or (M : M + 1).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
Y15 • M15 • R15 + Y15 • M15 • R15
Set if two’s complement overflow resulted from the operation; cleared
otherwise.
C:
Y15 • M15 + M15 • R15 + R15 + Y15
Set if the absolute value of the content of memory is larger than the
absolute value of the index register; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
CPY #opr16i
CPY opr8a
CPY opr16a
CPY oprx0_xysp
CPY oprx9,xysp
CPY oprx16,xysp
CPY [D,xysp]
CPY [oprx16,xysp]
MOTOROLA
6-68
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
8D
9D
BD
AD
AD
AD
AD
AD
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
3
3
3
4
6
6
Access Detail
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
CPU12
REFERENCE MANUAL
DAA
Description:
DAA
Decimal Adjust A
DAA adjusts the content of accumulator A and the state of the C status
bit to represent the correct binary-coded-decimal sum and the associated carry when a BCD calculation has been performed. In order to execute DAA, the content of accumulator A, the state of the C status bit, and
the state of the H status bit must all be the result of performing an ABA,
ADD or ADC on BCD operands, with or without an initial carry.
The table below shows DAA operation for all legal combinations of input
operands. Columns 1 through 4 represent the results of ABA, ADC, or
ADD operations on BCD operands. The correction factor in column 5 is
added to the accumulator to restore the result of an operation on two
BCD operands to a valid BCD value, and to set or clear the C bit. All values are in hexadecimal.
1
2
3
4
5
6
Initial
C Bit Value
Value of
A[7:4]
Initial
H Bit Value
Value of
A[3:0]
Correction
Factor
Corrected
C Bit Value
0
0–9
0
0–9
00
0
0
0–8
0
A–F
06
0
0
0–9
1
0–3
06
0
0
A–F
0
0–9
60
1
0
9–F
0
A–F
66
1
0
A–F
1
0–3
66
1
1
0–2
0
0–9
60
1
1
0–2
0
A–F
66
1
1
0–3
1
0–3
66
1
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
?
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
Undefined.
C:
Represents BCD carry. See table above.
Addressing Modes, Machine Code, and Execution Times:
Source Form
DAA
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
18 07
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
OfO
MOTOROLA
6-69
DBEQ
Decrement and Branch if Equal to Zero
DBEQ
Operation:
(Counter) – 1 ⇒ Counter
If (Counter) = 0, then (PC) + $0003 + Rel ⇒ PC,
Description:
Subtract one from the specified counter register A, B, D, X, Y, or SP. If
the counter register has reached zero, execute a branch to the specified
relative destination. The DBEQ instruction is encoded into three bytes of
machine code including the 9-bit relative offset (–256 to +255 locations
from the start of the next instruction).
IBEQ and TBEQ instructions are similar to DBEQ except that the counter
is incremented or tested rather than being decremented. Bits 7 and 6 of
the instruction postbyte are used to determine which operation is to be
performed.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Object Code1
Address Mode
Cycles
Access Detail
DBEQ abdxys, rel9
REL
04 lb rr
3/3
PPP
Notes:
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero
(DBEQ – 0) or not zero (DBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 would
be 0:0 for DBEQ.
Object Code
(if offset is positive)
Object Code
(if offset is negative)
Count
Register
Bits 2:0
A
B
000
001
DBEQ A, rel9
DBEQ B, rel9
04 00 rr
04 01 rr
04 10 rr
04 11 rr
D
X
Y
SP
100
101
110
111
DBEQ D, rel9
DBEQ X, rel9
DBEQ Y, rel9
DBEQ SP, rel9
04
04
04
04
04
04
04
04
MOTOROLA
6-70
Source Form
04
05
06
07
rr
rr
rr
rr
INSTRUCTION GLOSSARY
14
15
16
17
rr
rr
rr
rr
CPU12
REFERENCE MANUAL
DBNE
DBNE
Decrement and Branch if Not Equal to Zero
Operation:
(Counter) – 1 ⇒ Counter
If (Counter) not = 0, then (PC) + $0003 + Rel ⇒ PC,
Description:
Subtract one from the specified counter register A, B, D, X, Y, or SP. If
the counter register has not been decremented to zero, execute a
branch to the specified relative destination. The DBNE instruction is encoded into three bytes of machine code including a 9-bit relative offset
(–256 to +255 locations from the start of the next instruction).
IBNE and TBNE instructions are similar to DBNE except that the counter
is incremented or tested rather than being decremented. Bits 7 and 6 of
the instruction postbyte are used to determine which operation is to be
performed.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Object Code1
Address Mode
Cycles
Access Detail
DBNE abdxys, rel9
REL
04 lb rr
3/3
PPP
Notes:
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero
(DBEQ – 0) or not zero (DBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 would
be 0:0 for DBNE.
Object Code
(if offset is positive)
Object Code
(if offset is negative)
Count
Register
Bits 2:0
A
B
000
001
DBNE A, rel9
DBNE B, rel9
04 20 rr
04 21 rr
04 30 rr
04 31 rr
D
X
Y
SP
100
101
110
111
DBNE D, rel9
DBNE X, rel9
DBNE Y, rel9
DBNE SP, rel9
04
04
04
04
04
04
04
04
CPU12
REFERENCE MANUAL
Source Form
24
25
26
27
rr
rr
rr
rr
INSTRUCTION GLOSSARY
34
35
36
37
rr
rr
rr
rr
MOTOROLA
6-71
DEC
DEC
Decrement Memory
Operation:
(M) – $01 ⇒ M
Description:
Subtract one from the content of memory location M.
The N, Z and V status bits are set or cleared according to the results of
the operation. The C status bit is not affected by the operation, thus allowing the DEC instruction to be used as a loop counter in multiple-precision computations.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
Set if there was a two’s complement overflow as a result of the operation;
cleared otherwise. Two’s complement overflow occurs if and only if (M)
was $80 before the operation.
Addressing Modes, Machine Code, and Execution Times:
Source Form
DEC opr16a
DEC oprx0_xysp
DEC oprx9,xysp
DEC oprx16,xysp
DEC [D,xysp]
DEC [oprx16,xysp]
MOTOROLA
6-72
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
73
63
63
63
63
63
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
3
4
5
6
6
Access Detail
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
CPU12
REFERENCE MANUAL
DECA
DECA
Decrement A
Operation:
(A) – $01 ⇒ A
Description:
Subtract one from the content of accumulator A.
The N, Z and V status bits are set or cleared according to the results of
the operation. The C status bit is not affected by the operation, thus allowing the DEC instruction to be used as a loop counter in multiple-precision computations.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
Set if there was a two’s complement overflow as a result of the operation;
cleared otherwise. Two’s complement overflow occurs if and only if (A) was
$80 before the operation.
Addressing Modes, Machine Code, and Execution Times:
Source Form
DECA
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
43
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-73
DECB
DECB
Decrement B
Operation:
(B) – $01 ⇒ B
Description:
Subtract one from the content of accumulator B.
The N, Z and V status bits are set or cleared according to the results of
the operation. The C status bit is not affected by the operation, thus allowing the DEC instruction to be used as a loop counter in multiple-precision computations.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
Set if there was a two’s complement overflow as a result of the operation;
cleared otherwise. Two’s complement overflow occurs if and only if (B) was
$80 before the operation.
Addressing Modes, Machine Code, and Execution Times:
Source Form
DECB
MOTOROLA
6-74
Address Mode
INH
Object Code
53
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
DES
DES
Decrement Stack Pointer
Operation:
(SP) – $0001 ⇒ SP
Description:
Subtract one from the SP. This instruction assembles to LEAS –1,SP.
The LEAS instruction does not affect condition codes as DEX or DEY instructions do.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
DES translates to...
IDX
1B 9F
2
PP1
LEAS –1,SP
Notes:
1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-75
DEX
DEX
Decrement Index Register X
Operation:
(X) – $0001 ⇒ X
Description:
Subtract one from index register X. LEAX –1,X can produce the same
result, but LEAX does not affect the Z bit. Although the LEAX instruction
is more flexible, DEX requires only one byte of object code.
Only the Z bit is set or cleared according to the result of this operation.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
–
–
Z:
Set if result is $0000; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
DEX
MOTOROLA
6-76
Address Mode
INH
Object Code
09
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
DEY
DEY
Decrement Index Register Y
Operation:
(Y) – $0001 ⇒ Y
Description:
Subtract one from index register Y. LEAY –1,Y can produce the same
result, but LEAY does not affect the Z bit. Although the LEAY instruction
is more flexible, DEY requires only one byte of object code.
Only the Z bit is set or cleared according to the result of this operation.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
–
–
Z:
Set if result is $0000; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
DEY
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
03
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-77
EDIV
EDIV
Extended Divide 32-Bit by 16-Bit
(Unsigned)
Operation:
(Y : D) ÷ (X) ⇒ Y; Remainder ⇒ D
Description:
Divides a 32-bit unsigned dividend by a 16-bit divisor, producing a 16-bit
unsigned quotient and an unsigned 16-bit remainder. All operands and
results are located in CPU registers. If an attempt to divide by zero is
made, the contents of double accumulator D and index register Y do not
change, but the states of the N and Z bits in the CCR are undefined.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise. Undefined after overflow or division by zero.
Z:
Set if result is $0000; cleared otherwise. Undefined after overflow or
division by zero.
V:
Set if the result was > $FFFF; cleared otherwise. Undefined after division by zero.
C:
Set if divisor was $0000; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
EDIV
MOTOROLA
6-78
Address Mode
INH
Object Code
11
INSTRUCTION GLOSSARY
Cycles
11
Access Detail
ffffffffffO
CPU12
REFERENCE MANUAL
EDIVS
Extended Divide 32-Bit by 16-Bit
(Signed)
EDIVS
Operation:
(Y : D) ÷ (X) ⇒ Y; Remainder ⇒ D
Description:
Divides a signed 32-bit dividend by a 16-bit signed divisor, producing a
signed 16-bit quotient and a signed 16-bit remainder. All operands and
results are located in CPU registers. If an attempt to divide by zero is
made, the C status bit is set and the contents of double accumulator D
and index register Y do not change, but the states of the N and Z bits in
the CCR are undefined.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise. Undefined after overflow or
division by zero.
Z:
Set if result is $0000; cleared otherwise. Undefined after overflow or division
by zero.
V:
Set if the result was > $7FFF or < $8000; cleared otherwise. Undefined after
division by zero.
C:
Set if divisor was $0000; cleared otherwise. (Indicates division by zero.)
Addressing Modes, Machine Code, and Execution Times:
Source Form
EDIVS
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
18 14
INSTRUCTION GLOSSARY
Cycles
Access Detail
12
OffffffffffO
MOTOROLA
6-79
Extended Multiply and Accumulate
(Signed)
16-Bit by 16-Bit to 32-Bit
EMACS
EMACS
Operation:
(M(X) : M(X+1)) × (M(Y) : M(Y+1)) + (M ~ M+3) ⇒ M ~ M+3
Description:
A 16-bit value is multiplied by a 16-bit value to produce a 32-bit intermediate result. This 32-bit intermediate result is then added to the content
of a 32-bit accumulator in memory. EMACS is a signed integer operation. All operands and results are located in memory. When the EMACS
instruction is executed, the first source operand is fetched from an address pointed to by X, and the second source operand is fetched from
an address pointed to by index register Y. Before the instruction is executed, the X and Y index registers must contain values that point to the
most significant bytes of the source operands. The most significant byte
of the 32-bit result is specified by an extended address supplied with the
instruction.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00000000; cleared otherwise.
V:
M31 • I31 • R31 + M31 • I31 • R31
Set if result > $7FFFFFFF (+ overflow) or < $80000000 (– underflow).
Indicates two’s complement overflow.
C:
M15 • I15 + I15 • R15 + R15 • M15
Set if there was a carry from bit 15 of the result; cleared otherwise.
Indicates a carry from low word to high word of the result occurred.
Addressing Modes, Machine Code, and Execution Times:
Source Form1
Address Mode
Object Code
Cycles
EMACS opr16a
Special
18 12 hh ll
13
Notes:
1. opr16a is an extended address specification. Both X and Y point to source operands.
MOTOROLA
6-80
INSTRUCTION GLOSSARY
Access Detail
ORROfffRRfWWP
CPU12
REFERENCE MANUAL
Place Larger of Two
Unsigned 16-Bit Values
in Accumulator D
EMAXD
EMAXD
Operation:
MAX ((D), (M : M + 1)) ⇒ D
Description:
Subtracts an unsigned 16-bit value in memory from an unsigned 16-bit
value in double accumulator D to determine which is larger, and leaves
the larger of the two values in D. The Z status bit is set when the result
of the subtraction is zero (the values are equal), and the C status bit is
set when the subtraction requires a borrow (the value in memory is larger
than the value in the accumulator). When C = 1, the value in D has been
replaced by the value in memory.
The unsigned value in memory is accessed by means of indexed addressing modes, which allow a great deal of flexibility in specifying the
address of the operand. Auto increment/decrement variations of indexed
addressing facilitate finding the largest value in a list of values.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
D15 • M15 • R15 + D15 • M15 • R15
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
D15 • M15 + M15 • R15 + R15 • D15
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Condition codes reflect internal subtraction (R = D – M : M + 1).
Addressing Modes, Machine Code, and Execution Times:
Source Form
EMAXD oprx0_xysp
EMAXD oprx9,xysp
EMAXD oprx16,xysp
EMAXD [D,xysp]
EMAXD [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
18
18
18
18
18
1A
1A
1A
1A
1A
xb
xb ff
xb ee ff
xb
xb ee ff
INSTRUCTION GLOSSARY
Cycles
4
4
5
7
7
Access Detail
ORfP
ORPO
OfRPP
OfIfRfP
OfIPRfP
MOTOROLA
6-81
Place Larger of Two
Unsigned 16-Bit Values
in Memory
EMAXM
EMAXM
Operation:
MAX ((D), (M : M + 1)) ⇒ M : M + 1
Description:
Subtracts an unsigned 16-bit value in memory from an unsigned 16-bit
value in double accumulator D to determine which is larger, and leaves
the larger of the two values in the memory location. The Z status bit is
set when the result of the subtraction is zero (the values are equal), and
the C status bit is set when the subtraction requires a borrow (the value
in memory is larger than the value in the accumulator). When C = 0, the
value in D has replaced the value in memory.
The unsigned value in memory is accessed by means of indexed addressing modes, which allow a great deal of flexibility in specifying the
address of the operand.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
D15 • M15 • R15 + D15 • M15 • R15
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
D15 • M15 + M15 • R15 + R15 • D15
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Condition codes reflect internal subtraction (R = D – M : M + 1).
Addressing Modes, Machine Code, and Execution Times:
Source Form
EMAXM oprx0_xysp
EMAXM oprx9,xysp
EMAXM oprx16,xysp
EMAXM [D,xysp]
EMAXM [oprx16,xysp]
MOTOROLA
6-82
Address Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
18
18
18
18
18
1E
1E
1E
1E
1E
xb
xb ff
xb ee ff
xb
xb ee ff
INSTRUCTION GLOSSARY
Cycles
4
5
6
7
7
Access Detail
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
CPU12
REFERENCE MANUAL
Place Smaller of Two
Unsigned 16-Bit Values
in Accumulator D
EMIND
EMIND
Operation:
MIN ((D), (M : M + 1)) ⇒ D
Description:
Subtracts an unsigned 16-bit value in memory from an unsigned 16-bit
value in double accumulator D to determine which is larger, and leaves
the smaller of the two values in D. The Z status bit is set when the result
of the subtraction is zero (the values are equal), and the C status bit is
set when the subtraction requires a borrow (the value in memory is larger
than the value in the accumulator). When C = 0, the value in D has been
replaced by the value in memory.
The unsigned value in memory is accessed by means of indexed addressing modes, which allow a great deal of flexibility in specifying the
address of the operand. Auto increment/decrement variations of indexed
addressing facilitate finding the largest value in a list of values.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
D15 • M15 • R15 + D15 • M15 • R15
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
D15 • M15 + M15 • R15 + R15 • D15
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Condition codes reflect internal subtraction (R = D – M : M + 1).
Addressing Modes, Machine Code, and Execution Times:
Source Form
EMIND oprx0_xysp
EMIND oprx9,xysp
EMIND oprx16,xysp
EMIND [D,xysp]
EMIND [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
18
18
18
18
18
1B
1B
1B
1B
1B
xb
xb ff
xb ee ff
xb
xb ee ff
INSTRUCTION GLOSSARY
Cycles
4
4
5
7
7
Access Detail
ORfP
ORPO
OfRPP
OfIfRfP
OfIPRfP
MOTOROLA
6-83
Place Smaller of Two
Unsigned 16-Bit Values
in Memory
EMINM
EMINM
Operation:
MIN ((D), (M : M + 1)) ⇒ M : M + 1
Description:
Subtracts an unsigned 16-bit value in memory from an unsigned 16-bit
value in double accumulator D to determine which is larger, and leaves
the smaller of the two values in the memory location. The Z status bit is
set when the result of the subtraction is zero (the values are equal), and
the C status bit is set when the subtraction requires a borrow (the value
in memory is larger than the value in the accumulator). When C = 1, the
value in D has replaced the value in memory.
The unsigned value in memory is accessed by means of indexed addressing modes, which allow a great deal of flexibility in specifying the
address of the operand.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
D15 • M15 • R15 + D15 • M15 • R15
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
D15 • M15 + M15 • R15 + R15 • D15
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Condition codes reflect internal subtraction (R = D – M : M + 1).
Addressing Modes, Machine Code, and Execution Times:
Source Form
EMINM oprx0_xysp
EMINM oprx9,xysp
EMINM oprx16,xysp
EMINM [D,xysp]
EMINM [oprx16,xysp]
MOTOROLA
6-84
Address Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
18
18
18
18
18
1F
1F
1F
1F
1F
xb
xb ff
xb ee ff
xb
xb ee ff
INSTRUCTION GLOSSARY
Cycles
4
5
6
7
7
Access Detail
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
CPU12
REFERENCE MANUAL
EMUL
EMUL
Extended Multiply
16-Bit by 16-Bit (Unsigned)
Operation:
(D) × (Y) ⇒ Y : D
Description:
An unsigned 16-bit value is multiplied by an unsigned 16-bit value to produce an unsigned 32-bit result. The first source operand must be loaded
into 16-bit double accumulator D and the second source operand must
be loaded into index register Y before executing the instruction. When
the instruction is executed, the value in D is multiplied by the value in Y.
The upper 16-bits of the 32-bit result are stored in Y and the low-order
16-bits of the result are stored in D.
The C status bit can be used to round the high-order 16 bits of the result.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
–
∆
N:
Set if the MSB of the result is set; cleared otherwise.
Z:
Set if result is $00000000; cleared otherwise.
C:
Set if bit 15 of the result is set; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
EMUL
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
13
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
ffO
MOTOROLA
6-85
EMULS
EMULS
Extended Multiply
16-Bit by 16-Bit (Signed)
Operation:
(D) × (Y) ⇒ Y : D
Description:
A signed 16-bit value is multiplied by a signed 16-bit value to produce a
signed 32-bit result. The first source operand must be loaded into 16-bit
double accumulator D and the second source operand must be loaded
into index register Y before executing the instruction. When the instruction is executed, D is multiplied by the value Y. The 16 high-order bits of
the 32-bit result are stored in Y and the 16 low-order bits of the result are
stored in D.
The C status bit can be used to round the high-order 16 bits of the result.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
–
∆
N:
Set if the MSB of the result is set; cleared otherwise.
Z:
Set if result is $00000000; cleared otherwise.
C:
Set if bit 15 of the result is set; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
EMULS
MOTOROLA
6-86
Address Mode
INH
Object Code
18 13
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
OfO
CPU12
REFERENCE MANUAL
EORA
EORA
Exclusive-OR A
Operation:
(A) ⊕ (M) ⇒ A
Description:
Performs the logical exclusive OR between the content of accumulator
A and the content of memory location M. The result is placed in A. Each
bit of A after the operation is the logical exclusive OR of the corresponding bits of M and A before the operation.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
EORA #opr8i
EORA opr8a
EORA opr16a
EORA oprx0_xysp
EORA oprx9,xysp
EORA oprx16,xysp
EORA [D,xysp]
EORA [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
88
98
B8
A8
A8
A8
A8
A8
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
MOTOROLA
6-87
EORB
EORB
Exclusive-OR B
Operation:
(B) ⊕ (M) ⇒ B
Description:
Performs the logical exclusive OR between the content of accumulator
B and the content of memory location M. The result is placed in A. Each
bit of A after the operation is the logical exclusive OR of the corresponding bits of M and B before the operation.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
EORB #opr8i
EORB opr8a
EORB opr16a
EORB oprx0_xysp
EORB oprx9,xysp
EORB oprx16,xysp
EORB [D,xysp]
EORB [oprx16,xysp]
MOTOROLA
6-88
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
C8
D8
F8
E8
E8
E8
E8
E8
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
ETBL
ETBL
Extended Table Lookup and Interpolate
Operation:
(M : M + 1) + [(B) × ((M + 2 : M + 3) – (M : M + 1))] ⇒ D
Description:
ETBL linearly interpolates one of 256 result values that fall between
each pair of data entries in a lookup table stored in memory. Data points
in the table represent the endpoints of equally-spaced line segments.
Table entries and the interpolated result are 16-bit values. The result is
stored in the D accumulator.
Before executing ETBL, set up an index register so that it points to the
starting point (X1) of a line segment when the instruction is executed. X1
is the table entry closest to, but less than or equal to, the desired lookup
value. The next table entry after X1 is X2. XL is the distance in X between X1 and X2. Load accumulator B with a binary fraction (radix point
to left of MSB) representing the ratio (XL–X1) ÷ (X2–X1).
The 16-bit unrounded result is calculated using the following expression:
D = Y1 + [(B) × (Y2 – Y1)]
Where
(B) = (XL – X1) ÷ (X2 – X1)
Y1 = 16-bit data entry pointed to by <effective address>
Y2 = 16-bit data entry pointed to by <effective address> + 2
The intermediate value [(B) × (Y2 – Y1)] produces a 24-bit result with the
radix point between bits 7 and 8. Any indexed addressing mode, except
indirect modes or 9-bit and 16-bit offset modes, can be used to identify
the first data point (X1,Y1). The second data point is the next table entry.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
–
?
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
C:
Undefined.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ETBL oprx0_xysp
CPU12
REFERENCE MANUAL
Address Mode
IDX
Object Code
18 3F xb
INSTRUCTION GLOSSARY
Cycles
10
Access Detail
ORRffffffP
MOTOROLA
6-89
EXG
EXG
Exchange Register Contents
Operation:
See table
Description:
Exchanges the contents of registers specified in the instruction as shown
below. Note that the order in which exchanges between 8-bit and 16-bit
registers are specified affects the high byte of the 16-bit registers differently. Exchanges of D with A or B are ambiguous. Cases involving TMP2
and TMP3 are reserved for Motorola use, so some assemblers may not
permit their use, but it is possible to generate these cases by using DC.B
or DC.W assembler directives.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected, unless the CCR is the destination register. Condition codes
take on the value of the corresponding source bits, except that the X mask bit
cannot change from zero to one. Software can leave the X bit set, leave it
cleared, or change it from one to zero, but it can only be set by a reset or by
recognition of an XIRQ interrupt.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Object Code1
Address Mode
Cycles
Access Detail
EXG abcdxys,abcdxys
INH
B7 eb
1
P
Notes:
1. Legal coding for eb is summarized in the following table. Columns represent the high-order source digit. Rows
represent the low-order destination digit (bit 3 is a don’t-care). Values are in hexadecimal.
8
9
A
B
C
D
E
F
B⇒A
A⇒B
XL ⇒ A
$00:A ⇒ X
YL ⇒ A
$00:A ⇒ Y
SPL ⇒ A
$00:A ⇒ SP
B⇒B
$FF ⇒ A
XL ⇒ B
$FF:B ⇒ X
YL ⇒ B
$FF:B ⇒ Y
SPL ⇒ B
$FF:B ⇒ SP
0
A⇔A
B⇔A
CCR ⇔ A
TMP3L ⇒ A
$00:A ⇒ TMP3
1
A⇔B
B⇔B
CCR ⇔ B
TMP3L ⇒ B
$FF:B ⇒ TMP3
2
A ⇔ CCR
B ⇔ CCR
CCR ⇔ CCR
3
$00:A ⇒ TMP2 $00:B ⇒ TMP2 $00:CCR ⇒ TMP2
TMP2L ⇒ A
TMP2L ⇒ B
TMP2L ⇒ CCR
TMP3L ⇒ CCR
B ⇒ CCR
XL ⇒ CCR
YL ⇒ CCR
SPL ⇒ CCR
$FF:CCR ⇒ TMP3 $FF:CCR ⇒ D $FF:CCR ⇒ X $FF:CCR ⇒ Y $FF:CCR ⇒ SP
TMP3 ⇔ TMP2
D ⇔ TMP2
X ⇔ TMP2
Y ⇔ TMP2
SP ⇔ TMP2
4
$00:A ⇒ D
$00:B ⇒ D
$00:CCR ⇒ D
B ⇒ CCR
TMP3 ⇔ D
D⇔D
X⇔D
Y⇔D
SP ⇔ D
5
$00:A ⇒ X
XL ⇒ A
$00:B ⇒ X
XL ⇒ B
$00:CCR ⇒ X
XL ⇒ CCR
TMP3 ⇔ X
D⇔X
X⇔X
Y⇔X
SP ⇔ X
6
$00:A ⇒ Y
YL ⇒ A
$00:B ⇒ Y
YL ⇒ B
$00:CCR ⇒ Y
YL ⇒ CCR
TMP3 ⇔ Y
D⇔Y
X⇔Y
Y⇔Y
SP ⇔ Y
7
$00:A ⇒ SP
SPL ⇒ A
$00:B ⇒ SP
SPL ⇒ B
$00:CCR ⇒ SP
SPL ⇒ CCR
TMP3 ⇔ SP
D ⇔ SP
X ⇔ SP
Y ⇔ SP
SP ⇔ SP
MOTOROLA
6-90
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
FDIV
FDIV
Fractional Divide
Operation:
(D) ÷ (X) ⇒ X; Remainder ⇒ D
Description:
Divides an unsigned 16-bit numerator in double accumulator D by an unsigned 16-bit denominator in index register X, producing an unsigned
16-bit quotient in X, and an unsigned 16-bit remainder in D. If both the
numerator and the denominator are assumed to have radix points in the
same positions, the radix point of the quotient is to the left of bit 15. The
numerator must be less than the denominator. In the case of overflow
(denominator is less than or equal to the numerator) or division by zero,
the quotient is set to $FFFF, and the remainder is indeterminate.
FDIV is equivalent to multiplying the numerator by 216 and then performing 32 x 16-bit integer division. The result is interpreted as a binaryweighted fraction, which resulted from the division of a 16-bit integer by
a larger 16-bit integer. A result of $0001 corresponds to 0.000015, and
$FFFF corresponds to 0.9998. The remainder of an IDIV instruction can
be resolved into a binary-weighted fraction by an FDIV instruction. The
remainder of an FDIV instruction can be resolved into the next 16 bits of
binary-weighted fraction by another FDIV instruction.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
∆
∆
Z:
Set if quotient is $0000; cleared otherwise.
V:
1 if X ≤ D
Set if the denominator was less than or equal to the numerator;
cleared otherwise.
C:
X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0
Set if denominator was $0000; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
FDIV
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
18 11
INSTRUCTION GLOSSARY
Cycles
Access Detail
12
OffffffffffO
MOTOROLA
6-91
IBEQ
IBEQ
Increment and Branch if Equal
to Zero
Operation:
(Counter) + 1 ⇒ Counter
If (Counter) = 0, then (PC) + $0003 + Rel ⇒ PC,
Description:
Add one to the specified counter register A, B, D, X, Y, or SP. If the
counter register has reached zero, branch to the specified relative destination. The IBEQ instruction is encoded into three bytes of machine
code including a 9-bit relative offset (–256 to +255 locations from the
start of the next instruction).
DBEQ and TBEQ instructions are similar to IBEQ except that the counter
is decremented or tested rather than being incremented. Bits 7 and 6 of
the instruction postbyte are used to determine which operation is to be
performed.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Object Code1
Address Mode
Cycles
Access Detail
IBEQ abdxys, rel9
REL
04 lb rr
3/3
PPP
Notes:
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero
(IBEQ – 0) or not zero (IBNE – 1) versions, and bit 0 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should
be 1:0 for IBEQ.
Object Code
(if offset is positive)
Object Code
(if offset is negative)
Count
Register
Bits 2:0
A
B
000
001
IBEQ A, rel9
IBEQ B, rel9
04 80 rr
04 81 rr
04 90 rr
04 91 rr
D
X
Y
SP
100
101
110
111
IBEQ D, rel9
IBEQ X, rel9
IBEQ Y, rel9
IBEQ SP, rel9
04
04
04
04
04
04
04
04
MOTOROLA
6-92
Source Form
84
85
86
87
rr
rr
rr
rr
INSTRUCTION GLOSSARY
94
95
96
97
rr
rr
rr
rr
CPU12
REFERENCE MANUAL
IBNE
IBNE
Increment and Branch if Not
Equal to Zero
Operation:
(Counter) + 1 ⇒ Counter
If (Counter) not = 0, then (PC) + $0003 + Rel ⇒ PC
Description:
Add one to the specified counter register A, B, D, X, Y, or SP. If the
counter register has not been incremented to zero, branch to the specified relative destination. The IBNE instruction is encoded into three bytes
of machine code including a 9-bit relative offset (–256 to +255 locations
from the start of the next instruction).
DBNE and TBNE instructions are similar to IBNE except that the counter
is decremented or tested rather than being incremented. Bits 7 and 6 of
the instruction postbyte are used to determine which operation is to be
performed.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Object Code1
Address Mode
Cycles
Access Detail
IBNE abdxys, rel9
REL
04 lb rr
3/3
PPP
Notes:
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero
(IBEQ – 0) or not zero (IBNE – 1) versions, and bit 0 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should
be 1:0 for IBNE.
Object Code
(if offset is positive)
Object Code
(if offset is negative)
Count
Register
Bits 2:0
A
B
000
001
IBNE A, rel9
IBNE B, rel9
04 A0 rr
04 A1 rr
04 B0 rr
04 B1 rr
D
X
Y
SP
100
101
110
111
IBNE D, rel9
IBNE X, rel9
IBNE Y, rel9
IBNE SP, rel9
04
04
04
04
04
04
04
04
CPU12
REFERENCE MANUAL
Source Form
A4
A5
A6
A7
rr
rr
rr
rr
INSTRUCTION GLOSSARY
B4
B5
B6
B7
rr
rr
rr
rr
MOTOROLA
6-93
IDIV
IDIV
Integer Divide
Operation:
(D) ÷ (X) ⇒ X; Remainder ⇒ D
Description:
Divides an unsigned 16-bit dividend in double accumulator D by an unsigned 16-bit divisor in index register X, producing an unsigned 16-bit
quotient in X, and an unsigned 16-bit remainder in D. If both the divisor
and the dividend are assumed to have radix points in the same positions,
the radix point of the quotient is to the right of bit zero. In the case of division by zero, the quotient is set to $FFFF, and the remainder is indeterminate.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
0
∆
Z:
Set if quotient is $0000; cleared otherwise.
V:
0; Cleared.
C:
X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0
Set if denominator was $0000; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
IDIV
MOTOROLA
6-94
Address Mode
INH
Object Code
18 10
INSTRUCTION GLOSSARY
Cycles
Access Detail
12
OffffffffffO
CPU12
REFERENCE MANUAL
IDIVS
IDIVS
Integer Divide (Signed)
Operation:
(D) ÷ (X) ⇒ X; Remainder ⇒ D
Description:
Performs signed integer division of a signed 16-bit numerator in double
accumulator D by a signed 16-bit denominator in index register X, producing a signed 16-bit quotient in X, and a signed 16-bit remainder in D.
If division by zero is attempted, the values in D and X are not changed,
but the values of the N, Z, and V status bits are undefined.
Other than division by zero, which is not legal and causes the C status
bit to be set, the only overflow case is:
$8000
–32,768
------------------ = −−−−−−−−−−−− = +32,768
$FFFF
–1
But the highest positive value that can be represented in a 16-bit two’s
complement number is 32,767 ($7FFFF).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise. Undefined after overflow or division by zero.
Z:
Set if quotient is $0000; cleared otherwise. Undefined after overflow
or division by zero.
V:
Set if the result was > $7FFF or < $8000; cleared otherwise. Undefined after division by zero.
C:
X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0
Set if denominator was $0000; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
IDIVS
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
18 15
INSTRUCTION GLOSSARY
Cycles
Access Detail
12
OffffffffffO
MOTOROLA
6-95
INC
INC
Increment Memory
Operation:
(M) + $01 ⇒ M
Description:
Add one to the content of memory location M.
The N, Z and V status bits are set or cleared according to the results of
the operation. The C status bit is not affected by the operation, thus allowing the INC instruction to be used as a loop counter in multiple-precision computations.
When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE
branches can be expected to perform consistently. When operating on
two’s complement values, all signed branches are available.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
Set if there is a two’s complement overflow as a result of the operation; cleared otherwise. Two’s complement overflow occurs if and
only if (M) was $7F before the operation.
Addressing Modes, Machine Code, and Execution Times:
Source Form
INC opr16a
INC oprx0_xysp
INC oprx9,xysp
INC oprx16,xysp
INC [D,xysp]
INC [oprx16,xysp]
MOTOROLA
6-96
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
72
62
62
62
62
62
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
3
4
5
6
6
Access Detail
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
CPU12
REFERENCE MANUAL
INCA
INCA
Increment A
Operation:
(A) + $01 ⇒ A
Description:
Add one to the content of accumulator A.
The N, Z and V status bits are set or cleared according to the results of
the operation. The C status bit is not affected by the operation, thus allowing the INC instruction to be used as a loop counter in multiple-precision computations.
When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE
branches can be expected to perform consistently. When operating on
two’s complement values, all signed branches are available.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
Set if there is a two’s complement overflow as a result of the operation; cleared otherwise. Two’s complement overflow occurs if and
only if (A) was $7F before the operation.
Addressing Modes, Machine Code, and Execution Times:
Source Form
INCA
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
42
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-97
INCB
INCB
Increment B
Operation:
(B) + $01 ⇒ B
Description:
Add one to the content of accumulator B.
The N, Z and V status bits are set or cleared according to the results of
the operation. The C status bit is not affected by the operation, thus allowing the INC instruction to be used as a loop counter in multiple-precision computations.
When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE
branches can be expected to perform consistently. When operating on
two’s complement values, all signed branches are available.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
Set if there is a two’s complement overflow as a result of the operation; cleared otherwise. Two’s complement overflow occurs if and
only if (B) was $7F before the operation.
Addressing Modes, Machine Code, and Execution Times:
Source Form
INCB
MOTOROLA
6-98
Address Mode
INH
Object Code
52
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
INS
INS
Increment Stack Pointer
Operation:
(SP) + $0001 ⇒ SP
Description:
Add one to the SP. This instruction is assembled to LEAS 1,SP. The
LEAS instruction does not affect condition codes as an INX or INY instruction would.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
INS translates to...
IDX
1B 81
2
PP1
LEAS 1,SP
Notes:
1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-99
INX
INX
Increment Index Register X
Operation:
(X) + $0001 ⇒ X
Description:
Add one to index register X. LEAX 1,X can produce the same result but
LEAX does not affect the Z status bit. Although the LEAX instruction is
more flexible, INX requires only one byte of object code.
INX operation affects only the Z status bit.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
–
–
Z:
Set if result is $0000; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
INX
MOTOROLA
6-100
Address Mode
INH
Object Code
08
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
INY
INY
Increment Index Register Y
Operation:
(Y) + $0001 ⇒ Y
Description:
Add one to index register Y. LEAY 1,Y can produce the same result but
LEAY does not affect the Z status bit. Although the LEAY instruction is
more flexible, INY requires only one byte of object code.
INY operation affects only the Z status bit.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
–
–
Z:
Set if result is $0000; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
INY
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
02
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-101
JMP
JMP
Jump
Operation:
Effective Address ⇒ PC
Description:
Jumps to the instruction stored at the effective address. The effective address is obtained according to the rules for extended or indexed addressing.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
JMP opr16a
JMP oprx0_xysp
JMP oprx9,xysp
JMP oprx16,xysp
JMP [D,xysp]
JMP [oprx16,xysp]
MOTOROLA
6-102
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
06
05
05
05
05
05
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
3
3
3
4
6
6
Access Detail
PPP
PPP
PPP
fPPP
fIfPPP
fIfPPP
CPU12
REFERENCE MANUAL
JSR
JSR
Jump to Subroutine
Operation:
(SP) – $0002 ⇒ SP
RTNH : RTNL ⇒ M(SP) : M(SP + 1)
Subroutine Address ⇒ PC
Description:
Sets up conditions to return to normal program flow, then transfers control to a subroutine. Uses the address of the instruction following the JSR
as a return address.
Decrements the SP by two, to allow the two bytes of the return address to be stacked.
Stacks the return address (the SP points to the high order byte of the
return address).
Calculates an effective address according to the rules for extended,
direct or indexed addressing.
Jumps to the location determined by the effective address.
Subroutines are normally terminated with an RTS instruction, which restores the return address from the stack.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
JSR opr8a
JSR opr16a
JSR oprx0_xysp
JSR oprx9,xysp
JSR oprx16,xysp
JSR [D,xysp]
JSR [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
17
16
15
15
15
15
15
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
4
4
4
5
7
7
Access Detail
PPPS
PPPS
PPPS
PPPS
fPPPS
fIfPPPS
fIfPPPS
MOTOROLA
6-103
LBCC
Operation:
Long Branch if Carry Cleared
(Same as LBHS)
LBCC
If C = 0, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the C status bit and branches if C = 0.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBCC rel16
REL
18 24 qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
MOTOROLA
6-104
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
LBCS
Operation:
Long Branch if Carry Set
(Same as LBLO)
LBCS
If C = 1, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the C status bit and branches if C = 1.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBCS rel16
REL
18 25 qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-105
LBEQ
Operation:
Long Branch if Equal
LBEQ
If Z = 1, (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the Z status bit and branches if Z = 1.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBEQ rel16
REL
18 27 qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
MOTOROLA
6-106
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
LBGE
Operation:
Long Branch if Greater Than or Equal to
Zero
LBGE
If N ⊕ V = 0, (PC) + $0004 + Rel ⇒ PC
For signed two’s complement numbers,
if (Accumulator) ≥ Memory), then branch
Description:
If LBGE is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the two’s complement number in the accumulator was greater
than or equal to the two’s complement number in memory.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBGE rel16
REL
18 2C qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-107
LBGT
Operation:
LBGT
Long Branch if Greater Than Zero
If Z + (N ⊕ V) = 0, then (PC) + $0004 + Rel ⇒ PC
For signed two’s complement numbers,
If (Accumulator) > (Memory), then branch
Description:
If LBGT is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the two’s complement number in the accumulator was greater
than the two’s complement number in memory.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBGT rel16
REL
18 2E qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
MOTOROLA
6-108
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
LBHI
Operation:
LBHI
Long Branch if Higher
If C + Z = 0, then (PC) + $0004 + Rel ⇒ PC
For unsigned binary numbers, if (Accumulator) > (Memory), then branch
Description:
If LBHI is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the unsigned binary number in the accumulator was greater than
the unsigned binary number in memory. This instruction is generally not
useful after INC/DEC, LD/ST, TST/CLR/COM because these instructions do not affect the C status bit.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBHI rel16
REL
18 22 qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-109
LBHS
Operation:
Long Branch if Higher or Same
(Same as LBCC)
LBHS
If C = 0, then (PC) + $0004 + Rel ⇒ PC
For unsigned binary numbers, if (Accumulator) ≥ (Memory), then branch
Description:
If LBHS is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the unsigned binary number in the accumulator was greater than
or equal to the unsigned binary number in memory. This instruction is
generally not useful after INC/DEC, LD/ST, TST/CLR/COM because
these instructions do not affect the C status bit.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBHS rel16
REL
18 24 qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
MOTOROLA
6-110
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
LBLE
Operation:
LBLE
Long Branch if Less Than or
Equal to Zero
If Z + (N ⊕ V) = 1, then (PC) + $0004 + Rel ⇒ PC
For signed two’s complement numbers,
if (Accumulator) ≤ (Memory), then branch
Description:
If LBLE is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the two’s complement number in the accumulator was less than
or equal to the two’s complement number in memory.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBLE rel16
REL
18 2F qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-111
LBLO
Operation:
Long Branch if Lower
(Same as LBCS)
LBLO
If C = 1, then (PC) + $0004 + Rel ⇒ PC
For unsigned binary numbers, if (Accumulator) < (Memory), then branch
Description:
If LBLO is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the unsigned binary number in the accumulator was less than the
unsigned binary number in memory. This instruction is generally not useful after INC/DEC, LD/ST, TST/CLR/COM because these instructions do
not affect the C status bit.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBLO rel16
REL
18 25 qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
MOTOROLA
6-112
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
LBLS
Operation:
LBLS
Long Branch if Lower or Same
If C + Z = 1, then (PC) + $0004 + Rel ⇒ PC
For unsigned binary numbers, if (Accumulator) ≤ (Memory), then branch
Description:
If LBLS is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the unsigned binary number in the accumulator was less than or
equal to the unsigned binary number in memory. This instruction is generally not useful after INC/DEC, LD/ST, TST/CLR/COM because these
instructions do not affect the C status bit.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBLS rel16
REL
18 23 qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-113
LBLT
Operation:
LBLT
Long Branch if Less Than Zero
If N ⊕ V = 1, (PC) + $0004 + Rel ⇒ PC
For signed two’s complement numbers,
if (Accumulator) < (Memory), then branch
Description:
If LBLT is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the two’s complement number in the accumulator was less than
the two’s complement number in memory.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBLT rel16
REL
18 2D qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
MOTOROLA
6-114
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
LBMI
Operation:
LBMI
Long Branch if Minus
If N = 1, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the N status bit and branches if N = 1.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBMI rel16
REL
18 2B qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-115
LBNE
Operation:
Long Branch if Not Equal to Zero
LBNE
If Z = 0, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the Z status bit and branches if Z = 0.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBNE rel16
REL
18 26 qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
MOTOROLA
6-116
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
LBPL
Operation:
LBPL
Long Branch if Plus
If N = 0, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the N status bit and branches if N = 0.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBPL rel16
REL
18 2A qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-117
LBRA
LBRA
Long Branch Always
Operation:
(PC) + $0004 + Rel ⇒ PC
Description:
Unconditional branch to an address calculated as shown in the expression. Rel is a relative offset stored as a two’s complement number in the
second and third bytes of machine code corresponding to the long
branch instruction.
Execution time is longer when a conditional branch is taken than when
it is not, because the instruction queue must be refilled before execution
resumes at the new address. Since the LBRA branch condition is always
satisfied, the branch is always taken, and the instruction queue must always be refilled, so execution time is always the larger value.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LBRA rel16
MOTOROLA
6-118
Address Mode
REL
Object Code
18 20 qq rr
INSTRUCTION GLOSSARY
Cycles
4
Access Detail
OPPP
CPU12
REFERENCE MANUAL
LBRN
LBRN
Long Branch Never
Operation:
(PC) + $0004 ⇒ PC
Description:
Never branches. LBRN is effectively a 4-byte NOP that requires three
cycles to execute. LBRN is included in the instruction set to provide a
complement to the LBRA instruction. The instruction is useful during program debug, to negate the effect of another branch instruction without
disturbing the offset byte. A complement for LBRA is also useful in compiler implementations.
Execution time is longer when a conditional branch is taken than when
it is not, because the instruction queue must be refilled before execution
resumes at the new address. Since the LBRN branch condition is never
satisfied, the branch is never taken, and the queue does not need to be
refilled, so execution time is always the smaller value.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LBRN rel16
CPU12
REFERENCE MANUAL
Address Mode
REL
Object Code
18 21 qq rr
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
OPO
MOTOROLA
6-119
LBVC
Operation:
Long Branch if Overflow Cleared
LBVC
If V = 0, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the V status bit and branches if V = 0.
LBVC causes a branch when a previous operation on two’s complement
binary values does not cause an overflow. That is, when LBVC follows a
two’s complement operation, a branch occurs when the result of the operation is valid.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBVC rel16
REL
18 28 qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
MOTOROLA
6-120
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
LBVS
Operation:
Long Branch if Overflow Set
LBVS
If V = 1, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the V status bit and branches if V = 1.
LBVS causes a branch when a previous operation on two’s complement
binary values causes an overflow. That is, when LBVS follows a two’s
complement operation, a branch occurs when the result of the operation
is invalid.
See 3.7 Relative Addressing Mode for details of branch execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
LBVS rel16
REL
18 29 qq rr
4/3
OPPP/OPO1
Notes:
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and
three cycles if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
CPU12
REFERENCE MANUAL
Boolean
Z + (N ⊕ V) = 0
N⊕V=0
Z=1
Z + (N ⊕ V) = 1
N⊕V=1
C+Z=0
C=0
Z=1
C+Z=1
C=1
C=1
N=1
V=1
Z=1
—
Test
r≤m
r<m
r≠m
r>m
r≥m
r≤m
r<m
r≠m
r>m
r≥m
No Carry
Plus
No Overflow
r≠0
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
INSTRUCTION GLOSSARY
MOTOROLA
6-121
LDAA
LDAA
Load Accumulator A
Operation:
(M) ⇒ A
Description:
Loads the content of memory location M into accumulator A. The condition codes are set according to the data.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LDAA #opr8i
LDAA opr8a
LDAA opr16a
LDAA oprx0_xysp
LDAA oprx9,xysp
LDAA oprx16,xysp
LDAA [D,xysp]
LDAA [oprx16,xysp]
MOTOROLA
6-122
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
86
96
B6
A6
A6
A6
A6
A6
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
LDAB
LDAB
Load Accumulator B
Operation:
(M) ⇒ B
Description:
Loads the content of memory location M into accumulator B. The condition codes are set according to the data.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LDAB #opr8i
LDAB opr8a
LDAB opr16a
LDAB oprx0_xysp
LDAB oprx9,xysp
LDAB oprx16,xysp
LDAB [D,xysp]
LDAB [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
C6
D6
F6
E6
E6
E6
E6
E6
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
MOTOROLA
6-123
LDD
LDD
Load Double Accumulator
Operation:
(M : M + 1) ⇒ A : B
Description:
Loads the contents of memory locations M and M+1 into double accumulator D. The condition codes are set according to the data. The information from M is loaded into accumulator A, and the information from
M+1 is loaded into accumulator B.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LDD #opr16i
LDD opr8a
LDD opr16a
LDD oprx0_xysp
LDD oprx9,xysp
LDD oprx16,xysp
LDD [D,xysp]
LDD [oprx16,xysp]
MOTOROLA
6-124
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
CC
DC
FC
EC
EC
EC
EC
EC
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
3
3
3
4
6
6
Access Detail
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
CPU12
REFERENCE MANUAL
LDS
LDS
Load Stack Pointer
Operation:
(M : M+1) ⇒ SP
Description:
Loads the most significant byte of the SP with the content of memory location M, and loads the least significant byte of the SP with the content
of the next byte of memory at M + 1.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LDS #opr16i
LDS opr8a
LDS opr16a
LDS oprx0_xysp
LDS oprx9,xysp
LDS oprx16,xysp
LDS [D,xysp]
LDS [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
CF
DF
FF
EF
EF
EF
EF
EF
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
3
3
3
4
6
6
Access Detail
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
MOTOROLA
6-125
LDX
LDX
Load Index Register X
Operation:
(M : M + 1) ⇒ X
Description:
Loads the most significant byte of index register X with the content of
memory location M, and loads the least significant byte of X with the content of the next byte of memory at M + 1.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LDX #opr16i
LDX opr8a
LDX opr16a
LDX oprx0_xysp
LDX oprx9,xysp
LDX oprx16,xysp
LDX [D,xysp]
LDX [oprx16,xysp]
MOTOROLA
6-126
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
CE
DE
FE
EE
EE
EE
EE
EE
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
3
3
3
4
6
6
Access Detail
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
CPU12
REFERENCE MANUAL
LDY
LDY
Load Index Register Y
Operation:
(M : M + 1) ⇒ Y
Description:
Loads the most significant byte of index register Y with the content of
memory location M, and loads the least significant byte of Y with the content of the next memory location at M + 1.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LDY #opr16i
LDY opr8a
LDY opr16a
LDY oprx0_xysp
LDY oprx9,xysp
LDY oprx16,xysp
LDY [D,xysp]
LDY [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
CD
DD
FD
ED
ED
ED
ED
ED
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
3
3
3
4
6
6
Access Detail
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
MOTOROLA
6-127
LEAS
LEAS
Load Stack Pointer with
Effective Address
Operation:
Effective Address ⇒ SP
Description:
Loads the stack pointer with an effective address specified by the program. The effective address can be any indexed addressing mode operand address except an indirect address. Indexed addressing mode
operand addresses are formed by adding an optional constant supplied
by the program or an accumulator value to the current value in X, Y, SP,
or PC. See 3.8 Indexed Addressing Modes for more details.
LEAS does not alter condition code bits. This allows stack modification
without disturbing CCR bits changed by recent arithmetic operations.
Operation is a bit more complex when LEAS is used with auto-increment
or aut-odecrement operand specifications and the SP is the referenced
index register. The index register is loaded with what would have gone
out to the address bus in the case of a load index instruction. In the case
of a pre-increment or pre-decrement, the modification is made before the
index register is loaded. In the case of a post-increment or post-decrement, modification would have taken effect after the address went out on
the address bus, so post-modification does not affect the content of the
index register.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
LEAS oprx0_xysp
IDX
IDX1
LEAS oprx9,xysp
IDX2
LEAS oprx16,xysp
Notes:
1. Due to internal CPU requirements, the program
instruction.
MOTOROLA
6-128
Object Code
1B xb
1B xb ff
1B xb ee ff
Cycles
2
2
2
Access Detail
PP1
PO
PP
word fetch is performed twice to the same address during this
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
LEAX
LEAX
Load X with Effective Address
Operation:
Effective Address ⇒ X
Description:
Loads index register X with an effective address specified by the program. The effective address can be any indexed addressing mode operand address except an indirect address. Indexed addressing mode
operand addresses are formed by adding an optional constant supplied
by the program or an accumulator value to the current value in X, Y, SP,
or PC. See 3.8 Indexed Addressing Modes for more details.
Operation is a bit more complex when LEAX is used with auto-increment
or auto-decrement operand specifications and index register X is the referenced index register. The index register is loaded with what would
have gone out to the address bus in the case of a load indexed instruction. In the case of a pre-increment or pre-decrement, the modification is
made before the index register is loaded. In the case of a post-increment
or post-decrement, modification would have taken effect after the address went out on the address bus, so post-modification does not affect
the content of the index register.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
LEAX oprx0_xysp
IDX
IDX1
LEAX oprx9,xysp
IDX2
LEAX oprx16,xysp
Notes:
1. Due to internal CPU requirements, the program
instruction.
CPU12
REFERENCE MANUAL
Object Code
1A xb
1A xb ff
1A xb ee ff
Cycles
2
2
2
Access Detail
PP1
PO
PP
word fetch is performed twice to the same address during this
INSTRUCTION GLOSSARY
MOTOROLA
6-129
LEAY
LEAY
Load Y with Effective Address
Operation:
Effective Address ⇒ Y
Description:
Loads index register Y with an effective address specified by the program. The effective address can be any indexed addressing mode operand address except an indirect address. Indexed addressing mode
operand addresses are formed by adding an optional constant supplied
by the program or an accumulator value to the current value in X, Y, SP,
or PC. See 3.8 Indexed Addressing Modes for more details.
Operation is a bit more complex when LEAY is used with auto-increment
or auto-decrement operand specifications and index register Y is the referenced index register. The index register is loaded with what would
have gone out to the address bus in the case of a load indexed instruction. In the case of a pre-increment or pre-decrement, the modification is
made before the index register is loaded. In the case of a post-increment
or post-decrement, modification would have taken effect after the address went out on the address bus, so post-modification does not affect
the content of the index register.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
LEAY oprx0_xysp
IDX
IDX1
LEAY oprx9,xysp
IDX2
LEAY oprx16,xysp
Notes:
1. Due to internal CPU requirements, the program
instruction.
MOTOROLA
6-130
Object Code
19 xb
19 xb ff
19 xb ee ff
Cycles
2
2
2
Access Detail
PP1
PO
PP
word fetch is performed twice to the same address during this
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
LSL
LSL
Logical Shift Left Memory
(Same as ASL)
Operation:
C
Description:
b7 – – – – – – b0
0
Shifts all bits of the memory location M one place to the left. Bit 0 is loaded with zero. The C status bit is loaded from the most significant bit of M.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
M7
Set if the LSB of M was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LSL opr16a
LSL oprx0_xysp
LSL oprx9,xysp
LSL oprx16,xysp
LSL [D,xysp]
LSL [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
78
68
68
68
68
68
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
3
4
5
6
6
Access Detail
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
MOTOROLA
6-131
LSLA
LSLA
Logical Shift Left A
(Same as ASLA)
Operation:
C
Description:
b7 – – – – – – b0
0
Shifts all bits of accumulator A one place to the left. Bit 0 is loaded with
zero. The C status bit is loaded from the most significant bit of A.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
A7
Set if the LSB of A was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LSLA
MOTOROLA
6-132
Address Mode
INH
Object Code
48
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
LSLB
LSLB
Logical Shift Left B
(Same as ASLB)
Operation:
b7 – – – – – – b0
C
Description:
0
Shifts all bits of accumulator B one place to the left. Bit 0 is loaded with
zero. The C status bit is loaded from the most significant bit of B.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
B7
Set if the LSB of B was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LSLB
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
58
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-133
LSLD
LSLD
Logical Shift Left Double
(Same as ASLD)
Operation:
C
Description:
0
b7 – – – – – – b0
B
b7 – – – – – – b0
A
Shifts all bits of double accumulator D one place to the left. Bit 0 is loaded with zero. The C status bit is loaded from the most significant bit of
accumulator A.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
D15
Set if the MSB of D was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LSLD
MOTOROLA
6-134
Address Mode
INH
Object Code
59
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
LSR
LSR
Logical Shift Right Memory
Operation:
0
Description:
C
b7 – – – – – – b0
Shifts all bits of memory location M one place to the right. Bit 7 is loaded
with zero. The C status bit is loaded from the least significant bit of M.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
0
∆
∆
∆
N:
0; Cleared.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
M0
Set if the LSB of M was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LSR opr16a
LSR oprx0_xysp
LSR oprx9,xysp
LSR oprx16,xysp
LSR [D,xysp]
LSR [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
74
64
64
64
64
64
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
3
4
5
6
6
Access Detail
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
MOTOROLA
6-135
LSRA
LSRA
Logical Shift Right A
Operation:
0
Description:
b7 – – – – – – b0
C
Shifts all bits of accumulator A one place to the right. Bit 7 is loaded with
zero. The C status bit is loaded from the least significant bit of A.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
0
∆
∆
∆
N:
0; Cleared.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
A0
Set if the LSB of A was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LSRA
MOTOROLA
6-136
Address Mode
INH
Object Code
44
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
LSRB
LSRB
Logical Shift Right B
Operation:
0
Description:
b7 – – – – – – b0
C
Shifts all bits of accumulator B one place to the right. Bit 7 is loaded with
zero. The C status bit is loaded from the least significant bit of B.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
0
∆
∆
∆
N:
0; Cleared.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
B0
Set if the LSB of B was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LSRB
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
54
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-137
LSRD
LSRD
Logical Shift Right Double
Operation:
0
Description:
C
b7 – – – – – – b0
B
b7 – – – – – – b0
A
Shifts all bits of double accumulator D one place to the right. D15 (MSB
of A) is loaded with zero. The C status bit is loaded from D0 (LSB of B).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
0
∆
∆
∆
N:
0; Cleared.
Z:
Set if result is $0000; cleared otherwise.
V:
D0
Set if, after the shift operation, C is set; cleared otherwise.
C:
D0
Set if the LSB of D was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
LSRD
MOTOROLA
6-138
Address Mode
INH
Object Code
49
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
Place Larger of Two
Unsigned 8-Bit Values
in Accumulator A
MAXA
MAXA
Operation:
MAX ((A), (M)) ⇒ A
Description:
Subtracts an unsigned 8-bit value in memory from an unsigned 8-bit
value in accumulator A to determine which is larger, and leaves the larger of the two values in A. The Z status bit is set when the result of the
subtraction is zero (the values are equal), and the C status bit is set when
the subtraction requires a borrow (the value in memory is larger than the
value in the accumulator). When C = 1, the value in A has been replaced
by the value in memory.
The unsigned value in memory is accessed by means of indexed addressing modes, which allow a great deal of flexibility in specifying the
address of the operand. Auto increment/decrement variations of indexed
addressing facilitate finding the largest value in a list of values.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Condition codes reflect internal subtraction (R = A – M).
Addressing Modes, Machine Code, and Execution Times:
Source Form
MAXA oprx0_xysp
MAXA oprx9,xysp
MAXA oprx16,xysp
MAXA [D,xysp]
MAXA [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
18
18
18
18
18
18
18
18
18
18
xb
xb ff
xb ee ff
xb
xb ee ff
INSTRUCTION GLOSSARY
Cycles
4
4
5
7
7
Access Detail
OrfP
OrPO
OfrPP
OfIfrfP
OfIPrfP
MOTOROLA
6-139
Place Larger of Two
Unsigned 8-Bit Values
in Memory
MAXM
MAXM
Operation:
MAX ((A), (M)) ⇒ M
Description:
Subtracts an unsigned 8-bit value in memory from an unsigned 8-bit
value in accumulator A to determine which is larger, and leaves the larger of the two values in the memory location. The Z status bit is set when
the result of the subtraction is zero (the values are equal), and the C status bit is set when the subtraction requires a borrow (the value in memory is larger than the value in the accumulator). When C = 0, the value
in accumulator A has replaced the value in memory.
The unsigned value in memory is accessed by means of indexed addressing modes, which allow a great deal of flexibility in specifying the
address of the operand.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Condition codes reflect internal subtraction (R = A – M).
Addressing Modes, Machine Code, and Execution Times:
Source Form
MAXM oprx0_xysp
MAXM oprx9,xysp
MAXM oprx16,xysp
MAXM [D,xysp]
MAXM [oprx16,xysp]
MOTOROLA
6-140
Address Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
18
18
18
18
18
1C
1C
1C
1C
1C
xb
xb ff
xb ee ff
xb
xb ee ff
INSTRUCTION GLOSSARY
Cycles
4
5
6
7
7
Access Detail
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
CPU12
REFERENCE MANUAL
MEM
MEM
Determine Grade of Membership
(Fuzzy Logic)
Operation:
Grade of Membership ⇒ M(Y)
(Y) + $0001 ⇒ Y
(X) + $0004 ⇒ X
Description:
Accumulator A and index registers X and Y must be set up as follows before executing MEM.
A must hold the current crisp value of a system input variable.
X must point to a 4-byte data structure that describes the trapezoidal
membership function for a label of the system input.
Y must point to the fuzzy input (RAM location) where the resulting
grade of membership is to be stored.
The 4-byte membership function data structure consists of Point_1,
Point_2, Slope_1, and Slope_2, in that order.
Point_1 is the X-axis starting point for the leading side of the trapezoid, and Slope_1 is the slope of the leading side of the trapezoid.
Point_2 is the X-axis position of the rightmost point of the trapezoid,
and Slope_2 is the slope of the trailing side of the trapezoid. The
trailing side slopes up and left from Point_2.
A Slope_1 or Slope_2 value of $00 indicates a special case where the
membership function either starts with a grade of $FF at input = Point_1,
or ends with a grade of $FF at input = Point_2 (infinite slope).
When MEM is executed, X points at Point_1 and Slope_2 is at X + 3.
After execution, the content of A is unchanged. X has been incremented
by four to point to the next set of membership function points and slopes.
The fuzzy input (RAM location) to which Y pointed contains the grade of
membership that was calculated by MEM, and Y has been incremented
by one so it points to the next fuzzy input.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
?
–
?
?
?
?
H, N, Z, V, and C may be altered by this instruction.
Addressing Modes, Machine Code, and Execution Times:
Source Form
MEM
CPU12
REFERENCE MANUAL
Address Mode
Special
Object Code
01
INSTRUCTION GLOSSARY
Cycles
5
Access Detail
RRfOw
MOTOROLA
6-141
Place Smaller of Two
Unsigned 8-Bit Values
in Accumulator A
MINA
MINA
Operation:
MIN ((A), (M)) ⇒ A
Description:
Subtracts an unsigned 8-bit value in memory from an unsigned 8-bit
value in accumulator A to determine which is larger, and leaves the
smaller of the two values in accumulator A. The Z status bit is set when
the result of the subtraction is zero (the values are equal), and the C status bit is set when the subtraction requires a borrow (the value in memory is larger than the value in the accumulator). When C = 0, the value
in accumulator A has been replaced by the value in memory.
The unsigned value in memory is accessed by means of indexed addressing modes, which allow a great deal of flexibility in specifying the
address of the operand. Auto increment/decrement variations of indexed
addressing facilitate finding the largest value in a list of values.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Condition codes reflect internal subtraction (R = A – M).
Addressing Modes, Machine Code, and Execution Times:
Source Form
MINA oprx0_xysp
MINA oprx9,xysp
MINA oprx16,xysp
MINA [D,xysp]
MINA [oprx16,xysp]
MOTOROLA
6-142
Address Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
18
18
18
18
18
19
19
19
19
19
xb
xb ff
xb ee ff
xb
xb ee ff
INSTRUCTION GLOSSARY
Cycles
4
4
5
7
7
Access Detail
OrfP
OrPO
OfrPP
OfIfrfP
OfIPrfP
CPU12
REFERENCE MANUAL
Place Smaller of Two
Unsigned 8-Bit Values
in Memory
MINM
MINM
Operation:
MIN ((A), (M)) ⇒ M
Description:
Subtracts an unsigned 8-bit value in memory from an unsigned 8-bit
value in accumulator A to determine which is larger, and leaves the
smaller of the two values in the memory location. The Z status bit is set
when the result of the subtraction is zero (the values are equal), and the
C status bit is set when the subtraction requires a borrow (the value in
memory is larger than the value in the accumulator). When C = 1, the
value in accumulator A has replaced the value in memory.
The unsigned value in memory is accessed by means of indexed addressing modes, which allow a great deal of flexibility in specifying the
address of the operand.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Condition codes reflect internal subtraction (R = A – M).
Addressing Modes, Machine Code, and Execution Times:
Source Form
MINM oprx0_xysp
MINM oprx9,xysp
MINM oprx16,xysp
MINM [D,xysp]
MINM [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
18
18
18
18
18
1D
1D
1D
1D
1D
xb
xb ff
xb ee ff
xb
xb ee ff
INSTRUCTION GLOSSARY
Cycles
4
5
6
7
7
Access Detail
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
MOTOROLA
6-143
MOVB
MOVB
Move a Byte of Data
from One Memory Location to Another
Operation:
(M1) ⇒ M2
Description:
Moves the content of one memory location to another memory location.
The content of the source memory location is not changed.
Move instructions use separate addressing modes to access the source
and destination of a move. The following combinations of addressing
modes are supported: IMM–EXT, IMM–IDX, EXT–EXT, EXT–IDX, IDX–
EXT, and IDX–IDX. IDX operands allow indexed addressing mode specifications that fit in a single postbyte; including 5-bit constant, accumulator offsets, and auto increment/decrement modes. Nine-bit and 16-bit
constant offsets would require additional extension bytes and are not allowed. Indexed indirect modes (for example [D,r]) are also not allowed.
There are special considerations when using PC-relative addressing
with move instructions. These are discussed in 3.9 Instructions Using
Multiple Modes.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form1
Address Mode
Object Code
Cycles
18 0B ii hh ll
MOVB #opr8, opr16a
IMM–EXT
18 08 xb ii
IMM–IDX
MOVB #opr8i, oprx0_xysp
18 0C hh ll hh ll
EXT–EXT
MOVB opr16a, opr16a
18 09 xb hh ll
EXT–IDX
MOVB opr16a, oprx0_xysp
18 0D xb hh ll
IDX–EXT
MOVB oprx0_xysp, opr16a
18 0A xb xb
IDX–IDX
MOVB oprx0_xysp, oprx0_xysp
Notes:
1. The first operand in the source code statement specifies the source for the move.
MOTOROLA
6-144
INSTRUCTION GLOSSARY
4
4
6
5
5
5
Access Detail
OPwP
OPwO
OrPwPO
OPrPw
OrPwP
OrPwO
CPU12
REFERENCE MANUAL
MOVW
MOVW
Move a Word of Data
from One Memory Location to Another
Operation:
(M : M + 11) ⇒ M : M + 12
Description:
Moves the content of one location in memory to another location in memory. The content of the source memory location is not changed.
Move instructions use separate addressing modes to access the source
and destination of a move. The following combinations of addressing
modes are supported: IMM–EXT, IMM–IDX, EXT–EXT, EXT–IDX, IDX–
EXT, and IDX–IDX. IDX operands allow indexed addressing mode specifications that fit in a single postbyte; including 5-bit constant, accumulator offsets, and auto increment/decrement modes. Nine-bit and 16-bit
constant offsets would require additional extension bytes and are not allowed. Indexed indirect modes (for example [D,r]) are also not allowed.
There are special considerations when using PC-relative addressing
with move instructions. These are discussed in 3.9 Instructions Using
Multiple Modes.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form1
Address Mode
Object Code
Cycles
18 03 jj kk hh ll
MOVW #opr16i, opr16a
IMM–EXT
18 00 xb jj kk
IMM–IDX
MOVW #opr16i, oprx0_xysp
18 04 hh ll hh ll
EXT–EXT
MOVW opr16a, opr16a
18 01 xb hh ll
EXT–IDX
MOVW opr16a, oprx0_xysp
18 05 xb hh ll
IDX–EXT
MOVW oprx0_xysp, opr16a
18 02 xb xb
IDX–IDX
MOVW oprx0_xysp, oprx0_xysp
Notes:
1. The first operand in the source code statement specifies the source for the move.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
5
4
6
5
5
5
Access Detail
OPWPO
OPPW
ORPWPO
OPRPW
ORPWP
ORPWO
MOTOROLA
6-145
MUL
MUL
Multiply
8-Bit by 8-Bit (Unsigned)
Operation:
(A) × (B) ⇒ A : B
Description:
Multiplies the 8-bit unsigned binary value in accumulator A by the 8-bit
unsigned binary value in accumulator B, and places the 16-bit unsigned
result in double accumulator D. The carry flag allows rounding the most
significant byte of the result through the sequence: MUL, ADCA #0.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
∆
C:
R7
Set if bit 7 of the result (B bit 7) is set; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
MUL
MOTOROLA
6-146
Address Mode
INH
Object Code
12
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
ffO
CPU12
REFERENCE MANUAL
NEG
NEG
Negate Memory
Operation:
0 – (M) = (M) + 1 ⇒ M
Description:
Replaces the content of memory location M with its two’s complement
(the value $80 is left unchanged).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0
Set if there is a two’s complement overflow from the implied subtraction
from zero; cleared otherwise. Two’s complement overflow occurs if and
only if (M) = $80
C:
R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0
Set if there is a borrow in the implied subtraction from zero; cleared otherwise. Set in all cases except when (M) = $00.
Addressing Modes, Machine Code, and Execution Times:
Source Form
NEG opr16a
NEG oprx0_xysp
NEG oprx9,xysp
NEG oprx16,xysp
NEG [D,xysp]
NEG [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
70
60
60
60
60
60
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
3
4
5
6
6
Access Detail
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
MOTOROLA
6-147
NEGA
NEGA
Negate A
Operation:
0 – (A) = (A) + 1 ⇒ A
Description:
Replaces the content of accumulator A with its two’s complement (the
value $80 is left unchanged).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0
Set if there is a two’s complement overflow from the implied subtraction
from zero; cleared otherwise. Two’s complement overflow occurs if
and only if (A) = $80.
C:
R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0
Set if there is a borrow in the implied subtraction from zero; cleared otherwise. Set in all cases except when (A) = $00.
Addressing Modes, Machine Code, and Execution Times:
Source Form
NEGA
MOTOROLA
6-148
Address Mode
INH
Object Code
40
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
NEGB
NEGB
Negate B
Operation:
0 – (B) = (B) + 1 ⇒ B
Description:
Replaces the content of accumulator B with its two’s complement (the
value $80 is left unchanged).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0
Set if there is a two’s complement overflow from the implied subtraction
from zero; cleared otherwise. Two’s complement overflow occurs if and
only if (B) = $80.
C:
R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0
Set if there is a borrow in the implied subtraction from zero; cleared otherwise. Set in all cases except when (B) = $00.
Addressing Modes, Machine Code, and Execution Times:
Source Form
NEGB
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
50
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-149
NOP
NOP
Null Operation
Operation:
No operation
Description:
This single-byte instruction increments the PC and does nothing else.
No other CPU registers are affected. NOP is typically used to produce a
time delay, although some software disciplines discourage CPU frequency-based time delays. During debug, NOP instructions are sometimes used to temporarily replace other machine code instructions, thus
disabling the replaced instruction(s).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
NOP
MOTOROLA
6-150
Address Mode
INH
Object Code
A7
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
ORAA
ORAA
Inclusive OR A
Operation:
(A) + (M) ⇒ A
Description:
Performs bitwise logical inclusive OR between the content of accumulator A and the content of memory location M and places the result in A.
Each bit of A after the operation is the logical inclusive OR of the corresponding bits of M and of A before the operation.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ORAA #opr8i
ORAA opr8a
ORAA opr16a
ORAA oprx0_xysp
ORAA oprx9,xysp
ORAA oprx16,xysp
ORAA [D,xysp]
ORAA [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
8A
9A
BA
AA
AA
AA
AA
AA
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
MOTOROLA
6-151
ORAB
ORAB
Inclusive OR B
Operation:
(B) + (M) ⇒ B
Description:
Performs bitwise logical inclusive OR between the content of accumulator B and the content of memory location M. The result is placed in B.
Each bit of B after the operation is the logical inclusive OR of the corresponding bits of M and of B before the operation.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ORAB #opr8i
ORAB opr8a
ORAB opr16a
ORAB oprx0_xysp
ORAB oprx9,xysp
ORAB oprx16,xysp
ORAB [D,xysp]
ORAB [oprx16,xysp]
MOTOROLA
6-152
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
CA
DA
FA
EA
EA
EA
EA
EA
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
ORCC
ORCC
Logical OR CCR with Mask
Operation:
(CCR) + (M) ⇒ CCR
Description:
Performs bitwise logical inclusive OR between the content of memory
location M and the content of the CCR, and places the result in the CCR.
Each bit of the CCR after the operation is the logical OR of the corresponding bits of M and of CCR before the operation. To set one or more
bits, set the corresponding bit of the mask equal to one. Bits corresponding to zeros in the mask are not changed by the ORCC operation.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
⇑
–
⇑
⇑
⇑
⇑
⇑
⇑
Condition code bits are set if the corresponding bit was one before the
operation or if the corresponding bit in the instruction-provided mask
is one. The X interrupt mask cannot be set by any software instruction.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ORCC #opr8i
CPU12
REFERENCE MANUAL
Address Mode
IMM
Object Code
14 ii
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
MOTOROLA
6-153
PSHA
PSHA
Push A onto Stack
Operation:
(SP) – $0001 ⇒ SP
(A) ⇒ M(SP)
Description:
Stacks the content of accumulator A. The stack pointer is decremented
by one. The content of A is then stacked at the address the SP points to.
Push instructions are commonly used to save the contents of one or
more CPU registers at the start of a subroutine. Complementary pull instructions can be used to restore the saved CPU registers just before returning from the subroutine.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PSHA
MOTOROLA
6-154
Address Mode
INH
Object Code
36
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
Os
CPU12
REFERENCE MANUAL
PSHB
PSHB
Push B onto Stack
Operation:
(SP) – $0001 ⇒ SP
(B) ⇒ M(SP)
Description:
Stacks the content of accumulator B. The stack pointer is decremented
by one. The content of B is then stacked at the address the SP points to.
Push instructions are commonly used to save the contents of one or
more CPU registers at the start of a subroutine. Complementary pull instructions can be used to restore the saved CPU registers just before returning from the subroutine.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PSHB
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
37
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
Os
MOTOROLA
6-155
PSHC
PSHC
Push CCR onto Stack
Operation:
(SP) – $0001 ⇒ SP
(CCR) ⇒ M(SP)
Description:
Stacks the content of the condition codes register. The stack pointer is
decremented by one. The content of the CCR is then stacked at the address to which the SP points.
Push instructions are commonly used to save the contents of one or
more CPU registers at the start of a subroutine. Complementary pull instructions can be used to restore the saved CPU registers just before returning from the subroutine.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PSHC
MOTOROLA
6-156
Address Mode
INH
Object Code
39
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
Os
CPU12
REFERENCE MANUAL
PSHD
PSHD
Push Double Accumulator onto Stack
Operation:
(SP) – $0002 ⇒ SP
(A : B) ⇒ M(SP) : M(SP + 1)
Description:
Stacks the content of double accumulator D. The stack pointer is decremented by two, then the contents of accumulators A and B are stacked
at the location to which the SP points.
After PSHD executes, the SP points to the stacked value of accumulator
A. This stacking order is the opposite of the order in which A and B are
stacked when an interrupt is recognized. The interrupt stacking order is
backward-compatible with the M6800, which had no 16-bit accumulator.
Push instructions are commonly used to save the contents of one or
more CPU registers at the start of a subroutine. Complementary pull instructions can be used to restore the saved CPU registers just before returning from the subroutine.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PSHD
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
3B
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
OS
MOTOROLA
6-157
PSHX
PSHX
Push Index Register X onto Stack
Operation:
(SP) – $0002 ⇒ SP
(XH : XL) ⇒ M(SP) : M(SP + 1)
Description:
Stacks the content of index register X. The stack pointer is decremented
by two. The content of X is then stacked at the address to which the SP
points. After PSHX executes, the SP points to the stacked value of the
high-order half of X.
Push instructions are commonly used to save the contents of one or
more CPU registers at the start of a subroutine. Complementary pull instructions can be used to restore the saved CPU registers just before returning from the subroutine.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PSHX
MOTOROLA
6-158
Address Mode
INH
Object Code
34
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
OS
CPU12
REFERENCE MANUAL
PSHY
PSHY
Push Index Register Y onto Stack
Operation:
(SP) – $0002 ⇒ SP
(YH : YL) ⇒ M(SP) : M(SP + 1)
Description:
Stacks the content of index register Y. The stack pointer is decremented
by two. The content of Y is then stacked at the address to which the SP
points. After PSHY executes, the SP points to the stacked value of the
high-order half of Y.
Push instructions are commonly used to save the contents of one or
more CPU registers at the start of a subroutine. Complementary pull instructions can be used to restore the saved CPU registers just before returning from the subroutine.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PSHY
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
35
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
OS
MOTOROLA
6-159
PULA
PULA
Pull A from Stack
Operation:
(M(SP)) ⇒ A
(SP) + $0001 ⇒ SP
Description:
Accumulator A is loaded from the address indicated by the stack pointer.
The SP is then incremented by one.
Pull instructions are commonly used at the end of a subroutine, to restore the contents of CPU registers that were pushed onto the stack before subroutine execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PULA
MOTOROLA
6-160
Address Mode
INH
Object Code
32
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
ufO
CPU12
REFERENCE MANUAL
PULB
PULB
Pull B from Stack
Operation:
(M(SP)) ⇒ B
(SP) + $0001 ⇒ SP
Description:
Accumulator B is loaded from the address indicated by the stack pointer.
The SP is then incremented by one.
Pull instructions are commonly used at the end of a subroutine, to restore the contents of CPU registers that were pushed onto the stack before subroutine execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PULB
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
33
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
ufO
MOTOROLA
6-161
PULC
PULC
Pull Condition Code Register
from Stack
Operation:
(M(SP)) ⇒ CCR
(SP) + $0001 ⇒ SP
Description:
The condition code register is loaded from the address indicated by the
stack pointer. The SP is then incremented by one.
Pull instructions are commonly used at the end of a subroutine, to restore the contents of CPU registers that were pushed onto the stack before subroutine execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
∆
⇓
∆
∆
∆
∆
∆
∆
Condition codes take on the value pulled from the stack, except that
the X mask bit cannot change from zero to one. Software can leave the
X bit set, leave it cleared, or change it from one to zero, but it can only
be set by a reset or by recognition of an XIRQ interrupt.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PULC
MOTOROLA
6-162
Address Mode
INH
Object Code
38
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
ufO
CPU12
REFERENCE MANUAL
PULD
PULD
Pull Double Accumulator
from Stack
Operation:
(M(SP) : M(SP + 1)) ⇒ A : B
(SP) + $0002 ⇒ SP
Description:
Double accumulator D is loaded from the address indicated by the stack
pointer. The SP is then incremented by two.
The order in which A and B are pulled from the stack is the opposite of
the order in which A and B are pulled when an RTI instruction is executed. The interrupt stacking order for A and B is backward-compatible with
the M6800, which had no 16-bit accumulator.
Pull instructions are commonly used at the end of a subroutine, to restore the contents of CPU registers that were pushed onto the stack before subroutine execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PULD
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
3A
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
UfO
MOTOROLA
6-163
PULX
PULX
Pull Index Register X from Stack
Operation:
(M(SP) : M(SP + 1)) ⇒ XH : XL
(SP) + $0002 ⇒ SP
Description:
Index register X is loaded from the address indicated by the stack pointer. The SP is then incremented by two.
Pull instructions are commonly used at the end of a subroutine, to restore the contents of CPU registers that were pushed onto the stack before subroutine execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PULX
MOTOROLA
6-164
Address Mode
INH
Object Code
30
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
UfO
CPU12
REFERENCE MANUAL
PULY
PULY
Pull Index Register Y from Stack
Operation:
(M(SP) : M(SP + 1)) ⇒ YH : YL
(SP) + $0002 ⇒ SP
Description:
Index register Y is loaded from the address indicated by the stack pointer. The SP is then incremented by two.
Pull instructions are commonly used at the end of a subroutine, to restore the contents of CPU registers that were pushed onto the stack before subroutine execution.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
PULY
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
31
INSTRUCTION GLOSSARY
Cycles
3
Access Detail
UfO
MOTOROLA
6-165
REV
REV
Fuzzy Logic Rule Evaluation
Operation:
MIN – MAX Rule Evaluation
Description:
Performs an unweighted evaluation of a list of rules, using fuzzy input
values to produce fuzzy outputs. REV can be interrupted, so it does not
adversely affect interrupt latency.
The REV instruction uses an 8-bit offset from a base address stored in
index register Y to determine the address of each fuzzy input and fuzzy
output. For REV to execute correctly, each rule in the knowledge base
must consist of a table of 8-bit antecedent offsets followed by a table of
8-bit consequent offsets. The value $FE marks boundaries between antecedents and consequents, and between successive rules. The value
$FF marks the end of the rule list. REV can evaluate any number of rules
with any number of inputs and outputs.
Beginning with the address pointed to by the first rule antecedent, REV
evaluates each successive fuzzy input value until it encounters an $FE
separator. Operation is similar to that of a MINA instruction. The smallest
input value is the truth value of the rule. Then, beginning with the address pointed to by the first rule consequent, the truth value is compared
to each successive fuzzy output value until another $FE separator is encountered; if the truth value is greater than the current output value, it is
written to the output. Operation is similar to that of a MAXM instruction.
Rules are processed until an $FF terminator is encountered.
Before executing REV, perform the following set up operations.
X must point to the first 8-bit element in the rule list.
Y must point to the base address for fuzzy inputs and fuzzy outputs.
A must contain the value $FF, and the CCR V bit must = 0
(LDAA #$FF places the correct value in A and clears V).
Clear fuzzy outputs to zeros.
Index register X points to the element in the rule list that is being evaluated. X is automatically updated so that execution can resume correctly
if the instruction is interrupted. When execution is complete, X points to
the next address after the $FF separator at the end of the rule list.
Index register Y points to the base address for the fuzzy inputs and fuzzy
outputs. The value in Y does not change during execution.
MOTOROLA
6-166
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
Accumulator A holds intermediate results. During antecedent processing, a MIN function compares each fuzzy input to the value stored in A,
and writes the smaller of the two to A. When all antecedents have been
evaluated, A contains the smallest input value. This is the truth value
used during consequent processing. Accumulator A must be initialized
to $FF for the MIN function to evaluate the inputs of the first rule correctly. For subsequent rules, the value $FF is written to A when an $FE
marker is encountered. At the end of execution, accumulator A holds the
truth value for the last rule.
The V status bit signals whether antecedents (0) or consequents (1) are
being processed. V must be initialized to zero in order for processing to
begin with the antecedents of the first rule. Once execution begins, the
value of V is automatically changed as $FE separators are encountered.
At the end of execution, V should equal one, because the last element
before the $FF end marker should be a rule consequent. If V is equal to
zero at the end of execution, the rule list is incorrect.
Fuzzy outputs must be cleared to $00 before processing begins in order
for the MAX algorithm used during consequent processing to work correctly. Residual output values would cause incorrect comparison.
Refer to SECTION 9 FUZZY LOGIC SUPPORT for details.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
?
–
?
?
∆
?
V:
1; Normally set, unless rule structure is erroneous.
H, N, Z and C may be altered by this instruction.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
see note1
Orf(ttx)O
REV
Special
18 3A
ff + Orf
(add if interrupted)
Notes:
1. The 3-cycle loop in parentheses is executed once for each element in the rule list. When an interrupt occurs,
there is a 2-cycle exit sequence, a 4-cycle re-entry sequence, then execution resumes with a prefetch of the last
antecedent or consequent being processed at the time of the interrupt.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-167
REVW
Fuzzy Logic Rule Evaluation (Weighted)
REVW
Operation:
MIN – MAX Rule Evaluation with Optional Rule Weighting
Description:
REVW performs either weighted or unweighted evaluation of a list of
rules, using fuzzy inputs to produce fuzzy outputs. REVW can be interrupted, so it does not adversely affect interrupt latency.
For REVW to execute correctly, each rule in the knowledge base must
consist of a table of 16-bit antecedent pointers followed by a table of 16bit consequent pointers. The value $FFFE marks boundaries between
antecedents and consequents, and between successive rules. The
value $FFFF marks the end of the rule list. REVW can evaluate any
number of rules with any number of inputs and outputs.
Setting the C status bit enables weighted evaluation. To use weighted
evaluation, a table of 8-bit weighting factors, one per rule, must be stored
in memory. Index register Y points to the weighting factors.
Beginning with the address pointed to by the first rule antecedent,
REVW evaluates each successive fuzzy input value until it encounters
an $FFFE separator. Operation is similar to that of a MINA instruction.
The smallest input value is the truth value of the rule. Next, if weighted
evaluation is enabled, a computation is performed, and the truth value is
modified. Then, beginning with the address pointed to by the first rule
consequent, the truth value is compared to each successive fuzzy output
value until another $FFFE separator is encountered; if the truth value is
greater than the current output value, it is written to the output. Operation
is similar to that of a MAXM instruction. Rules are processed until an
$FFFF terminator is encountered.
Perform these set up operations before execution.
X must point to the first 16-bit element in the rule list.
A must contain the value $FF, and the CCR V bit must = 0
(LDAA #$FF places the correct value in A and clears V).
Clear fuzzy outputs to zeros.
Set or clear the CCR C bit. When weighted evaluation is enabled,
Y must point to the first item in a table of 8-bit weighting factors.
Index register X points to the element in the rule list that is being evaluated. X is automatically updated so that execution can resume correctly
if the instruction is interrupted. When execution is complete, X points to
the address after the $FFFF separator at the end of the rule list.
Index register Y points to the weighting factor being used. Y is automatically updated so that execution can resume correctly if the instruction is
interrupted. When execution is complete, Y points to the last weighting
factor used. When weighting is not used (C = 0), Y is not changed.
MOTOROLA
6-168
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
Accumulator A holds intermediate results. During antecedent processing, a MIN function compares each fuzzy input to the value stored in A,
and writes the smaller of the two to A. When all antecedents have been
evaluated, A contains the smallest input value. For unweighted evaluation, this is the truth value used during consequent processing. For
weighted evaluation, the value in A is multiplied by the quantity (Rule
Weight + 1) and the upper eight bits of the result replace the content of
A. Accumulator A must be initialized to $FF for the MIN function to evaluate the inputs of the first rule correctly. For subsequent rules, the value
$FF is written to A when an $FFFE marker is encountered. At the end of
execution, accumulator A holds the truth value for the last rule.
The V status bit signals whether antecedents (0) or consequents (1) are
being processed. V must be initialized to zero in order for processing to
begin with the antecedents of the first rule. Once execution begins, the
value of V is automatically changed as $FFFE separators are encountered. At the end of execution, V should equal one, because the last element before the $FF end marker should be a rule consequent. If V is
equal to zero at the end of execution, the rule list is incorrect.
Fuzzy outputs must be cleared to $00 before processing begins in order
for the MAX algorithm used during consequent processing to work correctly. Residual output values would cause incorrect comparison.
Refer to SECTION 9 FUZZY LOGIC SUPPORT for details.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
?
–
?
?
∆
!
V:
1; Normally set, unless rule structure is erroneous.
C:
Selects weighted (1) or unweighted (0) rule evaluation.
H, N, Z and C may be altered by this instruction.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
ORf(tTx)O
REVW
Special
18 3B
See note1
(rffRf)
(add 2 at end of ins if wts)
fff + ORft
(add if interrupted)
Notes:
1. The 3-cycle loop in parentheses expands to five cycles for separators when weighting is enabled. The loop is
executed once for each element in the rule list. When an interrupt occurs, there is a 2-cycle exit sequence, a 4cycle re-entry sequence, then execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the interrupt.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-169
ROL
ROL
Rotate Left Memory
Operation:
C
Description:
b7 – – – – – – b0
Shifts all bits of memory location M one place to the left. Bit 0 is loaded
from the C status bit. The C bit is loaded from the most significant bit of
M. Rotate operations include the carry bit to allow extension of shift and
rotate operations to multiple bytes. For example, to shift a 24-bit value
one bit to the left, the sequence ASL LOW, ROL MID, ROL HIGH could
be used where LOW, MID and HIGH refer to the low-order, middle and
high-order bytes of the 24-bit value, respectively.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
M7
Set if the MSB of M was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ROL opr16a
ROL oprx0_xysp
ROL oprx9,xysp
ROL oprx16,xysp
ROL [D,xysp]
ROL [oprx16,xysp]
MOTOROLA
6-170
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
75
65
65
65
65
65
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
3
4
5
6
6
Access Detail
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
CPU12
REFERENCE MANUAL
ROLA
ROLA
Rotate Left A
Operation:
C
Description:
b7 – – – – – – b0
Shifts all bits of accumulator A one place to the left. Bit 0 is loaded from
the C status bit. The C bit is loaded from the most significant bit of A. Rotate operations include the carry bit to allow extension of shift and rotate
operations to multiple bytes. For example, to shift a 24-bit value one bit
to the left, the sequence ASL LOW, ROL MID, ROL HIGH could be used
where LOW, MID and HIGH refer to the low-order, middle and high-order
bytes of the 24-bit value, respectively.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
A7
Set if the MSB of A was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ROLA
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
45
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-171
ROLB
ROLB
Rotate Left B
Operation:
C
Description:
b7 – – – – – – b0
Shifts all bits of accumulator B one place to the left. Bit 0 is loaded from
the C status bit. The C bit is loaded from the most significant bit of B. Rotate operations include the carry bit to allow extension of shift and rotate
operations to multiple bytes. For example, to shift a 24-bit value one bit
to the left, the sequence ASL LOW, ROL MID, ROL HIGH could be used
where LOW, MID and HIGH refer to the low-order, middle and high-order
bytes of the 24-bit value, respectively.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
B7
Set if the MSB of B was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ROLB
MOTOROLA
6-172
Address Mode
INH
Object Code
55
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
ROR
ROR
Rotate Right Memory
Operation:
b7 – – – – – – b0
Description:
C
Shifts all bits of memory location M one place to the right. Bit 7 is loaded
from the C status bit. The C bit is loaded from the least significant bit of
M. Rotate operations include the carry bit to allow extension of shift and
rotate operations to multiple bytes. For example, to shift a 24-bit value
one bit to the right, the sequence LSR HIGH, ROR MID, ROR LOW
could be used where LOW, MID and HIGH refer to the low-order, middle,
and high-order bytes of the 24-bit value, respectively.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
M0
Set if the LSB of M was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
ROR opr16a
ROR oprx0_xysp
ROR oprx9,xysp
ROR oprx16,xysp
ROR [D,xysp]
ROR [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
76
66
66
66
66
66
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
4
3
4
5
6
6
Access Detail
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
MOTOROLA
6-173
RORA
RORA
Rotate Right A
Operation:
b7 – – – – – – b0
Description:
C
Shifts all bits of accumulator A one place to the right. Bit 7 is loaded from
the C status bit. The C bit is loaded from the least significant bit of A. Rotate operations include the carry bit to allow extension of shift and rotate
operations to multiple bytes. For example, to shift a 24-bit value one bit
to the right, the sequence LSR HIGH, ROR MID, ROR LOW could be
used where LOW, MID and HIGH refer to the low-order, middle, and
high-order bytes of the 24-bit value, respectively.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
A0
Set if the LSB of A was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
RORA
MOTOROLA
6-174
Address Mode
INH
Object Code
46
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
RORB
RORB
Rotate Right B
Operation:
b7 – – – – – – b0
Description:
C
Shifts all bits of accumulator B one place to the right. Bit 7 is loaded from
the C status bit. The C bit is loaded from the least significant bit of B. Rotate operations include the carry bit to allow extension of shift and rotate
operations to multiple bytes. For example, to shift a 24-bit value one bit
to the right, the sequence LSR HIGH, ROR MID, ROR LOW could be
used where LOW, MID and HIGH refer to the low-order, middle and
high-order bytes of the 24-bit value, respectively.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set); cleared otherwise (for values of N and C after the shift).
C:
B0
Set if the LSB of B was set before the shift; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
RORB
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
56
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-175
RTC
RTC
Return from Call
Operation:
(M(SP)) ⇒ PPAGE
(SP) + $0001 ⇒ SP
(M(SP) : M(SP + 1)) ⇒ PCH : PCL
(SP) + $0002 ⇒ SP
Description:
Terminates subroutines in expanded memory invoked by the CALL
instruction. Returns execution flow from the subroutine to the calling program. The program overlay page (PPAGE) register and the return address are restored from the stack; program execution continues at the
restored address. For code compatibility purposes, CALL and RTC also
execute correctly in M68HC12 devices that do not have expanded memory capability.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
RTC
MOTOROLA
6-176
Address Mode
INH
Object Code
0A
INSTRUCTION GLOSSARY
Cycles
6
Access Detail
uUnPPP
CPU12
REFERENCE MANUAL
RTI
RTI
Return from Interrupt
Operation:
(M(SP)) ⇒ CCR; (SP) + $0001 ⇒ SP
(M(SP) : M(SP + 1)) ⇒ B : A; (SP) + $0002 ⇒ SP
(M(SP) : M(SP + 1)) ⇒ XH : XL; (SP) + $0004 ⇒ SP
(M(SP) : M(SP + 1)) ⇒ PCH : PCL; (SP) – $0002 ⇒ SP
(M(SP) : M(SP + 1)) ⇒ YH : YL; (SP) + $0004 ⇒ SP
Description:
Restores system context after interrupt service processing is completed.
The condition codes, accumulators B and A, index register X, the PC,
and index register Y are restored to a state pulled from the stack. The X
mask bit may be cleared as a result of an RTI instruction, but cannot be
set if it was cleared prior to execution of the RTI instruction.
If another interrupt is pending when RTI has finished restoring registers
from the stack, the SP is adjusted to preserve stack content, and the new
vector is fetched. This operation is functionally identical to the same operation in the M68HC11, where registers actually are re-stacked, but is
faster.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
∆
⇓
∆
∆
∆
∆
∆
∆
Condition codes take on the value pulled from the stack, except that the X mask bit cannot change from zero to one. Software can leave the X bit set, leave it cleared, or
change it from one to zero, but it can only be set by a reset or by recognition of an XIRQ
interrupt.
Addressing Modes, Machine Code, and Execution Times:
Source Form
RTI
(with interrupt pending)
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
0B
INSTRUCTION GLOSSARY
Cycles
8
10
Access Detail
uUUUUPPP
uUUUUVfPPP
MOTOROLA
6-177
RTS
RTS
Return from Subroutine
Operation:
(M(SP) : M(SP + 1)) ⇒ PCH : PCL; (SP) + $0002 ⇒ SP
Description:
Restores context at the end of a subroutine. Loads the program counter
with a 16-bit value pulled from the stack and increments the stack pointer
by two. Program execution continues at the address restored from the
stack.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
RTS
MOTOROLA
6-178
Address Mode
INH
Object Code
3D
INSTRUCTION GLOSSARY
Cycles
5
Access Detail
UfPPP
CPU12
REFERENCE MANUAL
SBA
SBA
Subtract Accumulators
Operation:
(A) – (B) ⇒ A
Description:
Subtracts the content of accumulator B from the content of accumulator
A and places the result in A. The content of B is not affected. For subtraction instructions, the C status bit represents a borrow.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
A7 • B7 • R7 + A7 • B7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
A7 • B7 + B7 • R7 + R7 • A7
Set if the absolute value of B is larger than the absolute value of A;
cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
SBA
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
18 16
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
OO
MOTOROLA
6-179
SBCA
SBCA
Subtract with Carry from A
Operation:
(A) – (M) – C ⇒ A
Description:
Subtracts the content of memory location M and the value of the C status
bit from the content of accumulator A. The result is placed in A. For subtraction instructions, the C status bit represents a borrow.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if the absolute value of the content of memory plus previous
carry is larger than the absolute value of the accumulator; cleared
otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
SBCA #opr8i
SBCA opr8a
SBCA opr16a
SBCA oprx0_xysp
SBCA oprx9,xysp
SBCA oprx16,xysp
SBCA [D,xysp]
SBCA [oprx16,xysp]
MOTOROLA
6-180
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
82
92
B2
A2
A2
A2
A2
A2
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
SBCB
SBCB
Subtract with Carry from B
Operation:
(B) – (M) – C ⇒ B
Description:
Subtracts the content of memory location M and the value of the C status
bit from the content of accumulator B. The result is placed in B. For subtraction instructions, the C status bit represents a borrow.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if the absolute value of the content of memory plus previous carry
is larger than the absolute value of the accumulator; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
SBCB #opr8i
SBCB opr8a
SBCB opr16a
SBCB oprx0_xysp
SBCB oprx9,xysp
SBCB oprx16,xysp
SBCB [D,xysp]
SBCB [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
C2
D2
F2
E2
E2
E2
E2
E2
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
MOTOROLA
6-181
SEC
SEC
Set Carry
Operation:
1 ⇒ C bit
Description:
Sets the C status bit. This instruction is assembled as ORCC #$01. The
ORCC instruction can be used to set any combination of bits in the CCR
in one operation.
SEC can be used to set up the C bit prior to a shift or rotate instruction
involving the C bit.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
1
C:
1; Set.
Addressing Modes, Machine Code, and Execution Times:
Source Form
SEC translates to...
ORCC #$01
MOTOROLA
6-182
Address Mode
IMM
Object Code
14 01
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
CPU12
REFERENCE MANUAL
SEI
SEI
Set Interrupt Mask
Operation:
1 ⇒ I bit
Description:
Sets the I mask bit. This instruction is assembled as ORCC #$10. The
ORCC instruction can be used to set any combination of bits in the CCR
in one operation. When the I bit is set, all maskable interrupts are inhibited, and the CPU will recognize only non-maskable interrupt sources or
an SWI.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
1
–
–
–
–
I:
1; Set.
Addressing Modes, Machine Code, and Execution Times:
Source Form
SEI translates to...
ORCC #$10
CPU12
REFERENCE MANUAL
Address Mode
IMM
Object Code
14 10
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
MOTOROLA
6-183
SEV
SEV
Set Two’s Complement Overflow Bit
Operation:
1 ⇒ V bit
Description:
Sets the V status bit. This instruction is assembled as ORCC #$02. The
ORCC instruction can be used to set any combination of bits in the CCR
in one operation.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
1
–
V:
1; Set.
Addressing Modes, Machine Code, and Execution Times:
Source Form
SEV translates to...
ORCC #$02
MOTOROLA
6-184
Address Mode
IMM
Object Code
14 02
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
CPU12
REFERENCE MANUAL
SEX
SEX
Sign Extend into 16-bit Register
Operation:
If r1 bit 7 = 0, then $00 : (r1) ⇒ r2
If r1 bit 7 = 1, then $FF : (r1) ⇒ r2
Description:
This instruction is an alternate mnemonic for the TFR r1,r2 instruction,
where r1 is an 8-bit register and r2 is a 16-bit register. The result in r2 is
the 16-bit sign extended representation of the original two’s complement
number in r1. The content of r1 is unchanged in all cases except that of
SEX A,D (D is A : B).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code1
Cycles
Access Detail
SEX abc,dxys
INH
B7 eb
1
P
Notes:
1. Legal coding for eb is summarized in the following table. Columns represent the high-order digit, and rows represent the low-order digit in hexadecimal (MSB is a don’t-care).
CPU12
REFERENCE MANUAL
0
1
2
3
sex:A ⇒ TMP2
sex:B ⇒ TMP2
sex:CCR ⇒ TMP2
4
sex:A ⇒ D
SEX A,D
sex:B ⇒ D
SEX B,D
sex:CCR ⇒ D
SEX CCR,D
5
sex:A ⇒ X
SEX A,X
sex:B ⇒ X
SEX B,X
sex:CCR ⇒ X
SEX CCR,X
6
sex:A ⇒ Y
SEX A,Y
sex:B ⇒ Y
SEX B,Y
sex:CCR ⇒ Y
SEX CCR,Y
7
sex:A ⇒ SP
SEX A,SP
sex:B ⇒ SP
SEX B,SP
sex:CCR ⇒ SP
SEX CCR,SP
INSTRUCTION GLOSSARY
MOTOROLA
6-185
STAA
STAA
Store Accumulator A
Operation:
(A) ⇒ M
Description:
Stores the content of accumulator A in memory location M. The content
of A is unchanged.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
STAA opr8a
STAA opr16a
STAA oprx0_xysp
STAA oprx9,xysp
STAA oprx16,xysp
STAA [D,xysp]
STAA [oprx16,xysp]
MOTOROLA
6-186
Address Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
5A
7A
6A
6A
6A
6A
6A
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
2
3
3
5
5
Access Detail
Pw
wOP
Pw
PwO
PwP
PIfPw
PIPPw
CPU12
REFERENCE MANUAL
STAB
STAB
Store Accumulator B
Operation:
(B) ⇒ M
Description:
Stores the content of accumulator B in memory location M. The content
of B is unchanged.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
STAB opr8a
STAB opr16a
STAB oprx0_xysp
STAB oprx9,xysp
STAB oprx16,xysp
STAB [D,xysp]
STAB [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
5B
7B
6B
6B
6B
6B
6B
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
2
3
3
5
5
Access Detail
Pw
wOP
Pw
PwO
PwP
PIfPw
PIPPw
MOTOROLA
6-187
STD
STD
Store Double Accumulator
Operation:
(A : B) ⇒ M : M + 1
Description:
Stores the content of double accumulator D in memory location M : M +
1. The content of D is unchanged.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
STD opr8a
STD opr16a
STD oprx0_xysp
STD oprx9,xysp
STD oprx16,xysp
STD [D,xysp]
STD [oprx16,xysp]
MOTOROLA
6-188
Address Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
5C
7C
6C
6C
6C
6C
6C
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
2
3
3
5
5
Access Detail
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
CPU12
REFERENCE MANUAL
STOP
STOP
Stop Processing
Operation:
(SP) – $0002 ⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; YH : YL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; XH : XL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; B : A⇒ (M(SP) : M(SP + 1))
(SP) – $0001 ⇒ SP; CCR ⇒ (M(SP))
Stop All Clocks
Description:
When the S control bit is set, STOP is disabled and operates like a twocycle NOP instruction. When the S bit is cleared, STOP stacks CPU context, stops all system clocks, and puts the device in standby mode.
Standby operation minimizes system power consumption. The contents
of registers and the states of I/O pins remain unchanged.
Asserting the RESET, XIRQ, or IRQ signals ends standby mode. Stacking on entry to STOP allows the CPU to recover quickly when an interrupt is used, provided a stable clock is applied to the device. If the
system uses a clock reference crystal that also stops during low-power
mode, crystal start-up delay lengthens recovery time.
If XIRQ is asserted while the X mask bit = 0 (XIRQ interrupts enabled),
execution resumes with a vector fetch for the XIRQ interrupt. If the X
mask bit = 1(XIRQ interrupts disabled), a two-cycle recovery sequence
including an O cycle is used to adjust the instruction queue, and execution continues with the next instruction after STOP.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
STOP (entering STOP)
(exiting STOP)
(continue)
(if STOP disabled)
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
18 3E
INSTRUCTION GLOSSARY
Cycles
9
5
2
2
Access Detail
OOSSSfSsf
VfPPP
fO
OO
MOTOROLA
6-189
STS
STS
Store Stack Pointer
Operation:
(SPH : SPL) ⇒ M : M + 1
Description:
Stores the content of the stack pointer in memory. The most significant
byte of the SP is stored at the specified address, and the least significant
byte of the SP is stored at the next higher byte address (the specified address plus one).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
STS opr8a
STS opr16a
STS oprx0_xysp
STS oprx9,xysp
STS oprx16,xysp
STS [D,xysp]
STS [oprx16,xysp]
MOTOROLA
6-190
Address Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
5F
7F
6F
6F
6F
6F
6F
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
2
3
3
5
5
Access Detail
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
CPU12
REFERENCE MANUAL
STX
STX
Store Index Register X
Operation:
(XH : XL) ⇒ M : M + 1
Description:
Stores the content of index register X in memory. The most significant
byte of X is stored at the specified address, and the least significant byte
of X is stored at the next higher byte address (the specified address plus
one).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
STX opr8a
STX opr16a
STX oprx0_xysp
STX oprx9,xysp
STX oprx16,xysp
STX [D,xysp]
STX [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
5E
7E
6E
6E
6E
6E
6E
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
2
3
3
5
5
Access Detail
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
MOTOROLA
6-191
STY
STY
Store Index Register Y
Operation:
(YH : YL) ⇒ M : M + 1
Description:
Stores the content of index register Y in memory. The most significant
byte of Y is stored at the specified address, and the least significant byte
of Y is stored at the next higher byte address (the specified address plus
one).
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
STY opr8a
STY opr16a
STY oprx0_xysp
STY oprx9,xysp
STY oprx16,xysp
STY [D,xysp]
STY [oprx16,xysp]
MOTOROLA
6-192
Address Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
5D
7D
6D
6D
6D
6D
6D
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
2
3
3
5
5
Access Detail
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
CPU12
REFERENCE MANUAL
SUBA
SUBA
Subtract A
Operation:
(A) – (M) ⇒ A
Description:
Subtracts the content of memory location M from the content of accumulator A, and places the result in A. For subtraction instructions, the C status bit represents a borrow.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
SUBA #opr8i
SUBA opr8a
SUBA opr16a
SUBA oprx0_xysp
SUBA oprx9,xysp
SUBA oprx16,xysp
SUBA [D,xysp]
SUBA [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
80
90
B0
A0
A0
A0
A0
A0
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
MOTOROLA
6-193
SUBB
SUBB
Subtract B
Operation:
(B) – (M) ⇒ B
Description:
Subtracts the content of memory location M from the content of accumulator B and places the result in B. For subtraction instructions, the C status bit represents a borrow.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
X7 • M7 • R7 + X7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
X7 • M7 + M7 • R7 + R7 • X7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
SUBB #opr8i
SUBB opr8a
SUBB opr16a
SUBB oprx0_xysp
SUBB oprx9,xysp
SUBB oprx16,xysp
SUBB [D,xysp]
SUBB [oprx16,xysp]
MOTOROLA
6-194
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
C0
D0
F0
E0
E0
E0
E0
E0
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
1
3
3
3
3
4
6
6
Access Detail
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
SUBD
SUBD
Subtract Double Accumulator
Operation:
(A : B) – (M : M + 1) ⇒ A : B
Description:
Subtracts the content of memory location M : M + 1 from the content of
double accumulator D and places the result in D. For subtraction instructions, the C status bit represents a borrow.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $0000; cleared otherwise.
V:
D15 • M15 • R15 + D15 • M15 • R15
Set if a two’s complement overflow resulted from the operation;
cleared otherwise.
C:
D15 • M15 + M15 • R15 + R15 • D15
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise.
Addressing Modes, Machine Code, and Execution Times:
Source Form
SUBD #opr16i
SUBD opr8a
SUBD opr16a
SUBD oprx0_xysp
SUBD oprx9,xyssp
SUBD oprx16,xysp
SUBD [D,xysp]
SUBD [oprx16,xysp]
CPU12
REFERENCE MANUAL
Address Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
83
93
B3
A3
A3
A3
A3
A3
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
2
3
3
3
3
4
6
6
Access Detail
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
MOTOROLA
6-195
SWI
SWI
Software Interrupt
Operation:
(SP) – $0002 ⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; YH : YL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; XH : XL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; B : A⇒ (M(SP) : M(SP + 1))
(SP) – $0001 ⇒ SP; CCR ⇒ (M(SP))
1⇒I
(SWI Vector) ⇒ PC
Description:
Causes an interrupt without an external interrupt service request. Uses
the address of the next instruction after SWI as a return address. Stacks
the return address, index registers Y and X, accumulators B and A, and
the CCR, decrementing the SP before each item is stacked. The I mask
bit is then set, the PC is loaded with the SWI vector, and instruction execution resumes at that location. SWI is not affected by the I mask bit.
Refer to SECTION 7 EXCEPTION PROCESSING for more information.
Condition Codes and Boolean Formulas:
I:
S
X
H
I
N
Z
V
C
–
–
–
1
–
–
–
–
1; Set.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
SWI
INH
3F
9
VSPSSPSsP1
Notes:
1. The CPU also uses the SWI processing sequence for hardware interrupts and unimplemented opcode traps. A
variation of the sequence (VfPPP) is used for resets.
MOTOROLA
6-196
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
TAB
TAB
Transfer from Accumulator A
to Accumulator B
Operation:
(A) ⇒ B
Description:
Moves the content of accumulator A to accumulator B. The former content of B is lost; the content of A is not affected. Unlike the general transfer instruction TFR A,B which does not affect condition codes, the TAB
instruction affects the N, Z, and V status bits for compatibility with
M68HC11.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TAB
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
18 0E
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
OO
MOTOROLA
6-197
TAP
TAP
Transfer from Accumulator A
to Condition Code Register
Operation:
(A) ⇒ CCR
Description:
Transfers the logic states of bits [7:0] of accumulator A to the corresponding bit positions of the CCR. The content of A remains unchanged.
The X mask bit can be cleared as a result of a TAP, but cannot be set if
it was cleared prior to execution of the TAP. If the I bit is cleared, there
is a one cycle delay before the system allows interrupt requests. This
prevents interrupts from occurring between instructions in the sequences CLI, WAI and CLI, SEI.
This instruction is accomplished with the TFR A,CCR instruction. For
compatibility with the M68HC11, the mnemonic TAP is translated by the
assembler.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
∆
⇓
∆
∆
∆
∆
∆
∆
Condition codes take on the value of the corresponding bit of accumulator A, except that the X mask bit cannot change from zero to one.
Software can leave the X bit set, leave it cleared, or change it from one
to zero, but it can only be set by a reset or by recognition of an XIRQ
interrupt.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TAP translates to...
TFR A,CCR
MOTOROLA
6-198
Address Mode
INH
Object Code
B7 02
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
CPU12
REFERENCE MANUAL
TBA
TBA
Transfer from Accumulator B
to Accumulator A
Operation:
(B) ⇒ A
Description:
Moves the content of accumulator B to accumulator A. The former content of A is lost; the content of B is not affected. Unlike the general transfer instruction TFR B,A, which does not affect condition codes, the TBA
instruction affects N, Z, and V for compatibility with M68HC11.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TBA
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
18 0F
INSTRUCTION GLOSSARY
Cycles
2
Access Detail
OO
MOTOROLA
6-199
TBEQ
TBEQ
Test and Branch if Equal to Zero
Operation:
If (Counter) = 0, then (PC) + $0003 + Rel ⇒ PC
Description:
Tests the specified counter register A, B, D, X, Y, or SP. If the counter
register is zero, branches to the specified relative destination. TBEQ is
encoded into three bytes of machine code including a 9-bit relative offset
(–256 to +255 locations from the start of the next instruction).
DBEQ and IBEQ instructions are similar to TBEQ, except that the
counter is decremented or incremented rather than simply being tested.
Bits 7 and 6 of the instruction postbyte are used to determine which operation is to be performed.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Object Code1
Address Mode
Cycles
Access Detail
TBEQ abdxys,rel9
REL
04 lb rr
3/3
PPP
Notes:
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero
(TBEQ – 0) or not zero (TBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should
be 0:1 for TBEQ.
Object Code
(if offset is positive)
Object Code
(if offset is negative)
Count
Register
Bits 2:0
A
B
000
001
TBEQ A, rel9
TBEQ B, rel9
04 40 rr
04 41 rr
04 50 rr
04 51 rr
D
X
Y
SP
100
101
110
111
TBEQ D, rel9
TBEQ X, rel9
TBEQ Y, rel9
TBEQ SP, rel9
04
04
04
04
04
04
04
04
MOTOROLA
6-200
Source Form
44
45
46
47
rr
rr
rr
rr
INSTRUCTION GLOSSARY
54
55
56
57
rr
rr
rr
rr
CPU12
REFERENCE MANUAL
TBL
TBL
Table Lookup and Interpolate
Operation:
(M) + [(B) × ((M+1) – (M))] ⇒ A
Description:
Linearly interpolates one of 256 result values that fall between each pair
of data entries in a lookup table stored in memory. Data points in the
table represent the endpoints of equally spaced line segments. Table
entries and the interpolated result are 8-bit values. The result is stored
in accumulator A.
Before executing TBL, set up an index register so that it will point to the
starting point (X1) of a line segment when the instruction is executed. X1
is the table entry closest to, but less than or equal to, the desired lookup
value. The next table entry after X1 is X2. XL is the X position of the desired lookup point. Load accumulator B with a binary fraction (radix point
to left of MSB), representing the ratio (XL–X1) ÷ (X2–X1).
The 8-bit unrounded result is calculated using the following expression:
A = Y1 + [(B) × (Y2 – Y1)]
Where
(B) = (XL – X1) ÷ (X2 – X1)
Y1 = 8-bit data entry pointed to by <effective address>
Y2 = 8-bit data entry pointed to by <effective address> + 1
The intermediate value [(B) × (Y2 – Y1)] produces a 16-bit result with the
radix point between bits 7 and 8. The result in A is the upper 8-bits (integer part) of this intermediate 16-bit value, plus the 8-bit value Y1.
Any indexed addressing mode referenced to X, Y, SP, or PC, except indirect modes or 9-bit and 16-bit offset modes, can be used to identify the
first data point (X1,Y1). The second data point is the next table entry.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
–
?
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
C:
Undefined.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TBL oprx0_xysp
CPU12
REFERENCE MANUAL
Address Mode
IDX
Object Code
18 3D xb
INSTRUCTION GLOSSARY
Cycles
8
Access Detail
OrrffffP
MOTOROLA
6-201
TBNE
TBNE
Test and Branch if Not Equal to Zero
Operation:
If (Counter) ≠ 0, then (PC) + $0003 + Rel ⇒ PC,
Description:
Tests the specified counter register A, B, D, X, Y, or SP. If the counter
register is not zero, branches to the specified relative destination. TBNE
is encoded into three bytes of machine code including a 9-bit relative offset (–256 to +255 locations from the start of the next instruction).
DBNE and IBNE instructions are similar to TBNE, except that the
counter is decremented or incremented rather than simply being tested.
Bits 7 and 6 of the instruction postbyte are used to determine which operation is to be performed.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Object Code1
Address Mode
Cycles
Access Detail
TBNE abdxys,rel9
REL
04 lb rr
3/3
PPP
Notes:
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero
(TBEQ – 0) or not zero (TBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should
be 0:1 for TBNE.
Object Code
(if offset is positive)
Object Code
(if offset is negative)
Count
Register
Bits 2:0
A
B
000
001
TBNE A, rel9
TBNE B, rel9
04 60 rr
04 61 rr
04 70 rr
04 71 rr
D
X
Y
SP
100
101
110
111
TBNE D, rel9
TBNE X, rel9
TBNE Y, rel9
TBNE SP, rel9
04
04
04
04
04
04
04
04
MOTOROLA
6-202
Source Form
64
65
66
67
rr
rr
rr
rr
INSTRUCTION GLOSSARY
74
75
76
77
rr
rr
rr
rr
CPU12
REFERENCE MANUAL
TFR
TFR
Transfer Register Content
to Another Register
Operation:
See table.
Description:
Transfers the content of a source register to a destination register specified in the instruction. The order in which transfers between 8-bit and 16bit registers are specified affects the high byte of the 16-bit registers differently. Cases involving TMP2 and TMP3 are reserved for Motorola
use, so some assemblers may not permit their use. It is possible to generate these cases by using DC.B or DC.W assembler directives.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
∆
∆
∆
∆
or
∆
⇓
∆
∆
None affected, unless the CCR is the destination register. Condition
codes take on the value of the corresponding source bits, except that
the X mask bit cannot change from zero to one. Software can leave
the X bit set, leave it cleared, or change it from one to zero, but it can
only be set by a reset or by recognition of an XIRQ interrupt.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code1
Cycles
Access Detail
TFR abcdxys,abcdxys
INH
B7 eb
1
P
Notes:
1. Legal coding for eb is summarized in the following table. Columns represent the high-order digit, and rows represent the low-order digit in hexadecimal (MSB is a don’t-care).
0
1
2
3
4
5
6
7
0
A⇒A
B⇒A
CCR ⇒ A
TMP3L ⇒ A
B⇒A
XL ⇒ A
YL ⇒ A
SPL ⇒ A
1
A⇒B
B⇒B
CCR ⇒ B
TMP3L ⇒ B
B⇒B
XL ⇒ B
YL ⇒ B
SPL ⇒ B
2
A ⇒ CCR
B ⇒ CCR
CCR ⇒ CCR
TMP3L ⇒ CCR
B ⇒ CCR
XL ⇒ CCR
YL ⇒ CCR
SPL ⇒ CCR
TMP3 ⇒ TMP2
D ⇒ TMP2 X ⇒ TMP2
Y ⇒ TMP2
SP ⇒ TMP2
3 sex:A ⇒ TMP2 sex:B ⇒ TMP2 sex:CCR ⇒ TMP2
4
sex:A ⇒ D
SEX A,D
sex:B ⇒ D
SEX B,D
sex:CCR ⇒ D
SEX CCR,D
TMP3 ⇒ D
D⇒D
X⇒D
Y⇒D
SP ⇒ D
5
sex:A ⇒ X
SEX A,X
sex:B ⇒ X
SEX B,X
sex:CCR ⇒ X
SEX CCR,X
TMP3 ⇒ X
D⇒X
X⇒X
Y⇒X
SP ⇒ X
6
sex:A ⇒ Y
SEX A,Y
sex:B ⇒ Y
SEX B,Y
sex:CCR ⇒ Y
SEX CCR,Y
TMP3 ⇒ Y
D⇒Y
X⇒Y
Y⇒Y
SP ⇒ Y
7
sex:A ⇒ SP
SEX A,SP
sex:B ⇒ SP
SEX B,SP
sex:CCR ⇒ SP
SEX CCR,SP
TMP3 ⇒ SP
D ⇒ SP
X ⇒ SP
Y ⇒ SP
SP ⇒ SP
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-203
TPA
TPA
Transfer from Condition Code
Register to Accumulator A
Operation:
(CCR) ⇒ A
Description:
Transfers the content of the condition code register to corresponding bit
positions of accumulator A. The CCR remains unchanged.
This mnemonic is implemented by the TFR CCR,A instruction. For compatibility with the M68HC11, the mnemonic TPA is translated into the
TFR CCR,A instruction by the assembler.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TPA translates to...
TFR CCR,A
MOTOROLA
6-204
Address Mode
INH
Object Code
B7 20
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
CPU12
REFERENCE MANUAL
TRAP
Unimplemented Opcode Trap
TRAP
Operation:
(SP) – $0002 ⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; YH : YL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; XH : XL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; B : A⇒ (M(SP) : M(SP + 1))
(SP) – $0001 ⇒ SP; CCR ⇒ (M(SP))
1⇒I
(Trap Vector) ⇒ PC
Description:
Traps unimplemented opcodes. There are opcodes in all 256 positions
in the page 1 opcode map, but only 54 of the 256 positions on page 2 of
the opcode map are used. If the CPU attempts to execute one of the unimplemented opcodes on page 2, an opcode trap interrupt occurs. Unimplemented opcode traps are essentially interrupts that share the
$FFF8:$FFF9 interrupt vector.
TRAP uses the next address after the unimplemented opcode as a return address. It stacks the return address, index registers Y and X, accumulators B and A, and the CCR, automatically decrementing the SP
before each item is stacked. The I mask bit is then set, the PC is loaded
with the trap vector, and instruction execution resumes at that location.
This instruction is not maskable by the I bit. Refer to SECTION 7 EXCEPTION PROCESSING for more information.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
1
–
–
–
–
I:
1; Set.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
$18 tn1
TRAP trapnum
INH
11
OfVSPSSPSsP
Notes:
1. The value tn represents an unimplemented page 2 opcode in either of the two ranges $30 to $39 or $40 to $FF.
CPU12
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-205
TST
TST
Test Memory
Operation:
(M) – $00
Description:
Subtracts $00 from the content of memory location M and sets the condition codes accordingly.
The subtraction is accomplished internally without modifying M.
The TST instruction provides limited information when testing unsigned
values. Since no unsigned value is less than zero, BLO and BLS have
no utility following TST. While BHI can be used after TST, it performs the
same function as BNE, which is preferred. After testing signed values,
all signed branches are available.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
0
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
C:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TST opr16a
TST oprx0_xysp
TST oprx9,xysp
TST oprx16,xysp
TST [D,xysp]
TST [oprx16,xysp]
MOTOROLA
6-206
Address Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
F7
E7
E7
E7
E7
E7
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
INSTRUCTION GLOSSARY
Cycles
3
3
3
4
6
6
Access Detail
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
CPU12
REFERENCE MANUAL
TSTA
TSTA
Test A
Operation:
(A) – $00
Description:
Subtracts $00 from the content of accumulator A and sets the condition
codes accordingly.
The subtraction is accomplished internally without modifying A.
The TSTA instruction provides limited information when testing unsigned values. Since no unsigned value is less than zero, BLO and BLS
have no utility following TSTA. While BHI can be used after TST, it performs the same function as BNE, which is preferred. After testing signed
values, all signed branches are available.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
0
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
C:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TSTA
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
97
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
MOTOROLA
6-207
TSTB
TSTB
Test B
Operation:
(B) – $00
Description:
Subtracts $00 from the content of accumulator B and sets the condition
codes accordingly.
The subtraction is accomplished internally without modifying B.
The TSTB instruction provides limited information when testing unsigned values. Since no unsigned value is less than zero, BLO and BLS
have no utility following TSTB. While BHI can be used after TST, it performs the same function as BNE, which is preferred. After testing signed
values, all signed branches are available.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
0
N:
Set if MSB of result is set; cleared otherwise.
Z:
Set if result is $00; cleared otherwise.
V:
0; Cleared.
C:
0; Cleared.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TSTB
MOTOROLA
6-208
Address Mode
INH
Object Code
D7
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
O
CPU12
REFERENCE MANUAL
TSX
TSX
Transfer from Stack Pointer
to Index Register X
Operation:
(SP) ⇒ X
Description:
This is an alternate mnemonic to transfer the stack pointer value to index
register X. The content of the SP remains unchanged. After a TSX instruction, X points at the last value that was stored on the stack.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TSX translates to...
TFR SP,X
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
B7 75
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
MOTOROLA
6-209
TSY
TSY
Transfer from Stack Pointer
to Index Register Y
Operation:
(SP) ⇒ Y
Description:
This is an alternate mnemonic to transfer the stack pointer value to index
register Y. The content of the SP remains unchanged. After a TSY instruction, Y points at the last value that was stored on the stack.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TSY translates to...
TFR SP,Y
MOTOROLA
6-210
Address Mode
INH
Object Code
B7 76
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
CPU12
REFERENCE MANUAL
TXS
TXS
Transfer from Index Register X
to Stack Pointer
Operation:
(X) ⇒ SP
Description:
This is an alternate mnemonic to transfer index register X value to the
stack pointer. The content of X is unchanged.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TXS translates to...
TFR X,SP
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
B7 57
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
MOTOROLA
6-211
TYS
TYS
Transfer from Index Register Y
to Stack Pointer
Operation:
(Y) ⇒ SP
Description:
This is an alternate mnemonic to transfer index register Y value to the
stack pointer. The content of Y is unchanged.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
TYS translates to...
TFR Y,SP
MOTOROLA
6-212
Address Mode
INH
Object Code
B7 67
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
CPU12
REFERENCE MANUAL
WAI
WAI
Wait for Interrupt
Operation:
(SP) – $0002 ⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; YH : YL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; XH : XL ⇒ (M(SP) : M(SP + 1))
(SP) – $0002 ⇒ SP; B : A⇒ (M(SP) : M(SP + 1))
(SP) – $0001 ⇒ SP; CCR ⇒ (M(SP))
Stop CPU Clocks
Description:
Puts the CPU into a wait state. Uses the address of the instruction following WAI as a return address. Stacks the return address, index registers Y and X, accumulators B and A, and the CCR, decrementing the SP
before each item is stacked.
The CPU then enters a wait state for an integer number of bus clock cycles. During the wait state, CPU clocks are stopped, but other MCU
clocks can continue to run. The CPU leaves the wait state when it senses an interrupt that has not been masked.
Upon leaving the wait state, the CPU sets the appropriate interrupt mask
bit(s), fetches the vector corresponding to the interrupt sensed, and instruction execution continues at the location the vector points to.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Although the WAI instruction itself does not alter the condition codes,
the interrupt that causes the CPU to resume processing also causes
the I mask bit (and the X mask bit, if the interrupt was XIRQ) to be set
as the interrupt vector is fetched.
Addressing Modes, Machine Code, and Execution Times:
Source Form
WAI (before interrupt)
(when interrupt comes)
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
3E
INSTRUCTION GLOSSARY
Cycles
8
5
Access Detail
OSSSfSsf
VfPPP
MOTOROLA
6-213
WAV
WAV
Weighted Average
Operation:
Do until B = 0, leave SOP in Y : D, SOW in X
Partial Product = (M pointed to by X) × (M pointed to by Y)
Sum-of-Products (24-bit SOP) = Previous SOP + Partial Product
Sum-of-Weights (16-bit SOW) = Previous SOW + (M pointed to by Y)
(X) + $0001 ⇒ X; (Y) + $0001 ⇒ Y
(B) – $01 ⇒ B
Description:
Performs weighted average calculations on values stored in memory.
Uses indexed (X) addressing mode to reference one source operand list,
and indexed (Y) addressing mode to reference a second source operand
list. Accumulator B is used as a counter to control the number of elements to be included in the weighted average.
For each pair of data points, a 24-bit sum of products (SOP) and a 16bit sum of weights (SOW) is accumulated in temporary registers. When
B reaches zero (no more data pairs), the SOP is placed in Y : D. The
SOW is placed in X. To arrive at the final weighted average, divide the
content of Y : D by X by executing an EDIV after the WAV.
This instruction can be interrupted. If an interrupt occurs during WAV execution, the intermediate results (six bytes) are stacked in the order
SOW[15:0], SOP[15:0], $00:SOP[23:16] before the interrupt is processed.
The wavr pseudo-instruction is used to resume execution after an interrupt. The mechanism is re-entrant. New WAV instructions can be started
and interrupted while a previous WAV instruction is interrupted.
This instruction is often used in fuzzy logic rule evaluation. Refer to SECTION 9 FUZZY LOGIC SUPPORT for more information.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
?
–
?
1
?
?
Z:
1; Set.
H, N, V and C may be altered by this instruction.
Addressing Modes, Machine Code, and Execution Times:
Source Form
Address Mode
Object Code
Cycles
Access Detail
WAV
Special
18 3C
See note1 Off(frrfffff)O
(add if interrupted)
SSSUUUrr
Notes:
1. The 8-cycle sequence in parentheses represents the loop for one iteration of SOP and SOW accumulation.
MOTOROLA
6-214
INSTRUCTION GLOSSARY
CPU12
REFERENCE MANUAL
XGDX
XGDX
Exchange Double Accumulator
and Index Register X
Operation:
(D) ⇔ (X)
Description:
Exchanges the content of double accumulator D and the content of index
register X. For compatibility with the M68HC11, the XGDX instruction is
translated into an EXG D,X instruction by the assembler.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
XGDX translates to...
EXG D,X
CPU12
REFERENCE MANUAL
Address Mode
INH
Object Code
B7 C5
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
MOTOROLA
6-215
XGDY
XGDY
Exchange Double Accumulator
and Index Register Y
Operation:
(D) ⇔ (Y)
Description:
Exchanges the content of double accumulator D and the content of index
register Y. For compatibility with the M68HC11, the XGDY instruction is
translated into an EXG D,Y instruction by the assembler.
Condition Codes and Boolean Formulas:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
None affected.
Addressing Modes, Machine Code, and Execution Times:
Source Form
XGDY translates to...
EXG D,Y
MOTOROLA
6-216
Address Mode
INH
Object Code
B7 C6
INSTRUCTION GLOSSARY
Cycles
1
Access Detail
P
CPU12
REFERENCE MANUAL
SECTION 7
EXCEPTION PROCESSING
Exceptions are events that require processing outside the normal flow of instruction
execution. This section describes exceptions and the way each is handled.
7.1 Types of Exceptions
CPU12 exceptions include resets, an unimplemented opcode trap, a software interrupt
instruction, X-bit interrupts, and I-bit interrupts. Each exception has an associated 16bit vector, which points to the memory location where the routine that handles the exception is located. As shown in Table 7-1, vectors are stored in the upper 128 bytes
of the standard 64-Kbyte address map.
Table 7-1 CPU12 Exception Vector Map
Vector Address
Source
$FFFE–$FFFF
System Reset
$FFFC–$FFFD
Clock Monitor Reset
$FFFA–$FFFB
COP Reset
$FFF8–$FFF9
Unimplemented Opcode Trap
$FFF6–$FFF7
Software Interrupt Instruction (SWI)
$FFF4–$FFF5
XIRQ Signal
$FFF2–$FFF3
IRQ Signal
$FFC0–$FFF1
Device-Specific Interrupt Sources
The six highest vector addresses are used for resets and unmaskable interrupt sources. The remaining vectors are used for maskable interrupts. All vectors must be programmed to point to the address of the appropriate service routine.
The CPU12 can handle up to 64 exception vectors, but the number actually used varies from device to device, and some vectors are reserved for Motorola use. Refer to
device documentation for more information.
Exceptions can be classified by the effect of the X and I interrupt mask bits on recognition of a pending request.
Resets, the unimplemented opcode trap, and the SWI instruction are not affected
by the X and I mask bits.
Interrupt service requests from the XIRQ pin are inhibited when X = 1, but are not
affected by the I bit.
All other interrupts are inhibited when I = 1.
CPU12
REFERENCE MANUAL
EXCEPTION PROCESSING
MOTOROLA
7-1
7.2 Exception Priority
A hardware priority hierarchy determines which reset or interrupt is serviced first when
simultaneous requests are made. Six sources are not maskable. The remaining sources are maskable, and the device integration module typically can change the relative
priorities of maskable interrupts. Refer to 7.4 Interrupts for more detail concerning interrupt priority and servicing.
The priorities of the unmaskable sources are:
1. RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ signal
5. Unimplemented opcode trap
6. Software interrupt instruction (SWI)
An external reset has the highest exception-processing priority, followed by clock
monitor reset, and then the on-chip watchdog reset.
The XIRQ interrupt is pseudo-non-maskable. After reset, the X bit in the CCR is set,
which inhibits all interrupt service requests from the XIRQ pin until the X bit is cleared.
The X bit can be cleared by a program instruction, but program instructions cannot reset X from zero to one. Once the X bit is cleared, interrupt service requests made via
the XIRQ pin become non-maskable.
The unimplemented page 2 opcode trap (TRAP) and the software interrupt instruction
(SWI) are special cases. In one sense, these two exceptions have very low priority,
because any enabled interrupt source that is pending prior to the time exception processing begins will take precedence. However, once the CPU begins processing a
TRAP or SWI, neither can be interrupted. Also, since these are mutually exclusive instructions, they have no relative priority.
All remaining interrupts are subject to masking via the I bit in the CCR. Most M68HC12
MCUs have an external IRQ pin, which is assigned the highest I-bit interrupt priority,
and an internal periodic real-time interrupt generator, which has the next highest priority. The other maskable sources have default priorities that follow the address order
of the interrupt vectors — the higher the address, the higher the priority of the interrupt.
Other maskable interrupts are associated with on-chip peripherals such as timers or
serial ports. Typically, logic in the device integration module can give one I-masked
source priority over other I-masked sources. Refer to the documentation for the specific M68HC12 derivative for more information.
7.3 Resets
M68HC12 devices perform resets with a combination of hardware and software. Integration module circuitry determines the type of reset that has occurred, performs basic
system configuration, then passes control to the CPU12. The CPU fetches a vector
determined by the type of reset that has occurred, jumps to the address pointed to by
the vector, and begins to execute code at that address.
MOTOROLA
7-2
EXCEPTION PROCESSING
CPU12
REFERENCE MANUAL
There are four possible sources of reset. Power-on reset (POR) and external reset
share the same reset vector. The computer operating properly (COP) reset and the
clock monitor reset each have a vector.
7.3.1 Power-On Reset
The M68HC12 device integration module incorporates circuitry to detect a positive
transition in the VDD supply and initialize the device during cold starts, generally by
asserting the reset signal internally. The signal is typically released after a delay that
allows the device clock generator to stabilize.
7.3.2 External Reset
The MCU distinguishes between internal and external resets by sensing how quickly
the signal on the RESET pin rises to logic level one after it has been asserted. When
the MCU senses any of the four reset conditions, internal circuitry drives the RESET
signal low for 16 clock cycles, then releases. Eight clock cycles later, the MCU samples the state of the signal applied to the RESET pin. If the signal is still low, an external reset has occurred. If the signal is high, reset has been initiated internally by either
the COP system or the clock monitor.
7.3.3 COP Reset
The MCU includes a computer operating properly (COP) system to help protect
against software failures. When the COP is enabled, software must write a particular
code sequence to a specific address in order to keep a watchdog timer from timing out.
If software fails to execute the sequence properly, a reset occurs.
7.3.4 Clock Monitor Reset
The clock monitor circuit uses an internal RC circuit to determine whether clock frequency is above a predetermined limit. If clock frequency falls below the limit when the
clock monitor is enabled, a reset occurs.
7.4 Interrupts
Each M68HC12 device can recognize a number of interrupt sources. Each source has
a vector in the vector table. The XIRQ signal, the unimplemented opcode trap, and the
SWI instruction are non-maskable, and have a fixed priority. The remaining interrupt
sources can be masked by the I bit. In most M68HC12 devices, the external interrupt
request pin is assigned the highest maskable interrupt priority, and the internal periodic real-time interrupt generator has the next highest priority. Other maskable interrupts
are associated with on-chip peripherals such as timers or serial ports. These maskable
sources have default priorities that follow the address order of the interrupt vectors.
The higher the vector address, the higher the priority of the interrupt. Typically, a device integration module incorporates logic that can give one maskable source priority
over other maskable sources.
CPU12
REFERENCE MANUAL
EXCEPTION PROCESSING
MOTOROLA
7-3
7.4.1 Non-Maskable Interrupt Request (XIRQ)
The XIRQ input is an updated version of the NMI input of earlier MCUs. The XIRQ
function is disabled during system reset and upon entering the interrupt service routine
for an XIRQ interrupt.
During reset, both the I bit and the X bit in the CCR are set. This disables maskable
interrupts and interrupt service requests made by asserting the XIRQ signal. After minimum system initialization, software can clear the X bit using an instruction such as
ANDCC #$BF. Software cannot reset the X bit from zero to one once it has been
cleared, and interrupt requests made via the XIRQ pin become non-maskable. When
a non-maskable interrupt is recognized, both the X and I bits are set after context is
saved. The X bit is not affected by maskable interrupts. Execution of an RTI at the end
of the interrupt service routine normally restores the X and I bits to the pre-interrupt
request state.
7.4.2 Maskable Interrupts
Maskable interrupt sources include on-chip peripheral systems and external interrupt
service requests. Interrupts from these sources are recognized when the global interrupt mask bit (I) in the CCR is cleared. The default state of the I bit out of reset is one,
but it can be written at any time.
The integration module manages maskable interrupt priorities. Typically, an on-chip
interrupt source is subject to masking by associated bits in control registers in addition
to global masking by the I bit in the CCR. Sources generally must be enabled by writing
one or more bits in associated control registers. There may be other interrupt-related
control bits and flags, and there may be specific register read-write sequences associated with interrupt service. Refer to individual on-chip peripheral descriptions for details.
7.4.3 Interrupt Recognition
Once enabled, an interrupt request can be recognized at any time after the I mask bit
is cleared. When an interrupt service request is recognized, the CPU responds at the
completion of the instruction being executed. Interrupt latency varies according to the
number of cycles required to complete the current instruction. Because the REV,
REVW and WAV instructions can take many cycles to complete, they are designed so
that they can be interrupted. Instruction execution resumes when interrupt execution
is complete. When the CPU begins to service an interrupt, the instruction queue is refilled, a return address is calculated, and then the return address and the contents of
the CPU registers are stacked as shown in Table 7-2.
After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt service request
caused the interrupt) is set to prevent other interrupts from disrupting the interrupt service routine. Execution continues at the address pointed to by the vector for the highest-priority interrupt that was pending at the beginning of the interrupt sequence. At
the end of the interrupt service routine, an RTI instruction restores context from the
stacked registers, and normal program execution resumes.
MOTOROLA
7-4
EXCEPTION PROCESSING
CPU12
REFERENCE MANUAL
Table 7-2 Stacking Order on Entry to Interrupts
Memory Location
CPU Registers
SP
RTNH : RTNL
SP +2
YH : YL
SP +4
XH : XL
SP +6
B:A
SP +8
CCR
7.4.4 External Interrupts
External interrupt service requests are made by asserting an active-low signal connected to the IRQ pin. Typically, control bits in the device integration module affect
how the signal is detected and recognized.
The I bit serves as the IRQ interrupt enable flag. When an IRQ interrupt is recognized,
the I bit is set to inhibit interrupts during the interrupt service routine. Before other
maskable interrupt requests can be recognized, the I bit must be cleared. This is generally done by an RTI instruction at the end of the service routine.
7.4.5 Return from Interrupt Instruction (RTI)
RTI is used to terminate interrupt service routines. RTI is an 8-cycle instruction when
no other interrupt is pending, and a 10-cycle instruction when another interrupt is
pending. In either case, the first five cycles are used to restore (pull) the CCR, B:A, X,
Y, and the return address from the stack. If no other interrupt is pending at this point,
three program words are fetched to refill the instruction queue from the area of the return address and processing proceeds from there.
If another interrupt is pending after registers are restored, a new vector is fetched, and
the stack pointer is adjusted to point at the CCR value that was just recovered (SP =
SP – 9). This makes it appear that the registers have been stacked again. After the SP
is adjusted, three program words are fetched to refill the instruction queue, starting at
the address the vector points to. Processing then continues with execution of the instruction that is now at the head of the queue.
7.5 Unimplemented Opcode Trap
The CPU12 has opcodes in all 256 positions in the page 1 opcode map, but only 54
of the 256 positions on page 2 of the opcode map are used. If the CPU attempts to
execute one of the 202 unused opcodes on page 2, an unimplemented opcode trap
occurs. The 202 unimplemented opcodes are essentially interrupts that share a common interrupt vector, $FFF8:$FFF9.
The CPU12 uses the next address after an unimplemented page 2 opcode as a return
address. This differs from the M68HC11 illegal opcode interrupt, which uses the address of an illegal opcode as the return address. In the CPU12, the stacked return address can be used to calculate the address of the unimplemented opcode for softwarecontrolled traps.
CPU12
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EXCEPTION PROCESSING
MOTOROLA
7-5
7.6 Software Interrupt Instruction
Execution of the SWI instruction causes an interrupt without an interrupt service request. SWI is not inhibited by the global mask bits in the CCR, and execution of SWI
sets the I mask bit. Once an SWI interrupt begins, maskable interrupts are inhibited
until the I bit in the CCR is cleared. This typically occurs when an RTI instruction at the
end of the SWI service routine restores context.
7.7 Exception Processing Flow
The first cycle in the exception processing flow for all CPU12 exceptions is the same,
regardless of the source of the exception. Between the first and second cycles of execution, the CPU chooses one of three alternative paths. The first path is for resets,
the second path is for pending X or I interrupts, and the third path is used for software
interrupts (SWI) and trapping unimplemented opcodes. The last two paths are virtually
identical, differing only in the details of calculating the return address. Refer to Figure
7-2 for the following discussion.
7.7.1 Vector Fetch
The first cycle of all exception processing, regardless of the cause, is a vector fetch.
The vector points to the address where exception processing will continue. Exception
vectors are stored in a table located at the top of the memory map ($FFC0–$FFFF).
The CPU cannot use the fetched vector until the third cycle of the exception processing sequence.
During the vector fetch cycle, the CPU issues a signal that tells the integration module
to drive the vector address of the highest priority, pending exception onto the system
address bus (the CPU does not provide this address).
After the vector fetch, the CPU selects one of the three alternate execution paths, depending upon the cause of the exception.
7.7.2 Reset Exception Processing
If reset caused the exception, processing continues to cycle 2.0. This cycle sets the X
and I bits in the CCR. The stack pointer is also decremented by two, but this is an artifact of shared code used for interrupt processing; the SP is not intended to have any
specific value after a reset. Cycles 3.0 through 5.0 are program word fetches that refill
the instruction queue. Fetches start at the address pointed to by the reset vector.
When the fetches are completed, exception processing ends, and the CPU starts executing the instruction at the head of the instruction queue.
MOTOROLA
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EXCEPTION PROCESSING
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REFERENCE MANUAL
START
Opcode trap?
No
1.0 - V
Yes
Yes
Fetch vector
T.1 - f
Internal calculations
2.2 - S
Push return address
Reset?
No
Interrupt?
No
Yes
2.0 - f
No bus access
2.1 - S
Push return address
Set X and I; SP–2 ⇒SP
Address of inst that would have
executed if no interrupt
Address of inst after SWI or
unimplemented opcode
3.0 - P
3.1 - P
3.2 - P
Fetch program word
Fetch program word
Fetch program word
Start to fill instruction queue
Start to fill instruction queue
Start to fill instruction queue
4.0 - P
4.1 - S
Push Y
4.2 - S
Push Y
5.1 - S
Push X
5.2 - S
Push X
6.1 - P
Fetch program word
6.2 - P
Fetch program word
Fetch program word
Continue to fill instruction queue
5.0 - P
Fetch program word
Finish filling instruction queue
END
Continue to fill instruction queue
Transfer B:A to 16-bit temp reg
Continue to fill instruction queue
Transfer B:A to 16-bit temp reg
7.1 - S
Push B:A
7.2 - S
8.1 - s
Push CCR (byte)
8.2 - s Push CCR (byte)
Set I bit
Set I bit
If XIRQ, set X bit
9.2 - P
9.1 - P
Fetch program word
Push B:A
Fetch program word
Finish filling instruction queue
Finish filling instruction queue
END
END
CPU12EXPFLOW
Figure 7-2 Exception Processing Flow Diagram
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EXCEPTION PROCESSING
MOTOROLA
7-7
7.7.3 Interrupt and Unimplemented Opcode Trap Exception Processing
If an exception was not caused by a reset, a return address is calculated.
Cycles 2.1and 2.2 are both S cycles (a 16-bit word), but the cycles are not identical
because the CPU12 performs different return address calculations for each type of exception.
When an X- or I-related interrupt causes the exception, the return address points
to the next instruction that would have been executed had processing not been interrupted.
When an exception is caused by an SWI opcode or by an unimplemented opcode
(see 7.5 Unimplemented Opcode Trap), the return address points to the next address after the opcode.
Once calculated, the return address is pushed onto the stack.
Cycles 3.1 through 9.1 are identical to cycles 3.2 through 9.2 for the rest of the sequence, except for X mask bit manipulation performed in cycle 8.1.
Cycle 3.1/3.2 is the first of three program word fetches that refill the instruction queue.
Cycle 4.1/4.2 pushes Y onto the stack.
Cycle 5.1/5.2 pushes X onto the stack.
Cycle 6.1/6.2 is the second of three program word fetches that refill the instruction
queue. During this cycle, the contents of the A and B accumulators are concatenated
into a 16-bit word in the order B:A. This makes register order in the stack frame the
same as that of the M68HC11, M6801, and the M6800.
Cycle 7.1/7.2 pushes the 16-bit word containing B:A onto the stack.
Cycle 8.1/8.2 pushes the 8-bit CCR onto the stack, then updates the mask bits.
When an XIRQ interrupt causes an exception, both X and I are set, which inhibits
further interrupts during exception processing.
When any other interrupt causes an exception, the I bit is set, but the X bit is not
changed.
Cycle 9.1/9.2 is the third of three program word fetches that refill the instruction queue.
It is the last cycle of exception processing. After this cycle the CPU starts executing
the first cycle of the instruction at the head of the instruction queue.
MOTOROLA
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EXCEPTION PROCESSING
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REFERENCE MANUAL
SECTION 8
DEVELOPMENT AND DEBUG SUPPORT
This section is an explanation of CPU-related aspects of the background debugging
system. Topics include the instruction queue status signals, instruction tagging, and
the single-wire background debug interface.
8.1 External Reconstruction of the Queue
The CPU12 uses an instruction queue to buffer program information and increase instruction throughput. The queue consists of two 16-bit stages, plus a 16-bit holding
latch. Program information is always fetched in aligned 16-bit words. At least three
bytes of program information are available to the CPU when instruction execution begins. The holding latch is used when a word of program information arrives before the
queue can advance.
Because of the queue, program information is fetched a few cycles before it is used
by the CPU. Internally, the MCU only needs to buffer the fetched data. But, in order to
monitor cycle-by-cycle CPU activity, it is necessary to externally reconstruct what is
happening in the instruction queue.
Two external pins, IPIPE[1:0], provide time-multiplexed information about data movement in the queue and instruction execution. To complete the picture for system debugging, it is also necessary to include program information and associated addresses
in the reconstructed queue.
The instruction queue and cycle-by-cycle activity can be reconstructed in real time or
from trace history captured by a logic analyzer. However, neither scheme can be used
to stop the CPU12 at a specific instruction. By the time an operation is visible outside
the MCU, the instruction has already begun execution. A separate instruction tagging
mechanism is provided for this purpose. A tag follows the information in the queue as
the queue is advanced. During debugging, the CPU enters active background debug
mode when a tagged instruction reaches the head of the queue, rather than executing
the tagged instruction. For more information about tagging, refer to 8.5 Instruction
Tagging.
8.2 Instruction Queue Status Signals
The IPIPE[1:0] signals carry time-multiplexed information about data movement and
instruction execution during normal CPU operation. The signals are available on two
multifunctional device pins. During reset, the pins are used as mode-select input signals MODA and MODB. After reset, information on the pins does not become valid until an instruction reaches queue stage 2.
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8-1
To reconstruct the queue, the information carried by the status signals must be captured externally. In general, data movement and execution start information are considered to be distinct 2-bit values, with the low-order bit on IPIPE0 and the high-order
bit on IPIPE1. Data movement information is available on rising edges of the E clock;
execution start information is available on falling edges of the E clock, as shown in Figure 8-1. Data movement information refers to data on the bus at the previous falling
edge of E. Execution information refers to the bus cycle from the current falling edge
to the next falling edge of E. Table 8-1 summarizes the information encoded on the
IPIPE[1:0] pins.
EX1 REFERS TO THIS CYCLE
ECLK
ADDR
DATA
IPIPE[1:0]
EX1
DM0
EX2
DM1
EX3
DM0 REFERS TO DATA CAPTURED
ON THIS ECLK TRANSITION
QUE STATUS TIM
Figure 8-1 Queue Status Signal Timing
Table 8-1 IPIPE[1:0] Decoding
Data Movement
(capture at E rise)
Mnemonic
Meaning
0:0
—
No movement
0:1
LAT
Latch data from bus
1:0
ALD
Advance queue and load from bus
1:1
ALL
Advance queue and load from latch
Execution Start
(capture at E fall)
Mnemonic
Meaning
0:0
—
No start
0:1
INT
Start interrupt sequence
1:0
SEV
Start even instruction
1:1
SOD
Start odd instruction
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8.2.1 Zero Encoding (0:0)
The 0:0 state at the rising edge of E indicates that there was no data movement in the
instruction queue during the previous cycle; the 0:0 state at the falling edge of E indicates continuation of an instruction or interrupt sequence.
8.2.2 LAT — Latch Data from Bus Encoding (0:1)
Fetched program information has arrived, but the queue is not ready to advance. The
information is latched into the buffer. Later, when the queue does advance, stage 1 is
refilled from the buffer, or from the data bus if the buffer is empty. In some instruction
sequences, there can be several latch cycles before the queue advances. In these
cases, the buffer is filled on the first latch event and additional latch requests are ignored.
8.2.3 ALD — Advance and Load from Data Bus Encoding (1:0)
The two-stage instruction queue is advanced by one word and stage 1 is refilled with
a word of program information from the data bus. The CPU requested the information
two bus cycles earlier but, due to access delays, the information was not available until
the E cycle immediately prior to the ALD.
8.2.4 ALL — Advance and Load from Latch Encoding (1:1)
The two-stage instruction queue is advanced by one word and stage 1 is refilled with
a word of program information from the buffer. The information was latched from the
data bus at the falling edge of a previous E cycle because the instruction queue was
not ready to advance when it arrived.
8.2.5 INT — Interrupt Sequence Encoding (0:1)
The E cycle starting at this E fall is the first cycle of an interrupt sequence. Normally
this cycle is a read of the interrupt vector. However, in systems that have interrupt vectors in external memory and an 8-bit data bus, this cycle reads only the upper byte of
the 16-bit interrupt vector.
8.2.6 SEV — Start Instruction on Even Address Encoding (1:0)
The E cycle starting at this E fall is the first cycle of the instruction in the even (high
order) half of the word at the head of the instruction queue. The queue treats the $18
prebyte for instructions on page 2 of the opcode map as a special 1-byte, 1-cycle instruction, except that interrupts are not recognized at the boundary between the prebyte and the rest of the instruction.
8.2.7 SOD — Start Instruction on Odd Address Encoding (1:1)
The E cycle starting at this E fall is the first cycle of the instruction in the odd (low order)
half of the word at the head of the instruction queue. The queue treats the $18 prebyte
for instructions on page 2 of the opcode map as a special 1-byte, 1-cycle instruction,
except that interrupts are not recognized at the boundary between the prebyte and the
rest of the instruction.
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DEVELOPMENT AND DEBUG SUPPORT
MOTOROLA
8-3
8.3 Implementing Queue Reconstruction
The raw signals required for queue reconstruction are the address bus (ADDR), the
data bus (DATA), the read/write strobe (R/W), the system clock (E), and the queue status signals (IPIPE[1:0]). An E clock cycle begins after an E fall. Addresses, R/W state,
and data movement status must be captured at the E rise in the middle of the cycle.
Data and execution start status must be captured at the E fall at the end of the cycle.
These captures can then be organized into records with one record per E clock cycle.
Implementation details depend upon the type of device and the mode of operation. For
instance, the data bus can be eight bits or 16 bits wide, and non-multiplexed or multiplexed. In all cases, the externally reconstructed queue must use 16-bit words. Demultiplexing and assembly of 8-bit data into 16-bit words is done before program
information enters the real queue, so it must also be done for the external reconstruction. An example:
Systems with an 8-bit data bus and a program stored in external memory require
two cycles for each program word fetch. MCU bus control logic freezes the CPU
clocks long enough to do two 8-bit accesses rather than a single 16-bit access, so
the CPU sees only 16-bit words of program information. To recover the 16-bit program words externally, latch the data bus state at the falling edge of E when
ADDR0 = 0, and gate the outputs of the latch onto DATA[15:8] when a LAT or ALD
cycle occurs. Since the 8-bit data bus is connected to DATA[7:0], the 16-bit word
on the data lines corresponds to the ALD or LAT status indication at the E rise after
the second 8-bit fetch, which is always to an odd address. IPIPE[1:0] status signals
indicate 0:0 at the beginning (E fall) and middle (E rise) of the first 8-bit fetch.
Some M68HC12 devices have address lines to support memory expansion beyond
the standard 64-Kbyte address space. When memory expansion is used, expanded
addresses must also be captured and maintained.
8.3.1 Queue Status Registers
Queue reconstruction requires the following registers, which can be implemented as
software variables when previously captured trace data is used, or as hardware latches in real time.
8.3.1.1 in_add, in_dat Registers
These registers contain the address and data from the previous external bus cycle.
Depending upon how records are read and processed from the raw capture information, it may be possible to simply read this information from the raw capture data file
when needed.
8.3.1.2 fetch_add, fetch_dat Registers
These registers buffer address and data for information that was fetched before the
queue was ready to advance.
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8.3.1.3 st1_add, st1_dat Registers
These registers contain address and data for the first stage of the reconstructed instruction queue.
8.3.1.4 st2_add, st2_dat Registers
These registers contain address and data for the final stage of the reconstructed instruction queue. When the IPIPE[1:0] signals indicate that an instruction is starting to
execute, the address and opcode can be found in these registers.
8.3.2 Reconstruction Algorithm
This section describes in detail how to use IPIPE[1:0] signals and status storage registers to perform queue reconstruction. An “is_full” flag is used to indicate when the
fetch_add and fetch_dat buffer registers contain information. The use of the flag is explained more fully in subsequent paragraphs.
Typically, the first few cycles of raw capture data are not useful because it takes several cycles before an instruction propagates to the head of the queue. During these
first raw cycles, the only meaningful information available are data movement signals.
Information on the external address and data buses during this setup time reflects the
actions of instructions that were fetched before data collection started.
In the special case of a reset, there is a five cycle sequence (VfPPP) during which the
reset vector is fetched and the instruction queue is filled, before execution of the first
instruction begins. Due to the timing of the switchover of the IPIPE[1:0] pins from their
alternate function as mode select inputs, the status information on these two pins may
be erroneous during the first cycle or two after the release of reset. This is not a problem because the status is correct in time for queue reconstruction logic to correctly replicate the queue.
Before starting to reconstruct the queue, clear the is_full flag to indicate that there is
no meaningful information in the fetch_add and fetch_dat buffers. Further movement
of information in the instruction queue is based on the decoded status on the
IPIPE[1:0] signals at the rising edges of E.
8.3.2.1 LAT Decoding
On a latch cycle, check the is_full flag. If and only if is_full = 0, transfer the address
and data from the previous bus cycle (in_add and in_dat) into the fetch_add and
fetch_dat registers respectively. Then, set the is_full flag. The usual reason for a latch
request instead of an advance request is that the previous instruction ended with a single aligned byte of program information in the last stage of the instruction queue. Since
the odd half of this word still holds the opcode for the next instruction, the queue cannot advance on this cycle. However, the cycle to fetch the next word of program information has already started and the data is on its way.
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DEVELOPMENT AND DEBUG SUPPORT
MOTOROLA
8-5
8.3.2.2 ALD Decoding
On an advance-and-load-from-data-bus cycle, the information in the instruction queue
must advance by one stage. Whatever was in stage 2 of the queue is simply thrown
away. The previous contents of stage 1 are moved to stage 2, and the address and
data from the previous cycle (in_add and in_dat) are transferred into stage 1 of the instruction queue. Finally, clear the is_full flag to indicate the buffer latch is ready for new
data. Usually, there would be no useful information in the fetch buffer when an ALD
cycle was encountered, but in the case of a change-of-flow, any data that was there
needs to be flushed out (by clearing the is_full flag).
8.3.2.3 ALL Decoding
On an advance-and-load-from-latch cycle, the information in the instruction queue
must advance by one stage. Whatever was in stage 2 of the queue is simply thrown
away. The previous contents of stage 1 are moved to stage 2, and the contents of the
fetch buffer latch are transferred into stage 1 of the instruction queue. One or more cycles preceding the ALL cycle will have been a LAT cycle. After updating the instruction
queue, clear the is_full flag to indicate the fetch buffer is ready for new information.
8.4 Background Debug Mode
M68HC12 MCUs include a resident debugging system. This system is implemented
with on-chip hardware rather than external software, and provides a full set of debugging options. The debugging system is less intrusive than systems used on other microcontrollers, because the control logic resides in the on-chip integration module,
rather than in the CPU. Some activities, such as reading and writing memory locations,
can be performed while the CPU is executing normal code with no effect on real-time
system activity.
The integration module generally uses CPU dead cycles to execute debugging commands while the CPU is operating normally, but can steal cycles from the CPU when
necessary. Other commands are firmware based, and require that the CPU be in active background debug mode (BDM) for execution. While BDM is active, the CPU executes a monitor program located in a small on-chip ROM.
Debugging control logic communicates with external devices serially, via the BKGD
pin. This single-wire approach helps to minimize the number of pins needed for development support.
Background debug does not operate in STOP mode.
8.4.1 Enabling BDM
The debugger must be enabled before it can be activated. Enabling has two phases.
First, the BDM ROM must be enabled by writing the ENBDM bit in the BDM status register, using a debugging command sent via the single wire interface. Once the ROM
is enabled, it remains available until the next system reset, or until ENBDM is cleared
by another debugging command. Second, BDM must be activated to map the ROM
and BDM control registers to addresses $FF00 to $FFFF and put the MCU in background mode.
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After the firmware is enabled, BDM can be activated by the hardware BACKGROUND
command, by breakpoints tagged via the LIM breakpoint logic or the BDM tagging
mechanism, and by the BGND instruction. An attempt to activate BDM before firmware
has been enabled causes the MCU to resume normal instruction execution after a
brief delay.
BDM becomes active at the next instruction boundary following execution of the BDM
BACKGROUND command. Breakpoints can be configured to activate BDM before a
tagged instruction is executed.
While BDM is active, BDM control registers are mapped to addresses $FF00 to $FF06.
These registers are only accessible through BDM firmware or BDM hardware commands. 8.4.4 BDM Registers describes the registers.
Some M68HC12 on-chip peripherals have a BDM control bit, which determines whether the peripheral function is available during BDM. If no bit is shown, the peripheral is
active in BDM.
8.4.2 BDM Serial Interface
The BDM serial interface uses a clocking scheme in which the external host generates
a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge
must be sent for every bit, whether data is transmitted or received.
BKGD is an open drain pin that can be driven either by the MCU or by an external host.
Data is transferred MSB first, at 16 E-clock cycles per bit. The interface times out if 512
E-clock cycles occur between falling edges from the host. The hardware clears the
command register when a time-out occurs.
The BKGD pin is used to send and receive data. The following diagrams show timing
for each of these cases. Interface timing is synchronous to MCU clocks, but the external host is asynchronous to the target MCU. The internal clock signal is shown for reference in counting cycles.
Figure 8-2 shows an external host transmitting a data bit to the BKGD pin of a target
M68HC12 MCU. The host is asynchronous to the target, so there is a 0- to 1-cycle delay from the host-generated falling edge to the time when the target perceives the bit.
Ten target E-cycles later, the target senses the bit level on the BKGD pin. The host
can drive high during host-to-target transmission to speed up rising edges, because
the target does not drive the pin during this time.
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DEVELOPMENT AND DEBUG SUPPORT
MOTOROLA
8-7
ECLOCK
(TARGET
MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED START
OF BIT TIME
TARGET SENSES BIT
10 CYCLES
EARLIEST
START OF
NEXT BIT
SYNCHRONIZATION
UNCERTAINTY
CPU12 BDM HT TIM
Figure 8-2 BDM Host to Target Serial Bit Timing
Figure 8-3 shows an external host receiving a logic one from the target MCU. Since
the host is asynchronous to the target, there is a 0- or 1-cycle delay from the host-generated falling edge on BKGD until the target perceives the bit. The host holds the signal low long enough for the target to recognize it (a minimum of two target E-clock
cycles), but must release the low drive before the target begins to drive the active-high
speed-up pulse seven cycles after the start of the bit time. The host should sample the
bit level about ten cycles after the start of bit time.
ECLOCK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
TARGET MCU
SPEEDUP
PULSE
PERCEIVED
START OF BIT TIME
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
R-C RISE
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST
START OF
NEXT BIT
HOST SAMPLES
BKGD PIN
CPU12 BDM TH TIM 1
Figure 8-3 BDM Target to Host Serial Bit Timing (Logic 1)
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Figure 8-4 shows the host receiving a logic zero from the target. Since the host is
asynchronous to the target, there is a 0- or 1-cycle delay from the host-generated falling edge on BKGD until the target perceives the bit. The host initiates the bit time, but
the target finishes it. To make certain the host receives a logic zero, the target drives
the BKGD pin low for 13 E-clock cycles, then briefly drives the signal high to speed up
the rising edge. The host samples the bit level about ten cycles after starting the bit
time.
ECLOCK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
HIGH-IMPEDANCE
SPEEDUP PULSE
TARGET MCU
DRIVE AND
SPEEDUP PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
EARLIEST
START OF
NEXT BIT
CPU12 BDM TH0TIM
Figure 8-4 BDM Target to Host Serial Bit Timing (Logic 0)
8.4.3 BDM Commands
All BDM opcodes are eight bits long, and can be followed by an address or data, as
indicated by the instruction.
Commands implemented in BDM control hardware are listed in Table 8-2. These commands, except for BACKGROUND, do not require the CPU to be in BDM mode for execution. The control logic uses CPU dead cycles to execute these instructions. If a
dead cycle cannot be found within 128 cycles, the control logic steals cycles from the
CPU.
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MOTOROLA
8-9
Table 8-2 BDM Commands Implemented in Hardware
Command
Opcode (Hex)
Data
Description
BACKGROUND
90
None
READ_BD_BYTE
E4
16-bit address
16-bit data out
Read from memory with BDM in map (may steal cycles
if external access) data for odd address on low byte,
data for even address on high byte.
STATUS1
E4
FF01,
0000 0000 (out)
READ_BD_BYTE $FF01. Running user code (BGND
instruction is not allowed).
FF01,
1000 0000 (out)
READ_BD_BYTE $FF01. BGND instruction is allowed.
FF01,
1100 0000 (out)
READ_BD_BYTE $FF01. Background mode active
(waiting for single wire serial command).
Enter background mode (if firmware enabled).
READ_BD_WORD
EC
16-bit address
16-bit data out
Read from memory with BDM in map (may steal cycles
if external access) must be aligned access.
READ_BYTE
E0
16-bit address
16-bit data out
Read from memory with BDM out of map (may steal cycles if external access) data for odd address on low
byte, data for even address on high byte.
READ_WORD
E8
16-bit address
16-bit data out
Read from memory with BDM out of map (may steal cycles if external access) must be aligned access.
WRITE_BD_BYTE
C4
16-bit address
16-bit data in
Write to memory with BDM in map (may steal cycles if
external access) data for odd address on low byte, data
for even address on high byte.
ENABLE_ FIRMWARE2
C4
FF01,
1xxx xxxx(in)
Write byte $FF01, set the ENBDM bit. This allows execution of commands which are implemented in firmware. Typically, read STATUS, OR in the MSB, write
the result back to STATUS.
WRITE_BD_WORD
CC
16-bit address
16-bit data in
Write to memory with BDM in map (may steal cycles if
external access) must be aligned access.
WRITE_BYTE
C0
16-bit address
16-bit data in
Write to memory with BDM out of map (may steal cycles
if external access) data for odd address on low byte,
data for even address on high byte.
WRITE_WORD
C8
16-bit address
16-bit data in
Write to memory with BDM out of map (may steal cycles
if external access) must be aligned access.
NOTES:
1. STATUS command is a specific case of the READ_BD_BYTE command.
2. ENABLE_FIRMWARE is a specific case of the WRITE_BD_BYTE command.
The CPU must be in background mode to execute commands that are implemented
in the BDM ROM. The CPU executes code from the ROM to perform the requested
operation. These commands are shown in Table 8-3.
The host controller must wait 150 cycles for a non-intrusive BDM command to execute
before another command can be sent. This delay includes 128 cycles for the maximum delay for a dead cycle.
BDM logic retains control of the internal buses until a read or write is completed. If an
operation can be completed in a single cycle, it does not intrude on normal CPU operation. However, if an operation requires multiple cycles, CPU clocks are frozen until
the operation is complete.
MOTOROLA
8-10
DEVELOPMENT AND DEBUG SUPPORT
CPU12
REFERENCE MANUAL
Table 8-3 BDM Firmware Commands
Command
Opcode (Hex)
Data
GO
08
none
Description
Resume normal processing
TRACE1
10
none
Execute one user instruction then return to BDM
TAGGO
18
none
Enable tagging then resume normal processing
WRITE_NEXT
42
16-bit data in
X = X + 2; Write next word @ 0,X
WRITE_PC
43
16-bit data in
Write program counter
WRITE_D
44
16-bit data in
Write D accumulator
WRITE_X
45
16-bit data in
Write X index register
WRITE_Y
46
16-bit data in
Write Y index register
WRITE_SP
47
16-bit data in
Write stack pointer
READ_NEXT
62
16-bit data out
X = X + 2; Read next word @ 0,X
READ_PC
63
16-bit data out
Read program counter
READ_D
64
16-bit data out
Read D accumulator
READ_X
65
16-bit data out
Read X index register
READ_Y
66
16-bit data out
Read Y index register
READ_SP
67
16-bit data out
Read stack pointer
8.4.4 BDM Registers
Seven BDM registers are mapped into the standard 64-Kbyte address space when
BDM is active. Mapping is shown in Table 8-4.
Table 8-4 BDM Register Mapping
Address
Register
$FF00
BDM instruction register
$FF01
BDM status register
$FF02–$FF03
BDM shift register
$FF04–$FF05
BDM address register
$FF06
BDM CCR register
The content of the instruction register is determined by the type of background instruction being executed. The status register indicates BDM operating conditions. The shift
register contains data being received or transmitted via the serial interface. The address register is temporary storage for BDM commands. The CCR register preserves
the content of the CPU12 CCR while BDM is active.
The only register of interest to users is the status register. The other BDM registers are
used only by the BDM firmware to execute commands. The registers can be accessed
by means of the hardware READ_BD and WRITE_BD commands, but must not be
written during BDM operation.
CPU12
REFERENCE MANUAL
DEVELOPMENT AND DEBUG SUPPORT
MOTOROLA
8-11
8.4.4.1 BDM Status Register
STATUS — BDM Status Register
$FF01
BIT 7
6
5
4
3
2
1
BIT 0
ENBDM
BDMACT
ENTAG
SDV
TRACE
0
0
0
RESET:
0
0
0
0
0
0
0
0
SP.
S. CHIP &
PERIPH.:
1
0
0
0
0
0
0
0
ENBDM — Enable BDM ROM
Shows whether the BDM ROM is enabled. Cleared by reset.
0 = BDM ROM not enabled
1 = BDM ROM enabled, but not in memory map unless BDM is active
BDMACT — BDM Active Flag
Shows whether the BDM ROM is in the memory map. Cleared by reset.
0 = ROM not in map
1 = ROM in map (MCU is in active BDM)
ENTAG — Instruction Tagging Enable
Shows whether instruction tagging is enabled. Set by the TAGGO instruction and
cleared when BDM is entered. Cleared by reset.
NOTE
Execute a TAGGO command to enable instruction tagging. Do not
write ENTAG directly.
0 = Tagging not enabled, or BDM active
1 = Tagging active
SDV — Shifter Data Valid
Shows that valid data is in the serial interface shift register.
NOTE
SDV is used by firmware-based instructions. Do not attempt to write
SDV directly.
0 = No valid data
1 = Valid Data
TRACE — Trace Flag
Shows when tracing is enabled.
NOTE
Execute a TRACE1 command to enable instruction tagging. Do not
attempt to write TRACE directly.
0 = Tracing not enabled
1 = Tracing active
MOTOROLA
8-12
DEVELOPMENT AND DEBUG SUPPORT
CPU12
REFERENCE MANUAL
8.5 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be reconstructed in real
time, or from trace history that was captured by a logic analyzer. However, the reconstructed queue cannot be used to stop the CPU at a specific instruction, because execution has already begun by the time an operation is visible outside the MCU. A
separate instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for tagging. The
TAGLO signal shares a pin with the LSTRB signal, and the TAGHI signal shares a pin
with the BKGD pin. Tagging information is latched on the falling edge of ECLK, as
shown in Figure 8-5.
TAGS ARE APPLIED TO PROGRAM INFORMATION
CAPTURED ON THIS ECLK TRANSITION
ECLK
LSTRB
VALID
LSTRB/TAGLO
TAGLO
VALID
TAGHI
VALID
BKGD/TAGHI
CPU12 TAG TIM
Figure 8-5 Tag Input Timing
Table 8-5 shows the functions of the two tagging pins. The pins operate independently; the state of one pin does not affect the function of the other. The presence of logic
level zero on either pin at the fall of ECLK performs the indicated function. Tagging is
allowed in all modes. Tagging is disabled when BDM becomes active.
Table 8-5 Tag Pin Function
CPU12
REFERENCE MANUAL
TAGHI
TAGLO
Tag
1
1
No Tag
1
0
Low Byte
0
1
High Byte
0
0
Both Bytes
DEVELOPMENT AND DEBUG SUPPORT
MOTOROLA
8-13
In M68HC12 derivatives that have hardware breakpoint capability, the breakpoint control logic and BDM control logic use the same internal signals for instruction tagging.
The CPU12 does not differentiate between the two kinds of tags.
The tag follows program information as it advances through the queue. When a tagged
instruction reaches the head of the queue, the CPU enters active background debug
mode rather than executing the instruction.
8.6 Breakpoints
Breakpoints halt instruction execution at particular places in a program. To assure
transparent operation, breakpoint control logic is implemented outside the CPU, and
particular models of MCU can have different breakpoint capabilities. Refer to the appropriate device manual for detailed information. Generally, breakpoint logic can be
configured to halt execution before an instruction executes, or to halt execution on the
next instruction boundary following the breakpoint.
8.6.1 Breakpoint Type
There are three basic types of breakpoints:
1. Address-only breakpoints that cause the CPU to execute an SWI. These breakpoints can be set only on addresses. When the breakpoint logic encounters the
breakpoint tag, the CPU12 executes an SWI instruction.
2. Address-only breakpoints that cause the MCU to enter BDM. These breakpoints can be set only on addresses. When the breakpoint logic encounters the
breakpoint tag, BDM is activated.
3. Address/data breakpoints that cause the MCU to enter BDM. These breakpoints can be set on an address, or on an address and data. When the breakpoint logic encounters the breakpoint tag, BDM is activated.
8.6.2 Breakpoint Operation
Breakpoints use two mechanisms to halt execution:
1. The tag mechanism marks a particular program fetch with a high (even) or low
(odd) byte indicator. The tagged byte moves through the instruction queue until
a start cycle occurs, then the breakpoint is taken. Breakpoint logic can be configured to force BDM, or to initiate an SWI when the tag is encountered.
2. The force BDM mechanism causes the MCU to enter active BDM at the next
instruction start cycle.
CPU12 instructions are used to implement both breakpoint mechanisms. When an
SWI tag is encountered, the CPU performs the same sequence of operations as for an
SWI. When BDM is forced, the CPU executes a BGND instruction. However, because
these operations are not part of the normal flow of instruction execution, the control
program must keep track of the actual breakpoint address.
MOTOROLA
8-14
DEVELOPMENT AND DEBUG SUPPORT
CPU12
REFERENCE MANUAL
Both SWI and BGND store a return PC value (SWI on the stack and BGND in the
CPU12 TMP2 register), but this value is automatically incremented to point to the next
instruction after SWI or BGND. In order to resume execution where a breakpoint occurred, the control program must preserve the breakpoint address rather than use the
incremented PC value.
The breakpoint logic generally uses match registers to determine when a break is taken. Registers can be used to match the high and low bytes of addresses for single and
dual breakpoints, to match data for single breakpoints, or to do both functions. Use of
the registers is generally determined by control bit settings.
CPU12
REFERENCE MANUAL
DEVELOPMENT AND DEBUG SUPPORT
MOTOROLA
8-15
MOTOROLA
8-16
DEVELOPMENT AND DEBUG SUPPORT
CPU12
REFERENCE MANUAL
SECTION 9
FUZZY LOGIC SUPPORT
The CPU12 has the first microcontroller instruction set to specifically address the
needs of fuzzy logic. This section describes the use of fuzzy logic in control systems,
discusses the CPU12 fuzzy logic instructions, and provides examples of fuzzy logic
programs.
9.1 Introduction
The CPU12 includes four instructions that perform specific fuzzy logic tasks. In addition, several other instructions are especially useful in fuzzy logic programs. The overall C-friendliness of the instruction set also aids development of efficient fuzzy logic
programs.
This section explains the basic fuzzy logic algorithm for which the four fuzzy logic instructions are intended. Each of the fuzzy logic instructions are then explained in detail. Finally, other custom fuzzy logic algorithms are discussed, with emphasis on use
of other CPU12 instructions.
The four fuzzy logic instructions are MEM, which evaluates trapezoidal membership
functions; REV and REVW, which perform unweighted or weighted MIN-MAX rule
evaluation; and WAV, which performs weighted average defuzzification on singleton
output membership functions.
Other instructions that are useful for custom fuzzy logic programs include MINA,
EMIND, MAXM, EMAXM, TBL, ETBL, and EMACS. For higher resolution fuzzy programs, the fast extended precision math instructions in the CPU12 are also beneficial.
Flexible indexed addressing modes help simplify access to fuzzy logic data structures
stored as lists or tabular data structures in memory.
The actual logic additions required to implement fuzzy logic support in the CPU12 are
quite small, so there is no appreciable increase in cost for the typical user. A fuzzy inference kernel for the CPU12 requires one-fifth as much code space, and executes
fifteen times faster than a comparable kernel implemented on a typical midrange microcontroller. By incorporating fuzzy logic support into a high-volume, general-purpose microcontroller product family, Motorola has made fuzzy logic available for a
huge base of applications.
9.2 Fuzzy Logic Basics
This is an overview of basic fuzzy logic concepts. It can serve as a general introduction
to the subject, but that is not the main purpose. There are a number of fuzzy logic programming strategies. This discussion concentrates on the methods implemented in
the CPU12 fuzzy logic instructions. The primary goal is to provide a background for a
detailed explanation of the CPU12 fuzzy logic instructions.
CPU12
REFERENCE MANUAL
FUZZY LOGIC SUPPORT
MOTOROLA
9-1
In general, fuzzy logic provides for set definitions that have fuzzy boundaries rather
than the crisp boundaries of Aristotelian logic. These sets can overlap so that, for a
specific input value, one or more sets associated with linguistic labels may be true to
a degree at the same time. As the input varies from the range of one set into the range
of an adjacent set, the first set becomes progressively less true while the second set
becomes progressively more true.
Fuzzy logic has membership functions which emulate human concepts like “temperature is warm”; that is, conditions are perceived to have gradual boundaries. This concept seems to be a key element of the human ability to solve certain types of complex
problems that have eluded traditional control methods.
Fuzzy sets provide a means of using linguistic expressions like “temperature is warm”
in rules which can then be evaluated with a high degree of numerical precision and
repeatability. This directly contradicts the common misperception that fuzzy logic produces approximate results — a specific set of input conditions always produces the
same result, just as a conventional control system does.
A microcontroller-based fuzzy logic control system has two parts. The first part is a
fuzzy inference kernel which is executed periodically to determine system outputs
based on current system inputs. The second part of the system is a knowledge base
which contains membership functions and rules. Figure 9-1 is a block diagram of this
kind of fuzzy logic system.
The knowledge base can be developed by an application expert without any microcontroller programming experience. Membership functions are simply expressions of the
expert’s understanding of the linguistic terms that describe the system to be controlled.
Rules are ordinary language statements that describe the actions a human expert
would take to solve the application problem.
Rules and membership functions can be reduced to relatively simple data structures
(the knowledge base) stored in nonvolatile memory. A fuzzy inference kernel can be
written by a programmer who does not know how the application system works. The
only thing the programmer needs to do with knowledge base information is store it in
the memory locations used by the kernel.
One execution pass through the fuzzy inference kernel generates system output signals in response to current input conditions. The kernel is executed as often as needed
to maintain control. If the kernel is executed more often than needed, processor bandwidth and power are wasted; delaying too long between passes can cause the system
to get too far out of control. Choosing a periodic rate for a fuzzy control system is the
same as it would be for a conventional control system.
MOTOROLA
9-2
FUZZY LOGIC SUPPORT
CPU12
REFERENCE MANUAL
KNOWLEDGE
BASE
INPUT
MEMBERSHIP
FUNCTIONS
SYSTEM
INPUTS
FUZZY
INFERENCE
KERNEL
FUZZIFICATION
…
RULE LIST
RULE EVALUATION
…
OUTPUT
MEMBERSHIP
FUNCTIONS
FUZZY INPUTS
(IN RAM)
FUZZY OUTPUTS
(IN RAM)
DEFUZZIFICATION
SYSTEM
OUTPUTS
FUZ LOG BD
Figure 9-1 Block Diagram of a Fuzzy Logic System
9.2.1 Fuzzification (MEM)
During the fuzzification step, the current system input values are compared against
stored input membership functions to determine the degree to which each label of
each system input is true. This is accomplished by finding the y-value for the current
input value on a trapezoidal membership function for each label of each system input.
The MEM instruction in the CPU12 performs this calculation for one label of one system input. To perform the complete fuzzification task for a system, several MEM instructions must be executed, usually in a program loop structure.
Figure 9-2 shows a system of three input membership functions, one for each label of
the system input. The x-axis of all three membership functions represents the range
of possible values of the system input. The vertical line through all three membership
functions represents a specific system input value. The y-axis represents degree of
truth and varies from completely false ($00 or 0%) to completely true ($FF or 100%).
The y-value where the vertical line intersects each of the membership functions, is the
degree to which the current input value matches the associated label for this system
input. For example, the expression “temperature is warm” is 25% true ($40). The value
$40 is stored to a RAM location, and is called a fuzzy input (in this case, the fuzzy input
for “temperature is warm”). There is a RAM location for each fuzzy input (for each label
of each system input).
CPU12
REFERENCE MANUAL
FUZZY LOGIC SUPPORT
MOTOROLA
9-3
MEMBERSHIP FUNCTIONS
FOR TEMPERATURE
$FF
FUZZY INPUTS
HOT
$C0
$80
$40
TEMPERATURE IS HOT
$00
TEMPERATURE IS WARM
$40
TEMPERATURE IS COLD
$C0
$00
0˚F
$FF
32˚F
64˚F
96˚F
128˚F
WARM
$C0
$80
$40
$00
0˚F
$FF
32˚F
64˚F
96˚F
128˚F
COLD
$C0
$80
$40
$00
0˚F
32˚F
64˚F
96˚F
128˚F
CURRENT
TEMPERATURE
IS 64˚F
FUZ MEM FNCT
Figure 9-2 Fuzzification Using Membership Functions
When the fuzzification step begins, the current value of the system input is in an accumulator of the CPU12, one index register points to the first membership function definition in the knowledge base, and a second index register points to the first fuzzy input
in RAM. As each fuzzy input is calculated by executing a MEM instruction, the result
is stored to the fuzzy input and both pointers are updated automatically to point to the
locations associated with the next fuzzy input. The MEM instruction takes care of everything except counting the number of labels per system input and loading the current
value of any subsequent system inputs.
The end result of the fuzzification step is a table of fuzzy inputs representing current
system conditions.
MOTOROLA
9-4
FUZZY LOGIC SUPPORT
CPU12
REFERENCE MANUAL
9.2.2 Rule Evaluation (REV and REVW)
Rule evaluation is the central element of a fuzzy logic inference program. This step
processes a list of rules from the knowledge base using current fuzzy input values from
RAM to produce a list of fuzzy outputs in RAM. These fuzzy outputs can be thought of
as raw suggestions for what the system output should be in response to the current
input conditions. Before the results can be applied, the fuzzy outputs must be further
processed, or defuzzified, to produce a single output value that represents the combined effect of all of the fuzzy outputs.
The CPU12 offers two variations of rule evaluation instructions. The REV instruction
provides for unweighted rules (all rules are considered to be equally important). The
REVW instruction is similar but allows each rule to have a separate weighting factor
which is stored in a separate parallel data structure in the knowledge base. In addition
to the weights, the two rule evaluation instructions also differ in the way rules are encoded into the knowledge base.
An understanding of the structure and syntax of rules is needed to understand how a
microcontroller performs the rule evaluation task. The following is an example of a typical rule.
If temperature is warm and pressure is high then heat is (should be) off.
At first glance, it seems that encoding this rule in a compact form understandable to
the microcontroller would be difficult, but it is actually simple to reduce the rule to a
small list of memory pointers. The left portion of the rule is a statement of input conditions and the right portion of the rule is a statement of output actions.
The left portion of a rule is made up of one or more (in this case two) antecedents connected by a fuzzy and operator. Each antecedent expression consists of the name of
a system input, followed by is, followed by a label name. The label must be defined by
a membership function in the knowledge base. Each antecedent expression corresponds to one of the fuzzy inputs in RAM. Since and is the only operator allowed to
connect antecedent expressions, there is no need to include these in the encoded
rule. The antecedents can be encoded as a simple list of pointers to (or addresses of)
the fuzzy inputs to which they refer.
The right portion of a rule is made up of one or more (in this case one) consequents.
Each consequent expression consists of the name of a system output, followed by is,
followed by a label name. Each consequent expression corresponds to a specific
fuzzy output in RAM. Consequents for a rule can be encoded as a simple list of pointers to (or addresses of) the fuzzy outputs to which they refer.
The complete rules are stored in the knowledge base as a list of pointers or addresses
of fuzzy inputs and fuzzy outputs. In order for the rule evaluation logic to work, there
must be some means of knowing which pointers refer to fuzzy inputs, and which refer
to fuzzy outputs. There also must be a way to know when the last rule in the system
has been reached.
CPU12
REFERENCE MANUAL
FUZZY LOGIC SUPPORT
MOTOROLA
9-5
One method of organization is to have a fixed number of rules with a specific number
of antecedents and consequents. A second method, employed in Motorola Freeware
M68HC11 kernels, is to mark the end of the rule list with a reserved value, and use a
bit in the pointers to distinguish antecedents from consequents. A third method of organization, used in the CPU12, is to mark the end of the rule list with a reserved value,
and separate antecedents and consequents with another reserved value. This permits
any number of rules, and allows each rule to have any number of antecedents and
consequents, subject to the limits imposed by availability of system memory.
Each rule is evaluated sequentially, but the rules as a group are treated as if they were
all evaluated simultaneously. Two mathematical operations take place during rule
evaluation. The fuzzy and operator corresponds to the mathematical minimum operation and the fuzzy or operation corresponds to the mathematical maximum operation.
The fuzzy and is used to connect antecedents within a rule. The fuzzy or is implied
between successive rules. Before evaluating any rules, all fuzzy outputs are set to
zero (meaning not true at all). As each rule is evaluated, the smallest (minimum) antecedent is taken to be the overall truth of the rule. This rule truth value is applied to
each consequent of the rule (by storing this value to the corresponding fuzzy output)
unless the fuzzy output is already larger (maximum). If two rules affect the same fuzzy
output, the rule that is most true governs the value in the fuzzy output because the
rules are connected by an implied fuzzy or.
In the case of rule weighting, the truth value for a rule is determined as usual by finding
the smallest rule antecedent. Before applying this truth value to the consequents for
the rule, the value is multiplied by a fraction from zero (rule disabled) to one (rule fully
enabled). The resulting modified truth value is then applied to the fuzzy outputs.
The end result of the rule evaluation step is a table of suggested or “raw” fuzzy outputs
in RAM. These values were obtained by plugging current conditions (fuzzy input values) into the system rules in the knowledge base. The raw results cannot be supplied
directly to the system outputs because they may be ambiguous. For instance, one raw
output can indicate that the system output should be medium with a degree of truth of
50% while, at the same time, another indicates that the system output should be low
with a degree of truth of 25%. The defuzzification step resolves these ambiguities.
9.2.3 Defuzzification (WAV)
The final step in the fuzzy logic program combines the raw fuzzy outputs into a composite system output. Unlike the trapezoidal shapes used for inputs, the CPU12 typically uses singletons for output membership functions. As with the inputs, the x-axis
represents the range of possible values for a system output. Singleton membership
functions consist of the x-axis position for a label of the system output. Fuzzy outputs
correspond to the y-axis height of the corresponding output membership function.
The WAV instruction calculates the numerator and denominator sums for weighted average of the fuzzy outputs according to the formula:
MOTOROLA
9-6
FUZZY LOGIC SUPPORT
CPU12
REFERENCE MANUAL
n
∑ Si F i
i =1
System Output = --------------------n
∑ Fi
i =1
Where n is the number of labels of a system output, Si are the singleton positions from
the knowledge base, and Fi are fuzzy outputs from RAM. For a common fuzzy logic
program on the CPU12, n is eight or less (though this instruction can handle any value
to 255) and Si and Fi are 8-bit values. The final divide is performed with a separate
EDIV instruction placed immediately after the WAV instruction.
Before executing WAV, an accumulator must be loaded with the number of iterations
(n), one index register must be pointed at the list of singleton positions in the knowledge base, and a second index register must be pointed at the list of fuzzy outputs in
RAM. If the system has more than one system output, the WAV instruction is executed
once for each system output.
9.3 Example Inference Kernel
Figure 9-3 is a complete fuzzy inference kernel written in CPU12 assembly language.
Numbers in square brackets are cycle counts. The kernel uses two system inputs with
seven labels each and one system output with seven labels. The program assembles
to 57 bytes. It executes in about 54 µs at an 8 MHz bus rate. The basic structure can
easily be extended to a general-purpose system with a larger number of inputs and
outputs.
Lines 1 to 3 set up pointers and load the system input value into the A accumulator.
Line 4 sets the loop count for the loop in lines 5 and 6.
Lines 5 and 6 make up the fuzzification loop for seven labels of one system input. The
MEM instruction finds the y-value on a trapezoidal membership function for the current
input value, for one label of the current input, and then stores the result to the corresponding fuzzy input. Pointers in X and Y are automatically updated by four and one
so they point at the next membership function and fuzzy input respectively.
Line 7 loads the current value of the next system input. Pointers in X and Y already
point to the right places as a result of the automatic update function of the MEM instruction in line 5.
Line 8 reloads a loop count.
Lines 9 and 10 form a loop to fuzzify the seven labels of the second system input.
When the program drops to line 11, the Y index register is pointing at the next location
after the last fuzzy input, which is the first fuzzy output in this system.
CPU12
REFERENCE MANUAL
FUZZY LOGIC SUPPORT
MOTOROLA
9-7
01
02
03
04
05
06
07
08
09
10
*
[2]
[2]
[3]
[1]
[5]
[3]
[3]
[1]
[5]
[3]
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FUZZIFY
LDX
LDY
LDAA
LDAB
MEM
DBNE
LDAA
LDAB
MEM
DBNE
#INPUT_MFS
#FUZ_INS
CURRENT_INS
#7
[1]
[2]
RULE_EVAL
[3]
[2]
[2]
[1]
[3n+4]
LDAB
CLR
DBNE
LDX
LDY
LDAA
REV
#7
1,Y+
b,RULE_EVAL
#RULE_START
#FUZ_INS
#$FF
;Loop count
;Clr a fuzzy out & inc ptr
;Loop to clr all fuzzy outs
;Point at first rule element
;Point at fuzzy ins and outs
;Init A (and clears V-bit)
;Process rule list
[2]
DEFUZ
[1]
[1]
[8b+9]
[11]
[1]
[3]
*
***** End
LDY
LDX
LDAB
WAV
EDIV
TFR
STAB
#FUZ_OUT
#SGLTN_POS
#7
;Point at fuzzy outputs
;Point at singleton positions
;7 fuzzy outs per COG output
;Calculate sums for wtd av
;Final divide for wtd av
;Move result to A:B
;Store system output
GRAD_LOOP
GRAD_LOOP1
B,GRAD_LOOP
CURRENT_INS+1
#7
B,GRAD_LOOP1
Y D
COG_OUT
;Point at MF definitions
;Point at fuzzy input table
;Get first input value
;7 labels per input
;Evaluate one MF
;For 7 labels of 1 input
;Get second input value
;7 labels per input
;Evaluate one MF
;For 7 labels of 1 input
Figure 9-3 Fuzzy Inference Engine
Line 11 sets the loop count to clear seven fuzzy outputs.
Lines 12 and 13 form a loop to clear all fuzzy outputs before rule evaluation starts.
Line 14 initializes the X index register to point at the first element in the rule list for the
REV instruction.
Line 15 initializes the Y index register to point at the fuzzy inputs and outputs in the
system. The rule list (for REV) consists of 8-bit offsets from this base address to particular fuzzy inputs or fuzzy outputs. The special value $FE is interpreted by REV as a
marker between rule antecedents and consequents.
Line 16 initializes the A accumulator to the highest 8-bit value in preparation for finding
the smallest fuzzy input referenced by a rule antecedent. The LDAA #$FF instruction
also clears the V-bit in the CPU12’s condition code register so the REV instruction
knows it is processing antecedents. During rule list processing, the V bit is toggled
each time an $FE is detected in the list. The V bit indicates whether REV is processing
antecedents or consequents.
Line 17 is the REV instruction, a self-contained loop to process successive elements
in the rule list until an $FF character is found. For a system of 17 rules with two antecedents and one consequent each, the REV instruction takes 259 cycles, but it is interruptible so it does not cause a long interrupt latency.
MOTOROLA
9-8
FUZZY LOGIC SUPPORT
CPU12
REFERENCE MANUAL
Lines 18 through 20 set up pointers and an iteration count for the WAV instruction.
Line 21 is the beginning of defuzzification. The WAV instruction calculates a sum-ofproducts and a sum-of-weights.
Line 22 completes defuzzification. The EDIV instruction performs a 32-bit by 16-bit divide on the intermediate results from WAV to get the weighted average.
Line 23 moves the EDIV result into the double accumulator.
Line 24 stores the low 8-bits of the defuzzification result.
This example inference program shows how easy it is to incorporate fuzzy logic into
general applications using the CPU12. Code space and execution time are no longer
serious factors in the decision to use fuzzy logic. The next section begins a much more
detailed look at the fuzzy logic instructions of the CPU12.
9.4 MEM Instruction Details
This section provides a more detailed explanation of the membership function evaluation instruction (MEM), including details about abnormal special cases for improperly
defined membership functions.
9.4.1 Membership Function Definitions
Figure 9-4 shows how a normal membership function is specified in the CPU12. Typically a software tool is used to input membership functions graphically, and the tool
generates data structures for the target processor and software kernel. Alternatively,
points and slopes for the membership functions can be determined and stored in
memory with define-constant assembler directives.
An internal CPU algorithm calculates the y-value where the current input intersects a
membership function. This algorithm assumes the membership function obeys some
common-sense rules. If the membership function definition is improper, the results
may be unusual. 9.4.2 Abnormal Membership Function Definitions discusses
these cases. The following rules apply to normal membership functions.
• $00 ≤ point1 < $FF
• $00 < point2 ≤ $FF
• point1 < point2
• The sloping sides of the trapezoid meet at or above $FF
Each system input such as temperature has several labels such as cold, cool, normal,
warm, and hot. Each label of each system input must have a membership function to
describe its meaning in an unambiguous numerical way. Typically, there are three to
seven labels per system input, but there is no practical restriction on this number as
far as the fuzzification step is concerned.
CPU12
REFERENCE MANUAL
FUZZY LOGIC SUPPORT
MOTOROLA
9-9
GRAPHICAL REPRESENTATION
$FF
$E0
$C0
DEGREE
OF
TRUTH
$A0
$80
SLOPE_2
$60
$40
SLOPE_1
POINT_1
POINT_2
$20
$00
$00
$10
$20
$30
$40
$50
$60
$70
$80
$90
$A0
$B0
$C0
$D0
$E0
$F0
$FF
INPUT RANGE
MEMORY REPRESENTATION
ADDR
$40
X-POSITION OF POINT_1
ADDR+1
$D0
X-POSITION OF POINT_2
ADDR+2
$08
SLOPE_1 ($FF/(X-POS OF SATURATION – POINT_1))
ADDR+3
$04
SLOPE_2 ($FF/(POINT_2 – X-POS OF SATURATION))
NORM MEM FNCTN
Figure 9-4 Defining a Normal Membership Function
9.4.2 Abnormal Membership Function Definitions
In the CPU12, it is possible (and proper) to define “crisp” membership functions. A
crisp membership function has one or both sides vertical (infinite slope). Since the
slope value $00 is not used otherwise, it is assigned to mean infinite slope to the MEM
instruction in the CPU12.
Although a good fuzzy development tool will not allow the user to specify an improper
membership function, it is possible to have program errors or memory errors which result in erroneous abnormal membership functions. Although these abnormal shapes
do not correspond to any working systems, understanding how the CPU12 treats
these cases can be helpful for debugging.
A close examination of the MEM instruction algorithm will show how such membership
functions are evaluated. Figure 9-5 is a complete flow diagram for the execution of a
MEM instruction. Each rectangular box represents one CPU bus cycle. The number in
the upper left corner corresponds to the cycle number and the letter corresponds to
the cycle type (refer to SECTION 6 INSTRUCTION GLOSSARY for details). The upper portion of the box includes information about bus activity during this cycle (if any).
The lower portion of the box, which is separated by a dashed line, includes information
about internal CPU processes. It is common for several internal functions to take place
during a single CPU cycle (for example, in cycle 2, two 8-bit subtractions take place
and a flag is set based on the results).
MOTOROLA
9-10
FUZZY LOGIC SUPPORT
CPU12
REFERENCE MANUAL
START
1-R
Read word @ 0,X — Point_1 and Point_2
X=X+4
2-R
Read word @ –2,X — Slope_1 and Slope_2
Y=Y+1
2a — Delta_1 = ACCA – Point_1
2b — Delta_2 = Point_2 – ACCA
2c — If (Delta_1 or Delta_2) < 0 then flag_d12n = 1 else flag_d12n = 0
3-f
No bus access
3a — If flag_d12n = 1 then Grade_1 = 0 else Grade_1 = Slope_1 * Delta_1
3b — If flag_d12n = 1 then Grade_2 = 0 else Grade_2 = Slope_2 * Delta_2
4-O
If misaligned then read program word to fill instruction queue else no bus access
4a — If (((Slope_2 = 0) or (Grade_2 > $FF)) and (flag_d12n = 0)) then Grade = $FF
else Grade = Grade_2
4b — If (((Slope_1 = 0) or (Grade_1 > $FF)) and (flag_d12n = 0)) then Grade = Grade
else Grade = Grade_1
5-w
Write byte @ –1,Y — Fuzzy input result (Grade)
END
MEM FLOW
Figure 9-5 MEM Instruction Flow Diagram
Consider 4a: If (((Slope_2 = 0) or (Grade_2 > $FF)) and (flag_d12n = 0)).
The flag_d12n is zero as long as the input value (in accumulator A) is within the trapezoid. Everywhere outside the trapezoid, one or the other delta term will be negative,
and the flag will equal one. Slope_2 equals zero indicates the right side of the trapezoid has infinite slope, so the resulting grade should be $FF everywhere in the trapezoid, including at point_2, as far as this side is concerned. The term grade_2 greater
than $FF means the value is far enough into the trapezoid that the right sloping side
of the trapezoid has crossed above the $FF cutoff level and the resulting grade should
be $FF as far as the right sloping side is concerned. 4a decides if the value is left of
the right sloping side (Grade = $FF), or on the sloping portion of the right side of the
trapezoid (Grade = Grade_2). 4b could still override this tentative value in grade.
CPU12
REFERENCE MANUAL
FUZZY LOGIC SUPPORT
MOTOROLA
9-11
In 4b, slope_1 is zero if the left side of the trapezoid has infinite slope (vertical). If so,
the result (grade) should be $FF at and to the right of point_1 everywhere within the
trapezoid as far as the left side is concerned. The grade_1 greater than $FF term corresponds to the input being to the right of where the left sloping side passes the $FF
cutoff level. If either of these conditions is true, the result (grade) is left at the value it
got from 4a. The “else” condition in 4b corresponds to the input falling on the sloping
portion of the left side of the trapezoid (or possibly outside the trapezoid), so the result
is grade equal grade_1. If the input was outside the trapezoid, flag_d12n would be one
and grade_1 and grade_2 would have been forced to $00 in cycle 3. The else condition of 4b would set the result to $00.
The following special cases represent abnormal membership function definitions. The
explanations describe how the specific algorithm in the CPU12 resolves these unusual
cases. The results are not all intuitively obvious, but rather fall out from the specific algorithm. Remember, these cases should not occur in a normal system.
9.4.2.1 Abnormal Membership Function Case 1
This membership function is abnormal because the sloping sides cross below the $FF
cutoff level. The flag_d12n signal forces the membership function to evaluate to $00
everywhere except from point_1 to point_2. Within this interval, the tentative values for
grade_1 and grade_2 calculated in cycle 3 fall on the crossed sloping sides. In step
4a, grade gets set to the grade_2 value, but in 4b this is overridden by the grade_1
value, which ends up as the result of the MEM instruction. One way to say this is that
the result follows the left sloping side until the input passes point_2, where the result
goes to $00.
Memory Definition: $60, $80, $04, $04; Point_1, Point_2, Slope_1, Slope_2
How Interpreted:
Graphical Representation:
P1
P1
P2
P2
ABN MEM 1
Figure 9-6 Abnormal Membership Function Case 1
If point_1 was to the right of point_2, flag_d12n would force the result to be $00 for all
input values. In fact, flag_d12n always limits the region of interest to the space greater
than or equal to point_1 and less than or equal to point_2.
MOTOROLA
9-12
FUZZY LOGIC SUPPORT
CPU12
REFERENCE MANUAL
9.4.2.2 Abnormal Membership Function Case 2
Like the previous example, the membership function in case 2 is abnormal because
the sloping sides cross below the $FF cutoff level, but the left sloping side reaches the
$FF cutoff level before the input gets to point_2. In this case, the result follows the left
sloping side until it reaches the $FF cutoff level. At this point, the (grade_1 > $FF) term
of 4b kicks in, making the expression true so grade equals grade (no overwrite). The
result from here to point_2 becomes controlled by the “else” part of 4a (grade =
grade_2), and the result follows the right sloping side.
Memory Definition: $60, $C0, $04, $04; Point_1, Point_2, Slope_1, Slope_2
Graphical Representation
P1
P2
How Interpreted
P1
Left Side P2
Crosses $FF
ABN MEM 2
Figure 9-7 Abnormal Membership Function Case 2
9.4.2.3 Abnormal Membership Function Case 3
The membership function in case 3 is abnormal because the sloping sides cross below
the $FF cutoff level, and the left sloping side has infinite slope. In this case, 4a is not
true, so grade equals grade_2. 4b is true because slope_1 is zero, so 4b does not
overwrite grade.
Memory Definition: $60, $80, $00, $04; Point_1, Point_2, Slope_1, Slope_2
Graphical Representation
P1
P2
How Interpreted
P1
P2
ABN MEM 3
Figure 9-8 Abnormal Membership Function Case 3
9.5 REV, REVW Instruction Details
This section provides a more detailed explanation of the rule evaluation instructions
(REV and REVW). The data structures used to specify rules are somewhat different
for the weighted versus unweighted versions of the instruction. One uses 8-bit offsets
in the encoded rules, while the other uses full 16-bit addresses. This affects the size
of the rule data structure and execution time.
CPU12
REFERENCE MANUAL
FUZZY LOGIC SUPPORT
MOTOROLA
9-13
9.5.1 Unweighted Rule Evaluation (REV)
This instruction implements basic min-max rule evaluation. CPU registers are used for
pointers and intermediate calculation results.
Since the REV instruction is essentially a list-processing instruction, execution time is
dependent on the number of elements in the rule list. The REV instruction is interruptible (typically within three bus cycles), so it does not adversely affect worst case interrupt latency. Since all intermediate results and instruction status are held in stacked
CPU registers, the interrupt service code can even include independent REV and
REVW instructions.
9.5.1.1 Set Up Prior to Executing REV
Some CPU registers and memory locations need to be set up prior to executing the
REV instruction. X and Y index registers are used as index pointers to the rule list and
the fuzzy inputs and outputs. The A accumulator is used for intermediate calculation
results and needs to be set to $FF initially. The V condition code bit is used as an instruction status indicator to show whether antecedents or consequents are being processed. Initially, the V bit is cleared to zero to indicate antecedents are being
processed. The fuzzy outputs (working RAM locations) need to be cleared to $00. If
these values are not initialized before executing the REV instruction, results will be erroneous.
The X index register is set to the address of the first element in the rule list (in the
knowledge base). The REV instruction automatically updates this pointer so that the
instruction can resume correctly if it is interrupted. After the REV instruction finishes,
X will point at the next address past the $FF separator character that marks the end
of the rule list.
The Y index register is set to the base address for the fuzzy inputs and outputs (in
working RAM). Each rule antecedent is an unsigned 8-bit offset from this base address
to the referenced fuzzy input. Each rule consequent is an unsigned 8-bit offset from
this base address to the referenced fuzzy output. The Y index register remains constant throughout execution of the REV instruction.
The 8-bit A accumulator is used to hold intermediate calculation results during execution of the REV instruction. During antecedent processing, A starts out at $FF and is
replaced by any smaller fuzzy input that is referenced by a rule antecedent (MIN). During consequent processing, A holds the truth value for the rule. This truth value is
stored to any fuzzy output that is referenced by a rule consequent, unless that fuzzy
output is already larger (MAX).
Before starting to execute REV, A must be set to $FF (the largest 8-bit value) because
rule evaluation always starts with processing of the antecedents of the first rule. For
subsequent rules in the list, A is automatically set to $FF when the instruction detects
the $FE marker character between the last consequent of the previous rule, and the
first antecedent of a new rule.
MOTOROLA
9-14
FUZZY LOGIC SUPPORT
CPU12
REFERENCE MANUAL
The instruction LDAA #$FF clears the V bit at the same time it initializes A to $FF. This
satisfies the REV setup requirement to clear the V bit as well as the requirement to
initialize A to $FF. Once the REV instruction starts, the value in the V bit is automatically maintained as $FE separator characters are detected.
The final requirement to clear all fuzzy outputs to $00 is part of the MAX algorithm.
Each time a rule consequent references a fuzzy output, that fuzzy output is compared
to the truth value for the current rule. If the current truth value is larger, it is written over
the previous value in the fuzzy output. After all rules have been evaluated, the fuzzy
output contains the truth value for the most-true rule that referenced that fuzzy output.
After REV finishes, A will hold the truth value for the last rule in the rule list. The V condition code bit should be one because the last element before the $FF end marker
should have been a rule consequent. If V is zero after executing REV, it indicates the
rule list was structured incorrectly.
9.5.1.2 Interrupt Details
The REV instruction includes a three-cycle processing loop for each byte in the rule
list (including antecedents, consequents, and special separator characters). Within
this loop, a check is performed to see if any qualified interrupt request is pending. If an
interrupt is detected, the current CPU registers are stacked and the interrupt is honored. When the interrupt service routine finishes, an RTI instruction causes the CPU
to recover its previous context from the stack, and the REV instruction is resumed as
if it had not been interrupted.
The stacked value of the program counter (PC), in case of an interrupted REV instruction, points to the REV instruction rather than the instruction that follows. This causes
the CPU to try to execute a new REV instruction upon return from the interrupt. Since
the CPU registers (including the V bit in the condition codes register) indicate the current status of the interrupted REV instruction, this effectively causes the rule evaluation operation to resume from where it left off.
9.5.1.3 Cycle-by-Cycle Details for REV
The central element of the REV instruction is a three-cycle loop that is executed once
for each byte in the rule list. There is a small amount of housekeeping activity to get
this loop started as REV begins, and a small sequence to end the instruction. If an interrupt comes, there is a special small sequence to save CPU status on the stack before honoring the requested interrupt.
Figure 9-9 is a REV instruction flow diagram. Each rectangular box represents one
CPU clock cycle. Decision blocks and connecting arrows are considered to take no
time at all. The letters in the small rectangles in the upper left corner of each bold box
correspond to execution cycle codes (refer to SECTION 6 INSTRUCTION GLOSSARY for details). Lower case letters indicate a cycle where 8-bit or no data is transferred.
Upper case letters indicate cycles where 16-bit or no data is transferred.
CPU12
REFERENCE MANUAL
FUZZY LOGIC SUPPORT
MOTOROLA
9-15
START
1.0 - O
Read program word if $18 misaligned
2.0 - r
Read byte @ 0,X (rule element Rx)
X = X + 1 point at next rule element
No bus access
3.0 - f
4.0 - t
Update Rx with value read in cyc 2 or 5
If Rx ≠ $FE or $FF
then Read byte @ Rx,Y (fuzzy in or out Fy)
else no bus access
If Rx = $FE & V was 1, Reset ACCA to $FF
If Rx = $FE Toggle V-bit
Yes
Interrupt pending?
No
5.0 - t
$FF
Rx = $FF, other?
5.2 - f
No bus access
Adjust PC to point at current REV instruction
Other
Read byte @ 0,X (rule element Rx)
6.2 - f
No bus access
Adjust X = X – 1
X = X + 1 point at next rule element
Continue to interrupt stacking
V-bit =?
0 (min)
6.0 - x
1 (max)
No bus access
6.1 - x
Update Fy with value read in cyc 4.0
If Rx ≠ $FE then A = min(A, Fy)
else A = A (no change to A)
No
Update Fy with value read in cyc 4.0
If Rx ≠ $FE or $FF, and ACCA > Fy
then Write byte @ Rx,Y
else no bus access
Rx = $FF (end of rules)?
Yes
7.0 - O Read program word if $3A misaligned
END
REV INST FLOW
Figure 9-9 REV Instruction Flow Diagram
MOTOROLA
9-16
FUZZY LOGIC SUPPORT
CPU12
REFERENCE MANUAL
When a value is read from memory, it cannot be used by the CPU until the second
cycle after the read takes place. This is due to access and propagation delays.
Since there is more than one flow path through the REV instruction, cycle numbers
have a decimal place. This decimal place indicates which of several possible paths is
being used. The CPU normally moves forward by one digit at a time within the same
flow (flow number is indicated after the decimal point in the cycle number). There are
two exceptions possible to this orderly sequence through an instruction. The first is a
branch back to an earlier cycle number to form a loop as in 6.0 to 4.0. The second type
of sequence change is from one flow to a parallel flow within the same instruction such
as 4.0 to 5.2, which occurs if the REV instruction senses an interrupt. In this second
type of sequence branch, the whole number advances by one and the flow number
changes to a new value (the digit after the decimal point).
In cycle 1.0, the CPU12 does an optional program word access to replace the $18 prebyte of the REV instruction. Notice that cycle 7.0 is also an O type cycle. One or the
other of these will be a program word fetch, while the other will be a free cycle where
the CPU does not access the bus. Although the $18 page prebyte is a required part of
the REV instruction, it is treated by the CPU12 as a somewhat separate single cycle
instruction.
Rule evaluation begins at cycle 2.0 with a byte read of the first element in the rule list.
Usually this would be the first antecedent of the first rule, but the REV instruction can
be interrupted, so this could be a read of any byte in the rule list. The X index register
is incremented so it points to the next element in the rule list. Cycle 3.0 is needed to
satisfy the required delay between a read and when data is valid to the CPU. Some
internal CPU housekeeping activity takes place during this cycle, but there is no bus
activity. By cycle 4.0, the rule element that was read in cycle 2.0 is available to the
CPU.
Cycle 4.0 is the first cycle of the main three cycle rule evaluation loop. Depending upon
whether rule antecedents or consequents are being processed, the loop will consist of
cycles 4.0, 5.0, 6.0, or the sequence 4.0, 5.0, 6.1. This loop is executed once for every
byte in the rule list, including the $FE separators and the $FF end-of-rules marker.
At each cycle 4.0, a fuzzy input or fuzzy output is read, except during the loop passes
associated with the $FE and $FF marker bytes, where no bus access takes place during cycle 4.0. The read access uses the Y index register as the base address and the
previously read rule byte (Rx) as an unsigned offset from Y. The fuzzy input or output
value read here will be used during the next cycle 6.0 or 6.1. Besides being used as
the offset from Y for this read, the previously read Rx is checked to see if it is a separator character ($FE). If Rx was $FE and the V-bit was one, this indicates a switch from
processing consequents of one rule to starting to process antecedents of the next rule.
At this transition, the A accumulator is initialized to $FF to prepare for the min operation to find the smallest fuzzy input. Also, if Rx is $FE, the V-bit is toggled to indicate
the change from antecedents to consequents, or consequents to antecedents.
During cycle 5.0, a new rule byte is read unless this is the last loop pass, and Rx is
$FF (marking the end of the rule list). This new rule byte will not be used until cycle 4.0
of the next pass through the loop.
CPU12
REFERENCE MANUAL
FUZZY LOGIC SUPPORT
MOTOROLA
9-17
Between cycle 5.0 and 6.x, the V-bit is used to decide which of two paths to take. If V
is zero, antecedents are being processed and the CPU progresses to cycle 6.0. If V is
one, consequents are being processed and the CPU goes to cycle 6.1.
During cycle 6.0, the current value in the A accumulator is compared to the fuzzy input
that was read in the previous cycle 4.0, and the lower value is placed in the A accumulator (min operation). If Rx is $FE, this is the transition between rule antecedents
and rule consequents, and this min operation is skipped (although the cycle is still
used). No bus access takes place during cycle 6.0 but cycle 6.x is considered an x type
cycle because it could be a byte write (cycle 6.1), or a free cycle (cycle 6.0 or 6.1 with
Rx = $FE or $FF).
If an interrupt arrives while the REV instruction is executing, REV can break between
cycles 4.0 and 5.0 in an orderly fashion so that the rule evaluation operation can resume after the interrupt has been serviced. Cycles 5.2 and 6.2 are needed to adjust
the PC and X index register so the REV operation can recover after the interrupt. PC
is adjusted backward in cycle 5.2 so it points to the currently running REV instruction.
After the interrupt, rule evaluation will resume, but the values that were stored on the
stack for index registers, accumulator A, and CCR will cause the operation to pick up
where it left off. In cycle 6.2, the X index register is adjusted backward by one because
the last rule byte needs to be re-fetched when the REV instruction resumes.
After cycle 6.2, the REV instruction is finished, and execution would continue to the
normal interrupt processing flow.
9.5.2 Weighted Rule Evaluation (REVW)
This instruction implements a weighted variation of min-max rule evaluation. The
weighting factors are stored in a table with one 8-bit entry per rule. The weight is used
to multiply the truth value of the rule (minimum of all antecedents) by a value from zero
to one to get the weighted result. This weighted result is then applied to the consequents, just as it would be for unweighted rule evaluation.
Since the REVW instruction is essentially a list-processing instruction, execution time
is dependent on the number of rules and the number of elements in the rule list. The
REVW instruction is interruptible (typically within three to five bus cycles), so it does
not adversely affect worst case interrupt latency. Since all intermediate results and instruction status are held in stacked CPU registers, the interrupt service code can even
include independent REV and REVW instructions.
The rule structure is different for REVW than for REV. For REVW, the rule list is made
up of 16-bit elements rather than 8-bit elements. Each antecedent is represented by
the full 16-bit address of the corresponding fuzzy input. Each rule consequent is represented by the full address of the corresponding fuzzy output.
The markers separating antecedents from consequents are the reserved 16-bit value
$FFFE, and the end of the last rule is marked by the reserved 16-bit value $FFFF.
Since $FFFE and $FFFF correspond to the addresses of the reset vector, there would
never be a fuzzy input or output at either of these locations.
MOTOROLA
9-18
FUZZY LOGIC SUPPORT
CPU12
REFERENCE MANUAL
9.5.2.1 Set Up Prior to Executing REVW
Some CPU registers and memory locations need to be set up prior to executing the
REVW instruction. X and Y index registers are used as index pointers to the rule list
and the list of rule weights. The A accumulator is used for intermediate calculation results and needs to be set to $FF initially. The V condition code bit is used as an instruction status indicator that shows whether antecedents or consequents are being
processed. Initially the V bit is cleared to zero to indicate antecedents are being processed. The C condition code bit is used to indicate whether rule weights are to be
used (1) or not (0). The fuzzy outputs (working RAM locations) need to be cleared to
$00. If these values are not initialized before executing the REVW instruction, results
will be erroneous.
The X index register is set to the address of the first element in the rule list (in the
knowledge base). The REVW instruction automatically updates this pointer so that the
instruction can resume correctly if it is interrupted. After the REVW instruction finishes,
X will point at the next address past the $FFFF separator word that marks the end of
the rule list.
The Y index register is set to the starting address of the list of rule weights. Each rule
weight is an 8-bit value. The weighted result is the truncated upper eight bits of the 16bit result, which is derived by multiplying the minimum rule antecedent value ($00–
$FF) by the weight plus one ($001–$100). This method of weighting rules allows an 8bit weighting factor to represent a value between zero and one inclusive.
The 8-bit A accumulator is used to hold intermediate calculation results during execution of the REVW instruction. During antecedent processing, A starts out at $FF and
is replaced by any smaller fuzzy input that is referenced by a rule antecedent. If rule
weights are enabled by the C condition code bit equal one, the rule truth value is multiplied by the rule weight just before consequent processing starts. During consequent
processing, A holds the truth value (possibly weighted) for the rule. This truth value is
stored to any fuzzy output that is referenced by a rule consequent, unless that fuzzy
output is already larger (MAX).
Before starting to execute REVW, A must be set to $FF (the largest 8-bit value) because rule evaluation always starts with processing of the antecedents of the first rule.
For subsequent rules in the list, A is automatically set to $FF when the instruction detects the $FFFE marker word between the last consequent of the previous rule, and
the first antecedent of a new rule.
Both the C and V condition code bits must be set up prior to starting a REVW instruction. Once the REVW instruction starts, the C bit remains constant and the value in the
V bit is automatically maintained as $FFFE separator words are detected.
The final requirement to clear all fuzzy outputs to $00 is part of the MAX algorithm.
Each time a rule consequent references a fuzzy output, that fuzzy output is compared
to the truth value (weighted) for the current rule. If the current truth value is larger, it is
written over the previous value in the fuzzy output. After all rules have been evaluated,
the fuzzy output contains the truth value for the most-true rule that referenced that
fuzzy output.
CPU12
REFERENCE MANUAL
FUZZY LOGIC SUPPORT
MOTOROLA
9-19
After REVW finishes, A will hold the truth value (weighted) for the last rule in the rule
list. The V condition code bit should be one because the last element before the $FFFF
end marker should have been a rule consequent. If V is zero after executing REVW,
it indicates the rule list was structured incorrectly.
9.5.2.2 Interrupt Details
The REVW instruction includes a three-cycle processing loop for each word in the rule
list (this loop expands to five cycles between antecedents and consequents to allow
time for the multiplication with the rule weight). Within this loop, a check is performed
to see if any qualified interrupt request is pending. If an interrupt is detected, the current CPU registers are stacked and the interrupt is honored. When the interrupt service routine finishes, an RTI instruction causes the CPU to recover its previous context
from the stack, and the REVW instruction is resumed as if it had not been interrupted.
The stacked value of the program counter (PC), in case of an interrupted REVW instruction, points to the REVW instruction rather than the instruction that follows. This
causes the CPU to try to execute a new REVW instruction upon return from the interrupt. Since the CPU registers (including the C bit and V bit in the condition codes register) indicate the current status of the interrupted REVW instruction, this effectively
causes the rule evaluation operation to resume from where it left off.
9.5.2.3 Cycle-by-Cycle Details for REVW
The central element of the REVW instruction is a three-cycle loop that is executed
once for each word in the rule list. For the special case pass (where the $FFFE separator word is read between the rule antecedents and the rule consequents, and
weights enabled by the C bit equal one), this loop takes five cycles. There is a small
amount of housekeeping activity to get this loop started as REVW begins and a small
sequence to end the instruction. If an interrupt comes, there is a special small sequence to save CPU status on the stack before the interrupt is serviced.
Figure 9-10 is a detailed flow diagram for the REVW instruction. Each rectangular box
represents one CPU clock cycle. Decision blocks and connecting arrows are considered to take no time at all. The letters in the small rectangles in the upper left corner
of each bold box correspond to the execution cycle codes (refer to SECTION 6 INSTRUCTION GLOSSARY for details). Lower case letters indicate a cycle where 8-bit
or no data is transferred. Upper case letters indicate cycles where 16-bit data could be
transferred.
MOTOROLA
9-20
FUZZY LOGIC SUPPORT
CPU12
REFERENCE MANUAL
START
1.0 - O
Read program word if $18 misaligned
2.0 - r
Read word @ 0,X (rule element Rx)
X = X + 2 point at next rule element
3.0 - f
No bus access
TMP2 = Y – 1 (weight pointer kept in TMP2)
4.0 - t
If Rx = $FFFE
If V = 0, then TMP2 = TMP2 + 1
If V = 0 and C = 1,
then read rule weight @,TMP2
else no bus access
Update Rx with value read in cyc 2 or 5
If Rx = $FFFF
then no bus access
If Rx = other
then read byte @,Rx fuzzy in/out FRx
Toggle V bit; If V now 0, A = $FF
No
5.0 - T
Interrupt pending?
If Rx ≠ $FFFF
then read rule word @,X0
5.3 - f
mul
V=C=1 & Rx=$FFFE
Min/max/mul?
max
V = 1 & Rx ≠ $FFFE or $FFFF
6.1 - x
No bus access
Adjust PC to point at current REVW instruction
X0 = X, X = X0 + 2
min
or default
Yes
If A > FRx write A to Rx
else no bus access
6.3 - f
No bus access
Adjust X = X – 2 pointer to rule list
7.3 - f
No bus access
If (Rx = $FFFE or $FFFE) and V = 0
then TMP2 = TMP2 – 1
8.3 - f
No bus access
Y = TMP2 + 1
No bus access
6.0 - x
A = min(A, FRx)
Continue to interrupt stacking
6.2 - f
No
7.0 - O
Begin multiply of (wt + 1) * A ⇒ A : B
Rx = $FFFF (end of rules)?
Yes
7.2 - R
Read program word if $3B misaligned
Adjust PC to point at next instruction
If C = 1 (weights enabled), Y = TMP2 + 1
No bus access
Read rule word @,X0
Continue multiply
8.2 - f
No bus access
Finish multiply
END
REVW INST FLW
Figure 9-10 REVW Instruction Flow Diagram
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In cycle 2.0, the first element of the rule list (a 16-bit address) is read from memory.
Due to propagation delays, this value cannot be used for calculations until two cycles
later (cycle 4.0). The X index register, which is used to access information from the
rule list, is incremented by two to point at the next element of the rule list.
The operations performed in cycle 4.0 depend on the value of the word read from the
rule list. $FFFE is a special token that indicates a transition from antecedents to consequents, or from consequents to antecedents of a new rule. The V bit can be used to
decide which transition is taking place, and V is toggled each time the $FFFE token is
detected. If V was zero, a change from antecedents to consequents is taking place,
and it is time to apply weighting (provided it is enabled by the C bit equal one). The
address in TMP2 (derived from Y) is used to read the weight byte from memory. In this
case, there is no bus access in cycle 5.0, but the index into the rule list is updated to
point to the next rule element.
The old value of X (X0) is temporarily held on internal nodes, so it can be used to access a rule word in cycle 7.2. The read of the rule word is timed to start two cycles before it will be used in cycle 4.0 of the next loop pass. The actual multiply takes place
in cycles 6.2 through 8.2. The 8-bit weight from memory is incremented (possibly overflowing to $100) before the multiply, and the upper eight bits of the 16-bit internal result
is used as the weighted result. By using weight+1, the result can range from 0.0 times
A to 1.0 times A. After 8.2, flow continues to the next loop pass at cycle 4.0.
At cycle 4.0, if Rx is $FFFE and V was one, a change from consequents to antecedents of a new rule is taking place, so accumulator A must be reinitialized to $FF. During
processing of rule antecedents, A is updated with the smaller of A, or the current fuzzy
input (cycle 6.0). Cycle 5.0 is usually used to read the next rule word and update the
pointer in X. This read is skipped if the current Rx is $FFFF (end of rules mark). If this
is a weight multiply pass, the read is delayed until cycle 7.2. During processing of consequents, cycle 6.1 is used to optionally update a fuzzy output if the value in accumulator A is larger.
After all rules have been processed, cycle 7.0 is used to update the PC to point at the
next instruction. If weights were enabled, Y is updated to point at the location that immediately follows the last rule weight.
9.6 WAV Instruction Details
The WAV instruction performs weighted average calculations used in defuzzification.
The pseudo-instruction wavr is used to resume an interrupted weighted average operation. WAV calculates the numerator and denominator sums using:
n
∑ Si F i
i =1
System Output = --------------------n
∑ Fi
i =1
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Where n is the number of labels of a system output, Si are the singleton positions from
the knowledge base, and Fi are fuzzy outputs from RAM. Si and Fi are 8-bit values.
The 8-bit B accumulator holds the iteration count n. Internal temporary registers hold
intermediate sums, 24 bits for the numerator and 16 bits for the denominator. This
makes this instruction suitable for n values up to 255 although eight is a more typical
value. The final long division is performed with a separate EDIV instruction immediately after the WAV instruction. The WAV instruction returns the numerator and denominator sums in the correct registers for the EDIV. (EDIV performs the unsigned division
Y = Y : D / X; remainder in D).
Execution time for this instruction depends on the number of iterations (labels for the
system output). WAV is interruptible so that worst case interrupt latency is not affected
by the execution time for the complete weighted average operation. WAV includes initialization for the 24-bit and 16-bit partial sums so the first entry into WAV looks different than a resume from interrupt operation. The CPU12 handles this difficulty with a
pseudo-instruction (wavr), which is specifically intended to resume an interrupted
weighted average calculation. Refer to 9.6.3 Cycle-by-Cycle Details for WAV and
wavr for more detail.
9.6.1 Setup Prior to Executing WAV
Before executing the WAV instruction, index registers X and Y and accumulator B
must be set up. Index register X is a pointer to the Si singleton list. X must have the
address of the first singleton value in the knowledge base. Index register Y is a pointer
to the fuzzy outputs Fi. Y must have the address of the first fuzzy output for this system
output. B is the iteration count n. The B accumulator must be set to the number of labels for this system output.
9.6.2 WAV Interrupt Details
The WAV instruction includes an 8-cycle processing loop for each label of the system
output. Within this loop, the CPU checks whether a qualified interrupt request is pending. If an interrupt is detected, the current values of the internal temporary registers for
the 24-bit and 16-bit sums are stacked, the CPU registers are stacked, and the interrupt is serviced.
A special processing sequence is executed when an interrupt is detected during a
weighted average calculation. This exit sequence adjusts the PC so that it points to
the second byte of the WAV object code ($3C), before the PC is stacked. Upon return
from the interrupt, the $3C value is interpreted as a wavr pseudo-instruction. The wavr
pseudo-instruction causes the CPU to execute a special WAV resumption sequence.
The wavr recovery sequence adjusts the PC so that it looks like it did during execution
of the original WAV instruction, then jumps back into the WAV processing loop. If another interrupt occurs before the weighted average calculation finishes, the PC is adjusted again as it was for the first interrupt. WAV can be interrupted any number of
times, and additional WAV instructions can be executed while a WAV instruction is interrupted.
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9.6.3 Cycle-by-Cycle Details for WAV and wavr
The WAV instruction is unusual in that the logic flow has two separate entry points.
The first entry point is the normal start of a WAV instruction. The second entry point is
used to resume the weighted average operation after a WAV instruction has been interrupted. This recovery operation is called the wavr pseudo-instruction.
Figure 9-11 is a flow diagram of the WAV instruction including the wavr pseudo-instruction. Each rectangular box in this figure represents one CPU clock cycle. Decision
blocks and connecting arrows are considered to take no time at all. The letters in the
small rectangles in the upper left corner of the boxes correspond to execution cycle
codes (refer to SECTION 6 INSTRUCTION GLOSSARY for details). Lower case letters indicate a cycle where 8-bit or no data is transferred. Upper case letters indicate
cycles where 16-bit data could be transferred.
In terms of cycle-by-cycle bus activity, the $18 page select prebyte is treated as a special 1-byte instruction. In cycle 1.0 of the WAV instruction, one word of program information will be fetched into the instruction queue if the $18 is located at an odd address.
If the $18 is at an even address, the instruction queue cannot advance so there is no
bus access in this cycle.
There is no bus access in cycles 2.0 or 3.0. In cycle 3.0, three internal 16-bit temporary
registers are cleared in preparation for summation operations. The WAV instruction
maintains a 32-bit sum-of-products in TMP3 : TMP2 and a 16-bit sum-of-weights in
TMP1. By keeping these sums inside the CPU, bus accesses are reduced and the
WAV operation is optimized for high speed.
Cycles 4.0 through 11.0 form the eight cycle main loop for WAV. The value in the 8-bit
B accumulator is used to count the number of loop iterations. B is decremented at the
top of the loop in cycle 4.0, and the test for zero is located at the bottom of the loop
after cycle 11.0. Cycle 5.0 and 6.0 are used to fetch the 8-bit operands for one iteration
of the loop. X and Y index registers are used to access these operands. The index registers are incremented as the operands are fetched. Cycle 7.0 is used to accumulate
the current fuzzy output into TMP1. Cycles 8.0 through 10.0 are used to perform the
eight by eight multiply of Fi times Si. The multiply result is accumulated into TMP3 :
TMP2 during cycles 10.0 and 11.0. Even though the sum-of-products will not exceed
24 bits, the sum is maintained in the 32-bit combined TMP3 : TMP2 register because
it is easier to use existing 16-bit operations than it would be to create a new smaller
operation to handle the high order bits of this sum.
Since the weighted average operation could be quite long, it is made to be interruptible. The usual longest latency path is from very early in cycle 7.0, through cycle 11.0,
to the top of the loop to cycle 4.0, through cycle 6.0 to the interrupt check. There is also
a three cycle (7.1 through 9.1) exit sequence making this latency path a total of 12 cycles. There is an even longer path, but it is much less likely to occur. If an interrupt
comes near the beginning of cycle 2.1, when a weighted average operation is being
resumed after a previous interrupt, the latency path is 2.1 through 6.1 plus 7.0 through
11.0 plus 4.0 through 6.0 plus the exit 7.1 through 9.1. This is a worst-case total of 17
cycles.
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WAV
1.0 - O
Read program word if $18 misaligned
2.0 - f
No bus access
wavr
2.1 - U
3.0 - f
Read word @ 0,SP (unstack TMP3)
SP = SP + 2
No bus access
TMP1 = TMP2 = TMP3 = $0000
3.1 - U
Read word @ 0,SP (unstack TMP2)
SP = SP + 2
4.0 - f
4.1 - U
No bus access
Read word @ 0,SP (unstack TMP1)
B = B – 1 decrement iteration counter
SP = SP + 2
5.0 - r
5.1 - r
Read byte @ –1,Y (fuzzy output Fi)
6.1 - r
Read byte @ –1,X (singleton Si)
7.1 - S
Write word @ –2,SP (stack TMP1)
Read byte @ 0,Y (fuzzy output Fi)
Y = Y + 1 point at next fuzzy output
6.0 - r
Read byte @ 0,X (singleton Si)
X = X + 1 point at next singleton
Interrupt pending?
No
7.0 - f
Yes
No bus access
TMP1 = TMP1 + Fi
SP = SP – 2
8.0 - f
8.1 - S
No bus access
Write word @ –2,SP (stack TMP2)
Start multiply PPROD = Si*Fi
SP = SP – 2
9.0 - f
9.1 - S
No bus access
Continue multiply
10.0 - f
Write word @ –2,SP (stack TMP3)
SP = SP – 2
Adjust PC to point at $3C wavr pseudo-opcode
No bus access
Finish multiply, TMP2 = TMP2 + PPROD
Continue to interrupt stacking
11.0 - f
No bus access
TMP3 = TMP3 + (carry from PPROD add)
No
12.0 - O
B = 0?
Yes
Read program word if $3C misaligned
Adjust PC to point at next instruction
Y : D = TMP3 : TMP2; X = TMP1
END
WAV INST FLOW
Figure 9-11 WAV and wavr Instruction Flow Diagram
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If the WAV instruction is interrupted, the internal temporary registers TMP3, TMP2,
and TMP1 need to be stored on the stack so the operation can be resumed. Since the
WAV instruction included initialization in cycle 2.0, the recovery path after an interrupt
needs to be different. The wavr pseudo-instruction has the same opcode as WAV, but
it is on the first page of the opcode map so there is no page prebyte ($18) like there is
for WAV. When WAV is interrupted, the PC is adjusted to point at the second byte of
the WAV object code, so that it will be interpreted as the wavr pseudo-instruction on
return from the interrupt, rather than the WAV instruction. During the recovery sequence, the PC is readjusted in case another interrupt comes before the weighted average operation finishes.
The resume sequence includes recovery of the temporary registers from the stack (2.1
through 4.1), and reads to get the operands for the current iteration. The normal WAV
flow is then rejoined at cycle 7.0.
Upon normal completion of the instruction (cycle 12.0), the PC is adjusted so it points
to the next instruction. The results are transferred from the TMP registers into CPU
registers in such a way that the EDIV instruction can be used to divide the sum-ofproducts by the sum-of-weights. TMP3 : TMP2 is transferred into Y : D and TMP1 is
transferred into X.
9.7 Custom Fuzzy Logic Programming
The basic fuzzy logic inference techniques described above are suitable for a broad
range of applications, but some systems may require customization. The built-in fuzzy
instructions use 8-bit resolution and some systems may require finer resolution. The
rule evaluation instructions only support variations of MIN-MAX rule evaluation and
other methods have been discussed in fuzzy logic literature. The weighted average of
singletons is not the only defuzzification technique. The CPU12 has several instructions and addressing modes that can be helpful when in developing custom fuzzy logic
systems.
9.7.1 Fuzzification Variations
The MEM instruction supports trapezoidal membership functions and several other varieties, including membership functions with vertical sides (infinite slope sides). Triangular membership functions are a subset of trapezoidal functions. Some practitioners
refer to s-, z-, and π-shaped membership functions. These refer to a trapezoid butted
against the right end of the x-axis, a trapezoid butted against the left end of the x-axis,
and a trapezoidal membership function that isn’t butted against either end of the xaxis, respectively. Many other membership function shapes are possible, if memory
space and processing bandwidth are sufficient.
Tabular membership functions offer complete flexibility in shape and very fast evaluation time. However, tables take a very large amount of memory space (as many as 256
bytes per label of one system input). The excessive size to specify tabular membership functions makes them impractical for most microcontroller-based fuzzy systems.
The CPU12 instruction set includes two instructions (TBL and ETBL) for lookup and
interpolation of compressed tables.
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The TBL instruction uses 8-bit table entries (y-values) and returns an 8-bit result. The
ETBL instruction uses 16-bit table entries (y-values) and returns a 16-bit result. A flexible indexed addressing mode is used to identify the effective address of the data point
at the beginning of the line segment, and the data value for the end point of the line
segment is the next consecutive memory location (byte for TBL and word for ETBL).
In both cases, the B accumulator represents the ratio of (the x-distance from the beginning of the line segment to the lookup point) to (the x-distance from the beginning
of the line segment to the end of the line segment). B is treated as an 8-bit binary fraction with radix point left of the MSB, so each line segment can effectively be divided
into 256 pieces. During execution of the TBL or ETBL instruction, the difference between the end point y-value and the beginning point y-value (a signed byte-TBL or
word-ETBL) is multiplied by the B accumulator to get an intermediate delta-y term. The
result is the y-value of the beginning point, plus this signed intermediate delta-y value.
Because indexed addressing mode is used to identify the starting point of the line segment of interest, there is a great deal of flexibility in constructing tables. A common
method is to break the x-axis range into 256 equal width segments and store the y value for each of the resulting 257 endpoints. The 16-bit D accumulator is then used as
the x input to the table. The upper eight bits (A) is used as a coarse lookup to find the
line segment of interest, and the lower eight bits (B) is used to interpolate within this
line segment.
In the program sequence…
LDX
LDD
TBL
#TBL_START
DATA_IN
A,X
The notation A,X causes the TBL instruction to use the Ath line segment in the table.
The low-order half of D (B) is used by TBL to calculate the exact data value from this
line segment. This type of table uses only 257 entries to approximate a table with 16
bits of resolution. This type of table has the disadvantage of equal width line segments,
which means just as many points are needed to describe a flat portion of the desired
function as are needed for the most active portions.
Another type of table stores x:y coordinate pairs for the endpoints of each linear segment. This type of table may reduce the table storage space compared to the previous
fixed-width segments because flat areas of the functions can be specified with a single
pair of endpoints. This type of table is a little harder to use with the CPU12 TBL and
ETBL instructions because the table instructions expect y-values for segment endpoints to be in consecutive memory locations.
Consider a table made up of an arbitrary number of x:y coordinate pairs, where all values are eight bits. The table is entered with the x-coordinate of the desired point to
lookup in the A accumulator. When the table is exited, the corresponding y-value is in
the A accumulator. Figure 9-12 shows one way to work with this type of table.
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BEGIN
FIND_LOOP
LDY
CMPA
#TABLE_START-2
2,+Y
;setup initial table pointer
;find first Xn > XL
;(auto pre-inc Y by 2)
BLS
FIND_LOOP
;loop if XL .le. Xn
* on fall thru, XB@-2,Y YB@-1,Y XE@0,Y and YE@1,Y
TFR
D,X
;save XL in high half of X
CLRA
;zero upper half of D
LDAB
0,Y
;D = 0:XE
SUBB
-2,Y
;D = 0:(XE-XB)
EXG
D,X
;X = (XE-XB).. D = XL:junk
SUBA
-2,Y
;A = (XL-XB)
EXG
A,D
;D = 0:(XL-XB), uses trick of EXG
FDIV
;X reg = (XL-XB)/(XE-XB)
EXG
D,X
;move fractional result to A:B
EXG
A,B
;byte swap - need result in B
TSTA
;check for rounding
BPL
NO_ROUND
INCB
;round B up by 1
NO_ROUND
LDAA
1,Y
;YE
PSHA
;put on stack for TBL later
LDAA
-1,Y
;YB
PSHA
;now YB@0,SP and YE@1,SP
TBL
2,SP+
;interpolate and deallocate
;stack temps
Figure 9-12 Endpoint Table Handling
The basic idea is to find the segment of interest, temporarily build a one-segment table
of the correct format on the stack, then use TBL with stack relative indexed addressing
to interpolate. The most difficult part of the routine is calculating the proportional distance from the beginning of the segment to the lookup point versus the width of the
segment ((XL–XB)/(XE–XB)). With this type of table, this calculation must be done at
run time. In the previous type of table, this proportional term is an inherent part (the
lowest order bits) of the data input to the table.
Some fuzzy theorists have suggested membership functions should be shaped like
normal distribution curves or other mathematical functions. This may be correct, but
the processing requirements to solve for an intercept on such a function would be unacceptable for most microcontroller-based fuzzy systems. Such a function could be
encoded into a table of one of the previously described types.
For many common systems, the thing that is most important about membership function shape is that there is a gradual transition from non-membership to membership
as the system input value approaches the central range of the membership function.
Let us examine the human problem of stopping a car at an intersection. We might use
rules like “If intersection is close and speed is fast, apply brakes.” The meaning (reflected in membership function shape and position) of the labels “close” and “fast” will
be different for a teenager than they are for a grandmother, but both can accomplish
the goal of stopping. It makes intuitive sense that the exact shape of a membership
function is much less important than the fact that it has gradual boundaries.
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9.7.2 Rule Evaluation Variations
The REV and REVW instructions expect fuzzy input and fuzzy output values to be 8bit values. In a custom fuzzy inference program, higher resolution may be desirable
(although this is not a common requirement). The CPU12 includes variations of minimum and maximum operations that work with the fuzzy MIN-MAX inference algorithm.
The problem with the fuzzy inference algorithm is that the min and max operations
need to store their results differently, so the min and max instructions must work differently or more than one variation of these instructions is needed.
The CPU12 has min and max instructions for 8- or 16-bit operands, where one operand is in an accumulator and the other is a referenced memory location. There are
separate variations that replace the accumulator or the memory location with the result. While processing rule antecedents in a fuzzy inference program, a reference value must be compared to each of the referenced fuzzy inputs, and the smallest input
must end up in an accumulator. The instruction…
EMIND
2,X+
;process one rule antecedent
automates the central operations needed to process rule antecedents. The E stands
for extended, so this instruction compares 16-bit operands. The D at the end of the
mnemonic stands for the D accumulator, which is both the first operand for the comparison and the destination of the result. The 2,X+ is an indexed addressing specification that says X points to the second operand for the comparison.
When processing rule consequents, the operand in the accumulator must remain constant (in case there is more than one consequent in the rule), and the result of the comparison must replace the referenced fuzzy output in RAM. To do this, use the
instruction…
EMAXM
2,X+
;process one rule consequent
The M at the end of the mnemonic indicates that the result will replace the referenced
memory operand. Again, indexed addressing is used. These two instructions would
form the working part of a 16-bit resolution fuzzy inference routine.
There are many other methods of performing inference, but none of these are as widely used as the min-max method. Since the CPU12 is a general-purpose microcontroller, the programmer has complete freedom to program any algorithm desired. A
custom programmed algorithm would typically take more code space and execution
time than a routine that used the built-in REV or REVW instructions.
9.7.3 Defuzzification Variations
There are two main areas where other CPU12 instructions can help with custom defuzzification routines. The first case is working with operands that are more than eight
bits. The second case involves using an entirely different approach than weighted average of singletons.
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The primary part of the WAV instruction is a multiply and accumulate operation to get
the numerator for the weighted average calculation. When working with operands as
large as 16 bits, the EMACS instruction could at least be used to automate the multiply
and accumulate function. The CPU12 has extended math capabilities, including the
EMACS instruction which uses 16-bit input operands and accumulates the sum to a
32-bit memory location and 32-bit by 16-bit divide instructions.
One benefit of the WAV instruction is that both a sum of products and a sum of weights
are maintained, while the fuzzy output operand is only accessed from memory once.
Since memory access time is such a significant part of execution time, this provides a
speed advantage compared to conventional instructions.
The weighted average of singletons is the most commonly used technique in microcontrollers because it is computationally less difficult than most other methods. The
simplest method is called max defuzzification, which simply uses the largest fuzzy output as the system result. However, this approach does not take into account any other
fuzzy outputs, even when they are almost as true as the chosen max output. Max defuzzification is not a good general choice because it only works for a subset of fuzzy
logic applications.
The CPU12 is well suited for more computationally challenging algorithms than
weighted average. A 32-bit by 16-bit divide instruction takes eleven or twelve 8-MHz
cycles for unsigned or signed variations. A 16-bit by 16-bit multiply with a 32-bit result
takes only three 8-MHz cycles. The EMACS instruction uses 16-bit operands and
accumulates the result in a 32-bit memory location, taking only twelve 8-MHz cycles
per iteration, including accessing all operands from memory and storing the result to
memory.
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SECTION 10
MEMORY EXPANSION
This section discusses expansion memory principles that apply to the entire M68HC12
family. Some family devices do not have memory expansion capabilities, and the size
of the expanded memory can also vary. Please refer to the documentation for a derivative to determine details of implementation.
10.1 Expansion System Description
Certain members of the M68HC12 family incorporate hardware that supports addressing a larger memory space than the standard 64 Kbytes. The expanded memory system uses fast on-chip logic to implement a transparent paged memory or bankswitching scheme.
Increased code efficiency is the greatest advantage of using bank switching instead of
implementing a large linear address space. In systems with large linear address spaces, instructions require more bits of information to address a memory location, and
CPU overhead is greater. Other advantages of bank switching include the ability to
change the size of system memory, and the ability to use various types of external
memory.
However, the add-on bank switching schemes used in other microcontrollers have
known weaknesses. These include the cost of external glue logic, increased programming overhead to change banks, and the need to disable interrupts while banks are
switched.
The M68HC12 system requires no external glue logic. Bank switching overhead is reduced by implementing control logic in the MCU. Interrupts do not need to be disabled
during switching because switching tasks are incorporated in special instructions that
greatly simplify program access to extended memory. Operation of the bank-switching
logic is transparent to the CPU.
The CPU12 has a linear 64-Kbyte address space. All MCU system resources, including control registers for on-chip peripherals and on-chip memory arrays, are mapped
into this space. In a typical M68HC12 derivative, the resources have default addresses
out of reset, but can be re-mapped to other addresses by means of control registers
in the on-chip integration module.
Memory expansion control logic is outside the CPU. A block of circuitry in the MCU
integration module manages overlays that occupy pre-defined locations in the 64Kbyte space addressed by the CPU. These overlays can be thought of as windows
through which the CPU accesses information in the expanded memory space.
There are three overlay windows. The program window expands program memory,
the data window is used for independent data expansion, and the extra window expands access to special types of memory such as EEPROM. The program window always occupies the 16-Kbyte space from $8000 to $BFFF. Data and extra windows can
vary in size and location.
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Each window has an associated page select register that selects external memory
pages to be accessed via the window. Only one page at a time can occupy a window;
the value in the register must be changed to access a different page of memory. With
8-bit registers, there can be up to 256 expansion pages per window, each page the
same size as the window.
For data and extra windows, page switching is accomplished by means of normal read
and write instructions. This is the traditional method of managing a bank-switching
system. The CPU12 CALL and RTC instructions automatically manipulate the program page select (PPAGE) register for the program window.
In M68HC12 expanded memory systems, control registers, vector spaces, and a portion of on-chip memory are located in unpaged portions of the 64-Kbyte address
space. The stack and I/O addresses should also be placed in unpaged memory to
make them accessible from any overlay page.
The initial portions of exception handlers must be located in unpaged memory because the 16-bit exception vectors cannot point to addresses in paged memory. However, service routines can call other routines in paged memory. The upper 16-Kbyte
block of memory space ($C000–$FFFF) is unpaged. It is recommended that all reset
and interrupt vectors point to locations in this area.
Although internal MCU resources, such as control registers and on-chip memory, have
default addresses out of reset, each can typically be relocated by changing the default
values in control registers. Normally, I/O addresses, control registers, vector spaces,
overlay windows, and on-chip memory are not mapped so that their respective address ranges overlap. However, there is an access priority order that prevents access
conflicts should such overlaps occur. Table 10-1 shows the mapping precedence. Resources with higher precedence block access to those with a lower precedence. The
windows have lowest priority — registers, exception vectors, and on-chip memory are
always visible to a program regardless of the values in the page select registers.
Table 10-1 Mapping Precedence
Precedence
Resource
1
Registers
2
Exception Vectors/BDM ROM
3
RAM
4
EEPROM
5
Flash
6
Expansion Windows
When background debugging is enabled and active, the CPU executes code located
in a small on-chip ROM mapped to addresses $FF20 to $FFFF, and BDM control registers are accessible at addresses $FF00 to $FF06. The BDM ROM replaces the regular system vectors while BDM is active, but BDM resources are not in the memory
map during normal execution of application programs.
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10.2 CALL and Return from Call Instructions
The CALL is similar to a JSR instruction, but the subroutine that is called can be located anywhere in the normal 64-Kbyte address space, or on any page of program expansion memory. When CALL is executed, a return address is calculated, then it and
the current program page register value are stacked, and a new instruction-supplied
value is written to PPAGE. The PPAGE value controls which of the 256 possible pages
is visible through the 16-Kbyte window in the 64-Kbyte memory map. Execution continues at the address of the called subroutine.
The actual sequence of operations that occur during execution of CALL is:
•
The CPU reads the old PPAGE value into an internal temporary register, and
writes the new instruction-supplied PPAGE value to PPAGE. This switches the
destination page into the program overlay window.
• The CPU calculates the address of the next instruction after the CALL instruction (the return address), and pushes this 16-bit value onto the stack.
• The old 8-bit PPAGE value is pushed onto the stack.
• The effective address of the subroutine is calculated, the queue is refilled, and
execution begins at the new address.
This sequence of operations is an uninterruptable CPU instruction. There is no need
to inhibit interrupts during CALL execution. In addition, a CALL can be performed from
any address in memory to any other address. This is a big improvement over other
bank-switching schemes, where the page switch operation can only be performed by
a program outside the overlay window.
For all practical purposes, the PPAGE value supplied by the instruction can be considered to be part of the effective address. For all addressing mode variations except indexed indirect modes, the new page value is provided by an immediate operand in the
instruction. For indexed indirect variations of CALL, a pointer specifies memory locations where the new page value and the address of the called subroutine are stored.
Use of indirect addressing for both the new page value and the address within the
page allows use run-time calculated values rather than immediate values that must be
known at the time of assembly.
The RTC instruction is used to terminate subroutines invoked by a CALL instruction.
RTC unstacks the PPAGE value and the return address, the queue is refilled, and execution resumes with the next instruction after the corresponding CALL.
The actual sequence of operations that occur during execution of RTC is:
• The return value of the 8-bit PPAGE register is pulled from the stack.
• The 16-bit return address is pulled from the stack and loaded into the PC.
• The return PPAGE value is written to the PPAGE register.
• The queue is refilled, and execution begins at the new address.
Since the return operation is implemented as a single uninterruptable CPU instruction,
the RTC can be executed from anywhere in memory, including from a different page
of extended memory in the overlay window.
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MEMORY EXPANSION
MOTOROLA
10-3
In an MCU where there is no memory expansion, the CALL and RTC instructions still
perform the same sequence of operations, but there is no PPAGE register or address
translation logic. The value the CPU reads when the PPAGE register is accessed is
indeterminate but doesn’t matter, because the value is not involved in addressing
memory in the unpaged 64-Kbyte memory map. When the CPU writes to the non-existent PPAGE register, nothing happens.
The CALL and RTC instructions behave like JSR and RTS, except they have slightly
longer execution times. Since extra execution cycles are required, routinely substituting CALL/RTC for JSR/RTS is not recommended. JSR and RTS can be used to access subroutines that are located on the same memory page. However, if a subroutine
can be called from other pages, it must be terminated with an RTC. In this case, since
RTC unstacks the PPAGE value as well as the return address, all accesses to the subroutine, even those made from the same page, must use CALL instructions.
10.3 Address Lines for Expansion Memory
All M68HC12 family members have at least 16 address lines, ADDR[15:0]. Devices
with memory expansion capability can have as many as six additional high-order external address lines, ADDR[21:16]. Each of these additional address lines is typically
associated with a control bit that allows address expansion to be selectively enabled.
When expansion is enabled, internal address translation circuitry multiplexes data
from the page select registers onto the high order address lines when there is an access to an address in a corresponding expansion window.
Assume that a device has six expansion address lines and an 8-bit PPAGE register.
The lines and the program expansion window have been enabled. The address $9000
is within the 16-Kbyte program overlay window. When there is an access to this address, the value in the PPAGE register is multiplexed onto external address lines ADDR[21:14]. The 14 low-order address lines select a location within the program overlay
page. Up to 256 16-Kbyte pages (4 Mbytes) of memory can be accessed through the
window. When there is an access to a location that is not within any enabled overlay
window, ADDR[21:16] are driven to logic level one.
The address translation logic can produce the same address on the external address
lines for two different internal addresses. For example, the 22-bit address $3FFFFF
could result from an internal access to $FFFF in the 64-Kbyte memory map, or to the
last location ($BFFF) within page 255 (PPAGE = $FF) of the program overlay window.
Considering only the 22 external address lines, the last physical page of the program
overlay appears to occupy the same address space as the unpaged 16-Kbyte block
from $C000 to $FFFF of the 64-Kbyte memory map. Using MCU chip-select circuits to
enable external memory can resolve these ambiguities.
10.4 Overlay Window Controls
There is a page select register associated with each overlay window. PPAGE holds
the page select for the program overlay, DPAGE holds the page select for the data
overlay, and EPAGE holds the page select for the extra page. The CPU12 manipulates the PPAGE register directly, so it will always be eight bits or less in devices that
MOTOROLA
10-4
MEMORY EXPANSION
CPU12
REFERENCE MANUAL
support program memory expansion. The DPAGE and EPAGE registers are not controlled by dedicated CPU12 instructions. These registers can be larger or smaller than
eight bits in various M68HC12 derivatives.
Typically, each of the overlay windows also has an associated control bit to enable
memory expansion through the appropriate window. Memory expansion is generally
disabled out of reset, so control bits must be written to enable the address translation
logic.
10.5 Using Chip-Select Circuits
M68HC12 chip-select circuits can be used to preclude ambiguities in memory-mapping due to the operation of internal address translation logic. If built-in chip selects are
not used, take care to use only overlay pages which produce unique addresses on the
external address lines.
M68HC12 derivatives typically have two or more chip-select circuits. Chip-select function is conceptually simple. Whenever an access to a pre-defined range of addresses
is made, internal MCU circuitry detects an address match and asserts a control signal
that can be used to enable external devices. Chip-select circuits typically incorporate
a number of options that make it possible to use more than one range of addresses
for matches as well as to enable various types and configurations of external devices.
Chip-select circuits used in conjunction with the memory-expansion scheme must be
able to match all accesses made to addresses within the appropriate program overlay
window. In the case of the program expansion window, the range of addresses occupies the 16-Kbyte space from $8000 to $BFFF. For data and extra expansion windows, the range of addresses varies from device to device. The following paragraphs
discuss a typical implementation of memory expansion chip-select functions in the
system integration module. Implementation will vary from device to device within the
M68HC12 family. Please refer to the appropriate device manual for details.
10.5.1 Program Memory Expansion Chip-Select Controls
There are two program memory expansion chip-select circuits, CSP0 and CSP1. The
associated control register contains eight control bits that provide for a number of system configurations.
10.5.1.1 CSP1E Control Bit
Enables (1) or disables (0) the CSP1 chip select. The default is disabled.
10.5.1.2 CSP0E Control Bit
Enables (1) or disables (0) the CSP0 chip select. The default is enabled. This allows
CSP0 to be used to select an external memory that includes the reset vector and startup initialization programs.
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MOTOROLA
10-5
10.5.1.3 CSP1FL Control Bit
Configures CSP1 to occupy all of the 64-Kbyte memory map that is not used by a higher-priority resource. If CSP1FL = 0, CSP1 is mapped to the area from $8000 to $FFFF.
CSP1 has the lowest access priority except for external memory space that is not associated with any chip select.
10.5.1.4 CSPA21 Control Bit
Logic one causes CSP0 and CSP1 to be controlled by the ADDR21 signal. CSP1 is
active when ADDR21 = 0, and CSP0 is active when ADDR21 = 1. When CSPA21 is
one, the CSP1FL bit is ignored and both CSP0 and CSP1 are active in the region
$8000–$FFFF. When CSPA21 is zero, CSP0 and CSP1 operate independently from
the value of the ADDR21 signal.
10.5.1.5 STRP0A:STRP0B Control Field
These two bits program an extra delay into accesses to the CSP0 area of memory.
The choices are 0, 1, 2, or 3 E-cycles in addition to the normal one cycle for unstretched accesses. This allows use of slow external memory without slowing down
the entire system.
10.5.1.6 STRP1A:STRP1B Control Field
These two bits program an extra delay into accesses to the CSP1 area of memory.
The choices are 0, 1, 2, or 3 E-cycles in addition to the normal one cycle for unstretched accesses. This allows use of slow external memory without slowing down
the entire system.
When enabled, CSP0 is active for the memory space from $8000 through $FFFF. This
includes the program overlay space ($8000–$BFFF) and the unpaged 16-Kbyte block
from $C000 through $FFFF. This configuration can be used if there is a single program
memory device (up to four Mbytes) in the system.
If CSP1 is also enabled and the CSPA21 bit is set, CSP1 can be used to select the
first 128 16-Kbyte pages (two Mbytes) in the program overlay expansion memory
space while CSP0 selects the higher numbered program expansion pages and the
unpaged block from $C000 through $FFFF. Recall that the external memory device
cannot distinguish between an access to the $C000 to $FFFF space and an access to
$8000–$BFFF in the 255th page (PPAGE = $FF) of the program overlay window.
10.5.2 Data Expansion Chip Select Controls
The data chip select (CSD) has four associated control bits.
10.5.2.1 CSDE Control Bit
Enables (1) or disables (0) the CSD chip select. The default is disabled.
MOTOROLA
10-6
MEMORY EXPANSION
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REFERENCE MANUAL
10.5.2.2 CSDHF Control Bit
Configures CSD to occupy the lower half of the 64-Kbyte memory map (for areas that
are not used by a higher priority resource). If CSDHF is zero, CSD occupies the range
of addresses used by the data expansion window.
10.5.2.3 STRDA:STRDB Control Field
These two bits program an extra delay into accesses to the CSD area of memory. The
choices are 0, 1, 2, or 3 additional E-cycles in addition to the normal one cycle for unstretched accesses. This allows use of slow external memory without slowing down
the entire system.
10.5.3 Extra Expansion Chip Select Controls
The extra chip select (CSE) has four associated control bits.
10.5.3.1 CSEE Control Bit
Enables (1) or disables (0) the CSE chip select. The default is disabled.
10.5.3.2 CSEEP Control Bit
Logic one configures CSE to be active for the EPAGE area. A logic zero causes CSE
to be active for the CS3 area of the internal register space, which can typically be
remapped to any 2-Kbyte boundary.
10.5.3.3 STREA:STREB Control Field
These two bits program an extra delay into accesses to the CSE area of memory. The
choices are 0, 1, 2, or 3 E-cycles in addition to the normal one cycle for unstretched
accesses. This allows use of slow external memory without slowing down the entire
system.
To use CSE with the extra overlay window, it must be enabled (CSEE = 1) and configured to follow the extra page (CSEEP = 1).
10.6 System Notes
The expansion overlay windows are specialized for specific application uses, but there
are no restrictions on the use of these memory spaces. Motorola MCUs have a memory-mapped architecture in which all memory resources are treated equally. Although
it is possible to execute programs in paged external memory in the data and extra
overlay areas, it is less convenient than using the program overlay area.
The CALL and RTC instructions automate the program page switching functions in an
uninterruptable instruction. For the data and extra overlay windows, the user must take
care not to let interrupts corrupt the page switching sequence or change the active
page while executing out of another page in the same overlay area.
Internal MCU chip-select circuits have access to all 16 internal CPU address lines and
the overlay window select lines. This allows all 256 expansion pages in an overlay window to be distinguished from unpaged memory locations with 22-bit addresses that
are the same as addresses in overlay pages.
CPU12
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MEMORY EXPANSION
MOTOROLA
10-7
MOTOROLA
10-8
MEMORY EXPANSION
CPU12
REFERENCE MANUAL
APPENDIX A
INSTRUCTION REFERENCE
A.1 Instruction Set Summary
Table A-1 is a quick reference to the CPU12 instruction set. The table shows source
form, describes the operation performed, lists the addressing modes used, gives machine encoding in hexadecimal form, and describes the effect of execution on the condition code bits.
A.2 Opcode Map
Table A-2 displays the mnemonic, opcode, addressing mode, and cycle count for
each instruction. The first table represents those opcodes with no prebyte. The second
page of the table represents those opcodes with a prebyte value of $18. Notice the first
hexadecimal digit of the opcode (shown in the upper left corner of each cell) corresponds to column location, while the second hexadecimal digit of the opcode corresponds to row location.
A.3 Indexed Addressing Postbyte Encoding
Table A-5 shows postbyte encoding for indexed addressing modes. The mnemonic
for the indexed addressing mode postbyte is xb. This is also the notation used in instruction glossary entries. Table A-3 presents the same information in two-digit hexadecimal format. The first digit of the postbyte is represented by the value of the
columns in the table. The second digit of the postbyte is represented by the value of
the row.
A.4 Transfer and Exchange Postbyte Encoding
Table A-4 shows postbyte encoding for transfer and exchange instructions. The mnemonic for the transfer and exchange postbyte is eb. This is also the notation used in
instruction glossary entries. The first digit of the instruction postbyte is related to the
columns of the table. The second digit of the postbyte is related to the rows. The body
of the table shows actions caused by the postbyte.
A.5 Loop Primitive Postbyte Encoding
Table A-6 shows postbyte encoding for loop primitive instructions. The mnemonic for
the loop primitive postbyte is lb. This is also the notation used in instruction glossary
entries. The loop primitive instructions are DBEQ, DBNE, IBEQ, IBNE, TBEQ, and
TBNE. The first digit of the instruction postbyte corresponds to the columns of the table. The second digit of the postbyte corresponds to the rows. The body of the table
shows actions caused by the postbyte.
CPU12
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INSTRUCTION REFERENCE
MOTOROLA
A-1
Table A-1 Instruction Set Summary
Source
Form
Operation
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
ABA
(A) + (B) ⇒ A
Add Accumulators A and B
INH
18 06
2
–
–
∆
–
∆
∆
∆
∆
ABX
(B) + (X) ⇒ X
Translates to LEAX B,X
IDX
1A E5
2
–
–
–
–
–
–
–
–
ABY
(B) + (Y) ⇒ Y
Translates to LEAY B,Y
IDX
19 ED
2
–
–
–
–
–
–
–
–
ADCA opr
(A) + (M) + C ⇒ A
Add with Carry to A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
89 ii
99 dd
B9 hh ll
A9 xb
A9 xb ff
A9 xb ee ff
A9 xb
A9 xb ee ff
1
3
3
3
3
4
6
6
–
–
∆
–
∆
∆
∆
∆
ADCB opr
(B) + (M) + C ⇒ B
Add with Carry to B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C9 ii
D9 dd
F9 hh ll
E9 xb
E9 xb ff
E9 xb ee ff
E9 xb
E9 xb ee ff
1
3
3
3
3
4
6
6
–
–
∆
–
∆
∆
∆
∆
ADDA opr
(A) + (M) ⇒ A
Add without Carry to A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8B ii
9B dd
BB hh ll
AB xb
AB xb ff
AB xb ee ff
AB xb
AB xb ee ff
1
3
3
3
3
4
6
6
–
–
∆
–
∆
∆
∆
∆
ADDB opr
(B) + (M) ⇒ B
Add without Carry to B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CB ii
DB dd
FB hh ll
EB xb
EB xb ff
EB xb ee ff
EB xb
EB xb ee ff
1
3
3
3
3
4
6
6
–
–
∆
–
∆
∆
∆
∆
ADDD opr
(A:B) + (M:M+1) ⇒ A:B
Add 16-Bit to D (A:B)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C3 jj kk
D3 dd
F3 hh ll
E3 xb
E3 xb ff
E3 xb ee ff
E3 xb
E3 xb ee ff
2
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
MOTOROLA
A-2
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
Table A-1 Instruction Set Summary (Continued)
Source
Form
Addr.
Mode
Operation
Machine
Coding (hex)
~*
S X H I N Z V C
ANDA opr
(A) • (M) ⇒ A
Logical And A with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
84 ii
94 dd
B4 hh ll
A4 xb
A4 xb ff
A4 xb ee ff
A4 xb
A4 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
ANDB opr
(B) • (M) ⇒ B
Logical And B with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C4 ii
D4 dd
F4 hh ll
E4 xb
E4 xb ff
E4 xb ee ff
E4 xb
E4 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
ANDCC opr
(CCR) • (M) ⇒ CCR
Logical And CCR with Memory
10 ii
1
⇓
⇓
⇓ ⇓ ⇓
⇓
⇓
⇓
78 hh ll
68 xb
68 xb ff
68 xb ee ff
68 xb
68 xb ee ff
48
58
4
3
4
5
6
6
1
1
–
–
–
–
∆
∆
∆
∆
59
1
–
–
–
–
∆
∆
∆
∆
77 hh ll
67 xb
67 xb ff
67 xb ee ff
67 xb
67 xb ee ff
47
57
4
3
4
5
6
6
1
1
–
–
–
–
∆
∆
∆
∆
3/1
–
–
–
–
–
–
–
–
4
4
4
4
6
–
–
–
–
∆
∆
0
–
IMM
ASL opr
0
C
b0
b7
Arithmetic Shift Left
ASLA
ASLB
Arithmetic Shift Left Accumulator A
Arithmetic Shift Left Accumulator B
ASLD
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
INH
0
C
b7 A
b0
b7
b0
B
Arithmetic Shift Left Double
ASR opr
b0
b7
Arithmetic Shift Right
C
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
ASRA
ASRB
Arithmetic Shift Right Accumulator A
Arithmetic Shift Right Accumulator B
BCC rel
Branch if Carry Clear (if C = 0)
REL
24 rr
BCLR opr, msk
(M) • (mm) ⇒ M
Clear Bit(s) in Memory
DIR
EXT
IDX
IDX1
IDX2
4D dd mm
1D hh ll mm
0D xb mm
0D xb ff mm
0D xb ee ff mm
BCS rel
Branch if Carry Set (if C = 1)
REL
25 rr
3/1
–
–
–
–
–
–
–
–
BEQ rel
Branch if Equal (if Z = 1)
REL
27 rr
3/1
–
–
–
–
–
–
–
–
BGE rel
Branch if Greater Than or Equal
(if N ⊕ V = 0) (signed)
REL
2C rr
3/1
–
–
–
–
–
–
–
–
BGND
Place CPU in Background Mode
see Background Mode section.
INH
00
5
–
–
–
–
–
–
–
–
BGT rel
Branch if Greater Than
(if Z ✛ (N ⊕ V) = 0) (signed)
REL
2E rr
3/1
–
–
–
–
–
–
–
–
BHI rel
Branch if Higher
(if C ✛ Z = 0) (unsigned)
REL
22 rr
3/1
–
–
–
–
–
–
–
–
CPU12
REFERENCE MANUAL
INSTRUCTION REFERENCE
MOTOROLA
A-3
Table A-1 Instruction Set Summary (Continued)
Source
Form
Operation
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
3/1
–
–
–
–
–
–
–
–
BHS rel
Branch if Higher or Same
(if C = 0) (unsigned)
same function as BCC
BITA opr
(A) • (M)
Logical And A with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
85 ii
95 dd
B5 hh ll
A5 xb
A5 xb ff
A5 xb ee ff
A5 xb
A5 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
BITB opr
(B) • (M)
Logical And B with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C5 ii
D5 dd
F5 hh ll
E5 xb
E5 xb ff
E5 xb ee ff
E5 xb
E5 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
BLE rel
Branch if Less Than or Equal
(if Z ✛ (N ⊕ V) = 1) (signed)
REL
2F rr
3/1
–
–
–
–
–
–
–
–
BLO rel
Branch if Lower
(if C = 1) (unsigned)
same function as BCS
REL
25 rr
3/1
–
–
–
–
–
–
–
–
BLS rel
Branch if Lower or Same
(if C ✛ Z = 1) (unsigned)
REL
23 rr
3/1
–
–
–
–
–
–
–
–
BLT rel
Branch if Less Than
(if N ⊕ V = 1) (signed)
REL
2D rr
3/1
–
–
–
–
–
–
–
–
BMI rel
Branch if Minus (if N = 1)
REL
2B rr
3/1
–
–
–
–
–
–
–
–
BNE rel
Branch if Not Equal (if Z = 0)
REL
26 rr
3/1
–
–
–
–
–
–
–
–
BPL rel
Branch if Plus (if N = 0)
REL
2A rr
3/1
–
–
–
–
–
–
–
–
BRA rel
Branch Always (if 1 = 1)
REL
20 rr
3
–
–
–
–
–
–
–
–
BRCLR
Branch if (M) • (mm) = 0
opr, msk, rel (if All Selected Bit(s) Clear)
DIR
EXT
IDX
IDX1
IDX2
4F dd mm rr
1F hh ll mm rr
0F xb mm rr
0F xb ff mm rr
0F xb ee ff mm rr
4
5
4
6
8
–
–
–
–
–
–
–
–
BRN rel
REL
21 rr
1
–
–
–
–
–
–
–
–
DIR
EXT
IDX
IDX1
IDX2
4E dd mm rr
1E hh ll mm rr
0E xb mm rr
0E xb ff mm rr
0E xb ee ff mm rr
4
5
4
6
8
–
–
–
–
–
–
–
–
REL
Branch Never (if 1 = 0)
BRSET
Branch if (M) • (mm) = 0
opr, msk, rel (if All Selected Bit(s) Set)
24 rr
BSET opr, msk
(M) ✛ (mm) ⇒ M
Set Bit(s) in Memory
DIR
EXT
IDX
IDX1
IDX2
4C dd mm
1C hh ll mm
0C xb mm
0C xb ff mm
0C xb ee ff mm
4
4
4
4
6
–
–
–
–
∆
∆
0
–
BSR rel
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1)
Subroutine address ⇒ PC
REL
07 rr
4
–
–
–
–
–
–
–
–
Branch to Subroutine
MOTOROLA
A-4
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
Table A-1 Instruction Set Summary (Continued)
Source
Form
Operation
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
BVC rel
Branch if Overflow Bit Clear (if V = 0)
REL
28 rr
3/1
–
–
–
–
–
–
–
BVS rel
Branch if Overflow Bit Set (if V = 1)
REL
29 rr
3/1
–
–
–
–
–
–
–
–
CALL opr, page
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1)
(SP) – 1 ⇒ SP;
(PPG) ⇒ M(SP);
pg ⇒ PPAGE register;
Program address ⇒ PC
EXT
IDX
IDX1
IDX2
4A hh ll pg
4B xb pg
4B xb ff pg
4B xb ee ff pg
8
8
8
9
–
–
–
–
–
–
–
–
4B xb
4B xb ee ff
10
10
–
–
–
–
–
–
–
–
–
Call subroutine in extended memory
(Program may be located on another
expansion memory page.)
CALL [D,r]
CALL [opr,r]
Indirect modes get program address
and new pg value based on pointer.
CBA
(A) – (B)
Compare 8-Bit Accumulators
INH
18 17
2
–
–
–
–
∆
∆
∆
∆
CLC
0⇒C
Translates to ANDCC #$FE
IMM
10 FE
1
–
–
–
–
–
–
–
0
CLI
0⇒I
Translates to ANDCC #$EF
(enables I-bit interrupts)
IMM
10 EF
1
–
–
–
0
–
–
–
–
CLR opr
0⇒M
Clear Memory Location
–
–
–
0
1
0
0
0⇒A
0⇒B
Clear Accumulator A
Clear Accumulator B
3
2
3
3
5
5
1
1
–
CLRA
CLRB
79 hh ll
69 xb
69 xb ff
69 xb ee ff
69 xb
69 xb ee ff
87
C7
CLV
0⇒V
Translates to ANDCC #$FD
10 FD
1
–
–
–
–
–
–
0
–
CMPA opr
(A) – (M)
Compare Accumulator A with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
81 ii
91 dd
B1 hh ll
A1 xb
A1 xb ff
A1 xb ee ff
A1 xb
A1 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
CMPB opr
(B) – (M)
Compare Accumulator B with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C1 ii
D1 dd
F1 hh ll
E1 xb
E1 xb ff
E1 xb ee ff
E1 xb
E1 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
[D,IDX]
[IDX2]
r = X, Y, SP, or PC
CPU12
REFERENCE MANUAL
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
IMM
INSTRUCTION REFERENCE
MOTOROLA
A-5
Table A-1 Instruction Set Summary (Continued)
Source
Form
Operation
COM opr
(M) ⇒ M equivalent to $FF – (M) ⇒ M
1’s Complement Memory Location
COMA
COMB
(A) ⇒ A Complement Accumulator A
(B) ⇒ B Complement Accumulator B
CPD opr
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
71 hh ll
61 xb
61 xb ff
61 xb ee ff
61 xb
61 xb ee ff
41
51
4
3
4
5
6
6
1
1
–
–
–
–
∆
∆
0
1
(A:B) – (M:M+1)
Compare D to Memory (16-Bit)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8C jj kk
9C dd
BC hh ll
AC xb
AC xb ff
AC xb ee ff
AC xb
AC xb ee ff
2
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
CPS opr
(SP) – (M:M+1)
Compare SP to Memory (16-Bit)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8F jj kk
9F dd
BF hh ll
AF xb
AF xb ff
AF xb ee ff
AF xb
AF xb ee ff
2
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
CPX opr
(X) – (M:M+1)
Compare X to Memory (16-Bit)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8E jj kk
9E dd
BE hh ll
AE xb
AE xb ff
AE xb ee ff
AE xb
AE xb ee ff
2
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
CPY opr
(Y) – (M:M+1)
Compare Y to Memory (16-Bit)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8D jj kk
9D dd
BD hh ll
AD xb
AD xb ff
AD xb ee ff
AD xb
AD xb ee ff
2
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
DAA
Adjust Sum to BCD
Decimal Adjust Accumulator A
INH
18 07
3
–
–
–
–
∆
∆
?
∆
DBEQ cntr, rel
(cntr) – 1⇒ cntr
if (cntr) = 0, then Branch
else Continue to next instruction
REL
(9-bit)
04 lb rr
3
–
–
–
–
–
–
–
–
REL
(9-bit)
04 lb rr
3
–
–
–
–
–
–
–
–
Decrement Counter and Branch if = 0
(cntr = A, B, D, X, Y, or SP)
DBNE cntr, rel
(cntr) – 1 ⇒ cntr
If (cntr) not = 0, then Branch;
else Continue to next instruction
Decrement Counter and Branch if ≠ 0
(cntr = A, B, D, X, Y, or SP)
MOTOROLA
A-6
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
Table A-1 Instruction Set Summary (Continued)
Source
Form
Operation
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
73 hh ll
63 xb
63 xb ff
63 xb ee ff
63 xb
63 xb ee ff
43
53
4
3
4
5
6
6
1
1
–
–
–
–
∆
∆
∆
–
DEC opr
(M) – $01 ⇒ M
Decrement Memory Location
DECA
DECB
(A) – $01 ⇒ A
(B) – $01 ⇒ B
DES
(SP) – $0001 ⇒ SP
Translates to LEAS –1,SP
IDX
1B 9F
2
–
–
–
–
–
–
–
–
DEX
(X) – $0001 ⇒ X
Decrement Index Register X
INH
09
1
–
–
–
–
–
∆
–
–
DEY
(Y) – $0001 ⇒ Y
Decrement Index Register Y
INH
03
1
–
–
–
–
–
∆
–
–
EDIV
(Y:D) ÷ (X) ⇒ Y Remainder ⇒ D
32 × 16 Bit ⇒ 16 Bit Divide (unsigned)
INH
11
11
–
–
–
–
∆
∆
∆
∆
EDIVS
(Y:D) ÷ (X) ⇒ Y Remainder ⇒ D
32 × 16 Bit ⇒ 16 Bit Divide (signed)
INH
18 14
12
–
–
–
–
∆
∆
∆
∆
EMACS sum
(M(X):M(X+1)) × (M(Y):M(Y+1)) + (M~M+3) ⇒
M~M+3
Special
18 12 hh ll
13
–
–
–
–
∆
∆
∆
∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1A xb
18 1A xb ff
18 1A xb ee ff
18 1A xb
18 1A xb ee ff
4
4
5
7
7
–
–
–
–
∆
∆
∆
∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1E xb
18 1E xb ff
18 1E xb ee ff
18 1E xb
18 1E xb ee ff
4
5
6
7
7
–
–
–
–
∆
∆
∆
∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1B xb
18 1B xb ff
18 1B xb ee ff
18 1B xb
18 1B xb ee ff
4
4
5
7
7
–
–
–
–
∆
∆
∆
∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1F xb
18 1F xb ff
18 1F xb ee ff
18 1F xb
18 1F xb ee ff
4
5
6
7
7
–
–
–
–
∆
∆
∆
∆
Decrement A
Decrement B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
16 × 16 Bit ⇒ 32 Bit
Multiply and Accumulate (signed)
EMAXD opr
MAX((D), (M:M+1)) ⇒ D
MAX of 2 Unsigned 16-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((D) – (M:M+1))
EMAXM opr
MAX((D), (M:M+1)) ⇒ M:M+1
MAX of 2 Unsigned 16-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((D) – (M:M+1))
EMIND opr
MIN((D), (M:M+1)) ⇒ D
MIN of 2 Unsigned 16-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((D) – (M:M+1))
EMINM opr
MIN((D), (M:M+1)) ⇒ M:M+1
MIN of 2 Unsigned 16-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((D) – (M:M+1))
EMUL
(D) × (Y) ⇒ Y:D
16 × 16 Bit Multiply (unsigned)
INH
13
3
–
–
–
–
∆
∆
–
∆
EMULS
(D) × (Y) ⇒ Y:D
16 × 16 Bit Multiply (signed)
INH
18 13
3
–
–
–
–
∆
∆
–
∆
CPU12
REFERENCE MANUAL
INSTRUCTION REFERENCE
MOTOROLA
A-7
Table A-1 Instruction Set Summary (Continued)
Source
Form
Operation
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
EORA opr
(A) ⊕ (M) ⇒ A
Exclusive-OR A with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
88 ii
98 dd
B8 hh ll
A8 xb
A8 xb ff
A8 xb ee ff
A8 xb
A8 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
EORB opr
(B) ⊕ (M) ⇒ B
Exclusive-OR B with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C8 ii
D8 dd
F8 hh ll
E8 xb
E8 xb ff
E8 xb ee ff
E8 xb
E8 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
ETBL opr
(M:M+1)+ [(B)×((M+2:M+3) – (M:M+1))] ⇒ D
16-Bit Table Lookup and Interpolate
IDX
18 3F xb
10
–
–
–
–
∆
∆
–
?
INH
B7 eb
1
–
–
–
–
–
–
–
–
INH
18 11
12
–
–
–
–
–
∆
∆
∆
REL
(9-bit)
04 lb rr
3
–
–
–
–
–
–
–
–
REL
(9-bit)
04 lb rr
3
–
–
–
–
–
–
–
–
Initialize B, and index before ETBL.
<ea> points at first table entry (M:M+1)
and B is fractional part of lookup value
(no indirect addr. modes allowed)
EXG r1, r2
(r1) ⇔ (r2) (if r1 and r2 same size) or
$00:(r1) ⇒ r2 (if r1=8-bit; r2=16-bit) or
(r1low) ⇔ (r2) (if r1=16-bit; r2=8-bit)
r1 and r2 may be
A, B, CCR, D, X, Y, or SP
FDIV
(D) ÷ (X) ⇒ X; r ⇒ D
16 × 16 Bit Fractional Divide
IBEQ cntr, rel
(cntr) + 1⇒ cntr
If (cntr) = 0, then Branch
else Continue to next instruction
Increment Counter and Branch if = 0
(cntr = A, B, D, X, Y, or SP)
IBNE cntr, rel
(cntr) + 1⇒ cntr
if (cntr) not = 0, then Branch;
else Continue to next instruction
Increment Counter and Branch if ≠ 0
(cntr = A, B, D, X, Y, or SP)
IDIV
(D) ÷ (X) ⇒ X; r ⇒ D
16 × 16 Bit Integer Divide (unsigned)
INH
18 10
12
–
–
–
–
–
∆
0
∆
IDIVS
(D) ÷ (X) ⇒ X; r ⇒ D
16 × 16 Bit Integer Divide (signed)
INH
18 15
12
–
–
–
–
∆
∆
∆
∆
MOTOROLA
A-8
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
Table A-1 Instruction Set Summary (Continued)
Source
Form
Operation
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
72 hh ll
62 xb
62 xb ff
62 xb ee ff
62 xb
62 xb ee ff
42
52
4
3
4
5
6
6
1
1
–
–
–
–
∆
∆
∆
–
INC opr
(M) + $01 ⇒ M
Increment Memory Byte
INCA
INCB
(A) + $01 ⇒ A
(B) + $01 ⇒ B
INS
(SP) + $0001 ⇒ SP
Translates to LEAS 1,SP
IDX
1B 81
2
–
–
–
–
–
–
–
–
INX
(X) + $0001 ⇒ X
Increment Index Register X
INH
08
1
–
–
–
–
–
∆
–
–
INY
(Y) + $0001 ⇒ Y
Increment Index Register Y
INH
02
1
–
–
–
–
–
∆
–
–
JMP opr
Subroutine address ⇒ PC
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
06 hh ll
05 xb
05 xb ff
05 xb ee ff
05 xb
05 xb ee ff
3
3
3
4
6
6
–
–
–
–
–
–
–
–
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
17 dd
16 hh ll
15 xb
15 xb ff
15 xb ee ff
15 xb
15 xb ee ff
4
4
4
4
5
7
7
–
–
–
–
–
–
–
–
Increment Acc. A
Increment Acc. B
Jump
JSR opr
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1);
Subroutine address ⇒ PC
Jump to Subroutine
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
LBCC rel
Long Branch if Carry Clear (if C = 0)
REL
18 24 qq rr
4/3
–
–
–
–
–
–
–
–
LBCS rel
Long Branch if Carry Set (if C = 1)
REL
18 25 qq rr
4/3
–
–
–
–
–
–
–
–
LBEQ rel
Long Branch if Equal (if Z = 1)
REL
18 27 qq rr
4/3
–
–
–
–
–
–
–
–
LBGE rel
Long Branch Greater Than or Equal
(if N ⊕ V = 0) (signed)
REL
18 2C qq rr
4/3
–
–
–
–
–
–
–
–
LBGT rel
Long Branch if Greater Than
(if Z ✛ (N ⊕ V) = 0) (signed)
REL
18 2E qq rr
4/3
–
–
–
–
–
–
–
–
LBHI rel
Long Branch if Higher
(if C ✛ Z = 0) (unsigned)
REL
18 22 qq rr
4/3
–
–
–
–
–
–
–
–
LBHS rel
Long Branch if Higher or Same
(if C = 0) (unsigned)
same function as LBCC
REL
18 24 qq rr
4/3
–
–
–
–
–
–
–
–
LBLE rel
Long Branch if Less Than or Equal
(if Z ✛ (N ⊕ V) = 1) (signed)
REL
18 2F qq rr
4/3
–
–
–
–
–
–
–
–
LBLO rel
Long Branch if Lower
(if C = 1) (unsigned)
same function as LBCS
REL
18 25 qq rr
4/3
–
–
–
–
–
–
–
–
LBLS rel
Long Branch if Lower or Same
(if C ✛ Z = 1) (unsigned)
REL
18 23 qq rr
4/3
–
–
–
–
–
–
–
–
LBLT rel
Long Branch if Less Than
(if N ⊕ V = 1) (signed)
REL
18 2D qq rr
4/3
–
–
–
–
–
–
–
–
LBMI rel
Long Branch if Minus (if N = 1)
REL
18 2B qq rr
4/3
–
–
–
–
–
–
–
–
LBNE rel
Long Branch if Not Equal (if Z = 0)
REL
18 26 qq rr
4/3
–
–
–
–
–
–
–
–
LBPL rel
Long Branch if Plus (if N = 0)
REL
18 2A qq rr
4/3
–
–
–
–
–
–
–
–
LBRA rel
Long Branch Always (if 1=1)
REL
18 20 qq rr
4
–
–
–
–
–
–
–
–
CPU12
REFERENCE MANUAL
INSTRUCTION REFERENCE
MOTOROLA
A-9
Table A-1 Instruction Set Summary (Continued)
Source
Form
Operation
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
LBRN rel
Long Branch Never (if 1 = 0)
REL
18 21 qq rr
3
–
–
–
–
–
–
–
–
LBVC rel
Long Branch if Overflow Bit Clear (if V=0)
REL
18 28 qq rr
4/3
–
–
–
–
–
–
–
–
LBVS rel
Long Branch if Overflow Bit Set (if V = 1)
REL
18 29 qq rr
4/3
–
–
–
–
–
–
–
–
LDAA opr
(M) ⇒ A
Load Accumulator A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
86 ii
96 dd
B6 hh ll
A6 xb
A6 xb ff
A6 xb ee ff
A6 xb
A6 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
LDAB opr
(M) ⇒ B
Load Accumulator B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C6 ii
D6 dd
F6 hh ll
E6 xb
E6 xb ff
E6 xb ee ff
E6 xb
E6 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
LDD opr
(M:M+1) ⇒ A:B
Load Double Accumulator D (A:B)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CC jj kk
DC dd
FC hh ll
EC xb
EC xb ff
EC xb ee ff
EC xb
EC xb ee ff
2
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
LDS opr
(M:M+1) ⇒ SP
Load Stack Pointer
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CF jj kk
DF dd
FF hh ll
EF xb
EF xb ff
EF xb ee ff
EF xb
EF xb ee ff
2
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
LDX opr
(M:M+1) ⇒ X
Load Index Register X
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CE jj kk
DE dd
FE hh ll
EE xb
EE xb ff
EE xb ee ff
EE xb
EE xb ee ff
2
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
LDY opr
(M:M+1) ⇒ Y
Load Index Register Y
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CD jj kk
DD dd
FD hh ll
ED xb
ED xb ff
ED xb ee ff
ED xb
ED xb ee ff
2
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
LEAS opr
Effective Address ⇒ SP
Load Effective Address into SP
IDX
IDX1
IDX2
1B xb
1B xb ff
1B xb ee ff
2
2
2
–
–
–
–
–
–
–
–
MOTOROLA
A-10
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
Table A-1 Instruction Set Summary (Continued)
Source
Form
Addr.
Mode
Operation
Machine
Coding (hex)
~*
S X H I N Z V C
LEAX opr
Effective Address ⇒ X
Load Effective Address into X
IDX
IDX1
IDX2
1A xb
1A xb ff
1A xb ee ff
2
2
2
–
–
–
–
–
–
–
–
LEAY opr
Effective Address ⇒ Y
Load Effective Address into Y
IDX
IDX1
IDX2
19 xb
19 xb ff
19 xb ee ff
2
2
2
–
–
–
–
–
–
–
–
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
78 hh ll
68 xb
68 xb ff
68 xb ee ff
68 xb
68 xb ee ff
48
58
4
3
4
5
6
6
1
1
–
–
–
–
∆
∆
∆
∆
59
1
–
–
–
–
∆
∆
∆
∆
74 hh ll
64 xb
64 xb ff
64 xb ee ff
64 xb
64 xb ee ff
44
54
4
3
4
5
6
6
1
1
–
–
–
–
0
∆
∆
∆
49
1
–
–
–
–
0
∆
∆
∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 18 xb
18 18 xb ff
18 18 xb ee ff
18 18 xb
18 18 xb ee ff
4
4
5
7
7
–
–
–
–
∆
∆
∆
∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1C xb
18 1C xb ff
18 1C xb ee ff
18 1C xb
18 1C xb ee ff
4
5
6
7
7
–
–
–
–
∆
∆
∆
∆
Special
01
5
–
–
?
–
?
?
?
?
LSL opr
0
C
b0
b7
Logical Shift Left
same function as ASL
LSLA
LSLB
Logical Shift Accumulator A to Left
Logical Shift Accumulator B to Left
LSLD
INH
0
C
b7
A
b0
b7
B
b0
Logical Shift Left D Accumulator
same function as ASLD
LSR opr
0
b0
b7
C
Logical Shift Right
LSRA
LSRB
Logical Shift Accumulator A to Right
Logical Shift Accumulator B to Right
LSRD
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
INH
0
b7
A
b0
b7
B
b0
C
Logical Shift Right D Accumulator
MAXA
MAX((A), (M)) ⇒ A
MAX of 2 Unsigned 8-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((A) – (M)).
MAXM
MAX((A), (M)) ⇒ M
MAX of 2 Unsigned 8-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((A) – (M)).
MEM
µ (grade) ⇒ M(Y);
(X) + 4 ⇒ X; (Y) + 1 ⇒ Y; A unchanged
if (A) < P1 or (A) > P2 then µ = 0, else
µ = MIN[((A) – P1)×S1, (P2 – (A))×S2, $FF]
where:
A = current crisp input value;
X points at 4-byte data structure that describes a trapezoidal membership function
(P1, P2, S1, S2);
Y points at fuzzy input (RAM location).
See instruction details for special cases.
CPU12
REFERENCE MANUAL
INSTRUCTION REFERENCE
MOTOROLA
A-11
Table A-1 Instruction Set Summary (Continued)
Source
Form
MINA
Operation
MIN((A), (M)) ⇒ A
MIN of Two Unsigned 8-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((A) – (M)).
MINM
MIN((A), (M)) ⇒ M
MIN of Two Unsigned 8-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((A) – (M)).
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 19 xb
18 19 xb ff
18 19 xb ee ff
18 19 xb
18 19 xb ee ff
4
4
5
7
7
–
–
–
–
∆
∆
∆
∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1D xb
18 1D xb ff
18 1D xb ee ff
18 1D xb
18 1D xb ee ff
4
5
6
7
7
–
–
–
–
∆
∆
∆
∆
MOVB opr1, opr2 (M1) ⇒ M2
Memory to Memory Byte-Move (8-Bit)
IMM-EXT
IMM-IDX
EXT-EXT
EXT-IDX
IDX-EXT
IDX-IDX
18 0B ii hh ll
18 08 xb ii
18 0C hh ll hh ll
18 09 xb hh ll
18 0D xb hh ll
18 0A xb xb
4
4
6
5
5
5
–
–
–
–
–
–
–
–
MOVW opr1, opr2 (M:M+11) ⇒ M:M+12
Memory to Memory Word-Move (16-Bit)
IMM-EXT
IMM-IDX
EXT-EXT
EXT-IDX
IDX-EXT
IDX-IDX
18 03 jj kk hh ll
18 00 xb jj kk
18 04 hh ll hh ll
18 01 xb hh ll
18 05 xb hh ll
18 02 xb xb
5
4
6
5
5
5
–
–
–
–
–
–
–
–
12
3
–
–
–
–
–
–
–
∆
70 hh ll
60 xb
60 xb ff
60 xb ee ff
60 xb
60 xb ee ff
40
4
3
4
5
6
6
1
–
–
–
–
∆
∆
∆
∆
50
1
MUL
(A) × (B) ⇒ A:B
INH
8 × 8 Unsigned Multiply
NEG opr
0 – (M) ⇒ M or (M) + 1 ⇒ M
Two’s Complement Negate
NEGA
0 – (A) ⇒ A equivalent to (A) + 1 ⇒ B
Negate Accumulator A
0 – (B) ⇒ B equivalent to (B) + 1 ⇒ B
Negate Accumulator B
NEGB
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
NOP
No Operation
A7
1
–
–
–
–
–
–
–
–
ORAA opr
(A) ✛ (M) ⇒ A
Logical OR A with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8A ii
9A dd
BA hh ll
AA xb
AA xb ff
AA xb ee ff
AA xb
AA xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
ORAB opr
(B) ✛ (M) ⇒ B
Logical OR B with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CA ii
DA dd
FA hh ll
EA xb
EA xb ff
EA xb ee ff
EA xb
EA xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
0
–
ORCC opr
(CCR) ✛ M ⇒ CCR
Logical OR CCR with Memory
14 ii
1
⇑
–
⇑ ⇑ ⇑
⇑
⇑
⇑
MOTOROLA
A-12
INH
IMM
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
Table A-1 Instruction Set Summary (Continued)
Source
Form
PSHA
Operation
(SP) – 1 ⇒ SP; (A) ⇒ M(SP)
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
INH
36
2
–
–
–
–
–
–
–
–
INH
37
2
–
–
–
–
–
–
–
–
INH
39
2
–
–
–
–
–
–
–
–
INH
3B
2
–
–
–
–
–
–
–
–
INH
34
2
–
–
–
–
–
–
–
–
INH
35
2
–
–
–
–
–
–
–
–
INH
32
3
–
–
–
–
–
–
–
–
INH
33
3
–
–
–
–
–
–
–
–
INH
38
3
∆
⇓
∆ ∆ ∆
∆
∆
∆
INH
3A
3
–
–
–
–
–
–
–
–
INH
30
3
–
–
–
–
–
–
–
–
INH
31
3
–
–
–
–
–
–
–
–
3**
per
rule
byte
–
–
–
–
–
–
∆
–
Push Accumulator A onto Stack
PSHB
(SP) – 1 ⇒ SP; (B) ⇒ M(SP)
Push Accumulator B onto Stack
PSHC
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)
Push CCR onto Stack
PSHD
(SP) – 2 ⇒ SP; (A:B) ⇒ M(SP):M(SP+1)
Push D Accumulator onto Stack
PSHX
(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1)
Push Index Register X onto Stack
PSHY
(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1)
Push Index Register Y onto Stack
PULA
(M(SP)) ⇒ A; (SP) + 1 ⇒ SP
Pull Accumulator A from Stack
PULB
(M(SP)) ⇒ B; (SP) + 1 ⇒ SP
Pull Accumulator B from Stack
PULC
(M(SP)) ⇒ CCR; (SP) + 1 ⇒ SP
Pull CCR from Stack
PULD
(M(SP):M(SP+1)) ⇒ A:B; (SP) + 2 ⇒ SP
Pull D from Stack
PULX
(M(SP):M(SP+1)) ⇒ XH:XL; (SP) + 2 ⇒ SP
PULY
(M(SP):M(SP+1)) ⇒ YH:YL; (SP) + 2 ⇒ SP
REV
MIN-MAX rule evaluation
Find smallest rule input (MIN).
Store to rule outputs unless fuzzy output is
already larger (MAX).
Pull Index Register X from Stack
Pull Index Register Y from Stack
Special
18 3A
For rule weights see REVW.
Each rule input is an 8-bit offset from the
base address in Y. Each rule output is an 8bit offset from the base address in Y. $FE
separates rule inputs from rule outputs. $FF
terminates the rule list.
REV may be interrupted.
CPU12
REFERENCE MANUAL
INSTRUCTION REFERENCE
MOTOROLA
A-13
Table A-1 Instruction Set Summary (Continued)
Source
Form
REVW
Operation
MIN-MAX rule evaluation
Find smallest rule input (MIN),
Store to rule outputs unless fuzzy output is
already larger (MAX).
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
3**
per
rule
byte;
5
per
wt.
–
–
?
–
?
?
∆
!
75 hh ll
65 xb
65 xb ff
65 xb ee ff
65 xb
65 xb ee ff
45
55
4
3
4
5
6
6
1
1
–
–
–
–
∆
∆
∆
∆
76 hh ll
66 xb
66 xb ff
66 xb ee ff
66 xb
66 xb ee ff
46
56
4
3
4
5
6
6
1
1
–
–
–
–
∆
∆
∆
∆
INH
0A
6
–
–
–
–
–
–
–
–
INH
0B
8
∆
⇓
∆ ∆ ∆
∆
∆
∆
INH
3D
5
–
–
–
–
–
–
–
–
INH
18 16
2
–
–
–
–
∆
∆
∆
∆
Special
18 3B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
Rule weights supported, optional.
Each rule input is the 16-bit address of a
fuzzy input. Each rule output is the 16-bit address of a fuzzy output. The value $FFFE
separates rule inputs from rule outputs.
$FFFF terminates the rule list.
REVW may be interrupted.
ROL opr
C
b0
b7
Rotate Memory Left through Carry
ROLA
ROLB
Rotate A Left through Carry
Rotate B Left through Carry
ROR opr
b7
b0
C
Rotate Memory Right through Carry
RORA
RORB
Rotate A Right through Carry
Rotate B Right through Carry
RTC
(M(SP)) ⇒ PPAGE; (SP) + 1 ⇒ SP;
(M(SP):M(SP+1)) ⇒ PCH:PCL;
(SP) + 2 ⇒ SP
Return from Call
RTI
(M(SP)) ⇒ CCR; (SP) + 1 ⇒ SP
(M(SP):M(SP+1)) ⇒ B:A; (SP) + 2 ⇒ SP
(M(SP):M(SP+1)) ⇒ XH:XL; (SP) + 4 ⇒ SP
(M(SP):M(SP+1)) ⇒ PCH:PCL; (SP) – 2 ⇒ SP
(M(SP):M(SP+1)) ⇒ YH:YL;
(SP) + 4 ⇒ SP
RTS
(M(SP):M(SP+1)) ⇒ PCH:PCL;
(SP) + 2 ⇒ SP
Return from Interrupt
Return from Subroutine
SBA
MOTOROLA
A-14
(A) – (B) ⇒ A
Subtract B from A
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
Table A-1 Instruction Set Summary (Continued)
Source
Form
Operation
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
SBCA opr
(A) – (M) – C ⇒ A
Subtract with Borrow from A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
82 ii
92 dd
B2 hh ll
A2 xb
A2 xb ff
A2 xb ee ff
A2 xb
A2 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
SBCB opr
(B) – (M) – C ⇒ B
Subtract with Borrow from B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C2 ii
D2 dd
F2 hh ll
E2 xb
E2 xb ff
E2 xb ee ff
E2 xb
E2 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
SEC
1⇒C
Translates to ORCC #$01
IMM
14 01
1
–
–
–
–
–
–
–
1
SEI
1 ⇒ I; (inhibit I interrupts)
Translates to ORCC #$10
IMM
14 10
1
–
–
–
1
–
–
–
–
SEV
1⇒V
Translates to ORCC #$02
IMM
14 02
1
–
–
–
–
–
–
1
–
SEX r1, r2
$00:(r1) ⇒ r2 if r1, bit 7 is 0 or
$FF:(r1) ⇒ r2 if r1, bit 7 is 1
INH
B7 eb
1
–
–
–
–
–
–
–
–
Sign Extend 8-bit r1 to 16-bit r2
r1 may be A, B, or CCR
r2 may be D, X, Y, or SP
Alternate mnemonic for TFR r1, r2
STAA opr
(A) ⇒ M
Store Accumulator A to Memory
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5A dd
7A hh ll
6A xb
6A xb ff
6A xb ee ff
6A xb
6A xb ee ff
2
3
2
3
3
5
5
–
–
–
–
∆
∆
0
–
STAB opr
(B) ⇒ M
Store Accumulator B to Memory
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5B dd
7B hh ll
6B xb
6B xb ff
6B xb ee ff
6B xb
6B xb ee ff
2
3
2
3
3
5
5
–
–
–
–
∆
∆
0
–
STD opr
(A) ⇒ M, (B) ⇒ M+1
Store Double Accumulator
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5C dd
7C hh ll
6C xb
6C xb ff
6C xb ee ff
6C xb
6C xb ee ff
2
3
2
3
3
5
5
–
–
–
–
∆
∆
0
–
CPU12
REFERENCE MANUAL
INSTRUCTION REFERENCE
MOTOROLA
A-15
Table A-1 Instruction Set Summary (Continued)
Source
Form
STOP
Operation
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP);
STOP All Clocks
Addr.
Mode
INH
Machine
Coding (hex)
18 3E
~*
S X H I N Z V C
9**
+5
or
+2**
–
–
–
–
–
–
–
–
If S control bit = 1, the STOP instruction is
disabled and acts like a two-cycle NOP.
Registers stacked to allow quicker recovery
by interrupt.
STS opr
(SPH:SPL) ⇒ M:M+1
Store Stack Pointer
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5F dd
7F hh ll
6F xb
6F xb ff
6F xb ee ff
6F xb
6F xb ee ff
2
3
2
3
3
5
5
–
–
–
–
∆
∆
0
–
STX opr
(XH:XL) ⇒ M:M+1
Store Index Register X
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5E dd
7E hh ll
6E xb
6E xb ff
6E xb ee ff
6E xb
6E xb ee ff
2
3
2
3
3
5
5
–
–
–
–
∆
∆
0
–
STY opr
(YH:YL) ⇒ M:M+1
Store Index Register Y
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5D dd
7D hh ll
6D xb
6D xb ff
6D xb ee ff
6D xb
6D xb ee ff
2
3
2
3
3
5
5
–
–
–
–
∆
∆
0
–
SUBA opr
(A) – (M) ⇒ A
Subtract Memory from Accumulator A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
80 ii
90 dd
B0 hh ll
A0 xb
A0 xb ff
A0 xb ee ff
A0 xb
A0 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
SUBB opr
(B) – (M) ⇒ B
Subtract Memory from Accumulator B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C0 ii
D0 dd
F0 hh ll
E0 xb
E0 xb ff
E0 xb ee ff
E0 xb
E0 xb ee ff
1
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
MOTOROLA
A-16
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
Table A-1 Instruction Set Summary (Continued)
Source
Form
Operation
SUBD opr
(D) – (M:M+1) ⇒ D
Subtract Memory from D (A:B)
SWI
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)
1 ⇒ I; (SWI Vector) ⇒ PC
Addr.
Mode
Machine
Coding (hex)
~*
S X H I N Z V C
83 jj kk
93 dd
B3 hh ll
A3 xb
A3 xb ff
A3 xb ee ff
A3 xb
A3 xb ee ff
2
3
3
3
3
4
6
6
–
–
–
–
∆
∆
∆
∆
INH
3F
9
–
–
–
1
–
–
–
–
–
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Software Interrupt
TAB
(A) ⇒ B
Transfer A to B
INH
18 0E
2
–
–
–
∆
∆
0
–
TAP
(A) ⇒ CCR
Translates to TFR A , CCR
INH
B7 02
1
∆
⇓
∆ ∆ ∆
∆
∆
∆
TBA
(B) ⇒ A
Transfer B to A
INH
18 0F
2
–
–
–
–
∆
∆
0
–
TBEQ cntr, rel
If (cntr) = 0, then Branch;
else Continue to next instruction
REL
(9-bit)
04 lb rr
3
–
–
–
–
–
–
–
–
18 3D xb
8
–
–
–
–
∆
∆
–
?
REL
(9-bit)
04 lb rr
3
–
–
–
–
–
–
–
–
INH
B7 eb
1
– –
or
∆ ⇓
–
–
–
–
–
–
∆ ∆ ∆
∆
∆
∆
–
–
–
–
–
Test Counter and Branch if Zero
(cntr = A, B, D, X,Y, or SP)
TBL opr
(M) + [(B) × ((M+1) – (M))] ⇒ A
8-Bit Table Lookup and Interpolate
IDX
Initialize B, and index before TBL.
<ea> points at first 8-bit table entry (M) and
B is fractional part of lookup value.
(no indirect addressing modes allowed.)
TBNE cntr, rel
If (cntr) not = 0, then Branch;
else Continue to next instruction
Test Counter and Branch if Not Zero
(cntr = A, B, D, X,Y, or SP)
TFR r1, r2
(r1) ⇒ r2 or
$00:(r1) ⇒ r2 or
(r1[7:0]) ⇒ r2
Transfer Register to Register
r1 and r2 may be A, B, CCR, D, X, Y, or SP
TPA
(CCR) ⇒ A
Translates to TFR CCR , A
CPU12
REFERENCE MANUAL
INH
B7 20
INSTRUCTION REFERENCE
1
–
–
–
MOTOROLA
A-17
Table A-1 Instruction Set Summary (Continued)
Source
Form
TRAP
Operation
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)
1 ⇒ I; (TRAP Vector) ⇒ PC
Addr.
Mode
INH
Machine
Coding (hex)
~*
S X H I N Z V C
18 tn
tn = $30–$39
or
$40–$FF
10
–
–
–
1
–
–
–
–
F7 hh ll
E7 xb
E7 xb ff
E7 xb ee ff
E7 xb
E7 xb ee ff
97
D7
3
3
3
4
6
6
1
1
–
–
–
–
∆
∆
0
0
Unimplemented opcode trap
TST opr
(M) – 0
Test Memory for Zero or Minus
TSTA
TSTB
(A) – 0
(B) – 0
TSX
(SP) ⇒ X
Translates to TFR SP,X
INH
B7 75
1
–
–
–
–
–
–
–
–
TSY
(SP) ⇒ Y
Translates to TFR SP,Y
INH
B7 76
1
–
–
–
–
–
–
–
–
TXS
(X) ⇒ SP
Translates to TFR X,SP
INH
B7 57
1
–
–
–
–
–
–
–
–
TYS
(Y) ⇒ SP
Translates to TFR Y,SP
INH
B7 67
1
–
–
–
–
–
–
–
–
WAI
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP);
INH
3E
8**
(in)
+
5
(int)
– –
or
– –
or
– 1
–
–
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
8**
per
lable
–
?
–
?
∆
?
?
Test A for Zero or Minus
Test B for Zero or Minus
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
WAIT for interrupt
WAV
Special
18 3C
B
∑ S i F i ⇒ Y:D
–
i =1
B
∑ Fi ⇒ X
i =1
Calculate Sum of Products and Sum of
Weights for Weighted Average Calculation
Initialize B, X, and Y before WAV. B specifies
number of elements. X points at first element
in Si list. Y points at first element in Fi list.
All Si and Fi elements are 8-bits.
If interrupted, six extra bytes of stack used
for intermediate values
MOTOROLA
A-18
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
Table A-1 Instruction Set Summary (Continued)
Source
Form
Addr.
Mode
Operation
Machine
Coding (hex)
~*
S X H I N Z V C
3C
**
–
–
?
–
?
∆
?
?
wavr
see WAV
pseudoinstruction
Resume executing an interrupted WAV instruction (recover intermediate results from
stack rather than initializing them to zero)
XGDX
(D) ⇔ (X)
Translates to EXG D, X
INH
B7 C5
1
–
–
–
–
–
–
–
–
XGDY
(D) ⇔ (Y)
Translates to EXG D, Y
INH
B7 C6
1
–
–
–
–
–
–
–
–
Special
NOTES:
*Each cycle (~) is typically 125 ns for an 8-MHz bus (16-MHz oscillator).
**Refer to detailed instruction descriptions for additional information.
Key to Table A-2
opcode (hex)
cycle count
00
0
mnemonic
MNE
AA
addressing mode
0
byte count
Addressing mode abbreviations:
DI — Direct
EX — Extended
ID — Indexed
IH — Inherent
IM — Immediate
RL — Relative
SP — Special
Cycle counts are for single-chip mode with 16-bit internal buses. Stack location (internal or external),
external bus width, and operand alignment can affect actual execution time.
CPU12
REFERENCE MANUAL
INSTRUCTION REFERENCE
MOTOROLA
A-19
MOTOROLA
A-20
Table A-2 CPU12 Opcode Map (Sheet 1 of 2)
*5
00
1 IM
5 11
IH
01
1 RL
3 23
1 IH
1 13
1 IH
3 14
RL
05
3 IM
3-6 15
loop‡
ORCC
INSTRUCTION REFERENCE
2-4 ID
3 16
3 RL
4 27
3 EX
4 17
2 RL
- 28
2 DI
1 18
page 2
INX
1 ID
6 1A
1 ID
8 1B
RTI
IH
0C
CPU12
REFERENCE MANUAL
BRSET
4-6 EX
4-8 1F
BRCLR
4 RL
5 2E
BRCLR
4-6 EX
PSHD
2-5 DI
4 5C
SWI
3 DI
4 5D
STY
BCLR
1 DI
*8 4E
WAI
STD
BSET
1 DI
5 4D
RTS
STAB
CALL
1 ID
*+9 4C
wavr
2 IH
STAA
4 DI
1 EX
2 4B 8-10 5B
2 IH
3/1 3F
BLE
5 RL
1 IH
8 5A
CALL
PULD
2 IH
3/1 3E
BGT
5 RL
5 2F
ASLD
LSRD
1 IH
3 4A
2 SP
3/1 3D
BLT
BCLR
3-5 EX
4-8 1E
BRSET
ID
0F
4 RL
4 2D
1 IH
1 59
1 IH
2 49
PSHC
2 IH
3/1 3C
BGE
BSET
3-5 EX
4-6 1D
BCLR
ID
0E
2-4 RL
4 2C
ASLB
ASLA
PULC
2 IH
3/1 3B
BMI
LEAS
1 ID
4-6 1C
BSET
ID
0D
2-4 RL
2 2B
1 IH
1 58
1 IH
3 48
2 IH
3/1 3A
BPL
LEAX
RTC
IH
0B
2-4 RL
2 2A
ASRB
ASRA
PSHB
2 IH
3/1 39
BVS
LEAY
DEX
IH
0A
1 IH
1 57
1 IH
2 47
3 DI
4 5E
BRSET
1 DI
9 4F
BRCLR
1 DI
STX
4 DI
4 5F
STS
4 DI
STX
2-4 EX
2-5 7F
STS
2 ID
STY
2-4 EX
2-5 7E
STX
2 ID
2 6F
STD
2-4 EX
2-5 7D
STY
2 ID
2 6E
STAB
2-4 EX
2-5 7C
STD
2 ID
2 6D
STAA
2-4 EX
2-5 7B
STAB
2 ID
2 6C
CLR
2-4 EX
2-5 7A
STAA
2 ID
2 6B
ASL
2-4 EX
2-5 79
CLR
1 ID
2 6A
ASR
2-4 EX
3-6 78
ASL
1 ID
1 69
ROR
2-4 EX
3-6 77
ASR
1 ID
1 68
ROL
2-4 EX
3-6 76
ROR
1 ID
1 67
LSR
2-4 EX
3-6 75
ROL
1 ID
1 66
RORB
RORA
PSHA
2 IH
3/1 38
BVC
- RL
2 29
1 1 19
IH
09
1 IH
1 56
1 IH
2 46
DEC
2-4 EX
3-6 74
LSR
1 ID
1 65
ROLB
ROLA
PSHY
2 IH
3/1 37
BEQ
JSR
BSR
RL
08
1 IH
1 55
1 IH
2 45
INC
2-4 EX
3-6 73
DEC
1 ID
1 64
LSRB
LSRA
PSHX
2 IH
3/1 36
BNE
JSR
JMP
EX
07
1 IH
1 54
1 IH
2 44
COM
2-4 EX
3-6 72
INC
1 ID
1 63
NEG
2-4 EX
3-6 71
COM
1 ID
1 62
DECB
DECA
PULB
2 IH
3/1 35
BCS
2-4 RL
4 26
1 IH
1 53
1 IH
3 43
2 IH
3/1 34
BCC
2 RL
4-7 25
JSR
JMP
ID
06
1 RL
1 24
COMB
INCB
INCA
PULA
3-6 70
NEG
1 ID
1 61
1 IH
1 52
1 IH
3 42
2 IH
3/1 33
BLS
EMUL
DEY
IH
04
COMA
PULY
2 IH
3/1 32
BHI
MUL
INY
IH
03
ID
BRN
1 RL
3 22
1 IH
1 12
1 IH
1 51
1 IH
3 41
1 60
NEGB
NEGA
PULX
2 IH
1 31
2 RL
11 21
EDIV
MEM
IH
02
BRA
1 50
3 40
3 30
1 20
10
ANDCC
BGND
STS
2-4 EX
4 80
1 90
3 IM
4 81
2 DI
1 91
2 DI
1 92
2 DI
2 93
3 DI
1 94
2 DI
1 95
2 DI
1 96
2 DI
1 97
1 IH
1 98
2 DI
1 99
2 DI
1 9A
ORAA
ADDA
CPD
3 IM
3 8D
CPY
3 IM
3 8E
CPX
3 IM
3 8F
CPS
3 IM
2 ID
3 AA
ORAA
2 DI
1 9B
ADDA
2 DI
2 9C
CPD
3 DI
2 9D
CPY
3 DI
2 9E
CPX
3 DI
2 9F
CPS
3 DI
ADDA
2 ID
3 AC
CPX
2-4 EX
3-6 BF
CPS
2 ID
CPY
2-4 EX
3-6 BE
CPX
2 ID
3 AF
CPD
2-4 EX
3-6 BD
CPY
2 ID
3 AE
ADDA
2-4 EX
3-6 BC
CPD
2 ID
3 AD
ORAA
2-4 EX
3-6 BB
CPS
2-4 EX
2 DI
1 DA
ORAB
3 IM
3 CB
LDD
3 IM
3 CD
LDY
3 IM
3 CE
LDX
3 IM
3 CF
LDS
3 IM
ORAB
2 DI
1 DB
ADDB
3 IM
3 CC
2 ID
3 EA
ADDB
2 DI
2 DC
LDD
3 DI
2 DD
LDY
3 DI
2 DE
LDX
3 DI
2 DF
LDS
3 DI
3
3
LDX
2-4 EX
3-6 FF
LDS
2 ID
3
3
LDY
2-4 EX
3-6 FE
LDX
2 ID
3 EF
3
3
LDD
2-4 EX
3-6 FD
LDY
2 ID
3 EE
3
3
ADDB
2-4 EX
3-6 FC
LDD
2 ID
3 ED
3
3
ORAB
2-4 EX
3-6 FB
ADDB
2 ID
3 EC
3
3
ADCB
2-4 EX
3-6 FA
ORAB
2 ID
3 EB
3
3
EORB
2-4 EX
3-6 F9
ADCB
ADCB
ADCB
3 IM
3 CA
2 ID
3 E9
3
3
TST
2-4 EX
3-6 F8
EORB
EORB
2 DI
1 D9
3
3
LDAB
2-4 EX
3-6 F7
TST
1 ID
3 E8
3
3
BITB
2-4 EX
3-6 F6
LDAB
2 ID
1 E7
TSTB
1 IH
1 D8
EORB
3 IM
3 C9
ADCA
2-4 EX
3-6 BA
ORAA
2 ID
3 AB
2 IH
3 C8
EORA
2-4 EX
3-6 B9
ADCA
ADCA
ADCA
3 IM
3 8C
2 ID
3 A9
2 DI
1 D7
3
3
ANDB
2-4 EX
3-6 F5
BITB
2 ID
3 E6
LDAB
LDAB
3 IM
1 C7
TFR/EXG CLRB
1 IH
3-6 B8
EORA
EORA
EORA
3 IM
3 8B
1 IH
3 A8
2 DI
1 D6
3
3
ADDD
2-4 EX
3-6 F4
ANDB
2 ID
3 E5
BITB
BITB
3 IM
3 C6
LDAA
2-4 EX
1 B7
NOP
TSTA
CLRA
3 IM
3 8A
2 ID
1 A7
2 DI
1 D5
3
3
SBCB
2-4 EX
3-6 F3
ADDD
2 ID
3 E4
ANDB
ANDB
3 IM
3 C5
BITA
2-4 EX
3-6 B6
LDAA
LDAA
LDAA
3 IM
3 89
2 ID
3 A6
3 DI
1 D4
3
3
CMPB
2-4 EX
3-6 F2
SBCB
2 ID
3 E3
3
SUBB
2-4 EX
3-6 F1
CMPB
2 ID
3 E2
ADDD
ADDD
3 IM
3 C4
2 ID
3 E1
SBCB
2 DI
2 D3
3-6 F0
SUBB
CMPB
2 DI
1 D2
SBCB
3 IM
3 C3
ANDA
2-4 EX
3-6 B5
BITA
BITA
BITA
3 IM
4 87
2 ID
3 A5
2 DI
1 D1
CMPB
SUBD
3 E0
SUBB
3 IM
3 C2
2-4 EX
3-6 B4
ANDA
ANDA
ANDA
3 IM
4 86
SUBD
2 ID
3 A4
3 IM
3 C1
SBCA
2-4 EX
3-6 B3
1 D0
SUBB
CMPA
2-4 EX
3-6 B2
SBCA
2 ID
3 A3
3 C0
SUBA
2-4 EX
3-6 B1
CMPA
2 ID
3 A2
SUBD
SUBD
3 IM
4 84
3 IM
4 85
2 ID
3 A1
SBCA
SBCA
3 IM
4 83
3-6 B0
SUBA
CMPA
CMPA
3 IM
4 82
3 IH
4 88
3 A0
SUBA
SUBA
3
3
LDS
2-4 EX
3
Table A-2 CPU12 Opcode Map (Sheet 2 of 2)
CPU12
REFERENCE MANUAL
4 10
00
MOVW
IM-ID
01
5 IH
5 11
MOVW
MOVW
ID-ID
03
MOVW
MOVW
EMACS
EDIVS
INSTRUCTION REFERENCE
2 RL
2 26
CBA
DAA
IH
08
2 IH
4 18
MOVB
IM-ID
09
MOVB
MINA
MOVB
EMAXD
4 ID
4 1B
MOVB
EMIND
IM-EX 5 ID
6 1C
0C
MOVB
MOVB
MINM
ID-EX 5 ID
2 1E
0E
TAB
MOTOROLA
A-21
IH
0F
TBA
IH
EMAXM
2 ID
2 1F
LBLE
3-5 RL
ETBL
4 ID
TRAP
3 IH
TRAP
2 IH
TRAP
2 IH
TRAP
2 IH
TRAP
2 IH
10 8F
TRAP
2 IH
TRAP
2 IH
10 AF
TRAP
2 IH
2 IH
10 DF
TRAP
TRAP
2 IH
2 IH
* Refer to instruction glossary for more information.
‡ The opcode $04 corresponds to one of the loop primitive instructions DBEQ, DBNE, IBEQ, IBNE, TBEQ, or TBNE.
2
10
TRAP
2 IH
10 FF
TRAP
2 IH
2
10
TRAP
2 IH
10 FE
TRAP
2 IH
10 EF
2
10
TRAP
2 IH
10 FD
TRAP
2 IH
10 EE
TRAP
TRAP
2 IH
10 CF
TRAP
2 IH
2 IH
10 DE
2
10
TRAP
2 IH
10 FC
TRAP
2 IH
10 ED
TRAP
TRAP
2 IH
10 CE
TRAP
2 IH
10 BF
2 IH
10 DD
2
10
TRAP
2 IH
10 FB
TRAP
2 IH
10 EC
TRAP
TRAP
2 IH
10 CD
TRAP
2 IH
10 BE
2 IH
10 DC
2
10
TRAP
2 IH
10 FA
TRAP
2 IH
10 EB
TRAP
TRAP
2 IH
10 CC
TRAP
2 IH
10 BD
TRAP
2 IH
10 AE
TRAP
2 IH
10 9F
TRAP
2 IH
TRAP
2 IH
10 9E
TRAP
2 IH
10 AD
2 IH
10 DB
2
10
TRAP
2 IH
10 F9
TRAP
2 IH
10 EA
TRAP
TRAP
2 IH
10 CB
TRAP
2 IH
10 BC
2 IH
10 DA
2
10
TRAP
2 IH
10 F8
TRAP
2 IH
10 E9
TRAP
TRAP
2 IH
10 CA
TRAP
2 IH
10 BB
TRAP
2 IH
10 AC
TRAP
2 IH
10 9D
TRAP
2 IH
10 8E
TRAP
2 IH
10 7F
TRAP
2 IH
10 8D
TRAP
2 IH
10 7E
TRAP
2 IH
10 6F
TRAP
2 IH
10 7D
TRAP
2 IH
10 6E
TRAP
2 IH
10 5F
TRAP
2 IH
10 6D
TRAP
2 IH
10 5E
TRAP
2 IH
10 4F
TRAP
2 IH
10 5D
TRAP
3 IH
*9+5 4E
STOP
4 IH
4/3 3F
TRAP
2 IH
8 4D
TBL
4 ID
4/3 3E
LBGT
3-5 RL
4-7 2F
EMINM
2 ID
LBLT
3-5 RL
4-7 2E
WAV
4 SP
4/3 3D
TRAP
2 IH
10 9C
TRAP
2 IH
10 AB
2 IH
10 D9
2
10
TRAP
2 IH
10 F7
TRAP
2 IH
10 E8
TRAP
TRAP
2 IH
10 C9
TRAP
2 IH
10 BA
2 IH
10 D8
2
10
TRAP
2 IH
10 F6
TRAP
2 IH
10 E7
TRAP
TRAP
2 IH
10 C8
TRAP
2 IH
10 B9
TRAP
2 IH
10 AA
TRAP
2 IH
10 9B
TRAP
2 IH
10 8C
TRAP
2 IH
10 9A
TRAP
2 IH
10 8B
TRAP
2 IH
10 7C
TRAP
2 IH
10 8A
TRAP
2 IH
10 7B
TRAP
2 IH
10 6C
TRAP
2 IH
10 7A
TRAP
2 IH
10 6B
TRAP
2 IH
10 5C
TRAP
2 IH
10 6A
TRAP
2 IH
10 5B
TRAP
2 IH
*8B 4C
TRAP
2 IH
10 5A
TRAP
2 IH
*3n 4B
REVW
4 SP
4/3 3C
LBGE
3-5 RL
4-7 2D
2 IH
*3n 4A
REV
4 SP
4/3 3B
LBMI
3-5 RL
4-7 2C
MAXM
EX-EX 6 ID
5 1D
0D
LBPL
3-5 RL
4-7 2B
TRAP
TRAP
4 IH
4/3 3A
TRAP
2 IH
10 A9
2 IH
10 D7
2
10
TRAP
2 IH
10 F5
TRAP
2 IH
10 E6
TRAP
TRAP
2 IH
10 C7
TRAP
2 IH
10 B8
2 IH
10 D6
2
10
TRAP
2 IH
10 F4
TRAP
2 IH
10 E5
TRAP
TRAP
2 IH
10 C6
TRAP
2 IH
10 B7
TRAP
2 IH
10 A8
TRAP
2 IH
10 99
TRAP
2 IH
10 A7
TRAP
2 IH
10 98
TRAP
2 IH
10 89
TRAP
2 IH
10 97
TRAP
2 IH
10 88
TRAP
2 IH
10 79
TRAP
2 IH
10 87
TRAP
2 IH
10 78
TRAP
2 IH
10 69
TRAP
2 IH
10 77
TRAP
2 IH
10 68
TRAP
2 IH
10 59
TRAP
2 IH
10 67
TRAP
2 IH
10 58
TRAP
2 IH
10 49
TRAP
2 IH
10 57
TRAP
2 IH
10 48
TRAP
4 IH
4/3 39
LBVS
3-5 RL
4-7 2A
2 IH
10 47
TRAP
4 IH
4/3 38
LBVC
3-5 RL
4-7 29
TRAP
TRAP
4 IH
4/3 37
LBEQ
2 RL
4-7 28
MAXA
4 ID
5 19
EX-ID 5 ID
5 1A
0A
ID-ID
0B
2 RL
2 27
2 IH
3 17
2 IH
10 D5
2
10
TRAP
2 IH
10 F3
TRAP
2 IH
10 E4
TRAP
TRAP
2 IH
10 C5
TRAP
2 IH
10 B6
TRAP
2 IH
10 D4
2
10
TRAP
2 IH
10 F2
TRAP
2 IH
10 E3
10
TRAP
2 IH
10 F1
TRAP
2 IH
10 E2
TRAP
2 IH
10 D3
10 F0
TRAP
2 IH
10 E1
TRAP
2 IH
10 D2
TRAP
2 IH
10 C4
TRAP
2 IH
10 B5
TRAP
2 IH
10 A6
TRAP
2 IH
10 B4
TRAP
2 IH
10 A5
TRAP
2 IH
10 96
TRAP
2 IH
10 A4
TRAP
2 IH
10 95
TRAP
2 IH
10 86
TRAP
2 IH
10 94
TRAP
2 IH
10 85
TRAP
2 IH
10 76
TRAP
2 IH
10 84
TRAP
2 IH
10 75
TRAP
2 IH
10 66
TRAP
2 IH
10 74
TRAP
2 IH
10 65
TRAP
2 IH
10 56
TRAP
2 IH
10 64
TRAP
2 IH
10 55
TRAP
2 IH
10 46
TRAP
2 IH
10 54
TRAP
2 IH
10 45
TRAP
4 IH
4/3 36
LBNE
SBA
ABA
2 IH
10 44
TRAP
4 IH
4/3 35
LBCS
IDIVS
ID-EX 5 IH
2 16
06
IH
07
LBCC
2 RL
12 25
TRAP
TRAP
4 IH
4/3 34
2 IH
10 D1
TRAP
2 IH
10 C3
10 E0
TRAP
TRAP
2 IH
10 C2
TRAP
2 IH
10 B3
10 D0
TRAP
2 IH
10 C1
TRAP
2 IH
10 B2
TRAP
2 IH
10 A3
10 C0
TRAP
2 IH
10 B1
TRAP
2 IH
10 A2
TRAP
2 IH
10 93
10 B0
TRAP
2 IH
10 A1
TRAP
2 IH
10 92
TRAP
2 IH
10 83
10 A0
TRAP
2 IH
10 91
TRAP
2 IH
10 82
TRAP
2 IH
10 73
10 90
TRAP
2 IH
10 81
TRAP
2 IH
10 72
TRAP
2 IH
10 63
10 80
TRAP
2 IH
10 71
TRAP
2 IH
10 62
TRAP
2 IH
10 53
10 70
TRAP
2 IH
10 61
TRAP
2 IH
10 52
TRAP
2 IH
10 43
10 60
TRAP
2 IH
10 51
TRAP
2 IH
10 42
TRAP
4 IH
4/3 33
LBLS
2 RL
12 24
2 IH
10 41
TRAP
4 IH
4/3 32
LBHI
4 RL
3 23
EMULS
EX-EX 6 IH
5 15
05
MOVW
LBRN
2 RL
13 22
4 SP
5 13
IM-EX 6 IH
6 14
04
4 IH
3 31
2 RL
12 21
10 50
TRAP
TRAP
LBRA
FDIV
EX-ID 5 IH
5 12
02
10 40
4 30
12 20
IDIV
2
10
TRAP
2 IH
2
MOTOROLA
A-22
Table A-3 Indexed Addressing Mode Postbyte Encoding (xb)
INSTRUCTION REFERENCE
E0
F0
n,X
9b const
n,SP
9b const
D1
–15,PC
5b const
E1
F1
–n,X
9b const
–n,SP
9b const
D2
–14,PC
5b const
E2
F2
n,X
16b const
n,SP
16b const
D3
–13,PC
5b const
E3
F3
[n,X]
16b indr
[n,SP]
16b indr
D4
–12,PC
5b const
E4
F4
A,X
A offset
A,SP
A offset
D5
–11,PC
5b const
E5
F5
B,X
B offset
B,SP
B offset
D6
–10,PC
5b const
E6
F6
D,X
D offset
D,SP
D offset
D7
–9,PC
5b const
E7
[D,X]
D indirect
F7
[D,SP]
D indirect
D8
–8,PC
5b const
E8
F8
n,Y
9b const
n,PC
9b const
D9
–7,PC
5b const
E9
9,PC
5b const
–n,Y
9b const
F9
–n,PC
9b const
BA
6,SP–
post-dec
CA
10,PC
5b const
DA
–6,PC
5b const
EA
FA
n,Y
16b const
n,PC
16b const
AB
5,–SP
pre-dec
BB
5,SP–
post-dec
CB
11,PC
5b const
DB
–5,PC
5b const
EB
[n,Y]
16b indr
FB
[n,PC]
16b indr
9C
–4,SP
5b const
AC
4,–SP
pre-dec
BC
4,SP–
post-dec
CC
12,PC
5b const
DC
–4,PC
5b const
EC
FC
A,Y
A offset
A,PC
A offset
8D
13,SP
5b const
9D
–3,SP
5b const
AD
3,–SP
pre-dec
BD
3,SP–
post-dec
CD
13,PC
5b const
DD
–3,PC
5b const
ED
FD
B,Y
B offset
B,PC
B offset
A0
1,+SP
pre-inc
B0
1,SP+
post-inc
C0
91
–15,SP
5b const
A1
2,+SP
pre-inc
B1
2,SP+
post-inc
C1
92
–14,SP
5b const
A2
3,+SP
pre-inc
B2
3,SP+
post-inc
C2
93
–13,SP
5b const
A3
4,+SP
pre-inc
B3
4,SP+
post-inc
C3
94
–12,SP
5b const
A4
5,+SP
pre-inc
B4
5,SP+
post-inc
C4
95
–11,SP
5b const
A5
6,+SP
pre-inc
B5
6,SP+
post-inc
C5
96
–10,SP
5b const
A6
7,+SP
pre-inc
B6
7,SP+
post-inc
C6
6,SP
5b const
77
87
97
7,SP
5b const
–9,SP
5b const
A7
8,+SP
pre-inc
B7
8,SP+
post-inc
C7
8,Y+
post-inc
68
78
88
98
8,Y–
post-dec
8,SP
5b const
–8,SP
5b const
A8
8,–SP
pre-dec
B8
8,SP–
post-dec
C8
8,–Y
pre-dec
59
69
79
89
99
7,–Y
pre-dec
7,Y–
post-dec
9,SP
5b const
–7,SP
5b const
A9
7,–SP
pre-dec
B9
7,SP–
post-dec
C9
–7,Y
5b const
4A
5A
6A
7A
10,Y
5b const
–6,Y
5b const
6,–Y
pre-dec
6,Y–
post-dec
8A
10,SP
5b const
9A
–6,SP
5b const
AA
6,–SP
pre-dec
4B
5B
6B
7B
8B
11,SP
5b const
9B
–5,SP
5b const
8C
12,SP
5b const
10
20
30
40
50
60
70
80
0,X
5b const
–16,X
5b const
1,+X
pre-inc
1,X+
post-inc
0,Y
5b const
–16,Y
5b const
1,+Y
pre-inc
1,Y+
post-inc
0,SP
5b const
01
11
21
31
41
51
61
71
81
1,X
5b const
–15,X
5b const
2,+X
pre-inc
2,X+
post-inc
1,Y
5b const
–15,Y
5b const
2,+Y
pre-inc
2,Y+
post-inc
1,SP
5b const
02
12
22
32
42
52
62
72
82
2,X
5b const
–14,X
5b const
3,+X
pre-inc
3,X+
post-inc
2,Y
5b const
–14,Y
5b const
3,+Y
pre-inc
3,Y+
post-inc
2,SP
5b const
03
13
23
33
43
53
63
73
83
3,X
5b const
–13,X
5b const
4,+X
pre-inc
4,X+
post-inc
3,Y
5b const
–13,Y
5b const
4,+Y
pre-inc
4,Y+
post-inc
3,SP
5b const
04
14
24
34
44
54
64
74
84
4,X
5b const
–12,X
5b const
5,+X
pre-inc
5,X+
post-inc
4,Y
5b const
–12,Y
5b const
5,+Y
pre-inc
5,Y+
post-inc
4,SP
5b const
05
15
25
35
45
55
65
75
85
5,X
5b const
–11,X
5b const
6,+X
pre-inc
6,X+
post-inc
5,Y
5b const
–11,Y
5b const
6,+Y
pre-inc
6,Y+
post-inc
5,SP
5b const
06
16
26
36
46
56
66
76
86
6,X
5b const
–10,X
5b const
7,+X
pre-inc
7,X+
post-inc
6,Y
5b const
–10,Y
5b const
7,+Y
pre-inc
7,Y+
post-inc
07
17
27
37
47
57
67
7,X
5b const
–9,X
5b const
8,+X
pre-inc
8,X+
post-inc
7,Y
5b const
–9,Y
5b const
8,+Y
pre-inc
08
18
28
38
48
58
8,X
5b const
–8,X
5b const
8,–X
pre-dec
8,X–
post-dec
8,Y
5b const
–8,Y
5b const
09
19
29
39
49
9,X
5b const
–7,X
5b const
7,–X
pre-dec
7,X–
post-dec
9,Y
5b const
0A
1A
2A
3A
10,X
5b const
–6,X
5b const
6,–X
pre-dec
6,X–
post-dec
0B
1B
2B
3B
11,X
5b const
CPU12
REFERENCE MANUAL
D0
–16,PC
5b const
90
–16,SP
5b const
00
–5,X
5b const
5,–X
pre-dec
5,X–
post-dec
11,Y
5b const
–5,Y
5b const
5,–Y
pre-dec
5,Y–
post-dec
0,PC
5b const
1,PC
5b const
2,PC
5b const
3,PC
5b const
4,PC
5b const
5,PC
5b const
6,PC
5b const
7,PC
5b const
8,PC
5b const
0C
1C
2C
3C
4C
5C
6C
7C
12,X
5b const
–4,X
5b const
4,–X
pre-dec
4,X–
post-dec
12,Y
5b const
–4,Y
5b const
4,–Y
pre-dec
4,Y–
post-dec
0D
1D
2D
3D
4D
5D
6D
7D
13,X
5b const
–3,X
5b const
3,–X
pre-dec
3,X–
post-dec
13,Y
5b const
–3,Y
5b const
3,–Y
pre-dec
3,Y–
post-dec
0E
1E
2E
3E
4E
5E
6E
7E
2,–X
pre-dec
2,X–
post-dec
14,Y
5b const
–2,Y
5b const
2,–Y
pre-dec
2,Y–
post-dec
9E
–2,SP
5b const
AE
2,–SP
pre-dec
BE
2,SP–
post-dec
CE
14,PC
5b const
DE
–2,PC
5b const
FE
–2,X
5b const
8E
14,SP
5b const
EE
14,X
5b const
D,Y
D offset
D,PC
D offset
0F
1F
2F
3F
4F
5F
6F
7F
8F
9F
–1,X
5b const
1,–X
pre-dec
1,X–
post-dec
15,Y
5b const
–1,Y
5b const
1,–Y
pre-dec
1,Y–
post-dec
15,SP
5b const
–1,SP
5b const
AF
1,–SP
pre-dec
BF
1,SP–
post-dec
CF
15,PC
5b const
DF
–1,PC
5b const
EF
15,X
5b const
FF
[D,PC]
D indirect
[D,Y]
D indirect
CPU12
REFERENCE MANUAL
Table A-4 Transfer and Exchange Postbyte Encoding
TRANSFERS
⇓ LS MS⇒
0
1
2
0
A⇒A
B⇒A
CCR ⇒ A
TMP3L ⇒ A
B⇒A
XL ⇒ A
YL ⇒ A
SPL ⇒ A
1
A⇒B
B⇒B
CCR ⇒ B
TMP3L ⇒ B
B⇒B
XL ⇒ B
YL ⇒ B
SPL ⇒ B
2
A ⇒ CCR
B ⇒ CCR
CCR ⇒ CCR
TMP3L ⇒ CCR
B ⇒ CCR
XL ⇒ CCR
YL ⇒ CCR
SPL ⇒ CCR
TMP3 ⇒ TMP2
D ⇒ TMP2
X ⇒ TMP2
Y ⇒ TMP2
SP ⇒ TMP2
3
sex:A ⇒ TMP2 sex:B ⇒ TMP2 sex:CCR ⇒ TMP2
3
4
5
6
7
INSTRUCTION REFERENCE
4
sex:A ⇒ D
SEX A,D
sex:B ⇒ D
SEX B,D
sex:CCR ⇒ D
SEX CCR,D
TMP3 ⇒ D
D⇒D
X⇒D
Y⇒D
SP ⇒ D
5
sex:A ⇒ X
SEX A,X
sex:B ⇒ X
SEX B,X
sex:CCR ⇒ X
SEX CCR,X
TMP3 ⇒ X
D⇒X
X⇒X
Y⇒X
SP ⇒ X
6
sex:A ⇒ Y
SEX A,Y
sex:B ⇒ Y
SEX B,Y
sex:CCR ⇒ Y
SEX CCR,Y
TMP3 ⇒ Y
D⇒Y
X⇒Y
Y⇒Y
SP ⇒ Y
7
sex:A ⇒ SP
SEX A,SP
sex:B ⇒ SP
SEX B,SP
sex:CCR ⇒ SP
SEX CCR,SP
TMP3 ⇒ SP
D ⇒ SP
X ⇒ SP
Y ⇒ SP
SP ⇒ SP
EXCHANGES
⇓ LS MS⇒
8
9
A
B
C
D
E
F
XL ⇒ A
$00:A ⇒ X
YL ⇒ A
$00:A ⇒ Y
SPL ⇒ A
$00:A ⇒ SP
XL ⇒ B
$FF:B ⇒ X
YL ⇒ B
$FF:B ⇒ Y
SPL ⇒ B
$FF:B ⇒ SP
0
A⇔A
B⇔A
CCR ⇔ A
TMP3L ⇒ A
$00:A ⇒ TMP3
B⇒A
A⇒B
1
A⇔B
B⇔B
CCR ⇔ B
TMP3L ⇒ B
$FF:B ⇒ TMP3
B⇒B
$FF ⇒ A
2
A ⇔ CCR
B ⇔ CCR
CCR ⇔ CCR
3
$00:A ⇒ TMP2 $00:B ⇒ TMP2 $00:CCR ⇒ TMP2
TMP2L ⇒ CCR
TMP2L ⇒ B
TMP2L ⇒ A
SPL ⇒ CCR
YL ⇒ CCR
XL ⇒ CCR
B ⇒ CCR
TMP3L ⇒ CCR
$FF:CCR ⇒ TMP3 $FF:CCR ⇒ D $FF:CCR ⇒ X $FF:CCR ⇒ Y $FF:CCR ⇒ SP
TMP3 ⇔ TMP2
D ⇔ TMP2
X ⇔ TMP2
Y ⇔ TMP2
SP ⇔ TMP2
MOTOROLA
A-23
4
$00:A ⇒ D
$00:B ⇒ D
$00:CCR ⇒ D
B ⇒ CCR
TMP3 ⇔ D
D⇔D
X⇔D
Y⇔D
SP ⇔ D
5
$00:A ⇒ X
XL ⇒ A
$00:B ⇒ X
XL ⇒ B
$00:CCR ⇒ X
XL ⇒ CCR
TMP3 ⇔ X
D⇔X
X⇔X
Y⇔X
SP ⇔ X
6
$00:A ⇒ Y
YL ⇒ A
$00:B ⇒ Y
YL ⇒ B
$00:CCR ⇒ Y
YL ⇒ CCR
TMP3 ⇔ Y
D⇔Y
X⇔Y
Y⇔Y
SP ⇔ Y
7
$00:A ⇒ SP
SPL ⇒ A
$00:B ⇒ SP
SPL ⇒ B
$00:CCR ⇒ SP
SPL ⇒ CCR
TMP3 ⇔ SP
D ⇔ SP
X ⇔ SP
Y ⇔ SP
SP ⇔ SP
Key to Table A-3
postbyte (hex)
B0
#,REG
source code syntax
type
type offset used
Table A-5 Indexed Addressing Mode Summary
Postbyte
Code (xb)
Operand
Syntax
Comments
rr0nnnnn
,r
n,r
–n,r
5-bit constant offset
n = –16 to +15
rr can specify X, Y, SP, or PC
111rr0zs
n,r
–n,r
Constant offset (9- or 16-bit signed)
z- 0 = 9-bit with sign in LSB of postbyte (s)
1 = 16-bit
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify X, Y, SP, or PC
111rr011
[n,r]
16-bit offset indexed-indirect
rr can specify X, Y, SP, or PC
rr1pnnnn
n,–r
n,+r
n,r–
n,r+
Auto pre-decrement /increment or Auto post-decrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
rr can specify X, Y, or SP (PC not a valid choice)
111rr1aa
A,r
B,r
D,r
Accumulator offset (unsigned 8-bit or 16-bit)
aa - 00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
111rr111
[D,r]
Accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
MOTOROLA
A-24
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
Table A-6 Loop Primitive Postbyte Encoding (lb)
00
A 10
A 20
A 30
A 40
A 50
A 60
A 70
A 80
A 90
DBEQ
DBEQ
DBNE
DBNE
TBEQ
TBEQ
TBNE
TBNE
IBEQ
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
01
B 11
DBEQ
B 21
DBEQ
(+)
—
03
13
—
23
—
D 14
33
—
D 24
—
43
—
D 34
D 44
D 54
73
—
D 64
D 74
D 84
DBNE
DBNE
TBEQ
TBEQ
TBNE
TBNE
IBEQ
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
X 15
X 25
X 35
X 45
X 55
X 65
X 75
DBNE
DBNE
TBEQ
TBEQ
TBNE
TBNE
IBEQ
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
Y 16
Y 26
Y 36
Y 46
Y 56
Y 66
Y 76
IBEQ
X B5
IBNE
X
IBNE
(+)
Y 96
D
IBNE
(–)
X A5
(–)
Y 86
D B4
IBNE
(+)
X 95
DBEQ
—
D A4
IBEQ
(–)
X 85
DBEQ
06
B3
—
D 94
DBEQ
—
A3
—
DBEQ
05
B2
—
93
—
(–)
A2
—
83
—
B
IBNE
(+)
92
—
B B1
IBNE
(–)
82
—
63
—
(+)
72
—
53
—
(–)
62
(–)
B A1
IBEQ
A
IBNE
(+)
B 91
IBEQ
A B0
IBNE
(–)
B 81
TBNE
(+)
52
—
B 71
TBNE
(–)
42
—
B 61
TBEQ
(+)
32
—
B 51
TBEQ
(–)
22
—
B 41
DBNE
(+)
12
04
DBNE
(–)
02
B 31
A A0
IBEQ
(–)
Y A6
Y B6
Y
DBEQ
DBEQ
DBNE
DBNE
TBEQ
TBEQ
TBNE
TBNE
IBEQ
IBEQ
IBNE
IBNE
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
07
SP 17
SP 27
SP 37
SP 47
SP 57
SP 67
SP 77
SP 87
SP 97
SP A7
SP B7
SP
DBEQ
DBEQ
DBNE
DBNE
TBEQ
TBEQ
TBNE
TBNE
IBEQ
IBEQ
IBNE
IBNE
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
postbyte (hex)
counter used
B0
A
_BEQ
(–)
branch condition
CPU12
REFERENCE MANUAL
sign of 9-bit relative branch offset
(lower eight bits are an extension byte
following postbyte)
INSTRUCTION REFERENCE
MOTOROLA
A-25
MOTOROLA
A-26
INSTRUCTION REFERENCE
CPU12
REFERENCE MANUAL
APPENDIX B
M68HC11 TO M68HC12 UPGRADE PATH
This appendix discusses similarities and differences between the CPU12 and the
M68HC11 CPU. In general, the CPU12 is a proper superset of the M68HC11. Significant changes have been made to improve the efficiency and capabilities of the CPU
without giving up compatibility and familiarity for the large community of M68HC11
programmers.
B.1 CPU12 Design Goals
The primary goals of the CPU12 design were:
•
•
•
•
•
•
•
ABSOLUTE source code compatibility with the M68HC11
Same programming model
Same stacking operations
Upgrade to 16-bit architecture
Eliminate extra byte/extra cycle penalty for using index register Y
Improve performance
Improve compatibility with high level languages
B.2 Source Code Compatibility
Every M68HC11 instruction mnemonic and source code statement can be assembled directly with a CPU12 assembler with no modifications.
The CPU12 supports all M68HC11 addressing modes and includes several new variations of indexed addressing mode. CPU12 instructions affect condition code bits in
the same way as M68HC11 instructions.
CPU12 object code is similar to but not identical to M68HC11 object code. Some primary objectives, such as the elimination of the penalty for using Y, could not be
achieved without object code differences. While the object code has been changed,
the majority of the opcodes are identical to those of the M6800, which was developed
more than 20 years earlier.
The CPU12 assembler automatically translates a few M68HC11 instruction mnemonics into functionally equivalent CPU12 instructions. For example, the CPU12 does not
have an increment stack pointer (INS) instruction, so the INS mnemonic is translated
to LEAS 1,S. The CPU12 does provide single-byte DEX, DEY, INX, and INY instructions because the LEAX and LEAY instructions do not affect the condition codes,
while the M68HC11 instructions update the Z bit according to the result of the decrement or increment.
Table B-1 shows M68HC11 instruction mnemonics that are automatically translated
into equivalent CPU12 instructions. This translation is performed by the assembler so
there is no need to modify an old M68HC11 program in order to assemble it for the
CPU12. In fact, the M68HC11 mnemonics can be used in new CPU12 programs.
CPU12
REFERENCE MANUAL
M68HC11 TO M68HC12 UPGRADE PATH
MOTOROLA
B-1
Table B-1 Translated M68HC11 Mnemonics
M68HC11
Mnemonic
Equivalent
CPU12 Instruction
Comments
ABX
ABY
LEAX B,X
LEAY B,Y
Since CPU12 has accumulator offset indexing, ABX and ABY are
rarely used in new CPU12 programs. ABX was one byte on M68HC11
but ABY was two bytes. The LEA substitutes are two bytes.
CLC
CLI
CLV
SEC
SEI
SEV
ANDCC #$FE
ANDCC #$EF
ANDCC #$FD
ORCC #$01
ORCC #$10
ORCC #$02
DES
INS
LEAS –1,S
LEAS 1,S
Unlike DEX and INX, DES and INS did not affect CCR bits in the
M68HC11, so the LEAS equivalents in CPU12 duplicate the function of
DES and INS. These instructions were one byte on M68HC11 and two
bytes on CPU12.
TAP
TPA
TSX
TSY
TXS
TYS
XGDX
XGDY
TFR A,CCR
TFR CCR,A
TFR S,X
TFR S,Y
TFR X,S
TFR Y,S
EXG D,X
EXG D,Y
The M68HC11 had a small collection of specific transfer and exchange
instructions. CPU12 expanded this to allow transfer or exchange
between any two CPU registers. For all but TSY and TYS (which take
two bytes on either CPU), the CPU12 transfer/exchange costs one
extra byte compared to the M68HC11. The substitute instructions execute in one cycle rather than two.
ANDCC and ORCC now allow more control over the CCR, including
the ability to set or clear multiple bits in a single instruction. These
instructions took one byte each on M68HC11 while the ANDCC and
ORCC equivalents take two bytes each.
All of the translations produce the same amount of or slightly more object code than
the original M68HC11 instructions. However, there are offsetting savings in other instructions. Y-indexed instructions in particular assemble into one byte less object
code than the same M68HC11 instruction.
The CPU12 has a two-page opcode map, rather than the four-page M68HC11 map.
This is largely due to redesign of the indexed addressing modes. Most of pages 2, 3,
and 4 of the M68HC11 opcode map are required because Y-indexed instructions use
different opcodes than X-indexed instructions. Approximately two-thirds of the
M68HC11 page 1 opcodes are unchanged in CPU12, and some M68HC11 opcodes
have been moved to page 1 of the CPU12 opcode map. Object code for each of the
moved instructions is one byte smaller than object code for the equivalent M68HC11
instruction. Table B-2 shows instructions that assemble to one byte less object code
on the CPU12.
Instruction set changes offset each other to a certain extent. Programming style also
affects the rate at which instructions appear. As a test, the BUFFALO monitor, an 8Kbyte M68HC11 assembly code program, was reassembled for the CPU12. The resulting object code is six bytes smaller than the M68HC11 code. It is fair to conclude
that M68HC11 code can be reassembled with very little change in size.
MOTOROLA
B-2
M68HC11 TO M68HC12 UPGRADE PATH
CPU12
REFERENCE MANUAL
Table B-2 Instructions with Smaller Object Code
Instruction
DEY
INY
INST n,Y
Comments
Page 2 opcodes in M68HC11 but page 1 in CPU12.
For values of n less than 16 (the majority of cases). Were on page 2, now are on page 1.
Applies to BSET, BCLR, BRSET, BRCLR, NEG, COM, LSR, ROR, ASR, ASL, ROL,
DEC, INC, TST, JMP, CLR, SUB, CMP, SBC, SUBD, ADDD, AND, BIT, LDA, STA, EOR,
ADC, ORA, ADD, JSR, LDS, and STS. If X is the index reference and the offset is greater
than 15 (much less frequent than offsets of 0, 1, and 2), the CPU12 instruction assembles
to one byte more of object code than the equivalent M68HC11 instruction.
PSHY
PULY
Were on page 2, now are on page 1.
LDY
STY
CPY
Were on page 2, now are on page 1.
CPY n,Y
LDY n,Y
STY n,Y
For values of n less than 16 (the majority of cases). Were on page 3, now are on page 1.
CPD
Was on page 2, 3, or 4, now on page 1. In the case of indexed with offset greater than 15,
CPU12 and M68HC11 object code are the same size.
The relative size of code for M68HC11 vs. code for CPU12 has also been tested by
rewriting several smaller programs from scratch. In these cases, the CPU12 code is
typically about 30% smaller. These savings are mostly due to improved indexed addressing.
It seems useful to mention the results of size comparisons done on C programs. A C
program compiled for the CPU12 is about 30% smaller than the same program compiled for the M68HC11. The savings are largely due to better indexing.
B.3 Programmer’s Model and Stacking
The CPU12 programming model and stacking order are identical to those of the
M68HC11.
B.4 True 16-Bit Architecture
The M68HC11 is a direct descendant of the M6800, one of the first microprocessors,
which was introduced in 1974. The M6800 was strictly an 8-bit machine, with 8-bit
data buses and 8-bit instructions. As Motorola devices evolved from the M6800 to the
M68HC11, a number of 16-bit instructions were added, but the data buses remained
eight bits wide, so these instructions were performed as sequences of 8-bit operations. The CPU12 is a true 16-bit implementation, but it retains the ability to work with
the mostly 8-bit M68HC11 instruction set. The larger ALU of the CPU12 (it can perform some 20-bit operations) is used to calculate 16-bit pointers and to speed up
math operations.
CPU12
REFERENCE MANUAL
M68HC11 TO M68HC12 UPGRADE PATH
MOTOROLA
B-3
B.4.1 Bus Structures
The CPU12 is a 16-bit processor with 16-bit data paths. Typical M68HC12 devices
have internal and external 16-bit data paths, but some derivatives incorporate operating modes that allow for an 8-bit data bus, so that a system can be built with low-cost
8-bit program memory. M68HC12 MCUs include an on-chip integration module that
manages the external bus interface. When the CPU makes a 16-bit access to a resource that is served by an 8-bit bus, the integration module performs two 8-bit accesses, freezes the CPU clocks for part of the sequence, and assembles the data into
a 16-bit word. As far as the CPU is concerned, there is no difference between this access and a 16-bit access to an internal resource via the 16-bit data bus. This is similar to the way an M68HC11 can stretch clock cycles to accommodate slow
peripherals.
B.4.2 Instruction Queue
The CPU12 has a two-word instruction queue and a 16-bit holding buffer, which
sometimes acts as a third word for queueing program information. All program information is fetched from memory as aligned 16-bit words, even though there is no requirement for instructions to begin or end on even word boundaries. There is no
penalty for misaligned instructions. If a program begins on an odd boundary (if the reset vector is an odd address), program information is fetched to fill the instruction
queue, beginning with the aligned word at the next address below the misaligned reset vector. The instruction queue logic starts execution with the opcode in the low order half of this word.
The instruction queue causes three bytes of program information (starting with the instruction opcode) to be directly available to the CPU at the beginning of every instruction. As it executes, each instruction performs enough additional program fetches to
refill the space it took up in the queue. Alignment information is maintained by the logic in the instruction queue. The CPU provides signals that tell the queue logic when to
advance a word of program information, and when to toggle the alignment status.
The CPU is not aware of instruction alignment. The queue logic includes a multiplexer
that sorts out the information in the queue to present the opcode and the next two
bytes of information as CPU inputs. The multiplexer determines whether the opcode
is in the even or odd half of the word at the head of the queue. Alignment status is
also available to the ALU for address calculations. The execution sequence for all instructions is independent of the alignment of the instruction.
The only situation where alignment can affect the number of cycles an instruction
takes occurs in devices that have a narrow (8-bit) external data bus, and is related to
optional program fetch cycles (O type cycles). O cycles are always performed, but
serve different purposes determined by instruction size and alignment.
Each instruction includes one program fetch cycle for every two bytes of object code.
Instructions with an odd number of bytes can use an O cycle to fetch an extra word of
object code. If the queue is aligned at the start of an instruction with an odd byte
count, the last byte of object code shares a queue word with the opcode of the next
instruction. Since this word holds part of the next instruction, the queue cannot adMOTOROLA
B-4
M68HC11 TO M68HC12 UPGRADE PATH
CPU12
REFERENCE MANUAL
vance after the odd byte executes, or the first byte of the next instruction would be
lost. In this case, the O cycle appears as a free cycle since the queue is not ready to
accept the next word of program information. If this same instruction had been misaligned, the queue would be ready to advance and the O cycle would be used to perform a program word fetch.
In a single-chip system or in a system with the program in 16-bit memory, both the
free cycle and the program fetch cycle take one bus cycle. In a system with the program in an external 8-bit memory, the O cycle takes one bus cycle when it appears as
a free cycle, but it takes two bus cycles when used to perform a program fetch. In this
case, the on-chip integration module freezes the CPU clocks long enough to perform
the cycle as two smaller accesses. The CPU handles only 16-bit data, and is not
aware that the 16-bit program access is split into two 8-bit accesses.
In order to allow development systems to track events in the CPU12 instruction
queue, two status signals (IPIPE[1:0]) provide information about data movement in
the queue and about the start of instruction execution. A development system can
use this information along with address and data information to externally reconstruct
the queue. This representation of the queue can also track both the data and address
buses.
B.4.3 Stack Function
Both the M68HC11 and the CPU12 stack nine bytes for interrupts. Since this is an
odd number of bytes, there is no practical way to assure that the stack will stay
aligned. To assure that instructions take a fixed number of cycles regardless of stack
alignment, the internal RAM in M68HC12 MCUs is designed to allow single cycle 16bit accesses to misaligned addresses. As long as the stack is located in this special
RAM, stacking and unstacking operations take the same amount of execution time,
regardless of stack alignment. If the stack is located in an external 16-bit RAM, a
PSHX instruction can take two or three cycles depending upon the alignment of the
stack. This extra access time is transparent to the CPU because the integration module freezes the CPU clocks while it performs the extra 8-bit bus cycle required for a
misaligned stack operation.
The CPU12 has a “last-used” stack rather than a “next-available” stack like the
M68HC11 CPU. That is, the stack pointer points to the last 16-bit stack address used,
rather than to the address of the next available stack location. This generally has very
little effect, because it is very unusual to access stacked information using absolute
addressing. The change allows a 16-bit word of data to be removed from the stack
without changing the value of the SP twice.
To illustrate, consider the operation of a PULX instruction. With the next-available
M68HC11 stack, if the SP = $01F0 when execution begins, the sequence of operations is: SP = SP + 1; load X from $01F1:01F2; SP = SP + 1; and the SP ends up at
$01F2. With the last-used CPU12 stack, if the SP = $01F0 when execution begins,
the sequence is: load X from $01F0:01F1; SP = SP + 2; and the SP again ends up at
$01F2. The second sequence requires one less stack pointer adjustment.
CPU12
REFERENCE MANUAL
M68HC11 TO M68HC12 UPGRADE PATH
MOTOROLA
B-5
The stack pointer change also affects operation of the TSX and TXS instructions. In
the M68HC11, TSX increments the SP by one during the transfer. This adjustment
causes the X index to point to the last stack location used. The TXS instruction operates similarly, except that it decrements the SP by one during the transfer. CPU12
TSX and TXS instructions are ordinary transfers — the CPU12 stack requires no adjustment.
For ordinary use of the stack, such as pushes, pulls, and even manipulations involving TSX and TXS, there are no differences in the way the M68HC11 and the CPU12
stacks look to a programmer. However, the stack change can affect a program algorithm in two subtle ways.
The LDS #$xxxx instruction is normally used to initialize the stack pointer at the start
of a program. In the M68HC11, the address specified in the LDS instruction is the first
stack location used. In the CPU12, however, the first stack location used is one address lower than the address specified in the LDS instruction. Since the stack builds
downward, M68HC11 programs reassembled for the CPU12 operate normally, but
the program stack is one physical address lower in memory.
In very uncommon situations, such as test programs used to verify CPU operation, a
program could initialize the SP, stack data, and then read the stack via an extended
mode read (it is normally improper to read stack data from an absolute extended address). To make an M68HC11 source program that contains such a sequence work
on the CPU12, change either the initial LDS #$xxxx, or the absolute extended address used to read the stack.
B.5 Improved Indexing
The CPU12 has significantly improved indexed addressing capability, yet retains
compatibility with the M68HC11. The one cycle and one byte cost of doing Y-related
indexing in the M68HC11 has been eliminated. In addition, high level language requirements, including stack relative indexing and the ability to perform pointer arithmetic directly in the index registers, have been accommodated.
The M68HC11 has one variation of indexed addressing that works from X or Y as the
reference pointer. For X indexed addressing, an 8-bit unsigned offset in the instruction is added to the index pointer to arrive at the address of the operand for the instruction. A load accumulator instruction assembles into two bytes of object code, the
opcode and a 1-byte offset. Using Y as the reference, the same instruction assembles into three bytes (a page prebyte, the opcode, and a one-byte offset.) Analysis of
M68HC11 source code indicates that the offset is most frequently zero and very seldom greater than four.
The CPU12 indexed addressing scheme uses a postbyte plus 0, 1, or 2 extension
bytes after the instruction opcode. These bytes specify which index register is used,
determine whether an accumulator is used as the offset, implement automatic pre/
post increment/decrement of indices, and allow a choice of 5-, 9-, or 16-bit signed offsets. This approach eliminates the differences between X and Y register use and dramatically enhances indexed addressing capabilities.
MOTOROLA
B-6
M68HC11 TO M68HC12 UPGRADE PATH
CPU12
REFERENCE MANUAL
Major improvements that result from this new approach are:
• Stack pointer can be used as an index register in all indexed operations
• Program counter can be used as index register in all but auto inc/dec modes
• Accumulator offsets allowed using A, B, or D accumulators
• Automatic pre- or post-, increment or decrement (by –8 to +8)
• 5-bit, 9-bit, or 16-bit signed constant offsets
• 16-bit offset indexed-indirect and accumulator D offset indexed-indirect
The change completely eliminates pages three and four of the M68HC11 opcode
map and eliminates almost all instructions from page two of the opcode map. For offsets of +0 to +15 from the X index register, the object code is the same size as it was
for the M68HC11. For offsets of +0 to +15 from the Y index register, the object code is
one byte smaller than it was for the M68HC11.
Table A-5 summarizes M68HC12 indexed addressing mode capabilities. Table A-3
shows how the postbyte is encoded.
B.5.1 Constant Offset Indexing
The CPU12 offers three variations of constant offset indexing in order to optimize the
efficiency of object code generation.
The most common constant offset is zero. Offsets of 1, 2,…4 are used fairly often, but
with less frequency than zero.
The 5-bit constant offset variation covers the most frequent indexing requirements by
including the offset in the postbyte. This reduces a load accumulator indexed instruction to two bytes of object code, and matches the object code size of the smallest
M68HC11 indexed instructions, which can only use X as the index register. The
CPU12 can use X, Y, SP, or PC as the index reference with no additional object code
size cost.
The signed 9-bit constant offset indexing mode covers the same positive range as the
M68HC11 8-bit unsigned offset. The size was increased to nine bits with the sign bit
(ninth bit) included in the postbyte, and the remaining 8-bits of the offset in a single
extension byte.
The 16-bit constant offset indexing mode allows indexed access to the entire normal
64-Kbyte address space. Since the address consists of 16 bits, the 16-bit offset can
be regarded as a signed (–32,768 to +32767) or unsigned (0 to 65,535) value. In 16bit constant offset mode, the offset is supplied in two extension bytes after the opcode
and postbyte.
CPU12
REFERENCE MANUAL
M68HC11 TO M68HC12 UPGRADE PATH
MOTOROLA
B-7
B.5.2 Auto-Increment Indexing
The CPU12 provides greatly enhanced auto increment and decrement modes of indexed addressing. In the CPU12, the index modification may be specified for before
the index is used (pre-), or after the index is used (post-), and the index can be incremented or decremented by any amount from one to eight, independent of the size of
the operand that was accessed. X, Y, and SP can be used as the index reference, but
this mode does not allow PC to be the index reference (this would interfere with proper program execution).
This addressing mode can be used to implement a software stack structure, or to manipulate data structures in lists or tables, rather than manipulating bytes or words of
data. Anywhere an M68HC11 program has an increment or decrement index register
operation near an indexed mode instruction, the increment or decrement operation
can be combined with the indexed instruction with no cost in object code size, as
shown in the following code comparison.
18 A6 00
18 08
18 08
LDAA 0,Y
INY
INY
A6 71
LDAA 2,Y+
The M68HC11 object code requires seven bytes, while the CPU12 requires only two
bytes to accomplish the same functions. Three bytes of M68HC11 code were due to
the page prebyte for each Y-related instruction ($18). CPU12 post-increment indexing
capability allowed the two INY instructions to be absorbed into the LDAA indexed
instruction. The replacement code is not identical to the original three instruction sequence because the Z condition code bit is affected by the M68HC11 INY instructions, while the Z bit in the CPU12 would be determined by the value loaded into A.
B.5.3 Accumulator Offset Indexing
This indexed addressing variation allows the programmer to use either an 8-bit accumulator (A or B), or the 16-bit D accumulator as the offset for indexed addressing.
This allows for a program-generated offset, which is more difficult to achieve in the
M68HC11. The following code compares the M68HC11 and CPU12 operations.
C6 05
CE 10 00
3A
A6 00
5A
26 F7
LDAB
LOOP LDX
ABX
LDAA
|
DECB
BNE
#$5
[2]
#$1000 [3]
[3]
0,X
[4]
C6 05
CE 10 00
A6 E5
04 31 FB
LOOP
LDAB
LDX
LOOP LDAA
|
DBNE
#$5
#$1000
B,X
[1]
[2]
[3]
B,LOOP
[3]
[2]
[3]
The CPU12 object code is only one byte smaller, but the LDX # instruction is outside
the loop. It is not necessary to reload the base address in the index register on each
pass through the loop because the LDAA B,X instruction does not alter the index
register. This reduces the loop execution time from 15 cycles to six cycles. This reduction, combined with the 8-MHz bus speed of the M68HC12 family, can have significant effects.
MOTOROLA
B-8
M68HC11 TO M68HC12 UPGRADE PATH
CPU12
REFERENCE MANUAL
B.5.4 Indirect Indexing
The CPU12 allows some forms of indexed indirect addressing where the instruction
points to a location in memory where the address of the operand is stored. This is an
extra level of indirection compared to ordinary indexed addressing. The two forms of
indexed indirect addressing are 16-bit constant offset indexed indirect and D accumulator indexed indirect. The reference index register can be X, Y, SP, or PC as in other
CPU12 indexed addressing modes. PC-relative indirect addressing is one of the more
common uses of indexed indirect addressing. The indirect variations of indexed addressing help in the implementation of pointers. D accumulator indexed indirect addressing can be used to implement a runtime computed GOTO function. Indirect
addressing is also useful in high level language compilers. For instance, PC-relative
indirect indexing can be used to efficiently implement some C case statements.
B.6 Improved Performance
The CPU12 improves on M68HC11 performance in several ways. M68HC12 devices
are designed using sub-micron design rules, and fabricated using advanced semiconductor processing, the same methods used to manufacture the M68HC16 and
M68300 families of modular microcontrollers. M68HC12 devices have a base bus
speed of eight MHz, and are designed to operate over a wide range of supply voltages. The 16-bit wide architecture also increases performance. Beyond these obvious
improvements, the CPU12 uses a reduced number of cycles for many of its instructions, and a 20-bit ALU makes certain CPU12 math operations much faster.
B.6.1 Reduced Cycle Counts
No M68HC11 instruction takes less than two cycles, but the CPU12 has more than 50
opcodes that take only one cycle. Some of the reduction comes from the instruction
queue, which assures that several program bytes are available at the start of each instruction. Other cycle reductions occur because the CPU12 can fetch 16 bits of information at a time, rather than eight bits at a time.
B.6.2 Fast Math
The CPU12 has some of the fastest math ever designed into a Motorola general-purpose MCU. Much of the speed is due to a 20-bit ALU that can perform two smaller operations simultaneously. The ALU can also perform two operations in a single bus
cycle in certain cases. Table B-3 compares the speed of CPU12 and M68HC11 math
instructions. The CPU12 requires fewer cycles to perform an operation, and the cycle
time is half that of the M68HC11.
CPU12
REFERENCE MANUAL
M68HC11 TO M68HC12 UPGRADE PATH
MOTOROLA
B-9
Table B-3 Comparison of Math Instruction Speeds
Instruction
Mnemonic
Math
Operation
M68HC11
1 Cycle = 250
ns
M68HC11
CPU12
w/Coprocessor
1 Cycle = 125 ns
1 Cycle = 250 ns
MUL
8 × 8 = 16
(signed)
10 cycles
—
3 cycles
EMUL
16 × 16 = 32
(unsigned)
—
20 cycles
3 cycles
EMULS
16 × 16 = 32
(signed)
—
20 cycles
3 cycles
IDIV
16 ÷ 16 = 16
(unsigned)
41 cycles
—
12 cycles
FDIV
16 ÷ 16 = 16
(fractional)
41 cycles
—
12 cycles
EDIV
32 ÷ 16 = 16
(unsigned)
—
33 cycles
11 cycles
EDIVS
32 ÷ 16 = 16
(signed)
—
37 cycles
12 cycles
IDIVS
16 ÷ 16 = 16
(signed)
—
—
12 cycles
EMACS
32 × (16 × 16) ⇒ 32
(signed MAC)
—
20 cycles
12 cycles
The IDIVS instruction is included specifically for C compilers, where word-sized operands are divided to produce a word-sized result (unlike the 32 ÷ 16 = 16 EDIV). The
EMUL and EMULS instructions place the result in registers so a C compiler can
choose to use only 16 bits of the 32-bit result.
B.6.3 Code Size Reduction
CPU12 assembly language programs written from scratch tend to be 30% smaller
than equivalent programs written for the M68HC11. This figure has been independently qualified by Motorola programmers and an independent C compiler vendor.
The major contributors to the reduction appear to be improved indexed addressing
and the universal transfer/exchange instruction.
In some specialized areas, the reduction is much greater. A fuzzy logic inference kernel requires about 250 bytes in the M68HC11, and the same program for the CPU12
requires about 50 bytes. The CPU12 fuzzy logic instructions replace whole subroutines in the M68HC11 version. Table lookup instructions also greatly reduce code
space.
Other CPU12 code space reductions are more subtle. Memory to memory moves are
one example. The CPU12 move instruction requires almost as many bytes as an
equivalent sequence of M68HC11 instructions, but the move operations themselves
do not require the use of an accumulator. This means that the accumulator often
need not be saved and restored, which saves instructions.
MOTOROLA
B-10
M68HC11 TO M68HC12 UPGRADE PATH
CPU12
REFERENCE MANUAL
Arithmetic on index pointers is another example. The M68HC11 usually requires that
the content of the index register be moved into accumulator D, where calculations are
performed, then back to the index register before indexing can take place. In the
CPU12, the LEAS, LEAX, and LEAY instructions perform arithmetic operations directly on the index pointers. The pre-/post-increment/decrement variations of indexed addressing also allow index modification to be incorporated into an existing indexed
instruction rather than performing the index modification as a separate operation.
Transfer and exchange operations often allow register contents to be temporarily
saved in another register rather than having to save the contents in memory. Some
CPU12 instructions such as MIN and MAX combine the actions of several M68HC11
instructions into a single operation.
B.7 Additional Functions
The CPU12 incorporates a number of new instructions that provide added functionality and code efficiency. Among other capabilities, these new instructions allow efficient processing for fuzzy logic applications and support subroutine processing in
extended memory beyond the standard 64-Kbyte address map for M68HC12 devices
incorporating this feature. Table B-4 is a summary of these new instructions. Subsequent paragraphs discuss significant enhancements.
Table B-4 New M68HC12 Instructions
Mnemonic
ANDCC
BCLR
BGND
BRCLR
BRSET
BSET
Addressing Modes
Immediate
Extended
Inherent
Extended
Extended
Extended
CALL
Extended, Indexed
CPS
DBNE
DBEQ
EDIV
EDIVS
EMACS
EMAXD
EMAXM
EMIND
EMINM
EMUL
EMULS
ETBL
EXG
IBEQ
IBNE
IDIVS
Immediate, Direct,
Extended, and Indexed
Relative
Relative
Inherent
Inherent
Special
Indexed
Indexed
Indexed
Indexed
Special
Special
Special
Inherent
Relative
Relative
Inherent
CPU12
REFERENCE MANUAL
Brief Functional Description
AND CCR with Mask (replaces CLC, CLI, and CLV)
Bit(s) Clear (added extended mode)
Enter Background Debug Mode, if enabled
Branch if Bit(s) Clear (added extended mode)
Branch if Bit(s) Set (added extended mode)
Bit(s) Set (added extended mode)
Similar to JSR Except also Stacks PPAGE Value
With RTC instruction, allows easy access to >64-Kbyte space
Compare Stack Pointer
Decrement and Branch if Equal to Zero (Looping Primitive)
Decrement and Branch if Not Equal to Zero (Looping Primitive)
Extended Divide Y:D/X = Y(Q) and D(R) (Unsigned)
Extended Divide Y:D/X = Y(Q) and D(R) (Signed)
Multiply and Accumulate 16 × 16 ⇒ 32 (Signed)
Maximum of Two Unsigned 16-Bit Values
Maximum of Two Unsigned 16-Bit Values
Minimum of Two Unsigned 16-Bit Values
Minimum of Two Unsigned 16-Bit Values
Extended Multiply 16 × 16 ⇒ 32; M(idx) ∗ D ⇒ Y:D
Extended Multiply 16 × 16 ⇒ 32 (signed); M(idx) ∗ D ⇒ Y:D
Table Lookup and Interpolate (16-bit entries)
Exchange Register Contents
Increment and Branch if Equal to Zero (Looping Primitive)
Increment and Branch if Not Equal to Zero (Looping Primitive)
Signed Integer Divide D/X ⇒ X(Q) and D(R) (Signed)
M68HC11 TO M68HC12 UPGRADE PATH
MOTOROLA
B-11
Table B-4 New M68HC12 Instructions (Continued)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBHS
LBLE
LBLO
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
LEAS
LEAX
LEAY
MAXA
MAXM
MEM
MINA
MINM
ORCC
PSHC
PSHD
PULC
PULD
REV
REVW
Addressing Modes
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Indexed
Indexed
Indexed
Indexed
Indexed
Special
Indexed
Indexed
Combinations of
Immediate, Extended,
and Indexed
Immediate
Inherent
Inherent
Inherent
Inherent
Special
Special
RTC
Inherent
SEX
TBEQ
TBL
TBNE
TFR
WAV
Inherent
Relative
Inherent
Relative
Inherent
Special
MOVB(W)
MOTOROLA
B-12
Brief Functional Description
Long Branch if Carry Clear (Same as LBHS)
Long Branch if Carry Set (Same as LBLO)
Long Branch if Equal (Z=1)
Long Branch if Greater than or Equal to Zero
Long Branch if Greater than Zero
Long Branch if Higher
Long Branch if Higher or Same (Same as LBCC)
Long Branch if Less than or Equal to Zero
Long Branch if Lower (Same as LBCS)
Long Branch if Lower or Same
Long Branch if Less than Zero
Long Branch if Minus
Long Branch if Not Equal to Zero
Long Branch if Plus
Long Branch Always
Long Branch Never
Long Branch if Overflow Clear
Long Branch if Overflow Set
Load Stack Pointer with Effective Address
Load X Index Register with Effective Address
Load Y Index Register with Effective Address
Maximum of Two Unsigned 8-Bit Values
Maximum of Two Unsigned 8-Bit Values
Determine Grade of Fuzzy Membership
Minimum of Two Unsigned 8-Bit Values
Minimum of Two Unsigned 8-Bit Values
Move Data from One Memory Location to Another
OR CCR with Mask (replaces SEC, SEI, and SEV)
Push CCR onto Stack
Push Double Accumulator onto Stack
Pull CCR Contents from Stack
Pull Double Accumulator from Stack
Fuzzy Logic Rule Evaluation
Fuzzy Logic Rule Evaluation with Weights
Restore Program Page and Return Address from Stack
Used with CALL Instruction, Allows Easy Access to >64-Kbyte Space
Sign Extend 8-bit Register into 16-bit Register
Test and Branch if Equal to Zero (Looping Primitive)
Table Lookup and Interpolate (8-bit Entries)
Test Register and Branch if Not Equal to Zero (Looping Primitive)
Transfer Register Contents to Another Register
Weighted Average (Fuzzy Logic Support)
M68HC11 TO M68HC12 UPGRADE PATH
CPU12
REFERENCE MANUAL
B.7.1 Memory-to-Memory Moves
The CPU12 has both 8- and 16-bit variations of memory-to-memory move instructions. The source address can be specified with immediate, extended, or indexed addressing modes. The destination address can be specified by extended or indexed
addressing mode. The indexed addressing mode for move instructions is limited to
modes that require no extension bytes (9- and 16-bit constant offsets are not allowed), and indirect indexing is not allowed for moves. This leaves a 5-bit signed constant offset, accumulator offsets, and the automatic increment/decrement modes.
The following simple loop is a block move routine capable of moving up to 256 words
of information from one memory area to another.
LOOP
MOVW
DBNE
2,X+ , 2,Y+ ;move a word and update pointers
B,LOOP
;repeat B times
The move immediate to extended is a convenient way to initialize a register without
using an accumulator or affecting condition codes.
B.7.2 Universal Transfer and Exchange
The M68HC11 has only eight transfer instructions and two exchange instructions.
The CPU12 has a universal transfer/exchange instruction that can be used to transfer
or exchange data between any two CPU registers. The operation is obvious when the
two registers are the same size, but some of the other combinations provide very
useful results. For example when an 8-bit register is transferred to a 16-bit register, a
sign-extend operation is performed. Other combinations can be used to perform a
zero-extend operation.
These instructions are used often in CPU12 assembly language programs. Transfers
can be used to make extra copies of data in another register, and exchanges can be
used to temporarily save data during a call to a routine that expects data in a specific
register. This is sometimes faster and produces more compact object code than saving data to memory with pushes or stores.
B.7.3 Loop Construct
The CPU12 instruction set includes a new family of six loop primitive instructions.
These instructions decrement, increment, or test a loop count in a CPU register and
then branch based on a zero or non-zero test result. The CPU registers that can be
used for the loop count are A, B, D, X, Y, or SP. The branch range is a 9-bit signed value (–512 to +511) which gives these instructions twice the range of a short branch instruction.
B.7.4 Long Branches
All of the branch instructions from the M68HC11 are also available with 16-bit offsets
which allows them to reach any location in the 64-Kbyte address space.
CPU12
REFERENCE MANUAL
M68HC11 TO M68HC12 UPGRADE PATH
MOTOROLA
B-13
B.7.5 Minimum and Maximum Instructions
Control programs often need to restrict data values within upper and lower limits. The
CPU12 facilitates this function with 8- and 16-bit versions of MIN and MAX instructions. Each of these instructions has a version that stores the result in either the accumulator or in memory.
For example, in a fuzzy logic inference program, rule evaluation consists of a series of
MIN and MAX operations. The min operation is used to determine the smallest rule
input (the running result is held in an accumulator), and the max operation is used to
store the largest rule truth value (in an accumulator) or the previous fuzzy output value (in a RAM location), to the fuzzy output in RAM. The following code demonstrates
how MIN and MAX instructions can be used to evaluate a rule with four inputs and
two outputs.
LDY
LDX
LDAA
MINA
MINA
MINA
MINA
MAXM
MAXM
#OUT1
#IN1
#$FF
1,X+
1,X+
1,X+
1,X+
1,Y+
1,Y+
;Point at first output
;Point at first input value
;start with largest 8-bit number in A
;A=MIN(A,IN1)
;A=MIN(A,IN2)
;A=MIN(A,IN3)
;A=MIN(A,IN4) so A holds smallest input
;OUT1=MAX(A,OUT1) and A is unchanged
;OUT1=MAX(A,OUT2) A still has min input
Before this sequence is executed, the fuzzy outputs must be cleared to zeros (not
shown). M68HC11 MIN or MAX operations are performed by executing a compare
followed by a conditional branch around a load or store operation.
These instructions can also be used to limit a data value prior to using it as an input to
a table lookup or other routine. Suppose a table is valid for input values between $20
and $7F. An arbitrary input value can be tested against these limits and be replaced
by the largest legal value if it is too big, or the smallest legal value if too small using
the following two CPU12 instructions.
HILIMIT FCB
LOWLIMIT FCB
MINA
MAXA
$7F
;comparison value needs to be in mem
$20
;so it can be referenced via indexed
HILIMIT,PCR ;A=MIN(A,$7F)
LOWLIMIT,PCR;A=MAX(A,$20)
;A now within the legal range $20 to $7F
The “,PCR” notation is also new for the CPU12. This notation indicates the programmer wants an appropriate offset from the PC reference to the memory location
(HILIMIT or LOWLIMIT in this example), and then to assemble this instruction into a
PC-relative indexed MIN or MAX instruction.
B.7.6 Fuzzy Logic Support
The CPU12 includes four instructions (MEM, REV, REVW, and WAV) specifically designed to support fuzzy logic programs. These instructions have a very small impact
on the size of the CPU, and even less impact on the cost of a complete MCU. At the
same time these instructions dramatically reduce the object code size and execution
time for a fuzzy logic inference program. A kernel written for the M68HC11 required
about 250 bytes and executed in about 750 milliseconds. The CPU12 kernel uses
about 50 bytes and executes in about 50 microseconds.
MOTOROLA
B-14
M68HC11 TO M68HC12 UPGRADE PATH
CPU12
REFERENCE MANUAL
B.7.7 Table Lookup and Interpolation
The CPU12 instruction set includes two instructions (TBL and ETBL) for lookup and
interpolation of compressed tables. Consecutive table values are assumed to be the x
coordinates of the endpoints of a line segment. The TBL instruction uses 8-bit table
entries (y-values) and returns an 8-bit result. The ETBL instruction uses 16-bit table
entries (y-values) and returns a 16-bit result.
An indexed addressing mode is used to identify the effective address of the data point
at the beginning of the line segment, and the data value for the end point of the line
segment is the next consecutive memory location (byte for TBL and word for ETBL).
In both cases, the B accumulator represents the ratio of (the x-distance from the beginning of the line segment to the lookup point) to (the x-distance from the beginning
of the line segment to the end of the line segment). B is treated as an 8-bit binary
fraction with radix point left of the MSB, so each line segment is effectively divided
into 256 pieces. During execution of the TBL or ETBL instruction, the difference between the end point y-value and the beginning point y-value (a signed byte for TBL or
a signed word for ETBL) is multiplied by the B accumulator to get an intermediate
delta-y term. The result is the y-value of the beginning point, plus this signed intermediate delta-y value.
B.7.8 Extended Bit Manipulation
The M68HC11 CPU only allows direct or indexed addressing. This typically causes
the programmer to dedicate an index register to point at some memory area such as
the on-chip registers. The CPU12 allows all bit manipulation instructions to work with
direct, extended or indexed addressing modes.
B.7.9 Push and Pull D and CCR
The CPU12 includes instructions to push and pull the D accumulator and the CCR. It
is interesting to note that the order in which 8-bit accumulators A and B are stacked
for interrupts is the opposite of what would be expected for the upper and lower bytes
of the 16-bit D accumulator. The order used originated in the M6800, an 8-bit microprocessor developed long before anyone thought 16-bit single-chip devices would be
made. The interrupt stacking order for accumulators A and B is retained for code
compatibility.
B.7.10 Compare SP
This instruction was added to the CPU12 instruction set to improve orthogonality and
high-level language support. One of the most important requirements for C high-level
language support is the ability to do arithmetic on the stack pointer for such things as
allocating local variable space on the stack. The LEAS –5,SP instruction is an example of how the compiler could easily allocate five bytes on the stack for local variables.
LDX 5,SP+ loads X with the value on the bottom of the stack and deallocates five
bytes from the stack in a single operation that takes only two bytes of object code.
CPU12
REFERENCE MANUAL
M68HC11 TO M68HC12 UPGRADE PATH
MOTOROLA
B-15
B.7.11 Support for Memory Expansion
Bank switching is a common method of expanding memory beyond the 64-Kbyte limit
of a CPU with a 64-Kbyte address space, but there are some known difficulties associated with bank switching. One problem is that interrupts cannot take place during
the bank switching operation. This increases worst case interrupt latency and requires extra programming space and execution time.
Some M68HC12 variants include a built-in bank switching scheme that eliminates
many of the problems associated with external switching logic. The CPU12 includes
CALL and return from call (RTC) instructions that manage the interface to the bankswitching system. These instructions are analogous to the JSR and RTS instructions,
except that the bank page number is saved and restored automatically during execution. Since the page change operation is part of an uninterruptable instruction, many
of the difficulties associated with bank switching are eliminated. On M68HC12 derivatives with expanded memory capability, bank numbers are specified by on-chip control registers. Since the addresses of these control registers may not be the same in
all M68HC12 derivatives, the CPU12 has a dedicated control line to the on-chip integration module that indicates when a memory-expansion register is being read or
written. This allows the CPU to access the PPAGE register without knowing the register address.
The indexed indirect versions of the CALL instruction access the address of the
called routine and the destination page value indirectly. For other addressing mode
variations of the CALL instruction, the destination page value is provided as immediate data in the instruction object code. CALL and RTC execute correctly in the normal
64-Kbyte address space, thus providing for portable code.
MOTOROLA
B-16
M68HC11 TO M68HC12 UPGRADE PATH
CPU12
REFERENCE MANUAL
APPENDIX C
HIGH-LEVEL LANGUAGE SUPPORT
Many programmers are turning to high-level languages such as C as an alternative to
coding in native assembly languages. High-level language (HLL) programming can
improve productivity and produce code that is more easily maintained than assembly
language programs. The most serious drawback to the use of HLL in MCUs has been
the relatively large size of programs written in HLL. Larger program ROM size requirements translate into increased system costs.
Motorola solicited the cooperation of third-party software developers to assure that the
CPU12 instruction set would meet the needs of a more efficient generation of compilers. Several features of the CPU12 were specifically designed to improve the efficiency of compiled HLL, and thus minimize cost.
This appendix identifies CPU12 instructions and addressing modes that provide improved support for high-level language. C language examples are provided to demonstrate how these features support efficient HLL structures and concepts. Since the
CPU12 instruction set is a superset of the M68HC11 instruction set, some of the discussions use the M68HC11 as a basis for comparison.
C.1 Data Types
The CPU12 supports the bit-sized data type with bit manipulation instructions which
are available in extended, direct, and indexed variations. The char data type is a simple 8-bit value that is commonly used to specify variables in a small microcontroller
system because it requires less memory space than a 16-bit integer (provided the variable has a range small enough to fit into eight bits). The 16-bit CPU12 can easily handle 16-bit integer types and the available set of conditional branches (including long
branches) allow branching based on signed or unsigned arithmetic results. Some of
the higher math functions allow for division and multiplication involving 32-bit values,
although it is somewhat less common to use such long values in a microcontroller system.
The CPU12 has special sign extension instructions to allow easy type-casting from
smaller data types to larger ones, such as from char to integer. This sign extension is
automatically performed when an 8-bit value is transferred to a 16-bit register.
C.2 Parameters and Variables
High-level languages make extensive use of the stack, both to pass variables and for
temporary and local storage. It follows that there should be easy ways to push and pull
all CPU registers, stack pointer based indexing should be allowed, and that direct
arithmetic manipulation of the stack pointer value should be allowed. The CPU12 instruction set provided for all of these needs with improved indexed addressing, the addition of an LEAS instruction, and the addition of push and pull instructions for the D
accumulator and the CCR.
CPU12
REFERENCE MANUAL
HIGH-LEVEL LANGUAGE SUPPORT
MOTOROLA
C-1
C.2.1 Register Pushes and Pulls
The M68HC11 has push and pull instructions for A, B, X, and Y, but requires separate
8-bit pushes and pulls of accumulators A and B to stack or unstack the 16-bit D accumulator (the concatenated combination of A:B). The PSHD and PULD instructions allow directly stacking the D accumulator in the expected 16-bit order.
Adding PSHC and PULC improved orthogonality by completing the set of stacking instructions so that any of the CPU registers can be pushed or pulled. These instructions
are also useful for preserving the CCR value during a function call subroutine.
C.2.2 Allocating and Deallocating Stack Space
The LEAS instruction can be used to allocate or deallocate space on the stack for temporary variables:
LEAS
–10,S
;Allocate space for 5 16-bit integers
LEAS
10,S
;Deallocate space for 5 16-bit ints
The (de)allocation can even be combined with a register push or pull as in the following
example:
LDX
8,S+
;Load return value and deallocate
X is loaded with the 16-bit integer value at the top of the stack, and the stack pointer
is adjusted up by eight to deallocate space for eight bytes worth of temporary storage.
Post-increment indexed addressing is used in this example, but all four combinations
of pre/post increment/decrement are available (offsets from –8 to +8 inclusive, from X,
Y, or SP). This form of indexing can often be used to get an index (or stack pointer)
adjustment for free during an indexed operation (the instruction requires no more code
space or cycles than a zero-offset indexed instruction).
C.2.3 Frame Pointer
In the C language, it is common to have a frame pointer in addition to the CPU stack
pointer. The frame is an area of memory within the system stack which is used for parameters and local storage of variables used within a function subroutine. The following is a description of how a frame pointer can be set up and used.
First, parameters (typically values in CPU registers) are pushed onto the system stack
prior to using a JSR or CALL to get to the function subroutine. At the beginning of the
called subroutine, the frame pointer of the calling program is pushed onto the stack.
Typically, an index register, such as X, is used as the frame pointer, so a PSHX instruction would save the frame pointer from the calling program.
Next, the called subroutine establishes a new frame pointer by executing a TFR S,X.
Space is allocated for local variables by executing an LEAS –n,S, where n is the number of bytes needed for local variables.
MOTOROLA
C-2
HIGH-LEVEL LANGUAGE SUPPORT
CPU12
REFERENCE MANUAL
Notice that parameters are at positive offsets from the frame pointer while locals are
at negative offsets. In the M68HC11, the indexed addressing mode uses only positive
offsets, so the frame pointer always points to the lowest address of any parameter or
local. After the function subroutine finishes, calculations are required to restore the
stack pointer to the mid-frame position between the locals and the parameters before
returning to the calling program. The CPU12 only requires execution of TFR X,S to
deallocate the local storage and return.
The concept of a frame pointer is supported in the CPU12 through a combination of
improved indexed addressing, universal transfer/exchange, and the LEA instruction.
These instructions work together to achieve more efficient handling of frame pointers.
It is important to consider the complete instruction set as a complex system with subtle
interrelationships rather than simply examining individual instructions when trying to
improve an instruction set. Adding or removing a single instruction can have unexpected consequences.
C.3 Increment and Decrement Operators
In C, the notation + + i or i – – is often used to form loop counters. Within limited constraints, the CPU12 loop primitives can be used to speed up the loop count and branch
function.
The CPU12 includes a set of six basic loop control instructions which decrement, increment, or test a loop count register, and then branch if it is either equal to zero or not
equal to zero. The loop count register can be A, B, D, X, Y, or SP. A or B could be used
if the loop count fits in an 8-bit char variable; the other choices are all 16-bit registers.
The relative offset for the loop branch is a 9-bit signed value, so these instructions can
be used with loops as long as 256 bytes.
In some cases, the pre- or post-increment operation can be combined with an indexed
instruction to eliminate the cost of the increment operation. This is typically done by
post-compile optimization because the indexed instruction that could absorb the increment/decrement operation may not be apparent at compile time.
C.4 Higher Math Functions
In the CPU12, subtle characteristics of higher math operations such as IDIVS and
EMUL are arranged so a compiler can handle inputs and outputs more efficiently.
The most apparent case is the IDIVS instruction, which divides two 16-bit signed numbers to produce a 16-bit result. While the same function can be accomplished with the
EDIVS instruction (a 32 by 16 divide), doing so is much less efficient because extra
steps are required to prepare inputs to the EDIVS, and because EDIVS uses the Y index register. EDIVS uses a 32-bit signed numerator and the C compiler would typically
want to use a 16-bit value (the size of an integer data type). The 16-bit C value would
need to be sign-extended into the upper 16-bits of the 32-bit EDIVS numerator before
the divide operation.
CPU12
REFERENCE MANUAL
HIGH-LEVEL LANGUAGE SUPPORT
MOTOROLA
C-3
Operand size is also a potential problem in the extended multiply operations but the
difficulty can be minimized by putting the results in CPU registers. Having higher precision math instructions is not necessarily a requirement for supporting high-level language because these functions can be performed as library functions. However, if an
application requires these functions, the code is much more efficient if the MCU can
use native instructions instead of relatively large, slow routines.
C.5 Conditional If Constructs
In the CPU12 instruction set, most arithmetic and data manipulation instructions automatically update the condition code register, unlike other architectures that only
change condition codes during a few specific compare instructions. The CPU12 includes branch instructions that perform conditional branching based on the state of the
indicators in the condition codes register. Short branches use a single byte relative offset that allows branching to a destination within about ±128 locations from the branch.
Long branches use a 16-bit relative offset that allows conditional branching to any location in the 64-Kbyte map.
C.6 Case and Switch Statements
Case and switch statements (and computed GOTOs) can use PC-relative indirect addressing to determine which path to take. Depending upon the situation, cases can
use either the constant offset variation or the accumulator D offset variation of indirect
indexed addressing.
C.7 Pointers
The CPU12 supports pointers by allowing direct arithmetic operations on the 16-bit index registers (LEAS, LEAX, and LEAY instructions) and by allowing indexed indirect
addressing modes.
C.8 Function Calls
Bank switching is a fairly common way of adapting a CPU with a 16-bit address bus to
accommodate more than 64-Kbytes of program memory space. One of the most significant drawbacks of this technique has been the requirement to mask (disable) interrupts while the bank page value was being changed. Another problem is that the
physical location of the bank page register can change from one MCU derivative to another (or even due to a change to mapping controls by a user program). In these situations, an operating system program has to keep track of the physical location of the
page register. The CPU12 addresses both of these problems with the uninterruptible
CALL and return from call (RTC) instructions.
The CALL instruction is similar to a JSR instruction, except that the programmer supplies a destination page value as part of the instruction. When CALL executes, the old
page value is saved on the stack and the new page value is written to the bank page
register. Since the CALL instruction is uninterruptible, this eliminates the need to separately mask off interrupts during the context switch.
MOTOROLA
C-4
HIGH-LEVEL LANGUAGE SUPPORT
CPU12
REFERENCE MANUAL
The CPU12 has dedicated signal lines that allow the CPU to access the bank page
register without having to use an address in the normal 64-Kbyte address space. This
eliminates the need for the program to know where the page register is physically located.
The RTC instruction is similar to the RTS instruction, except that RTC uses the byte
of information that was saved on the stack by the corresponding CALL instruction to
restore the bank page register to its old value. Although a CALL/RTC pair can be used
to access any function subroutine regardless of the location of the called routine (on
the current bank page or a different page), it is most efficient to access some subroutines with JSR/RTS instructions when the called subroutine is on the current page or
in an area of memory that is always visible in the 64-Kbyte map regardless of the bank
page selection.
Push and pull instructions can be used to stack some or all the CPU registers during
a function call. The CPU12 can push and pull any of the CPU registers A, B, CCR, D,
X, Y, or SP.
C.9 Instruction Set Orthogonality
One very helpful aspect of the CPU12 instruction set, orthogonality, is difficult to quantify in terms of direct benefit to an HLL compiler. Orthogonality refers to the regularity
of the instruction set. A completely orthogonal instruction set would allow any instruction to operate in any addressing mode, would have identical code sizes and execution
times for similar operations on different registers, and would include both signed and
unsigned versions of all mathematical instructions. Greater regularity of the instruction
makes it possible to implement compilers more efficiently, because operation is more
consistent, and fewer special cases must be handled.
CPU12
REFERENCE MANUAL
HIGH-LEVEL LANGUAGE SUPPORT
MOTOROLA
C-5
MOTOROLA
C-6
HIGH-LEVEL LANGUAGE SUPPORT
CPU12
REFERENCE MANUAL
APPENDIX D
ASSEMBLY LISTING
D.1 Assembler Test File
The following assembler test file illustrates all possible variations of the M68HC12 instruction set and can be used as a quick reference for instruction syntax. Instructions
are in alphabetical order and include redundancy.
*
68HC12 assembly listing
*
immed
equ
$72
dir
equ
$55
ext
equ
$1234
ind
equ
$37
small
equ
$e
mask
equ %11001100
0072
0055
1234
0037
000e
00cc
*
*
d000
ORG
d000
d002
d003
d005
d006
d007
d009
d02b
d04d
d091
d0b3
00 02
02
00 02
02
02
08 ae
d0f7
d0f9
d0fb
d0fd
d0ff
d101
d103
d105
d107
d109
d10b
d10d
d10f
d111
d113
d115
d117
d119
18
1a
19
89
89
89
89
89
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
06
e5
ed
72
72
72
72
72
a0
20
60
a7
67
c0
80
00
40
af
CPU12
REFERENCE MANUAL
$D000
dw
db
dc.w
dc.b
fcb
fdb
ds
ds.b
ds.w
rmb
rmw
2
2
2
2
2
2222
34
34
34
34
34
aba
abx
aby
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
#immed
#immed
#immed
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+y
,pc
,sp
,x
,y
1,-sp
d11b
d11d
d11f
d121
d123
d125
d127
d129
d12b
d12d
d12f
d131
d134
d137
d13a
d13c
d13e
d140
d142
d144
d146
d148
d14a
d14c
d14e
d152
d156
d15a
d15e
d162
d164
d166
d168
d16a
d16c
d16e
d170
d173
d176
d179
d17c
d17e
d180
d182
d185
d188
d18b
d18d
d18f
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
ASSEMBLY LISTING
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
e2
e2
e2
e2
e2
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
ef
ef
ef
01
89
33
44
01
7d
7d
7d
7d
10
10
10
88
44
33
44
88
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
ext,x
ext,x
ext,x
ext,x
ext,x
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
MOTOROLA
D-1
d191
d193
d195
d197
d199
d19b
d19d
d19f
d1a1
d1a3
d1a5
d1a7
d1a9
d1ab
d1ad
d1b0
d1b3
d1b7
d1bb
d1bf
d1c2
d1c5
d1c8
d1cb
d1cd
d1cf
d1d1
d1d3
d1d5
d1d7
d1d9
d1dc
d1de
d1e1
d1e5
d1e7
d1e9
d1eb
d1ee
d1f1
d1f3
d1f5
d1f7
d1fa
d1fd
d1ff
d201
d204
d206
d208
d20a
d20d
d20f
d211
d213
d216
d218
d21a
d21d
d220
d221
d222
d223
d225
d228
d22b
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
99
99
b9
b9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
a9
c9
e9
e9
e9
d9
f9
e9
8b
ab
9b
bb
bb
cb
eb
db
fb
c3
e3
d3
f3
84
a4
94
b4
c4
e4
d4
f4
10
68
78
78
48
58
59
67
77
77
47
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
72
a0
d2
f8
55
01
f2
72
a0
55
01
01
72
a0
55
01
00
a0
55
01
72
a0
55
01
72
a0
55
01
72
a0
00
01
88
88
01 88
01 88
01 88
37
37
37
37
7d
88
01 88
88
88
88
72
88
88
88
55
88
a0
00 55
01 88
MOTOROLA
D-2
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adca
adcb
adcb
adcb
adcb
adcb
adcb
adcb
adda
adda
adda
adda
adda
addb
addb
addb
addb
addd
addd
addd
addd
anda
anda
anda
anda
andb
andb
andb
andb
andcc
asl
asl
asl
asla
aslb
asld
asr
asr
asr
asra
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
1,+sp
-small,pc
125,pc
dir
ext
ext,sp
#immed
1,+sp
dir
ext
ext
#immed
1,+sp
dir
ext
#immed
1,+sp
dir
ext
#immed
1,+sp
dir
ext
#immed
1,+sp
dir
ext
#immed
1,+sp
dir
ext
d22c
d22d
d22f
d231
d233
d235
d237
d239
d23b
d23d
d23f
d242
d244
d246
d248
d24b
d24d
d24f
d251
d253
d255
d257
d259
d25b
d25d
d25f
d261
d264
d267
d26a
d26d
57
24
25
27
2c
2e
22
85
a5
95
b5
c5
e5
d5
f5
2f
23
2d
2b
26
2a
20
21
07
28
29
0d
0d
0d
0d
0d
fe
fe
fe
fe
fe
fe
72
a0
55
01
72
a0
55
01
fe
fe
fe
fe
fe
fe
fe
fe
fe
fe
fe
a0
a0
a0
bf
bf
55
55
55
55
55
asrb
bcc
bcs
beq
bge
bgt
bhi
bita
bita
bita
bita
bitb
bitb
bitb
bitb
ble
bls
blt
bmi
bne
bpl
bra
brn
bsr
bvc
bvs
bclr
bclr
bclr
bclr
bclr
*
*
*
*
*
*
#immed
1,+sp
dir
ext
#immed
1,+sp
dir
ext
*
*
*
*
*
*
*
*
*
*
*
1,+sp $55
1,+sp #$55
1,+sp,#$55
1,sp-,#$55
1,sp- #$55
d270
d273
d276
d279
0d
0d
0d
0d
20
20
20
20
55
55
55
55
bclr
bclr
bclr
bclr
1,+x $55
1,+x #$55
1,+x,$55
1,+x,#$55
d27c
d27f
d282
d285
4d
4d
4d
4d
55
55
55
55
55
55
55
55
bclr
bclr
bclr
bclr
dir $55
dir #$55
dir,$55
dir,#$55
d288
d28c
d290
d294
1d
1d
1d
1d
01
01
01
01
88
88
88
88
55
55
55
55
bclr
bclr
bclr
bclr
ext $55
ext #$55
ext,$55
ext,#$55
d298
d29c
d2a0
d2a4
0f
0f
0f
0f
a0
a0
a0
a0
55
55
55
55
fc
fc
fc
fc
brclr
brclr
brclr
brclr
1,+sp $55 *
1,+sp #$55 *
1,+sp,$55 *
1,+sp,#$55 *
d2a8
d2ac
d2b0
d2b4
4f
4f
4f
4f
55
55
55
55
55
55
55
55
fc
fc
fc
fc
brclr
brclr
brclr
brclr
dir $55 *
dir #$55 *
dir,$55 *
dir,#$55 *
d2b8
d2bd
d2c2
d2c7
1f
1f
1f
1f
01
01
01
01
88
88
88
88
55
55
55
55
brclr
brclr
brclr
brclr
ext $55 *
ext #$55 *
ext,$55,*
ext,#$55,*
1,+sp
dir
ext
d2cc
d2d0
d2d4
d2d8
0e
0e
0e
0e
a0
a0
a0
a0
55
55
55
55
fc
fc
fc
fc
brset
brset
brset
brset
1,+sp $55 *
1,+sp #$55 *
1,+sp,$55,*
1,+sp,#$55,*
ASSEMBLY LISTING
88
88
fb
fb
fb
fb
CPU12
REFERENCE MANUAL
d2dc
d2e0
d2e4
d2e8
4e
4e
4e
4e
55
55
55
55
55
55
55
55
fc
fc
fc
fc
brset
brset
brset
brset
dir $55 *
dir #$55 *
dir,$55,*
dir,#$55,*
d2ec
d2f1
d2f6
d2fb
1e
1e
1e
1e
01
01
01
01
88
88
88
88
55
55
55
55
brset
brset
brset
brset
ext $55 *
ext #$55 *
ext,$55,*
ext,#$55,*
d300
d303
d306
d309
0c
0c
0c
0c
a0
a0
a0
a0
55
55
55
55
bset
bset
bset
bset
1,+sp $55
1,+sp #$55
1,+sp,$55
1,+sp,#$55
d30c
d30f
d312
d315
4c
4c
4c
4c
55
55
55
55
55
55
55
55
bset
bset
bset
bset
dir $55
dir #$55
dir,$55
dir,#$55
d318
d31c
d320
d324
1c
1c
1c
1c
01
01
01
01
88
88
88
88
55
55
55
55
bset
bset
bset
bset
ext $55
ext #$55
ext,$55
ext,#$55
d328
d32b
d32e
d331
d334
d337
d33a
d33d
d340
d343
d346
d349
d34c
d34f
d352
d355
d358
d35b
d35e
d361
d364
d367
d36a
d36e
d372
d376
d379
d37c
d37f
d382
d385
d388
d38b
d38e
d391
d394
d397
d39a
d39d
d3a0
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
ef 55
ef 55
ef 55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
1,+sp $55
1,+x $55
1,+y $55
8,+sp $55
8,+x $55
8,+y $55
,pc $55
,sp $55
,x $55
,y $55
1,-sp $55
1,-x $55
1,-y $55
8,-sp $55
8,-x $55
8,-y $55
-1,sp $55
-1,x $55
-1,y $55
-16,sp $55
-16,x $55
-16,y $55
-17,sp $55
-17,x $55
-17,y $55
-small,pc $55
-small,sp $55
-small,x $55
-small,y $55
0,pc $55
0,sp $55
0,x $55
0,y $55
1,sp+ $55
1,x+ $55
1,y+ $55
1,sp $55
1,x $55
1,y $55
1,sp- $55
fb
fb
fb
fb
CPU12
REFERENCE MANUAL
d3a3
d3a6
d3a9
d3ad
d3b1
d3b5
d3b9
d3bc
d3bf
d3c2
d3c6
d3ca
d3ce
d3d1
d3d4
d3d7
d3da
d3dd
d3e0
d3e3
d3e6
d3e9
d3ec
d3ef
d3f2
d3f5
d3f8
d3fb
d3ff
d403
d408
d40d
d412
d416
d41a
d41e
d422
d425
d428
d42b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4a
4a
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
4b
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
00
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
d42e
d430
d432
d434
d436
d439
d43c
d43d
d43e
d440
d442
d444
d446
18
10
10
69
79
79
87
c7
10
81
a1
91
b1
17
fe
ef
a0
00 55
01 88
fd
72
a0
55
01 88
cba
clc
cli
clr
clr
clr
clra
clrb
clv
cmpa
cmpa
cmpa
cmpa
d449
d44b
d44d
d44f
d451
d453
d455
d457
d459
d45b
d45d
c1
c1
e1
e1
e1
e1
e1
e1
e1
e1
e1
72
72
a0
20
60
a7
27
67
c0
80
00
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
ASSEMBLY LISTING
55
55
7d
7d
7d
7d
55
55
55
10
10
10
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
88
01
01
01
37
37
37
37
55
55
55
55
55
55
55
55
55
55
55
55
55
88 55
88 55
88 55
55
55
55
55
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
call
1,x- $55
1,y- $55
125,pc $55
125,sp $55
125,x $55
125,y $55
15,sp $55
15,x $55
15,y $55
16,sp $55
16,x $55
16,y $55
8,sp+ $55
8,x+ $55
8,y+ $55
8,sp- $55
8,x- $55
8,y- $55
a,sp $55
a,x $55
a,y $55
b,sp $55
b,x $55
b,y $55
d,sp $55
d,x $55
d,y $55
dir $55
ext $55
ext,sp $55
ext,x $55
ext,y $55
ind,pc $55
ind,sp $55
ind,x $55
ind,y $55
small,pc $55
small,sp $55
small,x $55
small,y $55
1,+sp
dir
ext
#immed
1,+sp
dir
ext
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
MOTOROLA
D-3
d45f
d461
d463
d465
d467
d469
d46b
d46d
d46f
d471
d473
d475
d477
d479
d47c
d47f
d482
d484
d486
d488
d48a
d48c
d48e
d490
d492
d494
d496
d498
d49a
d49c
d49e
d4a0
d4a2
d4a4
d4a7
d4aa
d4ad
d4b0
d4b2
d4b4
d4b6
d4b9
d4bc
d4bf
d4c1
d4c3
d4c5
d4c7
d4c9
d4cb
d4cd
d4cf
d4d1
d4d3
d4d5
d4d7
d4d9
d4db
d4dd
d4df
d4e1
d4e4
d4e7
d4eb
d4ef
d4f3
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
e1
d1
d1
f1
f1
e1
e1
e1
e1
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
ef
ef
ef
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
MOTOROLA
D-4
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
d4f6
d4f9
d4fc
d4ff
d501
d503
d505
d507
d509
d50b
d50d
d50f
d511
d513
d515
d517
d519
d51b
d51d
d51f
d521
d523
d525
d527
d529
d52b
d52d
d52f
d531
d533
d536
d539
d53c
d53e
d540
d542
d544
d546
d548
d54a
d54c
d54e
d550
d552
d554
d556
d558
d55a
d55c
d55e
d561
d564
d567
d56a
d56c
d56e
d570
d573
d576
d579
d57b
d57d
d57f
d581
d583
d585
e1
e1
e1
e1
e1
e1
e1
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
ASSEMBLY LISTING
37
37
37
ef
ef
ef
7d
7d
7d
7d
10
10
10
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
cmpb
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
CPU12
REFERENCE MANUAL
d587
d589
d58b
d58d
d58f
d591
d593
d595
d597
d59a
d59d
d5a0
d5a4
d5a8
d5ac
d5af
d5b2
d5b5
d5b8
d5ba
d5bc
d5be
d5c0
d5c1
d5c2
d5c5
d5c8
d5ca
d5cc
d5ce
d5d0
d5d2
d5d4
d5d6
d5d8
d5da
d5dc
d5de
d5e0
d5e2
d5e4
d5e6
d5e8
d5ea
d5ec
d5ee
d5f0
d5f2
d5f4
d5f7
d5fa
d5fd
d5ff
d601
d603
d605
d607
d609
d60b
d60d
d60f
d611
d613
d615
d617
d619
61
61
61
61
61
61
61
61
71
71
71
61
61
61
61
61
61
61
61
61
61
61
41
51
8c
8c
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
e4
ec
f5
e5
ed
f6
e6
ee
00
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
00
00
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
55
88
88
01 88
01 88
01 88
37
37
37
37
72
72
ef
ef
ef
CPU12
REFERENCE MANUAL
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
com
coma
comb
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp-
d61b
d61d
d61f
d622
d625
d628
d62b
d62d
d62f
d631
d634
d637
d63a
d63c
d63e
d640
d642
d644
d646
d648
d64a
d64c
d64e
d650
d652
d654
d656
d658
d65a
d65c
d65f
d662
d666
d66a
d66e
d671
d674
d677
d67a
d67c
d67e
d680
d682
d685
d687
d689
d68b
d68d
d68f
d691
d693
d695
d697
d699
d69b
d69d
d69f
d6a1
d6a3
d6a5
d6a7
d6a9
d6ab
d6ad
d6af
d6b1
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
9c
9c
bc
bc
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
8f
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
ASSEMBLY LISTING
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
00
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
72
ef
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cpd
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
MOTOROLA
D-5
d6b4
d6b7
d6ba
d6bc
d6be
d6c0
d6c2
d6c4
d6c6
d6c8
d6ca
d6cc
d6ce
d6d0
d6d2
d6d4
d6d6
d6d8
d6da
d6dc
d6df
d6e2
d6e5
d6e8
d6ea
d6ec
d6ee
d6f1
d6f4
d6f7
d6f9
d6fb
d6fd
d6ff
d701
d703
d705
d707
d709
d70b
d70d
d70f
d711
d713
d715
d717
d719
d71c
d71f
d723
d727
d72b
d72e
d731
d734
d737
d739
d73b
d73d
d73f
d742
d745
d747
d749
d74b
d74d
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
af
9f
9f
bf
bf
af
af
af
af
af
af
af
af
af
af
af
8e
8e
ae
ae
ae
ae
ae
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
00
00
a0
20
60
a7
27
ef
ef
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
72
72
MOTOROLA
D-6
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cps
cpx
cpx
cpx
cpx
cpx
cpx
cpx
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
d74f
d751
d753
d755
d757
d759
d75b
d75d
d75f
d761
d763
d765
d767
d769
d76b
d76d
d76f
d771
d774
d777
d77a
d77c
d77e
d780
d782
d784
d786
d788
d78a
d78c
d78e
d790
d792
d794
d796
d798
d79a
d79c
d79f
d7a2
d7a5
d7a8
d7aa
d7ac
d7ae
d7b1
d7b4
d7b7
d7b9
d7bb
d7bd
d7bf
d7c1
d7c3
d7c5
d7c7
d7c9
d7cb
d7cd
d7cf
d7d1
d7d3
d7d5
d7d7
d7d9
d7dc
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
9e
9e
be
be
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
ASSEMBLY LISTING
ef
ef
ef
7d
7d
7d
7d
10
10
10
88
88
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
CPU12
REFERENCE MANUAL
d7df
d7e3
d7e7
d7eb
d7ee
d7f1
d7f4
d7f7
d7f9
d7fb
d7fd
d7ff
d802
d805
d807
d809
d80b
d80d
d80f
d811
d813
d815
d817
d819
d81b
d81d
d81f
d821
d823
d825
d827
d829
d82b
d82d
d82f
d831
d834
d837
d83a
d83c
d83e
d840
d842
d844
d846
d848
d84a
d84c
d84e
d850
d852
d854
d856
d858
d85a
d85c
d85f
d862
d865
d868
d86a
d86c
d86e
d871
d874
d877
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
ae
8d
8d
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
00
00
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
01 88
01 88
01 88
37
37
37
37
72
72
ef
ef
ef
7d
7d
7d
7d
10
10
10
CPU12
REFERENCE MANUAL
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpx
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
d879
d87b
d87d
d87f
d881
d883
d885
d887
d889
d88b
d88d
d88f
d891
d893
d895
d897
d899
d89c
d89f
d8a3
d8a7
d8ab
d8ae
d8b1
d8b4
d8b7
d8b9
d8bb
d8bd
d8bf
d8c1
d8c4
d8c7
d8ca
d8cd
d8cf
d8d1
d8d3
d8d5
d8d7
d8d9
d8db
d8dd
d8df
d8e1
d8e3
d8e5
d8e7
d8e9
d8eb
d8ed
d8ef
d8f1
d8f3
d8f5
d8f7
d8f9
d8fc
d8ff
d902
d904
d906
d908
d90a
d90c
d90e
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
9d
9d
bd
bd
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
ad
18
04
04
04
04
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
ASSEMBLY LISTING
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
07
30
31
35
36
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
88
88
01 88
01 88
01 88
37
37
37
37
fd
fd
fd
fd
ef
ef
ef
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
cpy
daa
dbne
dbne
dbne
dbne
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
a *
b *
x *
y *
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
MOTOROLA
D-7
d910
d912
d914
d916
d918
d91a
d91c
d91e
d920
d922
d924
d927
d92a
d92d
d930
d932
d934
d936
d939
d93c
d93f
d941
d943
d945
d947
d949
d94b
d94d
d94f
d951
d953
d955
d957
d959
d95b
d95d
d960
d963
d966
d96a
d96e
d972
d975
d978
d97b
d97e
d980
d982
d984
d986
d987
d988
d98a
d98b
d98c
d98d
d98f
d993
d997
d99b
d99e
d9a1
d9a4
d9a7
d9aa
d9ad
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
73
73
73
63
63
63
63
63
63
63
63
63
63
63
43
53
1b
09
03
11
18
18
18
18
18
18
18
18
18
18
18
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
00
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
7d
7d
7d
7d
10
10
10
55
88
88
01 88
01 88
01 88
37
37
37
37
9f
14
12
12
12
1a
1a
1a
1a
1a
1a
1a
00 55
01 88
00 0e
a0
20
60
a7
27
67
c0
MOTOROLA
D-8
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
deca
decb
des
dex
dey
ediv
edivs
emacs
emacs
emacs
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
dir
ext
small
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
d9b0
d9b3
d9b6
d9b9
d9bc
d9bf
d9c2
d9c5
d9c8
d9cb
d9ce
d9d1
d9d4
d9d7
d9da
d9dd
d9e1
d9e5
d9e9
d9ec
d9ef
d9f2
d9f5
d9f8
d9fb
d9fe
da01
da04
da07
da0a
da0d
da10
da13
da16
da19
da1c
da20
da24
da28
da2c
da2f
da32
da35
da39
da3d
da41
da44
da47
da4a
da4d
da50
da53
da56
da59
da5c
da5f
da62
da65
da68
da6b
da6e
da73
da78
da7d
da81
da85
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
ASSEMBLY LISTING
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
f2
e2
ea
f8
f0
e0
ef
ef
ef
7d
7d
7d
7d
10
10
10
01 88
01 88
01 88
37
37
37
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
emaxd
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
CPU12
REFERENCE MANUAL
da89
da8d
da90
da93
da96
da99
da9c
da9f
daa2
daa5
daa8
daab
daae
dab1
dab4
dab7
daba
dabd
dac0
dac3
dac6
dac9
dacc
dacf
dad2
dad5
dad8
dadb
dadf
dae3
dae7
daea
daed
daf0
daf3
daf6
daf9
dafc
daff
db02
db05
db08
db0b
db0e
db11
db14
db17
db1a
db1e
db22
db26
db2a
db2d
db30
db33
db37
db3b
db3f
db42
db45
db48
db4b
db4e
db51
db54
db57
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
1a
1a
1a
1a
1a
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
37
ef
ef
ef
7d
7d
7d
7d
10
10
10
CPU12
REFERENCE MANUAL
emaxd
emaxd
emaxd
emaxd
emaxd
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
db5a
db5d
db60
db63
db66
db69
db6c
db71
db76
db7b
db7f
db83
db87
db8b
db8e
db91
db94
db97
db9a
db9d
dba0
dba3
dba6
dba9
dbac
dbaf
dbb2
dbb5
dbb8
dbbb
dbbe
dbc1
dbc4
dbc7
dbca
dbcd
dbd0
dbd3
dbd6
dbd9
dbdd
dbe1
dbe5
dbe8
dbeb
dbee
dbf1
dbf4
dbf7
dbfa
dbfd
dc00
dc03
dc06
dc09
dc0c
dc0f
dc12
dc15
dc18
dc1c
dc20
dc24
dc28
dc2b
dc2e
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
ASSEMBLY LISTING
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1e
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
f5
e5
ed
f6
e6
ee
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
01 88
01 88
01 88
37
37
37
37
ef
ef
ef
7d
7d
7d
7d
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emaxm
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
b,sp
b,x
b,y
d,sp
d,x
d,y
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
MOTOROLA
D-9
dc31
dc35
dc39
dc3d
dc40
dc43
dc46
dc49
dc4c
dc4f
dc52
dc55
dc58
dc5b
dc5e
dc61
dc64
dc67
dc6a
dc6f
dc74
dc79
dc7d
dc81
dc85
dc89
dc8c
dc8f
dc92
dc95
dc98
dc9b
dc9e
dca1
dca4
dca7
dcaa
dcad
dcb0
dcb3
dcb6
dcb9
dcbc
dcbf
dcc2
dcc5
dcc8
dccb
dcce
dcd1
dcd4
dcd7
dcdb
dcdf
dce3
dce6
dce9
dcec
dcef
dcf2
dcf5
dcf8
dcfb
dcfe
dd01
dd04
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
MOTOROLA
D-10
10
10
10
01 88
01 88
01 88
37
37
37
37
ef
ef
ef
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
emind
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
dd07
dd0a
dd0d
dd10
dd13
dd16
dd1a
dd1e
dd22
dd26
dd29
dd2c
dd2f
dd33
dd37
dd3b
dd3e
dd41
dd44
dd47
dd4a
dd4d
dd50
dd53
dd56
dd59
dd5c
dd5f
dd62
dd65
dd68
dd6d
dd72
dd77
dd7b
dd7f
dd83
dd87
dd8a
dd8d
dd90
dd93
dd95
dd97
dd99
dd9b
dd9d
dd9f
dda1
dda3
dda5
dda7
dda9
ddab
ddad
ddaf
ddb1
ddb3
ddb5
ddb7
ddb9
ddbb
ddbd
ddbf
ddc1
ddc3
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
88
88
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
1f
72
72
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
ASSEMBLY LISTING
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
ef
7d
7d
7d
7d
10
10
10
01 88
01 88
01 88
37
37
37
37
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eminm
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
CPU12
REFERENCE MANUAL
ddc6
ddc9
ddcc
ddce
ddd0
ddd2
ddd4
ddd6
ddd8
ddda
dddc
ddde
dde0
dde2
dde4
dde6
dde8
ddea
ddec
ddee
ddf1
ddf4
ddf7
ddfa
ddfc
ddfe
de00
de03
de06
de09
de0b
de0d
de0f
de11
de13
de15
de17
de19
de1b
de1d
de1f
de21
de23
de25
de27
de29
de2b
de2e
de31
de35
de39
de3d
de40
de43
de46
de49
de4b
de4d
de4f
de51
de53
de55
de57
de59
de5b
de5d
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
98
98
b8
b8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
a8
c8
c8
e8
e8
e8
e8
e8
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
72
72
a0
20
60
a7
27
ef
ef
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
CPU12
REFERENCE MANUAL
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eora
eorb
eorb
eorb
eorb
eorb
eorb
eorb
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
de5f
de61
de63
de65
de67
de69
de6b
de6d
de6f
de71
de73
de75
de77
de79
de7b
de7d
de7f
de81
de84
de87
de8a
de8c
de8e
de90
de92
de94
de96
de98
de9a
de9c
de9e
dea0
dea2
dea4
dea6
dea8
deaa
deac
deaf
deb2
deb5
deb8
deba
debc
debe
dec1
dec4
dec7
dec9
decb
decd
decf
ded1
ded3
ded5
ded7
ded9
dedb
dedd
dedf
dee1
dee3
dee5
dee7
dee9
deec
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
d8
d8
f8
f8
ASSEMBLY LISTING
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
ef
ef
ef
7d
7d
7d
7d
10
10
10
88
88
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
MOTOROLA
D-11
deef
def3
def7
defb
defe
df01
df04
df07
df09
df0b
df0d
df0f
df12
df14
df16
df18
df1a
df1c
df1e
df20
df22
df24
df26
df28
df2a
df2c
df2e
df30
df32
df34
df36
df38
df3a
df3c
df3e
df40
df42
df44
df46
df48
df4a
df4c
df4e
df50
df52
df54
df56
df58
df5a
df5c
df5e
df60
df62
df64
df66
df68
df6a
df6c
df6e
df70
df72
df74
df76
df78
df7a
df7c
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
e8
18
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
18
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
3f
80
81
81
82
84
87
85
85
86
85
90
91
92
94
97
95
96
a0
a1
a2
a4
a7
a5
a6
c0
c1
c2
c4
c7
c5
c6
f0
f1
f2
f4
f7
f5
f6
d0
d1
d2
d4
d7
d5
d6
d6
e0
e1
e2
e4
e7
e5
e6
11
01 88
01 88
01 88
37
37
37
37
05
MOTOROLA
D-12
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
eorb
etbl
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
exg
fdiv
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
5++,x
a a
a b
a,b
a ccr
a d
a sp
a x
a,x
a y
a,x
b a
b b
b ccr
b d
b sp
b x
b y
ccr a
ccr b
ccr ccr
ccr d
ccr sp
ccr x
ccr y
d a
d b
d ccr
d d
d sp
d x
d y
sp a
sp b
sp ccr
sp d
sp sp
sp x
sp y
x a
x b
x ccr
x d
x sp
x x
x y
x,y
y a
y b
y ccr
y d
y sp
y x
y y
df7e
df80
df82
df84
df86
df88
df8a
df8c
df8e
df90
df92
df94
df96
df98
df9a
df9c
df9e
dfa0
dfa2
dfa4
dfa6
dfa8
dfaa
dfac
dfaf
dfb2
dfb5
dfb7
dfb9
dfbb
dfbd
dfbf
dfc1
dfc3
dfc5
dfc7
dfc9
dfcb
dfcd
dfcf
dfd1
dfd3
dfd5
dfd7
dfda
dfdd
dfe0
dfe3
dfe5
dfe7
dfe9
dfec
dfef
dff2
dff4
dff6
dff8
dffa
dffc
dffe
e000
e002
e004
e006
e008
e00a
18
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
10
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
ASSEMBLY LISTING
ef
ef
ef
7d
7d
7d
7d
10
10
10
idiv
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
CPU12
REFERENCE MANUAL
e00c
e00e
e010
e013
e016
e019
e01d
e021
e025
e028
e02b
e02e
e031
e033
e035
e037
e039
e03a
e03b
e03d
e03e
e03f
e041
e043
e045
e047
e049
e04b
e04d
e04f
e051
e053
e055
e057
e059
e05b
e05d
e05f
e061
e063
e065
e067
e069
e06b
e06e
e071
e074
e076
e078
e07a
e07c
e07e
e080
e082
e084
e086
e088
e08a
e08c
e08e
e090
e092
e094
e096
e099
e09c
62
62
72
72
72
62
62
62
62
62
62
62
62
62
62
62
42
52
1b
08
02
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
e6
ee
00
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
55
88
88
01 88
01 88
01 88
37
37
37
37
81
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
ef
ef
ef
7d
7d
7d
CPU12
REFERENCE MANUAL
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inc
inca
incb
ins
inx
iny
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
d,x
d,y
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
e09f
e0a2
e0a4
e0a6
e0a8
e0ab
e0ae
e0b1
e0b3
e0b5
e0b7
e0b9
e0bb
e0bd
e0bf
e0c1
e0c3
e0c5
e0c7
e0c9
e0cb
e0cd
e0cf
e0d2
e0d5
e0d8
e0dc
e0e0
e0e4
e0e7
e0ea
e0ed
e0f0
e0f2
e0f4
e0f6
e0f8
e0fa
e0fc
e0fe
e100
e102
e104
e106
e108
e10a
e10c
e10e
e110
e112
e114
e116
e118
e11a
e11c
e11e
e120
e122
e124
e127
e12a
e12d
e12f
e131
e133
e135
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
05
06
06
06
05
05
05
05
05
05
05
05
05
05
05
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
ASSEMBLY LISTING
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
00
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
7d
10
10
10
55
88
88
01 88
01 88
01 88
37
37
37
37
ef
ef
ef
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
MOTOROLA
D-13
e137
e139
e13b
e13d
e13f
e141
e143
e145
e147
e149
e14b
e14d
e14f
e152
e155
e158
e15b
e15d
e15f
e161
e164
e167
e16a
e16c
e16e
e170
e172
e174
e176
e178
e17a
e17c
e17e
e180
e182
e184
e186
e188
e18a
e18c
e18f
e192
e195
e199
e19d
e1a1
e1a4
e1a7
e1aa
e1ad
e1af
e1b1
e1b3
e1b5
e1b9
e1bd
e1c1
e1c5
e1c9
e1cd
e1d1
e1d5
e1d9
e1dd
e1e1
e1e5
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
17
17
16
16
16
15
15
15
15
15
15
15
15
15
15
15
18
18
18
18
18
18
18
18
18
18
18
18
18
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
24
24
25
27
2c
2e
22
2f
23
2d
2b
26
2a
7d
7d
7d
7d
10
10
10
88
88
88
01 88
01 88
01 88
37
37
37
37
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
ff
MOTOROLA
D-14
fc
fc
fc
fc
fc
fc
fc
fc
fc
fc
fc
fc
fc
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
jsr
lbcc
lbcc
lbcs
lbeq
lbge
lbgt
lbhi
lble
lbls
lblt
lbmi
lbne
lbpl
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
*
*
*
*
*
*
*
*
*
*
*
*
*
e1e9
e1ed
e1f1
e1f5
e1f9
e1fd
e1ff
e201
e203
e205
e207
e209
e20b
e20d
e20f
e211
e213
e215
e217
e219
e21b
e21d
e21f
e221
e223
e225
e227
e229
e22b
e22d
e230
e233
e236
e238
e23a
e23c
e23e
e240
e242
e244
e246
e248
e24a
e24c
e24e
e250
e252
e254
e256
e258
e25b
e25e
e261
e264
e266
e268
e26a
e26d
e270
e273
e275
e277
e279
e27b
e27d
e27f
18
18
15
18
18
86
86
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
20
21
fa
28
29
72
72
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
ASSEMBLY LISTING
ff
ff
ff
ff
ff
ef
ef
ef
7d
7d
7d
7d
10
10
10
fc
fc
fc
fc
fc
lbra
lbrn
lbsr
lbvc
lbvs
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
*
*
*
*
*
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
CPU12
REFERENCE MANUAL
e281
e283
e285
e287
e289
e28b
e28d
e28f
e291
e293
e295
e298
e29b
e29f
e2a3
e2a7
e2aa
e2ad
e2b0
e2b3
e2b5
e2b7
e2b9
e2bb
e2bd
e2bf
e2c1
e2c3
e2c5
e2c7
e2c9
e2cb
e2cd
e2cf
e2d1
e2d3
e2d5
e2d7
e2d9
e2db
e2dd
e2df
e2e1
e2e3
e2e5
e2e7
e2e9
e2eb
e2ee
e2f1
e2f4
e2f6
e2f8
e2fa
e2fc
e2fe
e300
e302
e304
e306
e308
e30a
e30c
e30e
e310
e312
a6
a6
a6
a6
a6
a6
a6
a6
96
96
b6
b6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
a6
c6
c6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
72
72
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
88
88
01 88
01 88
01 88
37
37
37
37
ef
ef
ef
CPU12
REFERENCE MANUAL
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldaa
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x-
e314
e316
e319
e31c
e31f
e322
e324
e326
e328
e32b
e32e
e331
e333
e335
e337
e339
e33b
e33d
e33f
e341
e343
e345
e347
e349
e34b
e34d
e34f
e351
e353
e356
e359
e35d
e361
e365
e368
e36b
e36e
e371
e373
e375
e377
e379
e37c
e37f
e381
e383
e385
e387
e389
e38b
e38d
e38f
e391
e393
e395
e397
e399
e39b
e39d
e39f
e3a1
e3a3
e3a5
e3a7
e3a9
e3ab
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
d6
d6
f6
f6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
e6
cc
cc
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ASSEMBLY LISTING
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
00
00
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
72
72
ef
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldab
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
MOTOROLA
D-15
e3ae
e3b1
e3b4
e3b6
e3b8
e3ba
e3bc
e3be
e3c0
e3c2
e3c4
e3c6
e3c8
e3ca
e3cc
e3ce
e3d0
e3d2
e3d4
e3d6
e3d9
e3dc
e3df
e3e2
e3e4
e3e6
e3e8
e3eb
e3ee
e3f1
e3f3
e3f5
e3f7
e3f9
e3fb
e3fd
e3ff
e401
e403
e405
e407
e409
e40b
e40d
e40f
e411
e413
e416
e419
e41d
e421
e425
e428
e42b
e42e
e431
e433
e435
e437
e439
e43c
e43f
e441
e443
e445
e447
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
dc
dc
fc
fc
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
ec
cf
cf
ef
ef
ef
ef
ef
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
00
00
a0
20
60
a7
27
ef
ef
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
72
72
MOTOROLA
D-16
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
lds
lds
lds
lds
lds
lds
lds
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
e449
e44b
e44d
e44f
e451
e453
e455
e457
e459
e45b
e45d
e45f
e461
e463
e465
e467
e469
e46b
e46e
e471
e474
e476
e478
e47a
e47c
e47e
e480
e482
e484
e486
e488
e48a
e48c
e48e
e490
e492
e494
e496
e499
e49c
e49f
e4a2
e4a4
e4a6
e4a8
e4ab
e4ae
e4b1
e4b3
e4b5
e4b7
e4b9
e4bb
e4bd
e4bf
e4c1
e4c3
e4c5
e4c7
e4c9
e4cb
e4cd
e4cf
e4d1
e4d4
e4d8
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
ef
df
ff
ef
ef
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
01
f2
e2
ASSEMBLY LISTING
ef
ef
ef
7d
7d
7d
7d
10
10
10
88
01 88
01 88
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
lds
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext,sp
ext,x
CPU12
REFERENCE MANUAL
e4dc
e4e0
e4e3
e4e6
e4e9
e4ec
e4ee
e4f0
e4f2
e4f4
e4f7
e4fa
e4fc
e4fe
e500
e502
e504
e506
e508
e50a
e50c
e50e
e510
e512
e514
e516
e518
e51a
e51c
e51e
e520
e522
e524
e526
e529
e52c
e52f
e531
e533
e535
e537
e539
e53b
e53d
e53f
e541
e543
e545
e547
e549
e54b
e54d
e54f
e551
e554
e557
e55a
e55d
e55f
e561
e563
e566
e569
e56c
e56e
e570
ef
ef
ef
ef
ef
ef
ef
ef
ef
ce
ce
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ea
f8
f0
e0
e8
ce
8e
0e
4e
00
00
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
01 88
37
37
37
37
72
72
ef
ef
ef
7d
7d
7d
7d
10
10
10
CPU12
REFERENCE MANUAL
lds
lds
lds
lds
lds
lds
lds
lds
lds
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
e572
e574
e576
e578
e57a
e57c
e57e
e580
e582
e584
e586
e588
e58a
e58c
e58e
e591
e594
e598
e59c
e5a0
e5a3
e5a6
e5a9
e5ac
e5ae
e5b0
e5b2
e5b4
e5b7
e5ba
e5bc
e5be
e5c0
e5c2
e5c4
e5c6
e5c8
e5ca
e5cc
e5ce
e5d0
e5d2
e5d4
e5d6
e5d8
e5da
e5dc
e5de
e5e0
e5e2
e5e4
e5e6
e5e9
e5ec
e5ef
e5f1
e5f3
e5f5
e5f7
e5f9
e5fb
e5fd
e5ff
e601
e603
e605
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
de
de
fe
fe
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
ee
cd
cd
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ASSEMBLY LISTING
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
00
00
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
88
88
01 88
01 88
01 88
37
37
37
37
72
72
ef
ef
ef
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldx
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
MOTOROLA
D-17
e607
e609
e60b
e60d
e60f
e611
e614
e617
e61a
e61d
e61f
e621
e623
e626
e629
e62c
e62e
e630
e632
e634
e636
e638
e63a
e63c
e63e
e640
e642
e644
e646
e648
e64a
e64c
e64e
e651
e654
e658
e65c
e660
e663
e666
e669
e66c
e66e
e670
e672
e674
e676
e678
e67a
e67c
e67e
e680
e682
e684
e686
e688
e68a
e68c
e68e
e690
e692
e694
e696
e698
e69a
e69c
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
dd
dd
fd
fd
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
ed
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
MOTOROLA
D-18
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
ldy
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
e69e
e6a0
e6a3
e6a6
e6a9
e6ab
e6ad
e6af
e6b1
e6b3
e6b5
e6b7
e6b9
e6bb
e6bd
e6bf
e6c1
e6c3
e6c5
e6c7
e6c9
e6cb
e6ce
e6d1
e6d4
e6d7
e6d9
e6db
e6dd
e6e0
e6e3
e6e6
e6e8
e6ea
e6ec
e6ee
e6f0
e6f2
e6f4
e6f6
e6f8
e6fa
e6fc
e6fe
e700
e702
e704
e708
e70c
e710
e713
e716
e719
e71c
e71e
e720
e722
e724
e726
e728
e72a
e72c
e72e
e730
e732
e734
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1a
1a
1a
1a
1a
1a
1a
1a
1a
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
ASSEMBLY LISTING
ef
ef
ef
7d
7d
7d
7d
10
10
10
01 88
01 88
01 88
37
37
37
37
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leas
leax
leax
leax
leax
leax
leax
leax
leax
leax
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
CPU12
REFERENCE MANUAL
e736
e738
e73a
e73c
e73e
e740
e742
e744
e746
e748
e74a
e74c
e74e
e750
e753
e756
e759
e75b
e75d
e75f
e761
e763
e765
e767
e769
e76b
e76d
e76f
e771
e773
e775
e777
e779
e77b
e77e
e781
e784
e787
e789
e78b
e78d
e790
e793
e796
e798
e79a
e79c
e79e
e7a0
e7a2
e7a4
e7a6
e7a8
e7aa
e7ac
e7ae
e7b0
e7b2
e7b4
e7b8
e7bc
e7c0
e7c3
e7c6
e7c9
e7cc
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
1a
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
f2
e2
ea
f8
f0
e0
e8
ce
ef
ef
ef
7d
7d
7d
7d
10
10
10
01 88
01 88
01 88
37
37
37
37
CPU12
REFERENCE MANUAL
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
leax
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
e7ce
e7d0
e7d2
e7d4
e7d6
e7d8
e7da
e7dc
e7de
e7e0
e7e2
e7e4
e7e6
e7e8
e7ea
e7ec
e7ee
e7f0
e7f2
e7f4
e7f6
e7f8
e7fa
e7fc
e7fe
e800
e803
e806
e809
e80b
e80d
e80f
e811
e813
e815
e817
e819
e81b
e81d
e81f
e821
e823
e825
e827
e829
e82b
e82e
e831
e834
e837
e839
e83b
e83d
e840
e843
e846
e848
e84a
e84c
e84e
e850
e852
e854
e856
e858
e85a
1a
1a
1a
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
ASSEMBLY LISTING
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ef
ef
ef
7d
7d
7d
7d
10
10
10
leax
leax
leax
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
MOTOROLA
D-19
e85c
e85e
e860
e862
e864
e868
e86c
e870
e873
e876
e879
e87c
e87e
e880
e882
e884
e886
e888
e88a
e88c
e88e
e890
e892
e894
e896
e898
e89a
e89c
e89e
e8a0
e8a2
e8a4
e8a6
e8a8
e8aa
e8ac
e8ae
e8b0
e8b3
e8b6
e8b9
e8bb
e8bd
e8bf
e8c1
e8c3
e8c5
e8c7
e8c9
e8cb
e8cd
e8cf
e8d1
e8d3
e8d5
e8d7
e8d9
e8db
e8de
e8e1
e8e4
e8e7
e8e9
e8eb
e8ed
e8f0
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
ed
f6
e6
ee
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
01 88
01 88
01 88
37
37
37
37
ef
ef
ef
7d
7d
7d
7d
10
10
MOTOROLA
D-20
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
leay
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
b,y
d,sp
d,x
d,y
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
e8f3
e8f6
e8f8
e8fa
e8fc
e8fe
e900
e902
e904
e906
e908
e90a
e90c
e90e
e910
e912
e914
e917
e91a
e91d
e921
e925
e929
e92c
e92f
e932
e935
e937
e939
e93b
e93d
e93e
e93f
e940
e942
e944
e946
e948
e94a
e94c
e94e
e950
e952
e954
e956
e958
e95a
e95c
e95e
e960
e962
e964
e966
e968
e96a
e96c
e96f
e972
e975
e977
e979
e97b
e97d
e97f
e981
e983
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
78
78
78
68
68
68
68
68
68
68
68
68
68
68
48
58
59
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
00
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
10
55
88
88
01 88
01 88
01 88
37
37
37
37
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1 ef
e1 ef
e9 ef
d2
92
12
52
c0
80
00
40
ASSEMBLY LISTING
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsl
lsla
lslb
lsld
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
CPU12
REFERENCE MANUAL
e985
e987
e989
e98b
e98d
e98f
e991
e993
e995
e997
e99a
e99d
e9a0
e9a3
e9a5
e9a7
e9a9
e9ac
e9af
e9b2
e9b4
e9b6
e9b8
e9ba
e9bc
e9be
e9c0
e9c2
e9c4
e9c6
e9c8
e9ca
e9cc
e9ce
e9d0
e9d3
e9d6
e9d9
e9dd
e9e1
e9e5
e9e8
e9eb
e9ee
e9f1
e9f3
e9f5
e9f7
e9f9
e9fa
e9fb
e9fc
e9fd
ea00
ea03
ea06
ea09
ea0c
ea0f
ea12
ea15
ea18
ea1b
ea1e
ea21
ea24
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
74
74
74
64
64
64
64
64
64
64
64
64
64
64
44
54
49
49
18
18
18
18
18
18
18
18
18
18
18
18
18
18
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
00
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
18
18
18
18
18
18
18
18
18
18
18
18
18
18
7d
7d
7d
7d
10
10
10
55
88
88
01 88
01 88
01 88
37
37
37
37
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
CPU12
REFERENCE MANUAL
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsr
lsra
lsrb
lsrd
lsrd
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
ea27
ea2a
ea2d
ea30
ea33
ea36
ea39
ea3c
ea3f
ea43
ea47
ea4b
ea4e
ea51
ea54
ea57
ea5a
ea5d
ea60
ea63
ea66
ea69
ea6c
ea6f
ea72
ea75
ea78
ea7b
ea7e
ea82
ea86
ea8a
ea8e
ea91
ea94
ea97
ea9b
ea9f
eaa3
eaa6
eaa9
eaac
eaaf
eab2
eab5
eab8
eabb
eabe
eac1
eac4
eac7
eaca
eacd
ead0
ead5
eada
eadf
eae3
eae7
eaeb
eaef
eaf2
eaf5
eaf8
eafb
eafe
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
ASSEMBLY LISTING
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
1c
1c
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
ef
ef
ef
7d
7d
7d
7d
10
10
10
01 88
01 88
01 88
37
37
37
37
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxa
maxm
maxm
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
MOTOROLA
D-21
eb01
eb04
eb07
eb0a
eb0d
eb10
eb13
eb16
eb19
eb1c
eb1f
eb22
eb25
eb28
eb2b
eb2e
eb31
eb34
eb37
eb3a
eb3d
eb41
eb45
eb49
eb4c
eb4f
eb52
eb55
eb58
eb5b
eb5e
eb61
eb64
eb67
eb6a
eb6d
eb70
eb73
eb76
eb79
eb7c
eb80
eb84
eb88
eb8c
eb8f
eb92
eb95
eb99
eb9d
eba1
eba4
eba7
ebaa
ebad
ebb0
ebb3
ebb6
ebb9
ebbc
ebbf
ebc2
ebc5
ebc8
ebcb
ebce
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
f2
MOTOROLA
D-22
ef
ef
ef
7d
7d
7d
7d
10
10
10
01 88
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
ext,sp
ebd3
ebd8
ebdd
ebe1
ebe5
ebe9
ebed
ebf0
ebf3
ebf6
ebf9
ebfa
ebfd
ec00
ec03
ec06
ec09
ec0c
ec0f
ec12
ec15
ec18
ec1b
ec1e
ec21
ec24
ec27
ec2a
ec2d
ec30
ec33
ec36
ec39
ec3c
ec40
ec44
ec48
ec4b
ec4e
ec51
ec54
ec57
ec5a
ec5d
ec60
ec63
ec66
ec69
ec6c
ec6f
ec72
ec75
ec78
ec7b
ec7f
ec83
ec87
ec8b
ec8e
ec91
ec94
ec98
ec9c
eca0
eca3
eca6
18
18
18
18
18
18
18
18
18
18
01
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
1c
1c
1c
1c
1c
1c
1c
1c
1c
1c
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
ASSEMBLY LISTING
01 88
01 88
37
37
37
37
ef
ef
ef
7d
7d
7d
7d
10
10
10
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
maxm
mem
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
CPU12
REFERENCE MANUAL
eca9
ecac
ecaf
ecb2
ecb5
ecb8
ecbb
ecbe
ecc1
ecc4
ecc7
ecca
eccd
ecd2
ecd7
ecdc
ece0
ece4
ece8
ecec
ecef
ecf2
ecf5
ecf8
ecfb
ecfe
ed01
ed04
ed07
ed0a
ed0d
ed10
ed13
ed16
ed19
ed1c
ed1f
ed22
ed25
ed28
ed2b
ed2e
ed31
ed34
ed37
ed3a
ed3e
ed42
ed46
ed49
ed4c
ed4f
ed52
ed55
ed58
ed5b
ed5e
ed61
ed64
ed67
ed6a
ed6d
ed70
ed73
ed76
ed79
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
01 88
01 88
01 88
37
37
37
37
ef
ef
ef
7d
CPU12
REFERENCE MANUAL
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
mina
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
ed7d
ed81
ed85
ed89
ed8c
ed8f
ed92
ed96
ed9a
ed9e
eda1
eda4
eda7
edaa
edad
edb0
edb3
edb6
edb9
edbc
edbf
edc2
edc5
edc8
edcb
edd0
edd5
edda
edde
ede2
ede6
edea
eded
edf0
edf3
edf6
edfa
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
1d
0a
0a
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
6b
6b
7d
7d
7d
10
10
10
01 88
01 88
01 88
37
37
37
37
90
90
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
minm
movb
movb
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
5,-y -16,sp
5,-y,-16,sp
; funny ` test
; stinky `000 test
;
edfe 18 0a 6b d2
ee02 18 0a 6b d2
movb
movb
ee06 18 0d 81 01 88
ee0b 18 0a 81 0c
movb
movb
5,-y -small,pc
5,-y,-small,pc
happy`
1,sp ext
1,sp 12,x
ee0f 18 08 af 72
movb
#immed 1,-sp
ee13
ee18
ee1c
ee20
ee24
ee28
ee2c
ee31
ee35
ee39
ee3d
ee41
ee45
ee49
ee4d
ee51
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
ext 1,-sp
5,-y -small,sp
5,-y,-small,sp
5,y- -small,sp
5,y-,-small,sp
1,x+ 1,y0,x
5,-y -small,x
5,-y,-small,x
5,-y -small,y
5,-y,-small,y
5,-y 0,pc
5,-y,0,pc
5,-y 0,sp
5,-y,0,sp
#immed 3,+x
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
ASSEMBLY LISTING
09
0a
0a
0a
0a
0a
0d
0a
0a
0a
0a
0a
0a
0a
0a
08
af
6b
6b
7b
7b
30
00
6b
6b
6b
6b
6b
6b
6b
6b
22
01 88
92
92
92
92
7f
00 00
12
12
52
52
c0
c0
80
80
72
MOTOROLA
D-23
ee55
ee59
ee5d
ee62
ee66
ee6a
ee6e
ee73
ee77
ee7b
ee7f
ee84
ee88
ee8c
ee90
ee95
ee99
ee9d
eea1
eea5
eea9
eead
eeb1
eeb5
eeb9
eebd
eec1
eec5
eec9
eecd
eed1
eed5
eed9
eedd
eee1
eee5
eee9
eeed
eef1
eef5
eef9
eefd
ef01
ef05
ef09
ef0d
ef11
ef15
ef19
ef1d
ef21
ef25
ef29
ef2d
ef31
ef35
ef39
ef3d
ef41
ef45
ef49
ef4d
ef51
ef55
ef59
ef5d
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
08
08
0b
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
6b
85
72
a0
a0
a0
a0
20
20
20
20
60
60
60
60
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
MOTOROLA
D-24
72
72
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
8f
0f
4f
b7
37
77
b8
38
78
f4
e4
ec
88
88
88
88
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
#immed 5,-y
#immed 5,sp
#immed ext
1,+sp 3,+x
1,+sp 5,-y
1,+sp 5,sp
1,+sp ext
1,+x 3,+x
1,+x 5,-y
1,+x 5,sp
1,+x ext
1,+y 3,+x
1,+y 5,-y
1,+y 5,sp
1,+y ext
3,+x 1,+sp
3,+x 1,+x
3,+x 1,+y
3,+x 8,+sp
3,+x 8,+x
3,+x 8,+y
3,+x ,pc
3,+x ,sp
3,+x ,x
3,+x ,y
3,+x 1,-sp
3,+x 1,-x
3,+x 1,-y
3,+x 8,-sp
3,+x 8,-x
3,+x 8,-y
3,+x -1,sp
3,+x -1,x
3,+x -1,y
3,+x -16,sp
3,+x -16,x
3,+x -16,y
3,+x -small,pc
3,+x -small,sp
3,+x -small,x
3,+x -small,y
3,+x 0,pc
3,+x 0,sp
3,+x 0,x
3,+x 0,y
3,+x 1,sp+
3,+x 1,x+
3,+x 1,y+
3,+x 1,sp
3,+x 1,x
3,+x 1,y
3,+x 1,sp3,+x 1,x3,+x 1,y3,+x 15,sp
3,+x 15,x
3,+x 15,y
3,+x 8,sp+
3,+x 8,x+
3,+x 8,y+
3,+x 8,sp3,+x 8,x3,+x 8,y3,+x a,sp
3,+x a,x
3,+x a,y
ef61
ef65
ef69
ef6d
ef71
ef75
ef79
ef7e
ef82
ef86
ef8a
ef8e
ef92
ef96
ef9a
ef9f
efa3
efa7
efab
efb0
efb4
efb8
efbc
efc1
efc5
efc9
efcd
efd2
efd6
efda
efde
efe3
efe7
efeb
efef
eff4
eff8
effc
f000
f005
f009
f00d
f011
f016
f01a
f01e
f022
f027
f02b
f02f
f033
f038
f03c
f040
f044
f049
f04d
f051
f055
f05a
f05e
f062
f066
f06b
f06f
f073
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
0a
0a
0a
0a
0a
0a
0d
0a
0a
0a
0a
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
09
0a
0a
0a
09
0a
0a
0a
09
0a
0a
0a
09
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
ASSEMBLY LISTING
22
22
22
22
22
22
22
22
22
22
22
a7
a7
a7
a7
27
27
27
27
67
67
67
67
c0
c0
c0
c0
80
80
80
80
00
00
00
00
40
40
40
40
af
af
af
af
2f
2f
2f
2f
6f
6f
6f
6f
a8
a8
a8
a8
28
28
28
28
68
68
68
68
9f
9f
9f
f5
e5
ed
f6
e6
ee
01
ce
8e
0e
4e
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
00
22
6b
85
00
22
6b
85
00
22
6b
85
00
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
88
88
88
88
00
00
00
00
88
88
88
88
88
88
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
3,+x b,sp
3,+x b,x
3,+x b,y
3,+x d,sp
3,+x d,x
3,+x d,y
3,+x ext
3,+x small,pc
3,+x small,sp
3,+x small,x
3,+x small,y
8,+sp 3,+x
8,+sp 5,-y
8,+sp 5,sp
8,+sp ext
8,+x 3,+x
8,+x 5,-y
8,+x 5,sp
8,+x ext
8,+y 3,+x
8,+y 5,-y
8,+y 5,sp
8,+y ext
,pc 3,+x
,pc 5,-y
,pc 5,sp
,pc ext
,sp 3,+x
,sp 5,-y
,sp 5,sp
,sp ext
,x 3,+x
,x 5,-y
,x 5,sp
,x ext
,y 3,+x
,y 5,-y
,y 5,sp
,y ext
1,-sp 3,+x
1,-sp 5,-y
1,-sp 5,sp
1,-sp ext
1,-x 3,+x
1,-x 5,-y
1,-x 5,sp
1,-x ext
1,-y 3,+x
1,-y 5,-y
1,-y 5,sp
1,-y ext
8,-sp 3,+x
8,-sp 5,-y
8,-sp 5,sp
8,-sp ext
8,-x 3,+x
8,-x 5,-y
8,-x 5,sp
8,-x ext
8,-y 3,+x
8,-y 5,-y
8,-y 5,sp
8,-y ext
-1,sp 3,+x
-1,sp 5,-y
-1,sp 5,sp
CPU12
REFERENCE MANUAL
f077
f07c
f080
f084
f088
f08d
f091
f095
f099
f09e
f0a2
f0a6
f0aa
f0af
f0b3
f0b7
f0bb
f0c0
f0c4
f0c8
f0cc
f0d1
f0d5
f0d9
f0dd
f0e2
f0e6
f0ea
f0ee
f0f3
f0f7
f0fb
f0ff
f104
f108
f10c
f110
f115
f119
f11d
f121
f126
f12a
f12e
f132
f137
f13b
f13f
f143
f148
f14c
f150
f154
f159
f15d
f161
f165
f16a
f16e
f172
f176
f17b
f17f
f183
f187
f18c
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
9f
1f
1f
1f
1f
5f
5f
5f
5f
90
90
90
90
10
10
10
10
50
50
50
50
d2
d2
d2
d2
92
92
92
92
12
12
12
12
52
52
52
52
c0
c0
c0
c0
80
80
80
80
00
00
00
00
40
40
40
40
b0
b0
b0
b0
30
30
30
30
70
70
70
70
81
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
CPU12
REFERENCE MANUAL
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
-1,sp ext
-1,x 3,+x
-1,x 5,-y
-1,x 5,sp
-1,x ext
-1,y 3,+x
-1,y 5,-y
-1,y 5,sp
-1,y ext
-16,sp 3,+x
-16,sp 5,-y
-16,sp 5,sp
-16,sp ext
-16,x 3,+x
-16,x 5,-y
-16,x 5,sp
-16,x ext
-16,y 3,+x
-16,y 5,-y
-16,y 5,sp
-16,y ext
-small,pc 3,+x
-small,pc 5,-y
-small,pc 5,sp
-small,pc ext
-small,sp 3,+x
-small,sp 5,-y
-small,sp 5,sp
-small,sp ext
-small,x 3,+x
-small,x 5,-y
-small,x 5,sp
-small,x ext
-small,y 3,+x
-small,y 5,-y
-small,y 5,sp
-small,y ext
0,pc 3,+x
0,pc 5,-y
0,pc 5,sp
0,pc ext
0,sp 3,+x
0,sp 5,-y
0,sp 5,sp
0,sp ext
0,x 3,+x
0,x 5,-y
0,x 5,sp
0,x ext
0,y 3,+x
0,y 5,-y
0,y 5,sp
0,y ext
1,sp+ 3,+x
1,sp+ 5,-y
1,sp+ 5,sp
1,sp+ ext
1,x+ 3,+x
1,x+ 5,-y
1,x+ 5,sp
1,x+ ext
1,y+ 3,+x
1,y+ 5,-y
1,y+ 5,sp
1,y+ ext
1,sp 3,+x
f190
f194
f198
f19d
f1a1
f1a5
f1a9
f1ae
f1b2
f1b6
f1ba
f1bf
f1c3
f1c7
f1cb
f1d0
f1d4
f1d8
f1dc
f1e1
f1e5
f1e9
f1ed
f1f2
f1f6
f1fa
f1fe
f202
f206
f20a
f20e
f212
f216
f21a
f21e
f222
f226
f22a
f22e
f232
f236
f23a
f23e
f242
f246
f24a
f24e
f252
f256
f25a
f25e
f262
f266
f26a
f26e
f272
f276
f27a
f27e
f282
f286
f28a
f28e
f292
f296
f29a
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
ASSEMBLY LISTING
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
81
81
81
01
01
01
01
41
41
41
41
bf
bf
bf
bf
3f
3f
3f
3f
7f
7f
7f
7f
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
8f
0f
4f
b7
88
88
88
88
88
88
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
1,sp 5,-y
1,sp 5,sp
1,sp ext
1,x 3,+x
1,x 5,-y
1,x 5,sp
1,x ext
1,y 3,+x
1,y 5,-y
1,y 5,sp
1,y ext
1,sp- 3,+x
1,sp- 5,-y
1,sp- 5,sp
1,sp- ext
1,x- 3,+x
1,x- 5,-y
1,x- 5,sp
1,x- ext
1,y- 3,+x
1,y- 5,-y
1,y- 5,sp
1,y- ext
5,-y 1,+sp
5,-y 1,+x
5,-y 1,+y
5,-y 8,+sp
5,-y 8,+x
5,-y 8,+y
5,-y ,pc
5,-y ,sp
5,-y ,x
5,-y ,y
5,-y 1,-sp
5,-y 1,-x
5,-y 1,-y
5,-y 8,-sp
5,-y 8,-x
5,-y 8,-y
5,-y -1,sp
5,-y -1,x
5,-y -1,y
5,-y -16,sp
5,-y -16,x
5,-y -16,y
5,-y -small,pc
5,-y -small,sp
5,-y -small,x
5,-y -small,y
5,-y 0,pc
5,-y 0,sp
5,-y 0,x
5,-y 0,y
5,-y 1,sp+
5,-y 1,x+
5,-y 1,y+
5,-y 1,sp
5,-y 1,x
5,-y 1,y
5,-y 1,sp5,-y 1,x5,-y 1,y5,-y 15,sp
5,-y 15,x
5,-y 15,y
5,-y 8,sp+
MOTOROLA
D-25
f29e
f2a2
f2a6
f2aa
f2ae
f2b2
f2b6
f2ba
f2be
f2c2
f2c6
f2ca
f2ce
f2d2
f2d6
f2db
f2df
f2e3
f2e7
f2eb
f2ef
f2f3
f2f7
f2fc
f300
f304
f308
f30d
f311
f315
f319
f31e
f322
f326
f32a
f32e
f332
f336
f33a
f33e
f342
f346
f34a
f34e
f352
f356
f35a
f35e
f362
f366
f36a
f36e
f372
f376
f37a
f37e
f382
f386
f38a
f38e
f392
f396
f39a
f39e
f3a2
f3a6
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0d
0a
0a
0a
0a
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
8f
8f
8f
8f
0f
0f
0f
0f
4f
4f
4f
4f
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
MOTOROLA
D-26
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
01
ce
8e
0e
4e
22
6b
85
01
22
6b
85
01
22
6b
85
01
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
88
88
88
88
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
5,-y 8,x+
5,-y 8,y+
5,-y 8,sp5,-y 8,x5,-y 8,y5,-y a,sp
5,-y a,x
5,-y a,y
5,-y b,sp
5,-y b,x
5,-y b,y
5,-y d,sp
5,-y d,x
5,-y d,y
5,-y ext
5,-y small,pc
5,-y small,sp
5,-y small,x
5,-y small,y
15,sp 3,+x
15,sp 5,-y
15,sp 5,sp
15,sp ext
15,x 3,+x
15,x 5,-y
15,x 5,sp
15,x ext
15,y 3,+x
15,y 5,-y
15,y 5,sp
15,y ext
5,sp 1,+sp
5,sp 1,+x
5,sp 1,+y
5,sp 8,+sp
5,sp 8,+x
5,sp 8,+y
5,sp ,pc
5,sp ,sp
5,sp ,x
5,sp ,y
5,sp 1,-sp
5,sp 1,-x
5,sp 1,-y
5,sp 8,-sp
5,sp 8,-x
5,sp 8,-y
5,sp -1,sp
5,sp -1,x
5,sp -1,y
5,sp -16,sp
5,sp -16,x
5,sp -16,y
5,sp -small,pc
5,sp -small,sp
5,sp -small,x
5,sp -small,y
5,sp 0,pc
5,sp 0,sp
5,sp 0,x
5,sp 0,y
5,sp 1,sp+
5,sp 1,x+
5,sp 1,y+
5,sp 1,sp
5,sp 1,x
f3aa
f3ae
f3b2
f3b6
f3ba
f3be
f3c2
f3c6
f3ca
f3ce
f3d2
f3d6
f3da
f3de
f3e2
f3e6
f3ea
f3ee
f3f2
f3f6
f3fb
f3ff
f403
f407
f40b
f40f
f413
f417
f41c
f420
f424
f428
f42d
f431
f435
f439
f43e
f442
f446
f44a
f44f
f453
f457
f45b
f460
f464
f468
f46c
f471
f475
f479
f47d
f482
f486
f48a
f48e
f493
f497
f49b
f49f
f4a4
f4a8
f4ac
f4b0
f4b5
f4b9
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0a
0d
0a
0a
0a
0a
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
ASSEMBLY LISTING
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
b7
b7
b7
b7
37
37
37
37
77
77
77
77
b8
b8
b8
b8
38
38
38
38
78
78
78
78
f4
f4
f4
f4
e4
e4
e4
e4
ec
ec
ec
ec
f5
f5
f5
f5
e5
e5
41
bf
3f
7f
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
01
ce
8e
0e
4e
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
88
88
88
88
88
88
88
88
88
88
88
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
5,sp 1,y
5,sp 1,sp5,sp 1,x5,sp 1,y5,sp 8,sp+
5,sp 8,x+
5,sp 8,y+
5,sp 8,sp5,sp 8,x5,sp 8,y5,sp a,sp
5,sp a,x
5,sp a,y
5,sp b,sp
5,sp b,x
5,sp b,y
5,sp d,sp
5,sp d,x
5,sp d,y
5,sp ext
5,sp small,pc
5,sp small,sp
5,sp small,x
5,sp small,y
8,sp+ 3,+x
8,sp+ 5,-y
8,sp+ 5,sp
8,sp+ ext
8,x+ 3,+x
8,x+ 5,-y
8,x+ 5,sp
8,x+ ext
8,y+ 3,+x
8,y+ 5,-y
8,y+ 5,sp
8,y+ ext
8,sp- 3,+x
8,sp- 5,-y
8,sp- 5,sp
8,sp- ext
8,x- 3,+x
8,x- 5,-y
8,x- 5,sp
8,x- ext
8,y- 3,+x
8,y- 5,-y
8,y- 5,sp
8,y- ext
a,sp 3,+x
a,sp 5,-y
a,sp 5,sp
a,sp ext
a,x 3,+x
a,x 5,-y
a,x 5,sp
a,x ext
a,y 3,+x
a,y 5,-y
a,y 5,sp
a,y ext
b,sp 3,+x
b,sp 5,-y
b,sp 5,sp
b,sp ext
b,x 3,+x
b,x 5,-y
CPU12
REFERENCE MANUAL
f4bd
f4c1
f4c6
f4ca
f4ce
f4d2
f4d7
f4db
f4df
f4e3
f4e8
f4ec
f4f0
f4f4
f4f9
f4fd
f501
f505
f50a
f50f
f514
f519
f51e
f523
f528
f52d
f532
f537
f53c
f541
f546
f54b
f550
f555
f55a
f55f
f564
f569
f56e
f573
f578
f57d
f582
f587
f58c
f591
f596
f59b
f5a0
f5a5
f5aa
f5af
f5b4
f5b9
f5be
f5c3
f5c8
f5cd
f5d2
f5d7
f5dc
f5e1
f5e6
f5eb
f5f0
f5f5
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
e5
e5
ed
ed
ed
ed
f6
f6
f6
f6
e6
e6
e6
e6
ee
ee
ee
ee
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
b7
37
77
b8
38
78
f4
e4
ec
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
CPU12
REFERENCE MANUAL
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
b,x 5,sp
b,x ext
b,y 3,+x
b,y 5,-y
b,y 5,sp
b,y ext
d,sp 3,+x
d,sp 5,-y
d,sp 5,sp
d,sp ext
d,x 3,+x
d,x 5,-y
d,x 5,sp
d,x ext
d,y 3,+x
d,y 5,-y
d,y 5,sp
d,y ext
ext 1,+sp
ext 1,+x
ext 1,+y
ext 8,+sp
ext 8,+x
ext 8,+y
ext ,pc
ext ,sp
ext ,x
ext ,y
ext 1,-sp
ext 1,-x
ext 1,-y
ext 8,-sp
ext 8,-x
ext 8,-y
ext -1,sp
ext -1,x
ext -1,y
ext -16,sp
ext -16,x
ext -16,y
ext -small,pc
ext -small,sp
ext -small,x
ext -small,y
ext 0,pc
ext 0,sp
ext 0,x
ext 0,y
ext 1,sp+
ext 1,x+
ext 1,y+
ext 1,sp
ext 1,x
ext 1,y
ext 1,spext 1,xext 1,yext 8,sp+
ext 8,x+
ext 8,y+
ext 8,spext 8,xext 8,yext a,sp
ext a,x
ext a,y
f5fa
f5ff
f604
f609
f60e
f613
f618
f61e
f623
f628
f62d
f632
f636
f63a
f63e
f643
f647
f64b
f64f
f654
f658
f65c
f660
f665
f669
f66d
f671
f676
f67b
f67f
f684
f688
f68d
f692
f697
f69c
f6a1
f6a6
f6ac
f6b0
f6b4
f6b8
f6bd
f6c1
f6c5
f6c9
f6ce
f6d2
f6d6
f6da
f6df
f6e3
f6e7
f6eb
f6ef
f6f3
f6f7
f6fb
f6ff
f703
f707
f70b
f70f
f713
f717
f71b
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
ASSEMBLY LISTING
09
09
09
09
09
09
0c
09
09
09
09
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
0a
0a
0a
0d
05
02
01
02
01
00
00
00
00
00
03
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
f5
e5
ed
f6
e6
ee
01
ce
8e
0e
4e
ce
ce
ce
ce
8e
8e
8e
8e
0e
0e
0e
0e
4e
4e
4e
4e
82
82
02
02
ae
ae
ae
22
6b
85
00
a0
a0
a0
a0
20
20
20
20
60
60
60
60
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
01
01
01
01
01
01
88
01
01
01
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
01
0c
01
00
01
00
00
00
00
00
72
22
6b
85
01
22
6b
85
01
22
6b
85
01
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
88
88
88
88
88
88
01 88
88
88
88
88
88
88
88
88
88
88
88
72
72
72
72
72
01 88
88
88
88
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movb
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
ext b,sp
ext b,x
ext b,y
ext d,sp
ext d,x
ext d,y
ext ext
ext small,pc
ext small,sp
ext small,x
ext small,y
small,pc 3,+x
small,pc 5,-y
small,pc 5,sp
small,pc ext
small,sp 3,+x
small,sp 5,-y
small,sp 5,sp
small,sp ext
small,x 3,+x
small,x 5,-y
small,x 5,sp
small,x ext
small,y 3,+x
small,y 5,-y
small,y 5,sp
small,y ext
2,sp ext
2,sp 12,x
ext 2,x
2,x 0,x
ext 2,-sp
#immed 2,-sp
#immed 2,-sp
#immed 3,+x
#immed 5,-y
#immed 5,sp
#immed ext
1,+sp 3,+x
1,+sp 5,-y
1,+sp 5,sp
1,+sp ext
1,+x 3,+x
1,+x 5,-y
1,+x 5,sp
1,+x ext
1,+y 3,+x
1,+y 5,-y
1,+y 5,sp
1,+y ext
3,+x 1,+sp
3,+x 1,+x
3,+x 1,+y
3,+x 8,+sp
3,+x 8,+x
3,+x 8,+y
3,+x ,pc
3,+x ,sp
3,+x ,x
3,+x ,y
3,+x 1,-sp
3,+x 1,-x
3,+x 1,-y
3,+x 8,-sp
3,+x 8,-x
3,+x 8,-y
MOTOROLA
D-27
f71f
f723
f727
f72b
f72f
f733
f737
f73b
f73f
f743
f747
f74b
f74f
f753
f757
f75b
f75f
f763
f767
f76b
f76f
f773
f777
f77b
f77f
f783
f787
f78b
f78f
f793
f797
f79b
f79f
f7a3
f7a7
f7ab
f7af
f7b3
f7b7
f7bc
f7c0
f7c4
f7c8
f7cc
f7d0
f7d4
f7d8
f7dd
f7e1
f7e5
f7e9
f7ee
f7f2
f7f6
f7fa
f7ff
f803
f807
f80b
f810
f814
f818
f81c
f821
f825
f829
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
05
02
02
02
02
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
01
02
02
02
01
02
02
02
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
a7
a7
a7
a7
27
27
27
27
67
67
67
67
c0
c0
c0
c0
80
80
80
80
00
00
00
MOTOROLA
D-28
9f
1f
5f
90
10
50
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
01
ce
8e
0e
4e
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
00
22
6b
85
00
22
6b
85
88
88
88
88
00
00
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
3,+x -1,sp
3,+x -1,x
3,+x -1,y
3,+x -16,sp
3,+x -16,x
3,+x -16,y
3,+x -small,pc
3,+x -small,sp
3,+x -small,x
3,+x -small,y
3,+x 0,pc
3,+x 0,sp
3,+x 0,x
3,+x 0,y
3,+x 1,sp+
3,+x 1,x+
3,+x 1,y+
3,+x 1,sp
3,+x 1,x
3,+x 1,y
3,+x 1,sp3,+x 1,x3,+x 1,y3,+x 8,sp+
3,+x 8,x+
3,+x 8,y+
3,+x 8,sp3,+x 8,x3,+x 8,y3,+x a,sp
3,+x a,x
3,+x a,y
3,+x b,sp
3,+x b,x
3,+x b,y
3,+x d,sp
3,+x d,x
3,+x d,y
3,+x ext
3,+x small,pc
3,+x small,sp
3,+x small,x
3,+x small,y
8,+sp 3,+x
8,+sp 5,-y
8,+sp 5,sp
8,+sp ext
8,+x 3,+x
8,+x 5,-y
8,+x 5,sp
8,+x ext
8,+y 3,+x
8,+y 5,-y
8,+y 5,sp
8,+y ext
,pc 3,+x
,pc 5,-y
,pc 5,sp
,pc ext
,sp 3,+x
,sp 5,-y
,sp 5,sp
,sp ext
,x 3,+x
,x 5,-y
,x 5,sp
f82d
f832
f836
f83a
f83e
f843
f847
f84b
f84f
f854
f858
f85c
f860
f865
f869
f86d
f871
f876
f87a
f87e
f882
f887
f88b
f88f
f893
f898
f89c
f8a0
f8a4
f8a9
f8ad
f8b1
f8b5
f8ba
f8be
f8c2
f8c6
f8cb
f8cf
f8d3
f8d7
f8dc
f8e0
f8e4
f8e8
f8ed
f8f1
f8f5
f8f9
f8fe
f902
f906
f90a
f90f
f913
f917
f91b
f920
f924
f928
f92c
f931
f935
f939
f93d
f942
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
01
02
02
02
01
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
ASSEMBLY LISTING
00
40
40
40
40
af
af
af
af
2f
2f
2f
2f
6f
6f
6f
6f
a8
a8
a8
a8
28
28
28
28
68
68
68
68
9f
9f
9f
9f
1f
1f
1f
1f
5f
5f
5f
5f
90
90
90
90
10
10
10
10
50
50
50
50
d2
d2
d2
d2
92
92
92
92
12
12
12
12
52
00
22
6b
85
00
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
00
00
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
,x ext
,y 3,+x
,y 5,-y
,y 5,sp
,y ext
1,-sp 3,+x
1,-sp 5,-y
1,-sp 5,sp
1,-sp ext
1,-x 3,+x
1,-x 5,-y
1,-x 5,sp
1,-x ext
1,-y 3,+x
1,-y 5,-y
1,-y 5,sp
1,-y ext
8,-sp 3,+x
8,-sp 5,-y
8,-sp 5,sp
8,-sp ext
8,-x 3,+x
8,-x 5,-y
8,-x 5,sp
8,-x ext
8,-y 3,+x
8,-y 5,-y
8,-y 5,sp
8,-y ext
-1,sp 3,+x
-1,sp 5,-y
-1,sp 5,sp
-1,sp ext
-1,x 3,+x
-1,x 5,-y
-1,x 5,sp
-1,x ext
-1,y 3,+x
-1,y 5,-y
-1,y 5,sp
-1,y ext
-16,sp 3,+x
-16,sp 5,-y
-16,sp 5,sp
-16,sp ext
-16,x 3,+x
-16,x 5,-y
-16,x 5,sp
-16,x ext
-16,y 3,+x
-16,y 5,-y
-16,y 5,sp
-16,y ext
-small,pc 3,+x
-small,pc 5,-y
-small,pc 5,sp
-small,pc ext
-small,sp 3,+x
-small,sp 5,-y
-small,sp 5,sp
-small,sp ext
-small,x 3,+x
-small,x 5,-y
-small,x 5,sp
-small,x ext
-small,y 3,+x
CPU12
REFERENCE MANUAL
f946
f94a
f94e
f953
f957
f95b
f95f
f964
f968
f96c
f970
f975
f979
f97d
f981
f986
f98a
f98e
f992
f997
f99b
f99f
f9a3
f9a8
f9ac
f9b0
f9b4
f9b9
f9bd
f9c1
f9c5
f9ca
f9ce
f9d2
f9d6
f9db
f9df
f9e3
f9e7
f9ec
f9f0
f9f4
f9f8
f9fd
fa01
fa05
fa09
fa0e
fa12
fa16
fa1a
fa1f
fa23
fa27
fa2b
fa30
fa34
fa38
fa3c
fa40
fa44
fa48
fa4c
fa50
fa54
fa58
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
02
02
02
02
02
02
02
02
52
52
52
c0
c0
c0
c0
80
80
80
80
00
00
00
00
40
40
40
40
b0
b0
b0
b0
30
30
30
30
70
70
70
70
81
81
81
81
01
01
01
01
41
41
41
41
bf
bf
bf
bf
3f
3f
3f
3f
7f
7f
7f
7f
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
a0
20
60
a7
27
67
c0
80
00
40
af
88
88
88
88
88
88
88
88
88
88
88
88
88
88
CPU12
REFERENCE MANUAL
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
-small,y 5,-y
-small,y 5,sp
-small,y ext
0,pc 3,+x
0,pc 5,-y
0,pc 5,sp
0,pc ext
0,sp 3,+x
0,sp 5,-y
0,sp 5,sp
0,sp ext
0,x 3,+x
0,x 5,-y
0,x 5,sp
0,x ext
0,y 3,+x
0,y 5,-y
0,y 5,sp
0,y ext
1,sp+ 3,+x
1,sp+ 5,-y
1,sp+ 5,sp
1,sp+ ext
1,x+ 3,+x
1,x+ 5,-y
1,x+ 5,sp
1,x+ ext
1,y+ 3,+x
1,y+ 5,-y
1,y+ 5,sp
1,y+ ext
1,sp 3,+x
1,sp 5,-y
1,sp 5,sp
1,sp ext
1,x 3,+x
1,x 5,-y
1,x 5,sp
1,x ext
1,y 3,+x
1,y 5,-y
1,y 5,sp
1,y ext
1,sp- 3,+x
1,sp- 5,-y
1,sp- 5,sp
1,sp- ext
1,x- 3,+x
1,x- 5,-y
1,x- 5,sp
1,x- ext
1,y- 3,+x
1,y- 5,-y
1,y- 5,sp
1,y- ext
5,-y 1,+sp
5,-y 1,+x
5,-y 1,+y
5,-y 8,+sp
5,-y 8,+x
5,-y 8,+y
5,-y ,pc
5,-y ,sp
5,-y ,x
5,-y ,y
5,-y 1,-sp
fa5c
fa60
fa64
fa68
fa6c
fa70
fa74
fa78
fa7c
fa80
fa84
fa88
fa8c
fa90
fa94
fa98
fa9c
faa0
faa4
faa8
faac
fab0
fab4
fab8
fabc
fac0
fac4
fac8
facc
fad0
fad4
fad8
fadc
fae0
fae4
fae8
faec
faf0
faf4
faf8
fafc
fb00
fb04
fb08
fb0c
fb10
fb14
fb19
fb1d
fb21
fb25
fb29
fb2d
fb31
fb35
fb3a
fb3e
fb42
fb46
fb4b
fb4f
fb53
fb57
fb5c
fb60
fb64
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
ASSEMBLY LISTING
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
05
02
02
02
02
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
8f
8f
8f
8f
0f
0f
0f
0f
4f
4f
4f
4f
85
85
85
2f
6f
a8
28
68
9f
1f
5f
90
10
50
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
8f
0f
4f
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
01
ce
8e
0e
4e
22
6b
85
01
22
6b
85
01
22
6b
85
01
a0
20
60
88
88
88
88
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
5,-y 1,-x
5,-y 1,-y
5,-y 8,-sp
5,-y 8,-x
5,-y 8,-y
5,-y -1,sp
5,-y -1,x
5,-y -1,y
5,-y -16,sp
5,-y -16,x
5,-y -16,y
5,-y -small,pc
5,-y -small,sp
5,-y -small,x
5,-y -small,y
5,-y 0,pc
5,-y 0,sp
5,-y 0,x
5,-y 0,y
5,-y 1,sp+
5,-y 1,x+
5,-y 1,y+
5,-y 1,sp
5,-y 1,x
5,-y 1,y
5,-y 1,sp5,-y 1,x5,-y 1,y5,-y 15,sp
5,-y 15,x
5,-y 15,y
5,-y 8,sp+
5,-y 8,x+
5,-y 8,y+
5,-y 8,sp5,-y 8,x5,-y 8,y5,-y a,sp
5,-y a,x
5,-y a,y
5,-y b,sp
5,-y b,x
5,-y b,y
5,-y d,sp
5,-y d,x
5,-y d,y
5,-y ext
5,-y small,pc
5,-y small,sp
5,-y small,x
5,-y small,y
15,sp 3,+x
15,sp 5,-y
15,sp 5,sp
15,sp ext
15,x 3,+x
15,x 5,-y
15,x 5,sp
15,x ext
15,y 3,+x
15,y 5,-y
15,y 5,sp
15,y ext
5,sp 1,+sp
5,sp 1,+x
5,sp 1,+y
MOTOROLA
D-29
fb68
fb6c
fb70
fb74
fb78
fb7c
fb80
fb84
fb88
fb8c
fb90
fb94
fb98
fb9c
fba0
fba4
fba8
fbac
fbb0
fbb4
fbb8
fbbc
fbc0
fbc4
fbc8
fbcc
fbd0
fbd4
fbd8
fbdc
fbe0
fbe4
fbe8
fbec
fbf0
fbf4
fbf8
fbfc
fc00
fc04
fc08
fc0c
fc10
fc14
fc18
fc1c
fc20
fc24
fc28
fc2c
fc30
fc34
fc39
fc3d
fc41
fc45
fc49
fc4d
fc51
fc55
fc5a
fc5e
fc62
fc66
fc6b
fc6f
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
02
05
02
02
02
02
02
02
02
05
02
02
02
05
02
02
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
b7
b7
b7
b7
37
37
37
37
77
77
MOTOROLA
D-30
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
01 88
ce
8e
0e
4e
22
6b
85
01 88
22
6b
85
01 88
22
6b
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
5,sp 8,+sp
5,sp 8,+x
5,sp 8,+y
5,sp ,pc
5,sp ,sp
5,sp ,x
5,sp ,y
5,sp 1,-sp
5,sp 1,-x
5,sp 1,-y
5,sp 8,-sp
5,sp 8,-x
5,sp 8,-y
5,sp -1,sp
5,sp -1,x
5,sp -1,y
5,sp -16,sp
5,sp -16,x
5,sp -16,y
5,sp -small,pc
5,sp -small,sp
5,sp -small,x
5,sp -small,y
5,sp 0,pc
5,sp 0,sp
5,sp 0,x
5,sp 0,y
5,sp 1,sp+
5,sp 1,x+
5,sp 1,y+
5,sp 1,sp
5,sp 1,x
5,sp 1,y
5,sp 1,sp5,sp 1,x5,sp 1,y5,sp 8,sp+
5,sp 8,x+
5,sp 8,y+
5,sp 8,sp5,sp 8,x5,sp 8,y5,sp a,sp
5,sp a,x
5,sp a,y
5,sp b,sp
5,sp b,x
5,sp b,y
5,sp d,sp
5,sp d,x
5,sp d,y
5,sp ext
5,sp small,pc
5,sp small,sp
5,sp small,x
5,sp small,y
8,sp+ 3,+x
8,sp+ 5,-y
8,sp+ 5,sp
8,sp+ ext
8,x+ 3,+x
8,x+ 5,-y
8,x+ 5,sp
8,x+ ext
8,y+ 3,+x
8,y+ 5,-y
fc73
fc77
fc7c
fc80
fc84
fc88
fc8d
fc91
fc95
fc99
fc9e
fca2
fca6
fcaa
fcaf
fcb3
fcb7
fcbb
fcc0
fcc4
fcc8
fccc
fcd1
fcd5
fcd9
fcdd
fce2
fce6
fcea
fcee
fcf3
fcf7
fcfb
fcff
fd04
fd08
fd0c
fd10
fd15
fd19
fd1d
fd21
fd26
fd2a
fd2e
fd32
fd37
fd3b
fd3f
fd43
fd48
fd4d
fd52
fd57
fd5c
fd61
fd66
fd6b
fd70
fd75
fd7a
fd7f
fd84
fd89
fd8e
fd93
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
ASSEMBLY LISTING
77
77
b8
b8
b8
b8
38
38
38
38
78
78
78
78
f4
f4
f4
f4
e4
e4
e4
e4
ec
ec
ec
ec
f5
f5
f5
f5
e5
e5
e5
e5
ed
ed
ed
ed
f6
f6
f6
f6
e6
e6
e6
e6
ee
ee
ee
ee
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
8,y+ 5,sp
8,y+ ext
8,sp- 3,+x
8,sp- 5,-y
8,sp- 5,sp
8,sp- ext
8,x- 3,+x
8,x- 5,-y
8,x- 5,sp
8,x- ext
8,y- 3,+x
8,y- 5,-y
8,y- 5,sp
8,y- ext
a,sp 3,+x
a,sp 5,-y
a,sp 5,sp
a,sp ext
a,x 3,+x
a,x 5,-y
a,x 5,sp
a,x ext
a,y 3,+x
a,y 5,-y
a,y 5,sp
a,y ext
b,sp 3,+x
b,sp 5,-y
b,sp 5,sp
b,sp ext
b,x 3,+x
b,x 5,-y
b,x 5,sp
b,x ext
b,y 3,+x
b,y 5,-y
b,y 5,sp
b,y ext
d,sp 3,+x
d,sp 5,-y
d,sp 5,sp
d,sp ext
d,x 3,+x
d,x 5,-y
d,x 5,sp
d,x ext
d,y 3,+x
d,y 5,-y
d,y 5,sp
d,y ext
ext 1,+sp
ext 1,+x
ext 1,+y
ext 8,+sp
ext 8,+x
ext 8,+y
ext ,pc
ext ,sp
ext ,x
ext ,y
ext 1,-sp
ext 1,-x
ext 1,-y
ext 8,-sp
ext 8,-x
ext 8,-y
CPU12
REFERENCE MANUAL
fd98
fd9d
fda2
fda7
fdac
fdb1
fdb6
fdbb
fdc0
fdc5
fdca
fdcf
fdd4
fdd9
fdde
fde3
fde8
fded
fdf2
fdf7
fdfc
fe01
fe06
fe0b
fe10
fe15
fe1a
fe1f
fe24
fe29
fe2e
fe33
fe38
fe3d
fe42
fe47
fe4c
fe51
fe56
fe5c
fe61
fe66
fe6b
fe70
fe74
fe78
fe7c
fe81
fe85
fe89
fe8d
fe92
fe96
fe9a
fe9e
fea3
fea7
feab
feaf
feb4
feb5
feb7
feb9
febb
febd
febf
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
12
60
60
60
60
60
60
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
04
01
01
01
01
02
02
02
05
02
02
02
05
02
02
02
05
02
02
02
05
9f
1f
5f
90
10
50
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
01
ce
8e
0e
4e
ce
ce
ce
ce
8e
8e
8e
8e
0e
0e
0e
0e
4e
4e
4e
4e
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
88
01
01
01
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
22
6b
85
01
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
01 88
88
88
88
88
88
88
88
88
a0
20
60
a7
27
67
CPU12
REFERENCE MANUAL
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
movw
mul
neg
neg
neg
neg
neg
neg
ext -1,sp
ext -1,x
ext -1,y
ext -16,sp
ext -16,x
ext -16,y
ext -small,pc
ext -small,sp
ext -small,x
ext -small,y
ext 0,pc
ext 0,sp
ext 0,x
ext 0,y
ext 1,sp+
ext 1,x+
ext 1,y+
ext 1,sp
ext 1,x
ext 1,y
ext 1,spext 1,xext 1,yext 8,sp+
ext 8,x+
ext 8,y+
ext 8,spext 8,xext 8,yext a,sp
ext a,x
ext a,y
ext b,sp
ext b,x
ext b,y
ext d,sp
ext d,x
ext d,y
ext ext
ext small,pc
ext small,sp
ext small,x
ext small,y
small,pc 3,+x
small,pc 5,-y
small,pc 5,sp
small,pc ext
small,sp 3,+x
small,sp 5,-y
small,sp 5,sp
small,sp ext
small,x 3,+x
small,x 5,-y
small,x 5,sp
small,x ext
small,y 3,+x
small,y 5,-y
small,y 5,sp
small,y ext
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
fec1
fec3
fec5
fec7
fec9
fecb
fecd
fecf
fed1
fed3
fed5
fed7
fed9
fedb
fedd
fedf
fee1
fee4
fee7
feea
feec
feee
fef0
fef2
fef4
fef6
fef8
fefa
fefc
fefe
ff00
ff02
ff04
ff06
ff08
ff0a
ff0c
ff0f
ff12
ff15
ff18
ff1a
ff1c
ff1e
ff21
ff24
ff27
ff29
ff2b
ff2d
ff2f
ff31
ff33
ff35
ff37
ff39
ff3b
ff3d
ff3f
ff41
ff43
ff45
ff48
ff4b
ff4e
ff52
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
70
70
70
60
60
ASSEMBLY LISTING
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
00
01
01
f2
e2
ef
ef
ef
7d
7d
7d
7d
10
10
10
55
88
88
01 88
01 88
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
neg
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext
ext,sp
ext,x
MOTOROLA
D-31
ff56
ff5a
ff5d
ff60
ff63
ff66
ff68
ff6a
ff6c
ff6e
ff6f
ff70
ff71
ff73
ff75
ff77
ff79
ff7b
ff7d
ff7f
ff81
ff83
ff85
ff87
ff89
ff8b
ff8d
ff8f
ff91
ff93
ff95
ff97
ff99
ff9b
ff9d
ff9f
ffa1
ffa4
ffa7
ffaa
ffac
ffae
ffb0
ffb2
ffb4
ffb6
ffb8
ffba
ffbc
ffbe
ffc0
ffc2
ffc4
ffc6
ffc8
ffca
ffcc
ffcf
ffd2
ffd5
ffd8
ffda
ffdc
ffde
ffe1
ffe4
60
60
60
60
60
60
60
60
60
40
50
a7
8a
8a
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
ea
f8
f0
e0
e8
ce
8e
0e
4e
72
72
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
01 88
37
37
37
37
ef
ef
ef
7d
7d
7d
7d
10
10
10
MOTOROLA
D-32
neg
neg
neg
neg
neg
neg
neg
neg
neg
nega
negb
nop
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
ffe7
ffe9
ffeb
ffed
ffef
fff1
fff3
fff5
fff7
fff9
fffb
fffd
ffff
0001
0003
0005
0007
0009
000c
000f
0013
0017
001b
001e
0021
0024
0027
0029
002b
002d
002f
0031
0033
0035
0037
0039
003b
003d
003f
0041
0043
0045
0047
0049
004b
004d
004f
0051
0053
0055
0057
0059
005b
005d
005f
0062
0065
0068
006a
006c
006e
0070
0072
0074
0076
0078
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
9a
9a
ba
ba
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
aa
ca
ca
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
72
72
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
ASSEMBLY LISTING
88
88
01 88
01 88
01 88
37
37
37
37
ef
ef
ef
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
oraa
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
CPU12
REFERENCE MANUAL
007a
007c
007e
0080
0082
0084
0086
0088
008a
008d
0090
0093
0096
0098
009a
009c
009f
00a2
00a5
00a7
00a9
00ab
00ad
00af
00b1
00b3
00b5
00b7
00b9
00bb
00bd
00bf
00c1
00c3
00c5
00c7
00ca
00cd
00d1
00d5
00d9
00dc
00df
00e2
00e5
00e7
00e9
00eb
00ed
00ef
00f0
00f1
00f2
00f3
00f4
00f5
00f6
00f7
00f8
00f9
00fa
00fc
00fe
0100
0102
0104
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
da
da
fa
fa
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
ea
14
36
37
3b
34
35
32
33
38
3a
30
31
18
65
65
65
65
65
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
72
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
3a
a0
20
60
a7
27
CPU12
REFERENCE MANUAL
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orab
orcc
psha
pshb
pshd
pshx
pshy
pula
pulb
pulc
puld
pulx
puly
rev
rol
rol
rol
rol
rol
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
0106
0108
010a
010c
010e
0110
0112
0114
0116
0118
011a
011c
011e
0120
0122
0124
0126
0128
012b
012e
0131
0133
0135
0137
0139
013b
013d
013f
0141
0143
0145
0147
0149
014b
014d
014f
0151
0153
0156
0159
015c
015f
0161
0163
0165
0168
016b
016e
0170
0172
0174
0176
0178
017a
017c
017e
0180
0182
0184
0186
0188
018a
018c
018f
0192
0195
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
75
75
75
65
ASSEMBLY LISTING
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
00
01
01
f2
ef
ef
ef
7d
7d
7d
7d
10
10
10
55
88
88
01 88
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext
ext,sp
MOTOROLA
D-33
0199
019d
01a1
01a4
01a7
01aa
01ad
01af
01b1
01b3
01b5
01b6
01b7
01b9
01bb
01bd
01bf
01c1
01c3
01c5
01c7
01c9
01cb
01cd
01cf
01d1
01d3
01d5
01d7
01d9
01db
01dd
01df
01e1
01e3
01e6
01e9
01ec
01ee
01f0
01f2
01f4
01f6
01f8
01fa
01fc
01fe
0200
0202
0204
0206
0208
020a
020c
020e
0211
0214
0217
021a
021c
021e
0220
0223
0226
0229
022b
65
65
65
65
65
65
65
65
65
65
45
55
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
01 88
01 88
37
37
37
37
ef
ef
ef
7d
7d
7d
7d
10
10
10
MOTOROLA
D-34
rol
rol
rol
rol
rol
rol
rol
rol
rol
rol
rola
rolb
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
022d
022f
0231
0233
0235
0237
0239
023b
023d
023f
0241
0243
0245
0247
024a
024d
0250
0254
0258
025c
025f
0262
0265
0268
026a
026c
026e
0270
0271
0272
0273
0274
0276
0278
027a
027c
027e
0280
0282
0284
0286
0288
028a
028c
028e
0290
0292
0294
0296
0298
029a
029c
029e
02a0
02a2
02a4
02a6
02a9
02ac
02af
02b1
02b3
02b5
02b7
02b9
02bb
66
66
66
66
66
66
66
66
66
66
66
66
66
76
76
76
66
66
66
66
66
66
66
66
66
66
66
46
56
0b
3d
18
82
82
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
00
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
55
88
88
01 88
01 88
01 88
37
37
37
37
16
72
72
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1 ef
e1 ef
e9 ef
d2
92
12
52
c0
80
00
ASSEMBLY LISTING
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
ror
rora
rorb
rti
rts
sba
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
CPU12
REFERENCE MANUAL
02bd
02bf
02c1
02c3
02c5
02c7
02c9
02cb
02cd
02cf
02d1
02d4
02d7
02da
02dd
02df
02e1
02e3
02e6
02e9
02ec
02ee
02f0
02f2
02f4
02f6
02f8
02fa
02fc
02fe
0300
0302
0304
0306
0308
030a
030c
030e
0311
0314
0318
031c
0320
0323
0326
0329
032c
032e
0330
0332
0334
0336
0338
033a
033c
033e
0340
0342
0344
0346
0348
034a
034c
034e
0350
0352
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
92
92
b2
b2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
a2
c2
c2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
72
72
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
CPU12
REFERENCE MANUAL
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbca
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
0354
0356
0358
035a
035c
035e
0360
0362
0364
0367
036a
036d
036f
0371
0373
0375
0377
0379
037b
037d
037f
0381
0383
0385
0387
0389
038b
038d
038f
0392
0395
0398
039b
039d
039f
03a1
03a4
03a7
03aa
03ac
03ae
03b0
03b2
03b4
03b6
03b8
03ba
03bc
03be
03c0
03c2
03c4
03c6
03c8
03ca
03cc
03cf
03d2
03d6
03da
03de
03e1
03e4
03e7
03ea
03ec
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
e2
d2
d2
f2
f2
e2
e2
e2
e2
e2
e2
e2
e2
e2
ASSEMBLY LISTING
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
ef
ef
ef
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
sbcb
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
MOTOROLA
D-35
03ee
03f0
03f2
03f4
03f6
03f8
03fa
03fc
03fe
0400
0402
0404
0406
0408
040a
040c
040e
0410
0412
0414
0416
0418
041a
041c
041e
0420
0422
0424
0426
0428
042a
042c
042e
0430
0432
0434
0436
0438
043a
043c
043e
0440
0442
0444
0446
0448
044b
044e
0451
0453
0455
0457
0459
045b
045d
045f
0461
0463
0465
0467
0469
046b
046d
046f
0471
0473
e2
e2
14
14
14
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
0e
4e
01
10
02
04
07
07
05
05
06
06
14
17
17
15
15
16
16
24
27
25
26
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
ef
ef
ef
7d
MOTOROLA
D-36
sbcb
sbcb
sec
sei
sev
sex
sex
sex
sex
sex
sex
sex
sex
sex
sex
sex
sex
sex
sex
sex
sex
sex
sex
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
small,x
small,y
a d
a sp
a,sp
a x
a,x
a y
a,y
b d
b sp
b,sp
b x
b,x
b y
b,y
ccr d
ccr sp
ccr x
ccr y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
0476
0479
047c
047f
0481
0483
0485
0488
048b
048e
0490
0492
0494
0496
0498
049a
049c
049e
04a0
04a2
04a4
04a6
04a8
04aa
04ac
04ae
04b0
04b3
04b6
04ba
04be
04c2
04c5
04c8
04cb
04ce
04d0
04d2
04d4
04d6
04d8
04da
04dc
04de
04e0
04e2
04e4
04e6
04e8
04ea
04ec
04ee
04f0
04f2
04f4
04f6
04f8
04fa
04fc
04fe
0500
0502
0505
0508
050b
050d
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
5a
5a
7a
7a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6a
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
ASSEMBLY LISTING
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
ef
ef
ef
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
staa
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
CPU12
REFERENCE MANUAL
050f
0511
0513
0515
0517
0519
051b
051d
051f
0521
0523
0525
0527
0529
052b
052d
0530
0533
0536
0539
053b
053d
053f
0542
0545
0548
054a
054c
054e
0550
0552
0554
0556
0558
055a
055c
055e
0560
0562
0564
0566
0568
056a
056d
0570
0574
0578
057c
057f
0582
0585
0588
058a
058c
058e
0590
0592
0594
0596
0598
059a
059c
059e
05a0
05a2
05a4
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
5b
5b
7b
7b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6b
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
CPU12
REFERENCE MANUAL
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
stab
std
std
std
std
std
std
std
std
std
std
std
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
05a6
05a8
05aa
05ac
05ae
05b0
05b2
05b4
05b6
05b8
05ba
05bc
05bf
05c2
05c5
05c7
05c9
05cb
05cd
05cf
05d1
05d3
05d5
05d7
05d9
05db
05dd
05df
05e1
05e3
05e5
05e7
05ea
05ed
05f0
05f3
05f5
05f7
05f9
05fc
05ff
0602
0604
0606
0608
060a
060c
060e
0610
0612
0614
0616
0618
061a
061c
061e
0620
0622
0624
0627
062a
062e
0632
0636
0639
063c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
6c
5c
5c
7c
7c
6c
6c
6c
6c
6c
6c
ASSEMBLY LISTING
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
ef
ef
ef
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
std
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
MOTOROLA
D-37
063f
0642
0644
0646
0648
064a
064c
064e
0650
0652
0654
0656
0658
065a
065c
065e
0660
0662
0664
0666
0668
066a
066c
066e
0670
0672
0674
0676
0678
067b
067e
0681
0683
0685
0687
0689
068b
068d
068f
0691
0693
0695
0697
0699
069b
069d
069f
06a1
06a3
06a6
06a9
06ac
06af
06b1
06b3
06b5
06b8
06bb
06be
06c0
06c2
06c4
06c6
06c8
06ca
06cc
6c
6c
6c
6c
6c
18
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
e8
ce
8e
0e
4e
3e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
37
ef
ef
ef
7d
7d
7d
7d
10
10
10
MOTOROLA
D-38
std
std
std
std
std
stop
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
06ce
06d0
06d2
06d4
06d6
06d8
06da
06dc
06de
06e1
06e5
06e9
06ed
06f0
06f3
06f6
06f9
06fb
06fd
06ff
0701
0703
0705
0707
0709
070b
070d
070f
0711
0713
0715
0717
0719
071b
071d
071f
0721
0723
0725
0727
0729
072b
072d
0730
0733
0736
0738
073a
073c
073e
0740
0742
0744
0746
0748
074a
074c
074e
0750
0752
0754
0756
0758
075b
075e
0761
6f
6f
6f
6f
6f
6f
6f
5f
7f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6f
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
ec
f5
e5
ed
f6
e6
ee
55
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
ASSEMBLY LISTING
88
01 88
01 88
01 88
37
37
37
37
ef
ef
ef
7d
7d
7d
7d
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
CPU12
REFERENCE MANUAL
0764
0766
0768
076a
076d
0770
0773
0775
0777
0779
077b
077d
077f
0781
0783
0785
0787
0789
078b
078d
078f
0791
0793
0795
0798
079b
079f
07a3
07a7
07aa
07ad
07b0
07b3
07b5
07b7
07b9
07bb
07bd
07bf
07c1
07c3
07c5
07c7
07c9
07cb
07cd
07cf
07d1
07d3
07d5
07d7
07d9
07db
07dd
07df
07e1
07e3
07e5
07e7
07ea
07ed
07f0
07f2
07f4
07f6
07f8
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
5e
5e
7e
7e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6e
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
ef
ef
ef
CPU12
REFERENCE MANUAL
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
stx
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
07fa
07fc
07fe
0800
0802
0804
0806
0808
080a
080c
080e
0810
0812
0815
0818
081b
081e
0820
0822
0824
0827
082a
082d
082f
0831
0833
0835
0837
0839
083b
083d
083f
0841
0843
0845
0847
0849
084b
084d
084f
0852
0855
0859
085d
0861
0864
0867
086a
086d
086f
0871
0873
0875
0877
0879
087b
087d
087f
0881
0883
0885
0887
0889
088b
088d
088f
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
5d
5d
7d
7d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
6d
80
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
ASSEMBLY LISTING
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
72
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
7d
7d
7d
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
sty
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
MOTOROLA
D-39
0891
0893
0895
0897
0899
089b
089d
089f
08a1
08a3
08a6
08a9
08ac
08ae
08b0
08b2
08b4
08b6
08b8
08ba
08bc
08be
08c0
08c2
08c4
08c6
08c8
08ca
08cc
08ce
08d1
08d4
08d7
08da
08dc
08de
08e0
08e3
08e6
08e9
08eb
08ed
08ef
08f1
08f3
08f5
08f7
08f9
08fb
08fd
08ff
0901
0903
0905
0907
0909
090c
0910
0914
0918
091b
091e
0921
0924
0926
0928
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
90
b0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a0
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
ef
ef
ef
7d
7d
7d
7d
10
10
10
88
01 88
01 88
01 88
37
37
37
37
MOTOROLA
D-40
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
suba
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
092a
092c
092e
0930
0932
0934
0936
0938
093a
093c
093e
0940
0942
0944
0946
0948
094a
094c
094e
0950
0952
0954
0956
0958
095a
095c
095f
0962
0965
0967
0969
096b
096d
096f
0971
0973
0975
0977
0979
097b
097d
097f
0981
0983
0985
0987
098a
098d
0990
0993
0995
0997
0999
099c
099f
09a2
09a4
09a6
09a8
09aa
09ac
09ae
09b0
09b2
09b4
09b6
a0
c0
c0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
4e
72
72
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ASSEMBLY LISTING
ef
ef
ef
7d
7d
7d
7d
10
10
10
suba
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
CPU12
REFERENCE MANUAL
09b8
09ba
09bc
09be
09c0
09c2
09c4
09c7
09ca
09ce
09d2
09d6
09d9
09dc
09df
09e2
09e4
09e6
09e8
09ea
09ed
09f0
09f2
09f4
09f6
09f8
09fa
09fc
09fe
0a00
0a02
0a04
0a06
0a08
0a0a
0a0c
0a0e
0a10
0a12
0a14
0a16
0a18
0a1a
0a1c
0a1f
0a22
0a25
0a27
0a29
0a2b
0a2d
0a2f
0a31
0a33
0a35
0a37
0a39
0a3b
0a3d
0a3f
0a41
0a43
0a45
0a47
0a4a
0a4d
e0
e0
e0
e0
d0
d0
f0
f0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
e0
83
83
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
00
00
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1
e1
e9
d2
92
12
52
c0
80
00
40
b0
30
70
81
01
41
bf
3f
7f
f8
f0
e0
88
88
01 88
01 88
01 88
37
37
37
37
72
72
ef
ef
ef
7d
7d
7d
CPU12
REFERENCE MANUAL
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subb
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
#immed
#immed
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
0a50
0a53
0a55
0a57
0a59
0a5c
0a5f
0a62
0a64
0a66
0a68
0a6a
0a6c
0a6e
0a70
0a72
0a74
0a76
0a78
0a7a
0a7c
0a7e
0a80
0a82
0a84
0a87
0a8a
0a8e
0a92
0a96
0a99
0a9c
0a9f
0aa2
0aa4
0aa6
0aa8
0aaa
0aab
0aad
0aaf
0ab1
0ab3
0ab6
0ab8
0aba
0abc
0abe
0ac0
0ac2
0ac4
0ac6
0ac8
0aca
0acc
0ace
0ad0
0ad2
0ad4
0ad6
0ad8
0ada
0adc
0ade
0ae0
0ae2
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
93
93
b3
b3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
a3
3f
b7
18
b7
18
18
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
ASSEMBLY LISTING
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
55
55
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
7d
10
10
10
88
88
01 88
01 88
01 88
37
37
37
37
c4
0e
02
0f
3d e5
00
00
01
01
02
04
07
05
05
06
06
10
11
12
14
17
15
16
20
21
22
24
27
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
subd
swi
swpb
tab
tap
tba
tbl
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
d
b,x
a a
a,a
a b
a,b
a ccr
a d
a sp
a x
a,x
a y
a,y
b a
b b
b ccr
b d
b sp
b x
b y
ccr a
ccr b
ccr ccr
ccr d
ccr sp
MOTOROLA
D-41
0ae4
0ae6
0ae8
0aea
0aec
0aee
0af0
0af2
0af4
0af6
0af8
0afa
0afc
0afe
0b00
0b02
0b04
0b06
0b08
0b0a
0b0c
0b0e
0b10
0b12
0b14
0b16
0b18
0b1a
0b1c
0b1e
0b20
0b22
0b24
0b26
0b28
0b2a
0b2c
0b2e
0b30
0b32
0b34
0b36
0b38
0b3a
0b3c
0b3e
0b40
0b42
0b44
0b46
0b48
0b4a
0b4c
0b4e
0b51
0b54
0b57
0b59
0b5b
0b5d
0b5f
0b61
0b63
0b65
0b67
0b69
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
25
26
40
41
42
44
47
45
46
70
71
72
74
77
75
76
50
51
52
54
57
55
56
60
61
62
64
67
65
66
20
a0
20
60
a7
27
67
c0
80
00
40
af
2f
6f
a8
28
68
9f
1f
5f
90
10
50
f1 ef
e1 ef
e9 ef
d2
92
12
52
c0
80
00
40
b0
30
MOTOROLA
D-42
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tfr
tpa
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
ccr x
ccr y
d a
d b
d ccr
d d
d sp
d x
d y
sp a
sp b
sp ccr
sp d
sp sp
sp x
sp y
x a
x b
x ccr
x d
x sp
x x
x y
y a
y b
y ccr
y d
y sp
y x
y y
1,+sp
1,+x
1,+y
8,+sp
8,+x
8,+y
,pc
,sp
,x
,y
1,-sp
1,-x
1,-y
8,-sp
8,-x
8,-y
-1,sp
-1,x
-1,y
-16,sp
-16,x
-16,y
-17,sp
-17,x
-17,y
-small,pc
-small,sp
-small,x
-small,y
0,pc
0,sp
0,x
0,y
1,sp+
1,x+
0b6b
0b6d
0b6f
0b71
0b73
0b75
0b77
0b79
0b7c
0b7f
0b82
0b85
0b87
0b89
0b8b
0b8e
0b91
0b94
0b96
0b98
0b9a
0b9c
0b9e
0ba0
0ba2
0ba4
0ba6
0ba8
0baa
0bac
0bae
0bb0
0bb2
0bb5
0bb8
0bbb
0bbf
0bc3
0bc7
0bca
0bcd
0bd0
0bd3
0bd5
0bd7
0bd9
0bdb
0bdc
0bdd
0bdf
0be1
0be3
0be5
0be7
0be8
0bea
0bec
0bee
0bef
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
f7
f7
f7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
e7
97
d7
b7
b7
b7
b7
18
3e
18
b7
b7
39
0a
70
81
01
41
bf
3f
7f
f8
f0
e0
e8
8f
0f
4f
f0
e0
e8
b7
37
77
b8
38
78
f4
e4
ec
f5
e5
ed
f6
e6
ee
00
01
01
f2
e2
ea
f8
f0
e0
e8
ce
8e
0e
4e
75
76
57
67
39
3c
c5
c6
ASSEMBLY LISTING
7d
7d
7d
7d
10
10
10
55
88
88
01 88
01 88
01 88
37
37
37
37
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tst
tsta
tstb
tsx
tsy
txs
tys
trap
wai
wav
xgdx
xgdy
pshc
rtc
1,y+
1,sp
1,x
1,y
1,sp1,x1,y125,pc
125,sp
125,x
125,y
15,sp
15,x
15,y
16,sp
16,x
16,y
8,sp+
8,x+
8,y+
8,sp8,x8,ya,sp
a,x
a,y
b,sp
b,x
b,y
d,sp
d,x
d,y
dir
ext
ext
ext,sp
ext,x
ext,y
ind,pc
ind,sp
ind,x
ind,y
small,pc
small,sp
small,x
small,y
$39
CPU12
REFERENCE MANUAL
INDEX
A
ABA instruction 6-8
Abbreviations for system resources 1-2
ABX instruction 6-9
ABY instruction 6-10
Accumulator direct indexed addressing mode 3-9
Accumulator offset indexed addressing mode 3-9
Accumulators 2-1, 5-8, 5-19
A 2-1, 3-5, 5-8, 6-8, 6-11, 6-13, 6-15 to 6-16,
6-20, 6-24, 6-35, 6-53, 6-57, 6-60, 6-63,
6-69 to 6-71, 6-73, 6-87, 6-90, 6-92 to 6-93,
6-97, 6-122, 6-124, 6-132, 6-134, 6-136,
6-139 to 6-140, 6-142 to 6-143, 6-146,
6-148, 6-151, 6-154, 6-157, 6-160, 6-167,
6-169, 6-171, 6-174, 6-177, 6-179 to 6-180,
6-185 to 6-186, 6-193, 6-196 to 6-204, 6-207
B 2-1, 3-5, 5-8, 6-8 to 6-10, 6-12, 6-14 to 6-15,
6-17, 6-21, 6-25, 6-36, 6-53, 6-58, 6-61, 6-64,
6-70 to 6-71, 6-74, 6-88 to 6-90,
6-92 to 6-93, 6-98, 6-123 to 6-124, 6-133,
6-137, 6-146, 6-149, 6-152, 6-155, 6-161,
6-172, 6-175, 6-177, 6-179, 6-181, 6-185,
6-187, 6-194, 6-196 to 6-197,
6-199 to 6-203, 6-208
D 2-1, 3-5, 5-8, 6-15, 6-22, 6-65, 6-70 to 6-71,
6-78 to 6-79, 6-81 to 6-86, 6-89 to 6-95,
6-124, 6-134, 6-138, 6-146, 6-157, 6-163,
6-185, 6-188, 6-195 to 6-196, 6-200,
6-202 to 6-203, 6-215 to 6-216
Indexed addressing 3-9
ADCA instruction 6-11
ADCB instruction 6-12
ADDA instruction 6-13
ADDB instruction 6-14
ADDD instruction 6-15
Addition instructions 5-3, 6-8 to 6-15
ADDR mnemonic 1-3
Addressing modes 3-1
Direct 3-3
Extended 3-3
Immediate 3-2
Indexed 2-2, 3-5
Inherent 3-2
Memory expansion 10-7
Relative 3-4
ANDA instruction 6-16
ANDB instruction 6-17
ANDCC instruction 6-18
ASL instruction 6-19
ASLA instruction 6-20
ASLB instruction 6-21
ASLD instruction 6-22
ASR instruction 6-23
CPU12
REFERENCE MANUAL
ASRA instruction 6-24
ASRB instruction 6-25
Asserted 1-3
Automatic indexing 3-8
Automatic program stack 2-2
B
Background debugging mode 5-22, 8-6
BKGD pin 8-7 to 8-9
Commands 8-9 to 8-10
Enabling and disabling 8-6
Instruction 5-22, 6-31, 8-6
Registers 8-11
ROM 8-6
Serial interface 8-7 to 8-9
Base index register 3-6, 3-10
BCC instruction 6-26
BCLR instruction 6-27
BCS instruction 6-28
BEQ instruction 6-29
BGE instruction 6-30
BGND instruction 5-22, 6-31, 8-6
BGT instruction 6-32
BHI instruction 6-33
BHS instruction 6-34
Binary-coded decimal instructions 5-4, 6-8,
6-11 to 6-14, 6-69
Bit manipulation instructions 5-7, 6-27, 6-48, B-15,
C-1
Mask operand 3-11, 6-27, 6-48
Multiple addressing modes 3-11, 6-27, 6-48
Bit test instructions 5-7, 6-35 to 6-36, C-1
BITA instruction 6-35
BITB instruction 6-36
Bit-condition branches 5-16, 6-45, 6-47
BKGD pin 8-7 to 8-9
BLE instruction 6-37
BLO instruction 6-38
BLS instruction 6-39
BLT instruction 6-40
BMI instruction 6-41
BNE instruction 6-42
Boolean logic instructions 5-6
AND 6-16 to 6-18
Complement 6-62 to 6-64
Exclusive OR 6-87 to 6-88
Inclusive OR 6-151 to 6-153
Negate 6-147 to 6-149
BPL instruction 6-43
BRA instruction 6-44
Branch instructions 3-4, 4-4 to 4-5, 5-13, C-4
Bit-condition 4-4 to 4-5, 5-16, 6-45, 6-47
Long 4-4 to 4-5, 5-13, 6-104 to 6-121, B-13
MOTOROLA
I-1
Loop primitive 4-5, 5-16, 6-70 to 6-71,
6-92 to 6-93, 6-200, 6-202
Offset values 5-13, 5-16
Offsets 3-4
Short 4-4 to 4-5, 5-13, 6-26, 6-28 to 6-30,
6-32 to 6-34, 6-37 to 6-44, 6-46, 6-50 to 6-51
Signed 5-13, 6-30, 6-32, 6-37, 6-40,
6-107 to 6-108, 6-111, 6-114
Simple 5-13, 6-26, 6-28 to 6-29, 6-41 to 6-43,
6-50 to 6-51, 6-104 to 6-106, 6-115 to 6-117,
6-120 to 6-121
Subroutine 5-17, 6-49
Taken/not-taken cases 4-4, 6-7
Unary 5-13, 6-44, 6-46, 6-118 to 6-119
Unsigned 5-13, 6-33 to 6-34, 6-38 to 6-39,
6-109 to 6-110, 6-112 to 6-113
BRCLR instruction 6-45
BRN instruction 6-46
BRSET instruction 6-47
BSET instruction 6-48
BSR instruction 4-3, 6-49
Bus cycles 6-5
Bus structure B-4
BVC instruction 6-50
BVS instruction 6-51
Byte moves 6-144
Byte order in memory 2-5
Byte-sized instructions 4-4 to 4-5
C
C status bit 2-5, 6-19 to 6-26, 6-28, 6-33 to 6-34,
6-38 to 6-39, 6-54, 6-69, 6-72 to 6-74,
6-78 to 6-79, 6-81 to 6-86, 6-95 to 6-98,
6-104 to 6-105, 6-109 to 6-110,
6-112 to 6-113, 6-131 to 6-140,
6-142 to 6-143, 6-168, 6-170 to 6-175,
6-179 to 6-182, 6-193 to 6-195
CALL instruction 3-12, 4-3, 5-17, 6-52,
10-2 to 10-3, B-16, C-4 to C-5
Case statements C-4
CBA instruction 6-53
Changes in execution flow 4-2 to 4-5,
6-102 to 6-103, 6-176 to 6-178, 6-196,
7-1 to 7-6
CLC instruction 6-54
Clear instructions 5-6, 6-56 to 6-58
Cleared 1-3
CLI instruction 6-55
Clock monitor reset 7-3
CLR instruction 6-56
CLRA instruction 6-57
CLRB instruction 6-58
CLV instruction 6-59
CMPA instruction 6-60
MOTOROLA
I-2
CMPB instruction 6-61
Code size B-10
COM instruction 6-62
COMA instruction 6-63
COMB instruction 6-64
Compare instructions 5-5, 6-53, 6-60 to 6-61,
6-65 to 6-68
Complement instructions 5-6, 6-62 to 6-64
Computer operating properly monitor 7-3
Condition codes instructions 5-21, 6-18,
6-54 to 6-55, 6-59, 6-153, 6-156, 6-162,
6-182 to 6-184, 6-198, 6-203 to 6-204, B-15
Condition codes register 2-1, 2-3, 6-18,
6-54 to 6-55, 6-59, 6-90, 6-128, 6-153, 6-156,
6-162, 6-177, 6-183 to 6-185, 6-198,
6-203 to 6-204, 6-206 to 6-208, C-4
C status bit 2-5, 6-19 to 6-26, 6-28, 6-33 to 6-34,
6-38 to 6-39, 6-54, 6-69, 6-72 to 6-74,
6-78 to 6-79, 6-81 to 6-86, 6-95 to 6-98,
6-104 to 6-105, 6-109 to 6-110,
6-112 to 6-113, 6-131 to 6-140,
6-142 to 6-143, 6-168, 6-170 to 6-175,
6-179 to 6-182, 6-193 to 6-195
H status bit 2-4, 6-8, 6-11 to 6-14, 6-69
I mask bit 2-4, 6-18, 6-55, 6-183, 6-196, 6-205,
6-213, 7-2, 7-4
Manipulation 5-21, 6-18, 6-54 to 6-55, 6-59,
6-153, 6-182 to 6-184, 6-198, 6-204
N status bit 2-4, 6-41, 6-43, 6-115, 6-117
S control bit 2-3, 6-189
Stacking 6-156, 6-162
V status bit 2-4, 6-50 to 6-51, 6-59,
6-120 to 6-121, 6-166 to 6-169, 6-184
X mask bit 2-3, 6-90, 6-162, 6-177, 6-189, 6-198,
6-203, 6-213, 7-2, 7-4
Z status bit 2-4, 6-29, 6-42, 6-81 to 6-84,
6-100 to 6-101, 6-106, 6-116,
6-139 to 6-140, 6-142 to 6-143
Conditional 16-bit read cycle 6-7
Conditional 8-bit read cycle 6-7
Conditional 8-bit write cycle 6-7
Conserving power 5-21, 6-189
Constant indirect indexed addressing mode 3-7
Constant offset indexed addressing mode
3-6 to 3-7
Conventions 1-3
COP reset 7-3
CPD instruction 6-65
CPS instruction 6-66
CPU wait 6-213
CPX instruction 6-67
CPY instruction 6-68
Cycle code letters 6-5
Cycle counts B-9
CPU12
REFERENCE MANUAL
Cycle-by-cycle operation 6-5
D
DAA instruction 6-69
DATA mnemonic 1-3
Data types 2-5
DBEQ instruction 6-70, A-25
DBNE instruction 6-71, A-25
DEC instruction 6-72
DECA instruction 6-73
DECB instruction 6-74
Decrement instructions 5-4, 6-72 to 6-77
Defuzzification 9-6, 9-22 to 9-24, 9-26, 9-29
DES instruction 6-75
DEX instruction 6-76
DEY instruction 6-77
Direct addressing mode 3-3
Division instructions 5-7
16-bit fractional 6-91
16-bit integer 6-94 to 6-95
32-bit extended 6-78 to 6-79
Divsion instructions C-3
E
EDIV instruction 6-78
EDIVS instruction 6-79
Effective address 3-2, 3-5, 6-128 to 6-130
EMACS instruction 5-11, 6-80, 9-1, 9-29
EMAXD 6-81
EMAXD instruction 6-81
EMAXM instruction 6-82, 9-1
EMIND instruction 6-83, 9-1
EMINM instruction 6-84
EMUL instruction 6-85
EMULS instruction 6-86
Enabling maskable interrupts 2-4
EORA instruction 6-87
EORB instruction 6-88
ETBL instruction 5-12, 6-89, 9-1
Even bytes 2-5
Exceptions 4-3, 7-1
Interrupts 7-3
Maskable interrupts 7-1, 7-4 to 7-5
Non-maskable interrupts 7-1, 7-4
Priority 7-2
Processing flow 7-6
Resets 7-1 to 7-3
Software interrupts 5-18, 6-196, 7-1, 7-6
Unimplemented opcode trap 7-1 to 7-2, 7-5
Vectors 7-1, 7-6
Exchange instructions 5-2, 6-90, 6-215 to 6-216,
B-11, B-13
Postbyte encoding A-24
CPU12
REFERENCE MANUAL
Execution cycles 6-5
Conditional 16-bit read 6-7
Conditional 8-bit read 6-7
Conditional 8-bit write 6-7
Free 6-5
Optional 4-4 to 4-5, 6-6
Program word access 6-6
Read indirect pointer 6-5
Read indirect PPAGE value 6-5
Read PPAGE 6-5
Read 16-bit data 6-6
Read 8-bit data 6-6
Stack 16-bit data 6-6
Stack 8-bit data 6-6
Unstack 16-bit data 6-7
Unstack 8-bit data 6-6
Vector fetch 6-7
Write PPAGE 6-5
Write 16-bit data 6-6
Write 8-bit data 6-6
Execution time 6-5
EXG instruction 6-90
Expanded memory 3-12, 4-3, 10-1, B-16,
C-4 to C-5
Addressing modes 3-12, 10-4 to 10-6
Bank switching 3-12, 10-1, 10-3 to 10-6
Chip-select circuits 10-4
Instructions 3-12, 5-17, 6-52, 6-176, 10-2 to 10-3
Overlay windows 10-1, 10-3 to 10-6
Page registers 3-12, 10-1, 10-4 to 10-6
Registers 10-5 to 10-6
Subroutines 5-17, 10-2, C-4 to C-5
Extended addressing mode 3-3
Extended division 5-7
Extension byte 3-5
External interrupts 7-5
External queue reconstruction 8-1
External reset 7-3
F
Fast math B-9
FDIV instruction 6-91
Fractional division 5-7
Frame pointer C-2 to C-3
Free cycle 6-5
Fuzzy logic 9-1
Antecedants 9-5
Consequents 9-5
Custom programming 9-26
Defuzzification 5-9, 9-6, 9-22 to 9-24, 9-26, 9-29
Fuzzification 5-9, 9-3, 9-26
Inference kernel 5-9, 9-2, 9-7
Inputs 5-9, 9-30
MOTOROLA
I-3
Instructions 5-9, 6-141, 6-166, 6-168, 6-214, 9-1,
9-9, 9-13 to 9-14, 9-17 to 9-19, 9-22, B-14
Interrupts 9-20, 9-23 to 9-24, 9-26
Knowledge base 9-2, 9-5
Membership functions 5-9, 6-141, 9-1 to 9-3,
9-9 to 9-13, 9-26 to 9-27
Outputs 5-9, 9-30
Rule evaluation 5-9, 6-166, 6-168, 9-1, 9-5,
9-13 to 9-15, 9-17 to 9-20, 9-22, 9-29
Rules 9-2, 9-5
Sets 9-2
Tabular membership functions 5-12, 9-26
Weighted average 5-9, 6-214, 9-1, 9-6,
9-22 to 9-24, 9-26
G
General purpose accumulators 2-1
H
H status bit 2-4, 6-8, 6-11 to 6-14, 6-69
High-level language C-1, C-3
Addressing modes C-1, C-3 to C-4
Condition codes register C-4
Expanded memory C-4 to C-5
Instructions C-1
Loop primitives C-3
Stack C-1 to C-2
I
I mask bit 2-4, 6-18, 6-55, 6-183, 6-196, 6-205,
6-213, 7-2
IBEQ instruction 6-92, A-25
IBNE A-25
IBNE instruction 6-93
IDIV instruction 6-94
IDIVS instruction 6-95, C-3
Immediate addressing mode 3-2
INC instruction 6-96
INCA instruction 6-97
INCB instruction 6-98
Increment instructions 5-4, 6-96 to 6-101
Index calculation instructions 5-20, 6-9 to 6-10,
6-76 to 6-77, 6-100 to 6-101, 6-129 to 6-130,
B-11
Index manipulation instructions 5-19, 6-67 to 6-68,
6-90, 6-126 to 6-127, 6-158 to 6-159,
6-164 to 6-165, 6-191 to 6-192, 6-203,
6-209 to 6-212, 6-215 to 6-216
Index registers 2-1 to 2-2, 5-19, C-2
X 3-5, 6-9, 6-67, 6-70 to 6-71, 6-76, 6-90 to 6-95,
6-100, 6-126, 6-128 to 6-130, 6-158, 6-164,
6-166, 6-168, 6-177, 6-185, 6-191, 6-196,
6-200 to 6-203, 6-209, 6-211, 6-215
Y 3-5, 6-10, 6-68, 6-70 to 6-71, 6-77 to 6-80,
MOTOROLA
I-4
6-85 to 6-86, 6-90, 6-92 to 6-93, 6-101,
6-127 to 6-130, 6-159, 6-165 to 6-166,
6-168, 6-177, 6-185, 6-192, 6-196,
6-200 to 6-203, 6-210, 6-212, 6-216
Indexed addressing modes 2-2, 3-5, A-22,
B-6 to B-9
Accumulator direct 3-9
Accumulator offset 3-9
Automatic indexing 3-8
Base index register 3-6, 3-10
Extension byte 3-5
Postbyte 3-5
Postbyte encoding 3-5, A-22
16-bit constant indirect 3-7
16-bit constant offset 3-7
5-bit constant offset 3-6
9-bit constant offset 3-7
Inference kernel, fuzzy logic 9-7
Inherent addressing mode 3-2
INS instruction 6-99
Instruction queue 1-1, 2-5, 4-1, 8-1, B-4
Alignment 4-1
Buffer 4-1
Debugging 8-1
Movement cycles 4-2
Reconstruction 8-1, 8-3, 8-5
Stages 4-1, 8-1
Status registers 8-4 to 8-5
Status signals 4-1, 8-1 to 8-3, 8-5 to 8-6
Instruction set A-2
Integer division 5-7
Interrupt instructions 5-18
Interrupts 7-3
Enabling and disabling 2-3 to 2-4, 6-55, 6-183,
7-2
External 7-5
I mask bit 2-4, 6-55, 6-183, 6-196, 6-213, 7-4
Instructions 5-18, 6-55, 6-177, 6-183, 6-196,
6-205
Low-power stop 5-21, 6-189
Maskable 2-4, 7-4
Non-maskable 2-3, 7-2, 7-4
Recognition 7-4
Return 2-4, 5-18, 6-177, 7-5
Service routines 7-4
Software 5-18, 6-196, 7-1, 7-6
Stacking 7-4
Vectors 7-3
Wait instruction 5-21, 6-213
X mask bit 2-3, 6-189, 6-213, 7-4
INX instruction 6-100
INY instruction 6-101
CPU12
REFERENCE MANUAL
J
JMP instruction 4-5, 6-102
JSR instruction 4-3, 6-103
Jump instructions 5-17
Jumps 4-5
K
Knowledge base 9-2
L
LBCC instruction 6-104
LBCS instruction 6-105
LBEQ instruction 6-106
LBGE instruction 6-107
LBGT instruction 6-108
LBHI instruction 6-109
LBHS instruction 6-110
LBLE instruction 6-111
LBLO instruction 6-112
LBLS instruction 6-113
LBLT instruction 6-114
LBMI instruction 6-115
LBNE instruction 6-116
LBPL instruction 6-117
LBRA instruction 6-118
LBRN instruction 6-119
LBVC instruction 6-120
LBVS instruction 6-121
LDAA instruction 6-122
LDAB instruction 6-123
LDD instruction 6-124
LDS instruction 6-125
LDX instruction 6-126
LDY instruction 6-127
LEAS instruction 6-128, C-2, C-4
Least signficant byte 1-3
Least significant word 1-3
LEAX instruction 6-129, C-4
LEAY instruction 6-130, C-4
Legal label 6-3
Literal expression 6-3
Load instructions 5-1, 6-122 to 6-130
Logic level one 1-3
Logic level zero 1-3
Loop primitive instructions 4-5, 6-70 to 6-71,
6-92 to 6-93, 6-200, 6-202, A-25, B-13, C-3
Offset values 5-16
Postbyte encoding A-25
Low-power stop 5-21, 6-189
LSL instruction 6-131
LSL mnemonics 5-8
LSLA instruction 6-132
LSLB instruction 6-133
CPU12
REFERENCE MANUAL
LSLD instruction 6-134
LSR instruction 6-135
LSRA instruction 6-136
LSRB instruction 6-137
LSRD instruction 6-138
M
Maskable interrupts 7-1, 7-4
MAXA instruction 6-139
Maximum instructions 5-11, B-14
16-bit 6-81 to 6-82
8-bit 6-139 to 6-140
MAXM instruction 6-140, 9-1
MEM instruction 5-9, 6-141, 9-1, 9-9 to 9-13
Membership functions 9-2
Memory and addressing symbols 1-2
Memory expansion
Addressing 10-7
Bank switching 10-7
Overlay windows 10-7
Page registers 10-3, 10-7
MINA instruction 6-142, 9-1
Minimum instructions 5-11, B-14
16-bit 6-83 to 6-84
8-bit 6-142 to 6-143
MINM instruction 6-143
Misaligned instructions 4-4 to 4-5
Mnemonic 1-3
Mnemonic ranges 1-3
Most significant byte 1-3
Most significant word 1-3
MOVB instruction 6-144
Move instructions 5-3, 6-144 to 6-145, B-10, B-13
Destination 3-10
Multiple addressing modes 3-10
PC relative addressing 3-10
Reference index register 3-10
Source 3-10
MOVW instruction 6-145
MUL instruction 6-146
Multiple addressing modes
Bit manipulation instructions 3-11, 6-27, 6-48
Move instructions 3-10, 6-144 to 6-145
Multiplication instructions 5-7
16-bit 6-85 to 6-86
8-bit 6-146
Multiply and accumulate instructions 5-11, 6-80,
6-214
M68HC11 compatibility 3-2, B-1
M68HC11 instruction mnemonics B-1
N
N status bit 2-4, 6-41, 6-43, 6-115, 6-117
MOTOROLA
I-5
NEG instruction 6-147
NEGA instruction 6-148
Negate instructions 5-6, 6-147 to 6-149
Negated 1-3
Negative integers 2-5
NEGB instruction 6-149
Non-maskable interrupts 7-1 to 7-2, 7-4
NOP instruction 5-22, 6-150
Notation
Branch taken/not taken 6-7
Changes in CCR bits 6-2
Cycle-by-cycle operation 6-5
Memory and addressing 1-2
Object code 6-2
Operators 1-3
Source forms 6-3
System resources 1-2
Null operation instruction 5-22, 6-150
Numeric range of branch offsets 3-4
O
Object code notation 6-2
Odd bytes 2-5
Opcodes B-2, B-9
Map A-20
Operators 1-3
Optional cycles 4-4 to 4-5, 6-6
ORAA instruction 6-151
ORAB instruction 6-152
ORCC instruction 6-153
Orthogonality C-5
P
Pointer calculation instructions 5-20,
6-128 to 6-130
Pointers C-4
Postbyte 3-5, 6-90, 6-185, 6-203
Postbyte encoding
Exchange instructions A-24
Indexed addressing modes A-22
Loop primitive instruction A-25
Transfer instructions A-24
Post-decrement indexed addressing mode 3-8
Post-increment indexed addressing mode 3-8
Power conservation 5-21, 6-189, 6-213
Power-on reset 7-3
Pre-decrement indexed addressing mode 3-8
Pre-increment indexed addressing mode 3-8
Priority, exception 7-2
Program counter 2-1 to 2-2, 3-5, 6-31, 6-49, 6-52,
6-103, 6-128 to 6-130, 6-144 to 6-145, 6-150,
6-177 to 6-178, 6-196, 6-201, 6-205
Program word access cycle 6-6
Programming model 1-1, 2-1, B-3
MOTOROLA
I-6
Pseudo-non-maskable interrupt 7-2
PSHA instruction 6-154
PSHB instruction 6-155
PSHC instruction 6-156
PSHD instruction 6-157
PSHX instruction 6-158
PSHY instruction 6-159
PULA instruction 6-160
PULB instruction 6-161
PULC instruction 6-162
PULD instruction 6-163, C-2
Pull instructions C-5
PULX instruction 6-164
PULY instruction 6-165
Push instructions C-5
PUSHD instruction C-2
R
Range of mnemonics 1-3
Read indirect PPAGE cycle 6-5
Read PPAGE cycle 6-5
Read 8-bit data cycle 6-6
Read16-bit data cycle 6-6
Register designators 6-3
Relative addressing mode 3-4
Relative offset 3-4
Resets 7-1 to 7-2
Clock monitor 7-3
COP 7-3
External 7-3
Power-on 7-3
REV instruction 5-9, 6-166, 9-1, 9-5, 9-13 to 9-15,
9-17 to 9-20, 9-22, 9-29
REVW instruction 5-9, 6-168, 9-1, 9-5,
9-13 to 9-15, 9-17 to 9-20, 9-22, 9-29
ROL instruction 6-170
ROLA instruction 6-171
ROLB instruction 6-172
ROM, BDM 8-6
ROR instruction 6-173
RORA instruction 6-174
RORB instruction 6-175
Rotate instructions 5-8, 6-170 to 6-175
RTC instruction 3-12, 4-3, 5-17, 6-176,
10-2 to 10-3, B-16, C-4 to C-5
RTI instruction 2-4, 5-18, 6-177, 7-5
RTS instruction 4-3, 6-178
S
S control bit 2-3, 6-189
SBA instruction 6-179
SBCA instruction 6-180
SBCB instruction 6-181
SEC instruction 6-182
CPU12
REFERENCE MANUAL
SEI instruction 6-183
Set 1-3
Setting memory bits 6-48
SEV instruction 6-184
SEX instruction 5-2, 6-185
Shift instructions 5-8
Arithmetic 6-19 to 6-25
Logical 6-131 to 6-138
Sign extension instruction 6-185
Signed branches 5-13
Signed integers 2-5
Signed multiplication 5-7
Sign-extension instruction 5-2, C-1
Simple branches 5-13
Software interrupts 6-196, 7-1
Source code compatibility 1-1, B-1
Source form notation 6-3
Specific mnemonic 1-3
STAA instruction 6-186
STAB instruction 6-187
Stack 2-2, B-5 to B-6
Interrupts 6-177, 6-196
Stop and wait 6-189, 6-213
Subroutines 6-49, 6-52, 6-103, 6-176, 6-178
Traps 6-205
Stack operation instructions 5-20, 6-154 to 6-165
Stack pointer 2-1 to 2-2, 3-5, 6-49, 6-52, 6-66,
6-70 to 6-71, 6-75, 6-90, 6-92 to 6-93, 6-99,
6-103, 6-125, 6-128 to 6-130, 6-155 to 6-165,
6-178, 6-185, 6-190, 6-200 to 6-203,
6-209 to 6-212, C-1
Initialization 2-2
Manipulation 5-20, 6-66, 6-75, 6-99, 6-125,
6-128, 6-154 to 6-155, 6-190, 6-209 to 6-212
Stacking order 2-2, B-5
Stack pointer instructions 5-20, 6-66, 6-75, 6-99,
6-125, 6-128, 6-190, 6-203, 6-209 to 6-212,
B-15, C-1
Stack 16-bit data cycle 6-6
Stack 8-bit data cycle 6-6
Stacking instructions 6-154 to 6-155
Standard CPU12 address space 2-5
STD instruction 6-188
STOP instruction 2-3, 5-21, 6-189
Store instructions 5-1, 6-186 to 6-188,
6-190 to 6-192
STS instruction 6-190
STX instruction 6-191
STY instruction 6-192
SUBA instruction 6-193
SUBB instruction 6-194
SUBD instruction 6-195
Subroutine instructions 5-17
CPU12
REFERENCE MANUAL
Subroutines 4-3, 6-103, C-4 to C-5
Expanded memory 4-3, 5-17, 6-52, 6-176
Instructions 5-17, 6-49, 6-103, C-4 to C-5
Return 6-176, 6-178
Subtraction instructions 5-3, 6-179 to 6-181,
6-193 to 6-195
SWI instruction 5-18, 6-196, 7-6
Switch statements C-4
Symbols and notation 1-2
T
TAB instruction 6-197
Table interpolation instructions 5-12, 6-89, 6-201,
B-15
Tabular membership functions 9-26 to 9-27
TAP instruction 6-198
TBA instruction 6-199
TBEQ instruction 6-200, A-25
TBL instruction 5-12, 6-201, 9-1, 9-26 to 9-27
TBNE instruction 6-202, A-25
Termination of interrupt service routines 5-18,
6-177, 7-5
Termination of subroutines 6-176, 6-178
Test instructions 5-5, 6-35 to 6-36, 6-200, 6-202,
6-206 to 6-208
TFR instruction 6-185, 6-198, 6-203 to 6-204,
6-209 to 6-212
TPA instruction 6-204
Transfer and exchange instructions C-1
Transfer instructions 5-2, 6-197 to 6-199,
6-203 to 6-204, 6-209 to 6-212, B-11, B-13
Postbyte encoding A-24
TRAP instruction 5-18, 6-205, 7-5
TST 6-206
TST instruction 6-206
TSTA instruction 6-207
TSTB instruction 6-208
TSX instruction 6-209
TSY instruction 6-210
Twos-complement form 2-5
TXS instruction 6-211
Types of instructions
Addition and Subtraction 5-3
Background and null 5-22
Binary-coded decimal 5-4
Bit test and manipulation 5-7
Boolean logic 5-6
Branch 5-13
Clear, complement, and negate 5-6
Compare and test 5-5
Condition code 5-21
Decrement and increment 5-4
Fuzzy logic 5-9
MOTOROLA
I-7
Index manipulation 5-19
Interrupt 5-18
Jump and subroutine 5-17
Load and store 5-1
Loop primitives 5-16
Maximum and minimum 5-11
Move 5-3
Multiplication and division 5-7
Multiply and accumulate 5-11
Pointer and index calculation 5-20
Shift and rotate 5-8
Sign extension 5-2
Stacking 5-20
Stop and wait 5-21
Table interpolation 5-12
Transfer and exchange 5-2
TYS instruction 6-212
Z
Z status bit 2-4, 6-29, 6-42, 6-81 to 6-84,
6-100 to 6-101, 6-106, 6-116, 6-139 to 6-140,
6-142 to 6-143
Zero-page addressing 3-3
U
Unary branches 5-13
Unimplemented opcode trap 5-18, 6-205,
7-1 to 7-2
Unsigned branches 5-13
Unsigned multiplication 5-7
Unstack 16-bit data cycle 6-7
Unstack 8-bit data cycle 6-6
Unweighted rule evaluation 6-166, 9-5,
9-13 to 9-15, 9-17 to 9-20, 9-22, 9-29
V
V status bit 2-4, 6-50 to 6-51, 6-59, 6-120 to 6-121,
6-166 to 6-169, 6-184
Vector fetch cycle 6-7
Vectors, exception 7-1, 7-6
W
WAI instruction 5-21, 6-213
WAV instruction 5-9, 5-11, 6-214, 9-1, 9-6,
9-22 to 9-24, 9-26, 9-29
Wavr pseudoinstruction 9-23 to 9-24, 9-26
Weighted average 6-214
Weighted rule evaluation 6-168, 9-5, 9-13 to 9-15,
9-17 to 9-20, 9-22, 9-29
Word moves 6-145
Write PPAGE cycle 6-5
Write 16-bit data cycle 6-6
Write 8-bit data cycle 6-6
X
X mask bit 2-3, 6-90, 6-162, 6-177, 6-189, 6-198,
6-203, 6-213
XGDX instruction 6-215
XGDY instruction 6-216
MOTOROLA
I-8
CPU12
REFERENCE MANUAL
SUMMARY OF CHANGES
This is a complete revision and reprint. All known errors in the publication have been
corrected. The following summary lists significant changes.
Page
Change
3-6
Additional information provided in Table 3-2.
3-9
Changed paragraph 3.8.6 to indicate accumulator offset is an unsigned value.
4-5
Changed paragraph 4.3.3.4 to show that both taken and not taken cases for loop primitives
use the same number of P cycles.
5-18
Table 5-22, operation sequence of RTI instruction modified to match sequence in Sec. 6.
6-3 and 6-4
Removed spurious letter “e” from “opr” source forms.
6-11 to 6-14
Added overbars to terms in Boolean formulae for ADCA, ADCB, ADDA, and ADDB.
6-27
Modified V bit description of condition code register.
6-70, 6-71, 6-92, 6-93, Corrected access details for loop primitives to show that taken and not taken cases both
6-200 and 6-202
use three P cycles.
6-78, 6-79, 6-94
Correction in descriptions for EDIV, EDIVS, and IDIV: “dividend” is divided by “divisor.”
6-78
Comment removed in EDIV description regarding C status bit.
6-81, 6-82, 6-83, 6-84, In condition code C bit description of EMAXD, EMAXM, EMIND, EMINM, MAXA, MAXM,
6-139, 6-140, 6-142, MINA, MINM, SUBA, SUBB and SUBD, two occurrences of the word “absolute” have been
6-143, 6-193, 6-194, removed.
6-195
6-148
Overbar added to term in NEGA operation description.
6-167
Corrected access detail for REV instruction.
6-177
Corrected operation sequence for RTI instruction.
6-189
Corrected operation sequence for STOP instruction. Also, fourth paragraph of description
modified so as to not indicate that SP is changed.
6-196
Condition code register corrected; status bit I is set (1) following the SWI instruction.
6-213
Corrected operation sequence for WAI instruction.
6-214
Corrected access detail for WAV instruction.
8-7
Section 8.4.2, second paragraph, time-out of 256 E clock cycles is changed to 512 E clock
cycles. Fourth paragraph, “Nine target E-cycles later,” is now “Ten target E-cycles later.”
8-8
Figure 8-2, nine cycle reference is changed to ten cycles; art is modified accordingly.
8-10
Table 8-2, command order changed, footnote explanations added, ENTER_TAG_MODE
command deleted.
8-12
Section 8.4.4.1, reset conditions for STATUS register corrected. ITF bit name is changed
to ENTAG, Instruction Tagging Enable.
9-16 and 9-21
Corrected flow arrow and font substitution errors in Figures 9-9 and 9-10.
9-24
Changed paragraph 9.6.3. to reflect a three-cycle delay rather than a four-cycle delay.
9-25
Corrected flow arrow error and removed cycle 10.1 Figure 9-11.
9-28
Figure 9-12, Corrected inappropriate line break in code.
B-10
Table B-3, last row (EMACS) math operation corrected and two occurrences of
“per iteration” removed.
B-13
Section B.7.2, first sentence, “six transfer instructions” is now “eight transfer instructions.”
General
Minor grammatical and typographic corrections to improve consistency and presentation.
New index markers.
CPU12
REFERENCE MANUAL
SUMMARY OF CHANGES
MOTOROLA
S-1
MOTOROLA
S-2
SUMMARY OF CHANGES
CPU12
REFERENCE MANUAL
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including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts.
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CPU12RM/AD