19-0734; Rev 0; 1/07 KIT ATION EVALU E L B AVAILA 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators Features The MAX15014–MAX15017 combine a step-down DCDC converter and a 50mA, low-quiescent-current lowdropout (LDO) regulator. The LDO regulator is ideal for powering always-on circuitry in automotive applications. The DC-DC converter input voltage range is 4.5V to 40V for the MAX15015/MAX15016, and 7.5V to 40V for the MAX15014/MAX15017. Combined DC-DC Converters and Low-QuiescentCurrent LDO Regulators 1A DC-DC Converters Operate from 4.5V to 40V (MAX15015/MAX15016) or 7.5V to 40V (MAX15014/MAX15017) Switching Frequency of 135kHz (MAX15014/MAX15016) or 500kHz (MAX15015/MAX15017) 50mA LDO Regulator Operates from 5V to 40V Independent of the DC-DC Converter 47µA Quiescent Current with DC-DC Converter Off and LDO On 6µA System Shutdown Current Frequency Synchronization Input Shutdown/Enable Inputs Adjustable Soft-Start Time Active-Low Open-Drain RESET Output with Programmable Timeout Delay Thermal Shutdown and Output Short-Circuit Protection Space-Saving (6mm x 6mm) Thermally Enhanced 36-Pin TQFN Package The DC-DC converter output is adjustable from 1.26V to 32V and can deliver up to 1A of load current. These devices utilize a feed-forward voltage-mode control scheme for good noise immunity in the high-voltage switching environment and offer external compensation allowing for maximum flexibility with a wide selection of inductor values and capacitor types. The switching frequency is internally fixed at 135kHz and 500kHz, depending on the version chosen. Moreover, the switching frequency can be synchronized to an external clock signal through the SYNC input. Light load efficiency is improved by automatically switching to a pulse-skip mode. The soft-start time is adjustable with an external capacitor. The DC-DC converter can be disabled independent of the LDO, thus reducing the quiescent current to 47µA (typ). The LDO linear regulators operate from 5V to 40V and deliver a guaranteed 50mA load current. The devices feature a preset output voltage of 5V (MAX1501_A) or 3.3V (MAX1501_B). Alternatively, the output voltage can be adjusted from 1.5V to 11V by using an external resistive divider. The LDO section also features a RESET output with adjustable timeout period. Protection features include cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown. All devices are available in a space-saving, high-power (2.86W), 36-pin TQFN package and are rated for operation over the -40°C to +125°C automotive temperature range. Ordering Information PART TEMP RANGE PINPACKAGE PKG CODE MAX15014AATX+ -40°C to +125°C 36 TQFN-EP* T3666-3 MAX15014BATX+ -40°C to +125°C 36 TQFN-EP* T3666-3 MAX15015AATX+ -40°C to +125°C 36 TQFN-EP* T3666-3 MAX15015BATX+ -40°C to +125°C 36 TQFN-EP* T3666-3 MAX15016AATX+ -40°C to +125°C 36 TQFN-EP* T3666-3 -40°C to +125°C 36 TQFN-EP* T3666-3 MAX15017AATX+ -40°C to +125°C 36 TQFN-EP* T3666-3 Car Radios MAX15017BATX+ T3666-3 Automotive Body Control Modules +Denotes a lead-free package. *EP = Exposed pad. Applications Automotive Instrument Cluster MAX15016BATX+ -40°C to +125°C 36 TQFN-EP* Navigation Systems ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX15014–MAX15017 General Description MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators ABSOLUTE MAXIMUM RATINGS LDO_OUT Output Current.................................Internally Limited Switch DC Current (DRAIN and LX pins combined) TJ = +125°C.......................................................................1.9A TJ = +150°C.....................................................................1.25A RESET Sink Current ..............................................................5mA Continuous Power Dissipation (TA = +70°C) 36-Pin TQFN (derate 26.3mW/°C above +70°C) Single-Layer Board .....................................................2105mW 36-Pin TQFN (derate 35.7mW/°C above +70°C) Multilayer Board ..........................................................2857mW Operating Temperature Range .........................-40°C to +125°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range ............................-60°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C IN_SW, IN_LDO, DRAIN, EN_SYS, EN_SW to SGND ..............................................................-0.3V to +45V IN_LDO to IN_SW ..................................................-0.3V to +0.3V LX to SGND ...........................................-0.3V to (VIN_SW + 0.3V) LX to PGND ...........................................-0.3V to (VIN_SW + 0.3V) BST to SGND ..........................................-0.3V to (VIN_SW + 12V) BST to LX................................................................-0.3V to +12V PGND to SGND .....................................................-0.3V to +0.3V REG, DVREG, SYNC, RESET, CT to SGND............-0.3V to +12V FB, COMP_SW, SS to SGND....................-0.3V to (VREG + 0.3V) SET_LDO, LDO_OUT to SGND ..............................-0.3V to +12V C+ to PGND (MAX15015/MAX15016 only)................(VDVREG - 0.3V) to 12V C- to PGND (MAX15015/MAX15016 only) ............-0.3V to (VDVREG + 0.3V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1µF, CIN_SW = 0.1µF, CIN_LDO = 0.1µF, CLDO_OUT = 10µF, CDRAIN = 0.22µF, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER System Supply Current (Not Switching) Switching System Supply Current LDO Quiescent Current System Shutdown Current System Enable Voltage SYMBOL CONDITIONS MIN VFB = 1.3V, MAX15014/MAX15017 ISYS ISW ILDO ISHDN MAX 0.7 1.8 VFB = 1.3V, MAX15015/MAX15016 0.85 VFB = 0V, MAX15014/MAX15017 5.6 VFB = 0V, MAX15015/MAX15016 8.6 ILDO_OUT = 100µA 47 63 ILDO_OUT = 50mA 130 200 6 10 1.8 mA No load VEN_SYS = 14V, VEN_SW = 0V VEN_SYS = 0V, VEN_SW = 0V VEN_SYSH EN_SYS = high, system on VEN_SYSL EN_SYS = low, system off 2.4 0.8 220 IEN_SYS UNITS mA No load System Enable Hysteresis System Enable Input Current TYP µA µA V mV VEN_SYS = 2.4V 0.5 2 VEN_SYS = 14V 0.6 2 µA BUCK CONVERTER Input Voltage Range 2 VIN_SW MAX15014/MAX15017 7.5 40.0 MAX15015/MAX15016 4.5 40.0 _______________________________________________________________________________________ V 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators (VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1µF, CIN_SW = 0.1µF, CIN_LDO = 0.1µF, CLDO_OUT = 10µF, CDRAIN = 0.22µF, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Undervoltage Lockout Threshold SYMBOL UVLOTH Undervoltage Lockout Hysteresis UVLOHYST Output Voltage Range VOUT Output Current MIN TYP MAX VIN_SW and IN_LDO rising, MAX15014/MAX15017 CONDITIONS 6.7 7.0 7.4 VIN_SW and IN_LDO rising, MAX15015/MAX15016 3.90 4.08 4.25 V MAX15014/MAX15017 0.54 MAX15015/MAX15016 0.3 Minimum output 1.26 Maximum output 32 IOUT EN_SW Input Voltage Threshold V V 1 VEN_SWH EN_SW = high, switching power supply is on VEN_SWL EN_SW = low, switching power supply is off A 2.4 0.8 EN_SW Hysteresis 220 Switching Enable Input Current IEN_SW UNITS V mV VEN_SW = 2.4V 0.5 2 VEN_SW = 14V 0.6 2 µA INTERNAL VOLTAGE REGULATOR Output Voltage VREG Line Regulation MAX15014/MAX15017, VIN_SW = 9V to 40V 7.6 8.4 MAX15015/MAX15016, VIN_SW = 5.5V to 40V 4.75 5.25 VIN_SW = 9.0V to 40V, MAX15014/MAX15017 1 VIN_SW = 5.5V to 40V, MAX15015/MAX15016 1 V mV/V Load Regulation IREG = 0 to 20mA 0.25 V Dropout Voltage VIN_SW = 7.5V (MAX15014/MAX15017), VIN_SW = 4.5V (MAX15015/MAX15016), IREG = 20mA 0.5 V OSCILLATOR Frequency Range fCLK Maximum Duty Cycle Minimum LX Low Time SYNC High-Level Voltage SYNC Low-Level Voltage DMAX VSYNC = 0V, MAX15014/MAX15016 122 136 150 VSYNC = 0V, MAX15015/MAX15017 425 500 575 VSYNC = 0V, VIN_SW = 7.5V, MAX15014 (135kHz) 90 98 VSYNC = 0V, VIN_SW = 4.5V, MAX15016 (135kHz) 90 98 kHz % VSYNC = 0V, VIN_SW = 4.5V, MAX15015 (500kHz) 90 96 VSYNC = 0V, VIN_SW = 7.5V, MAX15017 (500kHz) 90 98 VSYNC = 0V 94 ns 2.2 0.8 V _______________________________________________________________________________________ 3 MAX15014–MAX15017 ELECTRICAL CHARACTERISTICS (continued) MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators ELECTRICAL CHARACTERISTICS (continued) (VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1µF, CIN_SW = 0.1µF, CIN_LDO = 0.1µF, CLDO_OUT = 10µF, CDRAIN = 0.22µF, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYNC Frequency Range SYMBOL fSYNC CONDITIONS MIN TYP MAX MAX15014/MAX15016 100 200 MAX15015/MAX15017 400 600 Ramp Level Shift (Valley) 0.3 UNITS kHz V ERROR AMPLIFER Soft-Start Reference Voltage VSS 1.210 1.260 V µA Soft-Start Current ISS 7 12 17 FB Regulation Voltage VFB 1.210 1.235 1.260 V FB Input Range VFB 0 1.5 V FB Input Current IFB VFB = 1.244V -250 +250 nA ICOMP = -500µA to +500µA 0.25 4.5 COMP Voltage Range VSS = 0V 1.235 Open-Loop Gain Unity-Gain Bandwidth PWM Modulator Gain V 80 dB 1.8 MHz fSYNC = 500kHz, MAX15015/MAX15017 10 fSYNC = 135kHz, MAX15014/MAX15016 10 V/V CURRENT-LIMIT COMPARATOR Pulse Skip Threshold IPFM 100 200 300 mA Cycle-by-Cycle Current Limit IILIM 1.3 2 2.6 A Number of Consecutive ILIM Events to Hiccup Hiccup Timeout 7 — 512 Clock periods POWER SWITCH Switch On-Resistance VBST - VLX = 6V Switch Gate Charge VBST - VLX = 6V Switch Leakage Current VIN_SW = VIN_LDO = VLX = VDRAIN = 40V, VFB = 0V BST Quiescent Current VBST = 40V, VDRAIN = 40V, VFB = 0V, DVREG = 5V BST Leakage Current VBST = VDRAIN = VLX = VIN_SW = VIN_LDO = 40V, EN_SW = 0V 0.15 0.4 0.80 4 400 Ω nC 10 µA 600 µA 1 µA CHARGE PUMP (MAX15015/MAX15016) C- Output Voltage Low Sinking 10mA 0.1 V C- Output Voltage High Relative to DVREG, sourcing 10mA 0.1 V DVREG to C+ On-Resistance Sourcing 10mA 10 Ω LX to PGND On-Resistance Sinking 10mA 12 Ω 40 V 4.25 V LDO Input Voltage Range VIN_LDO Undervoltage Lockout Threshold UVLO_LDOTH Undervoltage Lockout Hysteresis UVLO_LDOHYST 4 5 VIN_LDO rising 3.90 4.1 0.3 _______________________________________________________________________________________ V 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators (VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1µF, CIN_SW = 0.1µF, CIN_LDO = 0.1µF, CLDO_OUT = 10µF, CDRAIN = 0.22µF, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Output Current SYMBOL IOUT CONDITIONS VIN = 6V (Note 2) SET_LDO = SGND, MAX1501_A Output Voltage VLDO_OUT SET_LDO = SGND, MAX1501_B Adjustable Output Voltage Range VADJ ∆VDO Dropout Voltage SET_LDO Input Leakage Current Power-Supply Rejection Ratio Short-Circuit Current ISET_LDO PSRR ISC UNITS 200 mA 4.90 5 5.06 ILDO_OUT = 1mA 4.90 5 5.06 6V ≤ VIN_LDO ≤ 40V, ILDO_OUT = 1mA 4.85 5 5.15 1mA ≤ IOUT ≤ 50mA, VIN_LDO = 14V 4.85 5 5.15 ILDO_OUT = 100µA 3.22 3.3 3.35 ILDO_OUT = 1mA 3.22 3.3 3.35 6V ≤ VIN_LDO ≤ 40V, ILDO_OUT = 1mA 3.2 3.3 3.4 1mA ≤ ILDO_OUT ≤ 50mA, VIN_LDO = 14V 3.2 3.3 3.4 1.5 11.0 IOUT = 10mA 0.6 IOUT = 50mA 0.82 IOUT = 10mA 0.1 IOUT = 50mA 0.4 VSET_LDO Minimum SET_LDO Threshold MAX ILDO_OUT = 100µA From EN_SYS high to LDO_OUT rise, RL = 500Ω, SET_LDO = SGND Startup Response Time SET_LDO Reference Voltage VIN_LDO = 4.0V, MAX1501_B TYP 65 VSET_LDO > 0.25V VIN_LDO = 5V, MAX1501_A MIN 400 1.220 1.241 (Note 3) 185 VSET_LDO = 11V 0.5 IOUT = 10mA, f = 100Hz, 500mVP-P, VLDO_OUT = 5V 78 IOUT = 10mA, f = 1MHz, 500mVP-P, VLDO_OUT = 5V 24 V V V µs 1.265 V mV 100 nA dB 125 185 300 mA _______________________________________________________________________________________ 5 MAX15014–MAX15017 ELECTRICAL CHARACTERISTICS (continued) MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators ELECTRICAL CHARACTERISTICS (continued) (VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1µF, CIN_SW = 0.1µF, CIN_LDO = 0.1µF, CLDO_OUT = 10µF, CDRAIN = 0.22µF, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 90 92.5 95 %VOUT 0.4 V 1 µA RESET OUTPUT RESET Threshold V RESET RESET goes high after rising VLDO_OUT crosses this threshold RESET Output Low Voltage VRL (VLDO_OUT – V RESET) / IRESET = 4kΩ RESET Output High Leakage Current IRH V RESET = 3.3V (For MAX15_ _ _B), V RESET = 5V (For MAX15_ _ _A) RESET Output Minimum Timeout Period When LDO_OUT reaches RESET threshold, CT = unconnected 50 µs ENABLE to RESET Minimum Timeout Period When EN_SYS goes high, CLDO_OUT = 10µF, ILDO_OUT = 50mA, VLDO_OUT = 3.3V, CT = unconnected 650 µs Delay Comparator Threshold (Rising) VCT-TH Delay Comparator Threshold Hysteresis VCTTH- CT Charge Current ICT-CHQ CT Discharge Current ICT-DIS 1.220 1.241 1.265 100 HYST VCT = 0V 1.5 2 V mV 3 µA 18 mA +160 °C 20 °C THERMAL SHUTDOWN Thermal Shutdown Temperature Thermal Shutdown Hysteresis Temperature rising Note 1: Limits at -40°C are guaranteed by design and not production tested. Note 2: Maximum output current is limited by package power dissipation. Note 3: This is the minimum voltage needed at SET_LDO for the system to recognize that the user wants an adjustable LDO_OUT. 6 _______________________________________________________________________________________ 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014–MAX15017 Typical Operating Characteristics (VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1µF, CIN_SW = 0.1µF, CIN_LDO = 0.1µF, CLDO_OUT = 10µF, CDRAIN = 0.22µF, see Figures 6 and 7, TA = +25°C, unless otherwise noted.) 6 5 4 3 2 MAX15016A 139 1 138 137 136 135 134 133 132 0 50 100 TEMPERATURE (°C) 150 96 95 94 93 ERROR AMPLIFIER OPEN-LOOP GAIN AND PHASE vs. FREQUENCY 98 96 92 90 88 86 84 91 82 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 0 40 340 5 10 15 20 25 30 35 40 70 60 50 40 30 260 220 180 140 PHASE 100 60 0.1 INPUT VOLTAGE (V) OUTPUT CURRENT LIMIT vs. INPUT VOLTAGE 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) TURN-ON/-OFF WAVEFORM TURN-ON/-OFF WAVEFORM MAX15014 toc09 MAX15014 toc08 MAX15014 toc07 2.5 TA = 0°C TA = +25°C 2.0 ILOAD = 1A ILOAD = 100mA EN_SW 2V/div 0V 1.5 TA = +85°C 1.0 300 GAIN 20 10 0 -10 80 90 MAX15014 toc06 110 100 90 80 94 92 470 MAXIMUM DUTY CYCLE vs. INPUT VOLTAGE (MAX15015A) GAIN (dB) 97 480 -60 -40 -20 0 20 40 60 80 100 120 140 160 TEMPERATURE (°C) MAX15014 toc05 98 490 450 100 MAXIMUM DUTY CYCLE (%) MAX15014 toc04 99 500 -60 -40 -20 0 20 40 60 80 100 120 140 160 TEMPERATURE (°C) MAXIMUM DUTY CYCLE vs. INPUT VOLTAGE (MAX15016A) 100 510 460 130 -50 MAXIMUM DUTY CYCLE (%) MAX15015A 520 131 0 OUTPUT CURRENT LIMIT (A) 530 EN_SW 2V/div 0V TA = +135°C VOUT 2V/div VOUT 2V/div 0.5 0V 0V 0 0 10 20 30 INPUT VOLTAGE (V) 40 50 PHASE (DEGREES) 7 140 SWITCHING FREQUENCY (kHz) 8 SWITCHING FREQUENCY vs. TEMPERATURE MAX15014 toc02 MAX15016 9 SWITCHING FREQUENCY (kHz) MAX15014 toc01 SYSTEM SHUTDOWN CURRENT (µA) 10 SWITCHING FREQUENCY vs. TEMPERATURE MAX15014 toc03 SYSTEM SHUTDOWN CURRENT vs. TEMPERATURE 2ms/div 2ms/div _______________________________________________________________________________________ 7 Typical Operating Characteristics (continued) (VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1µF, CIN_SW = 0.1µF, CIN_LDO = 0.1µF, CLDO_OUT = 10µF, CDRAIN = 0.22µF, see Figures 6 and 7, TA = +25°C, unless otherwise noted.) TURN-ON/-OFF WAVEFORM INCREASING VIN TURN-ON/-OFF WAVEFORM INCREASING VIN OUTPUT VOLTAGE vs. TEMPERATURE MAX15014 toc11 MAX15014 toc10 ILOAD = 100mA 3.38 0V VOUT 2V/div VOUT 2V/div 3.36 OUTPUT VOLTAGE (V) VIN 5V/div VIN 5V/div 0V 3.34 3.32 ILOAD = 0A 3.30 3.28 3.26 3.24 0V 0V MAX15014 toc12 3.40 ILOAD = 1A ILOAD = 1A 3.22 3.20 10ms/div EFFICIENCY vs. LOAD CURRENT EFFICIENCY vs. LOAD CURRENT (MAX15015A) VIN = 4.5V 80 VIN = 12V 50 VIN = 24V 40 VIN = 40V 30 VIN = 7.5V VIN = 4.5V 80 MAX15016A ILDO_OUT = 0A 0 100 10 100 LOAD CURRENT (mA) VIN = 12V 60 50 VIN = 24V 40 VIN = 24V 60 50 VIN = 12V 40 VIN = 40V 30 VIN = 40V 20 20 10 10 0 1000 1 100 10 1000 1 LOAD CURRENT (mA) 10 100 LOAD CURRENT (mA) MAX15014 toc16 90 VIN = 7.5V 80 MAX15014 toc18 VIN = 4.5V, IOUT = 0.25A TO 1A MAX15015A VIN = 12V, IOUT = 0.25A TO 1A MAX15015A VOUT AC-COUPLED 100mV/div VOUT AC-COUPLED 100mV/div 70 VIN = 24V 60 50 VIN = 12V 40 30 ILOAD 500mA/div VIN = 40V ILOAD 500mA/div 20 0 10 0 0 1 8 1000 LOAD-TRANSIENT RESPONSE LOAD-TRANSIENT RESPONSE MAX15014 toc17 VOUT = 5V 135 70 EFFICIENCY vs. LOAD CURRENT (MAX15017A) 100 110 VIN = 7.5V 80 0 1 10 35 60 85 TEMPERATURE (°C) VOUT = 5V 90 70 30 20 10 VOUT = 3.3V 90 EFFICIENCY (%) EFFICIENCY (%) 70 60 100 EFFICIENCY (%) 90 VIN = 7.5V -15 EFFICIENCY vs. LOAD CURRENT (MAX15014) MAX15014 toc14 VOUT = 3.3V -40 MAX15014 toc15 10ms/div MAX15014 toc13 100 EFFICIENCY (%) MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators 10 100 LOAD CURRENT (mA) 1000 200µs/div 200µs/div _______________________________________________________________________________________ 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators LX VOLTAGE AND INDUCTOR CURRENT LX VOLTAGE AND INDUCTOR CURRENT MAX15014 toc20 MAX15014 toc19 MAX150_ _ VLX 5V/div VLX 5V/div 0V 0V INDUCTOR CURRENT 100mA/div INDUCTOR CURRENT 200mA/div 0V ILOAD = 40mA ILOAD = 160mA 2µs/div 2µs/div LX VOLTAGE AND INDUCTOR CURRENT MINIMUM LX PULSE WIDTH vs. LOAD CURRENT MAX15014 toc21 MAX15014 toc22 400 350 LX PULSE WIDTH (ns) VLX 5V/div 0V INDUCTOR CURRENT 500mA/div 300 250 200 150 100 50 ILOAD = 1A VOUT = 3.3V 0 300 2µs/div 400 500 600 700 800 900 1000 LOAD CURRENT (mA) 40 NO LOAD 30 20 5.05 ILOAD = 1mA 5.00 ILOAD = 10mA 4.95 ILOAD = 50mA 4.90 10 MAX15015A MAX15015B 0 4.85 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 ILOAD = 1mA 3.30 LDO OUTPUT VOLTAGE (V) 50 3.31 MAX15014 toc24 ILOAD = 100µA LDO OUTPUT VOLTAGE (V) LDO QUIESCENT CURRENT (µA) 60 OUTPUT VOLTAGE vs. TEMPERATURE 5.10 MAX15014 toc23 70 OUTPUT VOLTAGE vs. TEMPERATURE MAX15014 toc25 LDO QUIESCENT CURRENT vs. TEMPERATURE 3.29 3.28 ILOAD = 10mA 3.27 3.26 ILOAD = 50mA 3.25 3.24 MAX15015B 3.23 -40 -15 10 35 60 85 TEMPERATURE (°C) 110 135 -40 -15 10 35 60 85 TEMPERATURE (°C) 110 135 _______________________________________________________________________________________ 9 MAX15014–MAX15017 Typical Operating Characteristics (continued) (VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1µF, CIN_SW = 0.1µF, CIN_LDO = 0.1µF, CLDO_OUT = 10µF, CDRAIN = 0.22µF, see Figures 6 and 7, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1µF, CIN_SW = 0.1µF, CIN_LDO = 0.1µF, CLDO_OUT = 10µF, CDRAIN = 0.22µF, see Figures 6 and 7, TA = +25°C, unless otherwise noted.) 700 0 TA = +85°C TA = +25°C 500 400 TA = -40°C ILOAD = 50mA EN_SYS 2V/div ILDO_OUT = 10mA -20 PSRR (dB) 600 ILDO_OUT = 50mA -10 MAX15014 toc28 MAX15014 toc27 VIN = 5V, ILOAD = 0 TO 50mA MAX15015A TA = +135°C 800 10 MAX15014 toc26 900 TURN-ON/-OFF WAVEFORM TOGGLING EN_SYS POWER-SUPPLY REJECTION RATIO DROPOUT VOLTAGE vs. LOAD CURRENT DROPOUT VOLTAGE (mV) MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators 0V -30 -40 300 -50 200 -60 100 -70 VOUT 2V/div 0V ILDO_OUT = 1mA -80 0 0 10 20 30 LOAD CURRENT (mA) 40 0.1k 50 1k 10k 100k FREQUENCY (Hz) 1M 2ms/div 10M TURN-ON/-OFF WAVEFORM TOGGLING EN_SYS TURN-ON/-OFF WAVEFORM TOGGLING EN_SYS MAX15014 toc30 MAX15014 toc29 RLOAD = 1kΩ MAX15015B RLOAD = 66Ω EN_SYS 2V/div EN_SYS 2V/div 0V 0V VLDO_OUT 1V/div VOUT 2V/div 0V 0V 10ms/div 10ms/div TURN-ON/-OFF WAVEFORM TOGGLING EN_SYS TURN-ON/-OFF WAVEFORM INCREASING VIN MAX15014 toc32 MAX15014 toc31 ILOAD = 50mA MAX15015B RLOAD = 660Ω EN_SYS 2V/div VIN 5V/div 0V 0V VLDO_OUT 1V/div 0V 0V 10ms/div 10 VLDO_OUT 2V/div 10ms/div ______________________________________________________________________________________ 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators TURN-ON/-OFF WAVEFORM INCREASING VIN LDO TURN-ON/-OFF WAVEFORM WITH INCREASING VIN MAX15014 toc34 MAX15014 toc33 ILOAD = 5mA MAX15015B RLOAD = 66Ω VIN 2V/div VIN 5V/div 0V 0V VLDO_OUT 1V/div VLDO_OU 2V/div 0V 0V 10ms/div 10ms/div TURN-ON/-OFF WAVEFORM INCREASING VIN LOAD-TRANSIENT RESPONSE MAX15014 toc36 MAX15014 toc35 MAX15015B RLOAD = 660Ω VLDO_OUT AC-COUPLED 100mV/div VIN 5V/div 0V VLDO_OUT 1V/div 0V ILOAD 20mA/div 0 10ms/div 100µs/div INPUT-VOLTAGE STEP RESPONSE RESIDUAL SWITCHING NOISE ON THE LDO OUTPUT MAX15014 toc38 MAX15014 toc37 DC-DCLOAD = 1A MAX15015B ILOAD = 1mA VIN 20V/div VLDO_OUT 10mV/div 0V VLDO_OUT AC-COUPLED 100mV/div 1ms/div 400ns/div ______________________________________________________________________________________ 11 MAX15014–MAX15017 Typical Operating Characteristics (continued) (VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1µF, CIN_SW = 0.1µF, CIN_LDO = 0.1µF, CLDO_OUT = 10µF, CDRAIN = 0.22µF, see Figures 6 and 7, TA = +25°C, unless otherwise noted.) MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators Pin Description PIN NAME FUNCTION MAX15014/ MAX15017 MAX15015/ MAX15016 1, 2, 3, 9, 12, 14, 16, 19, 24, 26, 27, 30, 35 1, 2, 3, 9, 12, 14, 16, 19, 24, 26, 27, 30, 35 N.C. No Connection. Not internally connected. Leave unconnected or connect to SGND. 23, 28 — I.C. Internally Connected. Leave unconnected. 4 4 RESET Active-Low Reset Output. When the rising VLDO_OUT voltage crosses the reset threshold, RESET goes high after an adjustable delay. Pull up RESET to LDO_OUT with at least 4kΩ. RESET is an active-low open-drain output. 5 5 SGND Signal Ground Connection. Connect SGND and PGND together at one point near the input bypass capacitor negative terminal. 6 6 CT 7 7 EN_SW Switching Regulator Enable Input (Active High). If EN_SW is high and EN_SYS is high, the switching power supply is enabled. EN_SW is internally pulled down to SGND through a 0.5µA current sink. 8 8 EN_SYS Active-High System Enable Input. Connect EN_SYS high to turn on the system. The LDO is active if EN_SYS is high; once EN_SYS is high, the switching regulator can be turned on if EN_SW is high. EN_SYS is internally pulled down to SGND through a 0.5µA current sink. 10 10 SET_LDO LDO Feedback Input/Output Voltage Setting. Connect SET_LDO to SGND to select the preset output voltage (5V or 3.3V). Connect SET_LDO to an external resistordivider network for adjustable output operation. 11 11 LDO_OUT Linear Regulator Output. Bypass with at least 10µF low-ESR capacitor from LDO_OUT to SGND. In the 5V LDO versions (A), the LDO operates in dropout below 6V down to the UVLO trip point. 13 13 IN_LDO 15 15 BST 17, 18 17, 18 LX 20, 21 20, 21 DRAIN Drain Connection of the Internal High-Side Switch. Connect both DRAIN inputs together. PGND Power Ground Connection. Connect the input bypass capacitor negative terminal, the anode of the freewheeling diode, and the output filter capacitor negative terminal to PGND. Connect PGND to SGND together at a single point near the input bypass capacitor negative terminal. 22 12 Reset Timeout Delay Capacitor Connection. CT is pulled low during reset. When out of reset, CT is pulled up to an internal 3.6V rail with a 2µA current source. When the rising CT voltage reaches the trip threshold (typically 1.24V), RESET is deasserted. When EN_SYS is low or in thermal shutdown, CT is low. 22 LDO Input Voltage. The input voltage range for the LDO extends from 5V to 40V. Bypass with a 0.1µF ceramic capacitor to SGND. High-Side Gate Driver Supply. Connect BST to the cathode of the bootstrap diode and to the positive terminal of the bootstrap capacitor. Source Connection of Internal High-Side Switch. Connect both LX pins to the inductor and the cathode of the freewheeling diode. ______________________________________________________________________________________ 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators PIN MAX15014/ MAX15017 MAX15015/ MAX15016 NAME FUNCTION — 23 C- 25 25 DVREG — 28 C+ 29 29 SYNC Oscillator Synchronization Input. SYNC can be driven by an external clock to synchronize the switching frequency. Connect SYNC to SGND when not used. 31 31 COMP Error Amplifier Output. Connect COMP to the compensation feedback network. 32 32 FB Feedback Regulation Point. Connect to the center tap of a resistive divider from converter output to SGND to set the output voltage. The FB voltage regulates to the voltage present at SS (1.235V). 33 33 SS Soft-Start and Reference Output. Connect a capacitor from SS to SGND to set the soft-start time. See the Applications Information section to calculate the value of the CSS capacitor. 34 34 REG Internal Regulator Output. 5V output for the MAX15015/MAX15016 and 8V output for the MAX15014/MAX15017. Bypass to SGND with at least a 1µF ceramic capacitor. 36 36 IN_SW Supply Input Connection. Connect to IN_LDO and an external voltage source from 4.5V to 40V. EN_SW and EN_SYS must be high and IN_SW must be above its UVLO threshold for operation of the switching regulator. — — EP Charge-Pump Flying Capacitor Negative Connection (MAX15015/MAX15016 only) Gate Drive Supply for the High-Side MOSFET Driver. Connect to REG and to the anode of the bootstrap diode for MAX15014/MAX15017. Connect to REG for MAX15015/MAX15016. Charge-Pump Flying Capacitor Positive Connection (MAX15015/MAX15016 only). Connect to the positive terminal of the external pump capacitor and to the anode of the bootstrap diode. Exposed Pad. The exposed pad must be electrically connected to SGND. For an effective heatsinking, solder the exposed pad to a large copper plane. ______________________________________________________________________________________ 13 MAX15014–MAX15017 Pin Description MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators Detailed Description current falls to 6µA. Additional features include a programmable soft-start, cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown. The LDO linear regulator operates from 5V to 40V and delivers a guaranteed 50mA load current. The devices feature a preset output voltage of 5.0V (MAX1501_A) or 3.3V (MAX1501_B). Alternatively, the output voltage can be adjusted from 1.5V to 11V using an external resistive divider. The LDO section also features a RESET output with adjustable timeout period. The MAX15014–MAX15017 combine a voltage-mode buck converter with an internal 0.5Ω power MOSFET switch and a low-quiescent-current LDO regulator. The buck converter of the MAX15015/MAX15016 has a wide input voltage range of 4.5V to 40V. The MAX15014/MAX15017’s input voltage range is 7.5V to 40V. Fixed switching frequencies of 135kHz and 500kHz are available. The internal low RDS_ON switch allows for up to 1A of output current, and the output voltage can be adjusted from 1.26V to 32V. External compensation and voltage feed-forward simplify loop compensation design and allow for a wide variety of L and C filter components. All devices offer an automatic switchover to pulse-skipping (PFM) mode, providing low quiescent current and high efficiency at light loads. Under no load, PFM mode operation reduces the current consumption to 5.6mA for the MAX15014/ MAX15017 and 8.6mA for the MAX15015/MAX15016. In shutdown (DC-DC and LDO regulator off), the supply IN_SW Enable Inputs and UVLO The MAX15014–MAX15017 feature two logic inputs, EN_SW (active-high) and EN_SYS (active-high) that can be used to enable the switching power supply and the LDO_OUT outputs. When VEN_SW is higher than the threshold and EN_SYS is high, the switching power supply is enabled. When EN_SYS is high, the LDO is active. When EN_SYS is low, the entire chip is off (see Table 1). EN_SYS IN_LDO C- C+ DVREG DVREG IN_LDO VINT REG UVLO_LDO VREFOK VINTOK VINT VINT VREG_EN UVLO_SW TSD SHDN - ENABLE LDO THERMAL SHDN TSD - SHDN VREF VINT SET_LOD MUX VINT UVLO_LDO TSD SHDN VINT VREF VREFOK + PREREG + VREF REF VINT VINTOK VREG_OK ISS LDO_OUT PASS ELEMENT 4.1V + REG_LDO LEVEL SHIFT PCLK UVLO_SW VREFOK VINTOK - EN_SW MAX15015/MAX15016 7.0V OR 4.1V VINT VINT 2µA OUT_LDO 185mV 0.925 x VREF VREF + RESET + DELAY COMPARATOR CT EN VREG_ OK DRAIN + SS + E/A - FB + SSA - - HIGH-SIDE CURRENT SENSE PFM OVERLOAD MANAGEMENT COMP REF_ILIM + VREF - REF_PFM BST CLK OVERL LX IN S/W SYNC EN OSC RAMP - + CPWM + PFM 0.3V SGND DVREG LOGIC CLK SCLK PCLK Figure 1. MAX15015/MAX15016 Simplified Block Diagram 14 ______________________________________________________________________________________ PGND 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators EN_SYS IN_LDO - PASS ELEMENT 4.1V VINT VINT VINT VREG_EN UVLO_SW TSD SHDN - ENABLE LDO THERMAL SHDN TSD - SHDN VREF MUX VINT UVLO_LDO TSD SHDN VINT VREF VREFOK + PREREG VINTOK VREG_OK EN_SW LDO_OUT UVLO_LDO VREFOK VINTOK + VREF REF UVLO_SW VREFOK VINTOK + REG_LDO ISS MAX15014/MAX15017 7.0V OR 4.1V VINT REG IN_LDO VINT VINT 2µA VINT SET_LOD OUT_LDO 185mV 0.925 x VREF VREG_ OK VREF + + RESET DELAY COMPARATOR EN CT + + E/A - SS FB + SSA - ILIM VREF DRAIN - REF_ILIM HIGH-SIDE CURRENT SENSE + PFM OVERLOAD MANAGEMENT COMP - REF_PFM CLK BST OVERL IN S/W SYNC EN OSC RAMP LX + - CPWM PFM SCLK 0.3V PCLK CLK SGND DVREG LOGIC + PGND Figure 2. MAX15014/MAX15017 Simplified Block Diagram Table 1. Enable Inputs Configuration EN_SW LDO REGULATOR DC-DC SWITCHING CONVERTER Low Low Off Off Low High Off Off EN_SYS High Low On Off High High On On The MAX15014–MAX15017 provide undervoltage lockout (UVLO). The UVLO monitors the input voltage (VIN_LDO) and is fixed at 4.1V (MAX15015/MAX15016) or 7V (MAX15014/MAX15017). Internal Linear Regulator (REG) REG is the output terminal of a 5V (MAX15015/ MAX15016), or 8V (MAX15014/MAX15017) LDO which is powered from IN_SW and provides power to the IC. Connect REG externally to DVREG to provide power for the high-side MOSFET gate driver. Bypass REG to SGND with a ceramic capacitor (CREG) of at least 1µF. Place the capacitor physically close to the MAX15014– MAX15017 to provide good bypassing. During normal operation, REG is intended for powering up only the internal circuitry and should not be used to supply power to external loads. ______________________________________________________________________________________ 15 MAX15014–MAX15017 IN_SW MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators Soft-Start and Reference (SS) SS is the 1.235V reference bypass connection for the MAX15014–MAX15017 and also controls the soft-start period. At startup, after input voltage is applied at IN_SW, IN_LDO and the UVLO thresholds are reached, the device enters soft-start. During soft-start, 14µA is sourced into the capacitor (CSS) connected from SS to SGND causing the reference voltage to ramp up slowly. When VSS reaches 1.244V, the output becomes fully active. Set the soft-start time (tSS) using following equation: V × CSS t SS = SS ISS where VSS = soft-start reference voltage = 1.235V (typ), ISS = soft-start current = 14 x 10-6A (typ), tSS is in seconds and CSS is in Farads. Internal Charge Pump (MAX15015/MAX15016) The MAX15015/MAX15016 feature an internal charge pump to enhance the turn-on of the internal MOSFET, allowing for operation with input voltages down to 4.5V. Connect a flying capacitor (CF) between C+ and C-, a boost diode from C+ to BST, as well as a bootstrap capacitor (CBST) between BST and LX to provide the gate drive voltage for the high-side n-channel DMOS switch. During the on-time, the flying capacitor is charged to VDVREG. During the off-time, the positive terminal of the flying capacitor (C+) is pumped to two times VDVREG and charge is dumped onto CBST to provide twice the regulator voltage across the high-side DMOS driver. Use a ceramic capacitor of at least 0.1µF for CBST and CF located as close as possible to the device. Gate Drive Supply (DVREG) DVREG is the supply input for the internal high-side MOSFET driver. The power for DVREG is derived from the output of the internal regulator (REG). Connect DVREG to REG externally. To filter the switching noise, the use of an RC filter (1Ω and 0.47µF) from REG to DVREG is recommended. In the MAX15015/MAX15016, the high-side drive supply is generated using the internal charge pump along with the bootstrap diode and capacitor. In the MAX15014/MAX15017, the high-side MOSFET driver supply is generated using only the bootstrap diode and capacitor. Error Amplifier The output of the internal error amplifier (COMP) is available for frequency compensation (see the Compensation Design section). The inverting input is FB, the noninverting input SS, and the output COMP. The error amplifier has an 16 80dB open-loop gain and a 1.8MHz GBW product. See the Typical Operating Characteristics for the Gain and Phase vs. Frequency graph. Oscillator/Synchronization Input (SYNC) With SYNC connected to SGND, the MAX15014– MAX15017 use their internal oscillator and switch at a fixed frequency of 135kHz and 500kHz. The MAX15014/ MAX15016 are the 135kHz options and MAX15015/ MAX15017 are the 500kHz options. For external synchronization, drive SYNC with an external clock from 400kHz to 600kHz (MAX15015/MAX15017) or 100kHz to 200kHz (MAX15014/MAX15016). When driven with an external clock, the device synchronizes to the rising edge of SYNC. PWM Comparator/Voltage Feed-Forward An internal ramp generator clocked by the internal oscillator is compared against the output of the error amplifier to generate the PWM signal. The maximum amplitude of the ramp (VRAMP) automatically adjusts to compensate for input voltage and oscillator frequency changes. This causes the V IN_SW / V RAMP to be a constant 10V/V across the input voltage range of 4.5V to 40V (MAX15015/MAX15016) or 7.5V to 40V (MAX15014/ MAX15017) and the SYNC frequency range of 400kHz to 600kHz (MAX15015/MAX15017) or 100kHz to 200kHz (MAX15014/MAX15016). Output Short-Circuit Protection (Hiccup Mode) The MAX15014–MAX15017 protect against an output short circuit by utilizing hiccup-mode protection. In hiccup mode, a series of sequential cycle-by-cycle current-limit events cause the part to shut down and restart with a soft-start sequence. This allows the device to operate with a continuous output short circuit. During normal operation, the current is monitored at the drain of the internal power MOSFET. When the current limit is exceeded, the internal power MOSFET turns off until the next on-cycle and a counter increments. If the counter counts seven consecutive current-limit events, the device discharges the soft-start capacitor and shuts down for 512 clock periods before restarting with a soft-start sequence. Each time the power MOSFET turns on and the device does not exceed the current limit, the counter is reset. LDO Regulator The LDO regulator operates over an input voltage from 5V to 40V, and can be enabled independently of the DC-DC converter section. Its quiescent current is as low as 47µA with a load current of 100µA. All devices ______________________________________________________________________________________ 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators RESET Output The RESET output is typically connected to the reset input of a microprocessor (µP). A µP’s reset input starts or restarts the µP in a known state. The MAX15014– MAX15017 supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power-down, and brownout conditions. RESET changes from high to low whenever the monitored voltage drops below the RESET threshold voltage. Once the monitored voltage exceeds its respective RESET threshold voltage(s), RESET remains low for the RESET timeout period, then goes high. The RESET timeout period is adjustable with an external capacitor (CCT) connected to CT. Thermal-Shutdown Protection The MAX15014–MAX15017 feature thermal shutdown protection which limits the total power dissipation in the device and protects it in the event of an extended thermal fault condition. When the die temperature exceeds +160°C, an internal thermal sensor shuts down the part, turning off the DC-DC converter and the LDO regulator, and allowing the IC to cool. After the die temperature falls by 20°C, the part restarts with a soft-start sequence. Applications Information Setting the Output Voltage Connect a resistive divider (R3 and R4, see Figures 6 and 7) from OUT to FB to SGND to set the output voltage. Choose R3 and R4 so that DC errors due to the FB input bias current do not affect the output-voltage setting precision. For the most common output-voltage settings (3.3V or 5V), R3 values in the 10kΩ range are adequate. Select R3 first and calculate R4 using the following equation: R4 = where VFB = 1.235V. R3 ⎡ VOUT ⎤ − 1⎥ ⎢ ⎣ VFB ⎦ Inductor Selection Three key inductor parameters must be specified for operation with the MAX15014–MAX15017: inductance value (L), peak inductor current (IPEAK), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current (∆IP-P). Higher ∆IP-P allows for a lower inductor value while a lower ∆IP-P requires a higher inductor value. A lower inductor value minimizes size and cost and improves large-signal and transient response, but reduces efficiency due to higher peak currents and higher peak-to-peak output voltage ripple for the same output capacitor. On the other hand, higher inductance increases efficiency by reducing the ∆IP-P. Resistive losses due to extra wire turns can exceed the benefit gained from lower ∆I P-P levels especially when the inductance is increased without also allowing for larger inductor dimensions. A good compromise is to choose ∆IP-P equal to 40% of the full load current. Calculate the inductor using the following equation: (V − V ) V L = OUT IN OUT VIN × fSW × ∆IP−P VIN and VOUT are typical values so that efficiency is optimum for typical conditions. The switching frequency (f SW ) is internally fixed at 135kHz (MAX15014/ MAX15016) or 500kHz (MAX15015/MAX15017) and can vary when synchronized to an external clock (see the Oscillator/Synchronization Input (SYNC) section). The ∆IP-P, which reflects the peak-to-peak output ripple, is worst at the maximum input voltage. See the Output-Capacitor Selection section to verify that the worst-case output ripple is acceptable. The inductor current (ISAT) is also important to avoid current runaway during continuous output short circuit. Select an inductor with an I SAT specification higher than the maximum peak current limit of 2.6A. Input-Capacitor Selection The discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to keep the input voltage ripple within design requirements. The input voltage ripple is comprised of ∆VQ (caused by the capacitor discharge) and ∆VESR (caused by the ESR of the input capacitor). The total voltage ripple is the sum of ∆VQ and ∆VESR. Calculate the input capacitance and ESR required for a specified ripple using the following equations: ______________________________________________________________________________________ 17 MAX15014–MAX15017 feature a preset output voltage of 5V (MAX1501_A) or 3.3V (MAX1501_B). Alternatively, the output voltage can be adjusted using an external resistive-divider network connected between LDO_OUT, SET_LDO, and SGND. See Figure 5. MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators ESR = ∆VESR ∆IP−P 2 IOUT _ MAX × D IOUT _ MAX + CIN = ∆VQ × fSW where CIN is the sum of CDRAIN and additional decoupling capacitance at the buck converter input, (V − V ) × VOUT ∆IP−P = IN OUT and VIN × fSW × L V D = OUT VIN IOUT_MAX is the maximum output current, D is the duty cycle, and fSW is the switching frequency. The MAX15014–MAX15017 include UVLO hysteresis and soft-start to avoid chattering during turn-on. However, use additional bulk capacitance if the input source impedance is high. Use enough input capacitance at lower input voltages to avoid possible undershoot below the undervoltage lockout threshold during transient loading. Output-Capacitor Selection The allowable output voltage ripple and the maximum deviation of the output voltage during load steps determine the output capacitance (COUT) and its equivalent series resistance (ESR). The output ripple is mainly composed of ∆VQ (caused by the capacitor discharge) and ∆VESR (caused by the voltage drop across the ESR of the output capacitor). The equations for calculating the peak-to-peak output voltage ripple are: ∆IP−P 8 × COUT × fSW ∆VESR = ESR × ∆IP−P ∆VQ = Normally, a good approximation of the output voltage ripple is ∆VRIPPLE = ∆VESR + ∆VQ. If using ceramic capacitors, assume the contribution to the output voltage ripple from ESR and the capacitor discharge to be equal to 20% and 80%, respectively. ∆IP-P is the peak-to-peak inductor current (see the Input-Capacitor Selection section) and fSW is the converter’s switching frequency. The allowable deviation of the output voltage during fast load transients also determines the output capaci- 18 tance, its ESR, and its equivalent series inductance (ESL). The output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. The response time (t RESPONSE) depends on the closed-loop bandwidth of the converter (see the Compensation Design section). The resistive drop across the output capacitor’s ESR, the drop across the capacitor’s ESL (∆VESL), and the capacitor discharge causes a voltage droop during the loadstep. Use a combination of low-ESR tantalum/aluminum electrolytic and ceramic capacitors for better transient load and voltage ripple performance. Non-leaded capacitors and capacitors in parallel help reduce the ESL. Keep the maximum output voltage deviation below the tolerable limits of the electronics being powered. Use the following equations to calculate the required ESR, ESL, and capacitance value during a load step: ∆VESR ISTEP I ×t COUT = STEP RESPONSE ∆VQ ∆VESL × t STEP ESL = ISTEP 1 tRESPONSE ≅ 3ƒ C ESR = where ISTEP is the load step, tSTEP is the rise time of the load step, tRESPONSE is the response time of the controller and fC is the closed-loop crossover frequency. Compensation Design The MAX15014–MAX15017 use a voltage-mode control scheme that regulates the output voltage by comparing the error amplifier output (COMP) with an internal ramp to produce the required duty cycle. The output lowpass LC filter creates a double pole at the resonant frequency, which has a gain drop of -40dB/decade. The error amplifier must compensate for this gain drop and phase shift to achieve a stable closed-loop system. The basic regulator loop consists of a power modulator, an output feedback divider, and a voltage error amplifier. The power modulator has a DC gain set by V IN / VRAMP, with a double pole and a single zero set by the output inductance (L), the output capacitance (COUT), and its ESR. The power modulator incorporates a voltage feed-forward feature, which automatically adjusts for variations in the input voltage resulting in a DC gain of 10. ______________________________________________________________________________________ 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators GMOD _ DC = fLC = VIN VRAMP 1 C8 = 10 R5 C6 2 × π × L × COUT fZESR = 1 fZI = 1 2π × R5 × C7 and fZ2 = 1 2π × (R3 + R6) × C6 and the higher frequency poles are at: fP2 = and fP3 = 1 2π × R6 × C6 1 C7 × C8 2π × R5 × C7 + C8 The compensation design primarily depends on the type of output capacitor. Ceramic capacitors exhibit very low ESR, and are well suited for high-switchingfrequency applications, but are limited in capacitance R6 R3 VOUT 2 × π × COUT × ESR The switching frequency is internally set at 500kHz for MAX15015/MAX15017 and can vary from 400kHz to 600kHz when driven with an external SYNC signal. The switching frequency is internally set at 135kHz for MAX15014/MAX15016 and can vary from 100kHz to 200kHz when driven with an external sync signal. The crossover frequency (fC), which is the frequency when the closed-loop gain is equal to unity, should be set to around 1/10 of the switching frequency or below. The crossover frequency occurs above the LC doublepole frequency, and the error amplifier must provide a gain and phase bump to compensate for the rapid gain and phase loss from the LC double pole, which exhibits little damping. This is accomplished by utilizing a Type 3 compensator that introduces two zeroes and three poles into the control loop. The error amplifier has a low-frequency pole (fP1) near the origin so that tight voltage regulation at DC can be achieved. The two zeroes are at: C7 EA R4 COMP REF GAIN (dB) CLOSED-LOOP GAIN EA GAIN fZ1 fZ2 fC fP2 fP3 FREQUENCY Figure 3. Error Amplifier Compensation Circuit (Closed-Loop and Error-Amplifier Gain Plot) for Ceramic Capacitors value and tend to be more expensive. Aluminum electrolytic capacitors have much larger ESR but can reach much larger capacitance values. Compensation when fC < fZESR This is usually the case when a ceramic capacitor is selected. In this case, fZESR occurs after fC. Figure 3 shows the error amplifier feedback as well as its gain response. fZ1 is set to 0.5 to 0.8 x fLC and fZ2 is set to fLC to compensate for the gain and phase loss due to the double pole. To achieve a 0dB crossover with -20dB/decade slope, poles fP2 and fP3 are set above the crossover frequency fC. The values for R3 and R4 are already determined in the Setting the Output Voltage section. The value of R3 is also used in the following calculations. Since fZ2 < fC < fP2, then R3 >> R6, and R3 + R6 can be approximated as R3. Now we can calculate C6 for zero fZ2 : C6 = 1 2π × fLC × R3 ______________________________________________________________________________________ 19 MAX15014–MAX15017 The following equations define the power modulator: MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators fC occurs between fZ2 and fP2. In this region, the compensator gain (GEA) at fC is due primarily to C6 and R5. Therefore, GEA(fC) = 2π x fC x C6 x R5 and the modulator gain at fC is: C8 GMOD (fC ) = R6 GMOD _ DC (2π × fC )2 × L × COUT R3 VOUT Since GEA(fC) x GMOD(fC) = 1, R5 is calculated by: EA R4 The frequency of fZ1 is set to 0.5 x fLC and now we can calculate C7: 1 2π × C6 × (0.5 × fSW ) Note that if the crossover frequency has been chosen as 1/10 of the switching frequency, then fP2 = 5xfC. The purpose of fP3 is to further attenuate the residual switching ripple at the COMP pin. If the ESR zero (f ZESR) occurs in a region between fC and fSW / 2, then fP3 can be used to cancel it. This way, the Bode plot of the loop gain plot will not flatten out soon after the 0dB crossover, and will maintain its -20dB/decade slope up to 1/2 of the switching frequency. If the ESR zero well exceeds fSW/2 (or even fSW), fP3 should in any case be set high enough not to erode the phase margin at the crossover frequency. For example, it can be set between 5 x fC and 10 x fC. The value for C8 is calculated from: C8 = C7 (2π × C7 × R5 × fP3 − 1) Compensation when fC > fZESR For larger ESR capacitors such as tantalum and aluminum electrolytic, fZESR can occur before fC. If fZESR < fC, then fC occurs between fP2 and fP3. fZ1 and fZ2 remain the same as before however, f P2 is now set equal to fZESR. The output capacitor’s ESR zero 20 GAIN (dB) CLOSED-LOOP GAIN EA GAIN 1 0.5 × 2π × R5 × fLC fP2 is set at 1/2 the switching frequency (fSW). R6 is then calculated by: R6 = COMP REF f × L × COUT × 2π R5 = C C6 × GMOD _ DC C7 = C7 R5 C6 fZ1 fZ2 fP2 fC fP3 FREQUENCY Figure 4. Error Amplifier Compensation Circuit (Closed-Loop and Error-Amplifier Gain Plot) for Higher ESR Output Capacitors frequency is higher than fLC but lower than the closedloop crossover frequency. The equations that define the error amplifier’s poles and zeros (fZ1, fZ2, fP2, and fP3) are the same as before. However, fP2 is now lower than the closed-loop crossover frequency. Figure 4 shows the error amplifier feedback as well as its gain response for circuits that use higher-ESR output capacitors (tantalum or aluminum electrolytic). Again, starting from R3, calculate C6 for zero fZ2: C6 = 1 2π × fLC × R3 and then place fP2 to cancel the ESR zero. R6 is calculated as: R6 = COUT × ESR C6 If the value obtained here for R6 is not considerably smaller than R3, then recalculate C6 using (R3 + R6) in place of R3. Then use the new value of C6 to obtain a better approximation for R6. The process can be further iterated, and convergence is ensured as long as fLC < fZESR. ______________________________________________________________________________________ 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators VIN_LDO IN_LDO LDO_OUT R3 × R6 fC2 R5 = × R3 + R6 GMOD _ DC × fLC2 C7 can still be calculated as: R1 MAX15014– MAX15017 SET_LDO C7 = 1 0.5 × 2π × R5 × fLC R2 SGND fP3 is set at 5xfC. Therefore, C8 is calculated as: C8 = C7 2π × C7 × R5 × fP3 − 1 Setting the LDO Linear Regulator Output Voltage The MAX15014–MAX15017 LDO regulator features Dual Mode™ operation: it can operate in either a preset voltage mode or an adjustable mode. In preset voltage mode, internal trimmed feedback resistors set the internal linear regulator to 3.3V or 5V (see the Selector Guide). Select preset voltage mode by connecting SET_LDO to ground. In adjustable mode, select an output voltage between 1.5V and 11V using two external resistors connected as a voltage-divider to SET_LDO (see Figure 5). Set the output voltage using the following equation: ⎛ R1 ⎞ VOUT = VSET _ LDO ⎜1 + ⎟ ⎝ R2 ⎠ where VSET_LDO = 1.241V and the recommended value for R2 is around 50kΩ. Setting the RESET Timeout Delay The RESET timeout period is adjustable to accommodate a variety of µP applications. Adjust the RESET timeout period by connecting a capacitor (C CT ) between CT and SGND. t RP = CCT × VCT − TH ICT − THQ where VCT-TH = delay comparator threshold (rising) = 1.241V (typ), ICT-THQ = CT charge current = 2 x 10-6A (typ), tRP is in seconds and CCT is in Farads. Figure 5. Setting the Output Voltage Using a Resistive Divider Connect CT to LDO_OUT to select the internally fixed timeout period. CCT must be low-leakage-type capacitor. Ceramic capacitors are recommended; do not use capacitors lower than 200pF to avoid the influence of parasitic capacitances. Capacitor Selection and Regulator Stability For stable operation over the full temperature range and with load currents up to 50mA, use a 10µF (min) output capacitor (CLDO_OUT) with a maximum ESR of 0.4Ω. To reduce noise and improve load-transient response, stability, and power-supply rejection, use larger output capacitor values. Some ceramic dielectrics such as Z5U and Y5V exhibit very large capacitance and ESR variation with temperature and are not recommended. With X7R or X5R dielectrics, 15µF should be sufficient for operation over their rated temperature range. For higherESR tantalum capacitors (up to 1Ω), use 22µF or more to maintain stability. To improve power-supply rejection and transient response use a minimum 0.1µF capacitor between IN_LDO and SGND. Power Dissipation The MAX15014–MAX15017 are available in a thermally enhanced package and can dissipate up to 2.86W at T A = +70°C. When the die temperature reaches +160°C, the part shuts down and is allowed to cool. After the die cools by 20°C, the device restarts with a soft-start. The power dissipated in the device is the sum of the power dissipated in the LDO, power dissipated from supply current (PQ), transition losses due to switching the internal power MOSFET (PSW), and the Dual Mode is a trademark of Maxim Integrated Products, Inc. ______________________________________________________________________________________ 21 MAX15014–MAX15017 The error amplifier gain between fP2 and fP3 is approximately equal to R5 / (R6 || R3). The ESR zero frequency fZESR might not be very much higher than the double-pole frequency fLC, therefore the value of R5 can be calculated as: MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators CIN_SW CIN_LDO R6 CDRAIN VIN 4.5V TO 40V R3 D1 C8 C6 IN_LDO C7 R5 IN_SW DRAIN BST COMP CBST FB R4 VIN 5V TO 40V EN_SW L VOUT1 AT 1A LX EN_SYS COUT D2 C+ MAX15015 MAX15016 CF C- RESET SS 10kΩ CT VOUT2 AT 50mA SYNC PGND LDO_OUT SGND REG CSS CCT 1Ω CREG DVREG 0.47µF CLDO_OUT SET_LDO PGND SGND Figure 6. MAX15015/MAX15016 Typical Application Circuit (4.5V to 40V Input Operation) power dissipated due to the RMS current through the internal power MOSFET (PMOSFET). The total power dissipated in the package must be limited such that the junction temperature does not exceed its absolute maximum rating of +150°C at maximum ambient temperature. Calculate the power lost in the MAX15014– MAX15017 using the following equations: The power loss through the switch: PMOSFET = (IRMS _ MOSFET )2 × RON IRMS _ MOSFET = D ⎡2 × I PK + (IPK × IDC ) + I2 DC ⎤⎥ ⎦ 3 ⎢⎣ ∆I IPK = IOUT + P−P 2 ∆IP−P IDC = IOUT − 2 VOUT D= VIN 22 RON is the on-resistance of the internal power MOSFET (see the Electrical Characteristics). The power loss due to switching the internal MOSFET: V ×I × (t R + t F ) × fSW PSW = IN OUT 4 tR and tF are the rise and fall times of the internal power MOSFET measured at LX. The power loss due to the switching supply current (ISW): PQ = VIN _ SW × ISW The power loss due to the LDO regulator: PLDO = (VIN _ LDO − VLDO _ OUT ) × ILDO _ OUT The total power dissipated in the device will be: PTOTAL = PMOSFET + PSW + PQ + PLDO ______________________________________________________________________________________ 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators CDRAIN VIN 7.5V TO 40V R3 MAX15014–MAX15017 CIN_SW CIN_LDO R6 D1 C8 C6 R5 IN_LDO C7 IN_SW DRAIN BST COMP CBST FB R4 VIN 7.5V TO 40V EN_SW L VOUT1 AT 1A LX EN_SYS COUT D2 MAX15014 MAX15017 RESET SS 10kΩ CT VOUT2 AT 50mA SYNC PGND LDO_OUT SGND REG CSS CCT 1Ω CREG DVREG 0.47µF CLDO_OUT SET_LDO PGND SGND Figure 7. MAX15014/MAX15017 Typical Application Circuit (7.5V to 40V Input-Voltage Operation) ______________________________________________________________________________________ 23 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators 28 C+ (I.C.) 29 SYNC 30 N.C. 31 COMP 32 FB 33 SS 34 REG 27 N.C. 26 N.C. 3 25 DVREG 4 24 N.C. 5 23 C- (I.C.) 22 PGND 21 DRAIN 20 DRAIN 19 N.C. + MAX15014–MAX15017 6 7 8 EP* 10 11 12 13 14 15 16 17 18 N.C. IN_LDO N.C. BST N.C. LX LX 9 ( ) MAX15014/MAX15017 *EP = EXPOSED PAD. Chip Information PROCESS: BiCMOS/DMOS 2 1 SET_LDO N.C. N.C. N.C. RESET SGND CT EN_SW EN_SYS N.C. 35 N.C. 36 IN_SW TOP VIEW LDO_OUT MAX15014–MAX15017 Pin Configuration TQFN Selector Guide LDO OUTPUT SWITCHING FREQUENCY (kHz) DC-DC MINIMUM INPUT VOLTAGE (V) CHARGE PUMP MAX15014A 135 7.5 MAX15014B 135 7.5 MAX15015A 500 4.5 MAX15015B 500 4.5 MAX15016A 135 4.5 MAX15016B 135 MAX15017A 500 MAX15017B 500 PART 24 5V 3.3V ADJUSTABLE OUTPUT — X — X — — X X X X — X X — X X X X — X 4.5 X — X X 7.5 — X — X 7.5 — — X X ______________________________________________________________________________________ 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators QFN THIN.EPS ______________________________________________________________________________________ 25 MAX15014–MAX15017 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX15014–MAX15017 1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
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