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TPA2005D1
SLOS369G – JULY 2002 – REVISED OCTOBER 2015
TPA2005D1 1.4-W MONO Filter-Free Class-D Audio Power Amplifier
1 Features
•
1
•
•
•
•
•
3 Description
The TPA2005D1 is a 1.4-W high efficiency filter-free
class-D audio power amplifier in a MicroStar Junior™
BGA, QFN, or MSOP package that requires only
three external components.
1.4 W Into 8 Ω From a 5 V Supply at
THD = 10% (Typ)
Maximum Battery Life and Minimum Heat
– Efficiency With an 8-Ω Speaker:
– 84% at 400 mW
– 79% at 100 mW
– 2.8-mA Quiescent Current
– 0.5-μA Shutdown Current
Capable of Driving an
8-Ω Speaker (2.5 V ≤ VDD ≤ 5.5 V) and a
4-Ω Speaker (2.5 V ≤ VDD ≤ 4.2 V)
Only Three External Components
– Optimized PWM Output Stage Eliminates LC
Output Filter
– Internally Generated 250-kHz Switching
Frequency Eliminates Capacitor & Resistor
– Improved PSRR (–71 dB at 217 Hz) and
Wide Supply Voltage (2.5 V to 5.5 V)
Eliminates Need for a Voltage Regulator
– Fully Differential Design Reduces RF
Rectification & Eliminates Bypass Capacitor
– Improved CMRR Eliminates Two Input
Coupling Capacitors
Space Saving Package
– 3 mm × 3 mm QFN package (DRB)
– 2.5 mm × 2.5 mm MicroStar Junior™ BGA
Package (ZQY)
– 3 mm x 5 mm MSOP PowerPAD™ Package
(DGN)
Use TPA2006D1 for 1.8 V Logic Compatibility on
Shutdown Pin
Features like 84% efficiency, –71-dB PSRR
at 217 Hz, improved RF-rectification immunity, and
15 mm2 total PCB area make the TPA2005D1 ideal
for cellular handsets. A fast start-up time of 9 ms with
minimal pop makes the TPA2005D1 ideal for PDA
applications.
In cellular handsets, the earpiece, speaker phone,
and melody ringer can each be driven by the
TPA2005D1. The device allows independent gain
control by summing the signals from each function
while minimizing noise to only 48 μVRMS.
The TPA2005D1 has
protection.
short-circuit
and
thermal
Device Information(1)
PART NUMBER
TPA2005D1
PACKAGE
BODY SIZE (NOM)
HVSSOP (8)
3.00 mm × 3.00 mm
VSON (8)
3.00 mm x 3.00 mm
BGA MICROSTAR
JUNIOR (15)
2.50 mm x 2.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Device Layout and Size
Actual Solution Size
CS
2.5 mm
RI
RI
2 Applications
6 mm
Ideal for Wireless or Cellular Handsets and PDAs
Application Circuit
To Battery
Internal
Oscillator
+
RI
VO+
PWM
–
RI
CS
IN–
_
Differential
Input
VDD
+
H–
Bridge
VO–
IN+
GND
SHUTDOWN
Bias
Circuitry
TPA2005D1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA2005D1
SLOS369G – JULY 2002 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 16
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Applications ............................................. 20
11 Power Supply Recommendations ..................... 24
11.1 Power Supply Decoupling Capacitors................... 24
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Examples................................................... 26
13 Device and Documentation Support ................. 28
13.1
13.2
13.3
13.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
14 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (July 2008) to Revision G
•
Page
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision E (July 2008) to Revision F
Page
•
Added Capable of Driving an 8-Ω Speaker and a 4-Ω Speaker ............................................................................................ 1
•
Added Use TPA2006D1 for 1.8 V Logic Compatibility on Shutdown Pin............................................................................... 1
•
Added to Description: The TPA2005D1 has short-circuit and thermal protection.................................................................. 1
•
Changed Storage temperature From: -40°C to 85°C To: -40°C to 150°C ............................................................................. 4
•
Added RL Load resistance, to the Abs Max Ratings Table .................................................................................................... 4
•
Added New graph, Figure 3 .................................................................................................................................................. 6
•
Changed graph, Figure 4 ....................................................................................................................................................... 6
•
Added graph, Figure 10 ......................................................................................................................................................... 6
•
Changed graph, Figure 11 ..................................................................................................................................................... 6
•
Changed graph, Figure 12 ..................................................................................................................................................... 6
•
Added graph, Figure 13 ......................................................................................................................................................... 7
•
Added graph, Figure 20 ......................................................................................................................................................... 8
•
Added graph, Figure 21 ......................................................................................................................................................... 8
•
Added graph, Figure 22 ......................................................................................................................................................... 8
•
Added Any capacitor in the audio path should have a rating of X7R or better. ................................................................... 23
•
Deleted Section: 8-Pin QFN 9DRB) Layout ......................................................................................................................... 26
2
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SLOS369G – JULY 2002 – REVISED OCTOBER 2015
5 Device Comparison Table
DEVICE
NUMBER
SPEAKER
CHANNELS
SPEAKER AMP
TYPE
OUTPUT POWER
(W)
PSRR (dB)
SUPPLY MIN (V)
SUPPLY MAX (V)
PACKAGE
FAMILY
BGA MICROSTAR
JUNIOR
TPA2005D1
Mono
Class D
1.4
75
2.5
5.5
TPA2006D1
Mono
Class D
1.45
75
2.5
5.5
HVSSOP
VSON
VSON
6 Pin Configuration and Functions
GQY and ZQY Packages
15-Pin MicroStar Junior™
Top and Side Views
SHUTDOWN
NC
IN+
IN−
(A1)
(B1)
(C1)
(D1)
(A4)
(B4)
(C4)
(D4)
DRB Package
8-Pin VSON
Top View
VO−
SHUTDOWN
VDD
VDD
VO+
DGN Package
8-Pin HVSSOP
Top View
SHUTDOWN
1
8 V
O−
SHUTDOWN
1
8
VO−
NC
2
7 GND
NC
2
7
GND
IN+
3
6 VDD
IN+
3
6
VDD
IN−
4
5 VO+
IN−
4
5
VO+
GND
NC − No internal connection
A.
The shaded terminals are used for electrical and thermal connections to the ground plane. All the shaded terminals
need to be electrically connected to ground. No connect (NC) terminals still need a pad and trace.
B.
The thermal pad of the DRB and DGN packages must be electrically and thermally connected to a ground plane.
Pin Functions
PIN
NAME
I/O
DESCRIPTION
GQY, ZQY
DRB, DGN
A2, A3, B3, C2, C3,
D2, D3
7
I
High-current ground
IN-
D1
4
I
Negative differential input
IN+
C1
3
I
Positive differential input
NC
B1
2
SHUTDOWN
A1
1
GND
No internal connection
I
Thermal Pad
Shutdown terminal (active low logic)
Must be soldered to a grounded pad on the PCB.
VDD
B4, C4
6
I
Power supply
VO-
A4
8
O
Negative BTL output
VO+
D4
5
O
Positive BTL output
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
In active mode
–0.3
6
V
In SHUTDOWN mode
V
VDD
Supply voltage (2)
–0.3
7
VI
Input voltage
–0.3
VDD + 0.3 V
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
85
°C
Tstg
Storage temperature
–65
150
°C
RL
(1)
(2)
Load resistance
2.5 ≤ VDD ≤ 4.2 V
3.2 (Minimum)
Ω
4.2 < VDD ≤ 6 V
6.4 (Minimum)
Ω
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For the MSOP (DGN) package option, the maximum VDD should be limited to 5 V if short-circuit protection is desired.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
RI
Input resistor
Gain ≤ 20 V/V (26 dB)
VIC
Common mode input voltage range
VDD = 2.5 V, 5.5 V, CMRR ≤ –49 dB
TA
Operating free-air temperature
NOM
MAX
UNIT
2.5
5.5
V
SHUTDOWN
2
VDD
V
SHUTDOWN
0
0.8
15
V
kΩ
0.5
VDD-0.8
V
–40
85
°C
7.4 Thermal Information
TPA2005D1
THERMAL METRIC (1)
ZQY
(MicroStar
Junior)
GQY
(MicroStar
Junior)
DRB (VSON)
DGN (MSOP
PowerPAD)
UNIT
15 PINS
15 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
92.7
92.7
50.9
57.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
120.5
120.5
66.2
53.8
°C/W
RθJB
Junction-to-board thermal resistance
104
104
25.9
33.7
°C/W
ψJT
Junction-to-top characterization parameter
3.1
3.1
1.4
1.9
°C/W
ψJB
Junction-to-board characterization parameter
44.8
44.8
26
33.47
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
7
6.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
TA = 25°C, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOS|
Output offset voltage (measured
differentially)
VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V
PSRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
CMRR
Common mode rejection ratio
VDD = 2.5 V to 5.5 V, VIC= VDD/2 to 0.5 V,
VIC= VDD/2 to VDD- 0.8 V
|IIH|
High-level input current
|IIL|
Low-level input current
I(Q)
I(SD)
rDS(on)
f(sw)
Quiescent current
Shutdown current
Static drain-source on-state resistance
MIN
TYP
MAX
UNIT
25
mV
–75
–55
dB
–68
–49
dB
VDD = 5.5 V, VI = 5.8 V
50
μA
VDD = 5.5 V, VI = 0.3 V
1
μA
VDD = 5.5 V, no load
3.4
VDD = 3.6 V, no load
2.8
VDD = 2.5 V, no load
2.2
3.2
V (SHUTDOWN) = 0.8 V, VDD = 2.5 V to 5.5 V
0.5
2
VDD = 2.5 V
770
VDD = 3.6 V
590
VDD = 5.5 V
500
Output impedance in SHUTDOWN
V (SHUTDOWN) = 0.8 V
Switching frequency
VDD = 2.5 V to 5.5 V
4.5
mA
μA
mΩ
>1
200
Gain
2
142 kW
RI
kΩ
250
2
300
150 kW
RI
2
kHz
V
V
158 kW
RI
7.6 Operating Characteristics
TA = 25°C, Gain = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Output power
VDD = 3.6 V
0.58
VDD = 2.5 V
0.26
VDD = 5 V
THD + N= 10%, f = 1 kHz, RL
VDD = 3.6 V
=8Ω
VDD = 2.5 V
1.45
PO = 1 W, f = 1 kHz, RL = 8
Ω
THD+N
TYP
1.18
THD + N= 1%, f = 1 kHz, RL
=8Ω
PO
MIN
VDD = 5 V
UNIT
W
0.75
W
0.35
VDD = 5 V
0.18%
Total harmonic distortion plus PO = 0.5 W, f = 1 kHz, RL = 8
VDD = 3.6 V
noise
Ω
0.19%
PO = 200 mW, f = 1 kHz, RL
=8Ω
VDD = 2.5 V
0.20%
–71
dB
dB
kSVR
Supply ripple rejection ratio
f = 217 Hz, V(RIPPLE) = 200
mVpp
Inputs ac-grounded with Ci =
2 μF
VDD = 3.6 V
SNR
Signal-to-noise ratio
PO= 1 W, RL = 8 Ω
VDD = 5 V
97
No weighting
48
Vn
Output voltage noise
VDD = 3.6 V, f = 20 Hz to 20
kHz,
Inputs ac-grounded with Ci =
2 μF
A weighting
36
CMRR
Common mode rejection ratio VIC = 1 Vpp , f = 217 Hz
ZI
Input impedance
Start-up time from shutdown
MAX
VDD = 3.6 V
–63
142
VDD = 3.6 V
μVRMS
150
dB
158
9
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kΩ
ms
5
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7.7 Typical Characteristics
100
90
RL = 32 W, 33 mH
90
80
RL = 8 W, 33 mH
Efficiency - %
70
RL = 16 W, 33 mH
Efficiency - %
60
50
40
30
10
RL = 8W, 33mH
70
VDD = 2.5 V,
60
RL = 8W, 33mH
50
40
Class-AB,
VDD = 5 V,
RL = 8 W
30
Class-AB,
RL = 8 Ω
20
VDD = 5 V,
80
20
10
VDD = 3.6
0
0
0
0.1
0.2
0.3
0.4
0.5
0
0.6
0.2
0.4
0.6
0.8
1
1.2
PO - Output Power - W
PO - Output Power - W
Figure 2. Efficiency vs Output Power
Figure 1. Efficiency vs Output Power
90
0.7
Class-AB, V DD = 5 V, RL = 8 W
80
0.6
70
PD - Power Dissipation - W
Efficiency - %
VDD = 4.2 V,
60
RL = 4 W, 33 mH
50
40
30
20
10
Class-AB,
VDD = 3.6 V,
RL = 8 W
0.5
0.4
0.5
1
1.5
RL = 4 W, 33 mH
0.3
VDD = 3.6 V,
RL = 8 W, 33 mH
0.2
0.1
VDD = 5 V,
RL = 8 W, 33 mH
0
0
0
VDD = 4.2 V,
0
0.2
0.4
0.6
0.8
1
1.2
PO - Output Power - W
PO - Output Power - W
Figure 3. Efficiency vs Output Power
Figure 4. Power Dissipation vs Output Power
250
300
VDD = 3.6 V
250
Supply Current - mA
Supply Current - mA
200
RL = 8 W, 33 mH
150
100
200
150
100
50
VDD = 3.6 V,
RL = 8 W, 33 mH
50
RL = 32 W, 33 mH
0
0
0.1
0.2
0.3
0.4
PO - Output Power - W
VDD = 2.5 V,
RL = 8 W, 33 mH
0
0.5
0
0.6
0.2
0.4
0.6
0.8
1
1.2
PO - Output Power - W
Figure 5. Supply Current vs Output Power
6
VDD = 5 V,
RL = 8 W, 33 mH
Figure 6. Supply Current vs Output Power
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3.8
1
3.6
0.9
I (SD) - Shutdown Current - m A
I (Q) − Quiescent Current − mA
Typical Characteristics (continued)
3.4
RL = 8 W, 33 mH
3.2
3
2.8
No Load
2.6
2.4
0.8
0.7
0.6
VDD = 2.5 V
0.5
0.4
VDD = 3.6 V
0.3
VDD = 5 V
0.2
2.2
0.1
0
2
2.5
3
3.5
4
4.5
5
0
5.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
VDD − Supply Voltage − V
Shutdown Voltage - V
Figure 7. Quiescent Current vs Supply Voltage
Figure 8. Shutdown Current vs Shutdown Voltage
1.6
1.6
RL = 8 W
f = 1 kHz
Gain = 2 V/V
1.4
1.2
RL = 4 W,
f = 1kHz,
Gain = 2 V/V
1.2
1
PO - Output Power - W
PO - Output Power - W
1.4
THD+N = 10%
0.8
1
THD+N = 10%
0.8
0.6
THD+N = 1%
0.6
THD+N = 1%
0.4
0.4
0.2
0.2
0
2.5
3
3.5
4
4.5
0
2.5
5
3
VDD - Supply Voltage - V
3.5
4
4.5
VDD - Supply Voltage - V
Figure 9. Output Power vs Supply Voltage
Figure 10. Output Power vs Supply Voltage
1.8
1.4
f = 1 kHz,
THD+N = 1%,
Gain = 2 V/V
1.2
f = 1 kHz,
THD+N = 10%,
Gain = 2 V/V
1.6
PO - Output Power - W
PO - Output Power - W
1.4
1
VDD = 3.6 V
VDD = 4.2 V
0.8
VDD = 5 V
0.6
0.4
VDD = 5 V
1.2
VDD = 4.2 V
1
VDD = 3.6 V
0.8
0.6
0.4
0.2
0.2
VDD = 2.5 V
0
4
8
12
16
20
24
28
0
4
32
VDD = 2.5 V
RL - Load Resistance - W
8
12
16
20
24
RL - Load Resistance - W
28
32
Figure 11. Output Power vs Load Resistance
Figure 12. Output Power vs Load Resistance
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30
20
RL = 4 W,
f = 1 kHz,
Gain = 2 V/V
10
VDD = 2.5 V
5
VDD = 3.6 V
2
VDD = 4.2 V
1
0.5
0.2
0.1
0.01
0.1
1
2
THD+N − Total Harmonic Distortion + Noise − %
THD+N - Total Harmonic Distortion + Noise - %
Typical Characteristics (continued)
30
20
10
RL = 8 W,
f = 1 kHz,
Gain = 2 V/V
5
2.5 V
2
3.6 V
1
5V
0.5
0.2
0.1
0.01
0.1
RL = 16 W,
f = 1 kHz,
Gain = 2 V/V
10
5
2.5 V
2
3.6 V
1
5V
0.5
0.2
0.1
0.01
0.1
1
2
10
VDD = 5 V
CI = 2 mF
RL = 8 W
Gain = 2 V/V
5
2
1
0.5
0.2
50 mW
0.1
1W
0.05
0.02
250 mW
0.008
20
100
PO − Output Power − W
8
10
2
VDD = 3.6 V
CI = 2 mF
RL = 8 W
Gain = 2 V/V
1
0.5
0.2
500 mW
25 mW
0.1
0.05
125 mW
0.02
0.01
20
100
1k
20 k
1k
f − Frequency − Hz
20 k
Figure 16. Total Harmonic Distortion + Noise vs Frequency
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
Figure 15. Total Harmonic Distortion + Noise vs Output
Power
5
2
Figure 14. Total Harmonic Distortion + Noise vs Output
Power
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
Figure 13. Total Harmonic Distortion + Noise vs Output
Power
30
20
1
PO − Output Power − W
PO - Output Power - W
10
VDD = 2.5 V
CI = 2 mF
RL = 8 W
Gain = 2 V/V
5
2
1
15 mW
75 mW
0.5
0.2
0.1
200 mW
0.05
0.02
0.01
20
100
1k
20 k
f − Frequency − Hz
f − Frequency − Hz
Figure 17. Total Harmonic Distortion + Noise vs Frequency
Figure 18. Total Harmonic Distortion + Noise vs Frequency
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10
VDD = 3.6 V
CI = 2 mF
RL = 16 W
Gain = 2 V/V
5
2
1
0.5
0.2
15 mW
0.1
75 mW
0.05
0.02
200 mW
0.01
20
100
1k
20 k
THD+N - Total Harmonic Distortion + Noise - %
THD+N − Total Harmonic Distortion + Noise − %
Typical Characteristics (continued)
10
5
VDD = 4.2 V,
2
R L = 4 W,
Gain = 2 V/V
500 mW
1
0.5
250 mW
1W
0.2
0.1
0.05
0.02
0.01
20
Figure 19. Total Harmonic Distortion + Noise vs Frequency
Figure 20. Total Harmonic Distortion + Noise vs Frequency
10
5
VDD = 3.6 V,
2
R L = 4 W,
Gain = 2V/V
1
250 mW
0.5
775 mW
500 mW
0.2
0.1
0.05
0.02
0.01
20
100
1k
f-Frequency-Hz
20k
1
VDD = 2.5 V
VDD = 3.6 V
0.1
0
5
VDD = 2.5 V,
2
RL = 4 W,
Gain = 2V/V
75 mW
15 mW
1
0.5
200 mW
0.2
0.1
0.05
0.02
0.01
20
100
1k
f - Frequency - Hz
20k
0
CI = 2 mF
RL = 8 W
Vp-p = 200 mV
Inputs ac-Grounded
Gain = 2 V/V
−10
−20
−30
−40
VDD = 3.6 V
−50
VDD =2. 5 V
−60
−70
VDD = 5 V
−80
0.5
1
1.5
2
2.5
3
3.5
VIC - Common Mode Input Voltage - V
Figure 23. Total Harmonic Distortion + Noise vs
Common Mode Input Voltage
20k
Figure 22. Total Harmonic Distortion + Noise vs Frequency
− Supply Voltage Rejection Ratio − dB
SVR
f = 1 kHz
PO = 200 mW
100
10
10
k
THD+N - Total Harmonic Distortion + Noise - %
Figure 21. Total Harmonic Distortion + Noise vs Frequency
THD+N - Total Harmonic Distortion + Noise - %
1k
f - Frequency - Hz
THD+N - Total Harmonic Distortion + Noise - %
f − Frequency − Hz
20
100
1k
f − Frequency − Hz
20 k
Figure 24. Supply Voltage Rejection Ratio vs Frequency
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Gain = 5 V/V
CI = 2 mF
RL = 8 W
Vp-p = 200 mV
Inputs ac-Grounded
−20
−30
VDD = 2. 5 V
−40
−50
VDD = 5 V
−60
−70
VDD = 3.6 V
−80
20
100
1k
f − Frequency − Hz
20 k
Figure 25. Supply Voltage Rejection Ratio vs Frequency 25
CI = 2 mF
RL = 8 W
Inputs Floating
Gain = 2 V/V
−10
−20
−30
−40
−50
−60
VDD = 3.6 V
−70
−80
−90
−100
20
100
1k
f − Frequency − Hz
Figure 26. Supply Voltage Rejection Ratio vs Frequency
- Supply Voltage Rejection Ratio - dB
0
0
f = 217 Hz
RL = 8 W
Gain = 2 V/V
-10
-20
-50
-100
-30
VDD = 2.5 V
VDD = 3.6 V
-60
k
SVR
-70
-80
VDD = 5 V
-90
0
-100
0
VDD Shown in Figure 22
CI = 2 mF,
Inputs ac-grounded
Gain = 2V/V
-50
-150
V DD - Supply Voltage - dBV
-50
-100
-150
400
800
1200
1600
-100
-150
0
400
800
1200
1600
2000
2000
Figure 28. GSM Power Supply Rejection vs Time
f - Frequency - Hz
Figure 29. GSM Power Supply Rejection vs Frequency
10
-150
f - Frequency - Hz
Figure 27. Supply Voltage Rejection Ratio vs
Common-mode Input Voltage
VO - Output Voltage - dBV
-50
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIC - Common Mode Input Voltage - V
0
VDD Shown in Figure 22
CI = 2 mF,
Inputs ac-grounded
Gain = 2V/V
0
CMRR − Common Mode Rejection Ratio − dB
-50
VO - Output Voltage - dBV
-40
0
20 k
V DD - Supply Voltage - dBV
−10
0
− Supply Voltage Rejection Ratio − dB
SVR
0
k
k
− Supply Voltage Rejection Ratio − dB
SVR
Typical Characteristics (continued)
0
VDD = 2.5 V to 5 V
VIC = 1 Vp−p
RL = 8 W
Gain = 2 V/V
−10
−20
−30
−40
−50
−60
−70
20
100
1k
f − Frequency − Hz
20 k
Figure 30. Common-mode Rejection Ratio vs Frequency
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Typical Characteristics (continued)
CMRR - Common Mode Rejection Ratio - dB
0
RL = 8W
Gain = 2 V/V
-10
-20
-30
-40
VDD = 2.5 V
VDD = 3.6 V
-50
-60
-70
-80
VDD = 5 V
-90
-100
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
VIC - Common Mode Input Voltage - V
5
Figure 31. Common-mode Rejection Ratio vs
Common-mode Input Voltage
8 Parameter Measurement Information
TPA2005D1
CI
+
Measurement
Output
CI
±
RI
IN+
OUT+
Load
RI
IN±
OUT±
VDD
+
30 kHz
Low Pass
Filter
+
Measurement
Input
±
GND
1 mF
VDD
±
(1)
CI was Shorted for any Common-Mode input voltage measurement .
(2)
A 33-mH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
(3)
The 30-kHz low-pass filter is required even if the analyzer has a low-pass filter. An RC filter (100 W, 47 nF) is used
on each output for the data sheet graphs.
Figure 32. Test Set-up for Graphs
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9 Detailed Description
9.1 Overview
The TPA2005D1 is a high-efficiency filter-free Class-D audio amplifier capable of delivering up to 1.4 W into 8-Ω
loads with 5-V power supply. The fully-differential design of this amplifier avoids the usage of bypass capacitors
and the improved CMRR eliminates the usage of input-coupling capacitors. This makes the device size a perfect
choice for small, portable applications as only three external components are required.
The advanced modulation used in the TPA2005D1 PWM output stage eliminates the need for an output filter.
9.2 Functional Block Diagram
Gain = 2 V/V
VDD
B4, C4
VDD
150 kW
IN− D1
_
+
+
_
Deglitch
Logic
Gate
Drive
+
_
Deglitch
Logic
Gate
Drive
A4
VO−
_
+
_
+
+
_
IN+ C1
150 kW
SHUTDOWN
†
A1
TTL
SD Input
Buffer
Biases
and
References
Ramp
Generator
Startup
& Thermal
Protection
Logic
D4
VO+
Short
Circuit
Detect
†
GND
A2, A3, B3, C2, C3, D2, D3
(terminal labels for MicroStar Junior™package)
9.3 Feature Description
9.3.1 Fully Differential Amplifier
The TPA2005D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The
common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless
of the common-mode voltage at the input. The fully differential TPA2005D1 can still be used with a single-ended
input; however, the TPA2005D1 should be used with differential inputs when in a noisy environment, like a
wireless handset, to ensure maximum noise rejection.
12
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Feature Description (continued)
9.3.1.1 Advantages of Fully Differential Amplifiers
• Input-coupling capacitors not required:
– The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. For example,
if a codec has a midsupply lower than the midsupply of the TPA2005D1, the common-mode feedback
circuit will adjust, and the TPA2005D1 outputs will still be biased at midsupply of the TPA2005D1. The
inputs of the TPA2005D1 can be biased from 0.5 V to VDD - 0.8 V. If the inputs are biased outside of that
range, input-coupling capacitors are required.
• Midsupply bypass capacitor, C(BYPASS), not required:
– The fully differential amplifier does not require a bypass capacitor. This is because any shift in the
midsupply affects both positive and negative channels equally and cancels at the differential output.
• Better RF-immunity:
– GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The
transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal
much better than the typical audio amplifier.
9.3.2 Efficiency and Thermal Information
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the 2,5-mm x 2,5-mm MicroStar Junior package is shown in the dissipation rating table. Converting this to θJA:
1
q
+
+ 1 + 62.5°CńW
JA
0.016
Derating Factor
(1)
Given θJA of 62.5°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal
dissipation of 0.2 W (worst case 5-V supply), the maximum ambient temperature can be calculated with equation
Equation 2.
T Max + T Max * q P
+ 150 * 62.5 (0.2) + 137.5°C
A
J
JA Dmax
(2)
Equation Equation 2 shows that the calculated maximum ambient temperature is 137.5°C at maximum power
dissipation with a 5-V supply; however, the maximum ambient temperature of the package is limited to 85°C.
Because of the efficiency of the TPA2005D1, it can be operated under all conditions to an ambient temperature
of 85°C. The TPA2005D1 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more resistive than 8-Ω
dramatically increases the thermal performance by reducing the output current and increasing the efficiency of
the amplifier.
9.3.3 Eliminating the Output Filter with the TPA2005D1
This section focuses on why the user can eliminate the output filter with the TPA2005D1.
9.3.3.1 Effect on Audio
The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.
9.3.3.2 Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA005Dxx family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VDD. Therefore,
the differential pre-filtered output varies between positive and negative VDD, where filtered 50% duty cycle yields
0 volts across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown
in Figure 33. Note that even at an average of 0 volts across the load (50% duty cycle), the current to the load is
high causing a high loss and thus causing a high supply current.
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Feature Description (continued)
OUT+
OUT–
+5 V
Differential Voltage
Across Load
0V
–5 V
Current
Figure 33. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With no Input
9.3.3.3 TPA2005D1 Modulation Scheme
The TPA2005D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUT+ and OUT- are now in phase with each other with no input. The duty cycle of OUT+ is greater
than 50% and OUT- is less than 50% for positive voltages. The duty cycle of OUT+ is less than 50% and OUT- is
greater than 50% for negative voltages. The voltage across the load sits at 0 volts throughout most of the
switching period greatly reducing the switching current, which reduces any I2R losses in the load.
OUT+
OUT–
Differential
Voltage
Across
Load
Output = 0 V
+5 V
0V
–5 V
Current
OUT+
OUT–
Differential
Voltage
Across
Load
Output > 0 V
+5 V
0V
–5 V
Current
Figure 34. The TPA2005D1 Output Voltage and Current Waveforms Into an Inductive Load
14
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Feature Description (continued)
9.3.3.4 Efficiency: Why You Must Use a Filter With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VDD and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA2005D1 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VDD instead of 2 × VDD. As the output power increases, the pulses widen making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker that results in less power
dissipated, which increases efficiency.
9.3.3.5 Effects of Applying a Square Wave Into a Speaker
If the amplitude of a square wave is high enough and the frequency of the square wave is within the bandwidth
of the speaker, a square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A
250-kHz switching frequency, however, is not significant because the speaker cone movement is proportional to
1/f2 for frequencies beyond the audio band. Therefore, the amount of cone movement at the switching frequency
is small. However, damage could occur to the speaker if the voice coil is not designed to handle the additional
power. To size the speaker for added power, the ripple current dissipated in the load needs to be calculated by
subtracting the theoretical supplied power, PSUP THEORETICAL, from the actual supply power, PSUP, at maximum
output power, POUT. The switching power dissipated in the speaker is the inverse of the measured efficiency,η
MEASURED, minus the theoretical efficiency,η THEORETICAL.
P
+P
–P
(at max output power)
SPKR
SUP SUP THEORETICAL
(3)
P
P
P
+ SUP – SUP THEORETICAL (at max output power)
SPKR
P
P
OUT
OUT
(4)
ǒ
Ǔ
1
1
(at max output power)
*
OUT h MEASURED h THEORETICAL
R
L
hTHEORETICAL +
(at max output power)
R ) 2r
L
DS(on)
P
SPKR
+P
(5)
(6)
The maximum efficiency of the TPA2005D1 with a 3.6 V supply and an 8-Ω load is 86% from equation
Equation 6. Using equation Equation 5 with the efficiency at maximum power (84%), we see that there is an
additional 17 mW dissipated in the speaker. The added power dissipated in the speaker is not an issue as long
as it is taken into account when choosing the speaker.
9.3.3.6 When to Use an Output Filter
Design the TPA2005D1 without an output filter if the traces from amplifier to speaker are short. The TPA2005D1
passed FCC and CE radiated emissions with no shielding with speaker trace wires 100 mm long or less.
Wireless handsets and PDAs are great applications for class-D without a filter.
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter, and the
frequency sensitive circuit is greater than 1 MHz. This is good for circuits that just have to pass FCC and CE
because FCC and CE only test radiated emissions greater than 30 MHz. If choosing a ferrite bead, choose one
with high impedance at high frequencies, but low impedance at low frequencies.
Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads
from amplifier to speaker.
Figure 35 and Figure 36 show typical ferrite bead and LC output filters.
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Feature Description (continued)
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 35. Typical Ferrite Chip Bead Filter (Chip bead example: NEC/Tokin: N2012ZPS121)
33 µH
OUTP
1 µF
33 µH
OUTN
1 µF
Figure 36. Typical LC Output Filter, Cutoff Frequency of 27 kHz
9.3.4 Thermal and Short-Circuit Protection
The TPA2005D1 features thermal and short-circuit protection. When the protection circuit is triggered, the device
will enter in shutdown mode, setting the outputs of the device into high impedance. Thermal protection turns the
device off when the junction temperature surpasses 150°C to prevent damage to the IC.
9.4 Device Functional Modes
9.4.1 Summing Input Signals with the TPA2005D1
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources
that need separate gain. The TPA2005D1 makes it easy to sum signals or use separate signal sources with
different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone
would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.
9.4.1.1 Summing Two Differential Input Signals
Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each input
source can be set independently (see equations Equation 7 and Equation 8, and Figure 37).
V
Gain 1 = O = 2 × 150 k V
V
R
V
(7)
I1
I1
V
Gain 2 = O = 2 × 150 k V
V
R
V
(8)
I2
I2
( )
()
If summing left and right inputs with a gain of 1 V/V, use RI1= RI2= 300 kΩ.
This configuration will use resistor values of RI1 = 3 MΩ, and RI2 = 150 kΩ
16
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Device Functional Modes (continued)
Differential
Input 1
+
RI1
–
RI1
+
RI2
To Battery
Internal
Oscillator
Differential
Input 2
RI2
CS
IN–
_
–
VDD
PWM
H–
Bridge
VO+
VO–
+
IN+
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Figure 37. Application Schematic With TPA2005D1 Summing Two Differential Inputs
9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
Figure 38 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended
input is set by CI2, shown in equation Equation 11. To assure that each input is balanced, the single-ended input
must be driven by a low-impedance source even if the input is not in use.
V
Gain 1 = O = 2 × 150 k V
V
R
V
(9)
I1
I1
V
Gain 2 = O = 2 × 150 k V
V
R
V
(10)
I2
I2
( )
()
CI2 =
1
(2p ´ RI2 ´ fc 2 )
(11)
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Device Functional Modes (continued)
If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring
tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is set
to gain 2 = 2 V/V, The resistor values are RI1 = 3 MΩ and RI2 = 150 kΩ.
The high pass corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less
than 20 Hz.
CI2 >
1
(2p ´ 150kW ´ 20Hz )
(12)
CI2 > 53nF
(13)
RI1
Differential
Input 1
Single-Ended
Input 2
RI1
CI2 R
I2
To Battery
Internal
Oscillator
CS
IN–
_
RI2
VDD
PWM
H–
Bridge
VO+
VO–
+
IN+
CI2
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Figure 38. Application Schematic With TPA2005D1 Summing Differential Input and
Single-Ended Input Signals
9.4.1.3 Summing Two Single-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently (see equations through Equation 17, and
Figure 39). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the INterminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not
outputting an ac signal.
V
Gain 1 = O = 2 × 150 k V
V
R
V
(14)
I1
I1
V
Gain 2 = O = 2 × 150 k V
V
R
V
(15)
I2
I2
( )
()
CI1 =
C2 =
1
(2p ´ RI1 ´ fc1 )
(16)
1
(2p ´ RI2 ´ fc 2 )
(17)
C +C ) C
P
I1
I2
R
R
I2
R + I1
P
R ) R
I1
I2
ǒ
18
(18)
Ǔ
(19)
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Device Functional Modes (continued)
Single-Ended
Input 1
Single-Ended
Input 2
CI1 R
I1
To Battery
CI2 R
I2
Internal
Oscillator
CS
IN–
_
RP
VDD
PWM
H–
Bridge
VO+
VO–
+
IN+
CP
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Figure 39. Application Schematic With TPA2005D1 Summing Two Single-Ended Inputs
9.4.2 Shutdown Mode
The TPA2005D1 can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW. While in
shutdown mode, the device output stage is turned off and set into high impedance, making the current
consumption very low. The device exits shutdown mode when a HIGH logic level is applied to SHUTDOWN pin.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device in several popular use cases.
Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible
modules allow full evaluation of the device in the most common modes of operation. Any design variation can be
supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the
audio amplifier discussion forum for additional information.
10.2 Typical Applications
These application circuits detail the recommended component selection and board configurations for the
TPA2005D1 device.
10.2.1 TPA2005D1 with Differential Input
To Battery
Internal
Oscillator
+
RI
–
RI
CS
IN–
_
Differential
Input
VDD
PWM
VO+
H–
Bridge
VO–
+
IN+
GND
SHUTDOWN
Bias
Circuitry
TPA2005D1
Filter-Free Class D
Figure 40. Typical TPA2005D1 Differential Input for a Wireless Phone
10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1.
Table 1. Design Requirements
PARAMETER
EXAMPLE
Power Supply
5V
High > 2 V
Shutdown Input
Low < 0.8 V
8Ω
Speaker
20
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10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Component Selection
Figure 40 shows the TPA2005D1 typical schematic with differential inputs and Figure 42 shows the TPA2005D1
with differential inputs and input capacitors, and Figure 43 shows the TPA2005D1 with single-ended inputs.
Differential inputs should be used whenever possible because the single-ended inputs are much more
susceptible to noise.
Table 2. Typical Component Values
REF DES
VALUE
EIA SIZE
MANUFACTURER
PART NUMBER
RI
150 kΩ (±0.5%)
0402
Panasonic
ERJ2RHD154V
CS
1 μF (+22%, -80%)
0402
Murata
GRP155F50J105Z
3.3 nF (±10%)
0201
Murata
GRP033B10J332K
CI
(1)
(1)
CI is only needed for single-ended input or if VICM is not between 0.5 V and VDD - 0.8 V. CI = 3.3 nF (with RI = 150 kΩ) gives a highpass corner frequency of 321 Hz.
10.2.1.2.2 Input Resistors (RI)
The input resistors (RI) set the gain of the amplifier according to equation Equation 20.
Gain = 2 × 150 k
R
I
(20)
Resistor matching is important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic
distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or
better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with
1% matching can be used with a tolerance greater than 1%.
Place the input resistors close to the TPA2005D1 to limit noise injection on the high-impedance nodes.
For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the TPA2005D1 to operate
at its best, and keeps a high voltage at the input making the inputs less susceptible to noise.
10.2.1.2.3 Decoupling Capacitor (CS)
The TPA2005D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1
μF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the
TPA2005D1 is important for the efficiency of the class-D amplifier, because any resistance or inductance in the
trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise
signals, a 10 μF or greater capacitor placed near the audio power amplifier would also help, but it is not required
in most applications because of the high PSRR of this device.
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10.2.1.3 Application Curves
1.6
RL = 8 W
f = 1 kHz
Gain = 2 V/V
PO - Output Power - W
1.4
1.2
1
THD+N = 10%
0.8
0.6
THD+N = 1%
0.4
0.2
0
2.5
3
3.5
4
4.5
5
VDD - Supply Voltage - V
Figure 41. Output Power vs Supply Voltage
10.2.2 TPA2005D1 with Differential Input and Input Capacitors
To Battery
CI
Differential
Input
Internal
Oscillator
RI
RI
CS
IN–
_
CI
VDD
PWM
H–
Bridge
VO+
VO–
+
IN+
GND
SHUTDOWN
Bias
Circuitry
TPA2005D1
Filter-Free Class D
Figure 42. TPA2005D1 Differential Input and Input Capacitors
10.2.2.1 Design Requirements
Please see Design Requirements.
10.2.2.2 Detailed Design Procedure
Please see Detailed Design Procedure.
10.2.2.2.1 Input Capacitors (CI)
The TPA2005D1 does not require input coupling capacitors if the design uses a differential source that is biased
from 0.5 V to VDD - 0.8 V (shown in Figure 40). If the input signal is not biased within the recommended
common-mode input range, if needing to use the input as a high pass filter (shown in Figure 42), or if using a
single-ended source (shown in Figure 43), input coupling capacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in
equation Equation 21.
fc =
1
(2p ´ RI ´ CI )
(21)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application.
22
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Equation Equation 22 is reconfigured to solve for the input coupling capacitance.
CI =
1
(2p ´ RI ´ fc )
(22)
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below, and
causes pop. Any capacitor in the audio path should have a rating of X7R or better.
For a flat low-frequency response, use large input coupling capacitors (1 μF). However, in a GSM phone the
ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation.
The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum.
10.2.3 TPA2005D1 with Single-Ended Input
To Battery
CI
Single-ended
Input
Internal
Oscillator
RI
CS
IN–
_
RI
VDD
PWM
H–
Bridge
VO+
VO–
+
IN+
CI
GND
SHUTDOWN
Bias
Circuitry
TPA2005D1
Filter-Free Class D
Figure 43. TPA2005D1 Single-Ended Input
10.2.3.1 Design Requirements
Please see Design Requirements.
10.2.3.2 Detailed Design Procedure
Please see Detailed Design Procedure.
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11 Power Supply Recommendations
The TPA2005D1 is designed to operate from an input voltage supply range between 2.5-V and 5.2-V. Therefore,
the output voltage range of power supply should be within this range and well regulated. The current capability of
upper power should not exceed the maximum current limit of the power switch.
11.1 Power Supply Decoupling Capacitors
The TPA2005D1 requires adequate power supply decoupling to ensure a high efficiency operation with low total
harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF,
within 2 mm of the VDD pin. This choice of capacitor and placement helps with higher frequency transients,
spikes, or digital hash on the line. In addition to the 0.1 μF ceramic capacitor, is recommended to place a 2.2 µF
to 10 µF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy
faster than the board supply, thus helping to prevent any droop in the supply voltage.
24
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12 Layout
12.1 Layout Guidelines
12.1.1 Component Location
Place all the external components close to the TPA2005D1. The input resistors need to be close to the
TPA2005D1 input pins so noise does not couple on the high impedance nodes between the input resistors and
the input amplifier of the TPA2005D1. Placing the decoupling capacitor, CS, close to the TPA2005D1 is important
for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device and the
capacitor can cause a loss in efficiency.
12.1.2 Trace Width
Make the high current traces going to pins VDD, GND, VO+ and VO- of the TPA2005D1 have a minimum width of
0,7 mm. If these traces are too thin, the TPA2005D1's performance and output power will decrease. The input
traces do not need to be wide, but do need to run side-by-side to enable common-mode noise cancellation.
12.1.3 MicroStar Junior™ BGA Specifications
Use the following MicroStar Junior BGA ball diameters:
• 0,25 mm diameter solder mask
• 0,28 mm diameter solder paste mask/stencil
• 0,38 mm diameter copper trace
Figure 44 shows how to lay out a board for the TPA2005D1 MicroStar Junior BGA.
0,28
mm
SD
0,38
mm
NC
0,25
mm
GND
GND
Vo−
GND
VDD
IN+
GND
GND
VDD
IN−
GND
GND
Vo+
Solder Mask
Paste Mask
Copper Trace
Figure 44. TPA2005D1 MicroStar Junior BGA Board Layout (Top View)
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12.2 Layout Examples
OUT SHUTDOWN
A1
A2
B1
IN +
IN
A3
A4
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
Decoupling capacitor
placed as close as
possible to the device
0.1µF
-
TPA2005D1
OUT +
Input Resistors
placed as close as
possible to the device
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Via to Power Supply
Via to Bottom Ground Plane
Figure 45. TPA2005D1 MicroStar Junior™ BGA Package Layout Example
Decoupling capacitor
placed as close as
possible to the device
1
8
2
7
IN +
3
6
-
4
5
SHUTDOWN
IN
OUT 0.1µF
OUT +
TPA2005D1
Input Resistors
placed as close as
possible to the device
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
Figure 46. TPA2005D1 DRB Package Layout Example
26
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Layout Examples (continued)
Decoupling capacitor
placed as close as
possible to the device
SHUTDOWN
1
8
2
7
IN +
3
6
-
4
5
IN
OUT 0.1µF
OUT +
TPA2005D1
Input Resistors
placed as close as
possible to the device
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
Figure 47. TPA2005D1 DGN Package Layout Example
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13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
MicroStar Junior, PowerPAD, E2E are trademarks of Texas Instruments.
is a trademark of ~ Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
28
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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29
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA2005D1DGN
ACTIVE
MSOPPowerPAD
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BAL
TPA2005D1DGNG4
ACTIVE
MSOPPowerPAD
DGN
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BAL
TPA2005D1DGNR
ACTIVE
MSOPPowerPAD
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BAL
TPA2005D1DGNRG4
ACTIVE
MSOPPowerPAD
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
BAL
TPA2005D1DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BIQ
TPA2005D1DRBRG4
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BIQ
TPA2005D1GQYR
ACTIVE
BGA
MICROSTAR
JUNIOR
GQY
15
2500
TBD
SNPB
Level-2-235C-1 YEAR
-40 to 85
PB051
TPA2005D1ZQYR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQY
15
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-2-260C-1 YEAR
-40 to 85
AAFI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Sep-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPA2005D1 :
• Automotive: TPA2005D1-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPA2005D1DGNR
MSOPPower
PAD
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TPA2005D1DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPA2005D1DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPA2005D1GQYR
BGA MI
CROSTA
R JUNI
OR
GQY
15
2500
330.0
8.4
2.8
2.8
1.25
4.0
8.0
Q1
TPA2005D1ZQYR
BGA MI
CROSTA
R JUNI
OR
ZQY
15
2500
330.0
8.4
2.8
2.8
1.25
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA2005D1DGNR
MSOP-PowerPAD
DGN
8
2500
364.0
364.0
27.0
TPA2005D1DRBR
SON
DRB
8
3000
367.0
367.0
35.0
TPA2005D1DRBR
SON
DRB
8
3000
367.0
367.0
35.0
TPA2005D1GQYR
BGA MICROSTAR
JUNIOR
GQY
15
2500
338.1
338.1
20.6
TPA2005D1ZQYR
BGA MICROSTAR
JUNIOR
ZQY
15
2500
338.1
338.1
20.6
Pack Materials-Page 2
MECHANICAL DATA
MPBG168B – SEPTEMBER 2000 – REVISED FEBRUARY 2002
GQY (S-PBGA-N15)
PLASTIC BALL GRID ARRAY
1,50 TYP
2,60
SQ
2,40
0,50
0,25
D
0,50
C
1,50 TYP
B
0,25
A
1
A1 Corner
2
3
4
Bottom View
0,77
0,71
1,00 MAX
Seating Plane
0,35
0,25
0,05 M
0,25
0,15
0,08
4201436/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar Junior configuration
Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
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