STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC

STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
STM32L15xCC STM32L15xRC
STM32L15xUC STM32L15xVC
Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3,
256KB Flash, 32KB SRAM, 8KB EEPROM, LCD, USB, ADC, DAC
Datasheet - production data
Features
• Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40 °C to 85 °C/105 °C temperature range
– 0.29μA Standby mode (3 wakeup pins)
– 1.15 μA Standby mode + RTC
– 0.44 μA Stop mode (16 wakeup lines)
– 1.4 μA Stop mode + RTC
– 8.6 μA Low-power Run mode
– 185 μA/MHz Run mode
– 10 nA ultra-low I/O leakage
– 8 μs wakeup time
• Core: ARM® Cortex®-M3 32-bit CPU
– From 32 kHz up to 32 MHz max
– 33.3 DMIPS peak (Dhrystone 2.1)
– Memory protection unit
• Reset and supply management
– Low power, ultrasafe BOR (brownout reset)
with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
• Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– High Speed Internal 16 MHz
factory-trimmed RC (+/- 1%)
– Internal Low Power 37 kHz RC
– Internal multispeed low power 65 kHz to
4.2 MHz PLL for CPU clock and USB
(48 MHz)
• Pre-programmed bootloader
– USB and USART supported
• Development support
– Serial wire debug supported
– JTAG and trace supported
• Up to 83 fast I/Os (70 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors
March 2014
This is information on a product in full production.
LQFP100 (14 × 14 mm)
LQFP64 (10 × 10 mm)
LQFP48 (7 x 7 mm)
UFBGA100
(7 x 7 mm)
WLCSP63
(0,400 mm
pitch)
UFQFPN48
(7x7 mm)
• Memories
– 256 KB Flash with ECC
– 32 KB RAM
– 8 KB of true EEPROM with ECC
– 128 Byte Backup Register
• LCD Driver for up to 8x40 segments
– Support contrast adjustment
– Support blinking mode
– Step-up converter on board
• Rich analog peripherals (down to 1.8 V)
– 2x Operational Amplifier
– 12-bit ADC 1Msps up to 25 channels
– 12-bit DAC 2 channels with output buffers
– 2x Ultra-low-power-comparators
(window mode and wake up capability)
• DMA controller 12x channels
• 9x peripherals communication interface
– 1x USB 2.0 (internal 48 MHz PLL)
– 3x USART
– 3x SPI 16 Mbits/s (2x SPI with I2S)
– 2x I2C (SMBus/PMBus)
• 11x timers: 1x 32-bit, 6x 16-bit with up to 4
IC/OC/PWM channels, 2x 16-bit basic timer, 2x
watchdog timers (independent and window)
• Up to 23 capacitive sensing channels
• CRC calculation unit, 96-bit unique ID
Table 1. Device summary
Reference
Part number
STM32L151CC
STM32L151RC(1)
STM32L151UC
STM32L151VC(1),
STM32L151CCT6,STM32L151CCU6
STM32L151RCT6
STM32L151UCY6
STM32L151VCT6,STM32L151VCH6
STM32L152CC
STM32L152RC(1)
STM32L152UC
STM32L152VC(1)
STM32L152CCT6,STM32L152CCU6
STM32L152RCT6
STM32L152UCY6
STM32L152VCT6,STM32L152VCH6
1.
For sales types ending with “A” and STM32L15xxC products
in WLCSP64 package, please refer to STM32L15xxC/D
datasheets
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Contents
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
2/133
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2
Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3
Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
ARM Cortex-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.4
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22
3.6
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8
DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9
LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10
ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11
DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.12
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.13
Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 26
3.14
System configuration controller and routing interface . . . . . . . . . . . . . . . 26
3.15
Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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3.16
3.17
Contents
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16.1
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16.2
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.3
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.4
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.5
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17.1
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17.2
Universal synchronous/asynchronous receiver transmitter (USART) . . 29
3.17.3
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.4
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.5
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 29
3.19
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.7
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.1.8
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.2
Embedded reset and power control block characteristics . . . . . . . . . . . 58
6.3.3
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.5
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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6.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.11
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.15
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.16
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.17
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.18
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.19
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.20
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.21
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.22
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.23
LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
7.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ultralow power STM32L15xxC device features and peripheral counts . . . . . . . . . . . . . . . 10
Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 15
Functionalities depending on the working mode (from Run/active down to
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VLCD rail decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STM32L15xxC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 58
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Current consumption in Run mode, code with data processing running from Flash. . . . . . 62
Current consumption in Run mode, code with data processing running from RAM . . . . . . 63
Current consumption in Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Current consumption in Low-power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 69
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Low-power mode wakeup timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 82
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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List of tables
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
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I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 92
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 112
LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 115
LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 118
UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm,
0.5 mm pitch package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid array package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
WLCSP63, 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . . 125
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
STM32L15xxC ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Ultra-low-power STM32L15xxC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM32L15xVC UFBGA100 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM32L15xVC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32L15xRC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32L15xUC WLCSP63 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32L15xCC UFQFPN48 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L15xCC LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 111
LQFP100 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LQFP100 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 114
LQFP64 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LQFP64 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 117
LQFP48 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LQFP48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
UFQFPN48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid array package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
WLCSP63, 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . . 124
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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7
Introduction
1
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L151xC and STM32L152xC ultra-low-power ARM® Cortex®-M3 based
microcontroller product line with a Flash memory of 256 Kbytes.
The ultra-low-power STM32L15xxC devices are available in 6 different package types: from
48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are
included, the description below gives an overview of the complete range of peripherals
proposed in this family.
These features make the ultra-low-power STM32L15xxC microcontroller family suitable for
a wide range of applications:
•
Medical and handheld equipment
•
Application control and user interface
•
PC peripherals, gaming, GPS and sport equipment
•
Alarm systems, wired and wireless sensors, Video intercom
•
Utility metering
This STM32L15xxC datasheet should be read in conjunction with the STM32L1xxxx
reference manual (RM0038). The document “Getting started with STM32L1xxx hardware
development” AN3216 gives a hardware implementation overview. Both documents are
available from the STMicroelectronics website www.st.com.
For information on the ARM® Cortex®-M3 core please refer to the ARM® Cortex®-M3
Technical Reference Manual, available from the www.arm.com website. Figure 1 shows the
general block diagram of the device family.
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2
Description
Description
The ultra-low-power STM32L15xxC incorporates the connectivity power of the universal
serial bus (USB) with the high-performance ARM® Cortex®-M3 32-bit RISC core operating
at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories
(Flash memory up to 256 Kbytes and RAM up to 32 Kbytes) and an extensive range of
enhanced I/Os and peripherals connected to two APB buses.
The STM32L15xxC devices offer two operational amplifiers, one 12-bit ADC, two DACs,
two ultra-low-power comparators, one general-purpose 32-bit timer, six general-purpose 16bit timers and two basic timers, which can be used as time bases.
Moreover, the STM32L15xxC devices contain standard and advanced communication
interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs and a USB. The
STM32L15xxC devices offer up to 23 capacitive sensing channels to simply add touch
sensing functionality to any application.
They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller has a built-in LCD voltage generator that allows you to
drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.
The ultra-low-power STM32L15xxC operate from a 1.8 to 3.6 V power supply (down to
1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option.
It is available in the -40 to +85 °C temperature range, extended to 105°C in low-power
dissipation state. A comprehensive set of power-saving modes allows the design of lowpower applications.
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51
Description
2.1
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Device overview
Table 2. Ultralow power STM32L15xxC device features and peripheral counts
Peripheral
STM32L15xCC
STM32L15xUC
STM32L15xRC
Flash (Kbytes)
256
Data EEPROM (Kbytes)
8
RAM (Kbytes)
32
Timers
32 bit
1
Generalpurpose
6
Basic
2
3/(2)
SPI/(I2S)
Communica
tion interfaces
I2C
2
USART
3
USB
1
GPIOs
37
51
Operation amplifiers
12-bit synchronized ADC
Number of channels
LCD (1)
COM x SEG
1
14
1
21
1
4x18
Operating temperatures
Packages
1
1
4x32 or 8x28
4x44 or 8x40
2
16
23
Max. CPU frequency
Operating voltage
1
25
2
2
Comparators
Capacitive sensing channels
83
2
12-bit DAC
Number of channels
32 MHz
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Ambient temperature: –40 to +85 °C
Junction temperature: –40 to + 105 °C
LQFP48,
UFQFPN48
1. STM32L152xx devices only.
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LQFP64,
WLCSP63
LQFP100,
UFBGA100
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
2.2
Description
Ultra-low-power device continuum
The ultra-low-power family offers a large choice of cores and features. From proprietary 8bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to
answer your needs, in terms of ultra-low-power features. The STM32 Ultra-low-power series
are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and healthcare,
wearable applications. Several built-in features like LCD drivers, dual-bank
memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many
others will clearly allow you to build very cost-optimized applications by reducing BOM.
Note:
STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible
the pin-to-pin compatibility between any STM8Lx and STM32Lx devices and between any of
the STM32Lx and STM32Fx series. Thanks to this unprecedented scalability, your old
applications can be upgraded to respond to the latest market features and efficiency
demand.
2.2.1
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for
STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2
Shared peripherals
STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a
very easy migration from one family to another:
•
Analog peripherals: ADC, DAC and comparators
•
Digital peripherals: RTC and some communication interfaces
2.2.3
Common system strategy
To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and
STM32L162xx families use a common architecture:
•
Same power supply range from 1.65 V to 3.6 V
•
Architecture optimized to reach ultra-low consumption both in low-power modes and
Run mode
•
Fast startup strategy from low-power modes
•
Flexible system clock
•
Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector
2.2.4
Features
ST ultra-low-power continuum also lies in feature compatibility:
•
More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
•
Memory density ranging from 2 to Kbytes
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Functional overview
3
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Functional overview
Figure 1. Ultra-low-power STM32L15xxC block diagram
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
3.1
Functional overview
Low-power modes
The ultra-low-power STM32L15xxC supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the internal low-drop regulator that supplies the
logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply.
There are three power consumption ranges:
•
Range 1 (VDD range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz
•
Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz
•
Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated
only with the multispeed internal RC oscillator clock source)
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
•
Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the
minimum clock (131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In Lowpower run mode, the clock frequency and the number of enabled peripherals are both
limited.
•
Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low power mode to minimize the regulator’s operating current. In Low power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
•
Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 μs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.
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Functional overview
•
•
•
Note:
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 μs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 μs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 μs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
Table 3. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply range
Operating power supply
range
DAC and ADC
operation
USB
Dynamic voltage
scaling range
I/O operation
VDD= VDDA = 1.65 to 1.71 V
Not functional
Not functional
Range 2 or
Range 3
Degraded speed
performance
Not functional
Not functional
Range 1, Range 2
or Range 3
Degraded speed
performance
Conversion time up
to 500 Ksps
Not functional
Range 1, Range 2
or
Range 3
Degraded speed
performance
VDD=VDDA= 1.71 to 1.8 V(1)
VDD=VDDA= 1.8 to 2.0 V(1)
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Functional overview
Table 3. Functionalities depending on the operating power supply range (continued)
Functionalities depending on the operating power supply range
Operating power supply
range
DAC and ADC
operation
USB
Dynamic voltage
scaling range
I/O operation
VDD=VDDA = 2.0 to 2.4 V
Conversion time up
to 500 Ksps
Functional(2)
Range 1, Range 2
or Range 3
Full speed operation
VDD=VDDA = 2.4 to 3.6 V
Conversion time up
to 1 Msps
Functional(2)
Range 1, Range 2
or Range 3
Full speed operation
1. CPU frequency changes from initial to final must respect “FCPU initial < 4*FCPU final” to limit VCORE drop due to current
consumption peak when frequency increases. It must also respect 5 μs delay between two changes. For example to switch
from 4.2 MHz to 32 MHz, you can switch from 4.2 MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.
2. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V.
Table 4. CPU frequency range depending on dynamic voltage scaling
CPU frequency range
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
Range 2
2.1MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws)
Range 3
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Functional overview
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 5. Functionalities depending on the working mode (from Run/active down to
standby)
Lowpower
Sleep
Stop
Standby
Run/Active
Sleep
Lowpower
Run
CPU
Y
--
Y
--
--
--
--
--
Flash
Y
Y
Y
Y
--
--
--
--
RAM
Y
Y
Y
Y
Y
--
--
--
Backup Registers
Y
Y
Y
Y
Y
--
Y
--
EEPROM
Y
Y
Y
Y
Y
--
--
--
Brown-out rest
(BOR)
Y
Y
Y
Y
Y
Y
Y
--
DMA
Y
Y
Y
Y
--
--
--
--
Programmable
Voltage Detector
(PVD)
Y
Y
Y
Y
Y
Y
Y
--
Power On Reset
(POR)
Y
Y
Y
Y
Y
Y
Y
--
Power Down Rest
(PDR)
Y
Y
Y
Y
Y
--
Y
--
High Speed
Internal (HSI)
Y
Y
--
--
--
--
--
--
High Speed
External (HSE)
Y
Y
--
--
--
--
--
--
Low Speed Internal
(LSI)
Y
Y
Y
Y
Y
--
--
--
Low Speed
External (LSE)
Y
Y
Y
Y
Y
--
--
--
Multi-Speed
Internal (MSI)
Y
Y
Y
Y
--
--
--
--
Inter-Connect
Controller
Y
Y
Y
Y
--
--
--
--
RTC
Y
Y
Y
Y
Y
Y
Y
--
RTC Tamper
Y
Y
Y
Y
Y
Y
Y
Y
Auto WakeUp
(AWU)
Y
Y
Y
Y
Y
Y
Y
Y
LCD
Y
Y
Y
Y
Y
--
--
--
USB
Y
Y
--
--
--
Y
--
--
--
--
Ips
Wakeup
capability
Wakeup
capability
USART
Y
Y
Y
Y
Y
(1)
SPI
Y
Y
Y
Y
--
--
--
--
I2C
Y
Y
Y
Y
--
(1)
--
--
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Functional overview
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) (continued)
Lowpower
Sleep
Stop
Standby
Run/Active
Sleep
Lowpower
Run
ADC
Y
Y
--
--
--
--
--
--
DAC
Y
Y
Y
Y
Y
--
--
--
Tempsensor
Y
Y
Y
Y
Y
--
--
--
OP amp
Y
Y
Y
Y
Y
--
--
--
Comparators
Y
Y
Y
Y
Y
Y
--
--
16-bit and 32-bit
Timers
Y
Y
Y
Y
--
--
--
--
IWDG
Y
Y
Y
Y
Y
Y
Y
Y
WWDG
Y
Y
Y
Y
--
--
--
--
Touch sensing
Y
Y
--
--
--
--
--
--
Systic Timer
Y
Y
Y
Y
--
--
--
GPIOs
Y
Y
Y
Y
Y
--
3 pins
0 μs
0.4 μs
3 μs
46 μs
Ips
Wakeup time to
Run mode
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to
185 μA/MHz
(from Flash)
Down to
34.5 μA/MHz
(from Flash)
Down to
8.6 μA
Down to
4.4 μA
Wakeup
capability
Y
Wakeup
capability
< 8 μs
58 μs
0.43 μA
(no RTC)
VDD=1.8V
0.29 μA
(no RTC)
VDD=1.8V
1.15 μA
(with RTC)
VDD=1.8V
0.9 μA
(with RTC)
VDD=1.8V
0.44 μA
(no RTC)
VDD=3.0V
0.29 μA
(no RTC)
VDD=3.0V
1.4 μA
(with RTC)
VDD=3.0V
1.15 μA
(with RTC)
VDD=3.0V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
3.2
ARM Cortex-M3 core with MPU
The ARM Cortex-M3 processor is the industry leading processor for embedded systems. It
has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an ARM core in the memory size usually associated
with 8- and 16-bit devices.
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Functional overview
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L15xxC is compatible with all ARM tools and
software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L15xxC embeds a nested vectored interrupt controller able to
handle up to 53 maskable interrupt channels (not including the 16 interrupt lines of ARM
Cortex-M3) and 16 priority levels.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support for tail-chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3
Reset and supply management
3.3.1
Power supply schemes
•
•
3.3.2
VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA
and VSSA must be connected to VDD and VSS, respectively.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
•
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
•
The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Functional overview
power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note:
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3
Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR) and power down.
•
MR is used in Run mode (nominal regulation)
•
LPR is used in the Low-power run, Low-power sleep and Stop modes
•
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).
3.3.4
Boot modes
At startup, boot pins are used to select one of three boot options:
•
Boot from Flash memory
•
Boot from System memory
•
Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1, USART2 or USB. See STM32™ microcontroller system memory boot mode
AN2606 for details.
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51
Functional overview
3.4
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
•
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•
System clock source: three different clock sources can be used to drive the master
clock SYSCLK:
–
1-24 MHz high-speed external crystal (HSE), that can supply a PLL
–
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
•
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
–
32.768 kHz low-speed external crystal (LSE)
–
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
•
•
•
•
•
RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Functional overview
Figure 2. Clock tree
3TANDBYSUPPLIEDVOLTAGEDOMAIN
ENABLE
7ATCHDOG
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7ATCHDOG
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,3)TEMPO
24#ENABLE
24#
,3%TEMPO
,3%/3#
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,3 ,3
,3
6$$#/2%
-(Z
,#$ENABLE
6
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LEVELSHIFTERS
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CK?LSI
CK?LSE
#+?,#$
-#/
NOTDEEPSLEEP
#+?072
6
NOTDEEPSLEEP
(3)2#
NOTSLEEPOR
DEEPSLEEP
LEVELSHIFTERS
6$$#/2%
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CLOCK
6
(3%
/3#
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CK?HSI
CK?HSE
LEVELSHIFTERS
6$$#/2%
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,3
6
-(ZCLOCK
DETECTOR
NOTSLEEPOR
DEEPSLEEP
!("
PRESCALER
6 CK?PLL
0,,
8
#+?&#,+
#+?#05
#+?4)-393
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!0"
PRESCALER PRESCALER
,3
#+?53"
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#LOCK
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USBENANDNOTDEEPSLEEP
CK?USB6CO6COMUSTBEAT-(Z
#+?4)-4'/
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TIMERENANDNOTDEEPSLEEP
APBPERIPHENANDNOTDEEPSLEEP
IF!0"PRESCX
X
ELSE
APBPERIPHENANDNOTDEEPSLEEP
-36
1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
24 MHz or 32 MHz.
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51
Functional overview
3.5
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Low-power real-time clock and backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD
(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the
month are made automatically. The RTC provides two programmable alarms and
programmable periodic interrupts with wakeup from Stop and Standby modes.
The programmable wakeup time ranges from 120 μs to 36 hours.
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
The RTC can also be automatically corrected with a 50/60Hz stable powerline.
The RTC calendar can be updated on the fly down to sub second precision, which enables
network system synchronization.
A time stamp can record an external event occurrence, and generates an interrupt.
There are thirty-two 32-bit backup registers provided to store 128 bytes of user application
data. They are cleared in case of tamper detection.
Three pins can be used to detect tamper events. A change on one of these pins can reset
backup register and generate an interrupt. To prevent false tamper event, like ESD event,
these three tamper inputs can be digitally filtered.
3.6
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected
to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB,
comparator events or capacitive sensing acquisition.
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
3.7
Functional overview
Memories
The STM32L15xxC devices have the following features:
•
32 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
The non-volatile memory is divided into three arrays:
–
256 Kbytes of embedded Flash program memory
–
8 Kbytes of data EEPROM
–
Options bytes
The options bytes are used to write-protect or read-out protect the memory (with 4 KB
granularity) and/or readout-protect the whole memory with the following options:
–
Level 0: no readout protection
–
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial
wire) and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
The user area of the Flash memory can be protected against Dbus read access by
PCROP feature (see RM0038 for details).
3.8
DMA (direct memory access)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.
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Functional overview
3.9
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
LCD (liquid crystal display)
The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
•
Internal step-up converter to guarantee functionality and contrast control irrespective of
VDD. This converter can be deactivated, in which case the VLCD pin is used to provide
the voltage to the LCD
•
Supports static, 1/2, 1/3, 1/4 and 1/8 duty
•
Supports static, 1/2, 1/3 and 1/4 bias
•
Phase inversion to reduce power consumption and EMI
•
Up to 8 pixels can be programmed to blink
•
Unneeded segments and common pins can be used as general I/O pins
•
LCD RAM can be updated at any time owing to a double-buffer
•
The LCD controller can operate in Stop mode
•
VLCD rail decoupling capability
Table 6. VLCD rail decoupling
Bias
Pin
3.10
1/2
1/3
1/4
VLCDRAIL1
1/2 VLCD
2/3 VLCD
1/2 VLCD
PB2
VLCDRAIL2
N/A
1/3 VLCD
1/4 VLCD
PB12
PE11
VLCDRAIL3
N/A
N/A
3/4 VLCD
PB0
PE12
ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L15xxC devices with up to 25
external channels, performing conversions in single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs with up to 24
external channels in a group
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
An injection mode allows high priority conversions to be done by interrupting a scan mode
which runs in as a background task.
The ADC includes a specific low-power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
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3.10.1
Functional overview
Temperature sensor
The temperature sensor (TSENSE) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode. See Table 61:
Temperature sensor calibration values on page 116.
3.10.2
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value (when no external voltage, VREF+, is
available for ADC). The precise voltage of VREFINT is individually measured for each part by
ST during production test and stored in the system memory area. It is accessible in readonly mode. See Table 16: Embedded internal reference voltage calibration values on page
61.
3.11
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
•
Two DAC converters: one for each output channel
•
Up to 10-bit output
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
•
Dual DAC channels, independent or simultaneous conversions
•
DMA capability for each channel (including the underrun interrupt)
•
External triggers for conversion
•
Input reference voltage VREF+
Eight DAC trigger inputs are used in the STM32L15xxC. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA channels.
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Functional overview
3.12
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Operational amplifier
The STM32L15xxC embeds two operational amplifiers with external or internal follower
routing capability (or even amplifier and filter capability with external components). When
one operational amplifier is selected, one external ADC channel is used to enable output
measurement.
The operational amplifiers feature:
•
Low input bias current
•
Low offset voltage
•
Low-power mode
•
Rail-to-rail input
3.13
Ultra-low-power comparators and reference voltage
The STM32L15xxC embeds two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
•
One comparator with fixed threshold
•
One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
–
DAC output
–
External I/O
–
Internal reference voltage (VREFINT) or a sub-multiple (1/4, 1/2, 3/4)
Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 μA typical).
3.14
System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of
internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage
VREFINT.
3.15
Touch sensing
The STM32L15xxC devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 23 capacitive sensing channels
distributed over 10 analog I/O groups. Both software and timer capacitive sensing
acquisition modes are supported.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
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Functional overview
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. The capacitive sensing acquisition only requires few external components to
operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups
(see Section 3.14: System configuration controller and routing interface).
Reliable touch sensing functionality can be quickly and easily implemented using the free
STM32L1xx STMTouch touch sensing firmware library.
3.16
Timers and watchdogs
The ultra-low-power STM32L15xxC devices include seven general-purpose timers, two
basic timers, and two watchdog timers.
Table 7 compares the features of the general-purpose and basic timers.
Table 7. Timer feature comparison
DMA
Capture/compare Complementary
request
channels
outputs
generation
Timer
Counter
resolution
Counter type
Prescaler factor
TIM2,
TIM3,
TIM4
16-bit
Up, down,
up/down
Any integer between
1 and 65536
Yes
4
No
TIM5
32-bit
Up, down,
up/down
Any integer between
1 and 65536
Yes
4
No
TIM9
16-bit
Up, down,
up/down
Any integer between
1 and 65536
No
2
No
TIM10,
TIM11
16-bit
Up
Any integer between
1 and 65536
No
1
No
TIM6,
TIM7
16-bit
Up
Any integer between
1 and 65536
Yes
0
No
3.16.1
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11)
There are seven synchronizable general-purpose timers embedded in the STM32L15xxC
devices (see Table 7 for differences).
TIM2, TIM3, TIM4, TIM5
TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four
independent channels each for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input captures/output compares/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10,
TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or
event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs.
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM10, TIM11 and TIM9
TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit
auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one
independent channel, whereas TIM9 has two independent channels for input capture/output
compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3,
TIM4, TIM5 full-featured general-purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.16.2
Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.16.3
SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.
3.16.4
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
3.16.5
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.17
Communication interfaces
3.17.1
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
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3.17.2
Functional overview
Universal synchronous/asynchronous receiver transmitter (USART)
The three USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They
support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability.
The three USARTs provide hardware management of the CTS and RTS signals.
All USART interfaces can be served by the DMA controller.
3.17.3
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPIs can be served by the DMA controller.
3.17.4
Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can
operate in master or slave mode, and can be configured to operate with a 16-/32-bit
resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192
kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
The I2Ss can be served by the DMA controller.
3.17.5
Universal serial bus (USB)
The STM32L15xxC embeds a USB device peripheral compatible with the USB full-speed
12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function interface. It has
software-configurable endpoint setting and supports suspend/resume. The dedicated
48 MHz clock is generated from the internal main PLL (the clock source must use a HSE
crystal oscillator).
3.18
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.19
Development support
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
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Functional overview
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a
specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.
The JTAG port can be permanently disabled with a JTAG fuse.
Embedded Trace Macrocell™
The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L15xxC through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer running debugger software. TPA
hardware is commercially available from common development tool vendors. It operates
with third party debugger software tools.
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4
Pin descriptions
Pin descriptions
Figure 3. STM32L15xVC UFBGA100 ballout
2
1
3
4
5
6
7
8
9
10
11
12
A
PE3
PE1
PB8
BOOT0
PD7
PD5
PB4
PB3
PA15
PA14
PA13
PA12
B
PE4
PE2
PB9
PB7
PB6
PD6
PD4
PD3
PD1
PC12
PC10
PA11
PC13
PE5
RTC_AF1
WKUP2
PE0
PD2
PD0
PC11
PH2
PA10
VSS_3
PC14
PE6
OSC32_IN WUKP3
PA9
PA8
PC9
VSS_4
PC8
PC7
PC6
VSS_2
VSS_1
VDD_2
VDD_1
C
D
E
PC15
VLCD
OSC32_OUT
VDD_3
PB5
F
PH0
OSC_IN
G
PH1
VDD_5
OSC_OUT
H
PC0
NRST
VDD_4
PD15
PD14
PD13
J
VSSA
PC1
PC2
PD12
PD11
PD10
K
VREF-
PC3
PA2
PA5
PC4
L
VREF+
PA0
WKUP1
PA3
PA6
PC5
PB2
M
VDDA
PA1
PA4
PA7
PB0
PB1
VSS_5
PD9
PD8
PB15
PB14
PB13
PE8
PE10
PE12
PB10
PB11
PB12
PE7
PE9
PE11
PE14
PE15
PE13
ai17096d
1. This figure shows the package top view
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51
Pin descriptions
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
6$$?
633?
0%
0%
0"
0"
"//4
0"
0"
0"
0"
0"
0$
0$
0$
0$
0$
0$
0$
0$
0#
0#
0#
0!
0!
Figure 4. STM32L15xVC LQFP100 pinout
,1&0
6$$?
633?
0(
0! 0!
0!
0!
0!
0!
0#
0#
0#
0#
0$
0$
0$
0$
0$
0$
0$
0$
0"
0"
0"
0"
0!
633?
6$$?
0!
0!
0!
0!
0#
0#
0"
0"
0"
0%
0%
0%
0%
0%
0%
0%
0%
0%
0"
0"
633?
6$$?
0%
0%
0%
0%
0%7+50
6,#$
0#7+50
0#/3#?).
0#/3#?/54
633?
6$$?
0(/3#?).
0(/3#?/54
.234
0#
0#
0#
0#
633!
62%&
62%&
6$$!
0!7+50
0!
0!
1. This figure shows the package top view
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Pin descriptions
6$$?
633?
0"
0"
"//4
0"
0"
0"
0"
0"
0$
0#
0#
0#
0!
0!
Figure 5. STM32L15xRC LQFP64 pinout
,1&0
6$$?
633? 0!
0!
0!
0!
0!
0!
0#
0#
0#
0#
0"
0"
0"
0"
0!
633?
6$$?
0!
0!
0!
0!
0#
0#
0"
0"
0"
0"
0"
633?
6$$?
6,#$
0#7+50
0#/3#?).
0#/3#?/54
0(/3#?).
0(/3#?/54
.234
0#
0#
0#
0#
633!
6$$!
0!7+50
0!
0!
AIC
1. This figure shows the package top view.
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51
Pin descriptions
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Figure 6. STM32L15xUC WLCSP63 ballout
!
633?
0!
0#
0$
0"
"//4
633?
"
0!
6$$?
0#
0#
0"
0"
6$$?
#
0!
0!
0!
0"
0"
0"
6,#$
$
0#
0!
0!
0"
0#
0#
0#
0#
0#
0!
0!
0#
0#
.234
0#
0"
0"
0#
633!
0(
0(
0"
0"
0"
0!
0!
0#
0#
(
6$$?
0"
0"
0!
633
0!
6$$!
*
633?
0"
0"
0#
0!
0!
0!
%
&
'
-36
1. This figure shows the package top view.
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Pin descriptions
0!
6$$?
0#7+50
633?
0#/3#?).
0!
0#/3#?/54
0!
0(/3#?).
0!
0(/3#?/54
0!
.234
0!
633!
0!
6$$!
0"
0!7+50
0"
0!
0!
0"
0"
633?
0!
0"
0"
0"
0"
0"
0"
0"
0"
0!
0"
"//4
0"
0!
0"
0!
633?
0!
6,#$
0!
6$$?
Figure 7. STM32L15xCC UFQFPN48 pinout
6$$?
0"
5&1&0.
AID
1. This figure shows the package top view.
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51
Pin descriptions
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
VDD_3
VSS_3
PB
PB8
BOO 0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
Figure 8. STM32L15xCC LQFP48 pinout
1
2
3
4
5
6
7
8
48 47 46 45 44 43 42 41 40 3 38 37
36
LQFP48
10
11
12
13 14 15 16 17 18 1 20 21 22 23 24
35
34
33
32
31
30
2
28
27
26
25
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA
PA8
PB15
PB14
PB13
PB12
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VLCD
PC13 R C_AF1 K P2
PC14 OSC32_IN
PC15 OSC32_O
PH0 OSC_IN
PH1 OSC_O
NRS
VSSA
VDDA
PA0 K P1
PA1
PA2
ai156 4b
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Pin descriptions
Table 8. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
I/O structure
Notes
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TC
Standard 3.3 V I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions Additional
Functions directly selected/enabled through peripheral registers
functions
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Pin descriptions
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 9. STM32L15xxC pin definitions
UFBGA100
LQFP100
LQFP64
WLCSP63
LQFP48 or UFQFPN48
Pin type(1)
I / O Structure
Pins
Main
function(2)
(after
reset)
B2
1
-
-
-
PE2
I/O
FT
PE2
TIM3_ETR/LCD_SEG38/
TRACECLK
A1
2
-
-
-
PE3
I/O
FT
PE3
TIM3_CH1/LCD_SEG39/
TRACED0
B1
3
-
-
-
PE4
I/O
FT
PE4
TIM3_CH2/TRACED1
C2
4
-
-
-
PE5
I/O
FT
PE5
TIM9_CH1/TRACED2
D2
5
-
-
-
PE6WKUP3
I/O
FT
PE6
WKUP3/RTC_TAMP3/
TIM9_CH2/TRACED3
E2
6
1
C7
1
VLCD(3)
S
C1
7
2
D5
2
PC13-WKUP2
I/O
FT
PC13
WKUP2/RTC_TAMP1/RTC_TS/
RTC_OUT
D1
8
3
D7
3
PC14OSC32_IN(4)
I/O
TC
PC14
OSC32_IN
E1
9
4
D6
4
PC15OSC32_OUT
I/O
TC
PC15
OSC32_OUT
F2
10
-
-
-
VSS_5
S
VSS_5
G2
11
-
-
-
VDD_5
S
VDD_5
F1
12
5
F6
5
PH0-OSC_IN(5)
I/O
TC
PH0
OSC_IN
G1
13
6
F7
6
PH1-OSC_OUT(5)
I/O
TC
PH1
OSC_OUT
H2
14
7
E7
7
NRST
H1
15
8
E6
-
PC0
I/O
FT
PC0
LCD_SEG18/ADC_IN10/
COMP1_INP
J2
16
9
E5
-
PC1
I/O
FT
PC1
LCD_SEG19/ADC_IN11/
COMP1_INP
J3
17
10 G7
-
PC2
I/O
FT
PC2
LCD_SEG20/ADC_IN12/
COMP1_INP
K2
18
11 G6
-
PC3
I/O
TC
PC3
LCD_SEG21/ADC_IN13/
COMP1_INP
J1
19
12 F5
8
VSSA
S
38/133
Pin name
Alternate functions
VLCD
I/O RST
NRST
VSSA
DocID022799 Rev 7
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Pin descriptions
Table 9. STM32L15xxC pin definitions (continued)
LQFP64
WLCSP63
LQFP48 or UFQFPN48
20
-
-
-
VREF-
S
VREF-
L1
21
-
-
-
VREF+
S
VREF+
M1
22
9
VDDA
S
VDDA
L2
M2
K3
23
24
25
13 H7
14 E4 10
15 G5 11
16 H6 12
L3
26
17 J7
E3
27
18
H3
28
19
M3
29
20 J6
K4
30
L4
31
PA0-WKUP1
PA1
PA2
I/O
I/O
I/O
I / O Structure
LQFP100
K1
Pin name
Pin type(1)
UFBGA100
Pins
FT
FT
FT
Main
function(2)
(after
reset)
Alternate functions
PA0
WKUP1/RTC_TAMP2/
TIM2_CH1_ETR/TIM5_CH1/
USART2_CTS/ADC_IN0/
COMP1_INP
PA1
TIM2_CH2/TIM5_CH2/
USART2_RTS/LCD_SEG0/
ADC_IN1/COMP1_INP/
OPAMP1_VINP
PA2
TIM2_CH3/TIM5_CH3/
TIM9_CH1/USART2_TX/
LCD_SEG1/ADC_IN2/
COMP1_INP/OPAMP1_VINM
PA3
TIM2_CH4/TIM5_CH4/
TIM9_CH2/USART2_RX/
LCD_SEG2/ADC_IN3/
COMP1_INP/OPAMP1_VOUT
13
PA3
I/O
-
-
VSS_4
S
VSS_4
-
-
VDD_4
S
VDD_4
14
PA4
I/O
TC
PA4
SPI1_NSS/SPI3_NSS/I2S3_WS/
USART2_CK/ADC_IN4/
DAC_OUT1/COMP1_INP
21 H4 15
PA5
I/O
TC
PA5
TIM2_CH1_ETR/SPI1_SCK/
ADC_IN5/DAC_OUT2/
COMP1_INP
PA6
TIM3_CH1/TIM10_CH1/
SPI1_MISO/LCD_SEG3/
ADC_IN6/COMP1_INP/
OPAMP2_VINP
22 G4 16
PA6
I/O
TC
FT
DocID022799 Rev 7
39/133
51
Pin descriptions
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 9. STM32L15xxC pin definitions (continued)
I / O Structure
Pin name
Pin type(1)
LQFP48 or UFQFPN48
WLCSP63
LQFP64
LQFP100
UFBGA100
Pins
Main
function(2)
(after
reset)
Alternate functions
M4
32
23 J5
17
PA7
I/O
FT
PA7
TIM3_CH2/TIM11_CH1/
SPI1_MOSI/LCD_SEG4/
ADC_IN7/COMP1_INP/
OPAMP2_VINM
K5
33
24 F4
-
PC4
I/O
FT
PC4
LCD_SEG22/ADC_IN14/
COMP1_INP
L5
34
25 J4
-
PC5
I/O
FT
PC5
LCD_SEG23/ADC_IN15/
COMP1_INP
M5
35
26 J3
18
PB0
I/O
TC
PB0
TIM3_CH3/LCD_SEG5/ADC_IN8
/COMP1_INP/VREF_OUT/
OPAMP2_VOUT/VLCDRAIL3
M6
36
27 H3 19
PB1
I/O
FT
PB1
TIM3_CH4/LCD_SEG6/
ADC_IN9/COMP1_INP/
VREF_OUT
L6
37
28 G3 20
PB2
I/O
FT
PB2
/BOOT1
COMP1_INP/VLCDRAIL1/ADCIN0b
M7
38
-
-
-
PE7
I/O
TC
PE7
ADC_IN22/COMP1_INP
L7
39
-
-
-
PE8
I/O
TC
PE8
ADC_IN23/COMP1_INP
M8
40
-
-
-
PE9
TC
PE9
TIM2_CH1_ETR/ADC_IN24/
COMP1_INP/TIM5_ETR
L8
41
-
-
-
PE10
I/O
TC
PE10
TIM2_CH2/ADC_IN25/
COMP1_INP
M9
42
-
-
-
PE11
I/O
FT
PE11
TIM2_CH3/VLCDRAIL2
L9
43
-
-
-
PE12
I/O
FT
PE12
TIM2_CH4/SPI1_NSS/VLCDRAIL3
M10
44
-
-
-
PE13
I/O
FT
PE13
SPI1_SCK
M11
45
-
-
-
PE14
I/O
FT
PE14
SPI1_MISO
M12
46
-
-
-
PE15
I/O
FT
PE15
SPI1_MOSI
L10
47
21
PB10
I/O
FT
PB10
TIM2_CH3/I2C2_SCL/
USART3_TX/LCD_SEG10
40/133
29 J2
DocID022799 Rev 7
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Pin descriptions
Table 9. STM32L15xxC pin definitions (continued)
I / O Structure
I/O
FT
PB11
-
VSS
S
VSS
L11
48
30 H2 22
-
-
F12
49
31 J1
23
VSS_1
S
VSS_1
G12
50
32 H1 24
VDD_1
S
VDD_1
-
WLCSP63
LQFP64
PB11
LQFP100
Main
function(2)
(after
reset)
UFBGA100
Pin name
Pin type(1)
LQFP48 or UFQFPN48
Pins
H5
Alternate functions
TIM2_CH4/I2C2_SDA/
USART3_RX/LCD_SEG11
L12
51
33 G2 25
PB12
I/O
FT
PB12
TIM10_CH1/I2C2_SMBA/
SPI2_NSS/I2S2_WS/
USART3_CK/LCD_SEG12/
ADC_IN18/COMP1_INP/VLCDRAIL2
K12
52
34 G1 26
PB13
I/O
FT
PB13
TIM9_CH1/SPI2_SCK/ I2S2_CK/
USART3_CTS/LCD_SEG13/
ADC_IN19/COMP1_INP
K11
53
35 F3
PB14
I/O
FT
PB14
TIM9_CH2/SPI2_MISO/
USART3_RTS/LCD_SEG14/
ADC_IN20/COMP1_INP
27
28
PB15
I/O
FT
PB15
TIM11_CH1/SPI2_MOSI/
I2S2_SD/LCD_SEG15/
ADC_IN21/COMP1_INP/
RTC_REFIN
-
-
PD8
I/O
FT
PD8
USART3_TX/LCD_SEG28
-
-
-
PD9
I/O
FT
PD9
USART3_RX/LCD_SEG29
57
-
-
-
PD10
I/O
FT
PD10
USART3_CK/LCD_SEG30
J11
58
-
-
-
PD11
I/O
FT
PD11
USART3_CTS/LCD_SEG31
J10
59
-
-
-
PD12
I/O
FT
PD12
TIM4_CH1/USART3_RTS/
LCD_SEG32
H12
60
-
-
-
PD13
I/O
FT
PD13
TIM4_CH2/LCD_SEG33
H11
61
-
-
-
PD14
I/O
FT
PD14
TIM4_CH3/LCD_SEG34
H10
62
-
-
-
PD15
I/O
FT
PD15
TIM4_CH4/LCD_SEG35
E12
63
-
PC6
I/O
FT
PC6
TIM3_CH1/I2S2_MCK/
LCD_SEG24
K10
54
36 F2
K9
55
-
K8
56
J12
37 F1
DocID022799 Rev 7
41/133
51
Pin descriptions
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 9. STM32L15xxC pin definitions (continued)
LQFP100
LQFP64
Pin type(1)
I / O Structure
Main
function(2)
(after
reset)
E11
64
38 E1
-
PC7
I/O
FT
PC7
TIM3_CH2/I2S3_MCK/
LCD_SEG25
E10
65
39 D1
-
PC8
I/O
FT
PC8
TIM3_CH3/LCD_SEG26
D12
66
40 E2
-
PC9
I/O
FT
PC9
TIM3_CH4/LCD_SEG27
D11
67
41 E3 29
PA8
I/O
FT
PA8
USART1_CK/MCO/LCD_COM0
D10
68
42 C1 30
PA9
I/O
FT
PA9
USART1_TX/LCD_COM1
C12
69
43 D2 31
PA10
I/O
FT
PA10
USART1_RX/LCD_COM2
B12
70
44 B1 32
PA11
I/O
FT
PA11
USART1_CTS/USB_DM/
SPI1_MISO
A12
71
45 D3 33
PA12
I/O
FT
PA12
USART1_RTS/USB_DP/
SPI1_MOSI
A11
72
46 C2 34
PA13
I/O
FT
JTMSSWDAT
C11
73
-
PH2
I/O
FT
PH2
F11
74
47 A1
35
VSS_2
S
VSS_2
G11
75
48 B2 36
VDD_2
S
VDD_2
A10
76
49 C3 37
PA14
I/O
FT
JTCKSWCLK
A9
77
50 A2
38
PA15
I/O
FT
JTDI
TIM2_CH1_ETR/SPI1_NSS/
SPI3_NSS/I2S3_WS/
LCD_SEG17
B11
78
51 B3
-
PC10
I/O
FT
PC10
SPI3_SCK/I2S3_CK/
USART3_TX/LCD_SEG28/
LCD_SEG40/LCD_COM4
C10
79
52 A3
-
PC11
I/O
FT
PC11
SPI3_MISO/USART3_RX/
LCD_SEG29/LCD_SEG41/
LCD_COM5
B10
80
53 B4
-
PC12
I/O
FT
PC12
SPI3_MOSI/I2S3_SD/
USART3_CK/LCD_SEG30/
LCD_SEG42/LCD_COM6
42/133
-
WLCSP63
UFBGA100
LQFP48 or UFQFPN48
Pins
-
Pin name
DocID022799 Rev 7
Alternate functions
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Pin descriptions
Table 9. STM32L15xxC pin definitions (continued)
UFBGA100
LQFP100
LQFP64
WLCSP63
LQFP48 or UFQFPN48
Pin type(1)
I / O Structure
Pins
Main
function(2)
(after
reset)
C9
81
-
-
-
PD0
I/O
FT
PD0
TIM9_CH1/SPI2_NSS/I2S2_WS
B9
82
-
-
-
PD1
I/O
FT
PD1
SPI2_SCK/I2S2_CK
C8
83
-
PD2
I/O
FT
PD2
TIM3_ETR/LCD_SEG31/
LCD_SEG43/LCD_COM7
B8
84
-
-
-
PD3
I/O
FT
PD3
SPI2_MISO/USART2_CTS
B7
85
-
-
-
PD4
I/O
FT
PD4
SPI2_MOSI/I2S2_SD/
USART2_RTS
A6
86
-
-
PD5
I/O
FT
PD5
USART2_TX
B6
87
-
-
-
PD6
I/O
FT
PD6
USART2_RX
A5
88
-
-
-
PD7
I/O
FT
PD7
TIM9_CH2/USART2_CK
A8
89
55 C4 39
PB3
I/O
FT
JTDO
TIM2_CH2/SPI1_SCK/
SPI3_SCK/I2S3_CK/LCD_SEG7/
COMP2_INM
A7
90
56 D4 40
PB4
I/O
FT
NJTRST
TIM3_CH1/SPI1_MISO/
SPI3_MISO/LCD_SEG8/
COMP2_INP
54 A4
Pin name
Alternate functions
C5
91
57 A5
41
PB5
I/O
FT
PB5
TIM3_CH2/I2C1_SMBA/
SPI1_MOSI/SPI3_MOSI/
I2S3_SD/LCD_SEG9/
COMP2_INP
B5
92
58 B5 42
PB6
I/O
FT
PB6
TIM4_CH1/I2C1_SCL/
USART1_TX/COMP2_INP
B4
93
59 C5 43
PB7
I/O
FT
PB7
TIM4_CH2/I2C1_SDA/
USART1_RX/PVD_IN/
COMP2_INP
A4
94
60 A6
BOOT0
I
B
BOOT0
A3
95
61 B6 45
PB8
I/O
FT
PB8
TIM4_CH3/TIM10_CH1/
I2C1_SCL/LCD_SEG16
B3
96
62 C6 46
PB9
I/O
FT
PB9
TIM4_CH4/TIM11_CH1/
I2C1_SDA/LCD_COM3
44
DocID022799 Rev 7
43/133
51
Pin descriptions
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 9. STM32L15xxC pin definitions (continued)
UFBGA100
LQFP100
LQFP64
WLCSP63
LQFP48 or UFQFPN48
Pin type(1)
I / O Structure
Pins
Main
function(2)
(after
reset)
C3
97
-
-
-
PE0
I/O
FT
PE0
TIM4_ETR/TIM10_CH1/
LCD_SEG36
A2
98
-
-
-
PE1
I/O
FT
PE1
TIM11_CH1/LCD_SEG37
D3
99
47
VSS_3
S
VSS_3
C4
100 64 B7 48
VDD_3
S
VDD_3
63 A7
Pin name
Alternate functions
1. I = input, O = output, S = supply.
2. Function availability depends on the chosen device.
3. Applicable to STM32L152xC devices only. In STM32L151xC devices, this pin should be connected to VDD.
4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the
LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose
PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over
the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
section in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038).
5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON
bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,
respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off ). The HSE has priority over the GPIO
function.
44/133
DocID022799 Rev 7
Table 10. Alternate function input/output
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
Port
name
AFIO5
AFIO6
AFIO7
.
AFIO10
.
AFIO11
.
.
AFIO14
AFIO15
CPRI
SYSTEM
Alternate function
SYSTEM
DocID022799 Rev 7
BOOT0
BOOT0
NRST
NRST
PA0WKUP1
WKUP1/
TAMPER2
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
USART1/2/3
USB
LCD
EVENT OUT
COMP1_INP/
TIMx_IC1_0/ EVENT OUT
G1IO1
TIM2_CH1_ ETR
TIM5_CH1
USART2_CTS
PA1
TIM2_CH2
TIM5_CH2
USART2_RTS
SEG0
COMP1_INP/
TIMx_IC2_0 EVENT OUT
G1IO2
PA2
TIM2_CH3
TIM5_CH3
TIM9_CH1
USART2_TX
SEG1
COMP1_INP/
TIMx_IC3_0/ EVENT OUT
G1IO3
PA3
TIM2_CH4
TIM5_CH4
TIM9_CH2
USART2_RX
SEG2
COMP1_INP/
TIMx_IC4_0/ EVENT OUT
G1IO4
PA4
SPI1_NSS
PA5
TIM2_CH1_ETR*
SPI3_NSS
I2S3_WS
COMP1_INP/
EVENT OUT
TIMx_IC1_1
USART2_CK
COMP1_INP/
EVENT OUT
TIMx_IC2_1
SPI1_SCK
TIM3_CH1
TIM10_
CH1
SPI1_MISO
SEG3
COMP1_INP/
TIMx_IC3_1 EVENT OUT
G2IO1
PA7
TIM3_CH2
TIM11_
CH1
SPI1_MOSI
SEG4
COMP1_INP/
TIMx_IC4_1/ EVENT OUT
G2IO2
USART1_CK
COM0
TIMx_IC1_2/
G4IO1
EVENT OUT
USART1_TX
COM1
TIMx_IC2_2/
G4IO2
EVENT OUT
45/133
PA9
MCO
Pin descriptions
PA6
PA8
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Alternate function input/output table
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
Port
name
AFIO5
AFIO6
AFIO7
.
AFIO10
.
AFIO11
.
.
AFIO14
AFIO15
CPRI
SYSTEM
TIMx_IC3_2/
G4IO3
EVENT OUT
Alternate function
SYSTEM
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
PA10
USART1/2/3
USB
USART1_RX
LCD
COM2
PA11
SPI1_MISO
USART1_CTS
USB_DM
TIMx_IC4_2
EVENT OUT
PA12
SPI1_MOSI
USART1_RTS
USB_DP
TIMx_IC1_3/
EVENT OUT
JTMS-SWDIO
TIMx_IC2_3/
G5IO1
EVENT OUT
PA14
JTCK-SWCLK
TIMx_IC3_3/
G5IO2
EVEN TOUT
PA15
JTDI
SEG17
TIMx_IC4_3/
G5IO3
EVEN TOUT
TIM2_CH1_ETR
SPI1_NSS
SPI3_NSS
I2S3_WS
PB0
TIM3_CH3
SEG5
COMP1_INP/
EVEN TOUT
G3IO1
PB1
TIM3_CH4
SEG6
COMP1_INP/
EVENT OUT
G3IO2
PB2
BOOT1
PB3
JTDO
PB4
JTRST
COMP1_INP/
EVENT OUT
G3IO3
TIM2_CH2
SPI1_SCK
TIM3_CH1
SPI3_SCK
I2S3_CK
SEG7
EVENT OUT
SPI1_MISO SPI3_MISO
SEG8
G6IO1
EVENT OUT
SPI3_MOSI
I2S3_SD
SEG9
G6IO2
EVENT OUT
PB5
TIM3_CH2
I2C1_
SMBA
PB6
TIM4_CH1
I2C1_SCL
USART1_TX
G6IO3
EVENT OUT
PB7
TIM4_CH2
I2C1_SDA
USART1_RX
G6IO4
EVENT OUT
PB8
TIM4_CH3
TIM10_
CH1
PB9
TIM4_CH4
TIM11_
CH1
PB10
TIM2_CH3
SPI1_MOSI
I2C1_SCL
SEG16
EVENT OUT
I2C1_SDA
COM3
EVENT OUT
SEG10
EVENT OUT
I2C2_SCL
USART3_TX
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
DocID022799 Rev 7
PA13
Pin descriptions
46/133
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
Port
name
AFIO5
AFIO6
AFIO7
.
AFIO10
.
AFIO11
.
.
AFIO14
AFIO15
CPRI
SYSTEM
Alternate function
SYSTEM
PB11
TIM2
TIM3/4/5
TIM9/
10/11
TIM2_CH4
I2C1/2
SPI1/2
SPI3
I2C2_SDA
USART1/2/3
USB
LCD
USART3_RX
SEG11
EVENT OUT
SPI2_NSS
I2S2_WS
USART3_CK
SEG12
COMP1_INP/
EVENT OUT
G7IO1
DocID022799 Rev 7
TIM10_
CH1
PB13
TIM9_
CH1
SPI2_SCK
I2S2_CK
USART3_CTS
SEG13
COMP1_INP/
EVENT OUT
G7IO2
PB14
TIM9_
CH2
SPI2_MISO
USART3_RTS
SEG14
COMP1_INP/
EVENT OUT
G7IO3
TIM11_
CH1
SPI2_MOSI
I2S2_SD
SEG15
COMP1_INP/
EVENT OUT
G7IO4
PC0
SEG18
COMP1_INP/
TIMx_IC1_4/ EVENT OUT
G8IO1
PC1
SEG19
COMP1_INP/
TIMx_IC2_4/ EVENT OUT
G8IO2
PC2
SEG20
COMP1_INP/
TIMx_IC3_4/ EVENT OUT
G8IO3
PC3
SEG21
COMP1_INP/
TIMx_IC4_4/ EVENT OUT
G8IO4
PC4
SEG22
COMP1_INP/
TIMx_IC1_5/ EVENT OUT
G9IO1
PC5
SEG23
COMP1_INP/
TIMx_IC2_5/ EVENT OUT
G9IO2
SEG24
TIMx_IC3_5/
G10IO1
EVENT OUT
SEG25
TIMx_IC4_5/
G10IO2
EVENT OUT
PB15
RTC_REFIN
PC6
TIM3_CH1
PC7
TIM3_CH2
I2C2_SMBA
I2S2_MCK
I2S3_MCK
Pin descriptions
47/133
PB12
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
Port
name
AFIO5
AFIO6
AFIO7
.
AFIO10
.
AFIO11
.
.
AFIO14
AFIO15
CPRI
SYSTEM
Alternate function
SYSTEM
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
USART1/2/3
USB
LCD
PC8
TIM3_CH3
SEG26
TIMx_IC1_6/
G10IO3
EVENT OUT
PC9
TIM3_CH4
SEG27
TIMx_IC2_6/
G10IO4
EVENT OUT
SPI3_SCK
I2S3_CK
USART3_TX
COM4/
SEG28/
SEG40
TIMx_IC3_6
EVENT OUT
PC11
SPI3_MISO USART3_RX
COM5/
SEG29
/SEG41
TIMx_IC4_6
EVENT OUT
PC12
SPI3_MOSI
USART3_CK
I2S3_SD
COM6/
SEG30/
SEG42
TIMx_IC1_7
EVENT OUT
PC13WKUP2
WKUP2/
TAMPER1/
TIMESTAMP/
ALARM_OUT/
512Hz
TIMx_IC2_7
EVENT OUT
PC14
OSC32_IN
OSC32_IN
TIMx_IC3_7
EVENT OUT
PC15
OSC32_
OUT
OSC32_OUT
TIMx_IC4_7
EVENT OUT
SPI2_NSS
I2S2_WS
TIMx_IC1_8
EVENT OUT
SPI2 SCK
I2S2_CK
TIMx_IC2_8
EVENT OUT
TIMx_IC3_8
EVENT OUT
TIMx_IC4_8
EVENT OUT
PD0
TIM9_CH1
PD1
PD2
PD3
COM7/
SEG31/
SEG43
TIM3_ETR
SPI2_MISO
USART2_CTS
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
DocID022799 Rev 7
PC10
Pin descriptions
48/133
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
Port
name
AFIO5
AFIO6
AFIO7
.
AFIO10
.
AFIO11
.
.
AFIO14
AFIO15
CPRI
SYSTEM
Alternate function
SYSTEM
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI2_MOSI
I2S2_SD
PD4
SPI3
USART1/2/3
USB
LCD
USART2_RTS
TIMx_IC1_9
EVENT OUT
PD5
USART2_TX
TIMx_IC2_9
EVENT OUT
PD6
USART2_RX
TIMx_IC3_9
EVENT OUT
USART2_CK
TIMx_IC4_9
EVENT OUT
PD7
TIM9_CH2
DocID022799 Rev 7
PD8
USART3_TX
SEG28
TIMx_IC1_10 EVENT OUT
PD9
USART3_RX
SEG29
TIMx_IC2_10 EVENT OUT
PD10
USART3_CK
SEG30
TIMx_IC3_10 EVENT OUT
PD11
USART3_CTS
SEG31
TIMx_IC4_10 EVENT OUT
USART3_RTS
SEG32
TIMx_IC1_11
EVENT OUT
PD12
TIM4_CH1
PD13
TIM4_CH2
SEG33
TIMx_IC2_11
EVENT OUT
PD14
TIM4_CH3
SEG34
TIMx_IC3_11
EVENT OUT
PD15
TIM4_CH4
SEG35
TIMx_IC4_11
EVENT OUT
PE0
TIM4_ETR
TIM10_
CH1
SEG36
TIMx_IC1_12 EVENT OUT
TIM11_
CH1
SEG37
TIMx_IC2_12 EVENT OUT
PE1
TRACECK
TIM3_ETR
SEG 38
TIMx_IC3_12 EVENT OUT
PE3
TRACED0
TIM3_CH1
SEG 39
TIMx_IC4_12 EVENT OUT
PE4
TRACED1
TIM3_CH2
PE5
TRACED2
TIM9_CH1
TIMx_IC2_13 EVENT OUT
PE6WKUP3
WKUP3/
TAMPER3 /
TRACED3
TIM9_CH2
TIMx_IC3_13 EVENT OUT
TIMx_IC1_13 EVENT OUT
Pin descriptions
49/133
PE2
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
Port
name
AFIO5
AFIO6
AFIO7
.
AFIO10
.
AFIO11
.
.
AFIO14
AFIO15
CPRI
SYSTEM
Alternate function
SYSTEM
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
USART1/2/3
USB
LCD
PE7
COMP1_INP/
EVENT OUT
TIMx_IC4_13
PE8
COMP1_INP/
EVENT OUT
TIMx_IC1_14
DocID022799 Rev 7
TIM2_CH1_ETR
TIM5_ETR
PE10
TIM2_CH2
COMP1_INP/
EVENT OUT
TIMx_IC3_14
PE11
TIM2_CH3
TIMx_IC4_14 EVENT OUT
PE12
TIM2_CH4
SPI1_NSS
TIMx_IC1_15 EVENT OUT
PE13
SPI1_SCK
TIMx_IC2_15 EVENT OUT
PE14
SPI1_MISO
TIMx_IC3_15 EVENT OUT
PE15
SPI1_MOSI
TIMx_IC4_15 EVENT OUT
PH0OSC
_IN
OSC_IN
PH1OSC_
OUT
OSC_OUT
PH2
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
COMP1_INP/
EVENT OUT
TIMx_IC2_14
PE9
Pin descriptions
50/133
Table 10. Alternate function input/output (continued)
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
5
Memory mapping
Memory mapping
Figure 9. Memory map
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DocID022799 Rev 7
51/133
51
Electrical characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
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52/133
DocID022799 Rev 7
DLE
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Power supply scheme
Figure 12. Power supply scheme
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Electrical characteristics
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DocID022799 Rev 7
53/133
110
Electrical characteristics
6.1.7
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Optional LCD power supply scheme
Figure 13. Optional LCD power supply scheme
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1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.
2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an
external capacitance is needed for correct behavior of this converter.
54/133
DocID022799 Rev 7
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
6.1.8
Electrical characteristics
Current consumption measurement
Figure 14. Current consumption measurement scheme
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DocID022799 Rev 7
55/133
110
Electrical characteristics
6.2
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics,
Table 12: Current characteristics, and Table 13: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 11. Voltage characteristics
Symbol
Ratings
VDD–VSS
VIN(2)
Min
Max
–0.3
4.0
Input voltage on five-volt tolerant pin
VSS − 0.3
VDD+4.0
Input voltage on any other pin
VSS − 0.3
4.0
External main supply voltage
(including VDDA and VDD)(1)
|ΔVDDx|
Variations between different VDD power pins
-
50
|VSSX − VSS|
Variations between all different ground pins
-
50
VREF+ –VDDA
Allowed voltage difference for VREF+ > VDDA
-
0.4
Electrostatic discharge voltage
(human body model)
see Section 6.3.11
VESD(HBM)
Unit
V
mV
V
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2.
VIN maximum must always be respected. Refer to Table 12 for maximum allowed injected current values.
Table 12. Current characteristics
Symbol
Ratings
Max.
Total current into sum of all VDD_x power lines (source)(1)
100
(sink)(1)
100
IVDD(PIN)
Maximum current into each VDD_x power pin
(source)(1)
70
IVSS(PIN)
Maximum current out of each VSS_x ground pin (sink)(1)
-70
Output current sunk by any I/O and control pin
25
IVDD(Σ)
IVSS(Σ)
(2)
IIO
ΣIIO(PIN)
IINJ(PIN) (3)
ΣIINJ(PIN)
Total current out of sum of all VSS_x ground lines
Output current sourced by any I/O and control pin
Total output current sunk by sum of all IOs and control
- 25
pins(2)
Total output current sourced by sum of all IOs and control pins(2)
Injected current on five-volt tolerant I/O(4), RST and B pins
Injected current on any other pin
(5)
Total injected current (sum of all I/O and control
Unit
mA
60
-60
-5/+0
±5
pins)(6)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.18.
4. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never
be exceeded. Refer to Table 11 for maximum allowed input voltage values.
56/133
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
5. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 11: Voltage characteristics for the maximum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 13. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Value
Unit
–65 to +150
°C
150
°C
Maximum junction temperature
6.3
Operating conditions
6.3.1
General operating conditions
Table 14. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
-
0
32
fPCLK1
Internal APB1 clock frequency
-
0
32
fPCLK2
Internal APB2 clock frequency
-
0
32
BOR detector disabled
1.65
3.6
BOR detector enabled, at power
on
1.8
3.6
BOR detector disabled, after
power on
1.65
3.6
1.65
3.6
1.8
3.6
FT pins; 2.0 V ≤ VDD
-0.3
5.5(3)
FT pins; VDD < 2.0 V
-0.3
5.25(3)
0
5.5
-0.3
VDD+0.3
VDD
VDDA
(1)
VIN
Standard operating voltage
Analog operating voltage
(ADC and DAC not used)
Analog operating voltage
(ADC or DAC used)
I/O input voltage
Must be the same voltage as
VDD(2)
BOOT0 pin
Any other pin
PD
Power dissipation at
TA = 85 °C(4)
MHz
V
V
LQFP48 package
364
LQFP100 package
465
LQFP64 package
435
UFQFPN48 package
625
UFBGA100
339
WLCSP63 package
408
DocID022799 Rev 7
Unit
V
mW
57/133
110
Electrical characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 14. General operating conditions (continued)
Symbol
Parameter
TA
Temperature range
TJ
Junction temperature range
Conditions
Min
Max
Maximum power dissipation
–40
85
Low-power dissipation(5)
–40
105
-40 °C ≤ TA ≤ 105 °C
–40
105
Unit
°C
°C
1. When the ADC is used, refer to Table 56: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and up to 140 mV in operation.
3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 72: Thermal
characteristics on page 126).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see Table 72:
Thermal characteristics on page 126).
6.3.2
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 14.
Table 15. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
VDD rise time rate
tVDD(1)
VDD fall time rate
TRSTTEMPO(1) Reset temporization
Typ
Max
BOR detector enabled
0
-
∞
BOR detector disabled
0
-
1000
BOR detector enabled
20
-
∞
BOR detector disabled
0
-
1000
VDD rising, BOR enabled
-
2
3.3
0.4
0.7
1.6
Falling edge
1
1.5
1.65
Rising edge
1.3
1.5
1.65
Falling edge
1.67
1.7
1.74
Rising edge
1.69
1.76
1.8
Falling edge
1.87
1.93
1.97
Rising edge
1.96
2.03
2.07
Falling edge
2.22
2.30
2.35
Rising edge
2.31
2.41
2.44
VDD rising, BOR
disabled(2)
VPOR/PDR
Power on/power down reset
threshold
VBOR0
Brown-out reset threshold 0
58/133
Min
VBOR1
Brown-out reset threshold 1
VBOR2
Brown-out reset threshold 2
DocID022799 Rev 7
Unit
μs/V
ms
V
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Table 15. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
VBOR3
Brown-out reset threshold 3
VBOR4
Brown-out reset threshold 4
VPVD0
Programmable voltage
detector threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
Vhyst
Hysteresis voltage
Min
Typ
Max
Falling edge
2.45
2.55
2.6
Rising edge
2.54
2.66
2.7
Falling edge
2.68
2.8
2.85
Rising edge
2.78
2.9
2.95
Falling edge
1.8
1.85
1.88
Rising edge
1.88
1.94
1.99
Falling edge
1.98
2.04
2.09
Rising edge
2.08
2.14
2.18
Falling edge
2.20
2.24
2.28
Rising edge
2.28
2.34
2.38
Falling edge
2.39
2.44
2.48
Rising edge
2.47
2.54
2.58
Falling edge
2.57
2.64
2.69
Rising edge
2.68
2.74
2.79
Falling edge
2.77
2.83
2.88
Rising edge
2.87
2.94
2.99
Falling edge
2.97
3.05
3.09
Rising edge
3.08
3.15
3.20
BOR0 threshold
-
40
-
All BOR and PVD
thresholds excepting
BOR0
-
100
-
Unit
V
mV
1. Guaranteed by characterization, not tested in production.
2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more
details.
DocID022799 Rev 7
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110
Electrical characteristics
6.3.3
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Embedded internal reference voltage
The parameters given in Table 17 are based on characterization results, unless otherwise
specified.
Table 16. Embedded internal reference voltage calibration values
Calibration value name
Description
Raw data acquired at
temperature of 30 °C ±5 °C
VDDA= 3 V ±10 mV
VREFINT_CAL
Memory address
0x1FF8 00F8 - 0x1FF8 00F9
Table 17. Embedded internal reference voltage
Symbol
VREFINT out
Parameter
(1)
Conditions
Internal reference voltage
Min
Typ
– 40 °C < TJ < +105 °C 1.202 1.224
Max
Unit
1.242
V
Internal reference current
consumption
-
-
1.4
2.3
μA
TVREFINT
Internal reference startup time
-
-
2
3
ms
VVREF_MEAS
VDDA and VREF+ voltage during
VREFINT factory measure
-
2.99
3
3.01
V
AVREF_MEAS
Including uncertainties
Accuracy of factory-measured VREF
due to ADC and
(2)
value
VDDA/VREF+ values
-
-
±5
mV
–40 °C < TJ < +105 °C
-
20
50
0 °C < TJ < +50 °C
-
-
20
ppm/°
C
Long-term stability
1000 hours, T= 25 °C
-
-
1000
ppm
Voltage coefficient
3.0 V < VDDA < 3.6 V
-
-
2000
ppm/V
IREFINT
TCoeff(3)
ACoeff
Temperature coefficient
(3)
VDDCoeff
(3)
TS_vrefint(3)
ADC sampling time when reading
the internal reference voltage
-
4
-
-
μs
TADC_BUF(3) (4)
Startup time of reference voltage
buffer for ADC
-
-
-
10
μs
IBUF_ADC(3)
Consumption of reference voltage
buffer for ADC
-
-
13.5
25
μA
IVREF_OUT(3)
VREF_OUT output current (5)
-
-
-
1
μA
CVREF_OUT(3)
VREF_OUT output load
-
-
-
50
pF
Consumption of reference voltage
buffer for VREF_OUT and COMP
-
-
730
1200
nA
VREFINT_DIV1(3)
1/4 reference voltage
-
24
25
26
(3)
1/2 reference voltage
-
49
50
51
VREFINT_DIV3(3)
3/4 reference voltage
-
74
75
76
ILPBUF(3)
VREFINT_DIV2
1. Tested in production
2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
3. Guaranteed by design, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.
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DocID022799 Rev 7
%
VREFIN
T
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
5. To guarantee less than 1% VREF_OUT deviation.
6.3.4
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to the Dhrystone 2.1 code, unless
otherwise specified. The current consumption values are derived from tests performed
under ambient temperature and VDD supply voltage conditions summarized in Table 14:
General operating conditions, unless otherwise specified.
The MCU is placed under the following conditions:
•
All I/O pins are configured in analog input mode
•
All peripherals are disabled except when explicitly mentioned.
•
The Flash memory access time, 64-bit access and prefetch is adjusted depending on
fHCLK frequency and voltage range to provide the best CPU performance.
•
When the peripherals are enabled fAPB1 = fAPB2 = fAHB.
•
When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used).
•
The HSE user clock applied to OSCI_IN input follows the characteristic specified in
Table 27: High-speed external user clock characteristics.
•
For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins.
•
For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not
specified otherwise.
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 18. Current consumption in Run mode, code with data processing running from Flash
Symbol
Parameter
fHCLK
Typ
Max(1)
1 MHz
215
400
2 MHz
400
600
4 MHz
725
960
4 MHz
0.915
1.1
8 MHz
1.75
2.1
16 MHz
3.4
3.9
8 MHz
2.1
2.8
16 MHz
4.2
4.9
32 MHz
8.25
9.4
Range 2, VCORE=1.5 V
VOS[1:0] = 10
16 MHz
3.5
4
Range 1, VCORE=1.8 V
VOS[1:0] = 01
32 MHz
8.2
9.6
65 kHz
40.5
110
524 kHz
125
190
4.2 MHz
775
900
Conditions
Range 3, VCORE=1.2 V
VOS[1:0] = 11
IDD
(Run
from
Flash)
Supply
current in
Run mode,
code
executed
from Flash
fHSE = fHCLK up to 16
MHz included, fHSE =
fHCLK/2 above 16 MHz
(PLL ON)(2)
Range 2, VCORE=1.5 V
VOS[1:0] = 10
Range 1, VCORE=1.8 V
VOS[1:0] = 01
HSI clock source (16
MHz)
MSI clock, 65 kHz
MSI clock, 524 kHz
Range 3, VCORE=1.2 V
VOS[1:0] = 11
MSI clock, 4.2 MHz
1. Based on characterization, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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μA
mA
μA
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Table 19. Current consumption in Run mode, code with data processing running from RAM
Symbol
Parameter
fHSE = fHCLK
up to 16 MHz,
included
fHSE = fHCLK/2 above
16 MHz
(PLL ON)(2)
IDD (Run
from
RAM)
Typ
Max(1)
1 MHz
Range 3,
VCORE=1.2 V VOS[1:0] 2 MHz
= 11
4 MHz
185
240
345
410
4 MHz
Range 2,
VCORE=1.5 V VOS[1:0] 8 MHz
= 10
16 MHz
0.755
1.4
1.5
2.1
3
3.5
8 MHz
1.8
2.8
16 MHz
3.6
4.1
32 MHz
7.15
8.3
Range 2,
VCORE=1.5 V VOS[1:0] 16 MHz
= 10
2.95
3.5
Range 1,
VCORE=1.8 V VOS[1:0] 32 MHz
= 01
7.15
8.4
38.5
85
110
160
690
810
Conditions
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
Supply current in
Run mode, code
executed from
RAM, Flash
switched off
HSI clock source (16
MHz)
MSI clock, 65 kHz
MSI clock, 524 kHz
MSI clock, 4.2 MHz
fHCLK
65 kHz
Range 3,
VCORE=1.2 V VOS[1:0] 524 kHz
= 11
4.2 MHz
645
880
Unit
µA
(3)
mA
µA
1. Based on characterization, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
3. Tested in production.
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Table 20. Current consumption in Sleep mode
Symbol
Parameter
Conditions
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to
16 MHz included,
Range 2,
fHSE = fHCLK/2
VCORE=1.5 V
above 16 MHz (PLL VOS[1:0] = 10
ON)(2)
Supply current
in Sleep
mode, Flash
OFF
HSI clock source
(16 MHz)
Max(1)
1 MHz
60.5
130
2 MHz
89.5
195
4 MHz
150
310
4 MHz
180
310
8 MHz
320
440
16 MHz
605
830
8 MHz
380
550
16 MHz
695
990
32 MHz
1600
2100
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz
650
890
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz
1600
2200
65 kHz
30
60
524 kHz
44
99
4.2 MHz
155
210
1 MHz
50
130
2 MHz
78.5
190
4 MHz
140
320
4 MHz
165
320
Range 3,
MSI clock, 524 kHz VCORE=1.2 V
VOS[1:0] = 11
MSI clock, 4.2 MHz
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to
Range 2,
16 MHz included,
VCORE=1.5 V
fHSE = fHCLK/2
above 16 MHz (PLL VOS[1:0] = 10
Supply current ON)(2)
in Sleep
Range 1,
mode, Flash
VCORE=1.8 V
ON
VOS[1:0] = 01
8 MHz
310
460
16 MHz
590
840
8 MHz
350
540
16 MHz
680
1000
32 MHz
1600
2100
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz
640
910
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz
1600
2200
65 kHz
19
90
524 kHz
33
96
4.2 MHz
145
220
HSI clock source
(16 MHz)
Supply current MSI clock, 65 kHz
Range 3,
in Sleep
MSI clock, 524 kHz VCORE=1.2V
mode, Flash
VOS[1:0] = 11
ON
MSI clock, 4.2 MHz
1. Based on characterization, not tested in production, unless otherwise specified.
64/133
Typ
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
MSI clock, 65 kHz
IDD (Sleep)
fHCLK
DocID022799 Rev 7
Unit
μA
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)
Table 21. Current consumption in Low-power run mode
Symbol Parameter
Typ
Max(1)
8.6
12
19
25
TA = 105 °C
35
47
TA =-40 °C to 25
°C
14
16
24
29
TA = 105 °C
40
51
TA = -40 °C to 25
°C
26
29
TA = 55 °C
28
31
TA = 85 °C
36
42
TA = 105 °C
52
64
TA = -40 °C to 25
°C
20
24
32
37
TA = 105 °C
49
61
TA = -40 °C to 25
°C
26
30
TA = 85 °C
38
44
TA = 105 °C
55
67
TA = -40 °C to 25
°C
41
46
TA = 55 °C
44
50
TA = 85 °C
56
87
TA = 105 °C
73
110
-
200
Conditions
TA = -40 °C to 25
°C
All
peripheral
s OFF,
code
executed
from RAM,
Flash
switched
OFF, VDD
from
1.65 V to
3.6 V
IDD
(LP
Run)
Supply
current in
Low-power
run mode
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = 85 °C
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = 85 °C
MSI clock,
131 kHz
fHCLK = 131 kHz
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = 85 °C
All
peripheral
s OFF,
code
MSI clock, 65 kHz
executed f
HCLK = 65 kHz
from
Flash,
VDD from
1.65 V to
3.6 V
MSI clock,
131 kHz
fHCLK = 131 kHz
Max
VDD from
IDD max allowed
current in 1.65 V to
(LP
Low-power 3.6 V
Run)
run mode
Unit
μA
1. Based on characterization, not tested in production, unless otherwise specified.
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 22. Current consumption in Low-power sleep mode
Symbol
Paramet
er
MSI clock, 65
kHz
fHCLK = 32 kHz
Flash OFF
MSI clock, 65
kHz
fHCLK = 32 kHz
Flash ON
All peripherals
OFF, VDD from MSI clock, 65
1.65 V to 3.6 V kHz
fHCLK = 65 kHz,
Flash ON
IDD
(LP
Sleep)
Max(1)
TA = -40 °C to
25 °C
4.4
-
TA = -40 °C to 25
°C
14
16
TA = 85 °C
19
23
TA = 105 °C
27
33
TA = -40 °C to 25
°C
15
17
TA = 85 °C
20
23
TA = 105 °C
28
33
17
19
18
21
22
25
TA = 105 °C
30
35
TA = -40 °C to 25
°C
14
16
TA = 85 °C
19
22
TA = 105 °C
27
32
TA = -40 °C to 25
°C
15
17
TA = 85 °C
20
23
TA = 105 °C
28
33
TA = -40 °C to
25 °C
17
19
TA = 55 °C
18
21
TA = 85 °C
22
25
TA = 105 °C
30
36
-
200
TA = -40 °C to
25 °C
MSI clock,
131 kHz
TA = 55 °C
fHCLK = 131 kHz,
TA = 85 °C
Flash ON
Supply
current in
Lowpower
sleep
mode
MSI clock, 65
kHz
fHCLK = 32 kHz
TIM9 and
USART1
enabled, Flash
ON, VDD from
1.65 V to 3.6 V
MSI clock,
65 kHz
fHCLK = 65 kHz
MSI clock,
131 kHz
fHCLK = 131 kHz
IDD max
(LP
Sleep)
Typ
Conditions
Max
allowed
current in
VDD from
Low1.65 V to 3.6 V
power
sleep
mode
1. Based on characterization, not tested in production, unless otherwise specified.
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μA
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Table 23. Typical and maximum current consumptions in Stop mode
Symbol
Parameter
Conditions
LCD
OFF
RTC clocked by LSI
or LSE external clock
(32.768kHz),
regulator in LP
mode,HSI and HSE
OFF (no independent
watchdog)
Typ
TA = -40°C to 25°C
VDD = 1.8 V
1.15
-
TA = -40°C to 25°C
1.4
-
TA = 55°C
2
-
TA= 85°C
3.4
10
TA = 105°C
6.35
23
1.55
6
2.15
7
3.55
12
6.3
27
3.9
10
4.65
11
6.25
16
TA = 105°C
9.1
44
TA = -40°C to 25°C
1.5
-
TA = 55°C
2.15
-
TA= 85°C
3.7
-
TA = 105°C
6.75
-
1.6
-
2.3
-
3.8
-
6.85
-
4
-
4.85
-
6.5
-
TA = 105°C
9.1
-
TA = -40°C to 25°C
VDD = 1.8V
1.2
-
TA = -40°C to 25°C
VDD = 3.0V
1.5
-
TA = -40°C to 25°C
VDD = 3.6V
1.75
-
TA = -40°C to 25°C
LCD
TA = 55°C
ON
(static T = 85°C
A
duty)(2)
TA = 105°C
TA = -40°C to 25°C
LCD
TA = 55°C
ON (1/8
duty)(3) TA= 85°C
IDD (Stop
with RTC)
Supply current in
Stop mode with RTC
enabled
LCD
OFF
TA = -40°C to 25°C
LCD
TA = 55°C
ON
(static T = 85°C
A
duty)(2)
TA = 105°C
RTC clocked by LSE
external quartz
(32.768kHz),
regulator in LP mode,
TA = -40°C to 25°C
HSI and HSE OFF
LCD
TA = 55°C
(no independent
ON
(1/8
watchdog(4)
duty)(3) TA= 85°C
LCD
OFF
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μA
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Table 23. Typical and maximum current consumptions in Stop mode (continued)
Symbol
Parameter
Conditions
Regulator in LP mode, HSI and
HSE OFF, independent
watchdog and LSI enabled
IDD (Stop)
Supply current in
Stop mode (RTC
disabled)
Typ
TA = -40°C to 25°C
1.6
2.2
TA = -40°C to 25°C
0.435
1
0.99
3
2.4
9
5.5
22(5)
2
-
1.45
-
1.45
-
Regulator in LP mode, LSI, HSI T = 55°C
A
and HSE OFF (no independent
TA= 85°C
watchdog)
TA = 105°C
IDD
(WU from
Stop)
MSI = 4.2 MHz
Supply current during
wakeup from Stop
MSI = 1.05 MHz
mode
MSI = 65 kHz(6)
Max(1) Unit
TA = -40°C to 25°C
μA
mA
1. Based on characterization, not tested in production, unless otherwise specified.
2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.
3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
5. Tested in production.
6. When MSI = 64 kHz, the RMS current is measured over the first 15 μs following the wakeup event. For the remaining part
of the wakeup period, the current corresponds the Run mode current.
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Table 24. Typical and maximum current consumptions in Standby mode
Symbol
Parameter
Typ
Max(1)
0.905
-
1.15
1.9
1.5
2.2
TA= 85 °C
1.75
4
TA = 105 °C
2.1
8.3(2)
TA = -40 °C to 25 °C
VDD = 1.8 V
0.98
-
TA = -40 °C to 25 °C
1.3
-
TA = 55 °C
1.7
-
TA= 85 °C
2.05
-
TA = 105 °C
2.45
-
1
1.7
0.29
0.6
0.345
0.9
0.575
2.75
1.45
7(2)
1
-
Conditions
TA = -40 °C to 25 °C
VDD = 1.8 V
T = -40 °C to 25 °C
RTC clocked by LSI (no A
independent watchdog) TA = 55 °C
IDD
(Standby
with RTC)
Supply current in
Standby mode with RTC
enabled
RTC clocked by LSE
external quartz(no
independent
watchdog)(3)
Independent watchdog
TA = -40 °C to 25 °C
and LSI enabled
IDD
(Standby)
Supply current in
Standby mode (RTC
disabled)
TA = -40 °C to 25 °C
Independent watchdog TA = 55 °C
and LSI OFF
TA = 85 °C
TA = 105 °C
IDD
(WU from
Standby)
Supply current during
wakeup time from
Standby mode
TA = -40 °C to 25 °C
Unit
μA
mA
1. Based on characterization, not tested in production, unless otherwise specified
2. Tested in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
•
all I/O pins are in input mode with a static value at VDD or VSS (no load)
•
all peripherals are disabled unless otherwise mentioned
•
the given value is calculated by measuring the current consumption
–
with all peripherals clocked off
–
with only one peripheral clocked on
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 25. Peripheral current consumption(1)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
VCORE=
1.8 V
VOS[1:0] =
01
Range 2,
VCORE=
1.5 V
VOS[1:0] =
10
Range 3,
VCORE=
1.2 V
VOS[1:0] =
11
Low-power
sleep and
run
TIM2
13
11
9
11
TIM3
12
10
9
11
TIM4
12
10
9
11
TIM5
16
13
11
14
TIM6
4
4
4
4
TIM7
4
4
4
4
LCD
4
3
3
4
WWDG
3
2.5
2.5
3
SPI2
8
7
9
7.5
SPI3
7
6
7
6
USART2
8
7
7
7
USART3
8
7
7
7
I2C1
8
7
6
7
I2C2
7
6
5
6
USB
15
7
7
7
PWR
3
3
3
3
DAC
6
5
4.5
5
COMP
4
3.5
3.5
4
Peripheral
APB1
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Unit
μA/MHz
(fHCLK)
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Table 25. Peripheral current consumption(1) (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
VCORE=
1.8 V
VOS[1:0] =
01
Range 2,
VCORE=
1.5 V
VOS[1:0] =
10
Range 3,
VCORE=
1.2 V
VOS[1:0] =
11
Low-power
sleep and
run
SYSCFG &
RI
3
2
2
3
TIM9
8
7
6
7
TIM10
6
5
5
5
TIM11
6
5
5
5
10
8
7
8
SPI1
4
4
4
4
USART1
8
7
6
7
GPIOA
7
6
5
6
GPIOB
7
6
5
6
GPIOC
7
6
5
6
GPIOD
7
6
5
6
GPIOE
7
6
5
6
GPIOH
2
2
1
2
0.5
0.5
0.5
1
(3)
Peripheral
APB2
ADC
AHB
(2)
CRC
FLASH
26
26
29
-
DMA1
18
15
13
18
DMA2
16
14
12
16
279
221
219
215
All enabled
IDD (RTC)
0.4
IDD (LCD)
3.1
IDD (ADC)(4)
1450
IDD (DAC)(5)
340
IDD (COMP1)
0.16
IDD (COMP2)
Slow mode
2
Fast mode
5
IDD (PVD / BOR)(6)
2.6
IDD (IWDG)
0.25
Unit
μA/MHz
(fHCLK)
μA
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
3. In Low-power sleep and run mode, the Flash memory must always be in power-down mode.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC
conversion (HSI consumption not included).
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC
conversion of VDD/2. DAC is in buffered mode, output is left floating.
6. Including supply current of internal reference voltage.
6.3.5
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode
•
Stop mode: the clock source is the MSI oscillator in the range configured before
entering Stop mode
•
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 14.
Table 26. Low-power mode wakeup timings
Symbol
tWUSLEEP
tWUSLEEP_LP
Parameter
Wakeup from Sleep mode
tWUSTDBY
Max(1) Unit
0.4
-
fHCLK = 262 kHz
Flash enabled
46
-
fHCLK = 262 kHz
Flash switched OFF
46
-
fHCLK = fMSI = 4.2 MHz
8.2
-
fHCLK = fMSI = 4.2 MHz
Voltage range 1 and 2
7.7
8.9
fHCLK = fMSI = 4.2 MHz
Voltage range 3
8.2
13.1
fHCLK = fMSI = 2.1 MHz
10.2
13.4
fHCLK = fMSI = 1.05 MHz
16
20
fHCLK = fMSI = 524 kHz
31
37
fHCLK = fMSI = 262 kHz
57
66
fHCLK = fMSI = 131 kHz
112
123
fHCLK = MSI = 65 kHz
221
236
Wakeup from Standby mode
FWU bit = 1
fHCLK = MSI = 2.1 MHz
58
104
Wakeup from Standby mode
FWU bit = 0
fHCLK = MSI = 2.1 MHz
2.6
3.25
Wakeup from Low-power sleep
mode, fHCLK = 262 kHz
Wakeup from Stop mode,
regulator in low-power mode
1. Based on characterization, not tested in production, unless otherwise specified
72/133
Typ
fHCLK = 32 MHz
Wakeup from Stop mode,
regulator in Run mode
tWUSTOP
Conditions
DocID022799 Rev 7
μs
ms
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
6.3.6
Electrical characteristics
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the
recommended clock input waveform is shown in Figure 15.
Table 27. High-speed external user clock characteristics(1)
Symbol
fHSE_ext
Parameter
User external clock source frequency
Conditions
Min
Typ
Max
Unit
CSS is on or PLL
is used
1
8
32
MHz
CSS is off, PLL
not used
0
8
32
MHz
VHSEH
OSC_IN input pin high level voltage
0.7VDD
-
VDD
VHSEL
OSC_IN input pin low level voltage
VSS
-
0.3VDD
12
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
-
-
20
OSC_IN input capacitance
-
2.6
-
Cin(HSE)
-
V
ns
pF
1. Guaranteed by design, not tested in production.
Figure 15. High-speed external clock source AC timing diagram
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Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 14.
Table 28. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
fLSE_ext
User external clock source
frequency
VLSEH
OSC32_IN input pin high level
voltage
VLSEL
OSC32_IN input pin low level
voltage
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time
Min
Typ
Max
Unit
1
32.768
1000
kHz
0.7VDD
-
VDD
V
-
VSS
-
0.3VDD
465
-
ns
CIN(LSE)
OSC32_IN input capacitance
-
-
-
10
-
0.6
-
pF
1. Guaranteed by design, not tested in production
Figure 16. Low-speed external clock source AC timing diagram
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 29. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
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Electrical characteristics
Table 29. HSE oscillator characteristics(1)(2)
Symbol
fOSC_IN
Parameter
Conditions
Min Typ
Max
Unit
24
MHz
Oscillator frequency
-
1
RF
Feedback resistor
-
-
200
-
kΩ
C
Recommended load
capacitance versus
equivalent serial
resistance of the crystal
(RS)(3)
RS = 30 Ω
-
20
-
pF
VDD= 3.3 V,
VIN = VSS with 30 pF
load
-
-
3
mA
C = 20 pF
fOSC = 16 MHz
-
-
2.5 (startup)
0.7 (stabilized)
C = 10 pF
fOSC = 16 MHz
-
-
2.5 (startup)
0.46 (stabilized)
Startup
3.5
-
-
mA /V
VDD is stabilized
-
1
-
ms
IHSE
IDD(HSE)
gm
tSU(HSE)(4)
HSE driving current
HSE oscillator power
consumption
Oscillator
transconductance
Startup time
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid
environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point
into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
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Figure 17. HSE oscillator circuit diagram
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1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 30. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 30. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSE
Low speed external oscillator
frequency
-
-
32.768
-
kHz
RF
Feedback resistor
-
-
1.2
-
MΩ
C(2)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
RS = 30 kΩ
-
8
-
pF
ILSE
LSE driving current
VDD = 3.3 V, VIN = VSS
-
-
1.1
μA
VDD = 1.8 V
-
450
-
VDD = 3.0 V
-
600
-
VDD = 3.6V
-
750
-
-
3
-
-
μA/V
VDD is stabilized
-
1
-
s
IDD (LSE)
gm
LSE oscillator current
consumption
Oscillator transconductance
tSU(LSE)(4) Startup time
nA
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.
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4.
Electrical characteristics
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Note:
For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator (see Figure 18).
CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Figure 18. Typical application with a 32.768 kHz crystal
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6.3.7
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Internal clock source characteristics
The parameters given in Table 31 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 14.
High-speed internal (HSI) RC oscillator
Table 31. HSI oscillator characteristics
Symbol
fHSI
TRIM
(1)(2)
Parameter
Conditions
Min
Typ
Max
Unit
Frequency
VDD = 3.0 V
-
16
-
MHz
HSI user-trimmed
resolution
Trimming code is not a multiple of 16
-
± 0.4
0.7
%
Trimming code is a multiple of 16
-
Accuracy of the
ACCHSI(2) factory-calibrated
HSI oscillator
-
± 1.5
%
VDDA = 3.0 V, TA = 25 °C
-1(3)
-
1(3)
%
VDDA = 3.0 V, TA = 0 to 55 °C
-1.5
-
1.5
%
VDDA = 3.0 V, TA = -10 to 70 °C
-2
-
2
%
VDDA = 3.0 V, TA = -10 to 85 °C
-2.5
-
2
%
VDDA = 3.0 V, TA = -10 to 105 °C
-4
-
2
%
VDDA = 1.65 V to 3.6 V
TA = -40 to 105 °C
-4
-
3
%
tSU(HSI)(2)
HSI oscillator
startup time
-
-
3.7
6
μs
IDD(HSI)(2)
HSI oscillator
power consumption
-
-
100
140
μA
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Based on characterization, not tested in production.
3. Tested in production.
Low-speed internal (LSI) RC oscillator
Table 32. LSI oscillator characteristics
Symbol
fLSI
(1)
DLSI(2)
tsu(LSI)(3)
IDD(LSI)
(3)
Parameter
Min
Typ
Max
Unit
LSI frequency
26
38
56
kHz
LSI oscillator frequency drift
0°C ≤ TA ≤ 85°C
-10
-
4
%
LSI oscillator startup time
-
-
200
μs
LSI oscillator power consumption
-
400
510
nA
1. Tested in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design, not tested in production.
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Electrical characteristics
Multi-speed internal (MSI) RC oscillator
Table 33. MSI oscillator characteristics
Symbol
Condition
Typ
MSI range 0
65.5
-
MSI range 1
131
-
MSI range 2
262
-
MSI range 3
524
-
MSI range 4
1.05
-
MSI range 5
2.1
-
MSI range 6
4.2
-
Frequency error after factory calibration
-
±0.5
-
%
DTEMP(MSI)(1)
MSI oscillator frequency drift
0 °C ≤ TA ≤ 85 °C
-
±3
-
%
DVOLT(MSI)(1)
MSI oscillator frequency drift
1.65 V ≤ VDD ≤ 3.6 V, TA = 25 °C
-
-
2.5
%/V
MSI range 0
0.75
-
MSI range 1
1
-
MSI range 2
1.5
-
MSI range 3
2.5
-
MSI range 4
4.5
-
MSI range 5
8
-
MSI range 6
15
-
MSI range 0
30
-
MSI range 1
20
-
MSI range 2
15
-
MSI range 3
10
-
MSI range 4
6
-
MSI range 5
5
-
MSI range 6,
Voltage range 1
and 2
3.5
-
MSI range 6,
Voltage range 3
5
-
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
fMSI
ACCMSI
IDD(MSI)
Parameter
(2)
tSU(MSI)
MSI oscillator power consumption
MSI oscillator startup time
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MHz
μA
μs
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Table 33. MSI oscillator characteristics (continued)
Symbol
tSTAB(MSI)(2)
fOVER(MSI)
Parameter
MSI oscillator stabilization time
MSI oscillator frequency overshoot
Condition
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MSI range 0
-
40
MSI range 1
-
20
MSI range 2
-
10
MSI range 3
-
4
MSI range 4
-
2.5
MSI range 5
-
2
MSI range 6,
Voltage range 1
and 2
-
2
MSI range 3,
Voltage range 3
-
3
Any range to
range 5
-
4
Any range to
range 6
-
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Based on characterization, not tested in production.
Typ
μs
MHz
6
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
6.3.8
Electrical characteristics
PLL characteristics
The parameters given in Table 34 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 14.
Table 34. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
2
-
24
MHz
PLL input clock duty cycle
45
-
55
%
fPLL_OUT
PLL output clock
2
-
32
MHz
tLOCK
Worst case PLL lock time
PLL input = 16 MHz
PLL VCO = 96 MHz
-
115
160
μs
Jitter
Cycle-to-cycle jitter
-
-
± 600
ps
IDDA(PLL)
Current consumption on VDDA
-
220
450
IDD(PLL)
Current consumption on VDD
-
120
150
fPLL_IN
μA
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
6.3.9
Memory characteristics
The characteristics are given at TA = -40 to 105 °C unless otherwise specified.
RAM memory
Table 35. RAM and hardware registers
Symbol
VRM
Parameter
Conditions
Data retention mode(1)
STOP mode (or RESET)
Min
Typ
Max
Unit
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
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Flash memory and data EEPROM
Table 36. Flash memory and data EEPROM characteristics
Symbol
Conditions
Min
Typ
Max(1)
Unit
-
1.65
-
3.6
V
Erasing
-
3.28
3.94
Programming
-
3.28
3.94
Average current during
the whole programming /
erase operation
-
600
900
μA
Maximum current (peak) TA = 25 °C, VDD = 3.6 V
during the whole
programming / erase
operation
-
1.5
2.5
mA
Parameter
VDD
Operating voltage
Read / Write / Erase
tprog
Programming time for
word or half-page
IDD
ms
1. Guaranteed by design, not tested in production.
Table 37. Flash memory and data EEPROM endurance and retention
Value
Symbol
NCYC
(2)
Parameter
Cycling (erase / write)
Program memory
Cycling (erase / write)
EEPROM data memory
Data retention (program memory) after
10 kcycles at TA = 85 °C
(2)
tRET
Data retention (EEPROM data memory)
after 300 kcycles at TA = 85 °C
Data retention (program memory) after
10 kcycles at TA = 105 °C
Data retention (EEPROM data memory)
after 300 kcycles at TA = 105 °C
Conditions
TA = -40°C to
105 °C
10
-
Unit
kcycles
300
-
-
30
-
-
30
-
-
TRET = +85 °C
years
10
-
-
10
-
-
TRET = +105 °C
1. Based on characterization not tested in production.
2. Characterization is done according to JEDEC JESD22-A117.
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6.3.10
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 38. They are based on the EMS levels and classes
defined in application note AN1709.
Table 38. EMS characteristics
Symbol
Parameter
Conditions
VFESD
VDD = 3.3 V, LQFP100, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK = 32 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
Level/
Class
2B
VDD = 3.3 V, LQFP100, TA = +25
°C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
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To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 39. EMI characteristics
Max vs. frequency range
Symbol Parameter
SEMI
6.3.11
Conditions
VDD = 3.3 V,
TA = 25 °C,
Peak level LQFP100 package
compliant with IEC
61967-2
Monitored
frequency band
4 MHz
16 MHz 32 MHz
voltage voltage voltage
range 3 range 2 range 1
0.1 to 30 MHz
3
-6
-5
30 to 130 MHz
18
4
-7
130 MHz to 1GHz
15
5
-7
SAE EMI Level
2.5
2
1
Unit
dBμV
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 40. ESD absolute maximum ratings
Symbol
VESD(HBM)
Ratings
Conditions
TA = +25 °C,
Electrostatic discharge
conforming to JESD22voltage (human body model)
A114
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C,
conforming to
ANSI/ESD STM5.3.1.
1. Based on characterization results, not tested in production.
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Maximum
value(1)
2
2000
Unit
V
II
500
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 41. Electrical sensitivities
Symbol
LU
6.3.12
Parameter
Static latch-up class
Conditions
Class
TA = +105 °C conforming to JESD78A
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 μA/+0 μA range), or other functional failure (for example reset occurrence oscillator
frequency deviation, LCD levels).
The test results are given in the Table 42.
Table 42. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Injected current on all 5 V tolerant (FT) pins
IINJ
Injected current on BOOT0
Injected current on any other pin
Negative
injection
Positive
injection
-5 (1)
NA
-0
NA
-5
(1)
Unit
mA
+5
1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
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6.3.13
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL
compliant.
Table 43. I/O static characteristics
Symbol
VIL
VIH
Parameter
Conditions
Input low level voltage
Input high level voltage
Ilkg
I/O Schmitt trigger voltage
hysteresis(2)
Input leakage current
(4)
Typ
Max
-
-
BOOT0
-
-
0.14 VDD(2)
TC I/O
0.45 VDD+0.38(2)
-
-
FT I/O
(2)
-
-
+0.56(2)
-
-
0.39 VDD+0.59
0.15 VDD
0.3
Unit
VDD(1)(2)
TC and FT I/O
BOOT0
Vhys
Min
V
TC and FT I/O
-
10% VDD(3)
-
BOOT0
-
0.01
-
VSS ≤ VIN ≤ VDD
I/Os with LCD
-
-
±50
VSS ≤ VIN ≤ VDD
I/Os with analog
switches
-
-
±50
VSS ≤ VIN ≤ VDD
I/Os with analog
switches and LCD
-
-
±50
VSS ≤ VIN ≤ VDD
I/Os with USB
-
-
±250
VSS ≤ VIN ≤ VDD
TC and FT I/Os
-
-
±50
FT I/O
VDD ≤ VIN ≤ 5V
-
-
±10
μA
nA
RPU
Weak pull-up equivalent
resistor(5)(1)
VIN = VSS
30
45
60
kΩ
RPD
Weak pull-down equivalent
resistor(5)
VIN = VDD
30
45
60
kΩ
CIO
I/O pin capacitance
-
-
5
-
pF
1. Tested in production
2. Data based on design simulation only. Not tested in production.
3. With a minimum of 200 mV.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
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Electrical characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA with the non-standard VOL/VOH specifications given in Table 44.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD(Σ) (see Table 12).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS(Σ) (see Table 12).
Output voltage levels
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 14. All I/Os are CMOS and TTL compliant.
Table 44. Output voltage characteristics
Symbol
Parameter
VOL(1)(2)
Output low level voltage for an I/O pin
VOH(3)(2)
Output high level voltage for an I/O pin
VOL
(3)(4)
Conditions
Min
Max
IIO = +8 mA
2.7 V < VDD < 3.6 V
-
0.4
VDD-0.4
-
-
0.45
VDD-0.45
-
-
1.3
VDD-1.3
-
Output low level voltage for an I/O pin
IIO =+ 4 mA
1.65 V < VDD <
2.7 V
VOH (3)(4) Output high level voltage for an I/O pin
VOL(1)(4)
Output low level voltage for an I/O pin
VOH(3)(4)
Output high level voltage for an I/O pin
IIO = +20 mA
2.7 V < VDD < 3.6 V
Unit
V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. Tested in production.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data, not tested in production.
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 19 and
Table 45, respectively.
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 14.
Table 45. I/O AC characteristics(1)
OSPEEDRx
[1:0] bit
value(1)
Symbol
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
fmax(IO)out
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
00
01
Fmax(IO)out Maximum frequency(3)
10
Output rise and fall time
Fmax(IO)out Maximum frequency(3)
11
-
Max(2)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
400
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
400
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
625
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
625
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
2
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
1
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
125
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
250
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
10
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
2
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
25
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
125
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
50
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
8
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
30
Conditions
fmax(IO)out
tf(IO)out
tr(IO)out
Min
Parameter
tf(IO)out
tr(IO)out
Output rise and fall time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
-
Unit
kHz
ns
MHz
ns
MHz
ns
MHz
ns
8
-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx
reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design. Not tested in production.
3. The maximum frequency is defined in Figure 19.
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Electrical characteristics
Figure 19. I/O AC characteristics definition
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6.3.14
AIC
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 46)
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 14.
Table 46. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
VIL(NRST)(1)
NRST input low level
voltage
-
-
-
0.3 VDD
VIH(NRST)(1)
NRST input high
level voltage
-
0.39 VDD+0.59
-
-
VOL(NRST)(1)
NRST output low
level voltage
Unit
V
IOL = 2 mA
2.7 V < VDD < 3.6 V
-
IOL = 1.5 mA
1.65 V < VDD < 2.7 V
-
-
0.4
Vhys(NRST)(1)
NRST Schmitt trigger
voltage hysteresis
-
-
10%VDD(2)
-
mV
RPU
Weak pull-up
equivalent resistor(3)
VIN = VSS
30
45
60
kΩ
VF(NRST)(1)
NRST input filtered
pulse
-
-
-
50
ns
VNF(NRST)(3)
NRST input not
filtered pulse
-
350
-
-
ns
1. Data based on design simulation only. Not tested in production.
2. With a minimum of 200 mV.
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is around 10%.
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Figure 20. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 46. Otherwise the reset will not be taken into account by the device.
6.3.15
TIM timer characteristics
The parameters given in the Table 47 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 47. TIMx(1) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
Parameter
Timer resolution time
Conditions
fTIMxCLK = 32 MHz
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 32 MHz
Timer resolution
-
16-bit counter clock
period when internal clock
is selected (timer’s
prescaler disabled)
-
tMAX_COUNT Maximum possible count
Min
Max
Unit
1
-
tTIMxCLK
31.25
-
ns
0
fTIMxCLK/2
MHz
0
16
MHz
16
bit
65536
tTIMxCLK
2048
μs
1
fTIMxCLK = 32 MHz 0.0312
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 32 MHz
-
134.2
s
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
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6.3.16
Electrical characteristics
Communications interfaces
I2C interface characteristics
The STM32L15xxC product line I2C interface meets the requirements of the standard I2C
communication protocol with the following restrictions: SDA and SCL are not “true” opendrain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin
and VDD is disabled, but is still present.
The I2C characteristics are described in Table 48. Refer also to Section 6.3.13: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 48. I2C characteristics
Symbol
Parameter
Standard mode
I2C(1)(2)
Fast mode I2C(1)(2)
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
th(SDA)
SDA data hold time
-
3450(3)
-
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
Start condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated Start condition
setup time
4.7
-
0.6
-
tsu(STO)
Stop condition setup time
4.0
-
0.6
-
μs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
μs
Cb
Capacitive load for each bus
line
-
400
-
400
pF
tSP
Pulse width of spikes that
are suppressed by the
analog filter
0
50(4)
0
50(4)
ns
μs
ns
μs
1. Guaranteed by design, not tested in production.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
4. The minimum width of the spikes filtered by the analog filter is above tSP(max).
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Figure 21. I2C bus AC waveforms and measurement circuit
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1. RS = series protection resistor.
2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
4. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 49. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400
0x801B
300
0x8024
200
0x8035
100
0x00A0
50
0x0140
20
0x0320
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external
components used to design the application.
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Electrical characteristics
SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 14.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 50. SPI characteristics(1)
Symbol
Min
Max(2)
Master mode
-
16
Slave mode
-
16
Slave transmitter
-
12(3)
-
6
ns
%
Parameter
Conditions
fSCK
1/tc(SCK)
SPI clock frequency
tr(SCK)(2)
tf(SCK)(2)
SPI clock rise and fall time
Capacitive load: C = 30 pF
SPI slave input clock duty cycle
Slave mode
30
70
tsu(NSS)
NSS setup time
Slave mode
4tHCLK
-
th(NSS)
NSS hold time
Slave mode
2tHCLK
-
SCK high and low time
Master mode
tSCK/2−5
tSCK/2+3
Master mode
5
-
Slave mode
6
-
Master mode
5
-
Slave mode
5
-
DuCy(SCK)
tw(SCKH)(2)
tw(SCKL)(2)
tsu(MI)(2)
tsu(SI)(2)
th(MI)
Data input setup time
(2)
(2)
th(SI)
Data input hold time
ta(SO)(4)
Data output access time
Slave mode
0
3tHCLK
tv(SO) (2)
Data output valid time
Slave mode
-
33
tv(MO)(2)
Data output valid time
Master mode
-
6.5
Slave mode
17
-
Master mode
0.5
-
th(SO)(2)
th(MO)
(2)
Data output hold time
Unit
MHz
ns
1. The characteristics above are given for voltage range 1.
2. Based on characterization, not tested in production.
3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK))
ranging between 40 to 60%.
4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Figure 22. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tS (NSS)
SCK Input
CPHA= 0
CPOL=0
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
O P
tr(SCK)
tf(SCK)
th(SO)
MS B O
BI 6 O
tdis(SO)
LSB O
tsu(SI)
MOSI
I NP
B I 1 IN
M SB IN
LSB IN
th(SI)
ai14134c
Figure 23. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tS (NSS)
SCK Input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
O P
MS B O
tsu(SI)
MOSI
I NP
th(NSS)
th(SO)
BI 6 O
tr(SCK)
tf(SCK)
tdis(SO)
LSB O
th(SI)
B I 1 IN
M SB IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics
Figure 24. SPI timing diagram - master mode(1)
High
NSS input
SCK Input
CPHA= 0
CPOL=0
SCK Input
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
MS BIN
BI 6 IN
LSB IN
th(MI)
MOSI
O P
M SB O
BI 1 O
tv(MO)
LSB O
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
USB characteristics
The USB interface is USB-IF certified (full speed).
Table 51. USB startup time
Symbol
(1)
tSTARTUP
Parameter
USB transceiver startup time
Max
Unit
1
μs
1. Guaranteed by design, not tested in production.
Table 52. USB DC electrical characteristics
Conditions
Min.(1)
Max.(1)
Unit
-
3.0
3.6
V
0.2
-
Differential common mode range Includes VDI range
0.8
2.5
Single ended receiver threshold
1.3
2.0
-
0.3
2.8
3.6
Symbol
Parameter
Input levels
VDD
USB operating voltage
VDI(2)
VCM
Differential input sensitivity
(2)
VSE(2)
I(USB_DP, USB_DM)
-
V
Output levels
VOL(3)
VOH
RL of 1.5 kΩ to 3.6 V(4)
Static output level low
(3)
Static output level high
RL of 15 kΩ to VSS
(4)
V
1. All the voltages are measured from the local ground potential.
2. Guaranteed by characterization, not tested in production.
3. Tested in production.
4. RL is the load connected on the USB drivers.
Figure 25. USB timings: definition of data signal rise and fall time
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Table 53. USB: full speed electrical characteristics
Driver characteristics(1)
Symbol
96/133
Parameter
Conditions
Min
Max
Unit
tr
Rise time(2)
CL = 50 pF
4
20
ns
tf
(2)
CL = 50 pF
4
20
ns
Fall Time
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Table 53. USB: full speed electrical characteristics (continued)
Driver characteristics(1)
Symbol
trfm
VCRS
Parameter
Conditions
Min
Max
Unit
tr/tf
90
110
%
1.3
2.0
V
Rise/ fall time matching
Output signal crossover voltage
1. Guaranteed by design, not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
6.3.17
I2S characteristics
Table 54. I2S characteristics
Symbol
fMCK
Parameter
Conditions
Min
Max
256 x 8K 256xFs (1)
I2S Main Clock Output
Master data: 32 bits
-
64xFs
Slave data: 32 bits
-
64xFs
30
70
fCK
I2S clock frequency
DCK
I2S clock frequency duty cycle Slave receiver, 48KHz
tr(CK)
I2S clock rise time
tf(CK)
I2S clock fall time
tv(WS)
-
WS valid time
Master mode
4
24
th(WS)
WS hold time
Master mode
0
-
tsu(WS)
WS setup time
Slave mode
15
-
th(WS)
WS hold time
Slave mode
0
-
tsu(SD_MR) Data input setup time
Master receiver
8
-
tsu(SD_SR) Data input setup time
Slave receiver
9
-
th(SD_MR)
Master receiver
5
-
Slave receiver
4
-
th(SD_SR)
MHz
MHz
%
8
Capacitive load CL=30pF
Data input hold time
Unit
8
tv(SD_ST)
Data output valid time
Slave transmitter
(after enable edge)
-
64
th(SD_ST)
Data output hold time
Slave transmitter
(after enable edge)
22
-
tv(SD_MT) Data output valid time
Master transmitter
(after enable edge)
-
12
th(SD_MT) Data output hold time
Master transmitter
(after enable edge)
8
-
ns
1. The maximum for 256xFs is 8 MHz
Note:
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
Figure 26. I2S slave timing diagram (Philips protocol)(1)
CK Input
tc(CK)
CPOL = 0
CPOL = 1
tw(CKH)
th(WS)
tw(CKL)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
Bitn transmit
tsu(SD_SR)
LSB transmit
th(SD_SR)
LSB receive(2)
SDreceive
th(SD_ST)
MSB receive
Bitn receive
LSB receive
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 27. I2S master timing diagram (Philips protocol)(1)
tf(CK)
tr(CK)
CK output
tc(CK)
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS)
th(WS)
tw(CKL)
WS output
tv(SD_MT)
SDtransmit
LSB transmit(2)
MSB transmit
LSB receive(2)
LSB transmit
th(SD_MR)
tsu(SD_MR)
SDreceive
Bitn transmit
th(SD_MT)
MSB receive
Bitn receive
LSB receive
ai14884b
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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6.3.18
Electrical characteristics
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 56 are guaranteed by design.
Table 55. ADC clock frequency
Symbol
fADC
Parameter
Conditions
2.4 V ≤ VDDA ≤ 3.6 V
Voltage
range 1 & 2
ADC clock
frequency
Min
VREF+ = VDDA
16
VREF+ < VDDA
VREF+ > 2.4 V
8
VREF+ < VDDA
VREF+ ≤ 2.4 V
1.8 V ≤ VDDA ≤ 2.4 V
Max
0.480
4
VREF+ = VDDA
8
VREF+ < VDDA
4
Voltage range 3
Unit
MHz
4
Table 56. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
-
1.8
-
3.6
VDDA
Power supply
VREF+
Positive reference voltage
2.4 V ≤ VDDA ≤ 3.6 V
VREF+ must be below or
equal to VDDA
1.8(1)
-
VDDA
VREF-
Negative reference voltage
-
-
VSSA
-
IVDDA
Current on the VDDA input pin
-
-
1000
1450
Peak
-
Average
-
-
0(4)
-
VREF+
Direct channels
-
-
1
Multiplexed channels
-
-
0.76
Direct channels
-
-
1.07
Multiplexed channels
-
-
0.8
Direct channels
-
-
1.23
Multiplexed channels
-
-
0.89
Direct channels
-
-
1.45
Multiplexed channels
-
-
1
IVREF(2)
VAIN
Current on the VREF input pin
Conversion voltage
12-bit sampling rate
10-bit sampling rate
fS
8-bit sampling rate
6-bit sampling rate
range(3)
DocID022799 Rev 7
400
700
Unit
V
μA
450
V
Msps
Msps
Msps
Msps
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Electrical characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 56. ADC characteristics (continued)
Symbol
tS(5)
Parameter
Sampling time
tCONV
Total conversion time
(including sampling time)
CADC
Internal sample and hold
capacitor
fTRIG
External trigger frequency
Regular sequencer
fTRIG
External trigger frequency
Injected sequencer
RAIN
(6)
Conditions
Min
Typ
Max
Direct channels
2.4 V ≤ VDDA ≤ 3.6 V
0.25
-
-
Multiplexed channels
2.4 V ≤ VDDA ≤ 3.6 V
0.56
-
-
Direct channels
1.8 V ≤ VDDA ≤ 2.4 V
0.56
-
-
Multiplexed channels
1.8 V ≤ VDDA ≤ 2.4 V
1
-
-
-
4
-
384
1/fADC
fADC = 16 MHz
1
-
24.75
μs
-
Unit
μs
4 to 384 (sampling phase) +12
(successive approximation)
1/fADC
Direct channels
-
Multiplexed channels
-
12-bit conversions
-
-
6/8/10-bit conversions
-
-
12-bit conversions
-
-
Tconv+2 1/fADC
6/8/10-bit conversions
-
-
Tconv+1 1/fADC
-
-
50
kΩ
Signal source impedance
16
-
pF
-
Tconv+1 1/fADC
Tconv
1/fADC
tlat
Injection trigger conversion
latency
fADC = 16 MHz
219
-
281
ns
-
3.5
-
4.5
1/fADC
tlatr
Regular trigger conversion
latency
fADC = 16 MHz
156
-
219
ns
-
2.5
-
3.5
1/fADC
-
-
-
3.5
μs
tSTAB
Power-up time
1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage
reference).
2. The current consumption through VREF is composed of two parameters:
- one constant (max 300 μA)
- one variable (max 400 μA), only during sampling time + 2 first conversion pulses
So, peak consumption is 300+400 = 700 μA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 μA at
1Msps
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pin descriptions for further details.
4. VSSA or VREF- must be tied to ground.
5. Minimum sampling time is reached for an external input impedance limited to a value as defined in Table 58: RAIN max for
fADC = 16 MHz
6. External impedance has another high value limitation when using short sampling time as defined in Table 58: RAIN max for
fADC = 16 MHz
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Table 57. ADC accuracy(1)(2)
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
ENOB
Effective number of bits
SINAD
Signal-to-noise and
distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
ENOB
Effective number of bits
SINAD
Signal-to-noise and
distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
Test conditions
2.4 V ≤ VDDA ≤ 3.6 V
2.4 V ≤ VREF+ ≤ 3.6 V
fADC = 8 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
2.4 V ≤ VDDA ≤ 3.6 V
VDDA = VREF+
fADC = 16 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Finput=10kHz
1.8 V ≤ VDDA ≤ 2.4 V
VDDA = VREF+
fADC = 8 MHz or 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Finput=10kHz
Min(3)
Typ
Max(3)
-
2
4
-
1
2
-
1.5
3.5
-
1
2
-
1.7
3
9.2
10
-
57.5
62
-
57.5
62
-
-
-70
-65
9.2
10
-
57.5
62
-
57.5
62
-
-
70
65
-
4
6.5
-
2
4
-
4
6
-
1
2
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
-
1.5
3
ET
Total unadjusted error
-
2
3
EO
Offset error
-
1
1.5
EG
Gain error
-
1.5
2
ED
Differential linearity error
-
1
2
EL
Integral linearity error
-
1
1.5
2.4 V ≤ VDDA ≤ 3.6 V
1.8 V ≤ VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
1.8 V ≤ VDDA ≤ 2.4 V
1.8 V ≤ VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Unit
LSB
bits
dB
bits
dB
LSB
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as
this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to
add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Based on characterization, not tested in production.
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Electrical characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Figure 28. ADC accuracy characteristics
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Figure 29. Typical connection diagram using the ADC
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1. Refer to Table 58: RAIN max for fADC = 16 MHz for the value of RAIN and Table 56: ADC characteristics
for the value of CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
102/133
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Figure 30. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion
Sampling (n cycles)
Conversion (12 cycles)
ADC clock
Iref+
700µA
300µA
Table 58. RAIN max for fADC = 16 MHz(1)
RAIN max (kΩ)
Ts
(cycles)
Ts
(μs)
Multiplexed channels
Direct channels
2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.6 V
1.8 V < VDDA < 2.4 V
4
0.25
Not allowed
Not allowed
0.7
Not allowed
9
0.5625
0.8
Not allowed
2.0
1.0
16
1
2.0
0.8
4.0
3.0
24
1.5
3.0
1.8
6.0
4.5
48
3
6.8
4.0
15.0
10.0
96
6
15.0
10.0
30.0
20.0
192
12
32.0
25.0
50.0
40.0
384
24
50.0
50.0
50.0
50.0
1. Guaranteed by design, not tested in production.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 12 depending on
whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic
(good quality). They should be placed as close as possible to the chip.
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110
Electrical characteristics
6.3.19
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
DAC electrical specifications
Data guaranteed by design, not tested in production, unless otherwise specified.
Table 59. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
1.8
-
3.6
1.8
-
3.6
Unit
VDDA
Analog supply voltage
VREF+
Reference supply
voltage
VREF-
Lower reference voltage
IDDVREF+(1)
Current consumption on No load, middle code (0x800)
VREF+ supply
No load, worst code (0x000)
VREF+ = 3.3 V
-
130
220
-
220
350
IDDA(1)
Current consumption on No load, middle code (0x800)
VDDA supply
No load, worst code (0xF1C)
VDDA = 3.3 V
-
210
320
-
320
520
RL(2)
Resistive load
5
-
-
kΩ
CL(2)
Capacitive load
-
-
50
pF
RO
Output impedance
DAC output buffer OFF
12
16
20
kΩ
DAC output buffer ON
0.2
-
VDDA – 0.2
V
DAC output buffer OFF
0.5
-
VREF+ –
1LSB
mV
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
1.5
3
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
1.5
3
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
2
4
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
2
4
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
±10
±25
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
±5
±8
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
±1.5
±5
VDAC_OUT
DNL
INL
(1)
(1)
Offset
Offset1(1)
104/133
V
VSSA
DAC output buffer ON
μA
Voltage on DAC_OUT
output
Differential non
linearity(3)
Integral non
(1)
VREF+ must always be below
VDDA
linearity(4)
Offset error at code
0x800 (5)
Offset error at code
0x001(6)
DocID022799 Rev 7
LSB
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Table 59. DAC characteristics (continued)
Symbol
Parameter
Conditions
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
Offset error temperature DAC output buffer OFF
dOffset/dT(1)
coefficient (code 0x800) V
= 3.3V
Min
Typ
Max
-20
-10
0
Unit
μV/°C
DDA
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer ON
0
20
50
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
+0.1 / -0.2%
+0.2 / -0.5%
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
+0 / -0.2%
+0 / -0.4%
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer OFF
-10
-2
0
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer ON
-40
-8
0
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
12
30
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
8
12
tSETTLING
Settling time (full scale:
for a 12-bit code
transition between the
CL ≤ 50 pF, RL ≥ 5 kΩ
lowest and the highest
input codes till
DAC_OUT reaches final
value ±1LSB
-
7
12
μs
Update rate
Max frequency for a
correct DAC_OUT
change (95% of final
value) with 1 LSB
variation in the input
code
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
1
Msps
tWAKEUP
Wakeup time from off
state (setting the ENx bit
CL ≤ 50 pF, RL ≥ 5 kΩ
in the DAC Control
(8)
register)
-
9
15
μs
PSRR+
VDDA supply rejection
ratio (static DC
measurement)
-
-60
-35
dB
Gain(1)
dGain/dT(1)
TUE(1)
Gain error(7)
Gain error temperature
coefficient
Total unadjusted error
CL ≤ 50 pF, RL ≥ 5 kΩ
%
μV/°C
LSB
1. Data based on characterization results.
2. Connected between DAC_OUT and VSSA.
3. Difference between two consecutive codes - 1 LSB.
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Electrical characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
6. Difference between the value measured at Code (0x001) and the ideal value.
7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON.
8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Figure 31. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RL
DAC_OUTx
12-bit
digital to
analog
converter
CL
ai17157V2
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.20
Operational amplifier characteristics
Table 60. Operational amplifier characteristics
Symbol
CMIR
VIOFFSET
Condition(1)
Min(2)
Typ
Max(2)
-
0
-
VDD
Maximum
calibration range
-
-
-
±15
After offset
calibration
-
-
-
±1.5
-
-
-
±40
-
-
-
±80
-
-
1
-
-
10
Parameter
Common mode input range
Input offset voltage
ΔVIOFFSET
Input offset voltage Normal mode
drift
Low-power mode
IIB
Input current bias
ILOAD
Drive current
IDD
Consumption
CMRR
Common mode
rejection ration
mV
Dedicated input
106/133
General purpose
input
75 °C
Normal mode
-
-
-
500
Low-power mode
-
-
-
100
-
100
220
-
30
60
Normal mode
Low-power mode
Unit
No load,
quiescent mode
Normal mode
-
-
-85
-
Low-power mode
-
-
-90
-
DocID022799 Rev 7
μV/°C
nA
μA
μA
dB
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Table 60. Operational amplifier characteristics (continued)
Symbol
PSRR
Condition(1)
Parameter
Power supply
rejection ratio
Normal mode
Low-power mode
Normal mode
GBW
Bandwidth
Low-power mode
Normal mode
Low-power mode
SR
Slew rate
RL
Resistive load
CL
Capacitive load
VOHSAT
High saturation
voltage
VDD<2.4 V
Max(2)
-
-85
-
-
-90
-
400
1000
3000
150
300
800
200
500
2200
70
150
800
VDD>2.4 V
(between 0.1 V and
VDD-0.1 V)
-
700
-
Low-power mode
VDD>2.4 V
-
100
-
-
300
-
-
50
-
Normal mode
55
100
-
Low-power mode
65
110
-
4
-
-
20
-
-
-
-
50
VDD100
-
-
VDD-50
-
-
-
-
100
-
-
50
Low-power mode
Open loop gain
VDD>2.4 V
Typ
Normal mode
Normal mode
AO
DC
Min(2)
Normal mode
Low-power mode
VDD<2.4 V
VDD<2.4 V
-
Normal mode
Low-power mode
Normal mode
ILOAD = max or
RL = min
Unit
dB
kHZ
V/ms
dB
kΩ
pF
mV
VOLSAT
Low saturation
voltage
ϕm
Phase margin
-
-
60
-
°
GM
Gain margin
-
-
-12
-
dB
tOFFTRIM
Offset trim time: during calibration,
minimum time needed between two
steps to have 1 mV accuracy
-
-
1
-
ms
Normal mode
CL ≤ 50 pf,
RL ≥ 4 kΩ
-
10
-
Low-power mode
CL ≤ 50 pf,
RL ≥ 20 kΩ
-
tWAKEUP
Low-power mode
Wakeup time
μs
30
-
1. Operating conditions are limited to junction temperature (0 °C to 105 °C) when VDD is below 2 V. Otherwise, the operating
temperature range is 105 °C to -40 °C.
2. Data based on characterization results, not tested in production.
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Electrical characteristics
6.3.21
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Temperature sensor characteristics
Table 61. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C ±5 °C
VDDA= 3 V ±10 mV
0x1FF8 00FA - 0x1FF8 00FB
TS_CAL2
TS ADC raw data acquired at
temperature of 110 °C ±5 °C
VDDA= 3 V ±10 mV
0x1FF8 00FE - 0x1FF8 00FF
Table 62. Temperature sensor characteristics
Symbol
TL
Parameter
(1)
Min
Typ
Max
Unit
-
±1
±2
°C
1.48
1.61
1.75
mV/°C
612
626.8
641.5
mV
Current consumption
-
3.4
6
μA
Startup time
-
-
10
ADC sampling time when reading the
temperature
4
-
-
VSENSE linearity with temperature
Avg_Slope(1)
Average slope
Voltage at 110°C
V110
I
(3)
DDA(TEMP)
tSTART
(3)
TS_temp(4)(3)
±5°C(2)
μs
1. Guaranteed by characterization, not tested in production.
2. Measured at VDD = 3 V ±10 mV. V110 ADC conversion result is stored in the TS_CAL2 byte.
3. Guaranteed by design, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.
6.3.22
Comparator
Table 63. Comparator 1 characteristics
Symbol
Conditions
Min(1)
Typ
Max(1)
Unit
3.6
V
VDDA
Analog supply voltage
-
1.65
R400K
R400K value
-
-
400
-
R10K
R10K value
-
-
10
-
Comparator 1 input
voltage range
-
0.6
-
VDDA
Comparator startup time
-
-
7
10
-
-
3
10
-
-
±3
±10
VIN
tSTART
td
Voffset
108/133
Parameter
Propagation
delay(2)
Comparator offset
DocID022799 Rev 7
kΩ
V
μs
mV
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Electrical characteristics
Table 63. Comparator 1 characteristics (continued)
Symbol
dVoffset/dt
ICOMP1
Min(1)
Typ
Max(1)
Unit
VDDA = 3.6 V
Comparator offset
VIN+ = 0 V
variation in worst voltage
VIN- = VREFINT
stress conditions
TA = 25 °C
0
1.5
10
mV/1000 h
Current consumption(3)
-
160
260
nA
Parameter
Conditions
-
1. Based on characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.
Table 64. Comparator 2 characteristics
Symbol
VDDA
VIN
Parameter
Min
Analog supply voltage
-
1.65
-
3.6
V
Comparator 2 input voltage range
-
0
-
VDDA
V
Fast mode
-
15
20
Slow mode
-
20
25
1.65 V ≤ VDDA ≤ 2.7 V
-
1.8
3.5
2.7 V ≤ VDDA ≤ 3.6 V
-
2.5
6
1.65 V ≤ VDDA ≤ 2.7 V
-
0.8
2
2.7 V ≤ VDDA ≤ 3.6 V
-
1.2
4
-
±4
±20
mV
VDDA = 3.3V
TA = 0 to 50 °C
V- =VREFINT,
3/4 VREFINT,
1/2 VREFINT,
1/4 VREFINT.
-
15
30
ppm
/°C
Fast mode
-
3.5
5
Slow mode
-
0.5
2
tSTART
Comparator startup time
td slow
Propagation delay(2) in slow mode
td fast
Propagation delay(2) in fast mode
Voffset
Comparator offset error
dThreshold/ Threshold voltage temperature
dt
coefficient
ICOMP2
Typ Max(1) Unit
Conditions
Current consumption(3)
μs
μA
1. Based on characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
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110
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6.3.23
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
LCD controller
The STM32L15xxC embeds a built-in step-up converter to provide a constant LCD
reference voltage independently from the VDD voltage. An external capacitor Cext must be
connected to the VLCD pin to decouple this converter.
Table 65. LCD controller characteristics
Symbol
Parameter
Min
Typ
Max
VLCD
LCD external voltage
-
-
3.6
VLCD0
LCD internal reference voltage 0
-
2.6
-
VLCD1
LCD internal reference voltage 1
-
2.73
-
VLCD2
LCD internal reference voltage 2
-
2.86
-
VLCD3
LCD internal reference voltage 3
-
2.98
-
VLCD4
LCD internal reference voltage 4
-
3.12
-
VLCD5
LCD internal reference voltage 5
-
3.26
-
VLCD6
LCD internal reference voltage 6
-
3.4
-
VLCD7
LCD internal reference voltage 7
-
3.55
-
0.1
-
2
Supply current at VDD = 2.2 V
-
3.3
-
Supply current at VDD = 3.0 V
-
3.1
-
Cext
ILCD(1)
RHtot(2)
VLCD external capacitance
Unit
V
μF
μA
Low drive resistive network overall value
5.28
6.6
7.92
MΩ
RL(2)
High drive resistive network total value
192
240
288
kΩ
V44
Segment/Common highest level voltage
-
-
VLCD
V
V34
Segment/Common 3/4 level voltage
-
3/4 VLCD
-
V23
Segment/Common 2/3 level voltage
-
2/3 VLCD
-
V12
Segment/Common 1/2 level voltage
-
1/2 VLCD
-
V13
Segment/Common 1/3 level voltage
-
1/3 VLCD
-
V14
Segment/Common 1/4 level voltage
-
1/4 VLCD
-
V0
Segment/Common lowest level voltage
0
-
-
Segment/Common level voltage error
TA = -40 to 85 °C
-
-
± 50
ΔVxx(3)
V
mV
1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD
connected.
2. Guaranteed by design, not tested in production.
3. Based on characterization, not tested in production.
110/133
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
7
Package characteristics
7.1
Package mechanical data
Package characteristics
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 32. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline
C
!
!
!
3%!4).'
0,!.%
#
MM
'!5'%0,!.%
,
$
!
+
CCC #
,
$
$
0).
)$%.4)&)#!4)/.
%
%
%
B
E
,?-%?6
1. Drawing is not to scale.
DocID022799 Rev 7
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132
Package characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 66. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical
data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
-
12.000
-
-
0.4724
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
-
12.000
-
-
0.4724
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 33. LQFP100 recommended footprint
75
51
76
50
0.5
0.3
16.7
14.3
100
26
1.2
1
25
12.3
16.7
ai14 06
1. Dimensions are in millimeters.
112/133
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Package characteristics
Marking of engineering samples
The following figure shows the engineering sample marking for the LQFP100 package. Only
the information field containing the engineering sample marking is shown.
Figure 34. LQFP100 package top view
(QJLQHHULQJVDPSOHPDUNLQJ
(6
069
DocID022799 Rev 7
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132
Package characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Figure 35. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline
C
!
!
!
3%!4).'
0,!.%
#
MM
'!5'%0,!.%
!
CCC #
+
,
$
,
$
$
0).
)$%.4)&)#!4)/.
%
E
7?-%?6
1. Drawing is not to scale.
114/133
%
%
B
DocID022799 Rev 7
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Package characteristics
Table 67. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
11.800
12.000
12.200
0.4646
0.4724
0.4803
D1
9.800
10.000
10.200
0.3858
0.3937
0.4016
D3
-
7.500
-
-
0.2953
-
E
11.800
12.000
12.200
0.4646
0.4724
0.4803
E1
9.800
10.000
10.200
0.3858
0.3937
0.4016
E3
-
7.500
-
-
0.2953
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
K
0.0
3.5
7.0
0.0
3.5
7.0
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 36. LQFP64 recommended footprint
48
33
0.3
4
12.7
32
0.5
10.3
10.3
64
17
1.2
1
16
7.8
12.7
ai14 0
1. Dimensions are in millimeters.
DocID022799 Rev 7
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132
Package characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Marking of engineering samples
The following figure shows the engineering sample marking for the LQFP64 package. Only
the information field containing the engineering sample marking is shown.
Figure 37. LQFP64 package top view
(QJLQHHULQJVDPSOHPDUNLQJ
(6
069
1. Samples marked “ES” are to be considered as “Engineering Samples”:i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in
production.Only if ST has authorized in writing the customer qualification Engineering Samples can be
used for reliability qualification trials.
116/133
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Package characteristics
Figure 38. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline
C
!
!
!
3%!4).'
0,!.%
#
MM
'!5'%0,!.%
CCC #
+
!
$
$
,
,
$
0).
)$%.4)&)#!4)/.
%
%
%
B
E
"?-%?6
1. Drawing is not to scale.
DocID022799 Rev 7
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132
Package characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 68. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
A
Min
Typ
1.600
A1
0.050
A2
1.350
b
0.170
c
0.090
D
8.800
D1
6.800
D3
0.0630
0.150
0.0020
0.0059
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
9.000
9.200
0.3465
0.3543
0.3622
7.000
7.200
0.2677
0.2756
0.2835
0.0079
5.500
0.2165
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
5.500
0.2165
e
0.500
0.0197
L
0.450
0.600
L1
k
0.750
0.0177
0.0236
1.000
0°
3.5°
7°
0°
3.5°
0.080
Figure 39. LQFP48 recommended footprint
0.50
1.20
0.30
25
36
37
24
0.20
7.30
5.80
7.30
48
13
12
1
1.20
5.80
.70
ai14 11b
1. Dimensions are in millimeters.
DocID022799 Rev 7
7°
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
.70
0.0295
0.0394
ccc
118/133
Max
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Package characteristics
Marking of engineering samples
The following figure shows the engineering sample marking for the LQFP48 package. Only
the information field containing the engineering sample marking is shown.
Figure 40. LQFP48 package top view
$ATECODE9EAR7EEK
9EAR
7EEK
2EVISIONCODE
-36
DocID022799 Rev 7
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132
Package characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Figure 41. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline
3LQLGHQWLILHU
ODVHUPDUNLQJDUHD
'
$
(
(
7
GGG
$
6HDWLQJ
SODQH
E
H
'HWDLO<
'
([SRVHGSDG
DUHD
<
'
/
&[ƒ
SLQFRUQHU
(
5W\S
'HWDLO=
=
$%B0(B9
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
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Package characteristics
Table 69. UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm,
0.5 mm pitch package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
0.000
0.020
0.050
0.0000
0.0008
0.0020
D
6.900
7.000
7.100
0.2717
0.2756
0.2795
E
6.900
7.000
7.100
0.2717
0.2756
0.2795
D2
5.500
5.600
5.700
0.2165
0.2205
0.2244
E2
5.500
5.600
5.700
0.2165
0.2205
0.2244
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
T
b
0.152
0.200
0.0060
0.250
e
0.300
0.0079
0.0098
0.500
0.0118
0.0197
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 42. UFQFPN48 recommended footprint
7.30
48
37
1
36
6.20
0.20
7.30
6.20
5.60
5.80
5.60
0.30
12
25
13
0.55
24
5.80
0.50
0.75
ai156 7
1. Dimensions are in millimeters.
DocID022799 Rev 7
121/133
132
Package characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Marking of engineering samples
The following figure shows the engineering sample marking for the UFQFPN48 package.
Only the information field containing the engineering sample marking is shown.
Figure 43. UFQFPN48 package top view
$ATECODE9EAR7EEK
9EAR
7EEK
2EVISIONCODE
-36
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Package characteristics
Figure 44. UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid array package
outline
= 6HDWLQJSODQH
GGG =
$ $ $
$ $
(
H
$EDOO
$EDOO
LGHQWLILHU LQGH[DUHD
)
;
(
$
)
'
'
H
<
0
%277209,(:
‘EEDOOV
‘ HHH 0 = < ;
‘ III 0 =
7239,(:
$&B0(B9
1. Drawing is not to scale.
Table 70. UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid array package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.460
0.530
0.600
0.0181
0.0209
0.0236
A1
0.050
0.080
0.110
0.0020
0.0031
0.0043
A2
0.400
0.450
0.500
0.0157
0.0177
0.0197
A3
0.080
0.130
0.180
0.0031
0.0051
0.0071
A4
0.270
0.320
0.370
0.0106
0.0126
0.0146
b
0.200
0.250
0.300
0.0079
0.0098
0.0118
D
6.950
7.000
7.050
0.2736
0.2756
0.2776
D1
5.450
5.500
5.550
0.2146
0.2165
0.2185
E
6.950
7.000
7.050
0.2736
0.2756
0.2776
E1
5.450
5.500
5.550
0.2146
0.2165
0.2185
e
F
0.500
0.700
0.750
0.0197
0.800
0.0276
0.0295
0.0315
ddd
0.100
0.0039
eee
0.150
0.0059
fff
0.050
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID022799 Rev 7
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132
Package characteristics
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Figure 45. WLCSP63, 0.400 mm pitch wafer level chip size package outline
E
BBB
!"ALLLOCATION
&
'
$ETAIL!
E
E
'
!
!
&
E
!
"OTTOMVIEW
"UMBSIDE
3IDEVIEW
!
!
"UMP
&RONTVIEW
!
FFF
$
3EATINGPLANE
$ETAIL!
ROTATED %
!REFERENCE
LOCATION
BBB
4OPVIEW
7AFERBACK3IDE
"5(@.&
1. Drawing is not to scale.
124/133
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STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Package characteristics
Table 71. WLCSP63, 0.400 mm pitch wafer level chip size package mechanical data
inches(1)
millimeters
Symbol
A
Min
Typ
Max
Min
Typ
Max
0.540
0.570
0.600
0.0213
0.0224
0.0236
A1
0.190
0.0075
A2
0.380
0.0150
A3
0.025
0.0010
Øb
0.240
0.270
0.300
0.0094
0.0106
0.0118
D
3.193
3.228
3.263
0.1257
0.1271
0.1285
E
4.129
4.164
4.199
0.1626
0.1639
0.1653
e
0.400
0.0157
e1
2.400
0.0945
e2
3.200
0.1260
F
0.414
0.0163
G
0.482
0.0190
aaa
0.100
0.0039
bbb
0.100
0.0039
ccc
0.100
0.0039
ddd
0.050
0.0020
eee
0.050
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID022799 Rev 7
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132
Package characteristics
7.2
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
•
TA max is the maximum ambient temperature in °C,
•
ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 72. Thermal characteristics
Symbol
ΘJA
126/133
Parameter
Value
Thermal resistance junction-ambient
UFBGA100 - 7 x 7 mm
59
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch
43
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch
46
Thermal resistance junction-ambient
WLCSP63 - 0.400 mm pitch
49
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch
55
Thermal resistance junction-ambient
UFQFPN48 - 7 x 7 mm / 0.5 mm pitch
32
DocID022799 Rev 7
Unit
°C/W
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Package characteristics
Figure 46. Thermal resistance
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ϮϱϬϬ͘ϬϬ
ϮϬϬϬ͘ϬϬ
&ŽƌďŝĚĚĞŶĂƌĞĂ
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W ;ŵtͿ
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/4)3[PP
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7.2.1
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D^ϯϭϰϬϱsϰ
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DocID022799 Rev 7
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132
Part numbering
8
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Part numbering
Table 73. STM32L15xxC ordering information scheme
Example:
STM32
L 151 R C
T
6
D xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
L = Low-power
Device subfamily
151: Devices without LCD
152: Devices with LCD
Pin count
C = 48 pins
U = 63 pins
R = 64 pins
V = 100 pins
Flash memory size
C = 256 Kbytes of Flash memory
Package
H = BGA
T = LQFP
Y = WLCSP
U = UFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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9
Revision History
Revision History
Table 74. Document revision history
Date
Revision
21-Feb-2012
1
Initial release.
2
Added WLCSP63 package.
Updated Figure 1: Ultra-low-power STM32L162xC block diagram.
Changed maximum number of touch sensing channels to 34, and
updated Table 2: Ultralow power STM32L15xxC device features and
peripheral counts.
Added Table 4: Functionalities depending on the working mode (from
Run/active down to standby), and Table 3: CPU frequency range
depending on dynamic voltage scaling.
Updated Section 3.10: ADC (analog-to-digital converter) to add
Section 3.10.1: Temperature sensor and Section 3.10.2: Internal
voltage reference (VREFINT).
Updated Figure 3: STM32L162VC LQFP100 pinout.
Table 10: STM32L15xxC pin definitions: updated name of reference
manual in footnote 5.
Changed I2C1_SMBAI into I2C1_SMBA in Table 10: STM32L15xxC
pin definitions.
Modified PB10/11/12 for AFIO4 alternate function, and replaced
LBAR by NADV for AFIO12 in Table 10: Alternate function
input/output.
Removed caution note below Figure 8: Power supply scheme.
Added Note 2 in Table 15: Embedded reset and power control block
characteristics.
Updated Table 14: General operating conditions.
Updated Table 22: Typical and maximum current consumptions in
Stop mode and added Note 6. Updated Table 23: Typical and
maximum current consumptions in Standby mode. Updated tWUSTOP
in Table : .
Updated Table 26: Peripheral current consumption.
Updated Table 60: SPI characteristics, added Note 1 and Note 3,
and applied Note 2 to tr(SCK), tf(SCK), tw(SCKH), tw(SCKL), tsu(MI), tsu(SI),
th(MI), and th(SI).
Added Table 61: I2S characteristics, Figure 29: I2S slave timing
diagram (Philips protocol)(1) and Figure 30: I2S master timing
diagram (Philips protocol)(1).
Updated Table 72: Temperature sensor characteristics.
Added Figure 40: Thermal resistance.
12-Oct-2012
Changes
DocID022799 Rev 7
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132
Revision History
STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC
Table 74. Document revision history (continued)
Date
01-Feb-2013
02-Sep-2013
130/133
Revision
Changes
3
Removed AHB1/AHB2 and corrected typo on APB1/APB2
in:Figure 1: Ultra-low-power STM32L15xxC block diagram-lowpower STM32L162xC block diagram
Updated “OP amp” line in Table 5: Functionalities depending on the
working mode (from Run/active down to standby)
Added IWDG and WWDG rows in Table 5: Functionalities depending
on the working mode (from Run/active down to standby)
Updated address range in Table 7: Internal voltage reference
measured values
The comment "HSE = 16 MHz(2) (PLL ON for fHCLK above 16
MHz)" replaced by "fHSE = fHCLK up to 16 MHz included, fHSE =
fHCLK/2 above 16 MHz (PLL ON)(2)” in table Table 20: Current
consumption in Sleep mode
replaced pin names D7,C7,C6,C8,B8,A8 respectively by
D11,D10,C12,B12,A12,A11 in column UFBGA100 of Table 9:
STM32L15xxC pin definitionsAdded more alternate functions
supported on pin K3 and M4 for UFBGA100 package in Table 9:
STM32L15xxC pin definitions
Added part number STM32L151CC in Table 1: Device summary
Updated Stop mode current to 1.5 μA in Ultra-low-power platform
Updated entire Section 7: Package characteristics
4
Removed UFBGA132 and LQFP144 packages
Removed first sentence in Section : I2C interface characteristics
Added Section Table 6.: VLCD rail decoupling
Added VRAIL functions in Table 9: STM32L15xxC pin definitions
Updated PH0-OSC_IN and PH1-OSC_OUT type in Table 9:
STM32L15xxC pin definitions.
Added Table 6.1.7: Optional LCD power supply scheme.
Updated consumption data in Table 6.3.4: Supply current
characteristics
Updated Table 10: Pin loading conditions
Updated Table 11: Pin input voltage Updated Table 18: Typical
application with a 32.768 kHz crystal
Updated Table 20: Recommended NRST pin protection
Table 21: I2C bus AC waveforms and measurement circuitUpdated
Table 29: Typical connection diagram using the ADC and
definition of symbol “RAIN” in Table 56: ADC characteristics
Updated dThreshold/dt conditions in Table 64: Comparator 2
characteristics.
Updated Table 46: Thermal resistance.
Added D2 and E2 in Table 69: UFQFPN48 – ultra thin fine pitch quad
flat pack no-lead 7 × 7 mm, 0.5 mm pitch package mechanical data
Fixed columns inversion in Table 67: LQFP64, 10 x 10 mm 64-pin
low-profile quad flat package mechanical data and Table 70:
UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid array
package mechanical data
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Revision History
Table 74. Document revision history (continued)
Date
12-Nov-2013
Revision
Changes
5
Updated Section 3.15: Touch sensing.
Added VDD= 1.71 to 1.8 V operating power supply range in Table 5:
Functionalities depending on the working mode (from Run/active
down to standby)
Renamed "I/O Level" to "I/O structure" in Table 9: STM32L15xxC pin
definitions, added the I/O structure for PC14, PC15, PC3, PH0, PH1,
PA3, PA4, PA5, PB0, PE7, PE8, PE9, PE10, NRST and BOOT0
Updated Table 11: Voltage characteristics added row
Updated Table 12: Current characteristics replaced with the one
inside STM32L15xxBxxA datasheet.
Updated Table 14: General operating conditions, footnote and added
row.
Updated Table 16: Embedded internal reference voltage calibration
values and moved inside Section 6.3.3: Embedded internal reference
voltage
Updated Section 6.3.4: Supply current characteristics.
Updated Table 18: Current consumption in Run mode, code with data
processing running from Flash.
Updated Table 19: Current consumption in Run mode, code with data
processing running from RAM.
Created Section 6.3.5: Wakeup time from low-power mode.
Updated Chapter 6.3.6: External clock source characteristics.
Updated Table 27: High-speed external user clock characteristics.
Moved Figure 15: High-speed external clock source AC timing
diagram after Table 27: High-speed external user clock
characteristics.
Updated Table 29: HSE oscillator characteristics.
Updated Section 6.3.11: Electrical sensitivity characteristics (title).
Updated Section 6.3.12: I/O current injection characteristics.
Updated Table 42: I/O current injection susceptibility and added
footnote.
Updated Table 43: I/O static characteristics
Updated Section 6.3.14: NRST pin characteristics.
Updated Table 56: ADC characteristics.
Added footnote(5) and (6) in Table 56: ADC characteristics
Updated THD values and added 4 more rows ENOB, SINAD, SNR,
THD in Table 57: ADC accuracy
Updated “SDA data hold time” and “SDA and SCL rise time” values
and added “Pulse width of spikes that are suppressed by the analog
filter” row in Table 48: I2C characteristics
Updated direct channels VDDA range in Table 58: RAIN max for
fADC = 16 MHz
Moved Table 61: Temperature sensor calibration values and moved
inside Section 6.3.21: Temperature sensor characteristics
Updated IDD (WU from Standby) unit in Table 24: Typical and
maximum current consumptions in Standby mode.
Updated Table 67: LQFP64, 10 x 10 mm 64-pin low-profile quad flat
package mechanical data
Updated Chapter 8: Part numbering (title).
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Revision History
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Table 74. Document revision history (continued)
Date
09-Dec-2013
13-Mar-2014
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Revision
Changes
6
Apply footnote 1 also to VDD= 1.8 to 2.0 V in Table 3: Functionalities
depending on the operating power supply range.
Updated Iinj pin in Table 12: Current characteristics.
Added Input Voltage in Table 14: General operating conditions.
Updated Input leakage current conditions in Table 43: I/O static
characteristics
Removed minimum value for fSin Table 56: ADC characteristics.
Removed Finput for ENOB,SINAD,SNR,THD in Table 57: ADC
accuracy.
Added tolerance for TS_CAL1 and TS_CAL2 in Table 61:
Temperature sensor calibration values.
7
Updated Chapter 3.7: Memories, Table 25: Peripheral current
consumption : updated Flash value, Table 42: I/O current injection
susceptibility, Table 43: I/O static characteristics:added BOOT0 pin
Table 46: NRST pin characteristics, Chapter 2.2: Ultra-low-power
device continuum. removed figures “Power supply and reference
decoupling (VREF+ not connected to VDDA) and “Power supply and
reference decoupling(VREF+ connected to VDDA). Updated Table 18:
Current consumption in Run mode, code with data processing
running from Flash, Table 19: Current consumption in Run mode,
code with data processing running from RAM, Table 20: Current
consumption in Sleep mode, Table 23: Typical and maximum current
consumptions in Stop mode, Table 24: Typical and maximum current
consumptions in Standby mode.
Updated Section 6.3.1: General operating conditions.
Updated Table 59: DAC characteristics
Added marking for LQFP48/UFQFPN48 packages
Updated Table 46: NRST pin characteristics
Updated Table 43: I/O static characteristics
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