Am29LV640D/Am29LV641D Data Sheet

Am29LV640D/Am29LV641D Data Sheet
Am29LV640D/Am29LV641D
Data Sheet (Retired Product)
Am29LV640D/Am29LV641D Cover Sheet
This product has been retired and is not recommended for designs. For new and current designs, S29GL064N supercedes
Am29LV640D/Am29LV641D. This is the factory-recommended migration path. Please refer to the S29GL-N data sheet for
specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 22366
Revision C
Amendment 7
Issue Date February 26, 2009
Da ta
Shee t
(Retire d
Pro duct)
This page left intentionally blank.
2
Am29LV640D/Am29LV641D
22366_C7 February 26, 2009
DATA SHEET
Am29LV640D/Am29LV641D
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileIO™ Control
This product has been retired and is not recommended for designs. For new and current designs, S29GL064N supercedes
Am29LV640D/Am29LV641D. This is the factory-recommended migration path. Please refer to the S29GL-N data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 3.0 to 3.6 volt read, erase, and program operations
■ VersatileIO™ control
— Device generates output voltages and tolerates data
input voltages on the DQ input/outputs as determined
by the voltage on VIO
■ High performance
— Access times as fast as 90 ns
■ Manufactured on 0.23 µm process technology
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
■ Minimum 1 million erase cycle guarantee per sector
■ Package options
— 48-pin TSOP (Am29LV641DH/DL only)
— 56-pin SSOP (Am29LV640DH/DL only)
— 63-ball Fine-Pitch BGA (Am29LV640DU only)
— 64-ball Fortified BGA (Am29LV640DU only)
■ CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sect27
■ SecSi (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number
— May be programmed and locked at the factory or by
the customer
— Accessible through a command sequence
■ Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
■ Ultra low power consumption (typical values at 3.0 V,
5 MHz)
— 9 mA typical active read current
— 26 mA typical erase/program current
— 200 nA typical standby mode current
■ Flexible sector architecture
— One hundred twenty-eight 32 Kword sectors
■ Sector Protection
— A hardware method to lock a sector to prevent
program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
■ Compatibility with JEDEC standards
— or that is not being erased, then resumes the erase
operation
■ Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
■ Ready/Busy# pin (RY/BY#) (Am29LV640DU in FBGA
package only)
— Provides a hardware method of detecting program or
erase cycle completion
■ Hardware reset pin (RESET#)
— Hardware method to reset the device for reading array
data
■ WP# pin (Am29LV641DH/DL in TSOP,
Am29LV640DH/DL in SSOP only)
— At VIL, protects the first or last 32 Kword sector,
regardless of sector protect/unprotect status
— At VIH, allows removal of sector protection
— An internal pull up to VCC is provided
■ ACC pin
— Accelerates programming time for higher throughput
during system production
■ Program and Erase Performance (VHH not applied to
the ACC input pin)
— Word program time: 11 µs typical
— Sector erase time: 0.9 s typical for each 32 Kword
sector
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 22366 Rev: C Amendment 7
Issue Date: February 26, 2009
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29LV640DU/Am29LV641DU is a 64 Mbit, 3.0
Volt (3.0 V to 3.6 V) single power supply flash memory
device organized as 4,194,304 words. Data appears
on DQ0-DQ15. The device is designed to be programmed in-system with the standard system 3.0 volt
VCC supply. A 12.0 volt VPP is not required for program
or erase operations. You can also program this device
in standard EPROM programmers.
Access times of 90 and 120 ns are available for applications where VIO ≥ VCC. An access time 120 ns are
available for applications where VIO < VCC. The device
is offered in 48-pin TSOP, 56-pin SSOP, 63-ball
Fine-Pitch BGA and 64-ball Fortified BGA packages.
To eliminate bus contention, each device has separate
chip enable (CE#), write enable (WE#), and output enable (OE#) controls.
Each device requires only a single 3.0 Volt power
supply (3.0 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm — an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm — an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on V IO. V IO is available in two
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various system environments.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
2
gle) status bits. After a program or erase cycle completes, the device is ready to read array data or accept
another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This is achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin can be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read boot-up firmware from the Flash memory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode, power consumption is greatly reduced.
The SecSi (Secured Silicon) Sector provides an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The Write Protect (WP#) feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector is still protected even during accelerated programming.
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to VHH, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during system production, but may also be used in the field if desired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA/fBGA Packages ......... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
RY/BY#: Ready/Busy# ............................................................ 30
DQ6: Toggle Bit I .................................................................... 30
Table 1. Device Bus Operations .....................................................10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
VersatileIO™ (VIO) Control ..................................................... 10
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 11
Figure 7. Maximum Negative Overshoot Waveform ..................... 33
Figure 8. Maximum Positive Overshoot Waveform....................... 33
Accelerated Program Operation ......................................................11
Autoselect Functions .......................................................................11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 12
Table 2. Sector Address Table ........................................................12
Autoselect Mode ..................................................................... 16
Table 3. Autoselect Codes, (High Voltage Method) .......................16
Sector Group Protection and Unprotection ............................. 17
Table 4. Sector Group Protection/Unprotection Address Table .....17
Write Protect (WP#) ................................................................ 18
Temporary Sector Group Unprotect ....................................... 18
Figure 1. Temporary Sector Group Unprotect Operation................ 18
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 19
SecSi (Secured Silicon) Sector Flash Memory Region .......... 20
Table 5. SecSi Sector Contents ......................................................20
Hardware Data Protection ...................................................... 20
Low VCC Write Inhibit .....................................................................20
Write Pulse “Glitch” Protection ........................................................21
Logical Inhibit ..................................................................................21
Power-Up Write Inhibit ....................................................................21
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 6. CFI Query Identification String .......................................... 21
System Interface String................................................................... 22
Table 8. Device Geometry Definition .............................................. 22
Table 9. Primary Vendor-Specific Extended Query ........................ 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................ 23
Reset Command ..................................................................... 24
Autoselect Command Sequence ............................................ 24
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 24
Word Program Command Sequence ..................................... 24
Unlock Bypass Command Sequence ..............................................25
Figure 3. Program Operation .......................................................... 25
Chip Erase Command Sequence ........................................... 25
Sector Erase Command Sequence ........................................ 26
Erase Suspend/Erase Resume Commands ........................... 26
Figure 4. Erase Operation............................................................... 27
Command Definitions ............................................................. 28
Command Definitions...................................................................... 28
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling ................................................................. 29
Figure 6. Toggle Bit Algorithm........................................................ 30
DQ2: Toggle Bit II ................................................................... 31
Reading Toggle Bits DQ6/DQ2 ............................................... 31
DQ5: Exceeded Timing Limits ................................................ 31
DQ3: Sector Erase Timer ....................................................... 31
Table 11. Write Operation Status ................................................... 32
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. ICC1 Current vs. Time (Showing
Active and Automatic Sleep Currents) ........................................... 35
Figure 10. Typical ICC1 vs. Frequency ............................................ 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Test Setup.................................................................... 36
Table 12. Test Specifications ......................................................... 36
Key to Switching Waveforms. . . . . . . . . . . . . . . . 36
Figure 12. Input Waveforms and
Measurement Levels...................................................................... 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Read-Only Operations ........................................................... 37
Figure 13. Read Operation Timings ............................................... 37
Hardware Reset (RESET#) .................................................... 38
Figure 14. Reset Timings ............................................................... 38
Erase and Program Operations .............................................. 39
Figure 15. Program Operation Timings..........................................
Figure 16. Accelerated Program Timing Diagram..........................
Figure 17. Chip/Sector Erase Operation Timings ..........................
Figure 18. Data# Polling Timings
(During Embedded Algorithms)......................................................
Figure 19. Toggle Bit Timings
(During Embedded Algorithms)......................................................
Figure 20. DQ2 vs. DQ6.................................................................
40
40
41
42
43
43
Temporary Sector Unprotect .................................................. 44
Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 44
Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 45
Alternate CE# Controlled Erase and Program Operations ..... 46
Figure 23. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 47
Erase And Programming Performance . . . . . . . 48
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 48
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49
SSO056—56-Pin Shrink Small Outline Package (SSOP) ...... 49
FBE063—63-Ball Fine-Pitch Ball Grid Array
(FBGA) 12 x 11 mm package ................................................. 50
LAA064—64-Ball Fortified Ball Grid Array
(FBGA) 13 x 11 mm package ................................................. 51
TS 048—48-Pin Standard TSOP ............................................ 52
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 5. Data# Polling Algorithm ................................................... 29
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
3
D A T A
S H E E T
PRODUCT SELECTOR GUIDE
Part Number
Am29LV640D/Am29LV641D
VCC = 3.0–3.6 V, VIO = 3.0–5.0 V
Speed Option
90R
120R
VCC = 3.0–3.6 V, VIO = 1.8–2.9 V
121R
Max Access Time (ns)
90
120
CE# Access Time (ns)
90
120
OE# Access Time (ns)
35
50
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15
RY/BY# (Note 1)
VCC
Sector Switches
VSS
WE#
WP#
(Note 2)
ACC
VIO
Erase Voltage
Generator
RESET#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Timer
A0–A21
Address Latch
STB
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
Notes:
1. RY/BY# is only available in the FBGA package.
2. WP# is only available in the TSOP and SSOP packages.
4
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
NC
NC
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
February 26, 2009 22366C7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin Standard TSOP
(Am29LV641DH/DL only)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Pin SSOP
(Am29LV640DH/DL
only)
Am29LV640D/Am29LV641D
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A16
VIO
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
RESET#
WE#
A20
A21
A8
A9
A10
A11
A12
A13
A14
A15
NC
NC
NC
NC
A16
VIO
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
5
D A T A
S H E E T
CONNECTION DIAGRAM
63-Ball Fine-Pitch BGA (FBGA)
Top View, Balls Facing Down
(Am29LV640DU only)
A8
B8
L8
M8
NC
NC
NC*
NC*
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
NC
NC
A13
A12
A14
A15
A16
VIO
DQ15
VSS
NC*
NC*
C6
D6
E6
F6
G6
H6
J6
K6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A2
D5
E5
F5
G5
H5
J5
K5
RESET#
A21
A19
DQ5
DQ12
VCC
DQ4
C4
D4
E4
F4
G4
H4
J4
K4
RY/BY#
ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
C3
D3
E3
F3
G3
H3
J3
K3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
C2
D2
E2
F2
G2
H2
J2
K2
L2
M2
OE#
VSS
NC*
NC*
L1
M1
NC*
NC*
A3
NC*
A1
C5
WE#
A4
A2
A1
A0
CE#
B1
* Balls are shorted together via the substrate but not connected to the die.
NC*
6
NC*
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
CONNECTION DIAGRAMS
64-Ball Fortified BGA (FBGA)
Top View, Balls Facing Down
(Am29LV640DU only)
A8
B8
C8
D8
E8
F8
G8
H8
RFU
RFU
RFU
VIO
VSS
RFU
RFU
RFU
A7
B7
C7
D7
E7
F7
G7
H7
A13
A12
A14
A15
A16
NC
DQ15
VSS
A6
B6
C6
D6
E6
F6
G6
H6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
WE#
RESET#
A21
A19
DQ5
DQ12
VCC
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY#
ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
A3
B3
C3
D3
E3
F3
G3
H3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A2
B2
C2
D2
E2
F2
G2
H2
A3
A4
A2
A1
A0
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
H1
RFU
RFU
RFU
RFU
RFU
VIO
RFU
RFU
Special Handling Instructions for
FBGA/fBGA Packages
Special handling is required for Flash Memory products
in BGA packages.
February 26, 2009 22366C7
Flash memory devices in BGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
Am29LV640D/Am29LV641D
7
D A T A
PIN DESCRIPTION
A0–A21
S H E E T
LOGIC SYMBOL
= 22 Addresses inputs
22
DQ0–DQ15 = 16 Data inputs/outputs
A0–A21
CE#
= Chip Enable input
OE#
= Output Enable input
WE#
= Write Enable input
WP#
= Hardware Write Protect input (N/A on
FBGA)
WP#
ACC
= Acceleration Input
ACC
RESET#
= Hardware Reset Pin input
RESET#
RY/BY#
= Ready/Busy output (FBGA only)
VIO
VCC
= 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
CE#
16
DQ0–DQ15
OE#
WE#
VIO
= Output Buffer power
VSS
= Device Ground
NC
= Pin Not Connected Internally
RFU
= Reserved for Future Use
8
RY/BY#
Note: WP# is not available on the FBGA package. RY/BY#
is not available on the TSOP and SSOP packages.
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29LV640D
Am29LV641D
H
90R
E
I
N
OPTIONAL PROCESSING
Blank = Standard Processing
N
= 32-byte ESN devices
(Contact an AMD representative for more information)
TEMPERATURE RANGE
I
F
=
=
Industrial (–40°C to +85°C)
Industrial (–40°C to +85°C) with Pb-Free Package
PACKAGE TYPE
E
Z
PC
=
=
=
WH
=
48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
56-Pin Shrink Small Outline Package (SSO056)
64-Ball Fortified Ball Grid Array
1.0 mm pitch, 13 x 11 mm package (LAA064)
63-Ball Fine-Pitch Ball Grid Array
0.80 mm pitch, 11 x 12 mm package (FBE063)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0)
H
L
U
=
=
=
Uniform sector device, highest address sector protected
Uniform sector device, lowest address sector protected
Uniform sector device (WP# not available)
DEVICE NUMBER/DESCRIPTION
Am29LV640DU/DH/DL, Am29LV641DH/DL
64 Megabit (4 M x 16-Bit) CMOS Uniform Sector Flash Memory with VersatileIO™ Control
3.0 Volt-only Read, Program, and Erase
Valid Combinations for
TSOP and SSOP Packages
Speed/VIO Range
AM29LV640DH90R,
ZI, ZF
AM29LV640DL90R
90 ns,
VIO = 3.0 V – 5.0 V
AM29LV641DH90R,
EI, FI, EF
AM29LV641DL90R
AM29LV640DH120R,
ZI, ZF
AM29LV640DL120R
120 ns,
VIO = 3.0 V – 5.0 V
AM29LV641DH120R,
EI, FI, EF
AM29LV641DL120R
AM29LV640DH121R,
ZI, ZF
AM29LV640DL121R
120 ns,
VIO = 1.8 V – 2.9 V
AM29LV641DH121R,
EI, FI, EF
AM29LV641DL121R
Note: LV640/641DH & DL have WP#, but no RY/BY#. U designator
in base part number replaced by H or L.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
February 26, 2009 22366C7
Valid Combinations for BGA Packages
Order Number
Package Marking
PCI,
L640DU90N
PCF
I, F
AM29LV640DU90R
WHI,
L640DU90R
WHF
PCI,
L640DU12N
PCF
AM29LV640DU120R
WHI,
L640DU12R
WHF
I, F
PCI,
L640DU21N
PCF
AM29LV640DU121R
WHI,
L640DU21R
WHF
Note: LV640DU has RY/BY#, but no WP#.
Speed/
VIO Range
90 ns, VIO =
3.0 V – 5.0 V
120 ns, VIO =
3.0 V – 5.0 V
120 ns, VIO =
1.8 V – 2.9 V
Note: Reverse pinout TSOP (TSR048) packages are not Note: offered
for new designs. For 128 Mb requirements, the S29GL128N product is
recommended as a single-device substitute for the 64 Mb + 64 Mb
clamshell design; please refer to the S29GL128N data sheet for
specifications and ordering information.
Am29LV640D/Am29LV641D
9
D A T A
S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information
needed to execute the command. The contents of the
Table 1.
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting
output. The following subsections describe each operation in further detail.
Device Bus Operations
CE#
OE#
WE#
RESET#
WP#
ACC
Addresses
(Note 2)
DQ0–
DQ15
Read
L
L
H
H
X
X
AIN
DOUT
Write (Program/Erase)
L
H
L
H
(Note 3)
X
AIN
(Note 4)
Accelerated Program
L
H
L
H
(Note 3)
VHH
AIN
(Note 4)
VCC ±
0.3 V
X
X
VCC ±
0.3 V
X
H
X
High-Z
Output Disable
L
H
H
H
X
X
X
High-Z
Reset
X
X
X
L
X
X
X
High-Z
Sector Group Protect (Note 2)
L
H
L
VID
H
X
SA, A6 = L,
A1 = H, A0 = L
(Note 4)
Sector Group Unprotect
(Note 2)
L
H
L
VID
H
X
SA, A6 = H,
A1 = H, A0 = L
(Note 4)
Temporary Sector Group
Unprotect
X
X
X
VID
H
X
AIN
(Note 4)
Operation
Standby
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the first or last sector is protected or unprotected as
determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped
from the factory (The SecSi Sector may be factory protected depending on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2, on page 20).
VersatileIO™ (VIO) Control
Requirements for Reading Array Data
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on V IO. V IO is available in two
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various system environments.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE#
should remain at VIH.
For example, a VIO of 4.5–5.0 volts allows for I/O at the
5 volt level, driving and receiving signals to and from
other 5 V devices on the same data bus.
10
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Requirements for Reading Array Data” on
page 11 for more infor mation. Refer to the AC
“Read-Only Operations” on page 38 table for timing
specifications and to Figure 13, on page 38 for the timing diagram. I CC1 in the “DC Characteristics” on
page 35 table represents the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word instead of four. The “Word
Program Command Sequence” on page 25 has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 on page 13 indicates
the address space that each sector occupies.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily intended to allow faster manufacturing throughput during system production.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal operation. Note that the ACC pin must not be at VHH for
operations other than accelerated programming, or
device damage may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the “Autoselect Mode” on page 17
February 26, 2009 22366C7
S H E E T
and “Autoselect Command Sequence” on page 25 for
more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device is in the standby mode, but the
standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes before it is
ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
ICC3 in the table “DC Characteristics” on page 35 represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t ACC +
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC4 in the table “DC Characteristics” on page 35 represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. To ensure data integrity,
the operation that was interrupted should be reinitiated
once the device is ready to accept another command
sequence.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current is
greater.
Am29LV640D/Am29LV641D
11
D A T A
S H E E T
within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.
The RESET# pin can be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the table “AC Characteristics” on page 38 for
RESET# parameters and to Figure 14, on page 39 for
the timing diagram.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
Table 2.
12
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Sector Address Table (Sheet 1 of 4)
Sector
A21
A20
A19
A18
A17
A16
A15
16-bit Address Range
(in hexadecimal)
SA0
0
0
0
0
0
0
0
000000–007FFF
SA1
0
0
0
0
0
0
1
008000–00FFFF
SA2
0
0
0
0
0
1
0
010000–017FFF
SA3
0
0
0
0
0
1
1
018000–01FFFF
SA4
0
0
0
0
1
0
0
020000–027FFF
SA5
0
0
0
0
1
0
1
028000–02FFFF
SA6
0
0
0
0
1
1
0
030000–037FFF
SA7
0
0
0
0
1
1
1
038000–03FFFF
SA8
0
0
0
1
0
0
0
040000–047FFF
SA9
0
0
0
1
0
0
1
048000–04FFFF
SA10
0
0
0
1
0
1
0
050000–057FFF
SA11
0
0
0
1
0
1
1
058000–05FFFF
SA12
0
0
0
1
1
0
0
060000–067FFF
SA13
0
0
0
1
1
0
1
068000–06FFFF
SA14
0
0
0
1
1
1
0
070000–077FFF
SA15
0
0
0
1
1
1
1
078000–07FFFF
SA16
0
0
1
0
0
0
0
080000–087FFF
SA17
0
0
1
0
0
0
1
088000–08FFFF
SA18
0
0
1
0
0
1
0
090000–097FFF
SA19
0
0
1
0
0
1
1
098000–09FFFF
SA20
0
0
1
0
1
0
0
0A0000–0A7FFF
SA21
0
0
1
0
1
0
1
0A8000–0AFFFF
SA22
0
0
1
0
1
1
0
0B0000–0B7FFF
SA23
0
0
1
0
1
1
1
0B8000–0BFFFF
SA24
0
0
1
1
0
0
0
0C0000–0C7FFF
SA25
0
0
1
1
0
0
1
0C8000–0CFFFF
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
Table 2.
S H E E T
Sector Address Table (Sheet 2 of 4)
Sector
A21
A20
A19
A18
A17
A16
A15
16-bit Address Range
(in hexadecimal)
SA26
0
0
1
1
0
1
0
0D0000–0D7FFF
SA27
0
0
1
1
0
1
1
0D8000–0DFFFF
SA28
0
0
1
1
1
0
0
0E0000–0E7FFF
SA29
0
0
1
1
1
0
1
0E8000–0EFFFF
SA30
0
0
1
1
1
1
0
0F0000–0F7FFF
SA31
0
0
1
1
1
1
1
0F8000–0FFFFF
SA32
0
1
0
0
0
0
0
100000–107FFF
SA33
0
1
0
0
0
0
1
108000–10FFFF
SA34
0
1
0
0
0
1
0
110000–117FFF
SA35
0
1
0
0
0
1
1
118000–11FFFF
SA36
0
1
0
0
1
0
0
120000–127FFF
SA37
0
1
0
0
1
0
1
128000–12FFFF
SA38
0
1
0
0
1
1
0
130000–137FFF
SA39
0
1
0
0
1
1
1
138000–13FFFF
SA40
0
1
0
1
0
0
0
140000–147FFF
SA41
0
1
0
1
0
0
1
148000–14FFFF
SA42
0
1
0
1
0
1
0
150000–157FFF
SA43
0
1
0
1
0
1
1
158000–15FFFF
SA44
0
1
0
1
1
0
0
160000–167FFF
SA45
0
1
0
1
1
0
1
168000–16FFFF
SA46
0
1
0
1
1
1
0
170000–177FFF
SA47
0
1
0
1
1
1
1
178000–17FFFF
SA48
0
1
1
0
0
0
0
180000–187FFF
SA49
0
1
1
0
0
0
1
188000–18FFFF
SA50
0
1
1
0
0
1
0
190000–197FFF
SA51
0
1
1
0
0
1
1
198000–19FFFF
SA52
0
1
1
0
1
0
0
1A0000–1A7FFF
SA53
0
1
1
0
1
0
1
1A8000–1AFFFF
SA54
0
1
1
0
1
1
0
1B0000–1B7FFF
SA55
0
1
1
0
1
1
1
1B8000–1BFFFF
SA56
0
1
1
1
0
0
0
1C0000–1C7FFF
SA57
0
1
1
1
0
0
1
1C8000–1CFFFF
SA58
0
1
1
1
0
1
0
1D0000–1D7FFF
SA59
0
1
1
1
0
1
1
1D8000–1DFFFF
SA60
0
1
1
1
1
0
0
1E0000–1E7FFF
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
13
D A T A
Table 2.
14
S H E E T
Sector Address Table (Sheet 3 of 4)
Sector
A21
A20
A19
A18
A17
A16
A15
16-bit Address Range
(in hexadecimal)
SA61
0
1
1
1
1
0
1
1E8000–1EFFFF
SA62
0
1
1
1
1
1
0
1F0000–1F7FFF
SA63
0
1
1
1
1
1
1
1F8000–1FFFFF
SA64
1
0
0
0
0
0
0
200000–207FFF
SA65
1
0
0
0
0
0
1
208000–20FFFF
SA66
1
0
0
0
0
1
0
210000–217FFF
SA67
1
0
0
0
0
1
1
218000–21FFFF
SA68
1
0
0
0
1
0
0
220000–227FFF
SA69
1
0
0
0
1
0
1
228000–22FFFF
SA70
1
0
0
0
1
1
0
230000–237FFF
SA71
1
0
0
0
1
1
1
238000–23FFFF
SA72
1
0
0
1
0
0
0
240000–247FFF
SA73
1
0
0
1
0
0
1
248000–24FFFF
SA74
1
0
0
1
0
1
0
250000–257FFF
SA75
1
0
0
1
0
1
1
258000–25FFFF
SA76
1
0
0
1
1
0
0
260000–267FFF
SA77
1
0
0
1
1
0
1
268000–26FFFF
SA78
1
0
0
1
1
1
0
270000–277FFF
SA79
1
0
0
1
1
1
1
278000–27FFFF
SA80
1
0
1
0
0
0
0
280000–287FFF
SA81
1
0
1
0
0
0
1
288000–28FFFF
SA82
1
0
1
0
0
1
0
290000–297FFF
SA83
1
0
1
0
0
1
1
298000–29FFFF
SA84
1
0
1
0
1
0
0
2A0000–2A7FFF
SA85
1
0
1
0
1
0
1
2A8000–2AFFFF
SA86
1
0
1
0
1
1
0
2B0000–2B7FFF
SA87
1
0
1
0
1
1
1
2B8000–2BFFFF
SA88
1
0
1
1
0
0
0
2C0000–2C7FFF
SA89
1
0
1
1
0
0
1
2C8000–2CFFFF
SA90
1
0
1
1
0
1
0
2D0000–2D7FFF
SA91
1
0
1
1
0
1
1
2D8000–2DFFFF
SA92
1
0
1
1
1
0
0
2E0000–2E7FFF
SA93
1
0
1
1
1
0
1
2E8000–2EFFFF
SA94
1
0
1
1
1
1
0
2F0000–2F7FFF
SA95
1
0
1
1
1
1
1
2F8000–2FFFFF
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
Table 2.
S H E E T
Sector Address Table (Sheet 4 of 4)
Sector
A21
A20
A19
A18
A17
A16
A15
16-bit Address Range
(in hexadecimal)
SA96
1
1
0
0
0
0
0
300000–307FFF
SA97
1
1
0
0
0
0
1
308000–30FFFF
SA98
1
1
0
0
0
1
0
310000–317FFF
SA99
1
1
0
0
0
1
1
318000–31FFFF
SA100
1
1
0
0
1
0
0
320000–327FFF
SA101
1
1
0
0
1
0
1
328000–32FFFF
SA102
1
1
0
0
1
1
0
330000–337FFF
SA103
1
1
0
0
1
1
1
338000–33FFFF
SA104
1
1
0
1
0
0
0
340000–347FFF
SA105
1
1
0
1
0
0
1
348000–34FFFF
SA106
1
1
0
1
0
1
0
350000–357FFF
SA107
1
1
0
1
0
1
1
358000–35FFFF
SA108
1
1
0
1
1
0
0
360000–367FFF
SA109
1
1
0
1
1
0
1
368000–36FFFF
SA110
1
1
0
1
1
1
0
370000–377FFF
SA111
1
1
0
1
1
1
1
378000–37FFFF
SA112
1
1
1
0
0
0
0
380000–387FFF
SA113
1
1
1
0
0
0
1
388000–38FFFF
SA114
1
1
1
0
0
1
0
390000–397FFF
SA115
1
1
1
0
0
1
1
398000–39FFFF
SA116
1
1
1
0
1
0
0
3A0000–3A7FFF
SA117
1
1
1
0
1
0
1
3A8000–3AFFFF
SA118
1
1
1
0
1
1
0
3B0000–3B7FFF
SA119
1
1
1
0
1
1
1
3B8000–3BFFFF
SA120
1
1
1
1
0
0
0
3C0000–3C7FFF
SA121
1
1
1
1
0
0
1
3C8000–3CFFFF
SA122
1
1
1
1
0
1
0
3D0000–3D7FFF
SA123
1
1
1
1
0
1
1
3D8000–3DFFFF
SA124
1
1
1
1
1
0
0
3E0000–3E7FFF
SA125
1
1
1
1
1
0
1
3E8000–3EFFFF
SA126
1
1
1
1
1
1
0
3F0000–3F7FFF
SA127
1
1
1
1
1
1
1
3F8000–3FFFFF
Note: All sectors are 32 Kwords in size.
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
15
D A T A
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the autoselect
mode requires VID (8.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in
Table 3. In addition, when verifying sector protection,
Table 3.
Description
S H E E T
the sector address must appear on the appropriate
highest order address bits (see Table 2 on page 13).
Table 3 shows the remaining address bits that are
don’t care. When all necessary bits are set as required, the programming equipment may then read the
corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10 on page 29.
This method does not require VID. Refer to “Autoselect
Command Sequence” on page 25 for more information.
Autoselect Codes, (High Voltage Method)
CE# OE# WE#
A21
to
A15
A14
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ15 to DQ0
Manufacturer ID: AMD
L
L
H
X
X
VID
X
L
X
L
L
0001h
Device ID: LV640DU/H/L,
LV641DH/L
L
L
H
X
X
VID
X
L
X
L
H
22D7h
Sector Protection
Verification
L
L
H
SA
X
VID
X
L
X
H
L
XX01h (protected),
XX00h (unprotected)
SecSi Sector Indicator Bit
(DQ7), WP# protects
highest address sector
(LV640DH/641DH), or
no WP# (LV640DU)
L
L
H
X
X
VID
X
L
X
H
H
XX98h (factory locked),
XX18h (not factory locked)
SecSi Sector Indicator Bit
(DQ7), WP# protects
lowest address sector
(LV640DL/641DL)
L
L
H
X
X
VID
X
L
X
H
H
XX88h (factory locked),
XX08h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
16
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
Sector Group Protection and
Unprotection
S H E E T
Table 4.
Sector Group Protection/Unprotection
Address Table
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Table 4). The hardware sector
group unprotection feature re-enables both program
and erase operations in previously protected sector
groups. Sector group protection/unprotection is implemented via two methods.
Sector Group
A21–A17
SA0–SA3
00000
Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2, on page
20 shows the algorithms and Figure 22, on page 46
shows the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be
protected prior to the first sector group unprotect write
cycle.
The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the
device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.
It is possible to determine whether a sector group is
protected or unprotected. See “Autoselect Mode” on
page 17 for details.
SA4–SA7
00001
SA8–SA11
00010
SA12–SA15
00011
SA16–SA19
00100
SA20–SA23
00101
SA24–SA27
00110
SA28–SA31
00111
SA32–SA35
01000
SA36–SA39
01001
SA40–SA43
01010
SA44–SA47
01011
SA48–SA51
01100
SA52–SA55
01101
SA56–SA59
01110
SA60–SA63
01111
SA64–SA67
10000
SA68–SA71
10001
SA72–SA75
10010
SA76–SA79
10011
SA80–SA83
10100
SA84–SA87
10101
SA88–SA91
10110
SA92–SA95
10111
SA96–SA99
11000
SA100–SA103
11001
SA104–SA107
11010
SA108–SA111
11011
SA112–SA115
11100
SA116–SA119
11101
SA120–SA123
11110
SA124–SA127
11111
Note: All sector groups are 128 Kwords in size.
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting the first or last sector without
using VID.
If the system asserts VIL on the WP# pin, the device
disables program and erase functions in the first or last
sector independently of whether those sectors were
protected or unprotected using the method described
in “Sector Group Protection and Unprotection”. Note
February 26, 2009 22366C7
that if WP# is at VIL when the device is in the standby
mode, the maximum input load current is increased.
See the table in “DC Characteristics” on page 35.
If the system asserts VIH on the WP# pin, the device
reverts to whether the first or last sector was previously set to be protected or unprotected using the
method described in “Sector Group Protection and
Unprotection” on page 18.
Am29LV640D/Am29LV641D
17
D A T A
S H E E T
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 4 on page 18)).
START
This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID (8.5 V – 12.5 V). During
this mode, formerly protected sector groups can be
programmed or erased by selecting the sector group
addresses. Once VID is removed from the RESET#
pin, all the previously protected sector groups are
protected again. Figure 1, on page 19 shows the algorithm, and Figure 21, on page 45 shows the timing diagrams, for this feature.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unprotect
Completed (Note 2)
Notes:
1. All protected sector groups unprotected (If WP# = VIL,
the first or last sector remains protected).
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group
Unprotect Operation
18
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
START
START
PLSCNT = 1
RESET# = VID
Wait 1 μs
Temporary Sector
Group Unprotect
Mode
No
PLSCNT = 1
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 μs
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Group Unprotect
Mode
Yes
Yes
Set up sector
group address
No
Sector Group Protect:
Write 60h to sector
group address with
A6 = 0, A1 = 1,
A0 = 0
All sector
groups
protected?
Yes
Set up first sector
group address
Sector Group
Unprotect:
Write 60h to sector
group address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 µs
Increment
PLSCNT
No
Verify Sector Group
Protect: Write 40h
to sector group
address twith A6 = 0,
A1 = 1, A0 = 0
Reset
PLSCNT = 1
Read from
sector group address
with A6 = 0,
A1 = 1, A0 = 0
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector group
address with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
No
Yes
Protect
another
sector group?
Device failed
Yes
PLSCNT
= 1000?
No
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Group
Protect
Algorithm
Set up
next sector group
address
No
Data = 00h?
Yes
Last sector
group
verified?
No
Yes
Sector Group
Protect complete
Sector Group
Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Figure 2.
February 26, 2009 22366C7
In-System Sector Group Protect/Unprotect Algorithms
Am29LV640D/Am29LV641D
19
D A T A
SecSi (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 words in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.
AMD offers the device with the SecSi Sector either
factor y locke d or custom er lockable. The factory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize that
sector in any manner they choose. The customer-lockable version also has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
The SecSi sector address space in this device is allocated as shown in Table 5:
Table 5.
SecSi Sector
Address Range
000000h–000007h
000008h–00007Fh
SecSi Sector Contents
Standard
ExpressFlash
Factory Locked Factory Locked
ESN
ESN or
determined by
customer
Unavailable
Determined by
customer
Customer
Lockable
Determined by
customer
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s ExpressFlash service.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an alternative to the factory-locked version, the device can be ordered such that the customer may progra m and p rote ct the 128 -wo rd SecSi sector.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
You can protect the SecSi Sector area using one of the
following procedures:
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, on
page 20, except that RESET# may be at either VIH
or VID. This allows in-system protection of the SecSi
Sector without raising any device pin to a high voltage. Note that this method is only applicable to the
SecSi Sector.
■ Write the three-cycle Enter SecSi Sector Region
command sequence, then use the alternate method
of sector protection described in the “Sector Group
Protection and Unprotection” on page 18.
Once the SecSi Sector is programmed, locked, and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
Hardware Data Protection
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence” on page 25). After
the system writes the Enter SecSi Sector command
sequence, it may read the SecSi Sector by using the
addresses normally occupied by the first sector (SA0).
This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. A factory locked
device has an 8-word random ESN at addresses
000000h–000007h.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The devices are then shipped from AMD’s factory with the
20
S H E E T
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadver tent writes (refer to Table 10 on
page 29 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or
from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when V CC is
greater than VLKO.
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE#, do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward-and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system reads CFI information at the addresses
given in Table 6 on page 22 to Table 9 on page 24. To
Table 6.
terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 6 on page 22
to Table 9 on page 24 The system must write the reset
command to return the device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents.
CFI Query Identification String
Addresses (x16)
Data
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
February 26, 2009 22366C7
Description
Am29LV640D/Am29LV641D
21
D A T A
Table 7.
S H E E T
System Interface String
Addresses (x16)
Data
Description
1Bh
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
0004h
Typical timeout per single word write 2N µs
20h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
000Ah
Typical timeout per individual block erase 2N ms
22h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
0005h
Max. timeout for word write 2N times typical
24h
0000h
Max. timeout for buffer write 2N times typical
25h
0004h
Max. timeout per individual block erase 2N times typical
26h
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 8.
Device Geometry Definition
Addresses (x16)
Data
27h
0017h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0001h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
007Fh
0000h
0000h
0001h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
22
Description
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
Table 9.
S H E E T
Primary Vendor-Specific Extended Query
Addresses (x16)
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
0031h
Major version number, ASCII
44h
0033h
Minor version number, ASCII
45h
0000h
Address Sensitive Unlock (Bits 1-0)
00b = Required, 01b = Not Required
Silicon Revision Number (Bits 7-2) 000000b = 0.23 µm Process Technology
46h
0002h
Erase Suspend
00 = Not Supported, 01 = To Read Only, 02 = To Read & Write
47h
0004h
Sector Protect
00 = Not Supported, X = Number of sectors per group
48h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0004h
Sector Protect/Unprotect scheme
04 = 29LV800A mode
4Ah
0000h
Simultaneous Operation
00 = Not Supported, XX = Number of Sectors in Bank
4Bh
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
00B5h
4Eh
00C5h
ACC (Acceleration) Supply Minimum
Bits 7–4 = Hex Value in Volts, Bits 0–3 = BCD Value in 100 mV
ACC (Acceleration) Supply Maximum
Bits 7–4 = Hex Value in Volts, Bits 0–3 = BCD Value in 100 mV
Top/Bottom Boot Sector Flag
4Fh
000Xh
00h = Uniform Sector, No WP# Control
04h = Uniform Sector, WP# Protects Bottom Sector
05h = Uniform Sector, WP# Protects Top Sector
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 10 on page 29 defines the valid
register command sequences. Writing incorrect address and data values or writing them in the improper sequence, resets the device to reading array
data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to “AC Characteristics” on page 38 for timing diagrams.
February 26, 2009 22366C7
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See “Erase Suspend/Erase Resume Commands” on page 27, for more information.
Am29LV640D/Am29LV641D
23
D A T A
S H E E T
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See
the next section, Reset Command, for more information.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence:
See also “Requirements for Reading Array Data” on
page 11 in the Device Bus Operations section for
more information. The “Read-Only Operations” on
page 38 table provides the read parameters, and Figure 13, on page 38 shows the timing diagram.
■ A read cycle at address XX00h returns the manufacturer code.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the device entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 10 on page 29 shows the address and data requirements. This method is an alternative to that
shown in Table 3 on page 17, which is intended for
PROM programmers and requires VID on address pin
A9. The autoselect command sequence may be written to an address that is either in the read or
erase-suspend-read mode. The autoselect command
cannot be written while the device is actively programming or erasing.
24
■ A read cycle at address XX01h returns the device
code.
■ A read cycle to an address containing a sector
group address (SA), and the address 02h on A7–A0
returns 01h if the sector group is protected, or 00h
if it is unprotected. (Refer to Table 4 on page 18 for
valid sector addresses).
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 8-word random Electronic Serial Number (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the device to normal operation. Table 10 on page 29 shows
the address and data requirements for both command
sequences. See also “SecSi (Secured Silicon) Sector
Flash Memory Region” on page 21 for further information.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. The “Command Definitions”
on page 29 shows the address and data requirements
for the word program command sequence.
When the Embedded Program algorithm is complete,
the device returns to the read mode and addresses
are no longer latched. The system determines the status of the program operation by using DQ7, DQ6, or
RY/BY#. Refer to “Write Operation Status” on page 30
for information on these status bits.
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device returns to the read
mode, to ensure data integrity.
S H E E T
page 40 table in the AC Characteristics section for parameters, and Figure 15, on page 41 for timing diagrams.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was successful. However, a succeeding read shows that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
START
Write Program
Command Sequence
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 10 on page 29 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
The device offers accelerated program operations
through the ACC pin. When the system asserts VHH on
the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the
ACC pin to accelerate the operation. Note that the
ACC pin must not be at VHH for operations other than
accelerated programming, or device damage may result.
Figure 3 illustrates the algorithm for the program operation. Refer to the “Erase and Program Operations” on
February 26, 2009 22366C7
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note: See Table 10 on page 29, for program command
sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 10 on
page 29 shows the address and data requirements for
the chip erase command sequence.
Am29LV640D/Am29LV641D
25
D A T A
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” on page 30
for information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 4, on page 28 illustrates the algorithm for the
erase operation. Refer to the table “Erase and Program Operations” on page 40 in the AC Characteristics section for parameters, and Figure 17, on page 42
for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and
the sector erase command. Table 10 on page 29
shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section “DQ3:
Sector Erase Timer” on page 32.). The time-out be-
26
S H E E T
gins from the rising edge of the final WE# pulse in the
command sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6,
DQ2, or RY/BY#. Refer to “Write Operation Status” on
page 30 for information on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device returns to reading array data, to ensure data integrity.
Figure 4, on page 28 illustrates the algorithm for the
erase operation. Refer to the table “Erase and Program Operations” on page 40 in the AC Characteristics section for parameters, and Figure 17, on page 42
for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written
during the sector erase time-out, the device immediately terminates the time-out period and suspends the
erase operation.
After the erase operation is suspended, the device enters the erase-suspend-read mode. The system can
read data from or program data to any sector not selected for erasure. (The device “erase suspends” all
sectors selected for erasure.) Reading at any address
within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or
DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to “Write
Operation Status” on page 30 for information on these
status bits.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-read
mode. The system determines the status of the program operation using the DQ7 or DQ6 status bits, just
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
as in the standard word program operation. Refer to
“Write Operation Status” on page 30 for more information.
START
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to
“Autoselect Mode” on page 17 and “Autoselect Command Sequence” on page 25 for details.
Write Erase
Command Sequence
(Notes 1, 2)
To resume the sector erase operation, the system
must write the Erase Resume command. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip
resumes erasing.
Data Poll to Erasing
Bank from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 4.
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
Erase Operation
27
D A T A
S H E E T
Command Definitions
Table 10.
Read (Note 5)
Autoselect (Note 7)
Reset (Note 6)
Bus Cycles (Notes 1–4)
Cycles
Command
Sequence
Command Definitions
Addr
Data
1
RA
RD
First
Second
Addr
Data
Third
Addr
Fourth
Data
Addr
Fifth
Data
1
XXX
F0
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
0001
Device ID
4
555
AA
2AA
55
555
90
X01
22D7
SecSi™ Sector Factory
Protect (Note 8)
6
555
AA
2AA
55
555
88
X02
60
Sector Group Protect Verify
(Note 9)
4
555
AA
2AA
55
555
90
(SA)X02
XX00/
XX01
Sixth
Addr
Data
Addr
Data
X02
40
X02
see
(Note
9)
Enter SecSi Sector Region
3
555
AA
2AA
55
555
88
Exit SecSi Sector Region
4
555
AA
2AA
55
555
90
XXX
00
Program
4
555
AA
2AA
55
555
A0
PA
PD
Unlock Bypass
555
AA
2AA
55
555
20
XXX
A0
PA
PD
Unlock Bypass Reset (Note 11)
3
2
2
XXX
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (Note 12)
1
XXX
B0
Erase Resume (Note 13)
1
XXX
30
CFI Query (Note 14)
1
55
98
Unlock Bypass Program (Note 10)
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
Notes:
1. See Table 1 on page 11 for a description of bus operations.
2. All values are in hexadecimal.
3.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4.
During unlock cycles, (when lower address bits are 555 or 2AAh
as shown in table) address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
5.
No unlock or command cycles required when device is in read
mode.
6.
The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
7.
The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the “Autoselect
Command Sequence” on page 25 section for more information.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
8.
If WP# protects the highest address sector (or if WP# is not
available), the data is 98h for factory locked and 18h for not
factory locked. If WP# protects the lowest address sector, the
data is 88h for factory locked and 08h for not factor locked.
9.
The data is 00h for an unprotected sector group and 01h for a
protected sector group.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
11. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
13. The Erase Resume command is valid only during the Erase
Suspend mode.
14. Command is valid when device is ready to read array data or when
device is in autoselect mode.
28
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 on page 33 and the following subsections
describe the function of these bits. DQ7 and DQ6 each offer
a method for determining whether a program or erase operation is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in
progress or was completed.
invalid. Valid data on DQ0–DQ7 appears on successive read cycles.
Table 11 on page 33 shows the outputs for Data# Polling on DQ7. Figure 5, on page 30 shows the Data#
Polling algorithm. Figure 18, on page 43 in the AC
Characteristics section shows the Data# Polling timing
diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, at thai time the device returns to
the read mode.
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
No
DQ5 = 1?
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has completed the program or erase operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
February 26, 2009 22366C7
Yes
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5.
Am29LV640D/Am29LV641D
Data# Polling Algorithm
29
D A T A
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
S H E E T
Table 11 on page 33 shows the outputs for Toggle Bit I
on DQ6. Figure 6, on page 31 shows the toggle bit algorithm. Figure 19, on page 44 in the “AC Characteristics” section shows the toggle bit timing diagrams.
Figure 20, on page 44 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsection “DQ2: Toggle Bit II” on page 32.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or the device is in the erase-suspend-read
mode.
START
Read DQ7–DQ0
Table 11 on page 33 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Read DQ7–DQ0
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection “DQ7:
Data# Polling” on page 30).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
30
No
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 6.
Am29LV640D/Am29LV641D
Toggle Bit Algorithm
22366C7 February 26, 2009
D A T A
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that were selected for erasure.
(The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 11 on page 33 to compare outputs for DQ2 and DQ6.
Figure 6, on page 31 shows the toggle bit algorithm in
flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I”
on page 31 subsection. Figure 19, on page 44 shows
the toggle bit timing diagram. Figure 20, on page 44
shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 31 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a
row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the
toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high
(see the sub-section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no
longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
February 26, 2009 22366C7
S H E E T
the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6, on
page 31).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit is
exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if the device was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase command. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also “Sector Erase Command Sequence” on page 27.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device accepts additional sector erase commands. To
ensure the command was accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If
DQ3 is high on the second status check, the last command might not have been accepted.
Table 11 on page 33 shows the status of DQ3 relative
to the other status bits.
Am29LV640D/Am29LV641D
31
D A T A
Table 11.
Standard
Mode
Erase
Suspend
Mode
Status
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend- Suspended Sector
Read
Non-Erase
Suspended Sector
Erase-Suspend-Program
S H E E T
Write Operation Status
DQ7
(Note 2)
DQ7#
0
DQ6
Toggle
Toggle
DQ5
(Note 1)
0
0
DQ3
N/A
1
DQ2
(Note 2)
No toggle
Toggle
RY/BY#
(Note 3)
0
0
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. RY/BY# is only available on the FBGA package.
32
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
VCC (Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
20 ns
VIO . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +5.5 V
Figure 7. Maximum Negative
Overshoot Waveform
A9, OE#, ACC, and RESET#
(Note 2) . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
Dur ing voltage transitions, input or I/O pins may
overshoot V SS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 7. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 8.
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot V SS to –2.0 V for
periods of up to 20 ns. See Figure 7. Maximum DC input
voltage on pin A9, OE#, ACC, and RESET# is +12.5 V
which may overshoot to +14.0 V for periods up to 20 ns.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0–3.6 V
VIO . . . . . . . . . . . . . . . . .either 1.8–2.9 V or 3.0–5.0 V
(see “Ordering Information” on page 10)
Operating ranges define those limits between which the
functionality of the device is guaranteed.
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
33
D A T A
S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
ILI
Input Load Current (Note 1)
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9, ACC Input Load Current
VCC = VCC max; A9 = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
ICC1
VCC Active Read Current
(Notes 2, 3)
CE# = VIL, OE# = VIH
Typ
Max
Unit
±1.0
µA
35
µA
±1.0
µA
5 MHz
9
16
1 MHz
2
4
ICC2
VCC Active Write Current (Notes 3, 4) CE# = VIL, OE# = VIH, WE# = VIL
26
30
mA
ICC3
VCC Standby Current (Note 3)
CE#, RESET# = VCC ± 0.3 V,
WP# = VIH
0.2
5
µA
ICC4
VCC Reset Current (Note 3)
RESET# = VSS ± 0.3 V, WP# = VIH
0.2
5
µA
ICC5
Automatic Sleep Mode (Notes 3, 5)
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V, WP# = VIH
0.2
5
µA
IACC
ACC Accelerated Program Current
CE# = VIL, OE# = VIH
ACC pin
5
10
mA
VCC pin
15
30
mA
VIL
Input Low Voltage (Note 6)
–0.5
0.8
V
VIH
Input High Voltage (Note 6)
0.7 x VCC
VCC + 0.3
V
VHH
Voltage for ACC Program
Acceleration
VCC = 3.0 V ± 10%
11.5
12.5
V
VID
Voltage for Autoselect and Temporary
VCC = 3.0 V ± 10%
Sector Unprotect
8.5
12.5
V
VOL
Output Low Voltage
0.45
V
VOH1
VOH2
VLKO
IOL = 4.0 mA, VCC = VCC min
Output High Voltage
mA
IOH = –2.0 mA, VCC = VCC min
0.8 VIO
V
IOH = –100 µA, VCC = VCC min
VIO–0.4
V
Low VCC Lock-Out Voltage (Note 7)
2.3
2.5
V
Notes:
1. On the WP# pin only, the maximum input load current when WP# = VIL is ± 5.0 µA.
The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
Maximum ICC specifications are tested with VCC = VCCmax.
ICC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
6. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH
for these connections is VIO + 0.3 V
7. Not 100% tested.
2.
3.
4.
5.
34
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
DC CHARACTERISTICS
Zero-Power Flash
Supply Current in mA
25
20
15
10
5
0
0
500
1000
1500
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9.
2000
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
3.6 V
10
Supply Current in mA
8
3.0 V
6
4
2
0
1
2
3
5
Frequency in MHz
Note: T = 25 °C
Figure 10.
February 26, 2009 22366C7
4
Typical ICC1 vs. Frequency
Am29LV640D/Am29LV641D
35
D A T A
S H E E T
TEST CONDITIONS
Table 12.
Test Specifications
3.3 V
Test Condition
2.7 kΩ
Device
Under
Test
Output Load
6.2 kΩ
30
Test Setup
pF
5
ns
0.0–3.0
V
Input timing measurement
reference levels (See Note)
1.5
V
Output timing measurement
reference levels
0.5 VIO
V
Input Pulse Levels
Figure 11.
100
Input Rise and Fall Times
Note: Diodes are IN3064 or equivalent
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
CL
120R,
121R
90R
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
3.0 V
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
1.5 V
Measurement Level
0.5 VIO V
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 12. Input Waveforms and
Measurement Levels
36
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
90R
120R,
121R
Unit
Min
90
120
ns
CE#, OE# = VIL
Max
90
120
ns
OE# = VIL
Max
90
120
ns
Output Enable to Output Delay
Max
35
50
ns
tDF
Chip Enable to Output High Z (Note 1)
Max
30
30
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
30
30
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
Min
0
ns
Read
Min
0
ns
tOEH
Output Enable Hold
Time (Note 1)
Toggle and
Data# Polling
Min
10
ns
JEDEC
Std.
Description
Test Setup
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
tEHQZ
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 12 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 13.
February 26, 2009 22366C7
Read Operation Timings
Am29LV640D/Am29LV641D
37
D A T A
S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tReady
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
μs
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
μs
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
tRH
RESET#
tRP
Figure 14.
38
Reset Timings
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
90R
120R,
121R
Unit
90
120
ns
JEDEC
Std.
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tAH
Address Hold Time
Min
tAHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
tDVWH
tDS
Data Setup Time
Min
tWHDX
tDH
Data Hold Time
Min
0
ns
tOEPH
Output Enable High during toggle bit polling
Min
20
ns
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
tWHWH1
tWHWH1
Word Programming Operation (Note 2)
Typ
11
µs
tWHWH1
tWHWH1
Accelerated Word Programming Operation (Note 2)
Typ
7
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.9
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Write Recovery Time from RY/BY#
Min
0
ns
Program/Erase Valid to RY/BY# Delay
Max
90
ns
tWLAX
tBUSY
45
50
0
45
ns
50
35
ns
50
ns
ns
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
39
D A T A
S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 15.
Program Operation Timings
VHH
ACC
VIL or VIH
VIL or VIH
tVHH
Figure 16.
40
tVHH
Accelerated Program Timing Diagram
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.
Figure 17.
February 26, 2009 22366C7
Chip/Sector Erase Operation Timings
Am29LV640D/Am29LV641D
41
D A T A
S H E E T
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
True
Valid Data
High Z
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 18. Data# Polling Timings
(During Embedded Algorithms)
42
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
DQ6/DQ2
tOE
Valid Data
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 19. Toggle Bit Timings
(During Embedded Algorithms)
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 20. DQ2 vs. DQ6
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
43
D A T A
S H E E T
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
µs
tRRB
RESET# Hold Time from RY/BY# High for
Temporary Sector Group Unprotect
Min
4
µs
Note: Not 100% tested.
VID
RESET#
VID
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 21.
44
Temporary Sector Group Unprotect Timing Diagram
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Group Protect or Unprotect
Data
60h
60h
Valid*
Verify
40h
Status
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 22.
February 26, 2009 22366C7
Sector Group Protect and Unprotect Timing Diagram
Am29LV640D/Am29LV641D
45
D A T A
S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
90R
120R,
121R
Unit
90
120
ns
JEDEC
Std
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
50
ns
tDVEH
tDS
Data Setup Time
Min
45
50
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
30
ns
tWHWH1
tWHWH1
Word Programming Operation (Note 2)
Typ
11
µs
tWHWH1
tWHWH1
Accelerated Word Programming Operation (Note 2)
Typ
7
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.9
sec
0
45
ns
50
ns
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
46
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 23.
February 26, 2009 22366C7
Alternate CE# Controlled Write (Erase/Program) Operation Timings
Am29LV640D/Am29LV641D
47
D A T A
S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.9
15
sec
Chip Erase Time
115
Excludes 00h programming
prior to erasure (Note 4)
Word Program Time
11
300
µs
Accelerated Word Program Time
7
210
µs
Chip Program Time (Note 3)
48
144
sec
sec
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
10 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Minimum Pattern Data Retention Time
48
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
PHYSICAL DIMENSIONS
SSO056—56-Pin Shrink Small Outline Package (SSOP)
Dwg rev AB; 10/99
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
49
D A T A
S H E E T
PHYSICAL DIMENSIONS
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm package
Dwg rev AF; 10/99
50
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
PHYSICAL DIMENSIONS
LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm package
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
51
D A T A
S H E E T
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99
Note: For reference only. BSC is an ANSI standard for Basic Space Centering.
* For reference only. BSC is an ANSI standard for Basic Space Centering.
52
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
REVISION SUMMARY
Revision A (April 26, 1999)
Ordering Information
Initial release.
Added the valid combinations for the SSOP package.
Revision A+1 (May 4, 1999)
Revision A+6 (September 28, 1999)
Global
Connection Diagrams
Deleted references to the 4-word unique ESN. Replaced references to VCCQ with VIO.
Clarified which packages are available for a particular
part number.
Connection Diagrams
Device Bus Operations
63-ball FBGA: Corrected signal for ball H7 to VIO.
VersatileIO Control: Added comment to contact AMD
for more information on this feature.
Ordering Information
DC Characteristics
Added “U” designator description.
SecSi (Secured Silicon) Sector Flash Memory
Region
In the third paragraph, replaced references to boot
sectors with SA0. Added table to show SecSi sector
contents.
DC Characteristics table
Added VIO = VCC as a test condition for ICC1 and ICC2.
Changed V HH minimum specification from 8.5 V to
11.5 V.
CMOS Compatible table: Added notes (1 and 2) for ILI
and test conditions column.
Test Conditions
In Test Specifications table and Input Waveforms and
Measurement Levels figure, changed the output measurement level to VIO/2.
AC Characteristics
Read-only Operations table: Added note for test setup
column.
Revision A+2 (May 14, 1999)
Revision B (June 20, 2000)
Ordering Information
Global
Clarified the differences between the H, L, and U
designators.
Deleted references to 150 ns speed option. Added
more information and specifications on VIO feature, including part number distinctions. At V IO < V CC, the
available speed options are 100 ns and 120 ns. At VIO
≥ VCC, the available speed options are 90 ns and 120
ns. Changed data sheet status to “Preliminary.”
Revision A+3 (June 7, 1999)
Product Selector Guide
Added note under table.
Distinctive Characteristics
Ordering Information
Deleted the “0” from the 120 and 150 ns part numbers.
Corrected the FBGA package marking for the 150 ns
speed option.
Clarified on which devices RY/BY# and WP# are available. Clarified package options for devices.
Ordering Information
Clarified on which devices RY/BY# and WP# are available. Clarified package options for devices. Reinstated
“0” into the 120 ns speed part number for VIO = 3.0 V
to 5.0 V; added part numbers for VIO = 1.8 V to 2.9 V.
Revision A+4 (June 25, 1999)
Global
Information on the 56-pin SSOP package has been
added: pinout information and physical dimension
drawings.
Device Bus Operations table
In the legend, corrected the VHH voltage range.
Command Definitions
SecSi Sector Contents table
Corrected the data for SecSi Sector protection in Note
9. Added device ID data to the table.
Corrected ending address in second row to 7Fh.
Revision A+5 (August 2, 1999)
Redefined VOH1 and VOH2 in terms of VIO. Added note
relative to VIO for VIH and VIL. Deleted note regarding
test condition assumption of VIO = VCC.
Block Diagram
DC Characteristics table
Separated WP# and ACC.
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
53
D A T A
S H E E T
Test Conditions
Revision B+5 (October 11, 2001)
Test Conditions table: Redefined output timing measurement reference level as 0.5 VIO.
Connection Diagrams, Ordering Information,
Physical Dimensions
Added note to table and figure.
Added 64-ball Fortified BGA package information.
Erase and Program Operations table, Alternate
CE# Controlled Erase and Program Operations
table, Erase and Programming Performance table
Changed the typical sector erase time to 1.6 s.
AC Characteristics—Figure 15. Program
Operations Timing and Figure 17. Chip/Sector
Erase Operations
Revision B+6 (January 10, 2002)
Global
Clarified description of VersatileIO (VIO) in the following sections: Distinctive Characteristics; General Description; VersatileIO (VIO) Control; Operating Ranges;
DC Characteristics; CMOS compatible.
Deleted tGHWL and changed OE# waveform to start at
high.
Reduced typical sector erase time from 1.6 s to 0.9 s.
Physical Dimensions
Changed minimum VOH1 from 0.85VIO to 0.8VIO. Deleted reference to Note 6 for both VOH1 and VOH2.
Replaced figures with more detailed illustrations.
DC Characteristics
Erase and Program Performance table
Revision B+1 (August 4, 2000)
Reduced typical sector erase time from 1.6 s to 0.9 s.
Changed typical chip program time from 90 s to 115 s.
Global
Added trademarks for SecSi Sector.
Accelerated Program Operation (page 12), Unlock
Bypass Command Sequence (page 26)
Revision B+7 (April 15, 2002)
Ordering Information
Added N designator for Fortified BGA package markings.
Added caution note regarding ACC pin.
Absolute Maximum Ratings
Corrected the maximum voltage on VIO to +5.5V.
Common Flash Interface (CFI)
DC Characteristics table
Revised data value at address 44h. Clarified description of data for addresses 45–47h, 49, 4A, 4D–4Fh.
Added WP# = VIH to test conditions for standby currents ICC3, ICC4, ICC5.
Table 10, Command Definitions
Revision B+2 (October 18, 2000)
Clarified and combined Notes 4 and 5 into Note 4.
Revision B+8 (September 20, 2002)
Distinctive Characteristics
Corrected package options for 56-pin SSOP as being
available on Am29LV640DH/DL only.
Sector Erase Command Sequence
Changed sentence arrangement in fourth paragraph.
Revision B+3 (January 18, 2001)
Revision B+9 (March 3, 2004)
Global
Table 10, Command Definitions
Deleted “Preliminary” status from document.
Revised SecSi Sector Factory Protect (note 8) command definitions.
General Description
In the second paragraph, corrected references to VIO
voltage ranges. The 90 and 120 speeds are available
where VIO ≥ VCC, and 100 and 120 ns speeds are available where VIO < VCC.
Revision B+4 (March 8, 2001)
Table 4, Sector Group Protection/Unprotection
Address Table
Corrected the sector group address bits for sectors
64–127.
54
Revision B+10 (April 5, 2004)
Command Definitions
Changed first Address data for Erase Suspend/Resume from BA to XXX.
Revision C (June 4, 2004)
Ordering Information
Added Pb-free OPNs.
Am29LV640D/Am29LV641D
22366C7 February 26, 2009
D A T A
S H E E T
Revision C + 1 (October 14, 2004)
Revision C + 4 (September 13, 2005)
Ordering Information
Valid Combinations
Added tRH reference line to Figure 14.
New option FF added on TSOP and SSOP packages.
Corrected description of Sector Erase Command Sequence on page 30.
Revision C5 (December 23, 2005)
Global
Added Colophon
Revision C + 2 (January 7, 2005)
Deleted reverse TSOP package option and 100 ns
speed option.
Valid Combinations
Revision C6 (January 22, 2007)
Updated table to include a note regarding product offerings for new designs.
AC Characteristics
Revision C + 3 (February 9, 2005)
Erase and Program Operations table: Changed tBUSY
to a maximum specification.
Pin Description
Revision C7 (February 26, 2009)
Added RFU to the list of pins.
Global
Global
Added obsolescence information.
Removed references to byte mode.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 1999–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are
for identification purposes only and may be trademarks of their respective companies.
Copyright © 2006–2009 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
ORNAND2™, HD-SIM™, EcoRAM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names
used are for informational purposes only and may be trademarks of their respective owners.
February 26, 2009 22366C7
Am29LV640D/Am29LV641D
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