OPERATION GUIDE UHF Narrow band radio transceiver STD-302S 419MHz Operation Guide Version 1.1 (Oct. 2015) This product requires electrical and radio knowledge for setup and operation. To ensure proper and safe operation, please read this operation guide thoroughly prior to use. Please keep this operation guide for future reference. CIRCUIT DESIGN, INC., 7557-1 Hotaka, Azumino Nagano 399-8303 JAPAN Tel: + +81-(0)263-82-1024 Fax: + +81-(0)263-82-1016 e-mail: [email protected] http://www.circuitdesign.jp OG_STD-302S-419M_v11e OPERATION GUIDE CONTENTS GENERAL DESCRIPTION & FEATURES...........................3 SPECIFICATIONS STD-302S 419 MHz...........................4 PIN DESCRIPTION .............................................................6 BLOCK DIAGRAM...............................................................8 DIMENSIONS......................................................................9 PLL IC CONTROL .............................................................10 PLL IC control ..................................................................10 How to calculate the setting values for the PLL register ........ 11 Method of serial data input to the PLL ................................12 TIMING CHART.................................................................13 PLL FREQUENCY SETTING REFERENCE .....................15 TEST DATA .......................................................................17 REGULATORY COMPLIANCE INFORMATION................18 CAUTIONS & WARNINGS................................................20 OG_STD-302S-419M_v11e 2 Circuit Design, Inc. OPERATION GUIDE GENERAL DESCRIPTION & FEATURES General Description The UHF FM narrow band semi-duplex radio data module STD-302S is a high performance transceiver designed for use in industrial applications requiring long range, high performance and reliability. All high frequency circuits are enclosed inside a robust housing to provide superior resistance against shock and vibration. The narrow band technique enables high interference rejection and concurrent operation with multiple modules. STD-302S, a narrowband module with 25 kHz channel steps, achieves high TX/RX switching speed, making it an ideal RF unit for inclusion in feedback systems. Features 10 mW RF power, 3.0 V operation Programmable RF channel Fast TX/RX switching time High sensitivity -118 dBm Excellent mechanical durability, high vibration & shock resistance Applications Telemetry Water level monitor for rivers, dams, etc. Monitoring systems for environmental data such as temperature, humidity, etc. Transmission of measurement data (pressure, rpm, current, etc) to PC Security alarm monitoring Telecontrol Industrial remote control systems Remote control systems for factory automation machines Control of various driving motors Data transmission RS232/RS485 serial data transmission OG_STD-302S-419M_v11e 3 Circuit Design, Inc. OPERATION GUIDE SPECIFICATIONS STD-302S 419 MHz All ratings at 25 +/-10 °C unless otherwise noted General characteristics Item Communication method Emission class Operating frequency range Operation temperature range Storage temperature range Frequency drift / year Initial frequency tolerance Dimensions Weight Units MHz °C °C ppm ppm mm g MIN TYP MAX Simplex, Half-duplex F1D 418.725 419.425 -20 60 -30 75 -1 1 -1.5 1.5 30 x 50 x 9 mm 25 g Remarks No dew condensation No dew condensation TX freq., RX Lo freq. TX freq., RX Lo freq. Not including antenna Electrical specification <Common> Item Oscillation type Frequency stability (-20 to 60°C) TX/RX switching time Channel step Data rate Max. pulse width Min. pulse width Data polarity PLL reference frequency PLL response Antenna impedance Operating voltage TX consumption current RX consumption current ppm ms kHz bps ms us MHz ms Ω V mA mA MIN TYP MAX PLL controlled VCO -4 4 15 20 25 2400 9600 15 100 Positive 21.25 30 60 50 3.0 5.5 46 50 26 30 Remarks Reference frequency at 25 °C DI/DO DO/DI DO/DI DO/DI DO/DI TCXO from PLL setting to LD out Nominal Vcc = 3.0 V Vcc = 3.0 V Transmitter part Item RF output power Deviation DI input level Residual FM noise Spurious emission Adjacent CH power OG_STD-302S-419M_v11e MIN mW kHz V kHz dBm dBm ±2.35 0 TYP 10 ±2.75 MAX ±3.15 5.5 0.17 -40 -37 Remarks 50Ω conducted PN9 9600 bps L= GND, H = 3 V- Vcc DI=L, LPF=20 kHz 2f / 3f, conduced 50Ω PN9 9600 bps CH25kHz/BW16kHz 4 Circuit Design, Inc. OPERATION GUIDE Receiver part Item Receiver type 1st IF frequency 2nd IF frequency Maximum input level *1 BER (0 error/2556 bits) *2 BER (1 % error) Sensitivity 12dB/ SINAD Spurious response rejection Adjacent CH selectivity *4 Intermodulation DO output level MHz kHz dBm dBm dBm dBm *3 *3 RSSI rising time Time until valid Data-out dB dB dB V ms *5 Spurious radiation (1st Lo) Spurious radiation RSSI ms dBm dBm mV MIN TYP MAX Double superheterodyne 21.7 450 10 -106 -109 -115 -118 50 50 50 50 0 2.8 30 50 50 70 50 100 70 120 -57 -47 190 240 290 Remarks PN 9 9600bps PN 9 9600bps fm1 k/ dev 2.75 kHz CCITT 1 st Mix, 2 signal method, 1 % error 2 nd Mix, 2 signal method, 1 % error +/- 25 kHz, 2 signal method, 1 % error 2 signal method, 1 % error L = GND H = 2.8 V CH shift of 25 kHz (from PLL setup) When power ON (from PLL setup) CH shift of 25 kHz (from PLL setup) When power ON (from PLL setup) x1, x2 Conducted 50Ω x3, x4, x5 With -113 dBm at 419.05MHz Specifications are subject to change without prior notice Notice The time required until a stable DO is established may get longer due to the possible frequency drift caused by operation environment changes, especially when switching from TX to RX, from RX to TX and changing channels. Please make sure to optimize the timing. The recommended preamble is more than 20 ms. Antenna connection is designed as pin connection. RF output power, sensitivity, spurious emission and spurious radiation levels may vary with the trace used between the RF pin and the coaxial connection. Please make sure to verify those parameters before use. The feet of the shield case should be soldered to a wide GND plane to avoid any change in characteristics. Notes about the specification values *1 BER: RF level where no error per 2556 bits is confirmed with the signal of PN9 and 9600 bps. *2 BER (1 % error) : RF level where 1% error per 2556 bits is confirmed with the signal of PN9 and 9600 bps. *3 Spurious response, CH selectivity: Jamming signal used in the measurement is unmodulated. *4 Intermodulation: Ratio between the receiver input level with BER 1% and the signal level (PN9 9600 bps) added at the points of 'Receiving frequency - 200 kHz ' + ' Receiving frequency -100kHz' with which BER 1% is achieved. *5 Time until valid Data-out : Valid DO is determined at the point where Bit Error Rate meter starts detecting the signal of 9600bps, 1010repeated signal. All specifications are specified based on the data measured in a shield room using the PLL setting controller board prepared by Circuit Design. Measuring equipment: SG=ANRITUS communication analyzer MT8802 Spectrum analyzer = ANRITSU MS2830A BER measure = ANRITSU MP1201G OG_STD-302S-419M_v11e 5 Circuit Design, Inc. OPERATION GUIDE PIN DESCRIPTION Pin name I/O Description Equivalent circuit RF I/O RF input terminal Antenna impedance nominal 50 Ω GND I GROUND terminal The GND pins and the feet of the shield case should be connected to a wide GND plane. VCC I Power supply terminal DC 3.0 to 5.5 V I TX select terminal GND = TXSEL active To enable the transmitter circuits, connect TXSEL to GND and RXSEL to OPEN or 2.8 V. I RX select terminal GND= RXSEL active To enable the receiver circuits, connect RXSEL to GND and TXSEL to OPEN or 2.8 V. AFOUT O Analogue output terminal There is a DC offset of approx. 1 V. Refer to the specification table for amplitude level. CLK I Clock terminal for PLL data setting input Interface voltage H = 2.8 V, L = 0 V DATA I PLL data setting input terminal Interface voltage H = 2.8 V, L = 0 V TXSEL RXSEL OG_STD-302S-419M_v11e 6 Circuit Design, Inc. OPERATION GUIDE LE I Load enable signal input terminal for PLL data setting input Interface voltage H = 2.8 V, L = 0 V LD O PLL lock/unlock indicator terminal Lock = H (2.8 V), Unlock = L (0 V) RSSI O Received Signal Strength Indicator terminal 22k DO DI O Data output terminal Interface voltage: H=2.8V, L=0V I Data input terminal Interface voltage: H=2.8V to Vcc, L=0V Input data pulse width Min.100 μs Max. 15 ms OG_STD-302S-419M_v11e 7 Circuit Design, Inc. OPERATION GUIDE. BLOCK DIAGRAM <STD-302S 419 MHz> OG_STD-302S-419M_v11e 8 Circuit Design, Inc. OPERATION GUIDE. DIMENSIONS OG_STD-302S-419M_v11e 9 Circuit Design, Inc. OPERATION GUIDE . PLL IC CONTROL PLL IC control Figure 1 up to 1200MHz VCO 2kohm Voltage Controled Oscillator Fin CLK Xf in Data 2kohm 2kohm GND LPF LE PLL Do +2.8v LE PS VCC ZC 2kohm 21.25MHz DATA MB15E03SL Vp Reference Oscillator CLK LD/f out OSCout P OSCin R LD STD-302 Control pin name #:Control v oltage = +2.8v STD-302S is equipped with an internal PLL frequency synthesizer as shown in Figure 1. The operation of the PLL circuit enables the VCO to oscillate at a stable frequency. Transmission frequency is set externally by the controlling IC. STD-302S has control terminals (CLK, LE, DATA) for the PLL IC and the setting data is sent to the internal register serially via the data line. Also STD-302S has a Lock Detect (LD) terminal that shows the lock status of the frequency. These signal lines are connected directly to the PLL IC through a 2 kΩ resistor. The interface voltage of STD-302S is 2.8 V, so the control voltage must be the same. STD-302S comes equipped with a Fujitsu MB15E03SL PLL IC. Please refer to the manual of the PLL IC. The following is a supplementary description related to operation with STD-302S. In this description, the same names and terminology as in the PLL IC manual are used, so please read the manual beforehand. OG_STD-302S-419M_v11e 10 Circuit Design, Inc. OPERATION GUIDE . How to calculate the setting values for the PLL register The PLL IC manual shows that the PLL frequency setting value is obtained with the following equation. fvco = [(M x N)+A] x fosc / R -- Equation 1 fvco : Output frequency of external VCO M: Preset divide ratio of the prescaler (64 or 128) N: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127 A<N)) fosc: Output frequency of the reference frequency oscillator R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) With STD-302S, there is an offset frequency (foffset) 21.7 MHz for the transmission RF channel frequency fch. Therefore the expected value of the frequency generated at VCO (fexpect) is as below. fvco = fexpect = fch – foffset ---- Equation 2 The PLL internal circuit compares the phase to the oscillation frequency fvco. This phase comparison frequency (fcomp) must be decided. fcomp is made by dividing the frequency input to the PLL from the reference frequency oscillator by reference counter R. STD-302S uses 21.25 MHz for the reference clock fosc. fcomp is one of 6.25 kHz, 12.5 kHz or 25 kHz. The above equation 1 results in the following with n = M x N + A, where “n” is the number for division. fvco=n*fcomp ---- Equation 3 n = fvco/fcomp ---- Equation 4 note: fcomp = fosc/R Also, this PLL IC operates with the following R, N, A and M relational expressions. R=fosc/fcomp ---- Equation 5 N = INT (n / M) ---- Equation 6 A = n - (M x N) ---- Equation 7 INT: integer portion of a division. As an example, the setting value of RF channel frequency fch 418.725 MHz can be calculated as below. The constant values depend on the electronic circuits of STD-302S. Conditions: Channel center frequency: fch = 418.725 MHz Constant: Offset frequency: foffset=21.7 M Constant: Reference frequency: fosc=21.25 MHz Set 25 kHz for Phase comparison frequency and 64 for Prescaler value M The frequency of VCO will be fvco = fexpect = fch - foffset = 418.725–21.7 = 397.025 MHz Dividing value “n” is derived from Equation 4 n = fvco / fcomp = 397.025MHz/25kHz = 15881 Value “R” of the reference counter is derived from Equation 5. R = fosc/fcomp = 21.25MHz/25kHz = 850 Value “N” of the programmable counter is derived from Equation 6. N = INT (n/M) = INT(15881/64) = 248 Value “A“ of the swallow counter is derived from Equation 7. A = n – (M x N) = 15881-64x248 = 9 The frequency of STD-302S is locked at a center frequency fch by inputting the PLL setting values N, A and R obtained with the above equations as serial data. The above calculations are the same for the other frequencies. Excel sheets that contain automatic calculations for the above equations can be found on our web site (www.circuitdesign.jp). The result of the calculations is arranged as a table in the CPU ROM. The table is read by the channel change routine each time the channel is changed, and the data is sent to the PLL. OG_STD-302S-419M_v11e 11 Circuit Design, Inc. OPERATION GUIDE . Method of serial data input to the PLL After the RF channel table plan is decided, the data needs to be allocated to the ROM table and read from there or calculated with the software. Together with this setting data, operation bits that decide operation of the PLL must be sent to the PLL. The operation bits for setting the PLL are as follows. These values are placed at the head of the reference counter value and are sent to the PLL. 1. CS: Charge pump current select bit CS = 0 +/-1.5 mA select VCO is optimized to +/-1.5 mA 2. LDS: LD/fout output setting bit LDS = 0 LD select Hardware is set to LD output 3. FC: Phase control bit for the phase comparator FC = 1 Hardware operates at this phase Figure 2 1st Data 2nd Data 2nd data N11 N10 N9 N8 N7 N6 1st data CS LDS FC SW R14 R13 A1 R1 CNT=0 CNT=1 Inv alid Data DATA MSB LSB CLK t1 t2 t6 t3 t0 LE STD-302 terminal name #: t0,t5 >= 100 ns t1,t2,t6 >= 20 ns t3,t4 >= 30 ns t4 t5 #: Keep the LE terminal at a low level, w hen w rite the data to the shift resister. The PLL IC, which operates as shown in the block diagram in the manual, shifts the data to the 19-bit shift register and then transfers it to the respective latch (counter, register) by judging the CNT control bit value input at the end. 1. CLK [Clock]: Data is shifted into the shift register on the rising edge of this clock. 2. LE [Load Enable]: Data in the 19-bit shift register is transferred to respective latches on the rising edge of the clock. The data is transferred to a latch according to the control bit CNT value. 3. Data [Serial Data]: You can perform either reference counter setup or programmable counter setup first. OG_STD-302S-419M_v11e 12 Circuit Design, Inc. OPERATION GUIDE . TIMING CHART Control timing in a typical application is shown in Figure 3. Initial setting of the port connected to the radio module is performed when power is supplied by the CPU and reset is completed. MOS-FET for supply voltage control of the radio module, RXSEL and TXSEL are set to inactive to avoid unwanted emissions. The power supply of the radio module is then turned on. When the radio module is turned on, the PLL internal resistor is not yet set and the peripheral VCO circuit is unstable. Therefore data transmission and reception is possible 40 ms after the setting data is sent to the PLL at the first change of channel, however from the second change of channel, the circuit stabilizes within 20 ms and is able to handle the data. Changing channels must be carried out in the receive mode. If switching is performed in transmission mode, unwanted emission occurs. If the module is switched to the receive mode when operating in the same channel, (a new PLL setting is not *1 necessary) it can receive data within 5 ms of switching . For data transmission, if the RF channel to be used for transmission is set while still in receiving mode, data can be sent at 5 ms after the radio module is switched from *2 reception to transmission . Check that the Lock Detect signal is “high” 20 ms after the channel is changed. In some cases the Lock Detect signal becomes unstable before the lock is correctly detected, so it is necessary to note if processing of the signal is interrupted. It is recommended to observe the actual waveform before writing the process program. *1 DC offset may occur due to frequency drift caused by ambient temperature change. Under conditions below 10 °C, 10 to 20 ms delay of DO output is estimated. The customer is requested to verify operation at low temperature and optimize the timing. *2 Sending ‘10101…..’ preamble just after switching to transmission mode enables smoother operation of the binarization circuit of the receiver. For 9600 bps, a preamble of ‘11001100’ is effective. Remark For details about PLL control and the sample programs, see our technical document ‘STD-302 interface method’ OG_STD-302S-419M_v11e 13 Circuit Design, Inc. OPERATION GUIDE Figure 3: Timing diagram for STD-302 Status immediately after pow er comes on. Normal status Channel change No channel change CPU Pow er on STD-302 Pow er on #:3 Receiv e mode Receiv e mode Receiv e mode activ e period activ e period activ e period Activ e period RXSEL CPU control, CH change & Data rec. Timing #:1 #:2 #:4 5 ms #:4 CH Data #:5 CH #:4 Data #:6 Check LD signal Check LD signal CH Data #:7 Check LD signal LD 40 ms 10 to 20 ms Transmit mode activ e TXSEL Transmit mode activ e Transmit mode activ e Data transmit 5 ms 5 ms #:1 Reset control CPU 5 ms #:5 40 ms later, the receiver can receive the data after changing the channel.. #:2 Initialize the port connected to the module. #:6 10 to 20 ms later, the receiver can receive the data after changing the channel. #:3 Supply pow er to the module after initializing CPU. #:7 5 ms later, the data can be received if the RF channel is not changed. #:4 RFchannel change must be performed in receiving mode. OG_STD-302S-419M_v11e 14 Circuit Design, Inc. . OPERATION GUIDE PLL FREQUENCY SETTING DATA REFERENCE 419 MHz band (418.7250 - 419.4250 MHz) Parameter name Phase Comparing Frequency Fcomp [kHz] Start Channel Frequency Fch [MHz] Channel Step Frequency [kHz] Number of Channel Prescaler M Parameter name Reference Frequency Fosc [MHz] Offset Frequency Foffset [MHz] Value : For data input 25 418.7250 25 29 64 : Result of calculation : Fixed value Parameter name Reference Counter R Programmable Counter N Min. Value Programmable Counter N Max. Value Swallow Counter A Min. Value Swallow Counter A Max. Value Value 21.25 21.7 Expect Frequency ＦEXPECT Lock Frequency FVCO No. Channel Frequency FCH (MHz) (MHz) (MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 418.7250 418.7500 418.7750 418.8000 418.8250 418.8500 418.8750 418.9000 418.9250 418.9500 418.9750 419.0000 419.0250 419.0500 419.0750 419.1000 419.1250 419.1500 419.1750 419.2000 419.2250 419.2500 419.2750 419.3000 419.3250 419.3500 419.3750 419.4000 419.4250 397.0250 397.0500 397.0750 397.1000 397.1250 397.1500 397.1750 397.2000 397.2250 397.2500 397.2750 397.3000 397.3250 397.3500 397.3750 397.4000 397.4250 397.4500 397.4750 397.5000 397.5250 397.5500 397.5750 397.6000 397.6250 397.6500 397.6750 397.7000 397.7250 397.0250 397.0500 397.0750 397.1000 397.1250 397.1500 397.1750 397.2000 397.2250 397.2500 397.2750 397.3000 397.3250 397.3500 397.3750 397.4000 397.4250 397.4500 397.4750 397.5000 397.5250 397.5500 397.5750 397.6000 397.6250 397.6500 397.6750 397.7000 397.7250 OG_STD-302S-419M_v11e 15 Value 850 248 248 9 37 Number of Division n Programable Counter N Swallow Counter A 15881 15882 15883 15884 15885 15886 15887 15888 15889 15890 15891 15892 15893 15894 15895 15896 15897 15898 15899 15900 15901 15902 15903 15904 15905 15906 15907 15908 15909 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 248 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Circuit Design, Inc. OPERATION GUIDE TEST DATA RSSI output level characteristic Measurement frequency: 419 MHz / Modulation: unmodulated 25°C +/- 5°C Signal level [dBm] -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 OG_STD-302S-419M_v11e RSSI [mV] (Typ.) 124 192 261 329 398 466 535 603 625 627 627 627 627 627 Measurement is done with the PLL setting control board prepared by Circuit Design. 16 Circuit Design, Inc. OPERATION GUIDE Regulatory compliance information Compliance STD-302S 419 MHz is designed to be installed in radio equipment for use in China. The technical specifications referred to in the design phase are shown below: Frequency Output power Band width Spurious emission Frequency tolerance 418.950 MHz, 418.975 MHz, 419.000 MHz, 419.025 MHz, 419.050 MHz, 419.075 MHz, 419.100 MHz, 419.125 MHz, 419.150 MHz, 419.175 MHz, 419.200 MHz, 419.250 MHz, 419.275MHz < 10 mW < 16 kHz < 2.5 μW -6 < 4 x 10 The relevant laws and regulations are subject to change. Compliance assessment This product was designed to meet the specification above, however it has not been assessed for conformity with the appropriate regulations. Users are required to verify that their final product meets the appropriate specifications and to perform the procedures for regulatory compliance. Guarantee of regulatory compliance We only guarantee that this product meets the specification in this document. We are exempt from any other responsibilities relating to regulatory compliance. We also recommend that the user consults the authorities in the relevant country for detailed regulatory information such as valid regulations, test specifications, assessment procedures, marking methods etc, before starting any project with this product. If technical documentation is required for compliance assessments, we will provide any documents, which may be considered necessary for assessment, under NDA. The documentation is only available in English. OG_STD-302S-419M_v11e 17 Circuit Design, Inc. OPERATION GUIDE Important notice Customers are advised to consult with Circuit Design sales representatives before ordering. Circuit Design believes the provided information is accurate and reliable. However, Circuit Design reserves the right to make changes to this product without notice. Circuit Design products are neither designed nor intended for use in life support applications where malfunction can reasonably be expected to result in significant personal injury to the user. Any use of Circuit Design products in such safety-critical applications is understood to be fully at the risk of the customer and the customer must fully indemnify Circuit Design, Inc for any damages resulting from any improper use. As the radio module communicates using electronic radio waves, there are cases where transmission will be temporarily cut off due to the surrounding environment and method of usage. The manufacturer is exempt from all responsibility relating to resulting harm to personnel or equipment and other secondary damage. The manufacturer is exempt from all responsibility relating to secondary damage resulting from the operation, performance and reliability of equipment connected to the radio module. Copyright All rights in this operation guide are owned by Circuit Design, Inc. No part of this document may be copied or distributed in part or in whole without the prior written consent of Circuit Design, Inc. Cautions As the radio module communicates using electronic radio waves, there are cases where transmission will be temporarily cut off due to the surrounding environment and method of usage. The manufacturer is exempt from all responsibility relating to resulting harm to personnel or equipment and other secondary damage. Do not use the equipment within the vicinity of devices that may malfunction as a result of electronic radio waves from the radio module. The manufacturer is exempt from all responsibility relating to secondary damage resulting from the operation, performance and reliability of equipment connected to the radio module. Communication performance will be affected by the surrounding environment, so communication tests should be carried out before actual use. Ensure that the power supply for the radio module is within the specified rating. Short circuits and reverse connections may result in overheating and damage and must be avoided at all costs. Ensure that the power supply has been switched off before attempting any wiring work. The case is connected to the GND terminal of the internal circuit, so do not make contact between the '+' side of the power supply terminal and the case. When batteries are used as the power source, avoid short circuits, recharging, dismantling, and pressure. Failure to observe this caution may result in the outbreak of fire, overheating and damage to the equipment. Remove the batteries when the equipment is not to be used for a long period of time. Failure to observe this caution may result in battery leaks and damage to the equipment. Do not use this equipment in vehicles with the windows closed, in locations where it is subject to direct sunlight, or in locations with extremely high humidity. The radio module is neither waterproof nor splash proof. Ensure that it is not splashed with soot or water. Do not use the equipment if water or other foreign matter has entered the case. Do not drop the radio module or otherwise subject it to strong shocks. Do not subject the equipment to condensation (including moving it from cold locations to locations with a significant increase in temperature.) Do not use the equipment in locations where it is likely to be affected by acid, alkalis, organic agents or corrosive gas. Do not bend or break the antenna. Metallic objects placed in the vicinity of the antenna will have a great effect on communication performance. As far as possible, ensure that the equipment is placed well away from metallic objects. The GND for the radio module will also affect communication performance. If possible, ensure that the case GND and the circuit GND are connected to a large GND pattern. Warnings Do not take a part or modify the equipment. Do not remove the product label (the label attached to the upper surface of the module.) Using a module from which the label has been removed is prohibited. Copyright 2015, Circuit Design, Inc. OG_STD-302S-419M_v11e 18 Circuit Design, Inc. OPERATION GUIDE REVISION HISTORY Version 1.0 1.1 Date Jul. 2015 Oct.2015 OG_STD-302S-419M_v11e Description The first issue RSSI characteristics was revised. 19 Remark Circuit Design, Inc.
* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project