AN656: Combining Multiple Configuration Schemes

AN656: Combining Multiple Configuration Schemes
Combining Multiple Configuration
Schemes
AN-656-1.0
Application Note
This application note describes how to configure Altera® FPGAs using multiple
configuration schemes on the same board.
Combining JTAG configuration with passive serial (PS) or active serial (AS)
configuration on your board is useful in the prototyping environment because it
allows multiple methods to configure your FPGA. For example, if your production
environment calls for PS configuration using a configuration device, you must
reprogram your configuration device every time you wanted to test a design change
in your FPGA. If you include the FPGA in the same JTAG chain as the configuration
device, the FPGA can be reconfigured using JTAG without having to reprogram the
configuration device.
In this application note, the generic term “download cable” includes the Altera
USB-Blaster, EthernetBlaster II, EthernetBlaster, and ByteBlaster II download
cables. The generic term “FPGA” includes Arria series, Cyclone series, and Stratix
series devices.
1
In this application note, the figures show the configuration interface connections only.
f For more information about pull-up resistor values or other pins on the configuration
devices, refer to the Configuration Devices page.
f For more information about pull-up resistor values, VCC values, or other pins on
FPGA, refer to the configuration chapter in the appropriate device handbook.
101 Innovation Drive
San Jose, CA 95134
www.altera.com
January 2012
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark
Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their
respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
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9001:2008
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Page 2
Passive Serial and JTAG
Passive Serial and JTAG
Figure 1 shows the configuration interface connections when you are using a
download cable to JTAG program a configuration device and using the configuration
device to configure the FPGAs. In Figure 1, multiple FPGAs are daisy-chained
together and the MSEL pins should be set to select PS as the configuration mode.
Figure 1. JTAG Programming of a Configuration Device with PS Configuration of FPGA Using a Configuration Device
VCC (1)
1 kΩ
VCC (1)
1 kΩ
VCC (1) VCC (1)
Download Cable
(JTAG Mode)
10-Pin Male Header
(2)
(2)
VCC (1)
(2)
FPGA
n
MSEL
nCE
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
VCC
VIO
GND
GND
nCEO
FPGA
n
1 kΩ
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
GND
Configuration Device
DATA
DCLK
OE
nCS
TMS
TCK
TDI
MSEL
nINIT_CONF
TDO
nCE
nCEO
FPGA
n
MSEL
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
nCE
nCEO N.C.
Notes to Figure 1:
(1) Connect VCC to the same supply voltage as the configuration device.
(2) If you use the internal pull-up resistors of the configuration device, do not use external pull-up resistors on these pins.
Figure 2 shows the configuration interface connections when the configuration device
and the FPGA are in the same JTAG chain. Ensure the TDO signal drives out enough
amount of high voltage to meet the next device's TDI minimum high-level input
voltage (VIH ). The TDO output drives out the voltage of the I/O bank’s VCCIO where it
resides. For example, if the TDO pin resides in an I/O bank whose VCCIO is set to 3.3 V,
the TDO pin drives out 3.3 V. The download cable is used to JTAG program the
configuration device and the FPGA. The configuration device is used to configure the
FPGA. Set the MSEL pins to select PS as the configuration mode.
Combining Multiple Configuration Schemes
January 2012
Altera Corporation
Passive Serial and JTAG
1
Page 3
If there is a configuration device on board, after power up, allow the FPGA to finish
configuration before attempting JTAG configuration.
Figure 2. JTAG Programming of a Configuration Device and FPGA with PS Configuration of FPGA Using a Configuration
Device
VCC (1)
1 kΩ
VCC (1)
1 kΩ
Download Cable
VCC (1)
(JTAG Mode)
10-Pin Male Header (2) VCC (1)
V (1)
(2) CC
(2)
VCC
VIO
FPGA
n
MSEL
GND
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
1 kΩ
GND
nCEO
nCE
N.C.
Configuration Device
DATA
DCLK
OE
nCS
TMS
TCK
TDI
GND
VCC
nINIT_CONF
TDO
TDI
TRST
TMS
TCK
TDO
Notes to Figure 2:
(1) Connect VCC to the same supply voltage as the configuration device.
(2) If you use the internal pull-up resistors of the configuration device, do not use external pull-up resistors on these pins.
January 2012
Altera Corporation
Combining Multiple Configuration Schemes
Page 4
Passive Serial and JTAG
You can use the download cables in different modes such as the JTAG mode or PS
mode. In each mode, the header of the download cable connects to different pins on
the FPGA. Therefore, two separate 10-pin headers are required on your board in order
to support two different modes of the download cable. Figure 3 shows a schematic
with two download cables. A download cable is used in JTAG mode to JTAG program
the configuration device. The second download cable is used in PS mode to configure
the FPGA using PS configuration. Set the MSEL pins to select PS as the configuration
mode.
Figure 3. JTAG Programming of Configuration Device with PS Configuration of FPGA Using a Configuration Device and
Download Cable
VCC (1)
Download Cable
(JTAG Mode)
10-Pin Male Header
1 kΩ
VCC (1)
1 kΩ
VCC
Download Cable
VCC (1)
(PS Mode)
V (1) 10-Pin Male Header
(2) CC
V (1)
(2) CC
(2)
VCC
VIO
VIO
FPGA
n
MSEL
GND
GND
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
1 kΩ
GND
(3) (3)
(3) (3)
nCEO
nCE
N.C.
Configuration Device
DATA
DCLK
OE
nCS
TMS
TCK
TDI
GND
(3)
nINIT_CONF
TDO
Notes to Figure 3:
(1) Connect VCC to the same supply voltage as the configuration device.
(2) If you use the internal pull-up resistors of the configuration device, do not use external pull-up resistors on these pins.
(3) To configure the FPGA with a download cable, you should either remove the configuration device from its socket or place a switch on the five
common signals between the download cable and the configuration device.
1
You should not attempt PS configuration with a download cable while a configuration
device is connected to an FPGA.
If you configure the FPGA using the download cable while the configuration device is
connected to the FPGA, the low signals driven on the nSTATUS and CONF_DONE pins
will pull the OE and nCS pins of the configuration device low. This will reset the
configuration device and cause the configuration device to try to configure the FPGA.
Combining Multiple Configuration Schemes
January 2012
Altera Corporation
Passive Serial and JTAG
Page 5
Figure 4 shows a schematic that allows configuration of the FPGA with either a PS
mode download cable or JTAG mode download cable. In addition, you can configure
the FPGA using the configuration device. A download cable is used in JTAG mode to
JTAG program the configuration device and FPGA. In Figure 4, the configuration
device and FPGA are in the same JTAG chain. Ensure the TDO signal drives out
enough amount of high voltage to meet the next device’s TDI minimum VIH . The TDO
output drives out the voltage of the I/O bank’s VCCIO where it resides. The second
download cable is used in PS mode to configure the FPGA using PS configuration. Set
the MSEL pins to select PS as the configuration mode.
Figure 4. Combining JTAG Programming of Configuration Device and FPGA with PS Configuration of FPGA Using a
Configuration Device and Download Cable
Download Cable
(JTAG Mode)
VCC (1) 10-Pin Male Header
Download Cable
(PS Mode)
VCC (1)
10-Pin Male Header
(2)
V (1)
(2) CC
(2)
VCC
VCC (1)
1 kΩ
VCC (1)
1 kΩ
VCC
VIO
VIO
FPGA
n
MSEL
GND
GND
DCLK
CONF_DONE
nCONFIG
nSTATUS
DATA0
1 kΩ
GND
(3) (3)
(3) (3)
nCEO
nCE
Configuration Device
DATA
DCLK
OE
nCS
TMS
TCK
TDI
N.C.
GND
VCC
(3)
nINIT_CONF
TDO
TDI
TRST
TMS
TCK
TDO
Notes to Figure 4:
(1) Connect VCC to the same supply voltage as the configuration device.
(2) If you use the internal pull-up resistors of the configuration device, do not use external pull-up resistors on these pins.
(3) To configure the FPGA with a download cable, you should either remove the configuration device from its socket or place a switch on the five
common signals between the download cable and the configuration device.
You can use Figure 1 on page 2 and Figure 4 for fast passive parallel (FPP) mode with
an exception—connect DATA[7..0] from the configuration device to the FPGAs that
support FPP configuration. You must set the MSEL pins accordingly.
January 2012
Altera Corporation
Combining Multiple Configuration Schemes
Page 6
Active Serial and JTAG
Active Serial and JTAG
For devices that support AS configuration, you can combine AS configuration with
JTAG-based configuration (Figure 5). This setup uses two 10-pin download cable
headers on the board. A download cable is used in JTAG mode to configure the FPGA
directly using the JTAG interface. The second download cable is used in AS mode to
program the serial configuration (EPCS) device in system using the AS programming
interface. Set the MSEL pins to select AS as the configuration mode. If you configure the
device using both schemes simultaneously, JTAG configuration takes precedence and
terminates AS configuration.
Figure 5. Combining JTAG Programming of Configuration Device and FPGA with AS Configuration of FPGA Using a
Configuration Device and Download Cable
VCC(1) VCC(1)
10 kΩ
VCC(1)
10 kΩ
10 kΩ
EPCS Device
FPGA
nSTATUS
CONF_DONE nCEO
nCONFIG
nCE
10 kΩ
MSEL
VCC
N.C.
10 kΩ
VCC
n
10 kΩ
GND
DATA
DCLK
nCS
ASDI
DATA
DCLK
nCSO
ASDO
Pin 1
TCK
TDO
TMS
TDI
Download Cable
(JTAG Mode)
10-Pin Male Header (Top View)
VCC
Pin 1
VCC(1)
VIO
1 kΩ
ByteBlaster II
(AS Mode)
10-Pin Male Header
GND
Note to Figure 5:
(1) Connect VCC to 3.3 V.
Document Revision History
Table 1 lists the revision history for this document.
Table 1. Document Revision History
Date
January 2012
Version
1.0
Combining Multiple Configuration Schemes
Changes
Initial release.
January 2012
Altera Corporation
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