datasheet for SYS82000RKXD by Apta Group

datasheet for SYS82000RKXD by Apta Group
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
hmp
2M x 8 SRAM MODULE
SYS82000RKXD - 70/85/10/12
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England. Tel. +44 (0191) 2930500. Fax. +44 (0191)
2590997
Issue 1.3 : February 2000
Description
Features
The SYS82000RKXD is a plastic 16Mbit Static
RAM Module housed in a standard 36 pin Single-InLine package organised as 2M x 8. This offers an
extremely high PCB packing density.
• Access Times of 70/85/100/120ns.
The module is constructed using four 512Kx8
SRAMs in TSOPII packages mounted on a FR4
epoxy substrate. Access times are 70, 85, 100 and
120ns.
The SYS82000RKXD is offered in standard and
low power versions, with the -L module having a low
voltage data retention mode for battery backed
applications.
• 36 Pin Industry Standard Single-In-Line package.
• 5 Volt Supply ± 10% .
• Power Dissipation :
Operating (min cycle)
Standby -L Version (CMOS)
610 mW (max).
2.2 mW (max).
• Completely Static Operation.
• Equal Access and Cycle Times.
• Low Voltage VCC Data Retention.
• Directly TTL Compatible.
• On-board Decoding & Capacitors.
• Compatible with the SYS8512RKX, SYS81000RKXB
and SYS82000RKX modules.
Pin Definition
Block Diagram
A0~A18
D0~7
/WE
/OE
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
/CS
/CS
/CS
/CS
/CS
A19
A20
Decoder
Pin Functions
Address Inputs
Data Input/Output
A0 - A20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D0 - D7
Chip Select
CS
Write Enable
WE
Output Enable
OE
No Connect
NC
Power (+5V)
VCC
Ground
A20
Vcc
WE
D2
D3
D0
A1
A2
A3
A4
GND
D5
A10
A11
A5
A13
A14
A19
CS
A15
A16
A12
A18
A6
D1
GND
A0
A7
A8
A9
D7
D4
D6
A17
Vcc
OE
GND
Package Details
Plastic 36 Pin Single-In-Line (SIP)
SYS82000RKXD - 70/85/10/12
Issue 1.3 February 2000
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Parameter
Symbol
(2)
T
Voltage on any pin relative to VSS
Power Dissipation
Storage Temperature
V
PT
TSTG
Min
Typ
Max
Unit
-0.3
-55
4.0
-
7.0
125
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) VT can be -3.0V pulse of less than 30ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
(Commercial)
(Industrial)
Symbol
Min
Typ
Max
Unit
VCC
VIH
VIL
TA
TAI
4.5
2.2
-0.3
0
-40
5.0
-
5.5
VCC+0.3
0.8
70
85
V
V
V
o
C
o
C
TA 0 to 70 oC
DC Electrical Characteristics (VCC=5V±10%)
Parameter
I/P Leakage Current
Symbol Test Condition
Min Typ
max
Unit
ILI
0V < VIN < VCC
-4
-
4
µA
Output Leakage Current
ILO
CS = VIH, VI/O = GND to VCC
-4
-
4
µA
Average Supply Current
ICC1
Min. Cycle, CS = VIL,VIL<VIN<VIH
-
-
110
mA
TTL levels
ISB1
CS = VIH
-
-
12
mA
CMOS levels
ISB2
CS > VCC-0.2V, 0.2<VIN<VCC-0.2V
-
-
8
mA
-L Version (CMOS)
ISB3
CS > VCC-0.2V, 0.2<VIN<VCC-0.2V
-
-
400
µA
VOL
IOL = 2.1mA
-
-
0.4
V
VOH
IOH = -1.0mA
2.4
-
-
V
Address,OE,WE
Standby Supply Current
Output Voltage
Typical values are at VCC=5.0V,TA=25oC and specified loading.
Capacitance (VCC=5V±10%,TA=25oC)
Parameter
Input Capacitance (Address,OE,WE)
I/P Capacitance (other)
I/O Capacitance
Note: Capacitance calculated, not measured.
Symbol Test Condition
CIN1
CIN2
CI/O
VIN = 0V
VIN = 0V
VI/O = 0V
2
max
Unit
32
8
40
pF
pF
pF
SYS82000RKXD - 70/85/10/12
Issue 1.3 February 2000
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
I/O Pin
645Ω
* Input rise and fall times: 5ns
1.76V
* Input and Output timing reference levels: 1.5V
100pF
* Output load: see diagram
* VCC=5V±10%
Operation Truth Table
CS
OE
WE
DATA PINS
SUPPLY CURRENT
MODE
H
X
X
High Impedance
ISB1 , ISB2 , ISB3
Standby
L
L
H
Data Out
ICC1
Read
L
H
L
Data In
ICC1
Write
L
L
L
Data In
ICC1
Write
L
H
H
High-Impedance
ISB1 , ISB2 , ISB3
High-Z
Notes : H = VIH : L =VIL : X = VIH or VIL
Low Vcc Data Retention Characteristics - L Version Only
Parameter
VCC for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Notes
Symbol
VDR
ICCDR1 (2)
tCDR
tR
Test Condition
min
CS > VCC-0.2V
VCC = 3.0V, CS > VCC-0.2V
TOP = 0°C to 40°C
See Retention Waveform
See Retention Waveform
2.0
0
5
(1) Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
3
typ(1)
-
max
Unit
200
-
V
µA
ns
ms
SYS82000RKXD - 70/85/10/12
Issue 1.3 February 2000
AC OPERATING CONDITIONS
Read Cycle
-70
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
-85
-10
-12
Symbol
min
max
min
max
min
max
min
max
Unit
tRC
tAA
tACS
tOE
tOH
tCLZ
tOLZ
tCHZ
tOHZ
70
10
10
5
0
0
70
70
35
25
25
85
10
10
5
0
0
85
85
45
30
30
100
10
10
5
0
0
100
100
50
35
35
120
10
10
5
0
0
120
120
60
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-70
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
Symbol
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
tDW
tDH
tOW
-85
-10
-12
min
max
min
max
min
max
min
max
Unit
70
60
60
0
50
3
0
30
0
5
25
-
85
75
75
0
55
3
0
35
0
5
30
-
100
80
80
0
60
3
0
40
0
5
35
-
120
100
100
0
70
3
0
45
0
5
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
SYS82000RKXD - 70/85/10/12
Issue 1.3 February 2000
Read Cycle Timing Waveform (1,2)
t RC
Address
t AA
OE
t OE
t OH
t OLZ
CS
t ACS
Don't
care.
t OHZ (3)
t CLZ (4,5)
Dout
Data Valid
t CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
tWC
Address
t WR(7)
OE
t AS(6)
t AW
t CW
CS
Don't
Care
WE
t OHZ(3,9)
t OW
t WP(2)
High-Z
Dout
t DW
Din
High-Z
t DH
Data Valid
5
(8)
SYS82000RKXD - 70/85/10/12
Issue 1.3 February 2000
Write Cycle No.2 Timing Waveform (1,5)
tWC
Address
t AS(6)
t WR(7)
t CW
CS
t AW
t WP(2)
WE
tOH
t WHZ(3,9)
t OW
High-Z
Dout
t DW
(8)
(4)
Don't
Care
t DH
High-Z
Din
Data Valid
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS and WE low.
(3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state.
Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes.
(7) CS or WE must be high during address transitions.
(8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the
output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
t CDR
tR
2.2V
2.2V
V DR
CS
CS > Vcc -0.2V
0V
6
SYS82000RKXD - 70/85/10/12
Package Information
Issue 1.3 February 2000
Dimensions in mm
Plastic 36 Pin Single-In-Line (SIP)
15.70 MAX
97.20 MAX
3.40 MAX
1.00
1
3.50 +/- 0.50
0.50 Typ.
2.54 Typ.
Ordering Information
SYS82000RKXDLI-70
Speed
70
85
10
12
=
=
=
=
70 ns
85 ns
100 ns
120 ns
Temperature Range
Blank = Commercial Temperature
I = Industrial Temperature
Power Consumption
Blank = Standard Part
L = Low Power Part
Package
RKXD = Plastic 36 Pin Single-In-Line
(SIP)
Organization
82000 = 2M x 8
Memory Type
SYS = Static RAM
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for aparticular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written approval
of a company director.
7
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