AOZ8300 Ultra-Low Capacitance TVS Diode Array General Description

AOZ8300 Ultra-Low Capacitance TVS Diode Array  General Description
AOZ8300
Ultra-Low Capacitance TVS Diode Array
General Description
Features
The AOZ8300 is a transient voltage suppressor array
designed to protect high speed data lines from ESD and
lightning.
 ESD protection for high-speed data lines:
This device incorporates eight surge rated, low
capacitance steering diodes and a TVS in a single
package. During transient conditions, the steering diodes
direct the transient to either the positive side of the power
supply line or to ground. They AOZ8300 may be used to
meet the ESD immunity requirements of IEC 61000-4-2,
Level 4. The TVS diodes provide effective suppression
of ESD voltages: ±15 kV (air discharge) and ±8 kV
(contact discharge).
The AOZ8300 comes in a Halogen Free and RoHS
compliant, SOT-23 package and is rated over a
-40 °C to +85 °C ambient temperature range. Both
packages are compatible with lead free and SnPb
assembly techniques. The small size, low capacitance,
and high ESD protection makes the AOZ8300 ideal for
protecting high speed video and data communication
interfaces.
– IEC 61000-4-2, level 4 (ESD) immunity test
– ±30 kV (air discharge) and ±30 kV (contact discharge)
– IEC 61000-4-5 (Lightning) 20 A (8/20 µs)
– IEC 61000-4-4 (EFT) 40 A (5/50 ns)
– Human Body Model (HBM) ±24 kV
 Protects four I/O lines
 Low clamping voltage
Applications
 USB 2.0 power and data line protection
 Video graphics cards
 Monitors and flat panel displays
 Digital Video Interface (DVI)
 10/100/1000 Ethernet
 Notebook computers
Typical Application
AOZ8300
TP1+
TP1TP2+
1
2
3
RJ45
Connector
TP2-
4
TP3+
5
GbE
Ethernet
PHY
6
7
TP3-
8
TP4+
AOZ8300
TP4-
Figure 1. 10/100/1000 Ethernet Port Connection
Rev. 1.0 December 2014
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Page 1 of 8
AOZ8300
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ8300CI-05
-40 °C to +85 °C
SOT23-6
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
CH1
1
6
CH4
VN
2
5
NC
CH2
3
4
CH3
SOT23-6
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
Peak Pulse Current (IPP), tP = 8/20 µs
20 A
Peak Power Dissipation (8 x 20 µs @ 25 °C)
450 W
Storage Temperature (TS)
-65 °C to +150 °C
ESD Rating per IEC61000-4-2,
Contact(1)
±30 kV
ESD Rating per IEC61000-4-2,
Air(1)
±30 kV
ESD Rating per Human Body Model
(2)
±30 kV
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150 pF, RDischarge = 330 Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100 pF, RDischarge = 1.5 kΩ.
Maximum Operating Ratings
Parameter
Rating
Junction Temperature (TJ)
Rev. 1.0 December 2014
-40 °C to +125 °C
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Page 2 of 8
AOZ8300
Electrical Characteristics
TA = 25°C unless otherwise specified.
Symbol
VRWM
VBR
Parameter
Reverse Working Voltage
Conditions
Min.
(5)
IT = 100 µA, between I/O and VIN
IR
Reverse Leakage Current
VRWM = 2.5 V, between I/O and VIN
VF
Diode Forward Voltage
IF = 15 mA
VCL
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 5 A, tp = 100 ns, any I/O pin to
Ground(3)(6)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 10 A, tp = 100 ns, any I/O pin to
Ground(3)(6)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 30 A, tp = 100 ns, any I/O pin to
Ground(3)(6)
Junction Capacitance
VR = 0 V, f = 1 MHz, any I/O pin to Ground
Cj
Channel Input Capacitance
Matching
Max.
Units
2.5
V
Between I/O and VIN(4)
Reverse Breakdown Voltage
Cj
Typ.
VR = 0 V, f = 1 MHz, between I/O
2.8
0.70
V
0.1
µA
1
V
3.5
-3.5
V
V
4.5
-5
V
V
9
-12
V
V
3.5
pF
0.2
pF
0.85
2.5
pins(3)
Notes:
3. These specifications are guaranteed by design.
4. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
5. VBR is measured at the pulse test current IT.
6. Measurements performed using a 100 ns Transmission Line Pulse (TLP) system.
Rev. 1.0 December 2014
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Page 3 of 8
AOZ8300
Typical Performance Characteristics
Forward Current vs. Forward Voltage
(tperiod = 100ns, tr = 1ns)
30
0
25
-5
Forward Current (A)
TLP Current (A)
TLP Current vs. Clamping Voltage
20
15
10
5
-10
-15
-20
-25
-30
0
-35
0
1
2
Rev. 1.0 December 2014
3
4
5
6
Clamping Voltage (V)
7
8
-10
-8
-6
-4
-2
0
Forward Voltage (V)
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Page 4 of 8
AOZ8300
Application Information
The AOZ8300 TVS is design to protect up to four data
lines from damaging transient over-voltage by clamping
the voltage to a reference. When the transient on a
protected data line exceeds the reference voltage, the
steering diode is forward bias thereby conducting the
harmful ESD transient away from the sensitive circuitry
under protection.
PCB Layout Guidelines
Printed circuit board layout is key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
most important design consideration. The AOZ8300
devices should be located as close as possible to the
noise source. AOZ8300 devices should be used on all
data and power lines that enter or exit the PCB at the
I/O connector. In most systems, surge pulses occur on
data and power lines that enter the PCB through the
I/O connector. Placing the AOZ8300 devices as close as
possible to the noise source ensures that a surge voltage
will be clamped before the pulse is coupled into adjacent
PCB traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8300 device. Long signal traces
will act as antennas and receive energy from fields that
are produced by the ESD pulse. By keeping line lengths
as short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced.
Minimize interconnecting line lengths by placing devices
with the most interconnects as close together as
possible. The protection circuits should shunt the surge
voltage to either the reference or chassis ground.
Shunting the surge voltage directly to the IC’s signal
ground may cause ground bounce. The clamping
performance of the TVS diodes on a single ground PCB
can be improved by minimizing the impedance with
relatively short and wide ground traces. The PCB layout
and IC package parasitic inductances can cause
significant overshoot to the TVS’s clamping voltage.
Rev. 1.0 December 2014
The inductance of the PCB can be reduced by using
short trace lengths and multiple layers with separate
ground and power planes. One effective method to
minimize loop problems is to incorporate a ground plane
in the PCB design. The AOZ8300 ultra-low capacitance
TVS is designed to protect four high speed data
transmission lines from transient over-voltages by
clamping them to a fixed reference. The low inductance
and construction minimizes voltage overshoot during
high current surges. When the voltage on the protected
line exceeds the reference voltage the internal steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the IO terminals or connectors to
restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4mm.
10. Keep the chassis ground trace length-to-width ratio
< 5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
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Page 5 of 8
AOZ8300
Package Dimensions, SOT23, 6L
Gauge Plane
Seating Plane
D
0.25mm
e1
C
E E1
L
θ1
e
b
A2
A
0.10mm
A1
Dimensions in millimeters
RECOMMENDED LAND PATTERN
1.20
0.80
2.40
0.95
0.63
Symbols
A
A1
A2
b
C
D
E
E1
e
e1
L
θ
Min.
0.90
0.00
0.70
0.30
0.08
2.70
2.50
1.50
Nom.
—
—
1.10
0.40
0.13
2.90
2.80
1.60
0.95 BSC
1.90 BSC
0.30
—
0°
—
Max.
1.25
0.15
1.20
0.50
0.20
3.10
3.10
1.70
0.60
8°
Dimensions in inches
Symbols
A
A1
A2
b
C
D
E
E1
e
e1
L
θ
Min.
0.035
0.000
0.028
0.012
0.003
0.106
0.098
0.059
Nom. Max.
—
0.049
—
0.006
0.043 0.047
0.016 0.020
0.005 0.008
0.114 0.122
0.110 0.122
0.063 0.067
0.037 BSC
0.075 BSC
0.012
—
0.024
0°
—
8°
UNIT: mm
Notes:
1. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each.
2. Dimension “L” is measured in gauge plane.
3. Tolerance 0.100mm (4 mil) unless otherwise specified.
4. Followed from JEDEC MO-178C & MC-193C.
6. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
Rev. 1.0 December 2014
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Page 6 of 8
AOZ8300
Tape and Reel Dimensions, SOT23, 6L
P2
Tape
A
P1
A–A
D1
D0
E1
K0
E2
B0
A0
P0
T
E
A
Feeding Direction
Unit: mm
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
SOT-23
3.15
±0.10
3.20
±0.10
1.40
±0.10
1.50
±0.05
1.00
±0.10/-0.0
8.00
±0.30
1.75
±0.10
3.50
±0.05
4.00
±0.10
4.00
±0.10
2.00
±0.05
0.23
±0.03
Reel
W1
S
R
K
M
J
H
N
Unit: mm
Tape Size
Reel Size
M
N
W1
H
S
K
R
J
8 mm
ø177.80
ø177.80
MAX.
ø55.00
MIN.
8.40
+1.50/-0.00
ø13.00
+0.50 / -0.20
1.50
MIN.
10.10
MIN.
12.70
4.00
+0.10/-0.10
Leader/Trailer and Orientation
Unit Per Reel:
3000pcs
Trailer Tape
300mm min.
Rev. 1.0 December 2014
Components Tape
Orientation in Pocket
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Leader Tape
500mm min.
Page 7 of 8
AOZ8300
Part Marking
AOZ8300CI
ALOW
LT
(SOT-23)
Assembly Lot Code
Part Number Code
Option & Assembly Location Code
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.0 December 2014
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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