Volume Forty-Four NEWS BRIEFS 2 IN-DEPTH ARTICLES DESIGN SHOWCASE Reference voltage for multiple ADCs 3 Designing compact telecom power supplies 6 Small, high-voltage boost converters 15 Compact, inductorless boost circuit regulates white-LED bias current 22 Analog switch lowers relay power consumption 23 LOW-NOISE REFERENCE CIRCUIT 3V 3V 0.1µF 0.1µF 2.048V N.C. 29 31 1 32 2 16.2kΩ 3 IC1 1µF 3 10Hz LOWPASS FILTER 4 - 0.1µF 5 + IC2 2 1 162Ω 2 1 REFOUT REFIN REFP REFN IC3 ADC 1 COM 100µF 0.1µF 0.1µF 0.1µF 10Hz LOWPASS FILTER 0.1µF NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs. N.C. 29 31 32 1 0.1µF 2 REFOUT REFIN REFP REFN COM IC4 ADC N 0.1µF 0.1µF 0.1µF For ultrasound applications, a single, low-noise reference circuit drives up to 1000 ADCs. (See article inside, page 3.) 2.2µF 10V News Briefs MAXIM REPORTS REVENUES AND EARNINGS FOR THE SECOND QUARTER OF FISCAL 2002 Maxim Integrated Products, Inc., (Nasdaq: MXIM) reported net revenues of $247.1 million for its fiscal second quarter ending December 29, 2001, down from the $438.3 million reported for the second quarter of fiscal 2001 and up from the $239.4 million reported for the first quarter of fiscal 2002. Net income for the quarter was $62.6 million, a decrease from the $122.2 million reported last year and an increase over the $61.3 million reported for the previous quarter. Diluted earnings per share were $0.18 for the second quarter, down from the $0.34 reported for the same period a year ago and up from the $0.17 reported for the first quarter of fiscal 2002. During the quarter, cash and short-term investments increased $22.1 million after the Company repurchased 2.0 million shares of its common stock for $67.8 million and acquired a total of $18.7 million of capital equipment. The stock repurchase was enabled by temporary suspension by the SEC of regulations relating to stock repurchases after pooling-of-interests transactions. Accounts receivable decreased by $4.7 million in the second quarter to $94.8 million, and inventories decreased $4.9 million to $154.4 million. Gross margin for the second quarter increased slightly to 70.1%, after increasing inventory reserves $3.0 million, compared to 70.0% reported for the first quarter. Research and development expense increased from the $66.0 million reported in the first quarter or 27.6% of net revenues to $68.6 million or 27.7% of net revenues, primarily the result of hiring additional engineers and investing in new product development. Selling, general and administrative expenses decreased from $25.1 million in the first quarter to $22.9 million in the second quarter, primarily due to control of discretionary spending. Second quarter bookings were approximately $230 million, a 9% increase over the first quarter’s level of $211 million. Turns orders received during the quarter were $125 million, a 23% increase over the $102 million received in the prior quarter (turns orders are customer orders that are for delivery within the same quarter and may result in revenue within the same quarter if the Company has available inventory that matches those orders). Order cancellations were down 39% from the first quarter and down 81% from the year ago level. Bookings increased in all geographic regions except the U.S., where bookings decreased slightly compared to the prior quarter. Bookings increased in most of the Company’s 14 business units, with particular strength in those business units with products for portable equipment. Bookings were down from the first quarter for those business units with products for the test equipment, fiber, and telecommunication equipment markets. Second quarter ending backlog shippable within the next 12 months was approximately $187 million, including $170 million requested for shipment in the third quarter of fiscal 2002. Jack Gifford, Chairman, President, and Chief Executive Officer, commented on the quarter: “We are encouraged by the continued increase in bookings during our second quarter. Although visibility remains limited, we currently expect bookings to increase again in our third quarter.” Mr. Gifford continued: “We are confident that inventory levels for much of the end equipment that our products address are either significantly reduced or have moderated. We remain cautious about the short-term outlook for the telecom and ATE markets, where our customers are still working through inventories. Although we believe that our customers’ visibility is better now than it has been in the past several quarters, turns orders remain high because of our short lead times. As lead times increase, we expect customers to place orders beyond their immediate needs.” Mr. Gifford concluded: “Unlike some companies in our industry, Maxim has continued to increase its engineering headcount and its investment in research and development activities. In our second quarter, R&D expenses were nearly 28% of net revenues, a historically high level for the Company and a remarkably high level for any mature company in our industry.” Certain statements in this press release are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. These statements involve risk and uncertainty. All forward-looking statements included in this news release are made as of the date hereof, based on the information available to the Company as of the date hereof, and the Company assumes no obligation to update any forward-looking statement. Maxim Integrated Products is a leading international supplier of quality analog and mixed-signal products for applications that require real world signal processing. ADC accuracy Reference voltage for multiple ADCs For many applications, gain and noise level have a major effect on ADC accuracy. The gain of an ADC is represented by the slope of its transfer function, which relates analog inputs to the allowable range of digital output codes. One way to quantify gain is to measure the full-scale (FS) input range, which is directly controlled by the reference-voltage level. For medical ultrasound imaging systems, variation in the full-scale range of the ADCs can cause errors in beam formation. It also varies the ADCs’ clipping point—an effect that may be important in certain signal-demodulation schemes. Ultrasound-imaging systems usually host a large array of analog-to-digital converters (ADCs). Not only do these systems require precise channel-to-channel matching, but also a careful design of the voltage reference system in order to maintain sufficient dynamic performance. These reference systems typically provide a precise, low-noise reference to a large bank of converters. To further ensure accuracy and stability, the ADCs’ reference inputs should be buffered to minimize the loading effects on the reference system. In response to these requirements, high-speed ADC manufacturers have begun supplying converters with reference inputs that can support the use of both the internal precision reference and an external, precision, reference-voltage source. An ADC’s noise level determines its useable dynamic range; this dynamic range should generally be as large as possible. The reference-noise component of ADC noise can be additive or multiplicative. Additive noise is easily filtered by local bypass capacitors on the individual ADCs, which in most designs are already present to optimize the ADC’s dynamic performance. Multiplicative noise, on the other hand, is more insidious. For ultrasound applications, reference noise in the audio frequency spectrum can modulate large “stationary” signals in the RF spectrum. Such signals are produced by stationary tissue in the ultrasound target. Audio modulation produces sidebands on the RF signal that can be demodulated by a Doppler detector, producing audio tones in the detected Doppler output signal. Medical ultrasound-imaging systems, for example, commonly use a large number of ADCs in the receiver’s beamforming electronics, usually organized in groups of 16, 24, 32, etc. Maximum beam accuracy requires the absolute minimum beamforming path errors. A major source of these errors can be traced to poor accuracy in terms of noise and the actual reference voltage present at each of the individual ADCs. Other error sources include variances in the distributed load seen by the reference’s source. In any particular system architecture, this load can consist of the many individual resistive and capacitive loads seen by the reference. Several approaches can provide the reference voltage for such ADC arrays: To estimate the amount of audio noise tolerable in an ultrasound application, assume a nearly full-scale RF signal applied to a 10-bit ADC like the MAX1448. The dynamic range of that device (almost 60dB) implies a noise floor of -60dBFS. That noise level can be normalized to a 1Hz bandwidth. The Nyquist bandwidth for an 80MHz sampling rate is 40MHz. The correction factor is √40MHz = 76dB, which places the ADC’s noise floor at -60dBFS 76dBFS = -136dBFS. Because a conservative design requires the reference-voltage noise to be at least 20dB lower (-156dBFS), a 2.0V reference requires an extremely low noise level of 33nVP-P (approximately 8nVRMS/√Hz). • Individual on-chip references. Though it offers a convenient connection locally to each ADC, this option features relatively poor matching between the converters. • A single, external reference voltage applied to all reference inputs of the ADC array. Such a configuration allows the user to engineer an external reference voltage of arbitrary accuracy, but incurs error due to small variations among the resistor ladders (one ladder internal to each ADC). A multi-ADC array may require a reference voltage more accurate than the one internal to each converter (the reference internal to MAX144x converters, for example, is ±1% accurate). The following two circuits are submitted as reference designs for such arrays. They feature a single, common low-frequency noise filter, and they achieve high-frequency noise suppression with local decoupling capacitors on individual ADCs. • An external reference driving the ADCs’ referenceladder taps directly. This option delivers maximum gain accuracy by directly controlling the reference voltage applied to each ADC ladder. However, it requires driving the (relatively) low resistance of the ladders, and some ADCs do not allow access to that internal bias point. 3 building blocks in the signal path of an ultrasound receiver. Note that proper power-up/down sequencing is ensured because all active parts are driven from the same supply voltage. That approach yields excellent gain matching and a very low noise level with minimal circuitry and should suffice in many applications that require multiple gainmatched ADCs. Single external reference Multiple-converter systems based on the MAX144x (IC3, IC4) family are well-suited for use with a common reference voltage. The REFIN pin of those converters can be connected directly to an external reference source, eliminating the need for any circuit modification. Moreover, the high input impedance of REFIN (even of multiple REFIN terminals connected in parallel) draws only a small load current. Generating a precision external reference A precision source like the MAX6062 (IC1) generates an external DC level of 2.048V (Figure 1), and exhibits a noisevoltage density of 150nV/√Hz. Its output passes through a 1pole lowpass filter (with 10Hz cutoff frequency) to an op amp (IC2) like the MAX4250, which buffers the reference before its output is applied to a second 10Hz lowpass filter. IC2 provides a low offset voltage (for high-gain accuracy) and a low noise level. The passive 10Hz filter following the buffer attenuates noise produced in the voltage-reference and buffer stages. This filtered-noise density, which decreases for higher frequencies, meets the noise levels specified for precision ADC operation. For applications requiring more stringent gain matching (Figure 2), the MAX144x family again is well suited. Connecting each REFIN to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. These voltages can have an arbitrarily tight tolerance, and the ADCs track them within 0.1% (typ). ADCs of this family also feature a 4kΩ resistance across the ladder reference connection, which allows the load to be easily driven even with many ADCs in parallel. A DC level of 2.500V can be generated by a precision source (IC1) such as the MAX6066, followed by a 10Hz lowpass filter and precision voltage divider. The buffered outputs of this divider are set to 2.0V, 1.5V, and 1.0V, with an accuracy that depends on the tolerance of the divider resistors. Converters of the MAX144x family are specified for a typical gain error of ±4.4% (better than ±0.5dB). This performance is better than the gain tolerance of all other 3V 3V 0.1µF 0.1µF 2.048V N.C. 29 31 1 32 2 16.2kΩ 3 IC1 1µF 3 10Hz LOWPASS FILTER 4 - 0.1µF 5 + IC2 2 1 162Ω 2 1 REFOUT REFIN REFP REFN IC3 ADC 1 COM 100µF 0.1µF 0.1µF 0.1µF 10Hz LOWPASS FILTER 0.1µF NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs. N.C. 29 31 32 1 0.1µF 2 0.1µF 0.1µF 0.1µF Figure 1. For ultrasound applications, a single, low-noise reference circuit drives up to 1000 ADCs. 4 REFOUT REFIN REFP REFN COM IC4 ADC N 2.2µF 10V Those three voltages are buffered by the quad op amp IC2, which is selected for its low noise and DC offset. The individual voltage followers are connected to 10Hz lowpass filters which filter both the reference-voltage noise and buffer-amplifier noise to a level of 3nV/√Hz. The 2.0V and 1.0V reference voltages set the differential full-scale range of the associated ADCs at 2VP-P. The 2.0V and 1.0V buffers drive the ADCs’ internal-ladder resistances between them: 4kΩ divided by the number of ADCs in the circuit. As an example, 32 ADCs will draw 8mA from those supplies—a load current well within the capability of IC2. that require more than 32 matched ADCs, a voltage reference and divider string common to all converters are highly recommended. Conclusion Systems requiring large numbers of data converters with good channel-to-channel matching require careful design of the voltage-reference system. The use of a common, highprecision, low-noise reference driving all the ADCs is a valuable approach for achieving high-accuracy matching. The flexible reference inputs and exceptional dynamic performance of 10-bit ADCs in the MAX144x family make them compelling candidates for such applications. This configuration’s gain accuracy can be good, depending on the accuracy grade of IC1 and the tolerance of resistors in the voltage divider. The gain matching of each ADC in this configuration is typically 0.1%. With the noise level below 3nV/√Hz at 100Hz, this circuit provides exemplary performance. As in Figure 1, the common power supply for all active components removes any concern about power-supply sequencing when powering up or down. (A similar idea appeared in the 1/24/02 issue of EDN.) References: 1. Maxim MAX1444 data sheet, Rev. 0, 10/00. 2. Maxim MAX1448EVKIT data sheet, Rev. 1, 12/01. 3. Maxim MAX4249–MAX4252 data sheet, Rev. 4, 1/02. 4. Maxim MAX6061–MAX6068 data sheet, Rev. 1, 5/01. With the outputs of the op amp buffers matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs. For applications 3V 0.1µF N.C. 29 31 1 2 21.5k Ω 3 IC1 2 3 + - 4 IC2A 11 1 1.5V 5 0.1µF + 21.5kΩ 21.5kΩ 9 2 0.1µF REFP REFN COM IC3 ADC 1 0.1µF 0.1µF 1.5V AT 0 4 7 - 4 IC2C 11 47Ω 10µF 6V 1.47kΩ 21.5kΩ 1.0V 10 + MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP. 1 REFIN 3V IC2B 6 11 3V 2.0V AT 8mA 47Ω 10µF 6V 330µF 1.47kΩ 6V 21.5kΩ 1µF 32 3V 2V REFOUT 3V 8 330µF 6V 0.1µF 1.0V AT -8mA 47Ω 10µF 6V 330µF 6V N.C. 1.47kΩ 29 31 REFOUT REFIN 32 REFP 1 REFN 2 COM NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs. 0.1µF 0.1µF 0.1µF Figure 2. Also for ultrasound applications, a precision, low-noise reference circuit drives up to 32 ADCs. 5 IC4 ADC 2 2.2µF 10V Designing compact telecom power supplies telecom power supplies. It enables the design of small, efficient, power-converter circuits. A fixed-switching frequency of 262kHz controls switching losses while allowing moderately small power components. The IC includes undervoltage lockout capability with large hysteresis and a low startup current. This results in lowloss designs for power supplies that feature a wide inputvoltage range and low output power. Cycle-by-cycle current limiting (achieved with a fast internal comparator) reduces overdesign in the MOSFET and transformer. Other features include maximum-dutycycle limiting and high-peak capability for the source and sink-drive currents. A reference design (Figure 1) illustrates the 5W flyback converter with an input-voltage range of 36V to 72V. Telecom power supplies are specified for operation over a wide input-voltage range (36V to 75V) but with circuit performance optimized at 48V. Such circuit designs should be compact, efficient, and have a low profile to comply with the tight spacing between cards. This article discusses a 5W flyback converter for telecom applications, based on the MAX5021—a universal offline power-supply controller. Telecom systems include numerous line cards. Connected in parallel to the high-power backplane, each has its own input-filter capacitor and low-voltage power converter. The large number of input-filter capacitors in parallel limits the value of each to a few microfarads, making the power-supply design fairly difficult. Power-stage design The first step in designing a power supply is deciding on a conversion topology. Topology selection criteria include the input-voltage range, output voltage, peak currents in the primary and secondary circuits, efficiency, form factor, and cost. The MAX5021 IC is a high-frequency, current-mode PWM controller suitable for wide-input-range, isolated 48VIN EPC13-CTX03-15498 COOPER 1 T1 J1 R11 7.5kΩ C1 1µF, 100V C2 1µF, 100V D2 MBRS340 1 C10 560pF R1 82Ω J3 C5 330µF, 10V NS_A D3 BAS21LT1 J2 GND L1 2kΩ AT 100MHz D1 C4 0.22µF 5 6 VCC U1 NDRV MAX5021 VIN OPTO 1 Q1 IRF5802 R10 51Ω 2 R5 249kΩ COM C7 10nF 7 5 3 J4 R8 510Ω MOC207 U3 1 6 C8 0.22µF 4 C9 10µF C11 2.2µF, 250VAC MMBD914 1 5V, 1A +VOUT L2 120Ω AT 100MHz C6 220µF 3 R12 47kΩ 4 TLV431AC 5 GND 2 CS 1 R9 1.3Ω C3 1nF U2 R7 8.06kΩ R3 100Ω R4 1.3Ω Figure 1. Based on the MAX5021 PWM controller, this flyback converter for telecom applications delivers 5W at 5V. 6 R6 24.9kΩ • Calculate the AL value of the core. • Calculate the RMS current in the primary, and estimate the secondary RMS current. • Consider the proper winding sequence and transformer construction for low leakage. 1) Use the following equation to estimate the minimum area product required: The best choice for a 5W output with a 1:2 input-voltage range and small form factor is a flyback topology whose minimum component count reduces the cost and form factor. The flyback transformer can be designed to operate either in continuous or discontinuous mode. Discontinuous mode causes the transformer core to complete its energy transfer during the off cycle, and continuous mode allows the next cycle to begin before the energy transfer is complete. In the present case, discontinuous mode is chosen for the following reasons: it maximizes energy storage in the magnetic component (thereby reducing the component’s size); it simplifies compensation (no right-half-plane zero); and it yields a higher unity-gain bandwidth. AP ≥ (1.1 × POUT × DMAX) ...( m 4 ) η × KP × KU × J × KT × BMAX × ƒ SW ( MIN) AP ≥ (2 × POUT ) × 10 −12 ...( m 4 ) η × BMAX where: η = expected efficiency of the converter; KP = area assigned to the primary (usually 0.5); KT = ratio of RMS to average current in the primary (0.55 to 0.65 for discontinuous flyback); KU = window utilization factor (0.4 to 0.5); J = current density (9.862x106A/m2 for winding temperature rise less than 40°C); and BMAX = maximum operating flux density in Teslas (use between 0.12T to 0.15T). A disadvantage of the discontinuous operating mode is the higher ratio of peak-to-average current in the primary and secondary circuits. A higher ratio means higher RMS current, which leads to higher loss and lower efficiency. For low-power conversion, the advantages of discontinuous mode easily surpass the disadvantages. Moreover, the IC’s drive capability is sufficient for driving the large switching MOSFET necessary to carry these peak currents. A telecom application using the MAX5021 in this topology easily achieves power outputs to 15W using standard MOSFETs. Select a core with area product (AP) equal to or greater than the figure calculated above, and note its core cross section area. Refer to the following table for output power vs. core size, AP, and core cross-section area (Ae): Transformer design Output Power vs. Core Size The key to low loss and high efficiency in the transformer is a proper core. The core and the winding-area product determine the amount of power the transformer can handle with an acceptable rise in temperature. Also considered in the core selection are the topology (ratio of average to RMS current in the winding), output current, efficiency, and form factor. The design of a discontinuous-mode transformer is explained below, step by step. Note that the first equation is a general one, and the second is specific to the MAX5021 power supply with a 40°C temperature rise. Output Power (W) Core Size Ap (mm4) Ae (mm2) Up to 2 EPC-10 30 9.4 3 to 4 EEM-12.7 90 12 5 to 8 EPC-13 145 12.5 9 to 12 EPD-15 216 13.5 (Refer to the Appendix on page 13 for an example.) 2) As discussed earlier, discontinuous operation requires that the core be discharged during the off-cycle. Secondary inductance determines the time required to discharge the core. Use the following equations to calculate secondary inductance: • Estimate the minimum area-product requirement, and select a core and bobbin with suitable form factor. • Calculate the secondary-winding inductance for guaranteed core discharge within the minimum off-time. • Calculate the primary-winding inductance for sufficient energy to support maximum load. • Calculate the number of turns in the primary. • Calculate the number of turns in the secondary and bias windings. 7 LS ≤ (VO + VD ) × (DOFF( MIN) )2 ...(H) 2 × IOUT × ƒSW (MAX ) LS ≤ 430 × 10 −9 × (VO + VD ) ...(H) IOUT where: VD = secondary-diode forward-voltage drop in volts. IOUT = maximum-rated output current in amperes. AL = 7) The transformer manufacturer must know the RMS currents in the primary, secondary, and bias windings to decide the thickness of the wire. To keep skin-effect loss under control, only wires thinner than 28AWG are recommended. Multiple wires in parallel can be used to achieve the required copper thickness. Multifilar windings are very common in high-frequency converters. Maximum RMS current in the primary and secondary windings occurs at 50% duty cycles (minimum input voltage) and maximum output power. Use the following equations to calculate primary and secondary RMS currents: POUT DMAX IPRMS = × ...( A ) 0.5 × DMAX × η × VIN ( MIN ) 3 3) Rising current in the primary builds energy in the core during the on-cycle, which is then released to deliver output power during the off-cycle. The primary inductance must hold enough energy during the on-time to support the maximum output power. LP = LP = VIN ( MIN ) 2 × DMAX 2 × η 2 × POUT × ƒS( MAX ) 0.4 × 10 −6 × VIN ( MIN )2 × η ...(H) POUT 4) Next, calculate the primary number of turns necessary to keep the maximum flux density within limits at the maximum V-s product across the primary. The maximum-operating peak current occurs at the maximum duty cycle. NP = NP = IPRMS = VIN ( MIN ) × DMAX Ae × BMAX × ƒS( MIN ) ISRMS = 2.1 × 10 −6 × VIN ( MIN ) Ae × BMAX 1.63 × POUT ...( A ) η × VIN ( MIN ) IOUT DOFF ( MAX ) ...( A ) 0.5 × DOFF ( MAX ) 3 ISRMS = 1.63 × IOUT.....( A ) Bias current is usually less than 10mA, so the selection of wire thickness depends more on the convenience of winding the wire than its current capacity. where: Ae = core cross section area in square meters. 5) Round off the primary number of turns to the closest integer, and calculate the number of turns for the secondary and bias windings using the rounded-off primary number of turns. Refer to the following equation: NS = NP × nH LP × 10 9... 2 2 NP 8) The winding technique and sequencing is important in achieving a lower leakage-inductance spike at switch turn-off. As an example, interleave the secondary between two primary halves and keep the bias winding close to the secondary, so the bias voltage follows the output voltage. LS LP MOSFET selection 11.7 NBIAS = VOUT + 0.2 Selection criteria for the MOSFET include maximum drain voltage, peak/RMS current in the primary, and maximum-allowable power dissipation for the package (without exceeding the junction temperature limits). Voltage at the MOSFET drain is the sum of the input voltage, the secondary voltage reflected through the transformer turns ratio, and the leakage-inductance spike. (Figure 2 illustrates the relationship between drain voltage and primary current.) The MOSFET’s absolute maximum VDS rating must be higher than the worst-case drain voltage (maximum input voltage and output load). The forward-bias drops of secondary- and biasrectifier diodes are assumed to be 0.2V and 0.7V, respectively. Refer to the diode manufacturer’s data sheet to verify these numbers. Again, round off the number of turns for secondary and bias windings to the closest integers. 6) The core’s AL value depends on the air gap in the magnetic path length. Most of the energy is stored in the air gap during the MOSFET’s on time. To reduce electromagnetic radiation, insert the air gap in the center leg of the core. VDS (MAX ) = VIN ( MAX ) + 8 NP × (VOUT + VD ) + VSPIKE ...(V) NS RCD snubber-network design To avoid an excessive VDS requirement for the MOSFET, we recommend using an RCD snubber across the primary to suppress the spike caused by energy in the leakage inductance. The snubber dissipates energy that would otherwise dissipate in the MOSFET itself. The snubber capacitor’s value should be high enough to absorb the leakage-inductance energy without allowing the MOSFET drain voltage to rise beyond an acceptable limit. Use the following equation to calculate this capacitance: DRAIN VOLTAGE 50V/div PRIMARY CURRENT 0.65A/div C= where: LL = leakage inductance, which should be specified by the transformer vendor. (Values of 1µH to 3µH are common for the transformer under discussion.) VSPIKE = spike voltage, typically 30V to 50V. IPK = peak primary current, which in this case (for a worst-case spike) equals the current-limit threshold divided by RSENSE. 1µs/div Figure 2. This scope photo shows Figure 1’s circuit operating at VIN = 36V, VOUT = 5V, and IOUT = 1A. The switching MOSFET (Q1) exhibits drain voltage (upper trace) at 50V/div, and primary current (lower trace) at 0.65A/div. The diode must be a fast-switching type, with reverseblocking voltage at least equal to the VDS(MAX) rating of the MOSFET. The resistor is selected for an RC time constant 2 to 3 times the switching period. Power dissipation in the resistor is the sum of the leakage-inductance energy times frequency, plus the power loss caused by DC bias across the capacitor. The following equation lets you estimate power dissipation in the resistor: 1 PR = ( × CSNUBBER × VSPIKE 2 ×) ƒS ( MAX) 2 N [(VO + VD) × P ]2 × (1 − DMIN ) NS + RSNUBBER where: D MIN = minimum duty cycle = D MAX /2. (A 50% derating is recommended for chip resistors.) A lower VDS Absolute Maximum Rating means a shorter channel, lower RDS(ON), lower gate charge, and a smaller package. Thus, it is advisable to keep VDS(MAX) low by choosing a lower NP/NS ratio and keeping the leakageinductance spike under control. A resistor/capacitor/diode (RCD) snubber network can suppress such spikes. The RMS current in the primary can be used to calculate DC loss in the MOSFET. Switching loss in the MOSFET depends on the operating frequency, the total gate charge, and the cross-conduction loss during turn-off. Cross-conduction loss during turn-on is negligible, because in discontinuous-conduction mode the primary current starts from zero. To avoid damage during poweron and during fault conditions, it may be necessary to derate the MOSFET. Use the following equation to estimate the MOSFET’s power dissipation: Input filter design The input filter reduces the amplitude of AC components in the converter’s current pulses, thereby making the converter appear to the source as a DC load. Design parameters for this filter are the RMS ripple-current capability, input voltage, and the allowable level for AC components reflected back to the source. PMOS = (1.4 × RDS (ON ) × IPRMS) + (Q G × VCC × ƒS (MAX ) ) + + (VIN ( MAX ) × IPK × toff × ƒS (MAX ) ) 4 (CDS × VDS 2 × ƒS (MAX ) ) 2 L L × IPK 2 ...( F ) VSPIKE 2 ...( W ) Because discontinuous-mode flyback converters draw peak triangular currents through the capacitor ESR during each cycle, large aluminum electrolytic capacitors are needed for their low ESR and high ripple-current ratings. Unfortunately for a distributed power system, the input-filter capacitances of parallel converters add where: QG = total gate charge of the MOSFET in coulombs; VCC = bias voltage in volts; tOFF = turn-off time in seconds; CDS = drain-to-source capacitance in farads. 9 together and may produce an unacceptable inrush current at startup. As an alternative, you can use ceramic capacitors to achieve low ESR and a high ripple-current rating while keeping the total capacitance low. secondary replenishes those lost charges by discharging the core during the off-cycle, and simultaneously supplies the load current. Again, output ripple is the sum of the voltage drop due to the output capacitor’s ESR (∆VESR), and the charge loss (∆VC) during the switch on-time. High switching frequency in the MAX5021 reduces the capacitance requirement. Use low-ESR tantalum capacitors for their favorable combination of capacitance and ESR, and use the following equations to calculate the capacitance and ESR: 4 × (1 − DOFF ) × IO × 10 −6 C OUT = ...( F ) ∆VC And, ∆VESR ESR O = ...(Ω) IO where: DOFF is the discharge duty cycle, calculated using the following equation: The input peak-to-peak ripple voltage is a combination of the voltage drop due to capacitor ESR (∆VESR) and the loss of charge from the capacitor (∆VC). For lowESR ceramic capacitors, use a 3:1 contribution from charge loss and ESR ripple respectively, and use the following equation to estimate capacitance and ESR for the capacitor: 4 × POUT × 10 −6 CIN = ...( F ) η × VIN ( MIN ) × ∆VC And, ESRIN = ∆VESR ....(Ω) IPK Choose a capacitor that can handle the necessary RMS ripple without increasing its internal temperature (Figure 3). Use the following equation to estimate RMS ripple in the input capacitor: ICRMS = DOFF = 1.63 × POUT ...( A ) η × VIN ( MIN ) IO × LS 2 × 10 −6 × (VO + VD ) Additional noise spikes ride on the output ripple, caused by the di/dt of secondary current flowing through the output capacitor’s ESL. A small LC filter can suppress these low-energy spikes, and it helps in attenuating switching-frequency ripple as well. To minimize the filter’s effect on phase loss and to ensure that it does not interfere with compensation, you should design its corner frequency more than one decade away from the estimated closed-loop bandwidth. Figure 4 shows the peak-to-peak ripple waveforms with and without the LC filter. Use a low-ESR ceramic capacitor of 1µF to 10µF, and calculate the inductance using the following equation: Output filter design The output capacitance required depends on the level of peak-to-peak ripple acceptable at the load end. The output capacitor for flyback converters supports load current during the switch on-time. The transformer L≤ DRAIN VOLTAGE 50V/div 1 ...(H) 4 × 10 3 × ƒC 2 × C where: fC = estimated closed-loop bandwidth. Power loss consideration INPUTVOLTAGE RIPPLE 500mV/div High-frequency switching converters can be very lossy, since switching loss simply adds to the DC loss. Careful component selection is necessary to keep switching loss at a minimum. The MAX5021 is designed to operate at a sufficiently high frequency to reduce the size of passive components while minimizing switching losses. The MAX5021’s low startup current and low quiescent operating current minimize power loss in the control circuitry. To reduce switching loss even further and achieve higher converter efficiency, use a MOSFET with 1µs/div Figure 3. This scope photo shows Figure 1’s circuit operating at VIN = 72V, VOUT = 5V, and IOUT = 1A. The circuit exhibits input-voltage ripple at 500mV/div (lower trace) and drain voltage at 50V/div (upper trace). 10 tF = turn-off time in seconds; VD = drain voltage at turn-off in volts; fSW = switching frequency (262kHz); IPK = primary peak current in amperes. OUTPUT RIPPLE WITHOUT LC FILTER 200mV/div Use a Schottky diode in the secondary to achieve low VDS and low reverse-recovery loss. Use the following equation to calculate DC loss in the secondary diode while neglecting reverse-recovery loss due to switching: OUTPUT RIPPLE WITH LC FILTER 100mV/div PD = VFB × IO where: VFB = forward drop for the secondary diode at ISPK/2, in volts. 2µs/div You can reduce the transformer-leakage inductance between primary and secondary by sandwiching the secondary between two halves of the primary. Use a multifilar winding structure to reduce skin-effect loss. Figure 4. This scope photo shows Figure 1’s circuit operating at VIN = 72V, VOUT = 5V, and IOUT = 1A. The circuit has less output-voltage ripple with an LC filter (lower trace at 100mV/div) than without (upper trace at 200mV/div). Frequency compensation The absence of a right-half-plane (RHP) zero in the discontinuous flyback converter simplifies the closedloop frequency compensation to a single pole-zero pair. No bandwidth limit arises from the location of the RHP zero. The loop is closed through the shunt regulator, optocoupler, and PWM comparator internal to the MAX5021. The location of the error amplifier’s pole and zero is determined from the existing PWM gain, the output-filter pole, and the ESR zero frequency. Use the following equations to calculate the current-mode converter’s PWM gain, the output-capacitor filter pole, and the output capacitor’s ESR zero: low gate charge and low gate-to-drain capacitance, and balance the MOSFET’s DC and switching-power losses. See graph of Converter Efficiency vs. Output Current (Figure 5), and use the following equation to calculate DC and switching losses in the MOSFET: PMOS = (1.4 R DS (ON ) × IPRMS) + (Q G × ƒSW × VCC ) + ( IPK × VD 6× tF × ƒSW ) where: QG = total gate charge for the MOSFET in nanocoulombs; VCC = voltage at VCC (pin 4 of MAX5021); A PWM = EFFICIENCY vs. OUTPUT CURRENT RL × LP × ƒSW × η 6.2 × 10 3 2 × × CTR RS RLED 85 48VIN 80 EFFICIENCY (%) 75 A PWM = 36VIN 70 5 × 61 × 10 −6 × 262 × 10 3 × 0.8 6.2 × 10 3 2 × ×1 0.65 510 65 72VIN 60 APWM = 105 55 50 Capacitor filter pole (fP): 45 40 0 0.2 0.4 0.6 0.8 1.0 ƒP = 1.2 IOUT (A) ƒP = Figure 5. This graph demonstrates Efficiency vs. Output Current curves for the circuit in Figure 1. 1 ...(Hz) 2 × π × RL × CO 1 ...(Hz) 2 × π × 5 × 330 × 10 −6 ƒP = 96...(Hz) 11 response time, which may also cause an output overshoot during turn-on. Figure 8 depicts the result of an optimally compensated loop. Capacitor ESR zero (fz): 1 ƒz = ...(Hz) 2 × π × CO × ESR 1 ....(Hz) 2 × π × 330 × 10 −6 × 0.06 CLOSED-LOOP RESPONSE ƒz = 8038....(Hz) 80 where: RL = load resistance; CTR = current-transfer ratio of optocoupler; RS = current-sense resistor in the primary path; and CO = output-filter capacitor. 180 135 60 90 PHASE GAIN (dB) 40 45 0 20 -45 0 Total loop gain equals the PWM gain (APWM) times the gain of the voltage divider and the error amplifier (shunt regulator). The available worst-case phase margin (PM) occurs at full load. -90 GAIN -20 PHASE (DEGREES) ƒz = -135 -180 -40 100 1k 10k 100k FREQUENCY (Hz) The response of the combined-error amplifier, optocoupler, and PWM is too complicated to estimate analytically. You should therefore use the existing compensation network to plot a Bode diagram of the closed-loop transfer function from control to output. Then place the zero and pole at appropriate locations for maximum “phase bump” at the crossover frequency. To maintain a gain slope of -1 to well beyond the crossover frequency, place the error-amplifier pole at the ESR zero location. Use the following equations to calculate the zero (fZE) and poles (fPE) of the error amplifier: 1 ƒZE = ...(Hz) 2 × π × Rƒ × Cƒ ƒZE = Figure 6. This Bode plot illustrates stability for Figure 1’s circuit operating with component values as shown. OUTPUT CURRENT 1A/div 1 ...(Hz) 2 × π × 47 × 10 3 × 10 × 10 −9 OUTPUT VOLTAGE 100mV/div ƒZE = 338...(Hz) ƒPE = ƒPE = 1 ....(Hz) 2 × π × Rƒ × Cƒƒ 50µs/div 1 ....(Hz) 2 × π × 47 × 10 3 × 220 × 10 −12 Figure 7. The transient response for Figure 1’s circuit: IOUT at 1A/div (lower trace), and VOUT at 100mV/div (upper trace). ƒPE = 15, 392....(Hz) Optimization on the board produces a closed-loop bandwidth of 8kHz with 44° of phase margin. The Bode plot of Figure 6 is based on the circuit of Figure 1, with values as shown for the compensation components. Layout and safety guidelines High-frequency switching converters produce current and voltage waveforms with high slew rates. To minimize voltage spikes and electromagnetic radiation, you should minimize inductance in the current loops and PC traces. Component placement is critical in keeping the high-frequency traces short. Follow the steps below for good layout: We can verify the load-transient response for a smalldeviation, fast-settling perturbation in the output voltage by switching the load from 100mA to 1A in 20µs (Figure 7). An overcompensated converter increases the 12 Step 1. Area product (AP): OUTPUT VOLTAGE 2V/div AP ≥ (2 × POUT ) × 10 −12 ...( m 4 ) η × BMAX AP ≥ (2 × 5.61) × 10 −12 ...( m 4 ) 0.8 × 0.12 AP ≥ 117 × 10 −12....( m 4 ) INPUT VOLTAGE 20V/div Select EPC13 (TDK Part Number – PC44EPC13-Z) Core Ap and Ae: A P = 145 × 10 −12....( m 4 ) 2ms/div A e = 12.5 × 10 −6....( m 2 ) Figure 8. These startup waveforms appear in Figure 1’s circuit with an optimally compensated loop. The circuit has a 48V input voltage at 20V/div (lower trace), and a 5V output voltage with 1A load at 2V/div (upper trace). Step 2. Secondary inductance (LS): • Minimize the loop formed by the input capacitor positive terminal, transformer primary, MOSFET switch, current-sense resistor, and input-capacitor negative terminal. LS ≤ 430 × 10 −9 × (VO + VD ) ...(H) I OUT S≤ 430 × 10 −9 × (5.1 + 0.4) ...( ) 1.1 • Keep the gate-drive trace from the MAX5021 to the switching MOSFET short. L S ≤ 2.15 × 10 −6...(H) • Place the RCD snubber components close to the input capacitor and MOSFET switch. Step 3. Primary inductance (LP): • Place the ceramic capacitors connected to the MAX5021 VCC, VIN, and CS pins close to the IC. LP = • Minimize the loop formed by the transformer secondary, secondary diode, and output capacitor. • For effective heatsinking on the PC board, connect a large copper area to the MOSFET drain, transformer secondary, and secondary diode. 0.4 × 10 −6 × VIN ( MIN )2 × η ...(H) POUT P = 0.4 × 10 −6 × 34 2 × 0.8 ...( ) 5.6 L P = 65 × 10 −6....(H) The type of circuit (SELV, TNV-1, TNV-2, or TNV-3) and its degree of pollution (determined by the circuit surroundings) determine the requirements for clearance and creepage between the primary and secondary circuits. For the minimum clearance and creepage distances between different circuit components, contact your safety engineer or refer to Underwriters Laboratory standard UL60950. Step 4. Primary turns (NP): NP = P= Appendix—Transformer Design Given the specifications VIN = 36V to 72V, VOUT = 5.1V, and IOUT = 1.1A, proceed as follows: 2.1 × 10 −6 × VIN ( MIN ) A e × BMAX 2.1 × 10 −6 × 36 12.5 × 10 −6 × 0.12 P = 47.6 Round off the primary turns, NP = 48. 13 Step 5. Secondary- and bias-winding turns (NS and Nbias): NS = NP × S LS LP = 8.7 Round off the secondary turns, NS = 9: Nbias = 11.7 × NS VOUT + 0.2 Nbias = 19.8 Round off the bias-winding turns, Nbias = 20. Step 6. Value of the core: AL = LP nH × 10 9... 2 NP 2 AL = 26... nH 2 Step 7. Primary and secondary RMS currents (IPRMS and ISRMS): IPRMS = IPRMS = 1.63 × POUT ....( A ) η × VIN MIN 1.63 × 5.1 × 1.1 ....(A ) 0.8 × 34 IPRMS = 0.33....( A ) ISRMS = 1.63 × IOUT....( A ) ISRMS = 1.79....( A ) 14 Small, high-voltage boost converters reduced, allowing the use of the MAX1605, which has a 28V internal MOSFET. The complete layout (smaller than an 8-pin DIP) fits on a 6mm x 8.5mm double-sided board (Figure 2). Theory of operation The biasing of avalanche photodiodes (APDs), piezoelectric transducers (PZTs), vacuum fluorescent displays (VFDs), and microelectromechanical systems (MEMS) require high-voltage power supplies. This article presents three topologies (Figures 1a, 1b, and 1c) for generating a high output voltage from a low input voltage. The advantages and disadvantages of each are discussed with focus given to power density and circuit size. The end of the article presents experimental data to contrast transformer-based and inductor-based solutions. The high-voltage bias required in many APD applications (75V) is derived from a 3V supply. That requirement presents the following challenges: Figure 2. This 6mm x 8.5mm DC-DC converter converts 2.5V to 75V using the MAX1605. The front and back layout of the circuit is shown. • High-voltage MOSFETs generally do not operate with a low 3V gate drive. • The larger drain-source capacitance of high-voltage MOSFETs requires energy in the inductor to slew the drain to the output voltage. The resulting losses are as large as 1/2 fswitch x CDSVOUT2. Standard boost and flyback DC-DC converters can be merged to form the hybrid topology of Figure 1c. The resulting merged topology stacks secondary-winding flyback voltage on top of the input voltage and the primary-winding flyback voltage (a standard flyback converter only takes advantage of flyback voltage produced at the secondary side). Compared with a standard boost converter, this topology produces higher output voltages from a lower voltage MOSFET by limiting the voltage seen at LX. • High-voltage MOSFETs are larger and more expensive than their lower voltage counterparts. High-voltage power MOSFETs are seldom found within switchingcontroller ICs. • Extreme duty cycles impose inefficiently small off-times or low switching frequencies. Lower switching frequency causes higher ripple and requires larger magnetics. A transformer provides the following advantages: • Higher attainable output voltages; • Lower operating duty cycle; • Lower voltage on the MOSFET. The circuit of Figure 1c solves these challenges by using an autotransformer. The peak voltage on the MOSFET is Figure 1a Figure 1b Figure 1c NODE 1 VIN VOUT ILIM VCC LX BOOST FB CONVERTER VOUT VIN ILIM VCC VIN 2.5V TO 5.5V D1 T1 NS NP LX FLYBACK CONVERTER FB GND 6-PIN SOT23 VOUT = 75V AT MORE THAN 6mA ILIM VCC CONTROL LOGIC LX MAX1605 GND N COUT FB A SMALL 6-PIN SOT23 WITH INTERNAL FET CONVERTS 2.5V TO 130V OR MORE THAN 6mA AT 75V. Figures 1a, 1b, and 1c. These high-voltage DC-DC converters in three topologies are used to create high output voltage from low input voltage. 15 The following advantages also accrue when operating the transformer in discontinuous mode, with a constant peak current in the MOSFET: IPK • Higher switching frequency produces lower output ripple • Higher frequency ripple • Smaller magnetics IL 0 T DxT STEADY-STATE CURRENT RIPPLE FOR VIN = 2.5V AND VOUT = 50V Figure 3. This analysis of the inductor current for the circuit of Figure 1a can be used to determine its duty cycle. Standard boost The circuit of Figure 1b could be made equivalent to the circuit of Figure 1a by connecting the left side of the transformer’s secondary winding to VIN and setting the turns ratio to 1. The secondary-side diode can be reflected to the primary side, making the relationship between a flyback converter and a boost converter easier to perceive. The standard boost converter is shown in Figure 1a. When the MOSFET turns on, the inductor current ramps up. When the MOSFET turns off, LX flies up to VOUT + VD, and the inductor current ramps down. Intuitively, if the inductor spends 1/nth of its time delivering energy to the output, the output voltage (VOUT) is n times the input voltage (V IN ), thus the following equation can be generated: Turns ratios larger than 1:1 provide leverage by allowing higher output voltage with less extreme duty cycles. Alternatively, node 1 of the transformer can be connected to any power supply, enabling leverage with respect to that supply. Because LX flies up during the off-cycle, an additional voltage step can be obtained by connecting node 1 to LX, as shown in Figure 1c. That connection also helps catch some of the leakage energy that would otherwise be dumped from the transformer’s primary side to the MOSFET, producing short, high-voltage spikes at the MOSFET’s drain. If the voltage spikes are higher than the MOSFET’s voltage tolerance, a snubber circuit will be necessary to dissipate the leakage energy. VOUT 1 = VIN 1 − D where D is the duty cycle. A more analytical proof can be found by using Figure 3. The key to this proof lies in steady-state operation, for which the current must ramp down the same amount that it ramps up: ∆I UP = ∆I DOWN Thus, the final inductor current equals the initial inductor current. ∆IDOWN = LX is shorted to ground in Figure 1b, allowing the primary-side current to ramp up as for an inductor. No current flows through the secondary side of the transformer and the diode is reverse-biased because VIN V tON = IN D × T LBST LBST VOUT − VIN V − VIN tOFF = OUT (1 − D) × T LBST LBST VPRIMARY = − VIN VSECONDARY = NS / NP × VPRIMARY Because they are equal, Primary-side current must cease when the switch at LX turns off, but the N x I product must remain constant: − VIN VIN V (1 − D) × T D × T = OUT LBST LBST IP_ initial × NP + IS_ initial × NS = IP_ final × NP + IS_ final × NS where subscript “P” indicates primary side, subscript “S” indicates secondary side, “initial” indicates current at the moment before the MOSFET is switched off, and “final” indicates current at the moment after the MOSFET is switched off. VIN × D = VOUT − VIN × (1 − D) VOUT 1 = VIN (1 − D) dI = VOUT - VIN dt LBST IOUTMAX The MAX1605 and many other boost converters can be used in this topology. Maximum output voltage is limited by the transformer turns ratio, the transformer and diode voltage ratings, the MOSFET’s voltage rating and drain capacitance, and the diode’s reverse-recovery time. ∆I UP = IINMAX dI = VIN dt LBST and D = 1− VIN VOUT 16 Because IS_initial = IP_final = 0, I S_ final = ISAT = IPK / N NP IP_ initial NS LTOT = LBST × N LP = LTOT / N 2 = LBST / N The circuit of Figure 1c is similar, except that IP_final = IS_final, thus NP I S_ final = I P_ initial NP + NS For the steady state, it is clear from Figure 4 that: ∆IUP = IPK To simplify, the turns ratio ‘N’ is expressed as: N= ∆IUP = IL ∆IDOWN = so dI VOUT - VIN = LTOT dt VOUT N × D = +1 VIN 1− D and D= VOUT − VIN VIN ( N − 1) + VOUT Figures 3 and 4 are both drawn to scale and have the same off-time (set to some optimal minimum). The shaded regions in Figures 3 and 4 represent energy delivered to the load, and the energy per pulse is proportional to the area of those regions. That energy can also be calculated from the expression 1/2 L x I2 (note that L in Figure 4 is N times larger, and I is N times smaller). Because the circuit of Figure 1c delivers less energy per pulse, the ripple is N times smaller. Thus, a transformer not only leverages the output voltage up; it also leverages the output ripple down. IINMAX IOUTMAX STEADY-STATE CURRENT RIPPLE FOR VIN = 2.5V and VOUT = 50V The topology of Figure 1c delivers less energy per pulse, but compensates by delivering more pulses, as clearly indicated in Figure 4. Figure 1c requires an N times larger inductance, but the saturation current can be N times smaller because the primary and secondary side see only IPK/N as much current simultaneously. With an ISAT smaller by a factor of N and an inductance N times larger, the transformer’s energy-storage capability may also be N times smaller. Transformer size is a function of its energystorage capability, so in theory you can use a transformer that is physically smaller by a factor of N. (In practice, the attainable size is determined by market limitations.) Figure 4. This analysis of the primary-side transformer current for the circuit of Figure 1c can be used to determine its duty cycle. The primary-side inductance is: LP = VOUT − VIN V − VIN tOFF = OUT (1 − D) × T LTOT LBST × N Solving for VOUT /VIN yields: IPK IPK N VIN VIN tON = D×T LP LBST / N VOUT − VIN VIN (1 − D) × T = D×T LBST × N LBST × N / N tOFF = (1 - D) x T MOSFET SWITCHES t = D X T ON OFF IPK ∆IUP = N N and Figure 4 shows the primary-side current waveform for Figure 1c. For step-up converters whose output is more than twice the input voltage, off-time has a greater effect on the efficiency than on-time. Assume (for a comparable boost converter) that off-time has been minimized by minimizing inductance (LBST), which also minimizes component size to the point that further reduction would lead to undesired efficiency loss. Then, select the Figure 4 transformer’s total inductance to be N times as large. Because the primary-side current ramps down from IPK/N instead of IPK, the primary inductance must be N times as large to maintain the same off-time. t ∆IDOWN = where ∆IUP is the upward step in the primary-side current and ∆IDOWN is the downward step. ∆IUP and ∆IDOWN can be calculated as follows: NP + NS NP because the secondary side of Figure 1c never acts independently. Though unconventional, this definition for N is more appropriate for Figure 1c. 2 dI = VIN x N LTOT dt and LTOT N2 where LTOT is the total inductance of the autotransformer since LP is N2 smaller than LTOT, and LTOT is N times larger than LBST, LP is LBST/N. As a result, the primary side ramps faster than a simple boost converter. 17 Output ripple Efficiency considerations For discontinuous conduction, either converter’s output ripple can be calculated by equating energy change in the inductor or transformer with energy change in the output capacitor during the off-cycle. Because the inductor/transformer has zero energy at the end of the cycle, no-load ripple can be calculated as: There are three main efficiency losses to consider in the transformer topology. Transformer/inductor DC resistance combined with switch resistance produces losses proportional to the square of the peak current. Transformer-leakage inductance produces loss because transformer energy is not completely coupled to the output. When the diode is quickly and heavily reversebiased (when the MOSFET turns on), any delay in the diode (the reverse-recovery time, tRR) can also cause significant loss. 1 2 1 2 LI 2 = 12 COUTVfinal 2 − 12 COUTVinitial2 LI 2 = 12 COUT(Vfinal − Vinitial ) × (Vfinal + Vinitial ) 1 2 LI 2 = COUT ∆VOUT × VOUT ∆VOUT = 1 2 The percent efficiency loss due to DC resistance in the switch and in the primary side of the transformer is independent of load, and can be approximated as: LI 2 COUT VOUT ER _ LOSS ×100% ER _ LOSS + Edelivered For the boost converter L = LBST and I = IPK. For the circuit of Figure 1c, L = LBST x N and I = IPK/N, so: ∆VOUTA = ∆VOUT C = 1 2 1 2 where ER_LOSS is the energy loss due to resistance per pulse, and Edelivered is the energy delivered per pulse. By taking the integral of the primary-side resistive power dissipation, the resistive efficiency loss for large duty cycles can be approximated as: LBST( IPK )2 CVOUT IPK 2 ) N = ∆VOUTA CVOUT N N × LBST ( 1I R 3 PK 1 I R + 1V 3 PK 2 IN where ∆VOUTA is the output ripple of the boost configuration, and ∆VOUTC is the output ripple for the Figure 1c circuit. Ripple in Figure 1c is 1/Nth as large for the boost configuration and the switching frequency is N times higher. where D is the duty cycle expressed as a percentage, and R is the sum of the switch resistance and the primaryside resistance. For operation in discontinuous mode, the same equation applies for the circuit of Figure 1a or 1c. The efficiency loss due to leakage inductance can be approximated as: L leakage ×100% L leakage + L primary Figure 5 offers a comparison of ripple for the circuits of Figures 1a and 1c, when both circuits are designed for the same off-time. Because the duty cycle is normalized in the transformer circuit (made closer to 50%), the controller can operate at a frequency N times higher for the same off-time. ESR RIPPLE × 100% where Lleakage is the total leakage inductance seen at the primary side. Transformers with higher turns ratios provide larger leakage inductance, higher frequency, and deliver lower energy per pulse, so the source of inefficiency becomes more significant. BOOST WITH TRANSFORMER LEVERAGE CAPACITIVE RIPPLE Transformer selection Since the selection of off-the-shelf transformers is much narrower than that of equivalent inductors, transformers generally cost more than inductors of equivalent energy and energy density. The customer base for transformers is smaller, yet the set of possible transformer configurations is much larger than that of corresponding inductor configurations. As a result, magnetic designs based on custom transformers are often necessary. STANDARD BOOST Figure 5. This illustration contrasts the ripple produced by the circuit of Figure 1a vs. the circuit of Figure 1c assuming both are optimized for a minimum acceptable off-time. 18 Figure 7 shows the MAX1605 maximum output current (the measured typical, for which the controller falls out of regulation by 5%) as a function of output voltage and input voltage. When specifying an autotransformer, consider an equivalent inductor. The following inductor, for example, is available from Toko: D32FU 680µH, 74mA, 20Ω, 3.5mm x 3.5mm x 2.2mm. It is reasonable to ask for an autotransformer whose end-to-end characteristics are similar. For such a transformer with a 1:9 turns ratio, the primary-side rating would be 6.8µH, 740mA, and 2Ω. That inductance rating is based on a value of N2 (where N is the total number of turns divided by the number of primary-side turns). For a 1:9 turns ratio there must be some multiple of 10 turns total. N = 10 must be used for the previous calculation. The saturation current is inversely proportional to N and resistance is proportional to N. MAXIMUM LOAD vs. OUTPU 10 VIN = 5V MAXIMUM LOAD (mA) 8 6 VIN = 3.3V 4 2 Occasionally, thermal limitations do not allow the maximum current rating to scale by N. Also, a limited product selection may bar you from that ideal starting point. This analysis provides a starting point and a decent edge when discussing possibilities with a custom transformer vendor. When wound as an autotransformer, an equivalent magnetic component should require less space (a smaller wiring cavity) because the lower currents allow thinner wire on the secondary side. (Extra manufacturing costs usually prohibit this approach, however.) VIN = 2.5V 0 30 40 50 60 70 80 90 100 OUTPUT VOLTAGE (V) Figure 7. This Maximum Load vs. Output Voltage graph illustrates the maximum load deliverable by the circuit of Figure 6. Output ripple for the circuit of Figure 1c can be calculated as: 1L ×I 2 P PK VRIPPLE = 2 COUT × VOUT Application where LP is the primary-side inductance, IPK is the peak primary-side current (500mA), C OUT is the output capacitance (0.47µF), and VOUT is the output voltage. For a 75V output, the ripple is 16mVP-P. The low inductance that produces such a low ripple is typically not efficient in a straight boost configuration like Figure 1a. The circuit of Figure 6 produces an APD bias of 75V. Because the transformer reduces voltage stress on the switch, you can use a small 6-pin SOT23 device such as the MAX1605. The 28V, 500mA MOSFET in that IC is more than adequate since it only sees peak voltages of VIN + (VOUT - VIN) / N = 17V. With a higher turns ratio, the circuit can handle higher voltages. SUMIDA CMD4D13 4365-T020, NP:NS IS 1:5, LP = 4.53µH IP_SAT = 562mA, RP = 0.852Ω SIZE IS 4.1mm x 4.3mm x 1.45mm VIN 2.5V TO 5.5V 0.47µF CENTRAL SEMICONDUCTOR CMOD4448 BK SOD-523 D1 T1 NP Even 16mV P-P ripple is not small enough for many applications. To bias an APD, high ripple is unacceptable because it couples directly into the signal. Such applications can use an RC or LC filter following the power supply, but the resistor in an RC filter produces a loadregulation error. (Typical load currents are small, but the ripple filter may require large resistors.) NS SHDN LIM VCC CONTROL LOGIC LX MAX1605 GND N 750kΩ FB 13.7kΩ At 100V, high-capacitance values require board space, so the filter is composed largely of resistance. For the same cutoff frequency (using the same resistor and capacitor), you can reduce the load-regulation error by a factor of β using the circuit of Figure 8. Although a fixed VBE drop is introduced instead, that approach dramatically reduces the dependence of VOUT on load. To achieve greater ripple reduction for the same level of load regulation, a β-times larger filter resistor can be used. VOUT = 75V AT MORE THAN 6mA 470pF COUT 0.47µF 100V CERAMIC CAPACITOR IN 1210 CASE (TDK C322X7R2A474K) Figure 6. This circuit, whose layout is shown in Figure 2, is used to produce 75V from 2.5V. 19 components were used in conjunction with the MAX668 Evaluation Kit: OUT RFILTER • Inductor: Coilcraft DO1813P-472HC 4.7µH, 2.6A 0.054Ω inductor • Ultra-fast diode: ES1D 200V 15ns reverse-recovery time • MOSFET: IRF640NS 200V 0.15Ω QG = 67nC, COSS = 185pF, and provides over 2A with 5.5V gate drive • Sense resistor: 50mΩ sense resistor CFILTER FILTERED OUT Another resistor connected between the FB terminal and a voltage source allows that source to adjust the output voltage by sinking or sourcing current to the FB terminal. You can then adjust the output voltage to 150V and the input voltage to 6V. Figure 8. A filter further reduces ripple. Experimental comparison: inductor and transformer approaches For a fair comparison of inductors versus transformers in a high-voltage converter, a switching converter with the following features was selected: • • • • For the inductor-based solution, the maximum load current is 18mA at 150V (2.7W). Peak efficiency (65%) occurs at maximum load and the quiescent (no-load) current is 91mA with a 6V supply. The quiescent-current loss in the inductor circuit is due to the diode’s reverse-recovery time and the MOSFET’s drain capacitance. Those effects are illustrated in Figure 10. External MOSFETs Adjustable switching frequency Adjustable current limit Evaluation kit available The transformer-based approach (Figure 11) was implemented by exchanging the inductor for the following transformer, using the topology of Figure 1c: The MAX668 current-mode controller fulfills these criteria while eliminating the need for a feedforward capacitor. The circuit of Figure 9 allows you to compare performance by swapping the transformer for an inductor and by swapping MOSFETs. Sumida CMD-8LN 6313-T036, LP = 5.6µH, IP = 2.3A, NP:NS = 1:9, RP = 0.5Ω The MAX668 includes a MOSFET driver that can efficiently drive the 48nC gate charge of an IRF7401 MOSFET. With the following components, it forms a 150V inductor-based boost converter. The following CEE98 6343-T361, NP:NS is 1:9, LP = 2.4µH, IP_SAT = 7A, RP = 0.055Ω SIZE IS 8.2mm x 9.5mm x 6.0mm D1 NP SYNC/ SHDN VCC EXT CS MAX668 FREQ R4 121kΩ ES1D ULTRA-FAST, 200V, 15ns DIODE T1 VIN = 5V 68µF LX Using a transformer with a 1:9 turns ratio requires only a 22V MOSFET, but an actual application would use a 30V MOSFET (instead of a 200V MOSFET) for the transformer circuit. Yet, the efficiency is 77% while delivering 25.5mA at 150V (3.8W). Peak efficiency is 88% at 15mA, and the no-load supply current is only 1.8mA total. NS Using the 200V MOSFET with a transformer allows the possibility of much higher voltage. A 200V MOSFET and 1:9 transformer can approach output voltages as high as 2kV in theory, but in practice the transformer windings cannot sustain such high voltage. A greater problem, however, is obtaining >1kV diodes with fast reverserecovery times. For slow reverse-recovery times, the switching speed must be reduced. VOUT R2 10MΩ N1 IRF7811W R1 50mΩ COUT FOUR 0.1µF 250V CERAMIC CAPACITORS PGND GND FB VADJ R3 75kΩ 220pF Substituting a 400V CMR1U-04 diode from Central Semiconductor (50ns t RR ) for the ES1D diode and changing the output capacitors allows the circuit to produce outputs as high as 400V. The ES1D diode cannot reliably produce outputs greater than 346V, because its anode goes to -9 x VIN when the MOSFET Figure 9. This circuit can be used to deliver higher power and higher output voltage. 20 ZOOM OF NO-LOAD SWITCHING WAVEFORM NO-LOAD SWITCHING WAVEFORM FOR AN INDUCTOR SOLUTION INDUCTOR CURRENT 500mA/div CHARGE INTO OUTPUT 0 CHARGE OUT OF OUTPUT 0.8A REVERSE-INDUCTOR CURRENT INDUCTOR CURRENT SLEWS CLX UP VLX 50V/div 0 INDUCTOR CURRENT SLEWS CLX DPWN MOSFET BODY DIODE CLAMPS NEGATIVE CURRENT DIODE IS CONDUCTING MOSFET IS ON 400ns/div 20ns/div Figure 10. This scope photo (left) demonstrates the effect of the ES1D diode’s 15ns reverse-recovery time. The zoom of the waveform (right) reveals that the inductor current actually ramps negative since the diode fails to turn off in time. turns on. Configured for VOUT = 330V, the circuit was able to produce 9.6mA (3.1W) at 60% efficiency and the peak efficiency was 66% at 4mA. MOSFET. The dominant loss is associated with the transformer’s primary-side resistance, which is about 0.5Ω. You can scale this system to provide higher power. For example, another custom transformer specified for IPSAT = 5A and LP = 1.7µH should deliver more than twice as much power. As mentioned earlier, a 30V MOSFET is more logical for the 150V output. The IRF640NS was replaced with a logic-level IRF7811W (30V, 0.012Ω, QG = 18nC, CDSS = 500pF). Resistance drops dramatically (from 0.15Ω to 0.012Ω), but the efficiency improvement is minor. When delivering a maximum load of 25.7mA at 150V, the efficiency is 82.3% (vs. 77%). Peak efficiency at 15.5mA is 88%. Efficiency results are summarized in Figure 12. Thus, besides use of the smaller, cheaper, and more efficient IRF7811W MOSFET, a transformer boost converter can operate with lower input voltages. Transformer leverage can improve power density and efficiency, reduce ripple, and allow the use of smaller, cheaper, and sometimes internal MOSFETS. The cost of applying transformer leverage is mostly due to market limitations. When size and power density are a high priority, consider using transformers. The insignificant improvement in efficiency implies two things. Primary losses are in the transformer (resistive loss and leakage energy), and capacitive losses are in the EFFICIENCY vs. LOAD 100 TRANSFORMER-BASED, 30V MOSFET, 150V OUTPUT 90 ILPRIM 0.5A/div EFFICIENCY (%) 80 O VLXI 20V/div TRANSFORMER-BASED, 200V MOSFET, 150V OUTPUT 70 60 50 40 TRANSFORMER-BASED, 200V MOSFET, 330V OUTPUT 30 O 20 OUTPUT RIPPLE AC-COUPLED 200mV/div 10 INDUCTOR-BASED, 200V MOSFET, 150V OUTPUT 0 0 5 10 15 20 25 LOAD (mA) Figure 12. This Efficiency vs. Load graph compares and contrasts transformer-based, step-up DC-DC converters vs. inductor-based, step-up DC-DC converters. The maximum load, quiescent current, and efficiency are greatly improved using a transformer. Figure 11. The switching waveform shows the transformer-based approach for the MAX668 circuit, a 150V step-up DC-DC converter shown in Figure 9. 21 DESIGN SHOWCASE Compact, inductorless boost circuit regulates white-LED bias current The increasing use of color LCDs in hand-held equipment is creating a need for smaller and cheaper sources of white backlight. Cold-cathode fluorescent lamps (CCFLs) and electro-luminescent (EL) panels have been used in the past, but those circuits are excessively large, expensive, and complex for today’s hand-held, consumer-electronics devices. Fortunately, recent advances in LED technology have produced an LED that emits white light. White LEDs have several advantages over conventional backlights, including small size, low cost, low complexity, and high reliability. 0.22µF 7 CXN 1Ω IN 1µF 3,4 8 CXP OUT IN 1µF 9 WHITE LED 0.22µF U1 FB 10 MAX1759 2 ON OFF SHDN 1 To µC 16Ω PGND 6 The typical forward-bias voltage for white LEDs is about 3.5V ±10%. To obtain white light, you simply forward-bias the device, but a boost circuit is required if the white LED’s forward voltage can be greater than the battery voltage. The conventional approach to this problem—a boost regulator that biases the LEDs through a ballast resistor—has two drawbacks. First, the wide variation of forward voltage in white LEDs causes a large variation in bias current and the resulting light output. Second, the conventional boost converter has a DC path between input and output (even in shutdown) that allows an inactive LED to drain the battery. POK GND 5 Figure 1. Unorthodox connections enable this regulated charge-pump IC to directly regulate the white LED’s bias current. secondary concern in this application and allows the use of a small (0.22µF) output capacitor. Even so, the output ripple is only 400mVP-P. (A similar idea appeared in the 3/5/01 issue of Electronic Design.) Figure 1’s compact circuit overcomes these problems. The regulated buck/boost charge pump in a small µMAX package (U1) has a 100mA outputcurrent capability. Configured as shown, the circuit directly regulates bias current flowing through the white LED. By biasing multiple white LEDs in parallel, it provides good light distribution. The U1’s design eliminates the troublesome input-output path in shutdown, and its SHDN input lets the user turn the backlight on and off. The circuit also includes a power-OK (POK) output for signaling a microprocessor when the backlight is available. Though not necessary in this case, the input RC “π” filter limits voltage ripple reflected back to the input to just 40mVP-P (for VIN = 3.6V). Because outputvoltage ripple is not visible to the eye, it is of 22 DESIGN SHOWCASE Analog switch lowers relay power consumption Table 1. Power dissipated by relay Relays are often used as electrically controlled switches. Unlike transistors, their switch contacts are electrically isolated from the control input. On the other hand, the power dissipation in a relay coil may be unattractive for battery-operated applications. Adding an analog switch lowers the dissipation, allowing the relay to operate at a lower voltage (Figure 1). Voltage (V) 5 (Normal OperatingVoltage) 3.5 (Pickup Voltage) 2.5 (Circuit of Figure 1) Power consumed by the relay coil equals V2/RCOIL. The circuit lowers this dissipation (after actuation) by applying less than the normal operating voltage of 5V. Note that the voltage required to turn a relay on (pickup voltage) is greater than that required to keep it on (dropout voltage). The relay shown has a 3.5V pickup voltage and a 1.5V dropout voltage, yet the circuit allows it to operate from an intermediate supply voltage of 2.5V. Table 1 compares the relay’s power dissipation with fixed-operating voltages across it, and with the Figure 1 circuit in place. SW1 D1 + 2 6 C2 0.15µF U1 MAX4624 63 221 45 250 The values for R2 and C2 are selected to allow C1 to charge almost completely before C2’s voltage reaches the logic threshold of the analog switch. In this case, the time constant C2R2 is about seven times C1(R1 + RON). Larger C2R2 values increase the delay between switch closure and relay activation. D2 4 1 450 Component values for this circuit depend on the relay characteristics and the supply voltage. The value of R1, which protects the analog switch from the initial current surge through C1, should be sufficiently small to allow C1 to charge rapidly, but large enough to prevent the surge current from exceeding the specified peak current for the analog switch. The switch’s peak current (U1) is 400mA, and the peak surge current is IPEAK = (VIN VD1)/(R1 + RON), where RON is the on-resistance of the analog switch (typically 1.2Ω). C1’s value depends on the relay characteristics and on the difference between VIN and the relay’s pickup voltage. Relays that need more turn-on energy require larger C1 values. VIN = 2.5V 5 90 When C2 reaches that threshold, the analog switch connects C1 in series with the 2.5V supply and relay coil. This action turns on the relay by boosting the voltage across its coil to 5V (twice the supply voltage). As C1 discharges through the coil, the coil voltage drops back to 2.5V minus the drop across D1, but the relay remains on because that voltage is above the relay’s dropout voltage (1.5V). By closing SW1, current flows in the relay coil, and C1 and C2 begin to charge. The relay remains inactive because the supply voltage is less than its pickup voltage. The RC time constants are such that C1 charges almost completely before the voltage across C2 reaches the logic threshold of the analog switch. C1 100µF R2 27kΩ Current Total Power (mA) Dissipation (mW) R1 4.7Ω 3 (A similar idea appeared in the 12/20/01 issue of EDN.) Figure 1. An analog switch lowers relay power dissipation. 23

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