SCK Controller Dataout AN

SCK Controller Dataout AN
SCK Controller Data Out for MirrorBit®
Multi I/O SPI Family
Application Note
1. Introduction
Data transfers across a bus occur when the behavior of the master and slave devices resident on the bus
follow a common set of known rules defined for such transfers. In addition to data transfers, rules or protocols
for other operations such as reading and writing of status information or configuration data, etc. may be
defined. The set of all protocols for a specific bus interface form a standard. And when standards are followed
universally but not controlled by a governing body, they are known as de facto standards. In the case of the
SPI bus, a de facto standard exists and is being followed by the group of devices developed by SPI flash
suppliers.
The popularity of the SPI bus continues to increase, fueled by the release of Multi I/O SPI flash memory
devices over the past couple of years. These devices support a superset of commands that add x2, or dual
mode, and x4, or quad mode, data bus width transfers. The Multi I/O SPI devices, performing in dual-mode,
can support up to the maximum read transfer bandwidth of 20 MB/s. And when performing in quad-mode,
they can support up to the maximum read transfer bandwidth of 40 MB/s. These new protocols are being
added to the SPI Bus de facto standard as they become supported by the SPI flash suppliers.
The new protocols for dual mode reads use the SI and the SO signals as two-bit parallel data bus bits. And
the new protocols for quad mode use the SI, SO, HOLD#, and WP# as four-bit parallel data bus bits. Because
the new quad-mode protocols map the HOLD# signal to IO4, a new method of supporting a HOLD function is
now needed. A new method of implementing a HOLD function is defined within this Application Note.
2. HOLD Functionality
The HOLD functionality essentially informs the flash memory that the processor wants to prevent data
overruns by disabling additional data transfers, i.e. holding off the flash.
In single mode and dual mode command execution, the HOLD# signal is left intact and is pulled low (active)
to perform a data transfer Hold to the SPI flash.
However, in quad mode command execution, the HOLD# signal is mapped for use as IO4. It cannot be used
to hold off data transfers. A new method is required to be defined.
3. A New HOLD Function
The SPI flash memory device is always a slave device on the SPI bus. The master is the external circuitry
that drives the SPI interface, and can be either a processor or a set of other logic. The master controls the
transfer of data on the bus. If the HOLD# signal is being used for data transfer in a quad mode command,
another method is to disable the flow of data transfer by preventing the SCK signal from toggling. When the
SCK is held low or high, the SPI flash will stop clocking new data on the IO[3:0] bus. When SCK resumes
toggling, the SPI flash will commence putting valid data onto the data bus, but only if the setup and hold
parameter specifications are met on the SPI bus. Otherwise incorrect data could be transferred. It is also
important to maintain clean SCK and a CS# signals; otherwise this could lead to resetting the read sequence.
While this method of disabling SCK is required to prevent data overruns in quad mode reads, it is optional
when executing a serial or dual command. In other words you could still use the HOLD# signal.
The timing diagrams in Figure 3.1 and Figure 3.2 show two valid examples for holding data output with the
Spansion® SPI SCK signal (Low State or High State).
Publication Number SCK_Controller_Dataout_AN
Revision 01
Issue Date August 19, 2010
A pplication
3.1
Note
Valid Examples for Holding Data Output (Low State and High State)
Figure 3.1 Holding Data Output with SPI SCK Low
10
28 29 30 31 32 33
34 35 36 37 38 39 40 41 42
43 44 45 46 47
297
9
296
8
295
7
294
6
293
5
292
4
291
3
290
2
289
1
288
0
287
CS#
SCK
24 -Bit
Address
Instruction
SI
23 22 21
3
Dummy Byte
2
1
0
7
6
5
4
3
2
1
0
Data Byte 1
High Impedance
SO
7
6
5
4
3
2
Data Byte 32
1
7
0
6
5
4
3
2
Data Byte 33
0
1
7
6
MSB
MSB
5
MSB
SCK Held Low
Figure 3.2 Holding Data Output with SPI SCK High
10
28 29 30 31 32 33
34 35 36 37 38 39 40 41 42
43 44 45 46 47
297
9
296
8
295
7
294
6
293
5
292
4
291
3
290
2
289
1
288
0
287
CS#
SCK
24 -Bit
Address
Instruction
SI
23 22 21
3
Dummy Byte
2
1
0
7
6
5
4
3
2
1
0
Data Byte 1
High Impedance
SO
7
6
5
4
3
MSB
2
Data Byte 32
1
0
7
MSB
6
5
4
3
2
1
Data Byte 33
0
7
6
MSB
SCK Held High
4. Summary
When the HOLD# signal is used in quad-mode Multi I/O SPI Support, the usual method for commanding the
flash device to pause is no longer available. An alternative way to inhibit the transfer of data is to disable the
SCK toggling. When doing so, it is important to maintain adherence to the AC Timing Parameter specification,
especially for Tsetup and THold. Since SCK is an input to the SPI flash device, the disabling of the SCK
signal will usually be handled by the processor, but may be performed through external methods.
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SCK Controller Data Out for MirrorBit® Multi I/O SPI Family
August 19, 2010
5
App l ic atio n
No t e
5. Revision History
Section
Description
Revision 01 (August 19, 2010)
Initial Release
August 19, 2010
SCK Controller Data Out for MirrorBit® Multi I/O SPI Family
3
A pplication
Note
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
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Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2010 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and
combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used
are for informational purposes only and may be trademarks of their respective owners.
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SCK Controller Data Out for MirrorBit® Multi I/O SPI Family
August 19, 2010
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