OPERATION GUIDE UHF Narrow band multi channel transceiver LMD-400-R 438-442/458-462 MHz Operation Guide Version 1.1 (Sep. 2011) CIRCUIT DESIGN, INC., 7557-1 Hotaka, Azumino Nagano 399-8303 JAPAN Tel: + +81-(0)263-82-1024 Fax: + +81-(0)263-82-1016 e-mail: [email protected] http://www.circuitdesign.jp OG_LMD-400-R-AB_v11e OPERATION GUIDE CONTENTS GENERAL DESCRIPTION & FEATURES...........................3 SPECIFICATIONS...............................................................4 PIN DESCRIPTION .............................................................6 BLOCK DIAGRAM...............................................................8 DIMENSIONS......................................................................9 PLL IC CONTROL .............................................................10 PLL IC control ..................................................................10 How to calculate the setting values for the PLL register ........ 11 Method of serial data input to the PLL ................................12 TIMING CHART.................................................................13 PLL FREQUENCY SETTING REFERENCE .....................15 REGULATORY COMPLIANCE INFORMATION................17 CAUTIONS & WARNINGS................................................19 REVISION HISTORY.........................................................20 OG_LMD-400-R-AB_v11e 2 Circuit Design, Inc. OPERATION GUIDE GENERAL DESCRIPTION & FEATURES General Description The LMD-400-R (438-442 MHz & 458-462 MHz) is a synthesized multi channel transceiver module for use under the EN 300 113 Land mobile services. This simple, compact and low power transceiver is designed for embedding in user equipment and suitable for various low power industrial telecontrol and telemetry applications requiring high performance and reliability. All high frequency circuits are enclosed inside a robust housing to provide superior resistance against shock and vibration. Using a TCXO as the reference oscillator circuit of the radio component ensures high frequency stability in the temperature range from -20 to +60 °C. The LMD-400-R is the same size and pin-compatible with Circuit Design’s EN 300220 compliant license-exempt transceiver model STD-302N-R that has been widely used as a standard transceiver for remote control in industrial radio applications. FCC Part 90 certified US version is available in 458 - 462.5 MHz. A custom variant in the 400 MHz band, with 4 MHz switching range is available for volume orders. Features Programmable RF channel with 12.5 kHz channel space 10 mW, GFSK, 4800 bps Low power operation 3- 5.5V, 52mA/TX, 42mA/RX High receiver selectivity & blocking Small size 50 x 30 x 9 mm Excellent mechanical durability, high vibration & shock resistance Wide operation range - 20 to +60 °C EN 300 113 compliant Applications Industrial remote control Telemetry Remote monitoring / Security Data acquisition/ SCADA OG_LMD-400-R-AB_v11e 3 Circuit Design, Inc. OPERATION GUIDE SPECIFICATIONS LMD-400-R 438-442 MHz / 458-462 MHz General characteristics All ratings at 25 +/-10 °C unless otherwise noted Item Applicable standard Communication method Emission class Modulation type Units Operating frequency range MHz Operation temperature range Storage temperature range Aging rate Initial frequency tolerance Dimensions Weight °C °C ppm ppm mm g MIN TYP MAX EN 300 113 Simplex, Half-duplex F1D GFSK 438.000 442.000 458.000 462.000 -20 60 -30 75 -1 1 -1.5 1.5 30 x 50 x 9 mm 25 g Remarks No dew condensation No dew condensation TX freq., RX Lo freq. TX freq., RX Lo freq. Not including antenna Electrical specification <Common> Item Oscillation type Frequency stability (-20 to 60°C) TX/RX switching time Channel step Data rate Max. pulse width Min. pulse width Data polarity PLL reference frequency PLL response Antenna impedance Operating voltage TX consumption current RX consumption current ppm ms kHz bps ms us MHz ms Ω V mA mA MIN TYP MAX PLL controlled VCO -2.5 2.5 15 20 12.5 2400 4800 15 20 200 Positive 21.25 30 60 50 3.0 5.5 52 56 42 46 Remarks Reference frequency at 25 °C DI/DO DO/DI DO/DI DO/DI DO/DI TCXO from PLL setting to LD out Nominal Vcc = 3.0 V Vcc = 3.0 V Transmitter part Item RF output power Deviation DI input level Residual FM noise mW kHz V kHz Spurious emission dBm Adjacent CH power Occupied bandwidth nW kHz OG_LMD-400-R-AB_v11e MIN +/-2.0 0 TYP 10 +/-2.4 MAX +/-2.8 5.5 0.08 -37 -31 200 8.5 4 Remarks Conducted 50 Ω PN9 4800 bps L= GND, H = 3 V- Vcc DI=L, LPF=20 kHz < 1000 MHz, conducted 50 Ω > 1000 MHz, conducted 50 Ω PN9 4800 bps PN9 4800 bps Circuit Design, Inc. OPERATION GUIDE Receiver part Item Receiver type 1st IF frequency 2nd IF frequency Maximum input level *1 BER (0 error/2556 bits) *2 BER (1 % error) Sensitivity 12dB/ SINAD Co-channel rejection dB MIN TYP MAX Double superheterodyne 21.7 450 10 -107 -110 -110 -7 70 70 60 Blocking dB 84 Intermodulation DO output level dB V 65 RSSI rising time ms Spurious response rejection Adjacent CH selectivity *3 Time until valid Data-out *4 st MHz kHz dBm dBm dBm dBm dB *3 dB ms Spurious radiation (1 Lo) dBm RSSI mV 200 130 30 50 50 70 -60 270 200 2.8 50 70 100 120 -57 340 270 Remarks PN 9 4800bps PN 9 4800bps fm1 k/ dev 2.4 kHz CCITT D/U ratio 1 st Mix, 2 signal method, 1 % error 2 nd Mix, 2 signal method, 1 % error 12.5 kHz ch, 2 signal method, 1 % error Unwanted signal +/-1M, 2 signal method, 1 % error 3 signal method, 1 % error L = GND H = 2.8 V CH shift of 25 kHz (from PLL setup) When power ON (from PLL setup) CH shift of 25 kHz (from PLL setup) When power ON (from PLL setup) Conducted 50 Ω With -100 dBm Wiｔh -110 dBm Specifications are subject to change without prior notice Notice The time required until a stable DO is established may get longer due to the possible frequency drift caused by operation environment changes, especially when switching from TX to RX, from RX to TX and changing channels. Please make sure to optimize the timing. The recommended preamble is more than 20 ms. Antenna connection is designed as pin connection. RF output power, sensitivity, spurious emission and spurious radiation levels may vary with the pattern used between the RF pin and the coaxial connection. Please make sure to verify those parameters before use. The feet of the shield case should be soldered to the wide GND pattern to avoid any change in characteristics. Notes about the specification values *1 BER: RF level where no error per 2556 bits is confirmed with the signal of PN9 and 4800 bps. *2 BER (1 % error) : RF level where 1% error per 2556 bits is confirmed with the signal of PN9 and 4800 bps. *3 Spurious response, CH selectivity: The deviation of the unwanted signal is 12% of the channel separation (=1.5kHz). Modulation frequency is 400Hz. *4 Time until valid Data-out : Valid DO is determined at the point where Bit Error Rate meter starts detecting the signal of 4800 bps, 1010repeated signal. All specifications are specified based on the data measured in a shield room using the PLL setting controller board prepared by Circuit Design. OG_LMD-400-R-AB_v11e 5 Circuit Design, Inc. OPERATION GUIDE PIN DESCRIPTION Pin name I/O Description Equivalent circuit 47P SAW FILTER RF GND I/O I RF RF input terminal Antenna impedance nominal 50 Ω 100nH GND GROUND terminal The GND pins and the feet of the shield case shoud be connected to the wide GND pattern. VCC 2.8V VCC TXSEL I Power supply terminal DC 3.0 to 5.5 V I TX select terminal GND = TXSEL active To enable the transmitter circuits, connect TXSEL to GND and RXSEL to OPEN or 2.8 V. REG 22µ 2.8V 20K TXSEL I O Analogue output terminal There is DC offset of approx. 1 V. Refer to the specification table for amplitude level. MB15E03 I PLL data setting input terminal Interface voltage H = 2.8 V, L = 0 V MB15E03 DATA I PLL data setting input terminal Interface voltage H = 2.8 V, L = 0 V LE I PLL data setting input terminal Interface voltage H = 2.8 V, L = 0 V AF CLK OG_LMD-400-R-AB_v11e 6 47P 10 2.8V RX select terminal GND= RXSEL active To enable the receiver circuits, connect RXSEL to GND and TXSEL to OPEN or 2.8 V. RXSEL 10µ 47P 2.8V 10 20K 2.8V RXSEL 2K CLK 2K DATA 2K LE MB15E03 Circuit Design, Inc. OPERATION GUIDE 2.8V LD O PLL lock/unlock monitor terminal Lock = H (2.8 V), Unlock = L (0 V) 2K LD MB15E03 102 RSSI O Received Signal Strength Indicator terminal 2.8V DO DI O I OG_LMD-400-R-AB_v11e Data output terminal Interface voltage: H=2.8V, L=0V 10K 2K DO 102 Data input terminal Interface voltage: H=2.8V to Vcc, L=0V Input data pulse width Min.100 µs Max. 15 ms 7 Circuit Design, Inc. OPERATION GUIDE. BLOCK DIAGRAM OG_LMD-400-R-AB_v11e <LMD-400-R 438-442 MHz /458-462 MHz> 8 Circuit Design, Inc. OPERATION GUIDE. DIMENSIONS OG_LMD-400-R-AB_v11e 9 Circuit Design, Inc. OPERATION GUIDE . PLL IC CONTROL PLL IC control Figure 1 up to 1200MHz VCO 2kohm Voltage Controled Oscillator Fin CLK Xf in Data 2kohm 2kohm LE GND LPF PLL Do +2.8v LE PS VCC ZC 2kohm 21.25MHz DATA MB15E03SL Vp TCXO Reference Oscillator CLK LD/f out OSCout P OSCin R LD STD-302 Control pin name #:Control v oltage = +2.8v LMD-400-R is equipped with an internal PLL frequency synthesizer as shown in Figure 1. The operation of the PLL circuit enables the VCO to oscillate at a stable frequency. Transmission frequency is set externally by the controlling IC. LMD-400-R has control terminals (CLK, LE, DATA) for the PLL IC and the setting data is sent to the internal register serially via the data line. Also LMD-400-R has a Lock Detect (LD) terminal that shows the lock status of the frequency. These signal lines are connected directly to the PLL IC through a 2 kΩ resistor. The interface voltage of LMD-400-R is 2.8 V, so the control voltage must be the same. LMD-400-R comes equipped with a Fujitsu MB15E03SL PLL IC. Please refer to the manual of the PLL IC. The following is a supplementary description related to operation with LMD-400-R. In this description, the same names and terminology as in the PLL IC manual are used, so please read the manual beforehand. OG_LMD-400-R-AB_v11e 10 Circuit Design, Inc. OPERATION GUIDE . How to calculate the setting values for the PLL register The PLL IC manual shows that the PLL frequency setting value is obtained with the following equation. fvco = [(M x N)+A] x fosc / R -- Equation 1 fvco : Output frequency of external VCO M: Preset divide ratio of the prescaler (64 or 128) N: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127 A<N)) fosc: Output frequency of the reference frequency oscillator R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) With LMD-400-R, there is an offset frequency (foffset) 21.7 MHz for the transmission RF channel frequency fch. Therefore the expected value of the frequency generated at VCO (fexpect) is as below. fvco = fexpect = fch – foffset ---- Equation 2 The PLL internal circuit compares the phase to the oscillation frequency fvco. This phase comparison frequency (fcomp) must be decided. fcomp is made by dividing the frequency input to the PLL from the reference frequency oscillator by reference counter R. LMD-400-R uses 21.25 MHz for the reference clock fosc. fcomp is one of 6.25 kHz, 12.5 kHz or 25 kHz. The above equation 1 results in the following with n = M x N + A, where “n” is the number for division. n = fvco/fcomp ---- Equation 4 note: fcomp = fosc/R fvco=n*fcomp ---- Equation 3 Also, this PLL IC operates with the following R, N, A and M relational expressions. R=fosc/fcomp ---- Equation 5 N = INT (n / M) ---- Equation 6 A = n - (M x N) ---- Equation 7 INT: integer portion of a division. As an example, the setting value of RF channel frequency fch 458.000 MHz can be calculated as below. The constant values depend on the electronic circuits of LMD-400-R. Conditions: Channel center frequency: fch = 458.000 MHz Constant: Offset frequency: foffset=21.7 MHz Constant: Reference frequency: fosc=21.25 MHz Set 12.5 kHz for Phase comparison frequency and 64 for Prescaler value M The frequency of VCO will be fvco = fexpect = fch - foffset = 458.000 –21.7 = 436.300 MHz Dividing value “n” is derived from Equation 4 n = fvco / fcomp = 436.300 MHz/12.5 kHz = 34904 Value “R” of the reference counter is derived from Equation 5. R = fosc/fcomp = 21.25 MHz/12.5 kHz = 1700 Value “N” of the programmable counter is derived from Equation 6. N = INT (n/M) = INT(34904/64) = 545 Value “A“ of the swallow counter is derived from Equation 7. A = n – (M x N) =34904 – 64 x 545 = 24 The frequency of LMD-400-R is locked at a center frequency fch by inputting the PLL setting values N, A and R obtained with the above equations as serial data. The above calculations are the same for the other frequencies. Excel sheets that contain automatic calculations for the above equations can be found on our web site (www.circuitdesign.jp). The result of the calculations is arranged as a table in the CPU ROM. The table is read by the channel change routine each time the channel is changed, and the data is sent to the PLL. OG_LMD-400-R-AB_v11e 11 Circuit Design, Inc. OPERATION GUIDE . Method of serial data input to the PLL After the RF channel table plan is decided, the data needs to be allocated to the ROM table and read from there or calculated with the software. Together with this setting data, operation bits that decide operation of the PLL must be sent to the PLL. The operation bits for setting the PLL are as follows. These values are placed at the head of the reference counter value and are sent to the PLL. 1. CS: Charge pump current select bit CS = 0 +/-1.5 mA select VCO is optimized to +/-1.5 mA 2. LDS: LD/fout output setting bit LDS = 0 LD select Hardware is set to LD output 3. FC: Phase control bit for the phase comparator FC = 1 Hardware operates at this phase Figure 2 1st Data 2nd Data 2nd data N11 N10 N9 N8 N7 N6 A1 CNT=0 1st data CS LDS FC SW R14 R13 R1 CNT=1 Inv alid Data DATA MSB LSB CLK t1 t2 t6 t3 t0 LE STD-302 terminal name #: t0,t5 >= 100 ns t1,t2,t6 >= 20 ns t3,t4 >= 30 ns t4 t5 #: Keep the LE terminal at a low level, w hen w rite the data to the shift resister. The PLL IC, which operates as shown in the block diagram in the manual, shifts the data to the 19-bit shift register and then transfers it to the respective latch (counter, register) by judging the CNT control bit value input at the end. 1. CLK [Clock]: Data is shifted into the shift register on the rising edge of this clock. 2. LE [Load Enable]: Data in the 19-bit shift register is transferred to respective latches on the rising edge of the clock. The data is transferred to a latch according to the control bit CNT value. 3. Data [Serial Data]: You can perform either reference counter setup or programmable counter setup first. OG_LMD-400-R-AB_v11e 12 Circuit Design, Inc. OPERATION GUIDE . TIMING CHART Control timing in a typical application is shown in Figure 3. Initial setting of the port connected to the radio module is performed when power is supplied by the CPU and reset is completed. MOS-FET for supply voltage control of the radio module, RXSEL and TXSEL are set to inactive to avoid unwanted emissions. The power supply of the radio module is then turned on. When the radio module is turned on, the PLL internal resistor is not yet set and the peripheral VCO circuit is unstable. Therefore data transmission and reception is possible 40 ms after the setting data is sent to the PLL at the first change of channel, however from the second change of channel, the circuit stabilizes within 20 ms and is able to handle the data. Changing channels must be carried out in the receive mode. If switching is performed in transmission mode, unwanted emission occurs. If the module is switched to the receive mode when operating in the same channel, (a new PLL setting is not necessary) it can receive data within 5 ms of switching*1. For data transmission, if the RF channel to be used for transmission is set while still in receiving mode, data can be sent at 5 ms after the radio module is switched from reception to transmission*2. Check that the Lock Detect signal is “high” 20 ms after the channel is changed. In some cases the Lock Detect signal becomes unstable before the lock is correctly detected, so it is necessary to note if processing of the signal is interrupted. It is recommended to observe the actual waveform before writing the process program. *1 DC offset may occur due to frequency drift caused by ambient temperature change. Under conditions below -10 °C, 10 to 20 ms delay of DO output is estimated. The customer is urged to verify operation at low temperature and optimize the timing. *2 Sending ‘10101…..’ preamble just after switching to transmission mode enables smoother operation of the binarization circuit of the receiver. Preamble length: -20 °C - +60 °C: 15 ms (Typical) OG_LMD-400-R-AB_v11e 13 Circuit Design, Inc. OPERATION GUIDE . LMD-400 Figure 3: Timing diagram for STD-302 Status immediately after pow er comes on. Normal status Channel change No channel change CPU Pow er on LMD-400 STD-302 Power on #:3 Pow er on Receiv e mode Receiv e mode Receiv e mode activ e period activ e period activ e period Activ e period RXSEL #:1 #:2 #:4 CPU control, CH change & Data rec. Timing 5 ms #:4 CH Data #:5 CH #:4 Data #:6 Check LD signal Check LD signal CH Data #:7 Check LD signal LD 40 ms 10 to 20 ms Transmit mode activ e Transmit mode activ e Transmit mode activ e TXSEL Data transmit 5 ms 5 ms #:1 Reset control CPU 5 ms #:5 40 ms later, the receiver can receive the data after changing the channel.. #:2 Initialize the port connected to the module. #:6 10 to 20 ms later, the receiver can receive the data after changing the channel. #:3 Supply pow er to the module after initializing CPU. #:7 5 ms later, the data can be received if the RF channel is not changed. #:4 RFchannel change must be performed in receiving mode. OG_LMD-400-R-AB_v11e 14 Circuit Design, Inc. OPERATION GUIDE PLL FREQUENCY SETTING DATA REFERENCE Example : Setting from 458.000 MHz to 458.6125 MHz Parameter name Value Phase Comparing Frequency Fcomp [kHz] Start Channel Frequency Fch [MHz] Channel Step Frequency [kHz] Number of Channel Prescaler M 12.5 458.000 12.5 50 64 Parameter name Reference Frequency Fosc [MHz] Offset Frequency Foffset [MHz] Value 21.25 21.7 Expect Channel Frequency Frequency FCH ＦEXPECT Lock Frequency FVCO : For data input : Result of calculation : Fixed value Parameter name Reference Counter R Programmable Counter N Min. Value Programmable Counter N Max. Value Swallow Counter A Min. Value Swallow Counter A Max. Value Number of Division n (MHz) (MHz) (MHz) 458.0000 436.3000 436.3000 34904 458.0125 436.3125 436.3125 458.0250 436.3250 436.3250 458.0375 436.3375 436.3375 Programable Counter N Swallow Counter A 24 34905 545 545 34906 545 26 34907 545 27 28 25 458.0500 436.3500 436.3500 34908 545 458.0625 436.3625 436.3625 34909 545 29 458.0750 436.3750 436.3750 34910 545 30 34911 545 31 32 458.0875 436.3875 436.3875 458.1000 436.4000 436.4000 34912 545 458.1125 436.4125 436.4125 34913 545 33 458.1250 436.4250 436.4250 34914 545 34 35 458.1375 436.4375 436.4375 34915 545 458.1500 436.4500 436.4500 34916 545 36 458.1625 436.4625 436.4625 34917 545 37 38 458.1750 436.4750 436.4750 34918 545 458.1875 436.4875 436.4875 34919 545 39 458.2000 436.5000 436.5000 34920 545 40 41 458.2125 436.5125 436.5125 34921 545 458.2250 436.5250 436.5250 34922 545 42 458.2375 436.5375 436.5375 34923 545 43 34924 545 44 45 458.2500 436.5500 436.5500 458.2625 436.5625 436.5625 34925 545 458.2750 436.5750 436.5750 34926 545 46 34927 545 47 48 458.2875 436.5875 436.5875 458.3000 436.6000 436.6000 34928 545 458.3125 436.6125 436.6125 34929 545 49 458.3250 436.6250 436.6250 34930 545 50 51 458.3375 436.6375 436.6375 34931 545 458.3500 436.6500 436.6500 34932 545 52 458.3625 436.6625 436.6625 34933 545 53 34934 545 54 458.3750 OG_LMD-400-R-AB_v11e 436.6750 436.6750 15 Value 1700 545 546 0 63 Circuit Design, Inc. OPERATION GUIDE 458.3875 436.6875 436.6875 34935 545 55 458.4000 436.7000 436.7000 34936 545 56 57 458.4125 436.7125 436.7125 34937 545 458.4250 436.7250 436.7250 34938 545 58 458.4375 436.7375 436.7375 34939 545 59 60 458.4500 436.7500 436.7500 34940 545 458.4625 436.7625 436.7625 34941 545 61 458.4750 436.7750 436.7750 34942 545 62 63 458.4875 436.7875 436.7875 34943 545 458.5000 436.8000 436.8000 34944 0 458.5125 436.8125 436.8125 34945 546 546 34946 546 2 3 458.5250 436.8250 436.8250 1 458.5375 436.8375 436.8375 34947 546 458.5500 436.8500 436.8500 34948 546 4 458.5625 436.8625 436.8625 34949 546 5 6 458.5750 436.8750 436.8750 34950 546 458.5875 436.8875 436.8875 34951 546 7 458.6000 436.9000 436.9000 34952 546 8 34953 546 9 458.6125 436.9125 436.9125 Excel sheets that contain automatic calculations for the above equations can be found on our web site (www.circuitdesign.jp). OG_LMD-400-R-AB_v11e 16 Circuit Design, Inc. OPERATION GUIDE Regulatory compliance information Regulatory compliance of the LMD-400-R The LMD-400-R is designed for embedding in other equipment (Products incorporating the LMD-400-R are henceforward referred to as final products). The European regulation applicable to the LMD-400-R is the R&TTE Directive 1999/5/EC. The conformity assessment for the LMD-400-R was completed in accordance with the R&TTE Directive Annex III procedures, and the Declaration of Conformity is attached to this manual. Note: The LMD-400-R is intended for use in hand-portable/mobile stations under Private Mobile Radio (PMR) service. PMR systems are usually operated under license and subject to National frequency management plans. For details of the national frequency plan, please consult the relevant authorities. Cautions related to regulatory compliance when embedding the LMD-400-R 1. Antenna The LMD-400-R is supplied without a dedicated antenna and the user is required to provide an antenna. The conformity assessment of the LMD-400-R was performed using Circuit Design’s standard antenna ANT-LEA-01 (1/4 lambda lead antenna), so we recommend using the ANT-LEA-01 antenna or an antenna with equivalent characteristics and performance. For details about our standard antenna, refer to www.circuitdesign.jp or contact us. If you use an antenna other than the recommended antenna, further radio conformity assessment may be required. 2. Supply voltage The LMD-400-R should be used within the specified voltage range (3.0 V to 5.5 V). 3. Enclosure To fulfill the requirements of EMC and safety requirements, the LMD-400-R should be mounted on the circuit boards of the final products and must be enclosed in the cases of the final products. No surface of the LMD-400R should be exposed. Conformity assessment of the final product The manufacturer of the final product is responsible for the conformity assessment procedures of the final product in accordance with the R&TTE Directive. As to the conformity assessment of the R&TTE Directive Article 3.2 (Efficient use of the radio spectrum), the manufacturer of the final product incorporating the R&TTE assessed LMD-400-R will be exempted from its conformity assessment procedures. For details of how to use the conformity assessment of the LMD-400-R, please consult the relevant authorities or accredited certification bodies. Notification of the final product The notification required by R&TTE Directive Article 6 (4) is not necessary if the final product is used in the harmonized frequency band and is classified as Class-1 equipment. If the final product is not used in the harmonized frequency band and is classified as Class-2 equipment, the manufacturer of the final product has a duty to notify the relevant radio regulatory authorities in the countries where the final product is sold. *NOTE: A list of Class-1 equipment is available at http://www.ero.dk/. Exemption clause Circuit Design, Inc does not guarantee the accuracy of the above mentioned information about the conformity assessment and notification of the final product. Directives, technical standards, principles of operation and the like may be interpreted differently by the authorities in each country. Also the national laws and restrictions vary with the country. In case of doubt or uncertainty, we recommend that you check with the authorities or official certification organizations of the relevant countries. OG_LMD-400-R-AB_v11e 17 Circuit Design, Inc. OPERATION GUIDE Regulatory compliance information OG_LMD-400-R-AB_v11e 18 Circuit Design, Inc. OPERATION GUIDE Important notice Customers are advised to consult with Circuit Design sales representatives before ordering. Circuit Design believes the provided information is accurate and reliable. However, Circuit Design reserves the right to make changes to this product without notice. • Circuit Design products are neither designed nor intended for use in life support applications where malfunction can reasonably be expected to result in significant personal injury to the user. Any use of Circuit Design products in such safety-critical applications is understood to be fully at the risk of the customer and the customer must fully indemnify Circuit Design, Inc for any damages resulting from any improper use. • As the radio module communicates using electronic radio waves, there are cases where transmission will be temporarily cut off due to the surrounding environment and method of usage. The manufacturer is exempt from all responsibility relating to resulting harm to personnel or equipment and other secondary damage. • The manufacturer is exempt from all responsibility relating to secondary damage resulting from the operation, performance and reliability of equipment connected to the radio module. • Copyright • All rights in this operation guide are owned by Circuit Design, Inc. No part of this document may be copied or distributed in part or in whole without the prior written consent of Circuit Design, Inc. Cautions • As the radio module communicates using electronic radio waves, there are cases where transmission will be temporarily cut off due to the surrounding environment and method of usage. The manufacturer is exempt from all responsibility relating to resulting harm to personnel or equipment and other secondary damage. • Do not use the equipment within the vicinity of devices that may malfunction as a result of electronic radio waves from the radio module. • The manufacturer is exempt from all responsibility relating to secondary damage resulting from the operation, performance and reliability of equipment connected to the radio module. • Communication performance will be affected by the surrounding environment, so communication tests should be carried out before actual use. • Ensure that the power supply for the radio module is within the specified rating. Short circuits and reverse connections may result in overheating and damage and must be avoided at all costs. • Ensure that the power supply has been switched off before attempting any wiring work. • The case is connected to the GND terminal of the internal circuit, so do not make contact between the '+' side of the power supply terminal and the case. • When batteries are used as the power source, avoid short circuits, recharging, dismantling, and pressure. Failure to observe this caution may result in the outbreak of fire, overheating and damage to the equipment. Remove the batteries when the equipment is not to be used for a long period of time. Failure to observe this caution may result in battery leaks and damage to the equipment. • Do not use this equipment in vehicles with the windows closed, in locations where it is subject to direct sunlight, or in locations with extremely high humidity. • The radio module is neither waterproof nor splash proof. Ensure that it is not splashed with soot or water. Do not use the equipment if water or other foreign matter has entered the case. • Do not drop the radio module or otherwise subject it to strong shocks. • Do not subject the equipment to condensation (including moving it from cold locations to locations with a significant increase in temperature.) • Do not use the equipment in locations where it is likely to be affected by acid, alkalis, organic agents or corrosive gas. • Do not bend or break the antenna. Metallic objects placed in the vicinity of the antenna will have a great effect on communication performance. As far as possible, ensure that the equipment is placed well away from metallic objects. • The GND for the radio module will also affect communication performance. If possible, ensure that the case GND and the circuit GND are connected to a large GND pattern. Warnings • Do not take a part or modify the equipment. • Do not remove the product label (the label attached to the upper surface of the module.) Using a module from which the label has been removed is prohibited. OG_LMD-400-R-AB_v11e 19 Circuit Design, Inc. OPERATION GUIDE REVISION HISTORY Version 0.9 1.0 1.1 Date Jan. 2010 May. 2010 Sept. 2011 OG_LMD-400-R-AB_v11e Description Preliminary DOC added specification reviewed DOC updated Remark 、 20 Circuit Design, Inc.
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