5495A/DM7495 4-Bit Parallel Access Shift Registers General Description These 4-bit registers feature parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The registers have three modes of operation. Parallel (broadside) load Shift right (the direction QA toward QD) Shift left (the direction QD toward QA) Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input. During loading, the entry of serial data is inhibited. Shift right is accomplished on the high-to-low transition of clock 1 when the mode control is low; shift left is accomplished on the high-to-low transition of clock 2 when the mode control is high by connecting the output of each flipflop to the parallel input of the previous flip-flop (QD to input C, etc.) and serial data is entered at input D. The clock input may be applied simultaneously to clock 1 and clock 2 if both modes can be clocked from the same source. Changes at the mode control input should normally be made while both clock inputs are low; however, conditions described in the last three lines of the truth table will also ensure that register contents are protected. Features Y Y Typical maximum clock frequency 36 MHz Typical power dissipation 250 mW Connection Diagram Dual-In-Line Package TL/F/6534 – 1 Order Number 5495ADMQB, 5495AFMQB or DM7495N See NS Package Number J14A, N14A or W14B C1995 National Semiconductor Corporation TL/F/6534 RRD-B30M105/Printed in U. S. A. 5495A/DM7495 4-Bit Parallel Access Shift Registers June 1989 Absolute Maximum Ratings (Note) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C 54A DM74 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol 5495A Parameter DM7495 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 V 0.8 0.8 V mA VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current b 0.8 b 0.8 IOL Low Level Output Current 16 16 mA fCLK Clock Frequency (Note 4) 0 25 MHz tW Clock Pulse Width (Note 4) 15 11 15 tSU Data Setup Time (Note 4) 20 10 20 tEN Time to Enable Clock (Note 4) Clock 1 20 20 Clock 2 15 15 2 tH Data Hold Time (Note 4) 0 tIN Time to Inhibit Clock 1 or Clock 2 (Note 4) 10 TA Free Air Operating Temperature 2 25 V 0 b 10 0 ns 10 ns ns b 10 ns 10 b 55 125 ns 0 70 §C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max VI e 2.4V Mode 80 Others 40 Low Level Input Current VCC e Max VI e 0.4V Mode b 3.2 Others b 1.6 Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max (Note 3) IIL IOS ICC 2.4 3.4 0.2 V 0.4 V 1 mA DM54 b 18 b 57 DM74 b 18 b 57 50 75 mA mA mA mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. Note 3: ICC is measured with all outputs and serial input open; A, B, C, and D inputs grounded: Mode Control at 4.5V: and a momentary 3V, then ground, applied to both clock inputs. Note 4: TA e 25§ C and VCC e 5V. 2 Switching Characteristics Symbol at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) From (Input) To (Output) Parameter RL e 400X, CL e 15 pF Min Units Max fMAX Maximum Clock Frequency tPHL Propagation Delay Time High to Low Level Output Clock to Output 25 MHz 35 ns tPLH Propagation Delay Time Low to High Level Output Clock to Output 35 ns Function Table Inputs Mode Control H H H L L L u v v u u Clocks Serial 2(L) 1(R) H X X X H v v L X X L L L H H Outputs Parallel v v L L H L H X X X X H L X X X X X A B C D X a QB ² X X X X X X X X X b QC ² X X X X X X X X X c QD ² X X X X X X X X X d d X X X X X X X X QA QB QC QD QA0 a QBn QA0 H L QA0 QA0 QA0 QA0 QA0 QB0 b QCn QB0 QAn QAn QB0 QB0 QB0 QB0 QB0 QC0 c QDn QC0 QBn QBn QC0 QC0 QC0 QC0 QC0 QD0 d d QD0 QCn QCn QD0 QD0 QD0 QD0 QD0 ² Shifting left requires external connection of QB to A, QC to B, QD to C. Serial data is entered at input D. H e High Level (Steady State), L e Low Level (Steady State), X e Don’t Care (Any input, including transitions) v e Transition from high to low level, u e Transition from low to high level a, b, c, d e The level of steady, state input at inputs A, B, C, or D, respectively. QA0, QB0, QC0, QD0 e The level of QA, QB, QC, QD, respectively, before the indicated steady state input conditions were established. QAn, QBn, QCn, QDn e The level of QA, QB, QC, QD, respectively, before the most recent v transition of the clock. Logic Diagram TL/F/6534 – 2 3 4 Physical Dimensions inches (millimeters) 14-Lead Ceramic Dual-In-Line Package (J) Order Number 5495ADMQB NS Package Number J14A 14-Lead Molded Dual-In-Line Package (N) Order Number DM7495N NS Package Number N14A 5 5495A/DM7495 4-Bit Parallel Access Shift Registers Physical Dimensions inches (millimeters) 14-Lead Ceramic Flat Package (W) Order Number 5495AFMQB NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project