datasheet for PC7119VM1200 by Freescale

datasheet for PC7119VM1200 by Freescale
Freescale Semiconductor
Data Sheet
Document Number: MSC7119
Rev. 8, 4/2008
MSC7119
Low-Cost 16-bit DSP with
DDR Controller and 10/100
Mbps Ethernet MAC
• StarCore® SC1400 DSP extended core with one SC1400 DSP
core, 256 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte
instruction cache (ICache), four-entry write buffer, programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
• 192 Kbyte M2 memory for critical data and temporary data
buffering.
• 8 Kbyte boot ROM.
• AHB-Lite crossbar switch that allows parallel data transfers
between four master ports and six slave ports, where each port
connects to an AHB-Lite bus; fixed or round robin priority
programmable at each slave port; programmable bus parking at
each slave port; low power mode.
• Internal PLL generates up to 300 MHz clock for the SC1400 core
and up to 150 MHz for the crossbar switch, DMA channels, M2
memory, and other peripherals.
• Clock synthesis module provides predivision of PLL input clock;
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
• Enhanced 16-bit wide host interface (HDI16) provides a glueless
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
• DDR memory controller that supports byte enables for up to a
32-bit data bus; glueless interface to 150 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
• Programmable memory interface with independent read buffers,
programmable predictive read feature for each buffer, and a write
buffer.
• System control unit performs software watchdog timer function;
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite master buses; and has address
out-of-range detection on each crossbar switch buses.
• Event port collects and counts important signal events including
DMA and interrupt requests and trigger events such as interrupts,
breakpoints, DMA transfers, or wake-up events; units operate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
MAP-BGA–400
17 mm × 17 mm
• Multi-channel DMA controller with 32 time-multiplexed
unidirectional channels, priority-based time-multiplexing
between channels using 32 internal priority levels, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
• Two independent TDM modules with independent receive and
transmit, programmable sharing of frame sync and clock,
programmable word size (8 or 16-bit), hardware-base
A-law/µ-law conversion, up to 50 Mbps data rate per TDM, up to
128 channels, with glueless interface to E1/T1 frames and MVIP,
SCAS, and H.110 buses.
• Ethernet controller with support for 10/100 Mbps MII/RMII
designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™,
and 802.3ac™; with internal receive and transmit FIFOs and a
FIFO controller; direct access to internal memories via its own
DMA controller; full and half duplex operation; programmable
maximum frame length; virtual local area network (VLAN) tag
and priority support; retransmission of transmit FIFO following
collision; CRC generation and verification for inbound and
outbound packets; and address recognition including
promiscuous, broadcast, individual address. hash/exact match,
and multicast hash match.
• UART with full-duplex operation up to 5.0 Mbps.
• Up to 41 general-purpose input/output (GPIO) ports.
• I2C interface that allows booting from EEPROM devices up to 1
Mbyte.
• Two quad timer modules, each with sixteen configurable 16-bit
timers.
• fieldBIST™ unit detects and provides visibility into unlikely field
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated speed, is free from
reliability defects, and reports diagnostics for partial or complete
device inoperability.
• Standard JTAG interface allows easy integration to system
firmware and internal on-chip emulation (OCE10) module.
• Optional booting external host via 8-bit or 16-bit access through
the HDI16, I2C, or SPI using in the boot ROM to access serial SPI
Flash/EEPROM devices; different clocking options during boot
with the PLL on or off using a variety of input frequency ranges.
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
Table of Contents
1
2
3
4
5
6
7
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 MAP-BGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .18
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .19
2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .41
3.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . .41
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .42
3.3 Estimated Power Usage Calculations. . . . . . . . . . . . . .49
3.4 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.5 DDR Memory System Guidelines . . . . . . . . . . . . . . . . .54
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
MSC7119 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3
MSC7119 Molded Array Process-Ball Grid Array
(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4
MSC7119 Molded Array Process-Ball Grid Array
(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5
Timing Diagram for a Reset Configuration Write . . . . 25
DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 26
DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 27
DDR DRAM AC Test Load. . . . . . . . . . . . . . . . . . . . . 28
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . .
TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . .
Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . .
Asynchronous Input Signal Timing . . . . . . . . . . . . . . .
Serial Management Channel Timing . . . . . . . . . . . . .
Read Timing Diagram, Single Data Strobe . . . . . . . .
Read Timing Diagram, Double Data Strobe . . . . . . . .
Write Timing Diagram, Single Data Strobe. . . . . . . . .
Write Timing Diagram, Double Data Strobe . . . . . . . .
Host DMA Read Timing Diagram, HPCR[OAD] = 0 . .
Host DMA Write Timing Diagram, HPCR[OAD] = 0 . .
I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . .
EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Test Clock Input Timing Diagram . . . . . . . . . . . . . . . .
Boundary Scan (JTAG) Timing Diagram . . . . . . . . . .
Test Access Port Timing Diagram . . . . . . . . . . . . . . .
TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 1 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 2 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 3 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 4 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 5 . . . . . . . . . . . . . . . . . . . .
PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . .
SSTL Termination Techniques . . . . . . . . . . . . . . . . . .
SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
29
29
30
30
31
33
33
34
34
35
35
36
37
37
37
38
38
39
40
40
40
43
44
45
46
47
48
54
55
MSC7119 Data Sheet, Rev. 8
2
Freescale Semiconductor
JTAG
DMA
(32 Channel)
AMDMA
128
64
OCE10
to IPBus
SC1400
Core
Trace
Buffer
(8 KB)
64
M2
SRAM
(192 KB)
128
Boot ROM
(8 KB)
128
ASM2
MUX
JTAG Port
64
DSP
Extended
Core
ASEMI
64
External
Memory
Interface
from
IPBus
External Bus
128
M1
SRAM
(256 KB)
64
128
AMEC
64
32
HDI16
Port
TDM
32
2 TDMs
PLL/Clock
I2C
APB
UART
PLL/Clock
I2C
RS-232
GPIO
64
AMENT
Ethernet
MAC
Note: The arrows show the
direction of the transfer.
ASAPB
Host
Interface
(HDI16)
ASM1
64
64
P XA XB
64
ASIB
32
IB Bridge
Extended
Core
Interface
AMIC
ASTH
MUX
Instruction
Cache
(16 KB)
APB Bridge
AHB-Lite Crossbar Switch
Interrupt Control
Fetch
Unit
32
Interrupts
GPIO
System Ctrl
32
to EMI
to DMA
MII/RMII
Watchdog
Event Port
BTMs
Events
to/from OCE10
Timers
IPBus
Figure 1. MSC7119 Block Diagram
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
3
Pin Assignments
1
Pin Assignments
This section includes diagrams of the MSC7119 package ball grid array layouts and pinout allocation tables.
1.1
MAP-BGA Ball Layout Diagrams
Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers.
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
GND
GND
DQM1
DQS2
CK
CK
HD15
HD12
HD10
HD7
HD6
HD4
HD1
HD0
GND
BM3
NC
NC
NC
NC
B
VDDM
NC
CS0
DQM2
DQS3
DQS0
CKE
WE
HD14
HD11
HD8
HD5
HD2
NC
BM2
NC
NC
NC
NC
NC
C
D24
D30
D25
CS1
DQM3
DQM0
DQS1
RAS
CAS
HD13
HD9
HD3
NC
NC
NC
NC
NC
NC
NC
NC
D
VDDM
D28
D27
GND
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDC
NC
NC
NC
E
GND
D26
D31
VDDM
VDDM
VDDC
VDDC
VDDC
VDDC
VDDM
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDC
VDDC
NC
NC
NC
F
VDDM
D15
D29
VDDC
VDDC
VDDC
GND
GND
GND
VDDM
VDDM
GND
GND
GND
VDDIO
VDDC
VDDC
NC
NC
NC
G
GND
D13
GND
VDDM
VDDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDIO
VDDIO
VDDC
NC
NC
NC
H
D14
D12
D11
VDDM
VDDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDIO
VDDIO
VDDC
NC
HA2
HA1
J
D10
VDDM
D9
VDDM
VDDM
VDDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDIO
VDDC
HA3
HACK
HREQ
K
D0
GND
D8
VDDC
VDDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDIO
VDDIO
VDDC
HA0
HDDS
HDS
L
D1
GND
D3
VDDC
VDDM
GND
GND
GND
GND
GND
GND
GND
GND
VDDIO
VDDIO
VDDIO
VDDC
HCS2
HCS1
HRW
M
D2
VDDM
D5
VDDM
VDDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDC
VDDC
SDA
UTXD
URXD
N
D4
D6
VREF
VDDM
VDDM
VDDM
GND
GND
GND
GND
GND
GND
GND
GND
VDDIO
VDDC
VDDC
CLKIN
SCL
VSSPLL
P
D7
D17
D16
VDDM
VDDM
VDDM
GND
GND
GND
GND
GND
GND
GND
GND
VDDIO
VDDIO
VDDC PORESET TPSEL VDDPLL
R
GND
D19
D18
VDDM
VDDM
VDDM
GND
VDDM
GND
VDDM
GND
GND
VDDIO
GND
VDDIO
VDDIO
VDDC
TDO
EE0
TEST0
T
VDDM
D20
D22
VDDM
VDDM
VDDC
VDDM
VDDM
VDDC
VDDM
VDDM
VDDIO
VDDIO
VDDIO
VDDIO
VDDC
VDDC
MDIO
TMS
HRESET
U
GND
D21
D23
VDDM
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
COL
TCK
TRST
V
VDDM
NC
A13
A11
A10
A5
A2
BA0
NC
T1TD
TX_ER
RXD2
RXD0
TX_EN
CRS
TDI
W
GND
VDDM
A12
A8
A7
A6
A3
NC
EVNT1 EVNT2 T0RFS T0TFS
T1TFS
TXD2
RXD3
TXD1
TXCLK RX_ER
Y
VDDM
GND
A9
A1
A0
A4
BA1
NMI
EVNT3 T0RCK
T1RCK T1TCK
TXD3
RXCLK
TXD0
RXD1
EVNT0 EVNT4 T0TCK T1RFS
T0RD
TOTD
T1RD
GND
MDC
RX_DV
Figure 2. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Top View
MSC7119 Data Sheet, Rev. 8
4
Freescale Semiconductor
Pin Assignments
Bottom View
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
NC
NC
NC
NC
BM3
GND
HD0
HD1
HD4
HD6
HD7
HD10
HD12
HD15
CK
CK
DQS2
DQM1
GND
GND
B
NC
NC
NC
NC
NC
BM2
NC
HD2
HD5
HD8
HD11
HD14
WE
CKE
DQS0
DQS3
DQM2
CS0
NC
VDDM
C
NC
NC
NC
NC
NC
NC
NC
NC
HD3
HD9
HD13
CAS
RAS
DQS1
DQM0
DQM3
CS1
D25
D30
D24
D
NC
NC
NC
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
GND
D27
D28
VDDM
E
NC
NC
NC
VDD
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDM
VDD
VDD
VDD
VDD
VDDM
VDDM
D31
D26
GND
F
NC
NC
NC
VDD
VDD
VDDIO
GND
GND
GND
VDDM
VDDM
GND
GND
GND
VDD
VDD
VDD
D29
D15
VDDM
G
NC
NC
NC
VDD
VDDIO
VDDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDM
GND
D13
GND
H
HA1
HA2
NC
VDD
VDDIO
VDDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDM
D11
D12
D14
J
HREQ
HACK
HA3
VDD
VDDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDM
VDDM
D9
VDDM
D10
K
HDS
HDDS
HA0
VDD
VDDIO
VDDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDD
D8
GND
D0
L
HRW
HCS1
HCS2
VDD
VDDIO
VDDIO
VDDIO
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDD
D3
GND
D1
M
URXD
UTXD
SDA
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDM
D5
VDDM
D2
N
VSSPLL
SCL
CLKIN
VDD
VDD
VDDIO
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDM
VDDM
VREF
D6
D4
P
VDDPLL TPSEL PORESET
VDD
VDDIO
VDDIO
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDM
VDDM
D16
D17
D7
R
TEST0
EE0
TDO
VDD
VDDIO
VDDIO
GND
VDDIO
GND
GND
VDDM
GND
VDDM
GND
VDDM
VDDM
VDDM
D18
D19
GND
T
HRESET
TMS
MDIO
VDD
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDM
VDDM
VDD
VDDM
VDDM
VDD
VDDM
VDDM
D22
D20
VDDM
U
TRST
TCK
COL
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDM
D23
D21
GND
V
TDI
CRS
TX_EN
RXD0
RXD2
TX_ER
T1TD
T1RFS T0TCK EVNT4 EVNT0
NC
BA0
A2
A5
A10
A11
A13
NC
VDDM
W
MDC
RX_ER TXCLK
TXD1
RXD3
TXD2
T1TFS
T1RD
T0TFS T0RFS EVNT2 EVNT1
NC
A3
A6
A7
A8
A12
VDDM
GND
Y
RX_DV
TXD0
RXCLK
TXD3
T1TCK T1RCK
TOTD
NMI
BA1
A4
A0
A1
A9
GND
VDDM
GND
RXD1
T0RD
T0RCK EVNT3
Figure 3. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
5
Pin Assignments
1.2
Signal List By Ball Location
Table 1 lists the signals sorted by ball number and configuration.
Table 1. MSC7119 Signals by Ball Designator
Signal Names
Software Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
Hardware Controlled
GPO Enabled
A1
GND
A2
GND
A3
DQM1
A4
DQS2
A5
CK
A6
CK
Primary
Alternate
A7
GPIC7
GPOC7
HD15
A8
GPIC4
GPOC4
HD12
A9
GPIC2
GPOC2
HD10
A10
reserved
HD7
A11
reserved
HD6
A12
reserved
HD4
A13
reserved
HD1
A14
reserved
HD0
A15
A16
GND
BM3
GPID8
A17
NC
A18
NC
A19
NC
A20
NC
B1
VDDM
B2
NC
B3
CS0
B4
DQM2
B5
DQS3
B6
DQS0
B7
CKE
B8
WE
GPOD8
reserved
B9
GPIC6
GPOC6
HD14
B10
GPIC3
GPOC3
HD11
B11
GPIC0
GPOC0
HD8
B12
reserved
HD5
B13
reserved
HD2
MSC7119 Data Sheet, Rev. 8
6
Freescale Semiconductor
Pin Assignments
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
GPI Enabled
(Default)
B14
B15
Interrupt
Enabled
Hardware Controlled
GPO Enabled
Primary
Alternate
NC
BM2
GPID7
B16
NC
B17
NC
B18
NC
B19
NC
B20
NC
C1
D24
C2
D30
C3
D25
C4
CS1
C5
DQM3
C6
DQM0
C7
DQS1
C8
RAS
C9
CAS
GPOD7
reserved
C10
GPIC5
GPOC5
HD13
C11
GPIC1
GPOC1
HD9
C12
reserved
HD3
C13
NC
C14
NC
C15
NC
C16
NC
C17
NC
C18
NC
C19
NC
C20
NC
D1
VDDM
D2
D28
D3
D27
D4
GND
D5
VDDM
D6
VDDM
D7
VDDM
D8
VDDM
D9
VDDM
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
7
Pin Assignments
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
Hardware Controlled
GPO Enabled
D10
VDDM
D11
VDDIO
D12
VDDIO
D13
VDDIO
D14
VDDIO
D15
VDDIO
D16
VDDIO
D17
VDDC
D18
NC
D19
NC
D20
NC
E1
GND
E2
D26
E3
D31
E4
VDDM
E5
VDDM
E6
VDDC
E7
VDDC
E8
VDDC
E9
VDDC
E10
VDDM
E11
VDDIO
E12
VDDIO
E13
VDDIO
E14
VDDIO
E15
VDDIO
E16
VDDC
E17
VDDC
E18
NC
E19
NC
E20
NC
F1
VDDM
F2
D15
F3
D29
F4
VDDC
F5
VDDC
Primary
Alternate
MSC7119 Data Sheet, Rev. 8
8
Freescale Semiconductor
Pin Assignments
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
Hardware Controlled
GPO Enabled
F6
VDDC
F7
GND
F8
GND
F9
GND
F10
VDDM
F11
VDDM
F12
GND
F13
GND
F14
GND
F15
VDDIO
F16
VDDC
F17
VDDC
F18
NC
F19
NC
F20
NC
G1
GND
G2
D13
G3
GND
G4
VDDM
G5
VDDM
G6
GND
G7
GND
G8
GND
G9
GND
G10
GND
G11
GND
G12
GND
G13
GND
G14
GND
G15
VDDIO
G16
VDDIO
G17
VDDC
G18
NC
G19
NC
G20
NC
H1
D14
Primary
Alternate
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
9
Pin Assignments
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
Hardware Controlled
GPO Enabled
H2
D12
H3
D11
H4
VDDM
H5
VDDM
H6
GND
H7
GND
H8
GND
H9
GND
H10
GND
H11
GND
H12
GND
H13
GND
H14
GND
H15
VDDIO
H16
VDDIO
H17
VDDC
H18
NC
Primary
Alternate
H19
reserved
HA2
H20
reserved
HA1
J1
D10
J2
VDDM
J3
D9
J4
VDDM
J5
VDDM
J6
VDDM
J7
GND
J8
GND
J9
GND
J10
GND
J11
GND
J12
GND
J13
GND
J14
GND
J15
GND
J16
VDDIO
J17
VDDC
MSC7119 Data Sheet, Rev. 8
10
Freescale Semiconductor
Pin Assignments
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
J18
Interrupt
Enabled
GPO Enabled
GPIC11
J19
J20
GPI Enabled
(Default)
Hardware Controlled
GPOC11
Alternate
HA3
HACK/HACK or HRRQ/HRRQ
reserved
HDSP
Primary
HREQ/HREQ or HTRQ/HTRQ
reserved
K1
D0
K2
GND
K3
D8
K4
VDDC
K5
VDDM
K6
GND
K7
GND
K8
GND
K9
GND
K10
GND
K11
GND
K12
GND
K13
GND
K14
GND
K15
VDDIO
K16
VDDIO
K17
VDDC
K18
reserved
HA0
K19
reserved
HDDS
K20
reserved
HDS/HDS or HWR/HWR
L1
D1
L2
GND
L3
D3
L4
VDDC
L5
VDDM
L6
GND
L7
GND
L8
GND
L9
GND
L10
GND
L11
GND
L12
GND
L13
GND
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
11
Pin Assignments
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
Hardware Controlled
GPO Enabled
L14
VDDIO
L15
VDDIO
L16
VDDIO
L17
VDDC
L18
GPIB11
GPOB11
Primary
Alternate
HCS2/HCS2
L19
reserved
HCS1/HCS1
L20
reserved
HRW or HRD/HRD
M1
D2
M2
VDDM
M3
D5
M4
VDDM
M5
VDDM
M6
GND
M7
GND
M8
GND
M9
GND
M10
GND
M11
GND
M12
GND
M13
GND
M14
GND
M15
GND
M16
VDDC
M17
VDDC
M18
GPIA14
IRQ15
GPOA14
SDA
M19
GPIA12
IRQ3
GPOA12
UTXD
M20
GPIA13
IRQ2
GPOA13
URXD
N1
D4
N2
D6
N3
VREF
N4
VDDM
N5
VDDM
N6
VDDM
N7
GND
N8
GND
N9
GND
MSC7119 Data Sheet, Rev. 8
12
Freescale Semiconductor
Pin Assignments
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
Hardware Controlled
GPO Enabled
N10
GND
N11
GND
N12
GND
N13
GND
N14
GND
N15
VDDIO
N16
VDDC
N17
VDDC
N18
CLKIN
N19
GPIA15
IRQ14
GPOA15
N20
VSSPLL
P1
D7
P2
D17
P3
D16
P4
VDDM
P5
VDDM
P6
VDDM
P7
GND
P8
GND
P9
GND
P10
GND
P11
GND
P12
GND
P13
GND
P14
GND
P15
VDDIO
P16
VDDIO
P17
VDDC
P18
PORESET
P19
TPSEL
P20
VDDPLL
R1
GND
R2
D19
R3
D18
R4
VDDM
R5
VDDM
Primary
Alternate
SCL
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
13
Pin Assignments
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
Hardware Controlled
GPO Enabled
R6
VDDM
R7
GND
R8
VDDM
R9
GND
R10
VDDM
R11
GND
R12
GND
R13
VDDIO
R14
GND
R15
VDDIO
R16
VDDIO
R17
VDDC
R18
TDO
R19
reserved
Alternate
EE0/DBREQ
R20
TEST0
T1
VDDM
T2
D20
T3
D22
T4
VDDM
T5
VDDM
T6
VDDC
T7
VDDM
T8
VDDM
T9
VDDC
T10
VDDM
T11
VDDM
T12
VDDIO
T13
VDDIO
T14
VDDIO
T15
VDDIO
T16
VDDC
T17
VDDC
T18
Primary
reserved
MDIO
T19
TMS
T20
HRESET
U1
GND
MSC7119 Data Sheet, Rev. 8
14
Freescale Semiconductor
Pin Assignments
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
Hardware Controlled
GPO Enabled
U2
D21
U3
D23
U4
VDDM
U5
VDDC
U6
VDDC
U7
VDDC
U8
VDDC
U9
VDDC
U10
VDDC
U11
VDDC
U12
VDDC
U13
VDDC
U14
VDDC
U15
VDDC
U16
VDDC
U17
VDDC
U18
reserved
TCK
U20
TRST
V1
VDDM
V2
NC
V3
A13
V4
A11
V5
A10
V6
A5
V7
A2
V8
BA0
V9
NC
V10
reserved
SWTE
GPIA16
Alternate
COL
U19
V11
Primary
EVNT0
IRQ12
GPOA16
EVNT4
V12
GPIA8
IRQ6
GPOA8
T0TCK
V13
GPIA4
IRQ1
GPOA4
T1RFS
V14
GPIA0
IRQ11
GPOA0
T1TD
V15
GPIA28
IRQ17
GPOA28
TX_ER
reserved
GPOD6
RXD2
reserved
V16
V17
GPID6
GPIA22
IRQ22
GPOA22
RXD0
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
15
Pin Assignments
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
V18
GPI Enabled
(Default)
GPIA24
V19
Hardware Controlled
Interrupt
Enabled
GPO Enabled
IRQ24
GPOA24
CRS
TDI
W1
GND
W2
VDDM
W3
A12
W4
A8
W5
A7
W6
A6
W7
A3
W8
NC
W9
GPIA17
GPOA17
IRQ13
BM0
Alternate
TX_EN
reserved
V20
W10
Primary
GPIC14
EVNT1
CLKO
GPOC14
EVNT2
W11
GPIA10
IRQ5
GPOA10
T0RFS
W12
GPIA7
IRQ7
GPOA7
T0TFS
W13
GPIA3
IRQ8
GPOA3
T1RD
W14
GPIA1
IRQ10
GPOA1
T1TFS
W15
GPID4
GPOD4
TXD2
reserved
RXD3
reserved
W16
GPIA27
IRQ18
GPOA27
W17
GPIA19
IRQ19
GPOA19
TXD1
W18
GPIA23
IRQ23
GPOA23
TXCLK or REFCLK
W19
GPIA26
IRQ26
GPOA26
RX_ER
W20
H8BIT
reserved
MDC
Y1
VDDM
Y2
GND
Y3
A9
Y4
A1
Y5
A0
Y6
A4
Y7
BA1
Y8
Y9
Y10
reserved
reserved
NMI
BM1
GPIC15
GPIA11
IRQ4
GPOC15
EVNT3
GPOA11
T0RCK
Y11
GPIA9
GPOA9
T0RD
Y12
GPIA6
GPOA6
T0TD
GPOA5
T1RCK
Y13
GPIA5
IRQ0
MSC7119 Data Sheet, Rev. 8
16
Freescale Semiconductor
Electrical Characteristics
Table 1. MSC7119 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
Primary
Alternate
Y14
GPIA2
IRQ9
GPOA2
Y15
GPIA29
IRQ16
GPOA29
TXD3
reserved
GPOD5
RXCLK
reserved
Y16
GPID5
T1TCK
Y17
GPIA20
IRQ20
GPOA20
TXD0
Y18
GPIA21
IRQ21
GPOA21
RXD1
GPOA25
RX_DV or CRS_DV
Y19
GND
Y20
2
Hardware Controlled
GPIA25
IRQ25
Electrical Characteristics
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications. For additional information, see the MSC711x Reference Manual.
2.1
Maximum Ratings
CAUTION
This device contains circuitry protecting against damage
due to high static voltage or electrical fields; however,
normal precautions should be taken to avoid exceeding
maximum voltage ratings. Reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (for
example, either GND or VDD).
In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification
does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values
in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction.
Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that can never exist.
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
17
Electrical Characteristics
Table 2 describes the maximum electrical ratings for the MSC7119.
Table 2. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Core supply voltage
VDDC
1.5
V
Memory supply voltage
VDDM
4.0
V
PLL supply voltage
VDDPLL
1.5
V
I/O supply voltage
VDDIO
–0.2 to 4.0
V
VIN
(GND – 0.2) to 4.0
V
VREF
4.0
V
Maximum operating temperature
TJ
105
°C
Minimum operating temperature
TA
–40
°C
TSTG
–55 to +150
°C
Input voltage
Reference voltage
Storage temperature range
Notes:
1.
2.
3.
2.2
Functional operating conditions are given in Table 3.
Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the listed limits may affect device reliability or cause permanent damage.
Section 3.1, Thermal Design Considerations includes a formula for computing the chip junction temperature (TJ).
Recommended Operating Conditions
Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 3. Recommended Operating Conditions
Rating
Symbol
Value
Unit
Core supply voltage
VDDC
1.14 to 1.26
V
Memory supply voltage
VDDM
2.38 to 2.63
V
PLL supply voltage
VDDPLL
1.14 to 1.26
V
I/O supply voltage
VDDIO
3.14 to 3.47
V
Reference voltage
VREF
1.19 to 1.31
V
TJ
TA
maximum: 105
minimum: –40
°C
°C
Operating temperature range
MSC7119 Data Sheet, Rev. 8
18
Freescale Semiconductor
Electrical Characteristics
2.3
Thermal Characteristics
Table 4 describes thermal characteristics of the MSC7119 for the MAP-BGA package.
Table 4. Thermal Characteristics for MAP-BGA Package
MAP-BGA 17
Characteristic
Symbol
× 17 mm5
Natural
Convection
200 ft/min
(1 m/s) airflow
Unit
Junction-to-ambient1, 2
RθJA
39
31
°C/W
Junction-to-ambient, four-layer board1, 3
RθJA
23
20
°C/W
Junction-to-board4
RθJB
12
°C/W
Junction-to-case5
RθJC
7
°C/W
Junction-to-package-top6
Ψ JT
2
°C/W
Notes:
1.
2.
3.
4.
5.
6.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
Section 3.1, Thermal Design Considerations explains these characteristics in detail.
2.4
DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC7119.
Note:
The leakage current is measured for nominal voltage values must vary in the same direction (for example, both VDDIO
and VDDC vary by +2 percent or both vary by –2 percent).
Table 5. DC Electrical Characteristics
Characteristic
Symbol
Min
Typical
Max
Unit
VDDC
VDDPLL
1.14
1.2
1.26
V
VDDM
2.375
2.5
2.625
V
VDDIO
3.135
3.3
3.465
V
VREF
0.49 × VDDM
1.25
0.51 × VDDM
V
VTT
VREF – 0.04
VREF
VREF + 0.04
V
VIHCLK
2.4
3.0
3.465
V
DRAM interface input high I/O voltage
VIHM
VREF + 0.28
VDDM
VDDM + 0.3
V
DRAM interface input low I/O voltage
VILM
–0.3
GND
VREF – 0.18
V
IIN
–1.0
0.09
1
µA
IVREF
—
—
5
µA
Core and PLL voltage
DRAM interface I/O voltage1
I/O voltage
DRAM interface I/O reference
voltage2
DRAM interface I/O termination voltage
Input high CLKIN voltage
Input leakage current, VIN = VDDIO
VREF input leakage current
3
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
19
Electrical Characteristics
Table 5. DC Electrical Characteristics (continued)
Characteristic
Symbol
Min
Typical
Max
Unit
IOZ
–1.0
0.09
1
µA
Signal low input current, VIL = 0.4 V
IL
–1.0
0.09
1
µA
Signal high input current, VIH = 2.0 V
IH
–1.0
0.09
1
µA
Output high voltage, IOH = –2 mA, except open drain pins
VOH
2.0
3.0
—
V
Output low voltage, IOL= 5 mA
VOL
—
0
0.4
V
P
—
324.0
—
mW
Tri-state (high impedance off state) leakage current,
VIN = VDDIO
5
Typical power at 300 MHz
Notes:
1.
2.
3.
4.
5.
The value of VDDM at the MSC7119 device must remain within 50 mV of VDDM at the DRAM device at all times.
VREF must be equal to 50% of VDDM and track VDDM variations as measured at the receiver. Peak-to-peak noise must not
exceed ±2% of the DC value.
VTT is not applied directly to the MSC7119 device. It is the level measured at the far end signal termination. It should be equal
to VREF. This rail should track variations in the DC level of VREF.
Output leakage for the memory interface is measured with all outputs disabled, 0 V ≤ VOUT ≤ VDDM.
The core power values were measured.using a standard EFR pattern at typical conditions (25°C, 300 MHz, 1.2 V core).
Table 6 lists the DDR DRAM capacitance.
Table 6. DDR DRAM Capacitance
Parameter/Condition
Symbol
Max
Unit
Input/output capacitance: DQ, DQS
CIO
30
pF
Delta input/output capacitance: DQ, DQS
CDIO
30
pF
Note:
These values were measured under the following conditions:
• VDDM = 2.5 V ± 0.125 V
• f = 1 MHz
• TA = 25°C
• VOUT = VDDM/2
• VOUT (peak to peak) = 0.2 V
MSC7119 Data Sheet, Rev. 8
20
Freescale Semiconductor
Electrical Characteristics
2.5
AC Timings
This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC
timings are based on a 30 pF load, except where noted otherwise, and a 50 Ω transmission line. For any additional pF, use the
following equations to compute the delay:
— Standard interface: 2.45 + (0.054 × Cload) ns
— DDR interface: 1.6 + (0.002 × Cload) ns
2.5.1
Clock and Timing Signals
The following tables describe clock signal characteristics. Table 6 shows the maximum frequency values for internal (core,
reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency values are not exceeded (see
Section 2.5.2 for the allowable ranges when using the PLL).
Table 6. Maximum Frequencies
Characteristic
Maximum in MHz
Core clock frequency (CLOCK)
300
External output clock frequency (CLKO)
75
Memory clock frequency (CK, CK)
150
TDM clock frequency (TxRCK, TxTCK)
50
Table 7. Clock Frequencies in MHz
Characteristic
Symbol
Min
Max
CLKIN frequency
FCLKIN
10
100
CLOCK frequency
FCORE
—
300
CK, CK frequency
FCK
—
150
FTDMCK
—
50
CLKO frequency
FCKO
—
75
AHB/IPBus/APB clock frequency
FBCK
—
150
TDMxRCK, TDMxTCK frequency
Note:
The rise and fall time of external clocks should be 5 ns maximum
Table 8. System Clock Parameters
Min
Max
Unit
CLKIN frequency
Characteristic
10
100
MHz
CLKIN slope
—
5
ns
CLKIN frequency jitter (peak-to-peak)
—
1000
ps
CLKO frequency jitter (peak-to-peak)
—
150
ps
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
21
Electrical Characteristics
2.5.2
Configuring Clock Frequencies
This section describes important requirements for configuring clock frequencies in the MSC7119 device when using the PLL
block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL):
•
PLLDVF field. Specifies the PLL division factor (PLLDVF + 1) to divide the input clock frequency FCLKIN. The output
of the divider block is the input to the multiplier block.
PLLMLTF field. Specifies the PLL multiplication factor (PLLMLTF + 1). The output from the multiplier block is the
loop frequency FLOOP.
RNG field. Selects the available PLL frequency range for FVCO, either FLOOP when the RNG bit is set (1) or FLOOP/2
when the RNG bit is cleared (0).
CKSEL field. Selects FCLKIN, FVCO, or FVCO/2 as the source for the core clock.
•
•
•
There are restrictions on the frequency range permitted at the beginning of the multiplication portion of the PLL that affect the
allowable values for the PLLDVF and PLLMLTF fields. The following sections define these restrictions and provide guidelines
to configure the device clocking when using the PLL. Refer to the Clock and Power Management chapter in the MSC711x
Reference Manual for details on the clock programming model.
2.5.2.1
PLL Multiplier Restrictions
There are two restrictions for correct usage of the PLL block:
•
•
The input frequency to the PLL multiplier block (that is, the output of the divider) must be in the range 10–25 MHz.
The output frequency of the PLL multiplier must be in the range 266–532 MHz.
When programming the PLL for a desired output frequency using the PLLDVF, PLLMLTF, and RNG fields, you must meet
these constraints.
2.5.2.2
Input Division Factors and Corresponding CLKIN Frequency Range
The value of the PLLDVF field determines the allowable CLKIN frequency range, as shown in Table 9.
Table 9. CLKIN Frequency Ranges by Divide Factor Value
PLLDVF
Field Value
Input Divide
Factor
CLKIN Frequency Range
0x00
1
10 to 25 MHz
Input Division by 1
0x01
2
20 to 50 MHz
Input Division by 2
Comments
0x02
3
30 to 75 MHz
Input Division by 3
0x03
4
40 to 100 MHz
Input Division by 4
0x04
5
50 to 100 MHz
Input Division by 5
0x05
6
60 to 100 MHz
Input Division by 6
0x06
7
70 to 100 MHz
Input Division by 7
0x07
8
80 to 100 MHz
Input Division by 8
0x08
9
90 to 100 MHz
Input Division by 9
0x09
10
100 MHz
Input Division by 10
Note:
The maximum CLKIN frequency is 100 MHz. Therefore, the PLLDVF value must be in the range from 1–10.
MSC7119 Data Sheet, Rev. 8
22
Freescale Semiconductor
Electrical Characteristics
2.5.2.3
Multiplication Factor Range
The multiplier block output frequency ranges depend on the divided input clock frequency as shown in Table 10.
Table 10. PLLMLTF Ranges
Multiplier Block (Loop) Output Range
266 ≤ [Divided Input Clock × (PLLMLTF + 1)] ≤ 532 MHz
Note:
Minimum PLLMLTF Value
Maximum PLLMLTF Value
266/Divided Input Clock
532/Divided Input Clock
This table results from the allowed range for FLoop. The minimum and maximum multiplication factors are dependent on the
frequency of the Divided Input Clock.
2.5.2.4
Allowed Core Clock Frequency Range
The frequency delivered to the core, extended core, and peripherals depends on the value of the CLKCTRL[RNG] bit as shown
in Table 11.
Table 11. Fvco Frequency Ranges
CLKCTRL[RNG] Value
Allowed Range of Fvco
1
266 ≤ Fvco ≤ 532 MHz
0
133 ≤ Fvco ≤ 266 MHz
Note:
This table results from the allowed range for Fvco, which is FLoop modified by CLKCTRL[RNG].
This bit along with the CKSEL determines the frequency range of the core clock.
Table 12. Resulting Ranges Permitted for the Core Clock
CLKCTRL[CKSEL]
CLKCTRL[RNG]
Resulting
Division
Factor
Allowed Range
of Core Clock
11
1
1
266 ≤ core clock ≤ 300 MHz
Limited by maximum core
frequency
11
0
2
133 ≤ core clock ≤ 266 MHz
Limited by range of PLL
01
1
2
133 ≤ core clock ≤ 266 MHz
Limited by range of PLL
01
0
4
66.5 ≤ core clock ≤ 133 MHz
Limited by range of PLL
Note:
Comments
This table results from the allowed range for FOUT, which depends on clock selected via CLKCTRL[CKSEL].
2.5.2.5
Core Clock Frequency Range When Using DDR Memory
The core clock can also be limited by the frequency range of the DDR devices in the system. Table 13 summarizes this
restriction.
Table 13. Core Clock Ranges When Using DDR
DDR Type
Allowed Frequency
Range for DDR CK
Corresponding Range
for the Core Clock
Comments
DDR 200 (PC-1600)
83–100 MHz
166 ≤ core clock ≤ 200 MHz
Core limited to 2 × maximum DDR frequency
DDR 266 (PC-2100)
83–133 MHz
166 ≤ core clock ≤ 266 MHz
Core limited to 2 × maximum DDR frequency
DDR 333 (PC-2600)
83–150 MHz
166 ≤ core clock ≤ 300 MHz
Core limited to 2 × maximum DDR frequency
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
23
Electrical Characteristics
2.5.3
Reset Timing
The MSC7119 device has several inputs to the reset logic. All MSC7119 reset sources are fed into the reset controller, which
takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause
a reset. Table 14 describes the reset sources.
Table 14. Reset Sources
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC7119 and configures various attributes of the
MSC7119. On PORESET, the entire MSC7119 device is reset. SPLL and DLL states are reset,
HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The
system is configured only when PORESET is asserted.
External Hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC7119. While HRESET is
asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400
extended core is reset.
Software
watchdog reset
Internal
When the MSC7119 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor
reset
Internal
When the MSC7119 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
JTAG EXTEST,
CLAMP, or
HIGHZ command
Internal
When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic
asserts an internal reset signal that generates an internal soft reset sequence.
Table 15 summarizes the reset actions that occur as a result of the different reset sources.
Table 15. Reset Actions for Each Reset Source
Power-On Reset
(PORESET)
Hard Reset
(HRESET)
Soft Reset
(SRESET)
External only
External or
Internal (Software
Watchdog or Bus
Monitor)
JTAG Command:
EXTEST, CLAMP,
or HIGHZ
Configuration pins sampled (refer to Section 2.5.3.1 for
details).
Yes
No
No
PLL and clock synthesis states Reset
Yes
No
No
HRESET Driven
Yes
Yes
No
Software watchdog and bus time-out monitor registers
Yes
Yes
Yes
Clock synthesis modules (STOPCTRL, HLTREQ, and
HLTACK) reset
Yes
Yes
Yes
Extended core reset
Yes
Yes
Yes
Peripheral modules reset
Yes
Yes
Yes
Reset Action/Reset Source
2.5.3.1
Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
external power to the MSC7119 reaches at least 2/3 VDD.
MSC7119 Data Sheet, Rev. 8
24
Freescale Semiconductor
Electrical Characteristics
2.5.3.2
Reset Configuration
The MSC7119 has two mechanisms for writing the reset configuration:
•
•
From a host through the host interface (HDI16)
From memory through the I2C interface
Five signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the boot and
operating conditions:
•
•
•
•
BM[0–1]
SWTE
H8BIT
HDSP
2.5.3.3
Reset Timing Tables
Table 16 and Figure 4 describe the reset timing for a reset configuration write.
Table 16. Timing for a Reset Configuration Write
No.
Characteristics
Expression
Unit
1
Required external PORESET duration minimum
16/FCLKIN
clocks
2
Delay from PORESET deassertion to HRESET deassertion
521/FCLKIN
clocks
Note:
Timings are not tested, but are guaranteed by design.
1
PORESET
Input
Configuration Pins
are sampled
PORESET
Internal
HRESET
Output(I/O)
2
Figure 4. Timing Diagram for a Reset Configuration Write
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
25
Electrical Characteristics
2.5.4
DDR DRAM Controller Timing
This section provides the AC electrical characteristics for the DDR DRAM interface.
2.5.4.1
DDR DRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR DRAM interface.
Table 17. DDR DRAM Input AC Timing
No.
Parameter
Symbol
Min
Max
Unit
—
AC input low voltage
VIL
—
VREF – 0.31
V
—
AC input high voltage
VIH
VREF + 0.31
VDDM + 0.3
V
201
Maximum Dn input setup skew relative to DQSn input
—
—
900
ps
202
Maximum Dn input hold skew relative to DQSn input
—
—
900
ps
Notes:
1.
2.
3.
Maximum possible skew between a data strobe (DQSn) and any corresponding bit of data (D[8n + {0...7}] if 0 ≤ n ≤ 7).
See Table 18 for tCK value.
Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is
done internally.
DQSn
202
202
D0
Dn
D1
201
Note: DQS centering is done internally.
201
Figure 5. DDR DRAM Input Timing Diagram
2.5.4.2
DDR DRAM Output AC Timing Specifications
Table 18 and Table 19 list the output AC timing specifications and measurement conditions for the DDR DRAM
interface.
Table 18. DDR DRAM Output AC Timing
No.
200
Parameter
Symbol
CK cycle time, (CK/CK crossing)1
• 100 MHz (DDR200)
• 150 MHz (DDR300)
Min
Max
Unit
10
6.67
—
—
ns
ns
tCK
204
An/RAS/CAS/WE/CKE output setup with respect to CK
tDDKHAS
0.5 × tCK – 1000
—
ps
205
An/RAS/CAS/WE/CKE output hold with respect to CK
tDDKHAX
0.5 × tCK – 1000
—
ps
206
CSn output setup with respect to CK
tDDKHCS
0.5 × tCK – 1000
—
ps
207
CSn output hold with respect to CK
tDDKHCX
0.5 × tCK – 1000
—
ps
208
CK to DQSn2
tDDKHMH
–600
600
ps
MSC7119 Data Sheet, Rev. 8
26
Freescale Semiconductor
Electrical Characteristics
Table 18. DDR DRAM Output AC Timing (continued)
No.
Parameter
Symbol
Min
Max
Unit
209
Dn/DQMn output setup with respect to DQSn3
tDDKHDS,
tDDKLDS
0.25 × tCK – 750
—
ps
210
Dn/DQMn output hold with respect to DQSn3
tDDKHDX,
tDDKLDX
0.25 × tCK – 750
—
ps
211
DQSn preamble start4
tDDKHMP
–0.25 × tCK
—
ps
212
DQSn epilogue end5
tDDKHME
–600
600
ps
Notes:
1.
2.
3.
4.
5.
All CK/CK referenced measurements are made from the crossing of the two signals ±0.1 V.
tDDKHMH can be modified through the TCFG2[WRDD] DQSS override bits. The DRAM requires that the first write data strobe
arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered
when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle
increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing
occurs in the middle of the control signal (An/RAS/CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal
assertion 1/2 DRAM cycle earlier than the default timing. This means that the signal is asserted no earlier than 600 ps before
the CK/CK crossing and no later than 600 ps after the crossing time; the device uses 1200 ps of the skew budget (the interval
from –600 to +600 ps). Timing is verified by referencing the falling edge of CK. See Chapter 10 of the MSC711x Reference
Manual for details.
Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe
should be centered inside of the data eye.
Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to
programmable delay of the write strobes (TCFG2[WRDD]), there pre-amble may be extended for a full DRAM cycle. For this
reason, we reference from DQSn.
All outputs are referenced to the rising edge of CK. Note that this is essentially the CK/DQSn skew in spec 208. In addition
there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the
chip to guarantee fast enough write-to-read turn-around times. This is already guaranteed by the memory controller operation.
Figure 6 shows the DDR DRAM output timing diagram.
CK
CK
200
204
An
RAS
CAS
WE
CKE
DQMn
206
205
207
Write A0
NOOP
211
208
DQSn
212
209
209
Dn
D0
D1
210
210
Figure 6. DDR DRAM Output Timing Diagram
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
27
Electrical Characteristics
Figure 7 provides the AC test load for the DDR DRAM bus.
Output
VOUT
Z0 = 50 Ω
RL = 50 Ω
Figure 7. DDR DRAM AC Test Load
Table 19. DDR DRAM Measurement Conditions
Symbol
VTH1
VOUT
2
Notes:
1.
2.
2.5.5
DDR DRAM
Unit
VREF ± 0.31 V
V
0.5 × VDDM
V
Data input threshold measurement point.
Data output measurement point.
TDM Timing
Table 20. TDM Timing
No.
Characteristic
Expression
Min
Max
Units
TC
20.0
—
ns
TDMxRCK/TDMxTCK High Pulse Width
0.4 × TC
8.0
—
ns
302
TDMxRCK/TDMxTCK Low Pulse Width
0.4 × TC
8.0
—
ns
303
TDM all input Setup time
3.0
—
ns
300
TDMxRCK/TDMxTCK
301
304
TDMxRD Hold time
3.5
—
ns
305
TDMxTFS/TDMxRFS input Hold time
2.0
—
ns
306
TDMxTCK High to TDMxTD output active
4.0
—
ns
307
TDMxTCK High to TDMxTD output valid
—
14.0
ns
308
TDMxTD hold time
2.0
—
ns
309
TDMxTCK High to TDMxTD output high impedance
—
10.0
ns
310
TDMxTFS/TDMxRFS output valid
—
13.5
ns
311
TDMxTFS/TDMxRFS output hold time
2.5
—
ns
Notes:
1.
2.
Output values are based on 30 pF capacitive load.
Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge
they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. Refer to the MSC711x
Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge.
300
302
301
TDMxRCK
303
304
TDMxRD
305
303
TDMxRFS
310
~
~
TDMxRFS (output)
311
Figure 8. TDM Receive Signals
MSC7119 Data Sheet, Rev. 8
28
Freescale Semiconductor
Electrical Characteristics
300
302
301
TDMxTCK
309
306
TDMxTD
TDMxRCK
310
TDMxTFS (output)
305
303
~
~ ~
~
307
308
311
TDMxTFS (input)
Figure 9. TDM Transmit Signals
2.5.6
2.5.6.1
Ethernet Timing
Receive Signal Timing
Table 21. Receive Signal Timing
No.
Min
Max
Unit
Receive clock period:
• MII: RXCLK (max frequency = 25 MHz)
• RMII: REFCLK (max frequency = 50 MHz)
40
20
—
—
ns
ns
801
Receive clock pulse width high—as a percent of clock period
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
802
Receive clock pulse width low—as a percent of clock period:
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
800
Characteristics
803
RXDn, RX_DV, CRS_DV, RX_ER to receive clock rising edge setup time
4
—
ns
804
Receive clock rising edge to RXDn, RX_DV, CRS_DV, RX_ER hold time
2
—
ns
800
801
802
Receive
clock
RXDn
RX_DV
CRS_DV
RX_ER
803
804
Valid
Figure 10. Ethernet Receive Signal Timing
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
29
Electrical Characteristics
2.5.6.2
Transmit Signal Timing
Table 22. Transmit Signal Timing
No.
Min
Max
Unit
Transmit clock period:
• MII: TXCLK
• RMII: REFCLK
40
20
—
—
ns
ns
801
Transmit clock pulse width high—as a percent of clock period
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
802
Transmit clock pulse width low—as a percent of clock period:
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
800
Characteristics
805
Transmit clock to TXDn, TX_EN, TX_ER invalid
4
—
ns
806
Transmit clock to TXDn, TX_EN, TX_ER valid
—
14
ns
Min
Max
Unit
60
30
—
—
ns
ns
800
801
Transmit
clock
802
806
805
TXDn
TX_EN
TX_ER
Valid
Figure 11. Ethernet Receive Signal Timing
2.5.6.3
Asynchronous Input Signal Timing
Table 23. Asynchronous Input Signal Timing
No.
807
Characteristics
• MII: CRS and COL minimum pulse width (1.5 × TXCLK period)
• RMII: CRS_DV minimum pulse width (1.5 x REFCLK period)
CRS
COL
CRS_DV
807
Figure 12. Asynchronous Input Signal Timing
MSC7119 Data Sheet, Rev. 8
30
Freescale Semiconductor
Electrical Characteristics
2.5.6.4
Management Interface Timing
Table 24. Ethernet Controller Management Interface Timing
No.
Characteristics
Min
Max
Unit
808
MDC period
400
—
ns
809
MDC pulse width high
160
—
ns
810
MDC pulse width low
160
—
ns
811
MDS falling edge to MDIO output invalid (minimum propagation delay)
0
—
ns
812
MDS falling edge to MDIO output valid (maximum propagation delay)
—
15
ns
813
MDIO input to MDC rising edge setup time
10
—
ns
814
MDC rising edge to MDIO input hold time
10
—
ns
808
809
810
MDC (output)
811
MDIO (output)
812
813
814
MDIO (input)
Figure 13. Serial Management Channel Timing
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
31
Electrical Characteristics
2.5.7
HDI16 Signals
Table 25. Host Interface (HDI16) Timing1, 2
No.
40
44a
44b
44c
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
62
63
64
Notes:
Characteristics3
Expression
Value
Unit
Host Interface Clock period
TCORE
Note 1
ns
Read data strobe minimum assertion width4
Note 11
ns
2.0 × TCORE + 9.0
HACK read minimum assertion width
1.5 × TCORE
Note 11
ns
Read data strobe minimum deassertion width4
HACK read minimum deassertion width
2.5 × TCORE
Note 11
ns
Read data strobe minimum deassertion width4 after “Last Data Register”
reads5,6, or between two consecutive CVR, ICR, or ISR reads7
HACK minimum deassertion width after “Last Data Register” reads5,6
1.5 × TCORE
Note 11
ns
Write data strobe minimum assertion width8
HACK write minimum assertion width
Write data strobe minimum deassertion width8
HACK write minimum deassertion width after ICR, CVR and Data Register
writes5
2.5 × TCORE
Note 11
ns
Host data input minimum setup time before write data strobe deassertion8
—
2.5
ns
Host data input minimum setup time before HACK write deassertion
Host data input minimum hold time after write data strobe deassertion8
—
2.5
ns
Host data input minimum hold time after HACK write deassertion
Read data strobe minimum assertion to output data active from high
impedance4
HACK read minimum assertion to output data active from high impedance
—
1.0
ns
Read data strobe maximum assertion to output data valid4
(2.0 × TCORE) + 8.0
Note 11
ns
HACK read maximum assertion to output data valid
Read data strobe maximum deassertion to output data high impedance4
HACK read maximum deassertion to output data high impedance
—
9.0
ns
Output data minimum hold time after read data strobe deassertion4
—
1.0
ns
Output data minimum hold time after HACK read deassertion
HCS[1–2] minimum assertion to read data strobe assertion4
—
0.5
ns
HCS[1–2] minimum assertion to write data strobe assertion8
—
0.0
ns
HCS[1–2] maximum assertion to output data valid
(2.0 × TCORE) + 6.0
Note 11
ns
—
0.5
ns
HCS[1–2] minimum hold time after data strobe deassertion9
HA[0–2], HRW minimum setup time before data strobe assertion9
—
5.0
ns
HA[0–2], HRW minimum hold time after data strobe deassertion9
—
5.0
ns
Maximum delay from read data strobe deassertion to host request
(3.0 × TCORE) + 6.0
Note 11
ns
deassertion for “Last Data Register” read4, 5, 10
Maximum delay from write data strobe deassertion to host request
deassertion for “Last Data Register” write5,8,10
(3.0 × TCORE) + 6.0
Note 11
ns
Minimum delay from DMA HACK (OAD=0) or Read/Write data
(2.0 × TCORE) + 1.0
Note 11
ns
strobe(OAD=1) deassertion to HREQ assertion.
Maximum delay from DMA HACK (OAD=0) or Read/Write data
(5.0 × TCORE) + 6.0
Note 11
ns
strobe(OAD=1) assertion to HREQ deassertion
1. TCORE = core clock period. At 300 MHz, TCORE = 3.333 ns.
2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3. VDD = 3.3 V ± 0.15 V; TJ = –40°C to +105 °C, C L = 30 pF for maximum delay timings and CL = 0 pF for minimum delay timings.
4. The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.
5. For 64-bit transfers, the “last data register” is the register at address 0x7, which is the last location to be read or written in data
transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).
6. This timing is applicable only if a read from the “last data register” is followed by a read from the RX[0–3] registers without first
polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.
7. This timing is applicable only if two consecutive reads from one of these registers are executed.
8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe
(HDS/HDS) in the single data strobe mode.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host
request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full
11. Compute the value using the expression.
12. The read and write data strobe minimum deassertion width for non-”last data register” accesses in single and dual data strobe
modes is based on timings 57 and 58.
MSC7119 Data Sheet, Rev. 8
32
Freescale Semiconductor
Figure 14 and Figure 15 show HDI16 read signal timing. Figure 16 and Figure 17 show HDI16 write signal timing.
HA[0–2]
57
58
56
53
HCS[1–2]
57
58
HRW
44a
HDS
44b
51
55
44c
50
52
49
HD[0–15]
61
HREQ (single host request)
HRRQ (double host request)
Figure 14. Read Timing Diagram, Single Data Strobe
HA[0–2]
57
58
56
53
HCS[1–2]
44a
HRD
44b
51
55
44a
50
52
49
HD[0–15]
61
HREQ (single host request)
HRRQ (double host request)
Figure 15. Read Timing Diagram, Double Data Strobe
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
33
HA[0–2]
57
58
56
54
HCS[1–2]
57
58
HRW
45
HDS
46
47
48
HD[0–15]
62
HREQ (single host request)
HTRQ (double host request)
Figure 16. Write Timing Diagram, Single Data Strobe
HA[0–2]
57
58
56
54
HCS[1–2]
45
HWR
46
48
47
HD[0–15]
62
HREQ (single host request)
HTRQ (double host request)
Figure 17. Write Timing Diagram, Double Data Strobe
MSC7119 Data Sheet, Rev. 8
34
Freescale Semiconductor
HREQ
(Output)
63
64
44a
44b
RX[0–3]
HACK
Read
51
50
49
52
Data
Valid
HD[0–15]
(Output)
Figure 18. Host DMA Read Timing Diagram, HPCR[OAD] = 0
HREQ
(Output)
63
64
46
45
HACK
TX[0–3]
Write
47
48
HD[0–15]
(Input)
Data
Valid
Figure 19. Host DMA Write Timing Diagram, HPCR[OAD] = 0
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
35
2.5.8
I2C Timing
Table 26. I2C Timing
Fast
No.
Characteristic
Unit
Min
Max
0
400
kHz
450
SCL clock frequency
451
Hold time START condition
(SCL clock period/2) – 0.3
—
µs
452
SCL low period
(SCL clock period/2) – 0.3
—
µs
453
SCL high period
(SCL clock period/2) – 0.1
—
µs
454
Repeated START set-up time (not shown in figure)
2 × 1/FBCK
—
µs
455
Data hold time
0
—
µs
456
Data set-up time
250
—
ns
457
SDA and SCL rise time
—
700
ns
458
SDA and SCL fall time
—
300
ns
459
Set-up time for STOP
(SCL clock period/2) – 0.7
—
µs
460
Bus free time between STOP and START
(SCL clock period/2) – 0.3
—
µs
Note:
SDA set-up time is referenced to the rising edge of SCL. SDA hold time is referenced to the falling edge of SCL. Load capacitance
on SDA and SCL is 400 pF.
453
458
Start Condition
1
SCL
2
3
457
4
452
451
SDA
5
6
7
8
Stop Condition
Start Condition
9
A
C
K
Data Byte
457
458
459
460
Start Condition
SCL
SDA
Data Byte
Figure 20. I2C Timing Diagram
MSC7119 Data Sheet, Rev. 8
36
Freescale Semiconductor
2.5.9
UART Timing
Table 27. UART Timing
No.
Characteristics
Expression
Min
Max
Unit
—
Internal bus clock (APBCLK)
FCORE/2
—
150
MHz
—
Internal bus clock period (1/APBCLK)
TAPBCLK
6.67
—
ns
16 × TAPBCLK
106.67
—
ns
400
URXD and UTXD inputs high/low duration
401
URXD and UTXD inputs rise/fall time
—
5
ns
402
UTXD output rise/fall time
—
5
ns
401
401
UTXD, URXD
inputs
400
400
Figure 21. UART Input Timing
402
402
UTXD Output
Figure 22. UART Output Timing
2.5.10
EE Timing
Table 28. EE0 Timing
Number
Notes:
Characteristics
65
EE0 input to the core
66
EE0 output from the core
1.
2.
3.
Type
Min
Asynchronous
4 core clock periods
Synchronous to core clock
1 core clock period
The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details.
Refer to Table 1-11 on page 1-16 for details on EE pin functionality.
Figure 24 shows the signal behavior of the EE pin.
65
EE0 In
66
EE0 Out
Figure 23. EE Pin Timing
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
37
2.5.11
Event Timing
Table 29. EVNT Signal Timing
Number
Characteristics
67
EVNT as input
68
EVNT as output
Notes:
1.
2.
3.
Type
Min
Asynchronous
1.5 × APBCLK periods
Synchronous to core clock
1 APBCLK period
Refer to Table 27 for a definition of the APBCLK period.
Direction of the EVNT signal is configured through the GPIO and Event port registers.
Refer to the signal chapter in the MSC711x Reference Manual for details on EVNT pin functionality.
Figure 24 shows the signal behavior of the EVNT pins.
67
EVNT in
68
EVNT out
Figure 24. EVNT Pin Timing
2.5.12
GPIO Timing
Table 30. GPIO Signal Timing1,2,3
Number
Notes:
Type
Min
601
GPI4.5
Asynchronous
1.5 × APBCLK periods
602
GPO5
Synchronous to core clock
1 APBCLK period
603
Port A edge-sensitive interrupt
Asynchronous
1.5 × APBCLK periods
604
Port A level-sensitive interrupt
Asynchronous
3 × APBCLK periods6
1.
2.
3.
4.
5.
6.
Characteristics
Refer to Table 27 for a definition of the APBCLK period.
Direction of the GPIO signal is configured through the GPIO port registers.
Refer to Section 1.5 for details on GPIO pin functionality.
GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data
into a register when the GPADR is read. The specification is not tested due to the asynchronous nature of the input and
dependence on the state of the DSP core. It is guaranteed by design.
The output signals cannot toggle faster than 75 MHz.
Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is
acknowledged.
Figure 25 shows the signal behavior of the GPI/GPO pins.
601
GPI
602
GPO
Figure 25. GPI/GPO Pin Timing
MSC7119 Data Sheet, Rev. 8
38
Freescale Semiconductor
2.5.13
JTAG Signals
Table 31. JTAG Timing
All frequencies
No.
Characteristics
Unit
Min
Max
700
TCK frequency of operation (1/(TC × 3)
Note:
TC = 1/CLOCK which is the period of the core clock. The TCK
frequency must less than 1/3 of the core frequency with an absolute
maximum limit of 40 MHz.
0.0
40.0
MHz
701
TCK cycle time
25.0
—
ns
702
TCK clock pulse width measured at VM = 1.6 V
11.0
—
ns
703
TCK rise and fall times
0.0
3.0
ns
704
Boundary scan input data set-up time
5.0
—
ns
705
Boundary scan input data hold time
14.0
—
ns
706
TCK low to output data valid
0.0
20.0
ns
707
TCK low to output high impedance
0.0
20.0
ns
708
TMS, TDI data set-up time
5.0
—
ns
709
TMS, TDI data hold time
14.0
—
ns
710
TCK low to TDO data valid
0.0
24.0
ns
711
TCK low to TDO high impedance
0.0
10.0
ns
712
TRST assert time
100.0
—
ns
Note:
All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface.
701
702
TCK
(Input)
VIH
VM
VM
VIL
703
703
Figure 26. Test Clock Input Timing Diagram
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
39
VIH
TCK
(Input)
VIL
704
Data
Inputs
705
Input Data Valid
706
Data
Outputs
Output Data Valid
707
Data
Outputs
Figure 27. Boundary Scan (JTAG) Timing Diagram
TCK
(Input)
VIH
VIL
708
TDI
TMS
(Input)
709
Input Data Valid
710
TDO
(Output)
Output Data Valid
711
TDO
(Output)
Figure 28. Test Access Port Timing Diagram
TRST
(Input)
712
Figure 29. TRST Timing Diagram
MSC7119 Data Sheet, Rev. 8
40
Freescale Semiconductor
Hardware Design Considerations
3
Hardware Design Considerations
This section described various areas to consider when incorporating the MSC7119 device into a system design.
3.1
Thermal Design Considerations
An estimation of the chip-junction temperature, TJ, in °C can be obtained from the following:
TJ = TA + (RθJA × PD)
Eqn. 1
where
TA = ambient temperature near the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = PINT + PI/O = power dissipation in the package (W)
PINT = IDD × VDD = internal power dissipation (W)
PI/O = power dissipated from device on output pins (W)
The power dissipation values for the MSC7119 are listed in Table 4. The ambient temperature for the device is the air
temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC
standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the
value determined on a single layer board and the value obtained on a board with two planes. The value that more closely
approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB).
The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a
board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural
convection) and well separated components. Based on an estimation of junction temperature using this technique, determine
whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the
device thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient temperature or
the power dissipation of the chip.
You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is
recommended) or an infrared temperature sensor on a spot on the device case. Use the following equation to determine TJ:
TJ = TT + (ΨJT × PD)
Eqn. 2
where
TT = thermocouple (or infrared) temperature on top of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
41
Hardware Design Considerations
3.2
Power Supply Design Considerations
This section outlines the MSC7119 power considerations: power supply, power sequencing, power planes, decoupling, power
supply filtering, and power consumption. It also presents a recommended power supply design and options for low-power
consumption. For information on AC/DC electrical specifications and thermal characteristics, refer to Section 2.
3.2.1
Power Supply
The MSC7119 requires four input voltages, as shown in Table 32.
Table 32. MSC7119 Voltages
Voltage
Symbol
Value
Core
VDDC
1.2 V
Memory
VDDM
2.5 V
Reference
VREF
1.25 V
I/O
VDDIO
3.3 V
You should supply the MSC7119 core voltage via a variable switching supply or regulator to allow for compatibility with
possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across VDDC
and GND and the I/O section is supplied with 3.3 V (± 10%) across VDDIO and GND. The memory and reference voltages supply
the DDR memory controller block. The memory voltage is supplied with 2.5 V across VDDM and GND. The reference voltage
is supplied across VREF and GND and must be between 0.49 × VDDM and 0.51 × VDDM. Refer to the JEDEC standard JESD8
(Stub Series Terminated Logic for 2.5 Volts (STTL_2)) for memory voltage supply requirements.
3.2.2
Power Sequencing
One consequence of multiple power supplies is that the voltage rails ramp up at different rates when power is initially applied.
The rates depend on the power supply, the type of load on each power supply, and the way different voltages are derived. It is
extremely important to observe the power up and power down sequences at the board level to avoid latch-up, forward biasing
of ESD devices, and excessive currents, which all lead to severe device damage.
Note:
There are five possible power-up/power-down sequence cases. The first four cases listed in the following sections are
recommended for new designs. The fifth case is not recommended for new designs and must be carefully evaluated
for current spike risks based on actual information for the specific application.
MSC7119 Data Sheet, Rev. 8
42
Freescale Semiconductor
Hardware Design Considerations
3.2.2.1
Case 1
The power-up sequence is as follows:
1.
2.
3.
4.
Turn on the VDDIO (3.3 V) supply first.
Turn on the VDDC (1.2 V) supply second.
Turn on the VDDM (2.5 V) supply third.
Turn on the VREF (1.25 V) supply fourth (last).
The power-down sequence is as follows:
1.
2.
3.
4.
Turn off the VREF (1.25 V) supply first.
Turn off the VDDM (2.5 V) supply second.
Turn off the VDDC (1.2 V) supply third.
Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
•
•
•
Make sure that the time interval between the ramp-down of VDDIO and VDDC is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for
power-up and power-down.
Refer to Figure 30 for relative timing for power sequencing case 1.
Ramp-down
Ramp-up
VDDIO = 3.3 V
Voltage
VDDM = 2.5 V
VREF = 1.25 V
VDDC = 1.2 V
<10 ms
<10 ms
<10 ms
<10 ms
Time
Figure 30. Voltage Sequencing Case 1
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
43
Hardware Design Considerations
3.2.2.2
Case 2
The power-up sequence is as follows:
1.
2.
3.
Note:
Turn on the VDDIO (3.3 V) supply first.
Turn on the VDDC (1.2 V) and VDDM (2.5 V) supplies simultaneously (second).
Turn on the VREF (1.25 V) supply last (third).
Make sure that the time interval between the ramp-up of VDDIO and VDDC/VDDM is less than 10 ms.
The power-down sequence is as follows:
1.
2.
3.
4.
Turn off the VREF (1.25 V) supply first.
Turn off the VDDM (2.5 V) supply second.
Turn off the VDDC (1.2 V) supply third.
Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
•
•
•
Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for
power-up and power-down.
Refer to Figure 31 for relative timing for Case 2.
Ramp-down
Ramp-up
VDDIO = 3.3 V
Voltage
VDDM = 2.5 V
VREF = 1.25 V
VDDC = 1.2 V
<10 ms
<10 ms
<10 ms
Time
Figure 31. Voltage Sequencing Case 2
MSC7119 Data Sheet, Rev. 8
44
Freescale Semiconductor
Hardware Design Considerations
3.2.2.3
Case 3
The power-up sequence is as follows:
1.
2.
3.
Note:
Turn on the VDDIO (3.3 V) supply first.
Turn on the VDDC (1.2 V) supply second.
Turn on the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (third).
Make sure that the time interval between the ramp-up of VDDIO and VDDC is less than 10 ms.
The power-down sequence is as follows:
1.
2.
3.
Turn off the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (first).
Turn off the VDDC (1.2 V) supply second.
Turn of the VDDIO (3.3 V) supply third (last).
Use the following guidelines:
•
•
•
Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down time for VDDC and VDDM is less than 10 ms for
power-up and power-down.
Refer to Figure 32 for relative timing for Case 3.
Ramp-down
Ramp-up
VDDIO = 3.3 V
Voltage
VDDM = 2.5 V
VREF = 1.25 V
VDDC = 1.2 V
<10 ms
<10 ms
<10 ms
<10 ms
Time
Figure 32. Voltage Sequencing Case 3
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
45
Hardware Design Considerations
3.2.2.4
Case 4
The power-up sequence is as follows:
1.
2.
Note:
Turn on the VDDIO (3.3 V) supply first.
Turn on the VDDC (1.2 V), VDDM (2.5 V), and VREF (1.25 V) supplies simultaneously (second).
Make sure that the time interval between the ramp-up of VDDIO and VDDC is less than 10 ms.
The power-down sequence is as follows:
1.
2.
Turn off the VDDC (1.2 V), VREF (1.25 V), and VDDM (2.5 V) supplies simultaneously (first).
Turn of the VDDIO (3.3 V) supply last.
Use the following guidelines:
•
•
Make sure that the time interval between the ramp-up or ramp-down time for VDDC and VDDM is less than 10 ms for
power-up and power-down.
Refer to Figure 33 for relative timing for Case 4.
Ramp-down
Ramp-up
VDDIO = 3.3 V
Voltage
VDDM = 2.5 V
VREF = 1.25 V
VDDC = 1.2 V
<10 ms
<10 ms
Time
Figure 33. Voltage Sequencing Case 4
MSC7119 Data Sheet, Rev. 8
46
Freescale Semiconductor
Hardware Design Considerations
3.2.2.5
Case 5 (not recommended for new designs)
The power-up sequence is as follows:
1.
2.
3.
4.
Note:
Turn on the VDDIO (3.3 V) supply first.
Turn on the VDDM (2.5 V) supply second.
Turn on the VDDC (1.2 V) supply third.
Turn on the VREF (1.25 V) supply fourth (last).
Make sure that the time interval between the ramp-up of VDDIO and VDDM is less than 10 ms.
The power-down sequence is as follows:
1.
2.
3.
4.
Turn off the VREF (1.25 V) supply first.
Turn off the VDDC (1.2 V) supply second.
Turn off the VDDM (2.5 V) supply third.
Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
•
•
•
Make sure that the time interval between the ramp-down of VDDIO and VDDM is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 2 ms for
power-up and power-down.
Refer to Figure 34 for relative timing for power sequencing case 5.
Ramp-down
Ramp-up
VDDIO = 3.3 V
Voltage
VDDM = 2.5 V
VREF = 1.25 V
VDDC = 1.2 V
<2 ms
<2 ms
<10 ms
<10 ms
Time
Figure 34. Voltage Sequencing Case 5
Note:
Cases 1, 2, 3, and 4 are recommended for system design. Designs that use Case 5 may have large current spikes on
the VDDM supply at startup and is not recommended for most designs. If a design uses case 5, it must accommodate
the potential current spikes. Verify risks related to current spikes using actual information for the specific application.
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
47
Hardware Design Considerations
3.2.3
Power Planes
Each power supply pin (VDDC, VDDM, and VDDIO) should have a low-impedance path to the board power supply. Each GND pin
should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the device.
The MSC7119 VDDC power supply pins should be bypassed to ground using decoupling capacitors. The capacitor leads and
associated printed circuit traces connecting to device power pins and GND should be kept to less than half an inch per capacitor
lead. A minimum four-layer board that employs two inner layers as power and GND planes is recommended. See Section 3.5
for DDR Controller power guidelines.
3.2.4
Decoupling
Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use standard capacitor
values of 0.01 µF for every two to three voltage pins. For core voltage decoupling, use two levels of decoupling. The first level
should consist of a 0.01 µF high frequency capacitor with low effective series resistance (ESR) and effective series inductance
(ESL) for every two to three voltage pins. The second decoupling level should consist of two bulk/tantalum decoupling
capacitors, one 10 µF and one 47 µF, (with low ESR and ESL) mounted as closely as possible to the MSC7119 voltage pins.
Additionally, the maximum drop between the power supply and the DSP device should be 15 mV at 1 A.
3.2.5
PLL Power Supply Filtering
The MSC7119 VDDPLL power signal provides power to the clock generation PLL. To ensure stability of the internal clock, the
power supplied to this pin should be filtered with capacitors that have low and high frequency filtering characteristics. VDDPLL
can be connected to VDDC through a 2 Ω resistor. VSSPLL can be tied directly to the GND plane. A circuit similar to the one
shown in Figure 35 is recommended. The PLL loop filter should be placed as closely as possible to the VDDPLL pin (which are
located on the outside edge of the silicon package) to minimize noise coupled from nearby circuits.The 0.01 µF capacitor should
be closest to VDDPLL, followed by the 0.1 µF capacitor, the 10 µF capacitor, and finally the 2-Ω resistor to VDDC. These traces
should be kept short.
2Ω
VDDC
VDDPLL
10 µF
0.1 µF 0.01 µF
Figure 35. PLL Power Supply Filter Circuits
3.2.6
Power Consumption
You can reduce power consumption in your design by controlling the power consumption of the following regions of the device:
•
•
•
•
Extended core. Use the SC1400 Stop and Wait modes by issuing a stop or wait instruction.
Clock synthesis module. Disable the PLL, timer, watchdog, or DDR clocks or disable the CLKO pin.
AHB subsystem. Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit.
Peripheral subsystem. Halt the individual on-device peripherals such as the DDR memory controller, Ethernet MAC,
HDI16, TDM, UART, I2C, and timer modules.
For details, see the “Clocks and Power Management” chapter of the MSC711x Reference Manual.
MSC7119 Data Sheet, Rev. 8
48
Freescale Semiconductor
Hardware Design Considerations
3.2.7
Power Supply Design
One of the most common ways to derive power is to use either a simple fixed or adjustable linear regulator. For the system I/O
voltage supply, a simple fixed 3.3 V supply can be used. However, a separate adjustable linear regulator supply for the core
voltage VDDC should be implemented. For the memory power supply, regulators are available that take care of all DDR power
requirements.
Table 33. Recommended Power Supply Ratings
Supply
Symbol
Nominal Voltage
Current Rating
Core
VDDC
1.2 V
1.5 A per device
Memory
VDDM
2.5 V
0.5 A per device
Reference
VREF
1.25 V
10 µA per device
I/O
VDDIO
3.3 V
1.0 A per device
3.3
Estimated Power Usage Calculations
The following equations permit estimated power usage to be calculated for individual design conditions. Overall power is
derived by totaling the power used by each of the major subsystems:
PTOTAL = PCORE + PPERIPHERALS + PDDRIO + PIO + PLEAKAGE
Eqn. 3
This equation combines dynamic and static power. Dynamic power is determined using the generic equation:
C × V2 × F × 10–3 mW
Eqn. 4
where,
C = load capacitance in pF
V = peak-to-peak voltage swing in V
F = frequency in MHz
3.3.1
Core Power
Estimation of core power is straightforward. It uses the generic dynamic power equation and assumes that the core load
capacitance is 750 pF, core voltage swing is 1.2 V, and the core frequency is 300 MHz. This yields:
PCORE = 750 pF × (1.2 V)2 × 300 MHz × 10–3 = 324.0 mW
Eqn. 5
This equation allows for adjustments to voltage and frequency if necessary.
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
49
Hardware Design Considerations
3.3.2
Peripheral Power
Peripherals include the DDR memory controller, Ethernet controller, DMA controller, HDI16, TDM, UART, timers, GPIOs,
and the I2C module. Basic power consumption by each module is assumed to be the same and is computed by using the
following equation which assumes an effective load of 20 pF, core voltage swing of 1.2 V, and a switching frequency of 100
MHz. This yields:
PPERIPHERAL = 20 pF × (1.2 V)2 × 150 MHz × 10–3 = 4.32 mW per peripheral
Eqn. 6
Multiply this value by the number of peripherals used in the application to compute the total peripheral power consumption.
3.3.3
External Memory Power
Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage,
termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7119
device, the 2.5 V power source provides the power for the termination, which is a static value of 16 mA per signal driven high.
The dynamic power is computed, however, using a differential voltage swing of ±0.200 V, yielding a peak-to-peak swing of 0.4
V. The equations for computing the DDR power are:
PDDRIO = PSTATIC + PDYNAMIC
Eqn. 7
PSTATIC = (unused pins × % driven high) × 16 mA × 2.5 V
Eqn. 8
PDYNAMIC = (pin activity value) × 20 pF × (0.4 V)2 × 300 MHz × 10–3 mW
Eqn. 9
pin activity value = (active data lines × % activity × % data switching) + (active address lines × % activity)
Eqn. 10
As an example, assume the following:
unused pins = 16 (DDR uses 16-pin mode)
% driven high = 50%
active data lines = 16
% activity = 60%
% data switching = 50%
active address lines = 3
In this example, the DDR memory power consumption is:
PDDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)2 × 300 × 10–3) = 326.3 mW
3.3.4
Eqn. 11
External I/O Power
The estimation of the I/O power is similar to the computation of the peripheral power estimates. The power consumption per
signal line is computed assuming a maximum load of 20 pF, a voltage swing of 3.3 V, and a switching frequency of 25 MHz,
which yields:
PIO = 20 pF × (3.3 V)2 × 25 MHz × 10–3 = 5.44 mW per I/O line
Eqn. 12
Multiply this number by the number of I/O signal lines used in the application design to compute the total I/O power.
Note:
3.3.5
The signal loading depends on the board routing. For systems using a single DDR device, the load could be as low as
7 pF.
Leakage Power
The leakage power is for all power supplies combined at a specific temperature. The value is temperature dependent. The
observed leakage value at room temperature is 64 mW.
MSC7119 Data Sheet, Rev. 8
50
Freescale Semiconductor
Hardware Design Considerations
3.3.6
Example Total Power Consumption
Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is
estimated as the following:
PTOTAL = 324.0 + (4 × 4.32) + 326.3 + (10 × 5.44) + 64 = 784.98 mW
3.4
Eqn. 13
Reset and Boot
This section describes the recommendations for configuring the MSC7119 at reset and boot.
3.4.1
Reset Circuit
HRESET is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. For
an open-drain output such as HRESET, take care when driving many buffers that implement input bus-hold circuitry. The
bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. Either a smaller
value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7119 output
current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design).
3.4.2
Reset Configuration Pins
Table 34 shows the MSC7119 reset configuration signals. These signals are sampled at the deassertion (rising edge) of
PORESET. For details, refer to the Reset chapter of the MSC711x Reference Manual.
Table 34. Reset Configuration Signals
Signal
BM[3–0]
SWTE
Description
Settings
Determines boot mode.
See Table 35 for details.
Determines watchdog functionality.
0
HDSP
Configures HDI16 strobe polarity.
H8BIT
Configures HDI16 operation mode.
Watchdog timer disabled.
1
Watchdog timer enabled.
0
Host Data strobes active low.
1
Host Data strobes active high.
0
HDI16 port configured for 16-bit operation.
1
HDI16 port configured for 8-bit operation.
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
51
Hardware Design Considerations
Table 35. Boot Mode Source Selection
Boot
Port
BM[3–0]
Input Clock
Frequency
Clock
Divide
PLL
CKSEL
RNG
Bit
Core Clock
Frequency
Comments
HDI Boot Modes
0000
HDI16
< Fmax
N/A
N/A
00
0
< Fmax
Not clocked by the PLL.
Can boot as 8- or 16-bit HDI.
0101
HDI16
22.2-25 MHz
1
12
11
1
266–300 MHz
Can boot as 8- or 16-bit HDI.
0010
HDI16
25-33.3 MHz
2
32
01
1
200–266 MHz
0111
HDI16
33-66 MHz
3
12
11
1
132–264 MHz
0100
HDI16
44.3-50 MHz
2
12
11
1
266–300 MHz
SPI Boot Modes - Using HA3, HCS2, BM3, BM2 Pins
1000
SPI (SW)
< Fmax
N/A
N/A
00
0
< Fmax
1001
SPI (SW)
15.6-25 MHz
1
17
11
0
133–212.5 MHz
1010
SPI (SW)
33-50 MHz
2
16
11
0
132–200 MHz
1011
SPI (SW)
44.3-75 MHz
3
18
11
0
133–225 MHz
The boot program automatically
determines whether EEPROM
or Flash memory.
SPI Boot Modes - Using URXD, UTXD, SCL, SDA Pins
1100
SPI (SW)
< Fmax
N/A
N/A
00
0
< Fmax
I2C
< 100 MHz
N/A
N/A
00
0
< 100 MHz
Not clocked by the PLL.
I2C is limited to a maximum bit
rate of 400 Kbps. With a clock
divider of 128, this limits the
maximum input clock frequency
to 100 MHz.
0011
Reserved
—
—
—
—
—
—
—
0110
Reserved
—
—
—
—
—
—
—
1101
Reserved
—
—
—
—
—
—
—
1110
Reserved
—
—
—
—
—
—
—
1111
Reserved
—
—
—
—
—
—
—
Boots through different set of
pins.
I2C Boot Modes
0001
Reserved
Notes:
1.
2.
3.
3.4.3
The clock divider determines the value used in the clock module CLKCTRL[PLLDVF] field.
The clock multiplier determines the value used in the clock module CLKCTRL[PLLMLTF] field.
Fmax is determined by the maximum frequency of the peripheral and of the SC1400 core as specified in the data sheet.
Boot
After a power-on reset, the PLL is bypassed and the device is directly clocked from the CLKIN pin. Thus, the device operates
slowly during the boot process. After the boot program is loaded, it can enable the PLL and start the device operating at a higher
speed. The MSC7119 can boot from an external host through the HDI16 or download a user program through the I2C port. The
boot operating mode is set by configuring the BM[0–3] signals sampled at the rising edge of PORESET, as shown in Table 35.
See the MSC711x Reference Manual for details of boot program operation.
3.4.3.1
HDI16 Boot
If the MSC7119 device boots from an external host through the HDI16, the port is configured as follows:
•
•
•
•
Operate in Non-DMA mode.
Operate in polled mode on the device side.
Operate in polled mode on the external host side.
External host must write four 16-bit values at a time with the first word as the most significant and the fourth word as
the least significant.
MSC7119 Data Sheet, Rev. 8
52
Freescale Semiconductor
Hardware Design Considerations
When booting from a power-on reset, the HDI16 is additionally configurable as follows:
•
•
8- or 16-bit mode as specified by the H8BIT pin.
Data strobe as specified by the HDSP and HDDS pins.
These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these
pins is unaffected.
Note:
When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit
as for other DSP products.
3.4.3.2
I2C Boot
When the MSC7119 device is configured to boot from the I2C port, the boot program configures the GPIO pins for I2C
operation. Then the MSC7118 device initiates accesses to the I2C module, downloading data to the MSC7118 device. The I2C
interface is configured as follows:
•
•
•
•
•
PLL is disabled and bypassed so that the I2C module is clocked with the IPBus clock.
I2C interface operates in master mode and polling is used.
EPROM operates in slave mode.
Clock divider is set to 128.
Address of slave during boot is 0xA0.
The IPBus clock is internally divided to generate the bit clock, as follows:
•
•
•
•
CLKIN must be a maximum of 100 MHz
PLL is bypassed.
IPBus clock = CLKIN/2 is a maximum of 50 MHz.
I2C bit clock must be less than or equal to:
— IPBus clock/I2C clock divider
— 50 MHz (max)/128
— 390.6 KHz
This satisfies the maximum clock rate requirement of 400 kbps for the I2C interface. For details on the boot procedure, see the
“Boot Program” chapter of the MSC711x Reference Manual.
3.4.3.3
SPI Boot
When the MSC7119 device is configured to boot from the SPI port, the boot program configures the GPIO pins for SPI
operation. Then the MSC7118 device initiates accesses to the SPI module, downloading data to the MSC7118 device. When
the SPI routines run in the boot ROM, the MSC7118 is always configured as the SPI master. Booting through the SPI is
supported for serial EEPROM devices and serial Flash devices. When a READ_ID instruction is issued to the serial memory
device and the device returns a value of 0x00 or 0xFF, the routines for accessing a serial EEPROM are used, at a maximum
frequency of 4 Mbps. Otherwise, the routines for accessing a serial Flash are used, and they can run at faster speeds. Booting is
performed through one of two sets of pins:
•
•
Main set: BM[2–3], HA3, and HCS2, which allow use of the PLL.
Alternate set: UTXD, URXD, SDA, and SCL, which cannot be used with the PLL.
In either configuration, an error during SPI boot is flagged on the EVNT3 pin. For details on the boot procedure, see the “Boot
Program” chapter of the MSC711x Reference Manual.
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
53
Hardware Design Considerations
3.5
DDR Memory System Guidelines
MSC7119 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM
memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown
in Figure 36. Technique B is the most popular termination technique.
VTT
Generator
VTT
Controller
RS
DDR
Bank
RT
SSTL_2
Address
Command
SSTL_2
Chip Selects
RS
Data
Strobes
Mask
RT
SSTL_2
VTT Terminator
Technique A
DDR
Bank
VREF
VTT
Generator
Controller
RS
Technique B
Chip Selects
Data
Strobes
Mask
DDR
Bank
RT
SSTL_2
SSTL_2
RS
RT
VTT Terminator Island
Address
Command
DDR
Bank
SSTL_2
Figure 36. SSTL Termination Techniques
Figure 37 illustrates the power wattage for the resistors. Typical values for the resistors are as follows:
•
•
RS = 22 Ω
RT = 24 Ω
MSC7119 Data Sheet, Rev. 8
54
Freescale Semiconductor
Hardware Design Considerations
VTT
Driver
VDDQ
RT
Receiver
RS
VREF
VSS
Figure 37. SSTL Power Value
3.5.1
VREF and VTT Design Constraints
VTT and VREF are isolated power supplies at the same voltage, with VTT as a high current power source. This section outlines
the voltage supply design needs and goals:
•
•
•
•
•
•
•
3.5.2
Minimize the noise on both rails.
VTT must track variation in the VREF DC offsets. Although they are isolated supplies, one possible solution is to use a
single IC to generate both signals.
Both references should have minimal drift over temperature and source supply.
It is important to minimize the noise from coupling onto VREF as follows:
— Isolate VREF and shield it with a ground trace.
— Use 15–20 mm track.
— Use 20–30 mm clearance between other traces for isolating.
— Use the outer layer route when possible.
— Use distributed decoupling to localize transient currents and return path and decouple with an inductance less than
3 nH.
Max source/sink transient currents of up to 1.8 A for a 32-bit data bus.
Use a wide island trace on the outer layer:
— Place the island at the end of the bus.
— Decouple both ends of the bus.
— Use distributed decoupling across the island.
— Place SSTL termination resistors inside the VTT island and ensure a good, solid connection.
Place the VTT regulator as closely as possible to the termination island.
— Reduce inductance and return path.
— Tie current sense pin at the midpoint of the island.
Decoupling
The DDR decoupling considerations are as follows:
•
•
•
•
•
DDR memory requires significantly more burst current than previous SDRAMs.
In the worst case, up to 64 drivers may be switching states.
Pay special attention and decouple discrete ICs per manufacturer guidelines.
Leverage VTT island topology to minimize the number of capacitors required to supply the burst current needs of the
termination rail.
See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel
(http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf).
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
55
Hardware Design Considerations
3.5.3
General Routing
The general routing considerations for the DDR are as follows:
•
•
•
•
•
•
3.5.4
All DDR signals must be routed next to a solid reference:
— For data, next to solid ground planes.
— For address/command, power planes if necessary.
All DDR signals must be impedance controlled. This is system dependent, but typical values are 50–60 ohm.
Minimize other cross-talk opportunities. As possible, maintain at least a four times the trace width spacing between all
DDR signals to non-DDR signals.
Keep the number of vias to a minimum to eliminate additional stubs and capacitance.
Signal group routing priorities are as follows:
— DDR clocks.
— Route MVTT/MVREF.
— Data group.
— Command/address.
Minimize data bit jitter by trace matching.
Routing Clock Distribution
The DDR clock distribution considerations are as follows:
•
•
•
•
•
3.5.5
DDR controller supports six clock pairs:
— 2 DIMM modules.
— Up to 36 discrete chips.
For route traces as for any other differential signals:
— Maintain proper difference pair spacing.
— Match pair traces within 25 mm.
Match all clock traces to within 100 mm.
Keep all clocks equally loaded in the system.
Route clocks on inner critical layers.
Data Routing
The DDR data routing considerations are as follows:
•
•
•
•
•
•
•
Route each data group (8-bits data + DQS + DM) on the same layer. Avoid switching layers within a byte group.
Take care to match trace lengths, which is extremely important.
To make trace matching easier, let adjacent groups be routed on alternate critical layers.
Pin swap bits within a byte group to facilitate routing (discrete case).
Tight trace matching is recommended within the DDR data group. Keep each 8-bit datum and its DM signal within ±
25 mm of its respective strobe.
Minimize lengths across the entire DDR channel:
— Between all groups maintain a delta of no more than 500 mm.
— Allows greater flexibility in the design for readjustments as needed.
DDR data group separation:
— If stack-up allows, keep DDR data groups away from the address and control nets.
— Route address and control on separate critical layers.
— If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages.
MSC7119 Data Sheet, Rev. 8
56
Freescale Semiconductor
Ordering Information
3.6
Connectivity Guidelines
This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7119
device. Following are guidelines for signal groups and configuration settings:
•
•
•
•
•
•
•
Clock and reset signals.
— SWTE is used to configure the MSC7119 device and is sampled on the deassertion of PORESET, so it should be
tied to VDDC or GND either directly or through pull-up or pull-down resistors until PORESET is deasserted. After
PORESET, this signal can be left floating.
— BM[0–1] configure the MSC7119 device and are sampled until PORESET is deasserted, so they should be tied to
VDDIO or GND either directly or through pull-up or pull-down resistors.
— HRESET should be pulled up.
Interrupt signals. When used, IRQ pins must be pulled up.
HDI16 signals.
— When they are configured for open-drain, the HREQ/HREQ or HTRQ/HTRQ signals require a pull-up resistor.
However, these pins are also sampled at power-on reset to determine the HDI16 boot mode and may need to be
pulled down. When these pins must be pulled down on reset and pulled up otherwise, a buffer can be used with
the HRESET signal as the enable.
— When the device boots through the HDI16, the HDDS, HDSP and H8BIT pins should be pulled up or down,
depending on the required boot mode settings.
Ethernet MAC/TDM2 signals. The MDIO signal requires an external pull-up resistor.
I2C signals. The SCL and SDA signals, when programmed for I2C, requires an external pull-up resistor.
General-purpose I/O (GPIO) signals. An unused GPIO pin can be disconnected. After boot, program it as an output
pin.
Other signals.
— The TEST0 pin must be connected to ground.
— The TPSEL pin should be pulled up to enable debug access via the EOnCE port and pulled down for boundary
scan.
— Pins labelled NO CONNECT (NC) must not be connected.
— When a 16-pin double data rate (DDR) interface is used, the 16 unused data pins should be no connects (floating)
if the used lines are terminated.
— Do not connect DBREQ to DONE (as you would for the MSC8101 device). Connect DONE to one of the EVNT
pins, and DBREQ to HRRQ.
4
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Part
Supply Voltage
Package Type
MSC7119
1.2 V core
2.5 V memory
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
Pin
Count
Core
Frequency
(MHz)
Solder Spheres
Order Number
400
300
Lead-free
MSC7119VM1200
Lead-bearing
MSC7119VF1200
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
57
Package Information
5
Package Information
Notes:
1. All dimensions in millimeters.
2. Dimensioning and tolerancing
per ASME Y14.5M–1994.
3. Maximum solder ball diameter
measured parallel to Datum A.
4. Datum A, the seating plane, is
determined by the spherical
crowns of the solder balls.
5. Parallelism measurement shall
exclude any effect of mark on
top surface of package.
CASE 1568-01
Figure 38. MSC7119 Mechanical Information, 400-pin MAP-BGA Package
6
Product Documentation
•
•
•
MSC711x Reference Manual (MSC711xRM). Includes functional descriptions of the extended cores and all the
internal subsystems including configuration and programming information.
Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC7119 device.
SC140/SC1400 DSP Core Reference Manual. Covers the SC140 and SC1400 core architecture, control registers, clock
registers, program control, and instruction set.
MSC7119 Data Sheet, Rev. 8
58
Freescale Semiconductor
Revision History
7
Revision History
Table 36 provides a revision history for this data sheet.
Table 36. Document Revision History
Revision
Date
Description
0
Sep. 2005
• Initial public release.
1
Oct 2005
• Added explanatory note to HDI16 timing table.
2
Oct. 2005
• Added information about signals GPIOB11, GPIOC11, GPIOD7, and GPIOD8 to the signal descriptions
and pinout location lists.
3
Dec. 2005
• Added information about signals GPIOA16, GPIOA17, GPIOA27, GPIOA28, and GPIOA29 to signal
description and pinout location lists.
4
Feb. 2006
• Updated orderable part numbers.
5
Nov. 2006
• Updated Reference Manual reference to MSC711x Reference Manual.
• Updated arrows in Host DMA Writing Timing figure.
6
Jun. 2007
• Updated to new data sheet format. Reorganized and renumbered sections, figures, and tables.
• Added a note to clarify the definition of TCK timing 700 in new Table 31.
• Removed references to VCCSYN and VCCSYN1 in the new power supply design recommendation Section
3.2.
7
Aug 2007
• The power-up and power-down sequences described in Section 3.2 starting on page 42 have been expanded
to five possible design scenarios/cases. These cases replace the previously recommended
power-up/power-down sequence recommendations. Section 3.2 has been clarified by adding subsection
headings.
8
Apr 2008
• Change the PLL filter resistor from 20 Ω to 2 Ω in Section 3.2.5.
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
59
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Document Number: MSC7119
Rev. 8
4/2008
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