P89LPC9408

P89LPC9408

8-bit microcontroller with two-clock 80C51 core 8 kB 3 V byte-erasable flash, 32 segment

×

4 LCD driver, 10-bit ADC

Rev. 01 — 16 December 2005 Product data sheet

1.

General description

The P89LPC9408 is a multi-chip module consisting of a P89LPC938 single-chip microcontroller combined with a PCF8576D universal LCD controller in a low-cost 64-pin package. The LCD controller provides 32 segments and supports from 1 to 4 backplanes.

Display overhead is minimized by an on-chip display RAM with auto-increment addressing.

2.

Features

2.1 Principal features

■ 8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.

Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

■ 256-byte RAM data memory.

■ 512-byte customer Data EEPROM on chip allows serialization of devices, storage of set-up parameters, etc.

■ 32 segment

×

4 backplane LCD controller supports from 1 to 4 backplanes.

■ 8-input multiplexed 10-bit ADC. Two analog comparators with selectable inputs and reference source.

■ Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output) and a 23-bit system timer that can also be used as a Real-Time Clock (RTC).

■ Enhanced UART with fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I 2 C-bus communication port and SPI communication port.

■ CCU provides PWM, input capture, and output compare functions.

■ High-accuracy internal RC oscillator option allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable.

■ 64-pin LQFP package with 20 microcontroller I/O pins minimum and up to 23 microcontroller I/O pins while using on-chip oscillator and reset options.

2.2 Additional features

■ 2.4 V to 3.6 V V

DD

operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).

■ Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.

Philips Semiconductors

P89LPC9408

8-bit two-clock 80C51 core with 32 segment

×


■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced

EMI.

■ Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application.

■ In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application.

■ Watchdog timer with separate on-chip oscillator, requiring no external components.

The watchdog prescaler is selectable from eight values.

■ Low voltage detect (brownout) allows a graceful system shutdown when power fails.

May optionally be configured as an interrupt.

■ Idle and two different power-down reduced power modes. Improved wake-up from

Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 9

µ

A typical (total power-down with voltage comparators disabled).

■ Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.

■ Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from

20 kHz to the maximum operating frequency of 18 MHz.

■ Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.

■ Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only.

■ Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.

■ LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip.

■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.

■ Only power and ground connections are required to operate the P89LPC9408 when internal reset option is selected.

■ Four interrupt priority levels.

■ Eight keypad interrupt inputs, plus two additional external interrupt inputs.

■ Schmitt trigger port inputs.

■ Second data pointer.

P89LPC9408_1

Product data sheet Rev. 01 — 16 December 2005

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

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3.

Ordering information

Table 1: Ordering information

Type number Package

Name Description

P89LPC9408FBD LQFP64 plastic low profile quad flat package; 64 leads; body 14

×

14

×

1.4 mm

3.1 Ordering options

Table 2: Part options

Type number

P89LPC9408FBD

Flash memory

8 kB

Temperature range

−

40

°

C to +85

°

C

Version

SOT791-1

Frequency

0 MHz to 18 MHz

4.

Block diagram

P3[1:0]

P2.5, P2[3:0]

P1[7:0]

P0[7:0]

P89LPC938

MCU

PCF8576D

LCD

CONTROLLER

A[2:0] SA0 OSC

SCL, SDA SCL_LCD, SDA_LCD

002aab775

S[31:0]

BP[3:0]

V

LCD

Fig 1.

Block diagram

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P89LPC9408


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P3[1:0]

P2[7:0]

P1[7:0]

P0[7:0]

CRYSTAL

OR

RESONATOR

X1

X2

P89LPC938

ACCELERATED 2-CLOCK 80C51 CPU

8 kB

CODE FLASH

256-BYTE

DATA RAM

512-BYTE

AUXILIARY RAM internal bus

512-BYTE

DATA EEPROM

PORT 3

CONFIGURABLE I/Os

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CONFIGURABLE

OSCILLATOR

CPU clock

ON-CHIP

RC

OSCILLATOR

UART

I

2

C-BUS

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0

TIMER 1

ANALOG

COMPARATORS

CCU (CAPTURE/

COMPARE UNIT)

ADC0

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

002aab106

Fig 2.

Microcontroller section block diagram

TXD

RXD

SCL

SDA

SPICLK

MOSI

MISO

SS

T0

T1

CMP2

CIN2A

CIN1A

CIN2B

CMP1

CIN1B

OCA

OCC

ICA

OCB

OCD

ICB

AD00

AD02

AD04

AD06

AD01

AD03

AD05

AD07

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BP0 BP1 BP2 BP3

V

DD

BACKPLANE

OUTPUTS

LCD BIAS

GENERATOR

LCD

VOLTAGE

SELECTOR

V

LCD

CLK

SYNC

OSC

V

SS

SCL

SDA

TIMING

OSCILLATOR

INPUT

FILTERS

BLINKER

DISPLAY

CONTROLLER

POWER-

ON

RESET

I

2

C-BUS

CONTROLLER

COMMAND

DECODER

S0 TO S39

DISPLAY SEGMENT OUTPUTS

DISPLAY LATCH

SHIFT REGISTER

INPUT

BANK

SELECTOR

DISPLAY

RAM

40

×

4 BITS

OUTPUT

BANK

SELECTOR

DATA

POINTER

SUB-

ADDRESS

COUNTER

SA0

Fig 3.

LCD display controller block diagram

5.

Functional diagram

A0 A1 A2

002aab470

AD05

AD00

AD01

AD02

AD03

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

CLKOUT

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

T1

XTAL2

XTAL1

PORT 0

PORT 3

V

DD

V

SS

P89LPC9408

002aab776

PORT 1

PORT 2

TXD

RXD

T0

INT0

INT1

RST

OCB

OCC

ICB

OCD

MOSI

MISO

SS

SPICLK

OCA

ICA

SCL

SDA

AD04

AD07

AD06

Fig 4.

P89LPC9408 functional diagram

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6.

Pinning information

6.1 Pinning

P0.5/CMPREF/KBI5

P0.4/CIN1A/KBI4/AD03

1

2

P0.3/CIN1B/KBI3/AD02

P0.2/CIN2A/KBI2/AD01

3

4

P0.1/CIN2B/KBI1/AD00

P2.0/ICB/AD07

5

6

P2.1/OCD/AD06

P0.0/CMP2/KBI0/AD05

7

8

P1.7/OCC/AD04

P1.6/OCB

9

10

P1.5/RST 11

V

SS

P3.1/XTAL1

12

13

P3.0/XTAL2/CLKOUT

P1.4/INT1

14

15

P1.3/INT0/SDA 16

P89LPC9408

36

35

34

33

40

39

38

37

44

43

42

41

48

47

46

45

S5

S4

S3

S2

S9

S8

S7

S6

S13

S12

S11

S10

S17

S16

S15

S14

002aab777

Fig 5.

Pin configuration

6.2 Pin description

Table 3: Pin description

Symbol Pin Type Description

P0.0 to P0.7

I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset

Port 0 latches are configured in the input only mode with the internal pull-up disabled.

The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to

Section 7.13.1 “Port configurations” and

Table 12 “Static electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt trigger inputs.

Port 0 also provides various special functions as described below:

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Table 3: Pin description …continued


P0.0/CMP2/

KBI0/AD05

8

I

I

I/O P0.0 — Port 0 bit 0.

O CMP2 — Comparator 2 output.

KBI0 — Keyboard input 0.

AD05 — ADC0 channel 5 analog input.

P0.1/CIN2B/

KBI1/AD00

5

P0.2/CIN2A/

KBI2/AD01

4

I

I

I

I/O P0.1 — Port 0 bit 1.

CIN2B — Comparator 2 positive input B.



I

I

I

I/O P0.2 — Port 0 bit 2.

CIN2A — Comparator 2 positive input A.



P0.3/CIN1B/

KBI3/AD02

3

P0.4/CIN1A/

KBI4/AD03

P0.5/

CMPREF/

KBI5

P0.6/CMP1/

KBI6

P0.7/T1/KBI7

P1.0 to P1.7

P1.0/TXD

P1.1/RXD

2

1

24

23

22

21

I

I

I

I/O P0.3 — Port 0 bit 3.

CIN1B — Comparator 1 positive input B.



I

I

I

I/O P0.4 — Port 0 bit 4.

CIN1A — Comparator 1 positive input A.



I

I/O P0.5 — Port 0 bit 5.

CMPREF — Comparator reference (negative) input.

I KBI5 — Keyboard input 5.

I/O P0.6 — Port 0 bit 6.

I

O CMP1 — Comparator 1 output.


I/O P0.7 — Port 0 bit 7.

I/O T1 — Timer/counter 1 external count input or overflow output.

I

I/O, I

[1]


Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to

Section 7.13.1 “Port configurations”

and

Table 12 “Static electrical characteristics”

for details. P1.2 and P1.3

are open drain when used as outputs. P1.5 is input only.



I/O P1.0 — Port 1 bit 0.

O TXD — Transmitter output for the serial port.

I

I/O P1.1 — Port 1 bit 1.

RXD — Receiver input for the serial port.

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P1.2/T0/SCL 17 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O T0 — Timer/counter 0 external count input or overflow output (open-drain when used as output).

I/O SCL — I 2 C-bus serial clock input/output.

P1.3/INT0/

SDA

P1.4/INT1

16

15 I

I/O P1.3 — Port 1 bit 3 (open-drain when used as output).

I INT0 — External interrupt 0 input.

I/O SDA — I 2 C-bus serial data input/output.

P1.4 — Port 1 bit 4.

P1.5/RST

P1.6/OCB

P1.7/OCC/

AD04

P2.0 to P2.3,

P2.5

P2.0/ICB/

AD07

P2.1/OCD/

AD06

P2.2/MOSI

P2.3/MISO

11

10

9

6

7

18

19

I

I INT1 — External interrupt 1 input.

P1.5 — Port 1 bit 5 (input only).

I RST — External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode.

When using an oscillator frequency above 12 MHz, the reset input function of

P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V

DD

has reached its specified level. When system power is removed V

DD

will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

DD below the minimum specified operating range.

falls

I/O P1.6 — Port 1 bit 6.

O OCB — Output Compare B.

I/O P1.7 — Port 1 bit 7.

I

O OCC — Output Compare C.


I/O Port 2: Port 2 is an 5-bit I/O port with a user-configurable output type. During reset







I/O P2.0 — Port 2 bit 0.

I

I ICB — Input Capture B.


I/O P2.1 — Port 2 bit 1.

O OCD — Output Compare D.

I AD06 — ADC0 channel 6 analog input.

I/O P2.2 — Port 2 bit 2.

I/O MOSI — SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input.

I/O P2.3 — Port 2 bit 3.

I/O MISO — When configured as master, this pin is input, when configured as slave, this pin is output.

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P2.5/SPICLK 20

P3.0 to P3.1

I/O P2.5 — Port 2 bit 5.

I/O SPICLK — SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input.

I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset





All pins have Schmitt triggered inputs.


P3.0/XTAL2/

CLKOUT

14

P3.1/XTAL1

SDA_LCD

SCL_LCD

BP0 to BP3

S0 to S31

V

V

V

SS

DD

LCD

13

63

64

27 to 30

31 to 62

12

25

26 I

I

I

I/O P3.0 — Port 3 bit 0.

O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration.

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer.

I/O P3.1 — Port 3 bit 1.

I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer.

I

I/O SDA LCD — I 2 C-bus data signal for the LCD controller.

SCL LCD — I 2 C-bus clock signal for the LCD controller.

O

O

BP0 to BP3: LCD backplane outputs.

S0 to S31: LCD segment outputs

Ground: 0 V reference.

Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.

LCD power supply: LCD supply voltage.

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

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7.

Functional description

Remark: Please refer to the P89LPC9408 User manual for a more detailed functional description.

7.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not defined.

• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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Table 4: Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR addr.

Bit functions and addresses

MSB LSB

Reset value

Hex Binary

E5 E4 E3

ACC* Accumulator

AD0CON ADC0 control register

Bit address

E0H

97H

E7

ENBI0

E6

ENADCI0

AD0INS ADC0 input select

AD0MODA ADC0 mode register A

AD0MODB ADC0 mode register B

AUXR1 Auxiliary function register

A3H

C0H

A1H

A2H

Bit address

F0H

BEH

B*

BRGR0 [1]

B register

Baud rate generator rate low

BRGR1

CCCRA

[1]

Baud rate generator rate high

BRGCON Baud rate generator control

Capture compare A control register

CCCRB

CCCRC

Capture compare B control register

Capture compare C control register

CCCRD

CMP1

Capture compare D control register

Comparator 1 control register

CMP2 Comparator 2 control register

DEECON Data EEPROM control register

BFH

BDH

EAH

EBH

ECH

EDH

ACH

ADH

F1H

ADI07

BNDI0

CLK2

CLKLP

F7

-

ICECA2

ICECB2

-

-

-

-

EEIF

ADI06

BURST0

CLK1

EBRR

F6

ICECA1

ICECB1

-

-

-

-

-

HVERR

TMM0

ADI05

SCC0

CLK0

ENT1

F5

-

ICECA0

ICECB0

-

-

CE1

CE2

ECTL1

EDGE0

ADI04

SCAN0

-

ENT0

F4

-

ICESA

ICESB

-

-

CP1

CP2

ECTL0

ADCI0

ADI03

-

-

SRST

F3

-

ICNFA

ICNFB

-

-

CN1

CN2

-

E2 E1 E0

00

ENADC0 ADCS01 ADCS00 00

ADI02

-

-

0

F2

-

FCOA

FCOB

FCOC

FCOD

OE1

OE2

-

ADI01

-

-

-

F1

SBRGS

OCMA1

OCMB1

ADI00 00

00

-

DPS

F0

00

00

00

00

00

BRGEN

00 [1]

OCMA0 00

OCMB0 00

OCMC1 OCMC0 00

OCMD1 OCMD0 00

CO1

CO2

-

CMF1

00 [2]

CMF2

00 [2]

EADR8 0E

0000 0000

0000 0000

0000 0000

0000 0000

000x 0000

0000 00x0

0000 0000

0000 0000

0000 0000 xxxx xx00

0000 0000

0000 0000 xxxx x000 xxxx x000 xx00 0000 xx00 0000

0000 1110


Table 4: Special function registers …continued




MSB LSB

Reset value

Hex Binary

0000 0000 DEEDAT Data EEPROM data register

DEEADR Data EEPROM address register

DIVM CPU clock divide-by-M control

DPTR

DPH

DPL

Data pointer

(2 bytes)

Data pointer high

Data pointer low

F2H

F3H

95H

00

00

00

I2CON*

I2DAT

I2SCLH

83H

82H

E7H FMADRH Program flash address high

FMADRL Program flash address low

FMCON Program flash control (Read)

FMDATA

I2ADR

I2SCLL

I2STAT

ICRAH

E6H

E4H BUSY HVA HVE SV OI

00

70

Program flash control (Write)

Serial clock generator/SCL duty cycle register high

Serial clock generator/SCL duty cycle register low

I 2 C status register

Input capture A register high

E4H

Program flash data E5H

I 2 C slave address register

DBH I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

DF DE DD DC DB DA D9 Bit address

I 2 C control register D8H

I 2 C data register DAH

I2EN STA STO SI AA -

DDH

DCH

D9H

ABH

FMCMD.7

STA.4

FMCMD.6

STA.3

FMCMD.5

STA.2

FMCMD.4

STA.1

FMCMD.3

STA.0

FMCMD.2

0

FMCMD.1

0

FMCMD.0

GC

D8

CRSEL

0

00

00

00

00

00

F8

00

00

00

00

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0111 0000

0000 0000

0000 0000 x000 00x0

0000 0000

0000 0000

1111 1000

0000 0000






MSB LSB

Reset value

Hex Binary

00 0000 0000 ICRAL

ICRBH

ICRBL

IEN0*

IEN1*

IEN2

IP0*

IP0H

IP1*

IP1H

IP2

IP2H

KBCON

Input capture A register low

Input capture B register high

AAH

AFH

Input capture B register low

Interrupt enable 0

AEH

Bit address

A8H

Bit address

Interrupt enable 1 E8H

Interrupt enable 2 D5H

Bit address

AF

EA

EF

EIEE

-

BF

Interrupt priority 0

Interrupt priority 0 high

B8H

B7H

Bit address




FF

F8H PADEE

F7H PADEEH

D6H

D7H

-


Keypad control register

94H -

-

-

86H KBMASK Keypad interrupt mask register

KBPATN Keypad pattern register

OCRAH

OCRAL

Output compare A register high

Output compare A register low

EFH

EEH

AE

EWDRT

EE

EST

-

BE

PWDRT

PWDRTH

FE

PST

PSTH

-

-

-

AD

EBO

ED

-

-

BD

PBO

PBOH

FD

-

-

-

-

-

AC

ES/ESR

EC

ECCU

-

BC

PS/PSR

PSH/

PSRH

FC

PCCU

PCCUH

-

-

-

AB

ET1

EB

ESPI

-

BB

PT1

PT1H

FB

PSPI

PSPIH

-

-

-

AA

EX1

EA

EC

-

BA

PX1

PX1H

FA

PC

PCH

-

-

-

A9

ET0

E9

EKBI

EADC

B9

PT0

PT0H

F9

PKBI

PKBIH

PADC

PADCH

PATN

_SEL

00

00

A8

EX0 00

E8

EI2C

-

00 [2]

00 [2]

B8

PX0

00 [2]

PX0H

00 [2]

F8

PI2C

00 [2]

PI2CH

00 [2]

-

-

KBIF

00 [2]

00 [2]

00 [2]

00

FF

00

00

0000 0000

0000 0000

0000 0000

00x0 0000

00x0 0000 x000 0000 x000 0000

00x0 0000

00x0 0000

00x0 0000

00x0 0000 xxxx xx00

0000 0000

1111 1111

0000 0000

0000 0000






MSB LSB

Reset value

Hex Binary

OCRBH 0000 0000

OCRBL

OCRCH

OCRCL

OCRDH

OCRDL

P0*

P1*

P2*

P3*

P0M1

P0M2

P1M1

P1M2

P2M1

P2M2

Output compare B register high

Output compare B register low

Output compare C register high

Output compare C register low

FBH

FAH

FDH

FCH

00

00

00

00

Output compare D register high

Output compare D register low

Port 0

Port 1

Port 2

FFH

FEH

Bit address

80H

Bit address

90H

Bit address

87

T1/KB7

97

OCC

97

86

CMP1

/KB6

96

OCB

96

85

CMPREF/

KB5

95

RST

95

84

CIN1A

/KB4

94

INT1

94

83

CIN1B

/KB3

93

82

CIN2A

/KB2

92

INT0/SDA T0/SCL

93 92

81

CIN2B

/KB1

91

RXD

91

80

CMP2

/KB0

90

TXD

90

00

00

A0H

Bit address

ICA

B7

OCA

B6

SPICLK

B5

SS

B4

MISO

B3

MOSI

B2

OCD

B1

ICB

B0

B0H XTAL1 XTAL2

84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0)

FF [2]

Port 3

Port 0 output mode 1






85H

91H

92H

A4H

A5H

(P0M2.7)

(P1M1.7)

(P1M2.7)

(P2M1.7)

(P2M2.7)

(P0M2.6)

(P1M1.6)

(P1M2.6)

(P2M1.6)

(P2M2.6)

(P0M2.5)

-

-

(P2M1.5)

(P2M2.5)

(P0M2.4)

(P1M1.4)

(P1M2.4)

(P2M1.4)

(P2M2.4)

(P0M2.3)

(P1M1.3)

(P1M2.3)

(P2M1.3)

(P2M2.3)

(P0M2.2)

(P1M1.2)

(P1M2.2)

(P2M1.2)

(P2M2.2)

(P0M2.1)

(P1M1.1)

(P1M2.1)

(P2M1.1)

(P2M2.1)

(P0M2.0)

(P1M1.0)

(P1M2.0)

(P2M1.0)

(P2M2.0)

00

D3

00

FF

00

[2]

[2]

[2]

[2]

[2]

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

[2]

[2]

[2]

[2]

1111 1111

0000 0000

11x1 xx11

00x0 xx00

1111 1111

0000 0000




Name

P3M1

Description


SFR addr.

B1H


MSB

-

LSB

Reset value

Hex

(P3M1.1) (P3M1.0)

03 [2]

Binary xxxx xx11

P3M2 Port 3 output mode 2

B2H (P3M2.1) (P3M2.0)

00 [2]

xxxx xx00

SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000 PCON

PCONA

Power control register

Power control register A

87H

B5H

PSW* Program status word

Bit address

D0H

F6H PT0AD Port 0 digital input disable

RSTSRC Reset source register

RTCCON RTC control

DFH

D1H

RTCH

RTCL

SADDR

SADEN

RTC register high

RTC register low

Serial port address register

Serial port address enable

D2H

D3H

A9H

B9H

SBUF

SMOD1

RTCPD

D7

CY

-

-

RTCF

SCON*

SSTAT

SP

SPCTL

SPSTAT

SPDAT

Serial Port data buffer register

99H

Bit address

Serial port control 98H

9F

SM0/FE

Serial port extended status register

BAH DBMOD

Stack pointer 81H

SPI control register E2H

SPI status register

SPI data register

E1H

E3H

SSIG

SPIF

DEEPD

D6

AC

-

-

RTCS1

9E

SM1

INTLO

SPEN

WCOL

VCPD

D5

F0

BOF

RTCS0

9D

SM2

CIDIS

DORD

-

ADPD

D4

RS1

POF

-

9C

REN

DBISEL

MSTR

-

I2PD

D3

RS0

R_BK

-

9B

TB8

FE

CPOL

-

SPPD

D2

OV

R_WD

-

9A

RB8

BR

CPHA

-

SPD

D1

F1

PT0AD.5

PT0AD.4

PT0AD.3

PT0AD.2

PT0AD.1

R_SF

ERTC

99

TI

OE

SPR1

-

CCUPD

00 [2]

D0

P

-

R_EX

00

00

RTCEN

60 [2] [4]

00 [4]

00 [4]

011x xx00

0000 0000

0000 0000

00 0000 0000

00 xx

98

RI 00

STINT 00

07

SPR0 04

00

00

0000 0000

0000 0000 xx00 000x

[3]

0000 0000 xxxx xxxx

0000 0000

0000 0000

0000 0111

0000 0100

00xx xxxx

0000 0000






MSB LSB

Reset value

Hex Binary xxx0 xxx0 TAMOD

TCON*

TCR20*

TCR21

TH0

TH1

TH2

TICR2

TIFR2

Timer 0 and 1 auxiliary mode

8FH -

Timer 0 and 1 control

CCU control register 0

CCU control register 1

Timer 0 high

Timer 1 high

CCU timer high

Bit address

88H

C8H

F9H

8CH

8DH

CDH

C9H

8F

TF1

PLEEN

TCOU2

TOIE2 CCU interrupt control register

CCU interrupt flag register

E9H TOIF2

-

8E

TR1

HLTRN

-

TOCIE2D

TOCF2D

-

8D

TF0

HLTEN

-

TOCIE2C

TOCF2C

T1M2

8C

TR0

ALTCD

-

TOCIE2B

TOCF2B

-

8B

IE1

ALTAB

PLLDV.3

TOCIE2A

TOCF2A

-

8A

IT1

TDIR2

PLLDV.2

-

-

-

89

IE0

TMOD21

PLLDV.1

TICIE2B

TICF2B

T0M2

88

IT0

TMOD20

PLLDV.0

TICIE2A

TICF2A

00

00

00

00

00

00

00

00

00

TISE2

TL0

TL1

TL2

CCU interrupt status encode register

Timer 0 low

Timer 1 low

CCU timer low

DEH

8AH

8BH

CCH

ENCINT.2

ENCINT.1

ENCINT.0 00

TMOD

TOR2H

Timer 0 and 1 mode 89H T1GATE

CCU reload register high

CFH

CEH TOR2L CCU reload register low

TPCR2H Prescaler control register high

TPCR2L Prescaler control register low

CBH -

T1C/T

-

T1M1

-

T1M0

-

T0GATE

-

T0C/T

-

T0M1

TPCR2H.

1

T0M0

TPCR2H.

0

00

00

00

00

CAH TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0 00

TRIM Internal oscillator trim register

96H RCCLK ENCLK TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

00

00

00

0000 0000

0000 0000

0xxx 0000

0000 0000

0000 0000

0000 0000

0000 0x00

0000 0x00 xxxx x000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000 xxxx xx00

0000 0000

[4] [5]




Name

WDCON

Description

Watchdog control register

SFR addr.

A7H


MSB

PRE2 PRE1 PRE0 WDRUN WDTOF

LSB

WDCLK

Reset value

Hex Binary

[4] [6]

FF 1111 1111 WDL Watchdog load

WFEED1 Watchdog feed 1

WFEED2 Watchdog feed 2

C1H

C2H

C3H

[1] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[2] All ports are in input only (high-impedance) state after power-up.

[3] The RSTSRC register reflects the cause of the P89LPC9408 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000.

[4] The only reset source that affects these SFRs is power-on reset.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.


Table 5: P89LPC938 extended special function registers


Bit functions and addresses Reset value

ADC0HBND FFEFH

MSB LSB Hex

FF

Binary

1111 1111

ADC0LBND

AD0DAT0R

AD0DAT0L

AD0DAT1R

AD0DAT1L

AD0DAT2R

AD0DAT2L

AD0DAT3R

AD0DAT3L

AD0DAT4R

AD0DAT4L

AD0DAT5R

AD0DAT5L

AD0DAT6R

AD0DAT6L

AD0DAT7R

AD0DAT7L

BNDSTA0

ADC0 high _boundary register, left

(MSB)

ADC0 low_boundary register (MSB)

ADC0 data register 0, right (LSB)

ADC0 data register 0, left (MSB)















ADC0 boundary status register

FFF8H

FFF9H

FFF6H

FFF7H

FFF4H

FFF5H

FFF2H

FFF3H

FFEEH

FFFEH

FFFFH

FFFCH

FFFDH

FFFAH

FFFBH

FFF0H

FFF1H

FFEDH

AD0DAT0[7:0]

AD0DAT0[9:2]

AD0DAT1[7:0]

AD0DAT1[9:2]

AD0DAT2[7:0]

AD0DAT2[9:2]

AD0DAT3[7:0]

AD0DAT3[9:2]

AD0DAT4[7:0]

AD0DAT4[9:2]

AD0DAT5[7:0]

AD0DAT5[9:2]

AD0DAT6[7:0]

AD0DAT6[9:2]

AD0DAT7[7:0]

AD0DAT7[9:2]

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000


P89LPC9408


×


7.2 Enhanced CPU

The P89LPC9408 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

7.3 Clocks

7.3.1 Clock definitions

The P89LPC9408 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see

Figure 6 ) and can also be optionally divided to a slower frequency (see

Section 7.8 “CCLK modification: DIVM register” ).

Note: f osc

is defined as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is CCLK ⁄

2

.

7.3.2 CPU clock (OSCCLK)

The P89LPC9408 provides several user-selectable oscillator options in generating the

CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.

7.3.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.

7.3.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

7.3.5 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V

DD


DD


DD

falls below the minimum specified operating range.

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7.3.6 Clock output

The P89LPC9408 supports a user-selectable clock output function on the

XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC9408. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is 1 ⁄

2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering idle, saving additional power.

7.4 On-chip RC oscillator option

The P89LPC9408 has a 6-bit TRIM register that can be used to tune the frequency of the

RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz

±

1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies.

7.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

7.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the

P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V

DD


DD


DD

falls below the minimum specified operating voltage.

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XTAL1

XTAL2

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

RTC

ADC0

OSCCLK

DIVM

CCLK

PCLK

÷

2

CPU

RC

OSCILLATOR

(7.3728 MHz

±

1 %)

RCCLK

WATCHDOG

OSCILLATOR

(400 kHz

+

30 %

−

20 %)

TIMER 0 AND

TIMER 1

I

2

C-BUS

PCLK

SPI UART

WDT

32

×

PLL

CCU

002aab102

Fig 6.

Block diagram of oscillator control

7.7 CPU Clock (CCLK) wake-up delay

The P89LPC9408 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus

60

µ s to 100

µ s. If the clock source is either the internal RC oscillator, watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60

µ s to 100

µ s.

7.8 CCLK modification: DIVM register

The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

7.9 Low power select

The P89LPC9408 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is

8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

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7.10 Memory organization

The various P89LPC9408 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

• XDATA

‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC9408 has 512 bytes of on-chip

XDATA memory, plus extended SFRs located in XDATA.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC9408 has 8 kB of on-chip Code memory.

7.11 Data RAM arrangement

The 768 bytes of on-chip RAM are organized as shown in

Table 6 .

Table 6: On-chip data memory usages

Type Data RAM

DATA

IDATA

XDATA

Memory that can be addressed directly and indirectly

Memory that can be addressed indirectly

Auxiliary (‘External Data’) on-chip memory that is accessed using the MOVX instructions

Size (bytes)

128

256

512

7.12 Interrupts

The P89LPC9408 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC9408 supports

16 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port

RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I 2 C-bus, keyboard, comparators 1 and 2, SPI, CCU, data EEPROM write, and ADC completion.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0, IEN1, or IEN2. The IEN0 register also contains a global disable bit, EA, which disables all interrupts.

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Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, IP1H, IP2, and

IP2H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.

7.12.1 External interrupt inputs

The P89LPC9408 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request.

If an external interrupt is enabled when the P89LPC9408 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to

Section 7.15 “Power reduction modes”

for details.

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RTCF

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF2

CMF1

EC

EA (IE0.7)

TF0

ET0

TF1

ET1

TI and RI/RI

ES/ESR

TI

EST

SI

EI2C

SPIF

ESPI any CCU interrupt

ECCU

EEIF

EIEE

IE0

EX0

IE1

EX1

BOF

EBO

KBIF

EKBI wake-up

(if in power-down) interrupt to CPU

ENADCI0

ADCI0

ENBI1

BNDI1

EADC

Fig 7.

Interrupt sources, interrupt enables, and power-down wake-up sources

002aab104

7.13 I/O ports

The P89LPC9408 has four I/O ports: Port 0 and Port 1 are 8-bit ports. Port 2 is a 5-bit port. Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in

Table 7 .

Table 7: Number of I/O pins available

Clock source Reset option

On-chip oscillator or watchdog oscillator No external reset (except during power-up)

External RST pin supported

Number of I/O pins

(not including LCD pins)

23

22

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Table 7: Number of I/O pins available …continued

Clock source Reset option

External clock input

Low/medium/high speed oscillator

(external crystal or resonator)

No external reset (except during power-up)


[1]

No external reset (except during power-up)


[1]

Number of I/O pins

(not including LCD pins)

22

21

21

20

[1] Required for operation above 12 MHz.

7.13.1 Port configurations

All but three I/O port pins on the P89LPC9408 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin.

1. P1.5 (RST) can only be an input and cannot be configured.

2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or open-drain.

7.13.1.1

Quasi-bidirectional output configuration

Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC9408 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to V

DD

, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression circuit.

7.13.1.2

Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V

DD

.

An open-drain port pin has a Schmitt trigger input that also has a glitch suppression circuit.

7.13.1.3

Input-only configuration

The input-only port configuration has no output drivers. It is a Schmitt trigger input that also has a glitch suppression circuit.

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7.13.1.4

Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt trigger input that also has a glitch suppression circuit.

7.13.2 Port 0 analog functions

The P89LPC9408 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-Only

(high-impedance) mode.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.

On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.

7.13.3 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.

• After power-up, all I/O pins except P1.5, may be configured by software.

• Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only or open-drain.

Every output on the P89LPC9408 has been designed to sink typical LED drive current.

However, there is a maximum total output current for all ports which must not be exceeded. Please refer to


for detailed specifications.

All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

7.14 Power monitoring functions

The P89LPC9408 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and Brownout detect.

7.14.1 Brownout detection

The Brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a Brownout detection to cause a processor reset, however it may alternatively be configured to generate an interrupt.

Brownout detection may be enabled or disabled in software.

If Brownout detection is enabled the brownout condition occurs when V

DD

falls below the brownout trip voltage, V bo

(see


), and is negated when V

DD

rises above V bo

. If the P89LPC9408 device is to operate with a power supply

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4 LCD driver, 10-bit ADC that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating.

For correct activation of Brownout detect, the V

DD

rise and fall times must be observed.

Please see


for specifications.

7.14.2 Power-on detection

The Power-on detect has a function similar to the Brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where

Brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.

7.15 Power reduction modes

The P89LPC9408 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.

7.15.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

7.15.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The

P89LPC9408 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage V

RAM

.

This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after V

DD

has been lowered to V

RAM

, therefore it is highly recommended to wake up the processor via reset in this case. V

DD

must be raised to within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, Comparators (note that Comparators can be powered-down separately), and RTC/System Timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.

7.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down.

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7.16 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,

P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

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Remark: During a power-up sequence, the RPE selection is overridden and this pin will always function as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset.

After power-up this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user configured via UCFG1).

• Power-on detect.

• Brownout detect.

• Watchdog timer.

• Software reset.

• UART break character detect reset.

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:

• During a power-on reset, both POF and BOF are set but the other flag bits are cleared.

• For any other reset, previously set flag bits that have not been cleared will remain set.

7.16.1 Reset vector

Following reset, the P89LPC9408 will fetch instructions from either address 0000H or the

Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address = 00H.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot

Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see

P89LPC9408 User manual). Otherwise, instructions will be fetched from address 0000H.

7.17 Timers/counters 0 and 1

The P89LPC9408 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer overflow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle.

Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different.

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7.17.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a

13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

7.17.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

7.17.3 Mode 2

Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.

7.17.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

7.17.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

7.17.6 Timer overflow toggle output

Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.

7.18 RTC/system timer

The P89LPC9408 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered-down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a

16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter can be either the

CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the RTC and its associated

SFRs to the default state.

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7.19 CCU

This unit features:

• A 16-bit timer with 16-bit reload on overflow.

• Selectable clock, with prescaler to divide clock source by any integral number between 1 and 1024.

• Four compare/PWM outputs with selectable polarity

• Symmetrical/asymmetrical PWM selection

• Two capture inputs with event counter and digital noise rejection filter

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• Seven interrupts with common interrupt vector (one Overflow, two Capture, four Compare)

• Safe 16-bit read/write via shadow registers.

7.19.1 CCU Clock (CCUCLK)

The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of a PLL. The PLL is designed to use a clock source between 0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode

(asymmetrical or symmetrical). The PLL contains a 4-bit divider to help divide PCLK into a frequency between 0.5 MHz and 1 MHz.

7.19.2 CCU clock prescaling

This CCUCLK can further be divided down by a prescaler. The prescaler is implemented as a 10-bit free-running counter with programmable reload at overflow.

7.19.3 Basic timer operation

The timer is a free-running up/down counter with a direction control bit. If the timer counting direction is changed while the counter is running, the count sequence will be reversed. The timer can be written or read at any time.

When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt generated if enabled. The 16-bit CCU Timer may also be used as an 8-bit up/down timer.

7.19.4 Output compare

There are four output compare channels A, B, C and D. Each output compare channel needs to be enabled in order to operate and the user will have to set the associated I/O pin to the desired output mode to connect the pin. When the contents of the timer matches that of a capture compare control register, the Timer Output Compare Interrupt Flag

(TOCFx) becomes set. An interrupt will occur if enabled.

7.19.5 Input capture

Input capture is always enabled. Each time a capture event occurs on one of the two input capture pins, the contents of the timer is transferred to the corresponding 16-bit input capture register. The capture event can be programmed to be either rising or falling edge triggered. A simple noise filter can be enabled on the input capture by enabling the Input

Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event. An event counter can be set to delay a capture by a number of capture events.

7.19.6 PWM operation

PWM operation has two main modes, symmetrical and asymmetrical.

In asymmetrical PWM operation the CCU Timer operates in down-counting mode regardless of the direction control bit.

In symmetrical mode, the timer counts up/down alternately. The main difference from basic timer operation is the operation of the compare module, which in PWM mode is used for PWM waveform generation.

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As with basic timer operation, when the PWM (compare) pins are connected to the compare logic, their logic state remains unchanged. However, since bit FCOx is used to hold the halt value, only a compare event can change the state of the pin.

TOR2 compare value timer value

0x0000 non-inverted inverted

002aaa893

Fig 8.

Asymmetrical PWM, down-counting

TOR2 compare value timer value

0 non-inverted inverted

Fig 9.

Symmetrical PWM

002aaa894

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7.19.7 Alternating output mode

In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating pairs for bridge drive control. In this mode the output of these PWM channels are alternately gated on every counter cycle.

TOR2

COMPARE VALUE A (or C)

COMPARE VALUE B (or D)

TIMER VALUE

0

PWM OUTPUT (OCA or OCC)

002aaa895

PWM OUTPUT (OCB or OCD)

Fig 10. Alternate output mode

7.19.8 PLL operation

The PWM module features a Phase Locked Loop that can be used to generate a

CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or higher. The PLL is fed an input signal of 0.5 MHz to 1 MHz and generates an output signal of 32 times the input frequency. This signal is used to clock the timer. The user will have to set a divider that scales PCLK by a factor of 1 to 16. This divider is found in the SFR register TCR21. The PLL frequency can be expressed as shown in

Equation 1

.

PLL frequency =

(

------------------

N + 1

)

Where: N is the value of PLLDV3:0.

(1)

Since N ranges in 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK ⁄

16

.

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7.19.9 CCU interrupts

There are seven interrupt sources on the CCU which share a common interrupt vector.

EA (IEN0.7)

ECCU (IEN1.4)

TOIE2 (TICR2.7)

TOIF2 (TIFR2.7)

TICIE2A (TICR2.0)

TICF2A (TIFR2.0)

TICIE2B (TICR2.1)

TICF2B (TIFR2.1)

TOCIE2A (TICR2.3)

TOCF2A (TIFR2.3)

TOCIE2B (TICR2.4)

TOCF2B (TIFR2.4)

TOCIE2C (TICR2.5)

TOCF2C (TIFR2.5)

TOCIE2D (TICR2.6)

TOCF2D (TIFR2.6) other interrupt sources interrupt to

CPU

PRIORITY

ENCODER

ENCINT.0

ENCINT.1

ENCINT.2

002aaa896

Fig 11. CCU interrupts

7.20 UART

The P89LPC9408 has an enhanced UART that is compatible with the conventional 80C51

UART except that Timer 2 overflow cannot be used as a baud rate source. The

P89LPC9408 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent

Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.

7.20.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 1 ⁄

16

of the CPU clock frequency.

7.20.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),

8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in

Section 7.20.5

“Baud rate generator and selection” ).

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7.20.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9 th data bit, and a stop bit (logic 1). When data is transmitted, the 9 th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.

Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9 th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either 1 ⁄

16

or 1 ⁄

32

of the CPU clock frequency, as determined by the SMOD1 bit in PCON.

7.20.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9 th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in

Section 7.20.5 “Baud rate generator and selection” ).

7.20.5 Baud rate generator and selection

The P89LPC9408 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as

Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see

Figure 12 ). Note

that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses OSCCLK.

timer 1 overflow

(PCLK-based)

SMOD1 = 1

÷

2

SMOD1 = 0 baud rate generator

(CCLK-based)

Fig 12. Baud rate sources for UART (Modes 1, 3)

SBRGS = 0 baud rate modes 1 and 3

SBRGS = 1

002aaa897

7.20.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are set up when SMOD0 is logic 0.

7.20.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.

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7.20.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to

SBUF while the previous data is being shifted out. Double buffering is only allowed in

Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled

(DBMOD = 0).

7.20.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the TX interrupt is generated when the double buffer is ready to receive new data.

7.20.10 The 9 th bit (bit 8) in double buffering (modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TX interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.

7.21 I

2

C-bus serial interface

The I 2 C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multi master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer

• The I 2 C-bus may be used for test and diagnostic purposes.

A typical I 2 C-bus configuration is shown in

Figure 13 . The P89LPC9408 device provides a

byte-oriented I 2 C-bus interface that supports data transfers up to 400 kHz.

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RPU RPU

I

2

C-bus

P1.3/SDA P1.2/SCL

I 2 C MCU

OTHER DEVICE

WITH I

2

C-BUS

INTERFACE

OTHER DEVICE

WITH I

2

C-BUS

INTERFACE

002aab410

SDA

SCL

Fig 13. I 2 C-bus configuration

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P1.3/SDA

P1.2/SCL

8

ADDRESS REGISTER I2ADR

P1.3

COMPARATOR

INPUT

FILTER

OUTPUT

STAGE

INPUT

FILTER

OUTPUT

STAGE

P1.2

SHIFT REGISTER

8

ACK

I2DAT

BIT COUNTER /

ARBITRATION &

SYNC LOGIC TIMING

AND

CONTROL

LOGIC

SERIAL CLOCK

GENERATOR timer 1 overflow

I2CON

I2SCLH

I2SCLL

CONTROL REGISTERS &

SCL DUTY CYCLE REGISTERS

8

CCLK interrupt status bus

STATUS

DECODER

I2STAT STATUS REGISTER

8

002aaa899

Fig 14. I 2 C-bus serial interface block diagram - P89LPC9408

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7.22 SPI

The P89LPC9408 provides another high-speed serial communication interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in

Master mode or up to 3 Mbit/s in Slave mode. It has a transfer completion flag and write collision flag protection.

CPU clock

DIVIDER

BY 4, 16, 64, 128

SELECT

SPI clock (master)

8-BIT SHIFT REGISTER

READ DATA BUFFER clock

CLOCK LOGIC

S

M

M

S

PIN

CONTROL

LOGIC

MISO

P2.3

MOSI

P2.2

SPICLK

P2.5

S

M

MSTR

SPEN SPI CONTROL

SPI STATUS REGISTER

SPI interrupt request

SPI CONTROL REGISTER internal data bus

002aab466

Fig 15. SPI block diagram

The SPI interface has three pins: SPICLK, MOSI, and MISO:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,

SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.

Typical connections are shown in

Figure 16

through

Figure 18 .

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7.22.1 Typical SPI configurations master

8-BIT SHIFT

REGISTER

SPI CLOCK

GENERATOR

MISO

MOSI

SPICLK

SS/PORT

Fig 16. SPI single master single slave configuration

MISO

MOSI

SPICLK

SS/PORT slave

8-BIT SHIFT

REGISTER

002aab467 master

8-BIT SHIFT

REGISTER

SPI CLOCK

GENERATOR

MISO

MOSI

SPICLK

SS/PORT

MISO

MOSI

SPICLK

SS/PORT slave

8-BIT SHIFT

REGISTER

SPI CLOCK

GENERATOR

Fig 17. SPI dual device configuration, where either can be a master or a slave

002aab468

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4 LCD driver, 10-bit ADC master

8-BIT SHIFT

REGISTER

SPI CLOCK

GENERATOR

MISO

MOSI

SPICLK port

MISO

MOSI

SPICLK

SS slave

8-BIT SHIFT

REGISTER

MISO

MOSI slave

8-BIT SHIFT

REGISTER port

SPICLK

SS

002aaa903

Fig 18. SPI single master multiple slaves configuration

7.23 Analog comparators

Two analog comparators are provided on the P89LPC9408. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input

(selectable from a pin or an internal reference voltage). Otherwise the output is a zero.

Each comparator may be configured to cause an interrupt when the output value changes.

The overall connections to both comparators are shown in

Figure 19 . The comparators

function to V

DD

= 2.4 V.

When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.

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(P0.4) CIN1A

(P0.3) CIN1B

(P0.5) CMPREF

V ref(bg)

CP1 comparator 1

CO1

OE1 change detect

CN1

CMF1

CMP1 (P0.6) interrupt

CP2 comparator 2 change detect

CMF2

EC

(P0.2) CIN2A

(P0.1) CIN2B

CMP2 (P0.0)

CO2

OE2

CN2

Fig 19. Comparator input and output connections

002aaa904

7.23.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as

V ref(bg)

, is 1.23 V

±

10 %.

7.23.2 Comparator interrupt

Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt.

7.23.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via

PCONA.5, or put the device in Total Power-down mode.

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7.24 Keypad Interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag

(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use.

In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs.

7.25 Watchdog timer

The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable

12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt.

Figure 20 shows the watchdog timer in Watchdog mode.

Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few

µ s to a few seconds. Please refer to the

P89LPC9408 User manual for more details.

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WDL (C1H)

MOV WFEED1, #0A5H

MOV WFEED2, #05AH watchdog oscillator

PCLK

÷

32 PRESCALER

8-BIT DOWN

COUNTER

SHADOW REGISTER reset

(1)

WDCON (A7H) PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK

002aaa905

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence.

Fig 20. Watchdog timer in Watchdog mode (WDTE = 1)

7.26 Additional features

7.26.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.

7.26.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two

Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.

7.27 LCD controller

7.27.1 General description

The LCD segment driver in the P89LPC9408 can interface to most LCDs using low multiplex rates. It generates the drive signals for static or multiplexed LCDs containing up to four backplanes and up to 32 segments. The LCD controller communicates to a host using the I 2 C-bus. The I 2 C-bus clock and data signals for both the microcontroller and the

LCD controller are available on the P89LPC9408 providing system flexibility.

Communication overhead to manage the display is minimized by an on-chip display RAM with auto-increment addressing, hardware subaddressing, and display memory switching

(static and duplex drive modes).

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7.27.2 Functional description

The LCD controller is a versatile peripheral device designed to interface microcontrollers to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 32 segments. The display configurations possible with the

LCD controller depend on the number of active backplane outputs required. A selection of display configurations is shown in

Table 8 . All of these configurations can be implemented

in a typical system.

The microcontroller communicates to the LCD controller using the I 2 C-bus.The

appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.

The only other connections required to complete the system are to the power supplies

(V

DD

, V

SS

and V

LCD

) and the LCD panel chosen for the application.

3

2

1

Table 8: Selection of display configurations

Number of

Back Planes

4

Segments

128

7-Segments Numeric

Digits

16

Indicator

Symbols

16

96

64

32

12

8

4

12

8

4

6

4

2

14- Segments Alphanumeric

Characters Indicator

Symbols

8 16

12

8

4

Dot Matrix

128

96

64

32

7.27.3 LCD bias voltages

LCD biasing voltages are obtained from an internal voltage divider consisting of three series resistors connected between V

LCD

and V

SS

. The LCD voltage can be temperature compensated externally via the supply to pin V

LCD

. A voltage selector drives the multiplexing of the LCD based on programmable configurations.

7.27.4 Oscillator

An internal oscillator provides the clock signals for the internal logic of the LCD controller and its LCD drive signals. After power-up, pin SDA must be HIGH to guarantee that the clock starts.

7.27.5 Timing

The LCD controller timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division of the clock frequency from either the internal or an external clock.

Frame frequency = f

CLK

/24.

7.27.6 Display register

A display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the

LCD segment outputs, and each column of the display RAM.

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7.27.7 Segment outputs

The LCD drive section includes 32 segment outputs S0 to S31. The segment output signals are generated according to the multiplexed backplane signals and the display latch data. When less than 32 segment outputs are required, the unused segment outputs should be left open-circuit.

7.27.8 Backplane outputs

The LCD drive section has four backplane outputs BP0 to BP3. The backplane output signals are generated based on the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1:2 multiplex drive mode, BP0 and

BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements.

7.27.9 Display RAM

The display RAM is a static 32

×

4-bit RAM which stores LCD data. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 32 segments for backplane 0 (BP0). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively.

7.27.10 Data pointer

The Display RAM is addressed using the data pointer. Either a single byte or a series of display bytes may be loaded into any location of the display RAM.

7.27.11 Output bank selector

The LCD controller includes a RAM bank switching feature in the static and 1:2 drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This allows display information to be prepared in an alternative bank and then selected for display when it is assembled.

7.27.12 Input bank selector

The input bank selector loads display data into the display RAM based on the selected

LCD drive configuration. The BANK SELECT command can be used to load display data in bit 2 in static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector functions are independent of the output bank selector.

7.27.13 Blinker

The LCD controller has a very versatile display blinking capability. The whole display can blink at a frequency selected by the BLINK command. Each blink frequency is a multiple integer value of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected, as shown in

Table 9 .

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An additional feature allows an arbitrary selection of LCD segments to be blinked in the static and 1:2 drive modes. This is implemented without any communication overheads by the output bank selector which alternates the displayed data between the data in the display RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can also be implemented by the BLINK command.

The entire display can be blinked at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit E at the required rate using the

MODE SET command.

Table 9: Blinking frequencies

Blink mode Normal operating mode ratio Normal Blink frequency

Off

2 Hz

1 Hz

0.5 Hz

f osc(LCD)

/768 f osc(LCD)

/1536 f osc(LCD)

/3072

Blinking off

2 Hz

1 Hz

0.5 Hz

Blink modes 0.5 Hz, 1 Hz and 2 Hz, and nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator frequency (f osc(LCD)

) of 1536 Hz at pin CLK. The oscillator frequency range is 397 Hz to 3046 Hz.

7.27.13.1

I 2 C-bus controller

The LCD controller acts as an I 2 C-bus slave receiver. In the P89LPC9408 the hardware subaddress inputs A0, A,1 and A2 are tied to V

SS

setting the hardware subaddress = 0.

7.27.14 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.

7.27.15 I 2 C-bus slave addresses

The I 2 C-bus slave address is 0111 0000. The LCD controller is a write-only device and will not respond to a read access.

7.28 Data EEPROM

The P89LPC9408 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can read, write and fill the memory via SFRs and one interrupt. This Data EEPROM provides

100,000 minimum erase/program cycles for each byte.

• Byte Mode: In this mode, data can be read and written one byte at a time.

• Row Fill: In this mode, the addressed row (64 bytes) is filled with a single value. The entire row can be erased by writing 00H.

• Sector Fill: In this mode, all 512 bytes are filled with a single value. The entire sector can be erased by writing 00H.

After the operation finishes, the hardware will set the EEIF bit, which if enabled will generate an interrupt. The flag is cleared by software.

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7.29 Flash program memory

7.29.1 General description

The P89LPC9408 flash memory provides in-circuit electrical erasure and programming.

The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage.

On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC9408 flash reliably stores memory contents even after

100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC9408 uses V

DD

as the supply voltage to perform the Program/Erase algorithms.

7.29.2 Features

• Programming and erase over the full operating voltage range.

• Byte erase allows code memory to be used for data storage.

• Read/Programming/Erase using ISP/IAP/ICP.

• Internal fixed boot ROM, containing low-level IAP routines available to user code.

• Default loader providing ISP via the serial port, located in upper end of user program memory.

• Boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing flexibility to the user.

• Any flash program or erase operation in 2 ms.

• Programming with industry-standard commercial programmers.

• Programmable security for the code in the flash for each sector.

• 100,000 typical erase/program cycles for each byte.

• 10 year minimum data retention.

7.29.3 Flash organization

The program memory consists of eight 1 kB sectors on the P89LPC9408 device. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.

7.29.4 Using flash as data storage

The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.

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7.29.5 Flash programming and erasing

Four different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP) under control of the application’s firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock - serial data interface. As shipped from the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for the device to be programmed in circuit through the serial port. The flash may also be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire user code space.

7.29.6 In-Circuit Programming

In-Circuit Programming is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC9408 through a two-wire serial interface. The Philips ICP facility has made ICP in an embedded application—using commercially available programmers—possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature.

Additional details may be found in the P89LPC9408 User manual.

7.29.7 In-Application Programming

In-Application Programming is performed in the application under the control of the microcontroller’s firmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The Philips IAP has made IAP in an embedded application possible without additional components. Two methods are available to accomplish IAP. A set of predefined IAP functions are provided in a Boot ROM and can be called through a common interface, PGM_MTP. Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors, pages, security bits, configuration bytes, and device ID. These functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FF03H.

The Boot ROM occupies the program memory space at the top of the address space from

FF00H to FEFFH, thereby not conflicting with the user program memory space.

In addition, IAP operations can be accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC9408 User manual.

7.29.8 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC9408 through the serial port. This firmware is provided by Philips and embedded within each P89LPC9408 device. The Philips ISP facility has made ISP in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (V

DD

, V

SS

,

TXD, RXD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.

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7.29.9 Power-on reset code execution

The P89LPC9408 contains two special flash elements: the Boot Vector and the Boot

Status Bit. Following reset, the P89LPC9408 examines the contents of the Boot Status

Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code. When the Boot Status Bit is set to a value other than zero, the contents of the Boot Vector are used as the HIGH byte of the execution address and the LOW byte is set to 00H.

Table 10 shows the factory default Boot Vector settings for these devices. Note: These

settings are different than the original P89LPC932. Tools designed to support the

P89LPC9408 should be used to program this device, such as Flash Magic version

1.98, or later. A factory-provided boot loader is preprogrammed into the address space indicated and uses the indicated boot loader entry point to perform ISP functions. This code can be erased by the user. Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this boot loader. Instead, the page erase function can be used to erase the first eight 64-byte pages located in

this sector. A custom boot loader can be written with the Boot Vector set to the custom boot loader, if desired.

Table 10: Default Boot Vector values and ISP entry points

Device Default

Boot Vector

Default boot loader entry point

Default boot loader code range

P89LPC9408 1FH 1F00H 1E00H to 1FFFH

1 kB sector range

1C00H to 1FFFH

7.29.10 Hardware activation of the boot loader

The boot loader can also be executed by forcing the device into ISP mode during a power-on sequence (see the P89LPC9408 User manual for specific information). This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code but can be manually forced into ISP operation. If the factory default setting for the Boot Vector (1FH) is changed, it will no longer point to the factory preprogrammed ISP boot loader code. After programming the flash, the status byte should be programmed to zero in order to allow execution of the user’s application code beginning at address 0000H.

7.30 User configuration bytes

Some user-configurable features of the P89LPC9408 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1. Please see the P89LPC9408 User manual for additional details.

7.31 User sector security bytes

There are eight User Sector Security Bytes on the P89LPC9408 device. Each byte corresponds to one sector. Please see the P89LPC9408 User manual for additional details.

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8.

ADC

8.1 General description

The P89LPC9408 has a 10-bit, 8-channel multiplexed successive approximation analog-to-digital converter module. A block diagram of the ADC is shown in

Figure 21 .

The ADC consists of an 8-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.

8.2 Features

■ 10-bit, 8-channel multiplexed input, successive approximation ADC.

■ Eight result register pairs.

■ Six operating modes

◆ Fixed channel, single conversion mode

◆ Fixed channel, continuous conversion mode

◆ Auto scan, single conversion mode

◆ Auto scan, continuous conversion mode

◆ Dual channel, continuous conversion mode

◆ Single step mode

■ Three conversion start modes

◆ Timer triggered start

◆ Start immediately

◆ Edge triggered

■ 10-bit conversion time of 4

µ s at an ADC clock of 9 MHz

■ Interrupt or polled operation

■ High and Low Boundary limits interrupt; selectable in or out-of-range

■ Clock divider

■ Power-down mode

8.3 Block diagram

INPUT

MUX comp

+

–

DAC0

SAR

8

CONTROL

LOGIC

CCLK

002aab103

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8.4 ADC operating modes

8.4.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register pair which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes.

8.4.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the eight result register pairs. The user may select whether an interrupt can be generated after every four or every eight conversions.

Additional conversion results will again cycle through the result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user.

8.4.3 Auto scan, single conversion mode

Any combination of the eight input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel. The user may select whether an interrupt, if enabled, will be generated after either the first four conversions have occurred or all selected channels have been converted. If the user selects to generate an interrupt after the four input channels have been converted, a second interrupt will be generated after the remaining input channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode.

8.4.4 Auto scan, continuous conversion mode

Any combination of the eight input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel. The user may select whether an interrupt, if enabled, will be generated after either the first four conversions have occurred or all selected channels have been converted. If the user selects to generate an interrupt after the four input channels have been converted, a second interrupt will be generated after the remaining input channels have been converted. After all selected channels have been converted, the process will repeat starting with the first selected channel. Additional conversion results will again cycle through the eight result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user.

8.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the first channel is placed in the result register pair, AD0DAT0R and AD0DAT0L. The result of the conversion of the second channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The first channel is again converted and its result stored in AD0DAT2R and AD0DAT2L. The second channel is again converted and its result placed in AD0DAT3R and AD0DAT3L, etc. An interrupt is generated, if enabled, after every set of four or eight conversions (user selectable).

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8.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any combination of the eight input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the ADC waits for the next start condition. May be used with any of the start modes.

8.5 Conversion start modes

8.5.1 Timer triggered start

The ADC is started by the overflow of Timer 0. Once a conversion has started, additional

Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all ADC operating modes.

8.5.2 Start immediately

Programming this mode immediately starts a conversion.This start mode is available in all

ADC operating modes.

8.5.3 Edge triggered

The ADC is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all ADC operating modes.

8.6 Boundary limits interrupt

The ADC has both a high and low boundary limit register. The user may select whether an interrupt is generated when the conversion result is within (or equal to) the high and low boundary limits or when the conversion result is outside the boundary limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt criteria. The boundary limit may be disabled by clearing the boundary limit interrupt enable.

An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits. In this case, after the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits) an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt criteria, the boundary limits will again be compared after all 8 MSBs have been converted.

A boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt.

8.7 Clock divider

The ADC requires that its internal clock source be in the range of 500 kHz to 3 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose.

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In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit

Idle mode when the conversion is completed if the ADC interrupt is enabled. In

Power-down mode or Total Power-down mode, the ADC does not function. If the ADC is enabled, it will consume power. Power can be reduced by disabling the ADC.

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9.

Limiting values

Table 11: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions

T amb(bias)

T stg

I

OH(I/O) bias ambient temperature storage temperature

I

OL(I/O)

HIGH-state output current per input/output pin

LOW-state output current per input/output pin

I

I/Otot(max) maximum total input/output current

V

P n tot(pack) voltage on any other pin except V

SS

, with respect to

V

DD total power dissipation (per package) based on package heat transfer, not device power consumption

-

-

-

-

-

Min

−

55

−

65

Max

+125

+150

20

20

100

3.5

1.5

Unit

°

C

°

C mA mA mA

V

W

[1] The following applies to

Table 11 :

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

SS

unless otherwise noted.

10. Static characteristics

(dV/dt) r

(dV/dt) f

V

DDR

V th(HL)

V

IL

V th(LH)

V

IH

V hys

Table 12: Static electrical characteristics

V

DD

T amb

= 2.4 V to 3.6 V unless otherwise specified.

= − 40 ° C to +85 ° C for industrial applications, unless otherwise specified.


I

DD(oper) operating supply current

[2]

-

Min

I

DD(idle)

Idle mode supply current

V

DD

= 3.6 V; f osc

= 12 MHz

V

DD

= 3.6 V; f osc

= 18 MHz

3.6 V; 12 MHz

[2]

[2]

-

-

3.6 V; 18 MHz

[2]

-

I

I

DD(pd)

DD(tpd)

Power-down mode supply current total Power-down mode supply current voltage comparators powered down;

V

DD

= 3.6 V

V

DD

= 3.6 V

[2]

-

[3]

rise rate fall rate data retention supply voltage

HIGH-LOW threshold voltage

LOW-state input voltage

LOW-HIGH threshold voltage

HIGH-state input voltage hysteresis voltage of V

DD of V

DD except SCL, SDA

SCL, SDA only except SCL, SDA

SCL, SDA only port 1

-

-

1.5

-

0.22V

DD

−

0.5

-

0.7V

DD

Typ

[1]

11

17

3.7

6

60

Max

15

23

5

8

85

9

-

-

-

-

0.4V

DD

-

0.6V

DD

0.2V

DD

25

µ

A

2

-

50

-

V

+0.3V

DD

V

0.7V

DD

V

5.5

V mV/

µ s mV/

µ s

V

V

Unit mA mA mA mA

µ

A

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Table 12: Static electrical characteristics …continued

V

DD

T amb

= 2.4 V to 3.6 V unless otherwise specified.



V

OL

LOW-state output voltage

[4]

-

Min

I

OL

= 20 mA;

V

DD

= 2.4 V to 3.6 V, all ports, all modes except high-Z

[4]

-

V

OH

HIGH-state output voltage

I

OL

= 3.2 mA; V

DD

= 2.4 V to 3.6 V; all ports; all modes except high-Z

I

OH

=

−

20

µ

A;

V

DD

= 2.4 V to 3.6 V; all ports; quasi-bidirectional mode

I

OH

=

−

3.2 mA;

V

DD

= 2.4 V to 3.6 V; all ports; push-pull mode

V

V

DD

DD

Typ

0.6

0.2

−

0.3

V

DD

−

0.7

V

DD

[1]

−

0.2 -

−

0.4 -

Max

1.0

0.3

V

V xtal n crystal voltage voltage on any other pin with respect to V

SS except XTAL1, XTAL2, V

DD

; with respect to V

SS

−

0.5

−

0.5

-

+4.0

+5.5

I

C

IL i

I

LI

I

THL

R

RST_N(int) input capacitance

LOW-state input current input leakage current

V

I

= 0.4 V

V

I

= V

IL or V

IH

HIGH-LOW transition current V

I

= 1.5 V at V

DD

= 3.6 V internal pull-up resistance on pin RST_N

[5]

-

[6]

-

[7]

[8]

-

−

30

10 -

-

-

-

15

−

80

±

10

−

450

30

V bo brownout trip voltage 2.4 V < V

DD

< 3.6 V; with

BOE = 1, BOPD = 0

2.40

2.70

V ref(bg)

TC bg band gap reference voltage band gap temperature coefficient

-

1.11

1.23

10

1.34

20

Unit

V

V

V

V

V pF

µ

A

µ

A

µ

A k

Ω

V

V ppm/

°

C

[1] Typical ratings are not guaranteed. The values listed are at room temperature, V

DD

= 3 V.

[2] The I

DD(oper)

, I

DD(idle)

, and I

DD(pd) specifications are measured using an external clock with the following functions disabled: comparators, real-time clock, and watchdog timer.

[3] The I

DD(tpd)

specification is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect, and watchdog timer.

[4] See

Section 9 “Limiting values” on page 53

for steady state (non-transient) limits on I

OL

or I

OH

. If I

OL

/I

OH

exceeds the test condition,

V

OL

/V

OH

may exceed the related specification.

[5] Pin capacitance is characterized but not tested.

[6] Measured with port in quasi-bidirectional mode.

[7] Measured with port in high-impedance mode.

[8] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when V

I

is approximately 2 V.

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11. Dynamic characteristics

Table 13: Dynamic characteristics (12 MHz)

V

DD

T amb

= 2.4 V to 3.6 V, unless otherwise specified.

=

−

40

°

C to +85

°

C for industrial applications, unless otherwise specified.

[1] [2]

Symbol Parameter Conditions Variable clock

Min Max t f osc(RC) f osc(WD) f osc internal RC oscillator frequency internal watchdog oscillator frequency oscillator frequency

T cy(clk) clock cycle time f

CLKLP

Glitch filter low-power select clock frequency see

Figure 23

t gr glitch rejection time sa signal acceptance time

P1.5/RST pin any pin except

P1.5/RST

P1.5/RST pin any pin except

P1.5/RST

7.189

320

0

83

0

-

-

125

50

50

15

-

-

7.557

520

12

-

8 t

External clock t

CHCX t

CLCX clock HIGH time clock LOW time t

CLCH clock rise time t

CHCL clock fall time

Shift register (UART mode 0) t t t

T

XLXL

QVXH

XHQX

XHDX serial port clock cycle time output data setup to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time t

XHDV input data valid to clock rising edge time

SPI interface f

SPI

T

SPICYC

SPI operating frequency slave master

SPI cycle time

SPILEAD slave master

SPI enable lead time slave t

SPILAG

SPI enable lag time slave see see

Figure 23

see

Figure 23

see see see see see see see

25

27

27

, see see

Figure 23

Figure 23

Figure 22

Figure 22

Figure 22

Figure 22

Figure 22

Figure 24

26 , 27

Figure 26

Figure 26

,

,

,

16T

13T

6

4

⁄

⁄

33

33

-

cy(clk) cy(clk)

-

-

150

0

-

CCLK

CCLK

250

250

T cy(clk)

− t

CLCX

T cy(clk)

− t

CHCX

T

8

8

-

-

-

cy(clk)

0

-

CCLK

+ 20

CCLK ⁄

-

-

⁄

6

4 f osc

= 12 MHz Unit

Min Max

7.189

7.557

MHz

320 520 kHz

-

-

-

-

-

-

MHz ns

MHz

-

-

125

50

33

33

-

-

1333

1083

-

-

150

0

-

500

333

250

250

50

15

-

-

-

-

8

8

-

-

103

0

-

2.0

3.0

-

-

-

ns ns ns ns ns ns ns ns ns ns ns ns ns

MHz

MHz ns ns ns ns

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Table 13: Dynamic characteristics (12 MHz) …continued

V

DD

T amb



[1] [2]


Min Max t

SPICLKH

SPICLK HIGH time see

Figure 24

,

25

,

26 , 27

master slave

2 ⁄

CCLK

3

⁄

CCLK

-

t

SPICLKL

SPICLK LOW time master see

Figure 24

,

25

,

26 , 27

t

SPIDSU

2

⁄

CCLK

3 ⁄

CCLK

100

-

t t t t

SPIDH

SPIA

SPIDIS

SPIDV slave

SPI data setup time

SPI data hold time see

Figure 24

,

25

,

26 , 27

see

Figure 24

,

25

,

26 , 27

SPI access time see

Figure 26

,

27

slave

SPI disable time see

Figure 26

,

27

slave

SPI enable to output data valid time see

Figure 24

, slave

25

,

26 , 27

master

100

0

0

-

-

-

120

240

240

167 t t

SPIOH

SPIR

SPI output data hold time see

Figure 24

,

25

,

26 , 27

see

Figure 24

,

25

,

26 , 27

0

-

-

100 t

SPIF

SPI rise time

SPI outputs

(SPICLK, MOSI, MISO)

SPI inputs (SPICLK, MOSI, MISO)

SPI fall time

SPI outputs

(SPICLK, MOSI, MISO)

SPI inputs (SPICLK, MOSI, MISO) see

25

,

Figure 24

26 , 27

,

-

-

2000

100

2000

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

165

250

100

100 f osc

= 12 MHz Unit

Min Max

165

250

-

ns ns

-

-

ns ns ns

ns

0

-

-

-

0

120 ns

240 ns

240 ns

167 ns

ns

-

-

-

100 ns

2000 ns

100 ns

2000 ns

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Table 14: Dynamic characteristics (18 MHz)

V

DD

T amb



[1] [2]


Min

7.189

Max

7.557

f osc(RC) f osc(WD) f osc

T cy(clk) internal RC oscillator frequency internal watchdog oscillator frequency oscillator frequency clock cycle time f

CLKLP

Glitch filter low-power select clock frequency see

Figure 23

t gr glitch rejection time P1.5/RST pin any pin except

P1.5/RST

320

0

55

0

-

-

520

18

-

8

50

15 t sa signal acceptance time P1.5/RST pin any pin except

P1.5/RST

125

50 -

t

External clock t

CHCX t

CLCX t

CLCH clock HIGH time clock LOW time clock rise time t

CHCL clock fall time

Shift register (UART mode 0)

T

XLXL t

QVXH serial port clock cycle time output data setup to clock rising edge time t

XHQX

XHDX output data hold after clock rising edge time input data hold after clock rising edge time see see see see see see see see

Figure 23

Figure 23

Figure 23

Figure 23

Figure 22

Figure 22

Figure 22

Figure 22

16T

13T

22

22

-

cy(clk) cy(clk)

-

-

T cy(clk)

− t

CLCX

T cy(clk)

− t

CHCX

T

5

5

-

cy(clk)

0

+ 20 t t t

XHDV f

SPI interface

SPI

SPI operating frequency slave master

T

SPICYC input data valid to clock rising edge time

SPILEAD

SPI cycle time slave master

SPI enable lead time

SPILAG slave

SPI enable lag time slave see

Figure 22

see

25

27

27

, see see

Figure 24

26 , 27

Figure 26

Figure 26

,

,

,

6

4 ⁄

⁄

150

0

-

CCLK

CCLK

250

250

-

-

-

CCLK

CCLK

⁄

-

-

⁄

6

4 f osc

= 18 MHz Unit

Min Max

7.189

7.557

MHz

320

-

-

-

520 kHz

-

-

-

MHz ns

MHz

-

-

125

50

22

22

-

-

888

722

-

-

150

0

-

333

222

250

250

50

15

-

-

-

-

5

5

-

-

75

0

-

3.0

4.5

-

-

-

ns ns ns ns ns ns ns ns ns ns ns ns ns

MHz

MHz ns ns ns ns

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Table 14: Dynamic characteristics (18 MHz) …continued

V

DD

T amb



[1] [2]


Min Max t

SPICLKH

SPICLK HIGH time see

Figure 24

,

25

,

26 , 27

master slave

2 ⁄

CCLK

3

⁄

CCLK

-

t

SPICLKL

SPICLK LOW time master see

Figure 24

,

25

,

26 , 27

t

SPIDSU

2

⁄

CCLK

3 ⁄

CCLK

100

-

t t t t

SPIDH

SPIA

SPIDIS

SPIDV slave

SPI data setup time

SPI data hold time see

Figure 24

,

25

,

26 , 27

see

Figure 24

,

25

,

26 , 27

SPI access time see

Figure 26

,

27

slave

SPI disable time see

Figure 26

,

27

slave

SPI enable to output data valid time see

Figure 24

, slave

25

,

26 , 27

master

100

0

0

-

-

-

80

160

160

111 t t

SPIOH

SPIR

SPI output data hold time see

Figure 24

,

25

,

26 , 27

see

Figure 24

,

25

,

26 , 27

0

-

-

100 t

SPIF

SPI rise time

SPI outputs (SPICLK, MOSI,

MISO)

SPI inputs (SPICLK, MOSI, MISO,

SS)

SPI fall time

SPI outputs (SPICLK, MOSI,

MISO)

SPI inputs (SPICLK, MOSI, MISO) see

25

,

Figure 24

26 , 27

,

-

-

2000

100

2000

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

111

167

100

100 f osc

= 18 MHz Unit

Min Max

111

167

-

ns ns

-

-

ns ns ns

ns

0

-

-

-

0

80 ns

160 ns

160 ns

111 ns

ns

-

100 ns

2000 ns

-

100 ns

2000 ns

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11.1 Waveforms

T

XLXL clock output data write to SBUF input data t

QVXH t

XHDV clear RI

0 valid t

XHQX t

XHDX

1 valid

2 3 valid valid

4 5 valid valid

6 valid

7 set TI valid set RI

002aaa906

Fig 22. Shift register mode timing

V

DD

−

0.5 V

0.45 V

0.2V

DD

0.2V

DD

+

0.9 V

−

0.1 V t

CHCL t

CLCX

T cy(clk) t

CHCX t

CLCH

002aaa907

Fig 23. External clock timing

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SS t

SPIF t

SPICLKH

T

SPICYC t

SPICLKL t

SPIR

SPICLK

(CPOL = 0)

(output) t

SPIF t

SPICLKL t

SPIR t

SPICLKH

SPICLK

(CPOL = 1)

(output)

MISO

(input) t

SPIDSU t

SPIDH

MSB/LSB in t

SPIDV

MOSI

(output) t

SPIF master MSB/LSB out t

SPIOH

LSB/MSB in t

SPIDV t

SPIR master LSB/MSB out

002aaa908

Fig 24. SPI master timing (CPHA = 0)

SS t

SPIF

T

SPICYC t

SPIR t

SPICLKL t

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPICLK

(CPOL = 1)

(output) t t

SPIF

SPICLKH

MISO

(input)

MOSI

(output) t

SPIF t

SPIDSU t

SPIDH

MSB/LSB in t

SPIDV master MSB/LSB out t

SPICLKL t

SPIOH t

SPIR

LSB/MSB in t

SPIDV t

SPIDV t

SPIR master LSB/MSB out

002aaa909

Fig 25. SPI master timing (CPHA = 1)

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SS t

SPIR t

SPILEAD t

SPIF t

SPICLKH

T

SPICYC t

SPICLKL t

SPIR

SPICLK

(CPOL = 0)

(input)

SPICLK

(CPOL = 1)

(input) t

SPIA

MISO

(output) t

SPIF t

SPICLKL t

SPIR t

SPICLKH t

SPIOH t

SPIDV slave MSB/LSB out

MOSI

(input) t

SPIDSU t

SPIDH

MSB/LSB in

Fig 26. SPI slave timing (CPHA = 0) t

SPIDSU t

SPIOH t

SPIDV t

SPILAG t

SPIR t

SPIOH slave LSB/MSB out not defined t

SPIDIS t

SPIDSU t

SPIDH

LSB/MSB in

002aaa910

SS t

SPIR t

SPILEAD

T

SPICYC t

SPIF t

SPICLKH t

SPICLKL t

SPIR

SPICLK

(CPOL = 0)

(input)

SPICLK

(CPOL = 1)

(input) t

SPIF t

SPICLKL t

SPIR t

SPICLKH t

SPIA

MISO

(output) t

SPIOH t

SPIDV not defined t

SPIOH t

SPIDV slave MSB/LSB out t

SPIOH t

SPIDV

MOSI

(input) t

SPIDSU t

SPIDH

MSB/LSB in t

SPILAG slave LSB/MSB out t

SPIR t

SPIDSU t

SPIDSU t

SPIDH

LSB/MSB in

002aaa911 t

SPIDIS

Fig 27. SPI slave timing (CPHA = 1)

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11.2 ISP entry mode

Table 15: Dynamic characteristics, ISP entry mode

V

DD

T amb


=

−

40

°

C to +85

°


Symbol Parameter Conditions Min t t

VR

RH t

RL

V

DD active to RST active delay time

RST HIGH time

RST LOW time

50

1

1 -

-

-

Typ

-

Max

-

32

Unit

µ s

µ s

µ s

V

DD t

VR t

RH

RST t

RL

Fig 28. ISP entry waveform

12. Other characteristics

12.1 Comparator electrical characteristics

Table 16: Comparator electrical characteristics

V

DD

T amb




V

V

IO

IC

CMRR t res(tot) t

(CE-OV)

I

LI input offset voltage common-mode input voltage common-mode rejection ratio total response time chip enable to output valid time input leakage current 0 V < V

I

< V

DD

-

-

Min

[1]

-

-

0

-

[1] This parameter is characterized, but not tested in production.

002aaa912

-

-

Typ

-

-

-

250

Max Unit

±

20 mV

V

DD

−

0.3

V

−

50 dB

500

10

±

10 ns

µ s

µ

A

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13. ADC electrical characteristics

E offset

E

G

E u(tot)

M

CTC

α ct(port)

SR in

T cy(ADC) t

ADC

Table 17: ADC electrical characteristics

V

DD

T amb


=

−

40

°

C to +85

°


All limits valid for an external source impedance of less than 10 k Ω .


V

IA analog input voltage

Min

V

SS

−

0.2

-

Typ

C ia analog input capacitance -

E

D

INL differential linearity error integral non-linearity -

-

-

offset error gain error total unadjusted error channel-to-channel matching crosstalk between port inputs input slew rate

ADC clock cycle time

ADC conversion time

0 kHz to 100 kHz

ADC enabled -

-

-

-

-

-

-

111 -

-

-

-

-

-

-

-

Max

3125

36T cy(ADC)

Unit

V

SS

+ 0.2

V

15

±

1

±

1

±

2

±

1

±

2

±

1

−

60

100 pF

LSB

LSB

LSB

%

LSB

LSB dB

V/ms ns

µ s

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14. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 14 x 14 x 1.4 mm SOT791-1 c y

X

A

49

48 33

32

ZE e w M bp

E

H

E A

A2

A1

L

Lp pin 1 index

16

17 detail X

64

1 e bp

D

H

D w M

ZD

B v M A v M B

0 5 scale

10 mm

DIMENSIONS (mm are the original dimensions)

UNIT

A max.

A

1

A

2

A

3 b p c mm 1.6

0.15

0.05

1.45

1.35

0.25

0.45

0.30

0.20

0.09

D

(1)

E

(1)

14.1

13.9

14.1

13.9

e H

D

H

E

0.8

16.15

15.85

16.15

15.85

L

1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

L p

0.75

0.45

v

0.2

w

0.2

y

0.1

Z

D

(1)

Z

E

(1)

1.2

0.8

1.2

0.8

θ

7 o

0 o

OUTLINE

VERSION

SOT791-1

IEC

136E18

REFERENCES

JEDEC JEITA

MS-026 ED-7311EC

EUROPEAN

PROJECTION

ISSUE DATE

02-10-22

θ

Fig 29. Package outline SOT791-1 (LQFP64)

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15. Abbreviations

ISP

LCD

LED

PWM

RAM

RC

SFR

SPI

UART

Table 18: Acronym list

Acronym

ADC

Description

Analog to Digital Converter

CPU

EPROM

EEPROM

EMI

Central Processing Unit

Erasable Programmable Read-Only Memory

Electrically Erasable Programmable Read-Only Memory

Electro-Magnetic Interference

In-System Programming

Liquid Crystal Display

Light Emitting Diode

Pulse Width Modulator

Random Access Memory

Resistance-Capacitance

Special Function Register

Serial Peripheral Interface

Universal Asynchronous Receiver/Transmitter

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16. Revision history

Table 19: Revision history

Document ID

P89LPC9408_1

Release date

20051216

Data sheet status

Product data sheet -

Change notice Doc. number

-

Supersedes

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17. Data sheet status

I

Level Data sheet status [1]

Objective data

Product status [2] [3]

Development

II

III

Preliminary data

Product data

Qualification

Production

Definition

This data sheet contains data from the objective specification for product development. Philips

Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

18. Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process

Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

20. Trademarks

19. Disclaimers

Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners.

I 2 C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors

21. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, send an email to: [email protected]

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22. Contents

1

2

2.1

2.2

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Principal features . . . . . . . . . . . . . . . . . . . . . . . 1

Additional features . . . . . . . . . . . . . . . . . . . . . . 1

3

3.1

4

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5

6

6.1

6.2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

Pinning information . . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Functional description . . . . . . . . . . . . . . . . . . 10

7.3.5

7.3.6

7.4

7.5

7.6

7.7

7.8

7.9

7.1

7.2

7.3

7.3.1

7.3.2

7.3.3

7.3.4

Special function registers . . . . . . . . . . . . . . . . 10

Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 19

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 19

CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 19

Low speed oscillator option . . . . . . . . . . . . . . 19

Medium speed oscillator option . . . . . . . . . . . 19

High speed oscillator option . . . . . . . . . . . . . . 19

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 20

On-chip RC oscillator option . . . . . . . . . . . . . . 20

Watchdog oscillator option . . . . . . . . . . . . . . . 20

External clock input option . . . . . . . . . . . . . . . 20

CPU Clock (CCLK) wake-up delay . . . . . . . . . 21

CCLK modification: DIVM register . . . . . . . . . 21

Low power select . . . . . . . . . . . . . . . . . . . . . . 21

7.10

7.11

7.12

7.12.1

Memory organization . . . . . . . . . . . . . . . . . . . 22

Data RAM arrangement . . . . . . . . . . . . . . . . . 22

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

External interrupt inputs . . . . . . . . . . . . . . . . . 23

7.13

7.13.1

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Port configurations . . . . . . . . . . . . . . . . . . . . . 25

7.13.1.1

Quasi-bidirectional output configuration . . . . . 25

7.13.1.2

Open-drain output configuration . . . . . . . . . . . 25

7.13.1.3

Input-only configuration . . . . . . . . . . . . . . . . . 25

7.13.1.4

Push-pull output configuration . . . . . . . . . . . . 26

7.13.2

7.13.3

Port 0 analog functions . . . . . . . . . . . . . . . . . . 26

Additional port features. . . . . . . . . . . . . . . . . . 26

7.14

7.14.1

7.14.2

7.15

Power monitoring functions. . . . . . . . . . . . . . . 26

Brownout detection . . . . . . . . . . . . . . . . . . . . . 26

Power-on detection . . . . . . . . . . . . . . . . . . . . . 27

Power reduction modes . . . . . . . . . . . . . . . . . 27

7.15.1

7.15.2

7.15.3

7.16

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Power-down mode . . . . . . . . . . . . . . . . . . . . . 27

Total Power-down mode . . . . . . . . . . . . . . . . . 27

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.16.1

7.17

7.17.1

7.17.2

7.17.3

7.17.4

7.17.5

7.17.6

7.18

7.19

7.19.1

7.19.2

7.19.3

7.19.4

7.19.5

7.22

7.22.1

7.23

7.23.1

7.23.2

7.23.3

7.24

7.25

7.26

7.26.1

7.26.2

7.27

7.27.1

7.27.2

7.27.3

Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Timers/counters 0 and 1 . . . . . . . . . . . . . . . . 28

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Timer overflow toggle output . . . . . . . . . . . . . 29

RTC/system timer. . . . . . . . . . . . . . . . . . . . . . 29

CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

CCU Clock (CCUCLK) . . . . . . . . . . . . . . . . . . 30

CCU clock prescaling . . . . . . . . . . . . . . . . . . . 30

Basic timer operation . . . . . . . . . . . . . . . . . . . 30

Output compare . . . . . . . . . . . . . . . . . . . . . . . 30

Input capture . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.19.6

7.19.7

7.19.8

7.19.9

7.20

7.20.1

7.20.2

7.20.3

PWM operation . . . . . . . . . . . . . . . . . . . . . . . 30

Alternating output mode . . . . . . . . . . . . . . . . . 32

PLL operation . . . . . . . . . . . . . . . . . . . . . . . . . 32

CCU interrupts . . . . . . . . . . . . . . . . . . . . . . . . 33

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.20.4

7.20.5

7.20.6

7.20.7

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Baud rate generator and selection . . . . . . . . . 34

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 34

Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.20.8

7.20.9

Double buffering . . . . . . . . . . . . . . . . . . . . . . . 35

Transmit interrupts with double buffering enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . 35

7.20.10

The 9 th

bit (bit 8) in double buffering

7.21

(modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . 35

I 2

C-bus serial interface . . . . . . . . . . . . . . . . . . 35

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Typical SPI configurations . . . . . . . . . . . . . . . 39

Analog comparators . . . . . . . . . . . . . . . . . . . . 40

Internal reference voltage. . . . . . . . . . . . . . . . 41

Comparator interrupt . . . . . . . . . . . . . . . . . . . 41

Comparators and power reduction modes . . . 41

Keypad Interrupt (KBI) . . . . . . . . . . . . . . . . . . 42

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 42

Additional features . . . . . . . . . . . . . . . . . . . . . 43

Software reset . . . . . . . . . . . . . . . . . . . . . . . . 43

Dual data pointers . . . . . . . . . . . . . . . . . . . . . 43

LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 43

General description . . . . . . . . . . . . . . . . . . . . 43

Functional description . . . . . . . . . . . . . . . . . . 44

LCD bias voltages . . . . . . . . . . . . . . . . . . . . . 44

continued >>

P89LPC9408_1



68 of 69


P89LPC9408


×


8

8.4.4

8.4.5

8.4.6

8.5

8.5.1

8.5.2

8.5.3

8.6

8.7

8.8

8.1

8.2

8.3

8.4

8.4.1

8.4.2

8.4.3

7.29

7.29.1

7.29.2

7.29.3

7.29.4

7.29.5

7.29.6

7.29.7

7.27.4

7.27.5

7.27.6

7.27.7

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Display register . . . . . . . . . . . . . . . . . . . . . . . . 44

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 45

7.27.8

7.27.9

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 45

Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.27.10

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.27.11

Output bank selector. . . . . . . . . . . . . . . . . . . . 45

7.27.12

Input bank selector . . . . . . . . . . . . . . . . . . . . . 45

7.27.13

Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.27.13.1 I 2

C-bus controller . . . . . . . . . . . . . . . . . . . . . . 46

7.27.14

Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.27.15

I 2

C-bus slave addresses . . . . . . . . . . . . . . . . . 46

7.28

Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . 46

Flash program memory. . . . . . . . . . . . . . . . . . 47

General description. . . . . . . . . . . . . . . . . . . . . 47

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Flash organization . . . . . . . . . . . . . . . . . . . . . 47

Using flash as data storage . . . . . . . . . . . . . . 47

Flash programming and erasing . . . . . . . . . . . 48

In-Circuit Programming. . . . . . . . . . . . . . . . . . 48

In-Application Programming . . . . . . . . . . . . . . 48

7.29.8

7.29.9

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Power-on reset code execution. . . . . . . . . . . . 49

7.29.10

Hardware activation of the boot loader . . . . . . 49

7.30

User configuration bytes . . . . . . . . . . . . . . . . . 49

7.31

User sector security bytes . . . . . . . . . . . . . . . 49

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

General description. . . . . . . . . . . . . . . . . . . . . 50

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 50

ADC operating modes . . . . . . . . . . . . . . . . . . 51

Fixed channel, single conversion mode . . . . . 51

Fixed channel, continuous conversion mode . 51

Auto scan, single conversion mode . . . . . . . . 51

Auto scan, continuous conversion mode . . . . 51

Dual channel, continuous conversion mode . . 51

Single step mode . . . . . . . . . . . . . . . . . . . . . . 52

Conversion start modes . . . . . . . . . . . . . . . . . 52

Timer triggered start . . . . . . . . . . . . . . . . . . . . 52

Start immediately . . . . . . . . . . . . . . . . . . . . . . 52

Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 52

Boundary limits interrupt. . . . . . . . . . . . . . . . . 52

Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Power-down and Idle mode . . . . . . . . . . . . . . 52

9

10

11

11.1

11.2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 53

Static characteristics. . . . . . . . . . . . . . . . . . . . 53

Dynamic characteristics . . . . . . . . . . . . . . . . . 55

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . 62

18

19

20

21

12

12.1

13

14

15

16

17

Other characteristics . . . . . . . . . . . . . . . . . . . 62

Comparator electrical characteristics . . . . . . . 62

ADC electrical characteristics . . . . . . . . . . . . 63

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 64

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 65

Revision history . . . . . . . . . . . . . . . . . . . . . . . 66

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 67

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Contact information . . . . . . . . . . . . . . . . . . . . 67

© Koninklijke Philips Electronics N.V. 2005

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Date of release: 16 December 2005

Document number: P89LPC9408_1

Published in the Netherlands

P89LPC9408

8-bit microcontroller with two-clock 80C51 core 8 kB 3 V byte-erasable flash, 32 segment

×

4 LCD driver, 10-bit ADC

1.

General description

2.

Features

3.

Ordering information

4.

Block diagram

5.

Functional diagram

6.

Pinning information

7.

Functional description

8.

ADC

9.

Limiting values

10. Static characteristics

11. Dynamic characteristics

12. Other characteristics

13. ADC electrical characteristics

14. Package outline

15. Abbreviations

16. Revision history

17. Data sheet status

18. Definitions

20. Trademarks

19. Disclaimers

21. Contact information

22. Contents

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