S29GL-S Page Mode Accesses AN

S29GL-S Page Mode Accesses AN
S29GL-S Page Mode Accesses
Application Note
1. Introduction
Today's high performance embedded systems are enabling richer user experiences; these new designs are
dramatically increasing system architecture complexity and requiring higher NVM densities to support today's
OS, Application, and digital data contents. Continued innovations are required to address competing system
requirements and provide highest performance capabilities without impacting other systems constraints like
cost or reliability. A typical high performance embedded system uses code shadowing architecture where the
system start-up is significantly defined by the shadowing and initialization times. The Host microcontroller and
flash read bandwidths directly impact the shadowing time. The market expectation is that a new system
design will improve system performance and enable faster system start-up time without impacting costs; slow
system responses and slow start-ups are typically perceived negatively and not acceptable in many
applications. Spansion's portfolio provides three baseline architectures of flash-memory devices supporting
different read access modes (Asynchronous, Page, and Burst) offering a range of read bandwidth capabilities
to address different performance requirements. This application note will focus on the application of
Spansion's cost effective high performance S29GL-S Page Mode Flash as a solution to improve read
bandwidth.
2. Page Mode Architecture
The flash internal architecture defines the supported read access modes; a given read mode provides an
expected range of read bandwidth (BW) performance. A Spansion® flash design can offer one or more of
three baseline read access modes: Asynchronous, Page, and Burst. Figure 2.1 illustrates how the typical
flash architecture complexity increases to support the faster read accesses or higher read BW.
Figure 2.1 Architecture Complexity
Flash Read Performance versus Architecture
Burst Access
Read Bandwidth
Page Access
Asynchronous Access
Architecture Complexity
Publication Number S29GL-S_Page_Mode_Accesses_AN
Revision 01
Issue Date August 19, 2014
A pplication
Note
Spansion flash featuring Page Read Mode offers the designer a straight forward, reliable and economical
solution to improve the flash read BW and key system attributes such as faster system start-up times and
overall system performance. For example, Spansion's S29GL-S supports both Asynchronous and Page Read
accesses supporting read BWs of up to 22 Mbytes/s for asynchronous accesses and 98.5 Mbytes/s for Page
accesses. The S29GL-S can support Page Read BWs that are greater than 4x faster than standard
Asynchronous Read BWs.
2.1
Page Mode Architecture
The Read Page Mode flash architecture enables significant Read BW improvements compared to
Asynchronous Read access performance. Below is a quick overview of the key details related to
Asynchronous and Page architectures and read processes. The S29GL-S Block Diagram in Figure 2.2
highlights the major functional blocks utilized in both Asynchronous and Page Read processes; key blocks
such as address decoder, cell matrix, data latch, and input / output buffers are referenced in the following
Asynchronous and Page Read discussions.
An Asynchronous Architecture supports a basic read access to a single word stored in the cell matrix and its
read performance is derived from the initial read access time. The initial access defines the time (tACC) for the
flash to complete the read process which includes: an address decode (A0:Amax), capture of a single word
from the flash cell matrix, and transferring the subject word to the flash output buffer.
Figure 2.2 S29GL-S Block Diagram
DQ15–DQ0
RY/BY#
VCC
Sector Switches
VSS
VIO
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
AMax**–A0
Address Latch
Timer
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
STB
VCC Detector
STB
The flash Page Mode architecture is more complex than simple asynchronous flash; a Page Mode flash
supports reading a group or page of words stored in the cell matrix and its read performance is derived from
the initial read access and subsequent intra-page read times. A Page Read initial access defines the time
(tACC) for the flash to complete the initial read process including address decode (A0:Amax), capturing a page
of words from the flash cell matrix into flash internal buffers, and transferring the first word to the flash output
buffer. Subsequent intra-page read accesses to other words in the same page boundary are completed in
time tPACC which is much faster than tACC.
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Another key aspect of Page Mode architecture is the page boundary size which is defined for each Page flash
design. For example, all S29GL-S densities (128 Mb to 1 Gb) support 16-word page size. The Page boundary
addresses are selected by the higher address bits A4-Amax. The LSB address bits A0-A3 (in word mode)
select the specific word within a page boundary. Table 2.1 highlights the intra-page addressing (A0:A3) for a
16-word page size:
Table 2.1 Example Intra-Page Addressing — S29GL-S
Word / Addressing
A3
A2
A1
A0
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
……..
…….
………
…….
……..
12
1
1
0
1
1
1
0
0
13
1
1
14
1
1
1
0
15
1
1
Figure 2.3 illustrates a S29GL-S initial and intra-page read access timing diagram. During the initial read
access CE# and OE# must go to VIL, and a valid address must be placed on Amax:A0. The first read has an
access time tACC or tCE which are the same as a standard asynchronous read. Subsequent intra-page reads
are completed in time tPACC. The intra-page reads are completed by keeping A4-Amax constant and
changing A0-A3 to select the specific word within that page boundary.
The S29GL-S data sheet shows the speed grade option for the initial read access and the intra-Page Read
accesses as tACC: 90 ns to 120 ns and tPACC: 15 ns to 30 ns. Using a S29GL-S which supports tACC = 90 ns
and tPACC = 20 ns; Figure 2.3 shows that the initial access time of 90 ns is required to complete the first read
from a given page, and each subsequent intra-Page Read is only 20 ns. Given that tPACC << tACC, it is clear
that utilizing the Page Mode feature can significantly improve read BWs over standard asynchronous reads.
Figure 2.3 Page Read Timing Diagram
tACC
Amax-A4
A3-A0
tCE
CE#
tOE
OE#
tPACC
DQ15-DQ0
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2.2
Note
Host Microcontroller Page Mode Accesses
The main objective and focus for utilizing Page Read mode is to enable higher read BWs of data transfers
from flash to host microcontroller. The Page Read access does require the system or host processor memory
interface controller to support the page boundary addressing and dynamic wait states adjustments to
complete initial page access and subsequent intra-page accesses. Freescale's MPC, i.MX, TI's OMAP™, and
other host microcontrollers have integrated control logic that enables seamless interface of their local bus
interfaces to Spansion's S29GL-S and achieve page read capabilities. For example, the Freescale™ i.MX6
WIEM controller can be directly interfaced to S29GL-S flash supporting either Asynchronous or Page Mode
read accesses. The following provides a quick overview of the Freescale i.MX6 and S29GL-S page read
features followed by example Asynchronous and Page Read accesses.
iMX6 Overview:
 Asynchronous Access: Single word
 Page Access options: 2, 4, 8, 16, or 32 words (cache size should match flash Page size)
 EIM Main Clock: Maximum frequency 133 MHz
 Flexible Read and Write Access Timing
Freescale's i.MX6 data sheet and reference manuals detail the internal EIM clocking options for adjusting the
initial access and Page access times.
S29GL-S Page Access:
 16-word Page Boundary
 Initial Access: tACC options from 90 ns to 120 ns
Best case Asynchronous read BW: ~22 MB/s excluding SOC setup and hold times
 Page Read Access: tPACC options from 15 ns to 30 ns
Best case Page read BW ~98.5 MB/s excluding SOC setup and hold times
Figure 2.4 and Figure 2.5 below illustrate i.MX6 and S29GL-S Asynchronous and Page read accesses.
General Guidelines:
S29GL-S device supports tACC = 110 ns and tPACC = 15 ns
The i.MX6:
 EIM Clock ~133 MHz
 Access Timing: tACC ~ 135 ns and tPACC ~22.5 ns
Figure 2.4 shows the time to complete a single asynchronous word read access required ~158 ns, which
provides a Read BW of ~13 MB/s.
Figure 2.4 iMX6 / S29GL-S Asynchronous Read Access
3
6
9
12
15
18
21
Total Access (ns)
23
45
68
90
113
135
158
Initial Access (ns)
0
23
45
68
90
113
Clock Cycles
HClk
CE#
Addr
Address Valid: A23:A0
Data
Data 0
OE#
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Figure 2.5 shows the time to complete a 16-word Page Read requires ~474 ns, which provides a Read BW of
~68 MB/s. These results shows the Page Read BW of 68 Mbytes/s is ~5X faster than the Asynchronous
Read BW of ~13 Mbytes/s.
Figure 2.5 iMX6 / S29GL-S Page Read Access
3
Clock Cycles
Total Access (ns)
Initial Access (ns)
0
23
0
6
9
12
15
18
21
24
27
30 …. 57
60
63
45
68
90
113
135
158
180
203
226
451
474
90
113
+2
+4
+6
23
45
68
429
HClk
CE#
Addr: A23: A24
Addr: A3:A0
Page Address
Intra Page Address +0
+28
+8
+30
OE#
Data Word
0
1
2
3
4
14
15
Microcontroller providers sometimes offer scripts to perform DMA transfers of large blocks of data from flash
to DDR. Note the i.MX6 continuous Read BW using a DMA process is less than 68 MB/s. The i.MX6
architecture completes the DMA process in two independent steps or time sequences:
 First the transfer of flash data to i.MX6 internal memory.
 Second transferring data in its internal memory to DDR.
 These process steps are repeated until the defined block of data transfer is complete. These two steps are
not processed simultaneously.
In addition to providing improved Read BW performance; the S29GL-S Page Mode Flash provides a second
order benefit: lower flash power consumption during intra-page reads. The intra-Page Read currents are
significantly less than standard active Read current levels; each intra-Page Read access reduces the time the
flash is operating at the higher active read current levels. For example, the S29GL-S flash supports the
following typical Read currents: ICC1 standard active Read of 55 mA and ICC2 intra-Page Read current of
9 mA. ICC1 is six times greater than ICC2. Clearly, reading a 16-word page utilizing Page Read capabilities will
consume less energy than reading each of the 16 words asynchronously.
3. Summary
Many high speed embedded systems continue to increase in terms of complexity, performance and required
code size to support a richer user experience. These designs require continued innovation to address
competing system requirements to provide highest performance capabilities without impacting other system
constraints like cost or reliability. For example, a typical high performance embedded system uses code
shadowing memory architecture. The system start-up time is directly related to the read BW to transfer data
from flash to the host microcontroller to complete the shadowing process.
Spansion Page Mode Flash, like the S29GL-S family, provides a cost effective high performance solution to
significantly improve read BWs versus standard asynchronous accesses. There are a number of host
microcontrollers like the i.MX6 which can be directly interfaced to S29GL-S Page Mode Flash and support
complementing Page Read capabilities enabling enhanced read performance. The exact read BW
performance obtained in a particular design depends on the processor and the configuration setups.
Spansion S29GL-S Page Mode capabilities provide a straight forward and cost efficient solution to
significantly improve read BWs compared to standard asynchronous read accesses.
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A pplication
Note
4. Revision History
Section
Description
Revision 01 (August 19, 2014)
Initial release
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Colophon
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