Xilinx Zynq-7000 XC7Z030, XC7Z045, XC7Z100 SoC Preliminary Product Specification

Zynq-7000 All Programmable SoC
(XC7Z030, XC7Z045, and XC7Z100):
DC and AC Switching Characteristics
Preliminary Product Specification
DS191 (v1.4) April 24, 2013
Introduction
Zynq™-7000 All Programmable SoCs are available in -3, -2,
and -1 speed grades, with -3 having the highest
performance. Zynq-7000 device DC and AC characteristics
are specified in commercial, extended, and industrial
temperature ranges. Except the operating temperature
range or unless otherwise noted, all the DC and AC
electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a -1 speed grade
industrial device are the same as for a -1 speed grade
commercial device). However, only selected speed grades
and/or devices are available in the commercial, extended, or
industrial temperature ranges.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
This Zynq-7000 AP SoC (XC7Z030, XC7Z045, and
XC7Z100) data sheet, part of an overall set of
documentation on the Zynq-7000 devices, is available on
the Xilinx website at www.xilinx.com/zynq. All specifications
are subject to change without notice.
DC Characteristics
Table 1: Absolute Maximum Ratings (1)
Symbol
Description
Min
Max
Units
Processing System (PS)
VCCPINT
PS primary logic supply
–0.5
1.1
V
VCCPAUX
PS auxiliary supply voltage
–0.5
2.0
V
VCCPLL
PS PLL supply
–0.5
2.0
V
VCCO_DDR
PS DDR I/O supply
–0.5
2.0
V
VCCO_MIO(2)
PS MIO I/O supply
–0.5
3.6
V
VPREF
PS input reference voltage
–0.5
2.0
V
VPIN(2)(3)(4)(5)
PS MIO I/O input voltage
–0.40
VCCO_MIO + 0.55
V
PS DDR I/O input voltage
–0.55
VCCO_DDR + 0.55
V
Programmable Logic (PL)
VCCINT
PL internal supply voltage
–0.5
1.1
V
VCCAUX
PL auxiliary supply voltage
–0.5
2.0
V
VCCBRAM
PL supply voltage for the block RAM memories
–0.5
1.1
V
PL output drivers supply voltage for 3.3V HR I/O banks
–0.5
3.6
V
PL output drivers supply voltage for 1.8V HP I/O banks
–0.5
2.0
V
VCCAUX_IO
Auxiliary supply voltage
–0.5
2.06
V
VREF
Input reference voltage
–0.5
2.0
V
I/O input voltage for 3.3V HR I/O banks
–0.40
VCCO + 0.55
V
I/O input voltage for 1.8V HP I/O banks
–0.55
VCCO + 0.55
V
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards
except TMDS_33(6)
–0.40
2.625
V
VCCO
VIN
(3)(4)(5)
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in the United States and other countries. AMBA, AMBA Designer, ARM, Cortex-A9, CoreSight, Cortex, PrimeCell, ARM Powered, and ARM Connected Partner are trademarks
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 1: Absolute Maximum Ratings (1) (Cont’d)
Symbol
Min
Max
Units
Key memory battery backup supply
–0.5
2.0
V
VMGTAVCC
Analog supply voltage for the GTX transmitter and receiver circuits
–0.5
1.1
V
VMGTAVTT
Analog supply voltage for the GTX transmitter and receiver termination
circuits
–0.5
1.32
V
VMGTVCCAUX
Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers
–0.5
1.935
V
VMGTREFCLK
GTX transceiver reference clock absolute input voltage
–0.5
1.32
V
VMGTAVTTRCAL
Analog supply voltage for the resistor calibration circuit of the GTX
transceiver column
–0.5
1.32
V
VIN
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
–0.5
1.26
V
IDCIN
DC input current for receiver input pins DC coupled VMGTAVTT = 1.2V
–
14
mA
IDCOUT
DC output current for transmitter pins DC coupled VMGTAVTT = 1.2V
–
14
mA
VCCBATT
Description
GTX Transceiver
XADC
VCCADC
XADC supply relative to GNDADC
–0.5
2.0
V
VREFP
XADC reference input relative to GNDADC
–0.5
2.0
V
–65
150
°C
–
+220
°C
–
+260
°C
–
+125
°C
Temperature
TSTG
TSOL
Storage temperature (ambient)
Maximum soldering temperature for Pb/Sn component bodies
Maximum soldering temperature for Pb-free component bodies
Maximum junction temperature(7)
Tj
(7)
(7)
Notes:
1.
2.
3.
4.
5.
6.
7.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Applies to both MIO supply banks VCCO_MIO0 and VCCO_MIO1.
The lower absolute voltage specification always applies.
For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the Zynq-7000 All Programmable SoC Technical
Reference Manual (UG585).
The maximum limit applied to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5.
See Table 12 for TMDS_33 specifications.
For soldering guidelines and thermal considerations, see the Zynq-7000 All Programmable SoC Packaging and Pinout Specification
(UG865).
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 2: Recommended Operating Conditions (1)(2)
Symbol
Description
Min
Typ
Max
Units
PS
VCCPINT(3)
PS internal supply voltage
0.95
1.00
1.05
V
VCCPAUX
PS auxiliary supply voltage
1.71
1.80
1.89
V
VCCPLL
PS PLL supply voltage
1.71
1.80
1.89
V
VCCO_DDR
PS DDR supply voltage
1.14
–
1.89
V
VCCO_MIO(4)
PS supply voltage for MIO banks
1.71
–
3.465
V
VPIN(5)
PS DDR and MIO I/O input voltage
–0.20
–
VCCO_DDR + 0.20
VCCO_MIO + 0.20
V
VCCINT
Internal supply voltage
0.97
1.00
1.03
V
VCCAUX
Auxiliary supply voltage
1.71
1.80
1.89
V
VCCBRAM
Block RAM supply voltage
0.97
1.00
1.03
V
Supply voltage for 3.3V HR I/O banks
1.14
–
3.465
V
Supply voltage for 1.8V HP I/O banks
1.14
–
1.89
V
Auxiliary supply voltage when set to 1.8V
1.71
1.80
1.89
V
Auxiliary supply voltage when set to 2.0V
1.94
2.00
2.06
V
V
PL
VCCO(6)(7)
VCCAUX_IO
I/O input voltage
–0.20
–
VCCO + 0.20
VIN(5)
I/O input voltage (when VCCO = 3.3V) for VREF and differential
I/O standards except TMDS_33(8)
–0.20
–
2.625
IIN(9)
Maximum current through any (PS or PL) pin in a powered or
unpowered bank when forward biasing the clamp diode
–
–
10
mA
VCCBATT(10)
Battery voltage
1.0
–
1.89
V
Analog supply voltage for the GTX transceiver QPLL frequency
range ≤ 10.3125 GHz(12)(13)
0.97
1.0
1.08
V
Analog supply voltage for the GTX transceiver QPLL frequency
range > 10.3125 GHz
1.02
1.05
1.08
VMGTAVTT(11)
Analog supply voltage for the GTX transmitter and receiver
termination circuits
1.17
1.2
1.23
V
VMGTVCCAUX(11)
Auxiliary analog QPLL voltage supply for the transceivers
1.75
1.80
1.85
V
VMGTAVTTRCAL(11)
Analog supply voltage for the resistor calibration circuit of the
GTX transceiver column
1.17
1.2
1.23
V
VCCADC
XADC supply relative to GNDADC
1.71
1.80
1.89
V
VREFP
Externally supplied reference voltage
1.20
1.25
1.30
V
GTX Transceiver
VMGTAVCC(11)
XADC
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 2: Recommended Operating Conditions (1)(2) (Cont’d)
Symbol
Description
Min
Typ
Max
Units
Junction temperature operating range for commercial (C)
temperature devices
0
–
85
°C
Junction temperature operating range for extended (E)
temperature devices
0
–
100
°C
Junction temperature operating range for industrial (I)
temperature devices
–40
–
100
°C
Temperature
Tj
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
All voltages are relative to ground. The PL and PS share a common ground.
For the design of the power distribution system consult the Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide (UG933).
When the processor cores operate FCPU_6X4X_621_MAX at 1 GHz (-3E speed grade) or when the DDR interface operates at 1333 Mb/s, the
VCCPINT minimum is 0.97V and the VCCPINT maximum is 1.03V.
Applies to both MIO supply banks VCCO_MIO0 and VCCO_MIO1.
The lower absolute voltage specification always applies.
Configuration data is retained even if VCCO drops to 0V.
Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
See Table 12 for TMDS_33 specifications.
A total of 200 mA per PS or PL bank should not be exceeded.
VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.
Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
For data rates ≤ 10.3125 Gb/s, VMGTAVCC should be 1.0V ±3% for lower power consumption.
For lower power consumption, VMGTAVCC should be 1.0V ±3% over the entire CPLL frequency range.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Min
Typ(1)
Max
Units
VDRINT
Data retention VCCINT voltage (below which configuration data might be lost)
0.75
–
–
V
VDRI
Data retention VCCAUX voltage (below which configuration data might be lost)
1.5
–
–
V
IREF
VREF leakage current per pin
–
–
15
µA
IL
Input or output leakage current per pin (sample-tested)
–
–
15
µA
PL die input capacitance at the pad
–
–
8
pF
PS die input capacitance at the pad
–
–
8
pF
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
90
–
330
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V
68
–
250
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V
34
–
220
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
23
–
150
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
12
–
120
µA
Pad pull-down (when selected) @ VIN = 3.3V
68
–
330
µA
Pad pull-down (when selected) @ VIN = 1.8V
45
–
180
µA
Analog supply current, analog circuits in powered up state
–
–
25
mA
Battery supply current
–
–
150
nA
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_40) for commercial (C), industrial (I), and extended (E)
temperature devices
28
40
55
Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_50) for commercial (C), industrial (I), and extended (E)
temperature devices
35
50
65
Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_60) for commercial (C), industrial (I), and extended (E)
temperature devices
44
60
83
Ω
n
Temperature diode ideality factor
–
1.010
–
–
r
Temperature diode series resistance
–
2
–
Ω
CIN(2)
CPIN
(2)
IRPU
IRPD
ICCADC
IBATT
(3)
RIN_TERM(4)
Notes:
1.
2.
3.
4.
Typical values are specified at nominal voltage, 25°C.
This measurement represents the die capacitance at the pad, not including the package.
Maximum value specified for worst case process at 25°C.
Termination resistance to a VCCO/2 level.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O and 3.3V HR I/O Banks(1)
AC Voltage Overshoot
VCCO + 0.55
% of UI @–40°C to 100°C
AC Voltage Undershoot
% of UI @–40°C to 100°C
–0.40
100
–0.45
61.7
–0.50
25.8
–0.55
11.0
100
VCCO + 0.60
46.6
–0.60
4.77
VCCO + 0.65
21.2
–0.65
2.10
VCCO + 0.70
9.75
–0.70
0.94
VCCO + 0.75
4.55
–0.75
0.43
VCCO + 0.80
2.15
–0.80
0.20
VCCO + 0.85
1.02
–0.85
0.09
VCCO + 0.90
0.49
–0.90
0.04
VCCO + 0.95
0.24
–0.95
0.02
Notes:
1.
A total of 200 mA per bank should not be exceeded.
Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for PL 1.8V HP I/O Banks(1)(2)
AC Voltage Overshoot
% of UI @–40°C to 100°C
AC Voltage Undershoot
% of UI @–40°C to 100°C
VCCO + 0.55
100
–0.55
100
VCCO + 0.60
50.0
–0.60
50.0
VCCO + 0.65
50.0
–0.65
50.0
VCCO + 0.70
47.0
–0.70
50.0
VCCO + 0.75
21.2
–0.75
50.0
VCCO + 0.80
9.71
–0.80
50.0
VCCO + 0.85
4.51
–0.85
28.4
VCCO + 0.90
2.12
–0.90
12.7
VCCO + 0.95
1.01
–0.95
5.79
Notes:
1.
2.
A total of 200 mA per bank should not be exceeded.
For UI smaller than 20 µs.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 6: Typical Quiescent Supply Current
Symbol
ICCPINTQ
ICCPAUXQ
ICCDDRQ
ICCINTQ
ICCAUXQ
Description
PS quiescent VCCPINT supply current
PS quiescent VCCPAUX supply current
PS quiescent VCCO_DDR supply current
PL quiescent VCCINT supply current
PL quiescent VCCAUX supply current
ICCAUX_IOQ PL quiescent VCCAUX_IO supply current
ICCOQ
ICCBRAMQ
PL quiescent VCCO supply current
PL quiescent VCCBRAM supply current
Device
Speed Grade
Units
-3
-2
-1
XC7Z030
122
122
122
mA
XC7Z045
122
122
122
mA
XC7Z100
N/A
XC7Z030
13
13
13
mA
XC7Z045
13
13
13
mA
XC7Z100
N/A
XC7Z030
4
4
4
mA
XC7Z045
4
4
4
mA
XC7Z100
N/A
XC7Z030
246
246
246
mA
XC7Z045
611
611
611
mA
XC7Z100
N/A
XC7Z030
56
56
56
mA
XC7Z045
131
131
131
mA
XC7Z100
N/A
XC7Z030
2
2
2
mA
XC7Z045
2
2
2
mA
XC7Z100
N/A
XC7Z030
4
4
4
mA
XC7Z045
4
4
4
mA
XC7Z100
N/A
XC7Z030
11
11
11
mA
XC7Z045
23
23
23
mA
XC7Z100
N/A
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1.
2.
3.
Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO resources.
Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for
conditions other than those specified.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
PS Power-On/Off Power Supply Requirements
The recommended power-on sequence is VCCPINT, VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0,
VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The
recommended power-off sequence is the reverse of the power-on sequence. If VCCPAUX, VCCPLL and the PS VCCO supplies
(VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) have the same recommended voltage levels, then they can be powered by the
same supply and ramped simultaneously. Xilinx recommends powering VCCPLL with the same supply as VCCPAUX, with an
optional ferrite bead filter.
For VCCO_MIO0 and VCCO_MIO1 voltages of 3.3V:
•
The voltage difference between VCCO_MIO0 /VCCO_MIO1 and VCCPAUX must not exceed 2.625V for longer than
TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.
•
The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
PL Power-On/Off Power Supply Sequencing
The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current
draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the poweron sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same
supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they
can be powered by the same supply and ramped simultaneously.
For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:
•
The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each
power-on/off cycle to maintain device reliability levels.
•
The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
The recommended power-on sequence to achieve minimum current draw for the GTX transceivers is VCCINT, VMGTAVCC,
VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and
VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to
achieve minimum current draw.
If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during
power-up and power-down.
•
When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT – VMGTAVCC > 150 mV and VMGTAVCC < 0.7V, the
VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current
draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.
•
When VMGTAVTT is powered before VCCINT and VMGTAVTT – VCCINT > 150 mV and VCCINT < 0.7V, the VMGTAVTT current
draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to
0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.
PS—PL Power Sequencing
The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR,
VCCO_MIO0, and VCCO_MIO1) can be powered before or after the PL power supplies (VCCINT, VCCBRAM, VCCAUX, VCCO,
VCCAUX_IO, VMGTAVCC, VMGTAVTT, VMGTVCCAUX, and VCCADC). The PS and PL power regions are isolated to prevent
damage.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Power Supply Requirements
Table 7 shows the minimum current, in addition to ICCQ, that is required by Zynq-7000 devices for proper power-on and
configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies have
passed through their power-on reset threshold voltages. The Zynq-7000 device must not be configured until after VCCINT is
applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these
supplies.
Table 7: Power-On Current for Zynq-7000 Devices(1)
ICCPINTMIN
ICCPAUXMIN
ICCDDRMIN
ICCINTMIN
ICCAUXMIN
ICCOMIN
ICCAUX_IOMIN
ICCBRAMMIN
Typ(2)
Typ(2)
Typ(2)
Typ(2)
Typ(2)
Typ(2)
Typ(2)
Typ(2)
XC7Z030
ICCPINTQ +
70 mA
ICCPAUXQ +
40 mA
ICCDDRQ +
130 mA
per bank
ICCINTQ +
900 mA
ICCAUXQ +
60 mA
ICCOQ +
90 mA
per bank
ICCOAUXIOQ +
40 mA
per bank
ICCBRAMQ +
90 mA
mA
XC7Z045
ICCPINTQ +
70 mA
ICCPAUXQ +
40 mA
ICCDDRQ +
130 mA
per bank
ICCINTQ +
1400 mA
ICCAUXQ +
60 mA
ICCOQ +
90 mA
per bank
ICCOAUXIOQ +
40 mA
per bank
ICCBRAMQ +
90 mA
mA
Device
XC7Z100
Units
mA
Notes:
1.
2.
Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents.
Typical values are specified at nominal voltage, 25°C.
Table 8: Power Supply Ramp Time
Symbol
Description
Conditions
Min
Max
Units
TVCCPINT
Ramp time from GND to 90% of VCCPINT
0.2
50
ms
TVCCPAUX
Ramp time from GND to 90% of VCCPAUX
0.2
50
ms
TVCCO_DDR
Ramp time from GND to 90% of VCCO_DDR
0.2
50
ms
TVCCO_MIO
Ramp time from GND to 90% of VCCO_MIO
0.2
50
ms
TVCCINT
Ramp time from GND to 90% of VCCINT
0.2
50
ms
TVCCO
Ramp time from GND to 90% of VCCO
0.2
50
ms
TVCCAUX
Ramp time from GND to 90% of VCCAUX
0.2
50
ms
TVCCAUX_IO
Ramp time from GND to 90% of VCCAUX_IO
0.2
50
ms
TVCCBRAM
Ramp time from GND to 90% of VCCBRAM
ms
TJ =
0.2
50
100°C(1)
–
500
85°C(1)
–
800
TVCCO2VCCAUX
Allowed time per power cycle for VCCO – VCCAUX > 2.625V
and VCCO_MIO – VCCPAUX > 2.625V
TMGTAVCC
Ramp time from GND to 90% of VMGTAVCC
0.2
50
ms
TMGTAVTT
Ramp time from GND to 90% of VMGTAVTT
0.2
50
ms
TMGTVCCAUX
Ramp time from GND to 90% of VMGTVCCAUX
0.2
50
ms
TJ =
ms
Notes:
1.
Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
PS I/O Levels
Table 9: PS DC Input and Output Levels(1)
VOL
VOH
IOL
IOH
V, Max
V, Min
mA
mA
–0.300 35% VCCO_MIO 65% VCCO_MIO VCCO_MIO + 0.300
0.450
VCCO_MIO – 0.450
8
–8
LVCMOS25
–0.300
0.700
1.700
VCCO_MIO + 0.300
0.400
VCCO_MIO – 0.400
8
–8
MIO
LVCMOS33
–0.300
0.800
2.000
3.450
0.400
VCCO_MIO – 0.400
8
–8
MIO
HSTL_I_18
–0.300 VPREF – 0.100 VPREF + 0.100 VCCO_MIO + 0.300
0.400
VCCO_MIO – 0.400
8
–8
8
–8
Bank
I/O
Standard
MIO
LVCMOS18
MIO
VIH
VIL
V, Min
V, Max
V, Min
V, Max
DDR SSTL18_I
–0.300 VPREF – 0.125 VPREF + 0.125 VCCO_DDR + 0.300 VCCO_DDR/2 – 0.470 VCCO_DDR/2 + 0.470
DDR SSTL15
–0.300 VPREF – 0.100 VPREF + 0.100 VCCO_DDR + 0.300 VCCO_DDR/2 – 0.175 VCCO_DDR/2 + 0.175 13.0 –13.0
DDR SSTL135
–0.300 VPREF – 0.090 VPREF + 0.090 VCCO_DDR + 0.300 VCCO_DDR/2 – 0.150 VCCO_DDR/2 + 0.150 13.0 –13.0
DDR HSUL_12
–0.300 VPREF – 0.130 VPREF + 0.130 VCCO_DDR + 0.300
20% VCCO_DDR
80% VCCO_DDR
0.1
–0.1
Notes:
1.
Tested according to relevant specifications.
Table 10: PS Complementary Differential DC Input and Output Levels
Bank
I/O Standard
VICM(1)
VID(2)
V, Min V,Typ V, Max V,Min V, Max
DDR DIFF_HSUL_12
0.300
0.600
0.850
0.100
–
DDR DIFF_SSTL135
0.300
0.675
1.000
0.100
–
DDR DIFF_SSTL15
0.300
0.750
1.125
0.100
DDR DIFF_SSTL18_I
0.300
0.900
1.425
0.100
VOL(3)
VOH(4)
V, Max
V, Min
20% VCCO
80% VCCO
IOL
IOH
mA, Max mA, Min
0.100
–0.100
(VCCO_DDR/2) – 0.150 (VCCO_DDR/2) + 0.150
13.0
–13.0
–
(VCCO_DDR/2) – 0.175 (VCCO_DDR/2) + 0.175
13.0
–13.0
–
(VCCO_DDR/2) – 0.470 (VCCO_DDR/2) + 0.470
8.00
–8.00
Notes:
1.
2.
3.
4.
VICM is the input common mode voltage.
VID is the input differential voltage (Q–Q).
VOL is the single-ended low-output voltage.
VOH is the single-ended high-output voltage.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
PL I/O Levels
Table 11: SelectIO DC Input and Output Levels(1)(2)
I/O Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Max
V, Min
mA
mA
HSTL_I
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
0.400
VCCO – 0.400
8
–8
HSTL_I_12
–0.300
VREF – 0.080
VREF + 0.080
VCCO + 0.300
25% VCCO
75% VCCO
6.3
–6.3
HSTL_I_18
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
0.400
VCCO – 0.400
8
–8
HSTL_II
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
0.400
VCCO – 0.400
16
–16
HSTL_II_18
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
0.400
VCCO – 0.400
16
–16
HSUL_12
–0.300
VREF – 0.130
VREF + 0.130
VCCO + 0.300
20% VCCO
80% VCCO
0.1
–0.1
LVCMOS12
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.400
VCCO – 0.400
Note 3
Note 3
LVCMOS15,
LVDCI_15
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
25% VCCO
75% VCCO
Note 4
Note 4
LVCMOS18,
LVDCI_18
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO – 0.450
Note 5
Note 5
LVCMOS25
–0.300
0.700
1.700
VCCO + 0.300
0.400
VCCO – 0.400
Note 6
Note 6
LVCMOS33
–0.300
0.800
2.000
3.450
0.400
VCCO – 0.400
Note 6
Note 6
LVTTL
–0.300
0.800
2.000
3.450
0.400
2.400
Note 7
Note 7
MOBILE_DDR
–0.300
20% VCCO
80% VCCO
VCCO + 0.300
10% VCCO
90% VCCO
0.1
–0.1
PCI33_3
–0.400
30% VCCO
50% VCCO
VCCO + 0.500
10% VCCO
90% VCCO
1.5
–0.5
SSTL12
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150
14.25
–14.25
SSTL135
–0.300
VREF – 0.090
VREF + 0.090
VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150
13.0
–13.0
SSTL135_R
–0.300
VREF – 0.090
VREF + 0.090
VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150
8.9
–8.9
SSTL15
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175
13.0
–13.0
SSTL15_R
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175
8.9
–8.9
SSTL18_I
–0.300
VREF – 0.125
VREF + 0.125
VCCO + 0.300 VCCO/2 – 0.470 VCCO/2 + 0.470
8
–8
SSTL18_II
–0.300
VREF – 0.125
VREF + 0.125
VCCO + 0.300 VCCO/2 – 0.600 VCCO/2 + 0.600
13.4
–13.4
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Tested according to relevant specifications.
3.3V and 2.5V standards are only supported in 3.3V I/O banks.
Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks.
Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks.
Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks.
Supported drive strengths of 4, 8, 12, or 16 mA
Supported drive strengths of 4, 8, 12, 16, or 24 mA
For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471).
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 12: Differential SelectIO DC Input and Output Levels
I/O Standard
VICM(1)
V, Min V, Typ
BLVDS_25
VID(2)
V, Max
VOCM(3)
V, Min V, Typ V, Max
VOD(4)
V, Min
V, Typ
V, Max
V, Min V, Typ V, Max
Note 5
0.300
1.200
1.425
0.100
–
–
–
1.250
–
MINI_LVDS_25 0.300
1.200
VCCAUX
0.200
0.400
0.600
1.000
1.200
1.400
0.300
0.450
0.600
PPDS_25
0.200
0.900
VCCAUX
0.100
0.250
0.400
0.500
0.950
1.400
0.100
0.250
0.400
RSDS_25
0.300
0.900
1.500
0.100
0.350
0.600
1.000
1.200
1.400
0.100
0.350
0.600
TMDS_33
2.700
2.965
3.230
0.150
0.675
1.200 VCCO–0.405 VCCO–0.300 VCCO–0.190 0.400
0.600
0.800
Notes:
1.
2.
3.
4.
5.
6.
7.
VICM is the input common mode voltage.
VID is the input differential voltage (Q – Q).
VOCM is the output common mode voltage.
VOD is the output differential voltage (Q – Q).
VOD for BLVDS will vary significantly depending on topology and loading.
LVDS_25 is specified in Table 14.
LVDS is specified in Table 15.
Table 13: Complementary Differential SelectIO DC Input and Output Levels
VICM(1)
I/O Standard
VID(2)
VOL(3)
VOH(4)
IOL
IOH
V, Min
V, Typ
V, Max
V,
Min
V, Max
V, Max
V, Min
mA, Max
mA, Min
DIFF_HSTL_I
0.300
0.750
1.125
0.100
–
0.400
VCCO–0.400
8.00
–8.00
DIFF_HSTL_I_18
0.300
0.900
1.425
0.100
–
0.400
VCCO–0.400
8.00
–8.00
DIFF_HSTL_II
0.300
0.750
1.125
0.100
–
0.400
VCCO–0.400
16.00
–16.00
DIFF_HSTL_II_18
0.300
0.900
1.425
0.100
–
0.400
VCCO–0.400
16.00
–16.00
DIFF_HSUL_12
0.300
0.600
0.850
0.100
–
20% VCCO
80% VCCO
0.100
–0.100
DIFF_MOBILE_DDR
0.300
0.900
1.425
0.100
–
10% VCCO
90% VCCO
0.100
–0.100
DIFF_SSTL12
0.300
0.600
0.850
0.100
–
(VCCO/2) – 0.150 (VCCO/2) + 0.150
14.25
–14.25
DIFF_SSTL135
0.300
0.675
1.000
0.100
–
(VCCO/2) – 0.150 (VCCO/2) + 0.150
13.0
–13.0
DIFF_SSTL135_R
0.300
0.675
1.000
0.100
–
(VCCO/2) – 0.150 (VCCO/2) + 0.150
8.9
–8.9
DIFF_SSTL15
0.300
0.750
1.125
0.100
–
(VCCO/2) – 0.175 (VCCO/2) + 0.175
13.0
–13.0
DIFF_SSTL15_R
0.300
0.750
1.125
0.100
–
(VCCO/2) – 0.175 (VCCO/2) + 0.175
8.9
–8.9
DIFF_SSTL18_I
0.300
0.900
1.425
0.100
–
(VCCO/2) – 0.470 (VCCO/2) + 0.470
8.00
–8.00
DIFF_SSTL18_II
0.300
0.900
1.425
0.100
–
(VCCO/2) – 0.600 (VCCO/2) + 0.600
13.4
–13.4
Notes:
1.
2.
3.
4.
VICM is the input common mode voltage.
VID is the input differential voltage (Q – Q).
VOL is the single-ended low-output voltage.
VOH is the single-ended high-output voltage.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
LVDS DC Specifications (LVDS_25)
The LVDS_25 standard is available in the HR I/O banks.
Table 14: LVDS_25 DC Specifications(1)
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
2.375
2.500
2.625
V
VCCO
Supply Voltage
VOH
Output High Voltage for Q and Q
RT = 100 Ω across Q and Q signals
–
–
1.675
V
VOL
Output Low Voltage for Q and Q
RT = 100 Ω across Q and Q signals
0.700
–
–
V
VODIFF
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
RT = 100 Ω across Q and Q signals
247
350
600
mV
VOCM
Output Common-Mode Voltage
RT = 100 Ω across Q and Q signals
1.000
1.250
1.425
V
VIDIFF
Differential Input Voltage (Q – Q), Q = High (Q – Q), Q = High
100
350
600
mV
VICM
Input Common-Mode Voltage
0.300
1.200
1.425
V
Notes:
1.
Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the
7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.
LVDS DC Specifications (LVDS)
The LVDS standard is available in the HP I/O banks.
Table 15: LVDS DC Specifications(1)
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
1.710
1.800
1.890
V
VCCO
Supply Voltage
VOH
Output High Voltage for Q and Q
RT = 100 Ω across Q and Q signals
–
–
1.675
V
VOL
Output Low Voltage for Q and Q
RT = 100 Ω across Q and Q signals
0.825
–
–
V
VODIFF
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
RT = 100 Ω across Q and Q signals
247
350
600
mV
VOCM
Output Common-Mode Voltage
RT = 100 Ω across Q and Q signals
1.000
1.250
1.425
V
VIDIFF
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
Common-mode input voltage = 1.25V
100
350
600
mV
VICM
Input Common-Mode Voltage
Differential input voltage = ±350 mV
0.300
1.200
1.425
V
Notes:
1.
Differential inputs for LVDS can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the 7 Series
FPGAs SelectIO Resources User Guide (UG471) for more information.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
AC Switching Characteristics
All values represented in this data sheet are based on the speed specifications in ISE® Design Suite 14.5 v1.06 and
Vivado® Design Suite 2013.1 v1.06 for the -3, -2, and -1 speed grades.
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance Product Specification
These specifications are based on simulations only and are typically available soon after device design specifications are
frozen. Although speed grades with this designation are considered relatively stable and conservative, some underreporting might still occur.
Preliminary Product Specification
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades
with this designation are intended to give a better indication of the expected performance of production silicon. The
probability of under-reporting delays is greatly reduced as compared to Advance data.
Production Product Specification
These specifications are released once enough production silicon of a particular device family member has been
characterized to provide full correlation between specifications and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to Production before faster speed grades.
Testing of AC Switching Characteristics
Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are
representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Zynq-7000 devices.
Speed Grade Designations
Since individual family members are produced at different times, the migration from one category to another depends
completely on the status of the fabrication process for each device. Table 16 correlates the current status of each Zynq-7000
device on a per speed grade basis.
Table 16: Zynq-7000 Device Speed Grade Designations
Device
Speed Grade Designations
Advance
Preliminary
Production
XC7Z030
-3, -2, -1
XC7Z045
-3, -2, -1
XC7Z100
-2, -1
Production Silicon and Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 17 lists the production released Zynq-7000 device, speed grade, and the minimum corresponding supported speed
specification version and software revisions. The software and speed specifications listed are the minimum releases
required for production. All subsequent releases of software and speed specifications are valid.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 17: Zynq-7000 Device Production Software and Speed Specification Release
Speed Grade Designations
Device
-3
-2
-1
XC7Z030
ISE 14.5 v1.06 and Vivado 2013.1 v1.06
XC7Z045
ISE 14.5 v1.06 and Vivado 2013.1 v1.06
XC7Z100
N/A
Notes:
1.
Blank entries indicate a device and/or speed grade in advance or preliminary status.
PS Performance Characteristics
For further design requirement details, refer to the Zynq-7000 All Programmable SoC Technical Reference Manual (UG585).
Table 18: CPU Clock Domains Performance
Symbol
Clock Ratio
Description
Speed Grade
Units
-3
-2
-1
Maximum CPU clock frequency
1000
733
667
MHz
Maximum CPU_3X clock frequency
500
367
333
MHz
Maximum CPU_2X clock frequency
333
244
222
MHz
FCPU_1X_621_MAX
Maximum CPU_1X clock frequency
167
122
111
MHz
FCPU_6X4X_421_MAX(1)
Maximum CPU clock frequency
710
600
533
MHz
Maximum CPU_3X clock frequency
355
300
267
MHz
Maximum CPU_2X clock frequency
355
300
267
MHz
Maximum CPU_1X clock frequency
178
150
133
MHz
FCPU_6X4X_621_MAX(1)(2)
FCPU_3X2X_621_MAX
6:2:1
FCPU_2X_621_MAX
FCPU_3X2X_421_MAX
FCPU_2X_421_MAX
4:2:1
FCPU_1X_421_MAX
Notes:
1.
2.
The maximum frequency during BootROM execution is 500 MHz across all speed specifications.
When the processor cores operate FCPU_6X4X_621_MAX at 1 GHz (-3E speed grade), the VCCPINT minimum is 0.97V and the VCCPINT
maximum is 1.03V.
Table 19: PS DDR Clock Domains Performance(1)
Symbol
Description
Speed Grade
-3
-2
-1
Units
FDDR3_MAX
Maximum DDR3 interface performance
1333(2)
1066
1066
Mb/s
FDDR3L_MAX
Maximum DDR3L interface performance
800
800
800
Mb/s
FDDR2_MAX
Maximum DDR2 interface performance
800
800
800
Mb/s
FLPDDR2_MAX
Maximum LPDDR2 interface performance
800
800
800
Mb/s
FDDRCLK_2XMAX
Maximum DDR_2X clock frequency
444
408
355
MHz
Notes:
1.
2.
All performance numbers apply to both internal and external VREF configurations.
When a DDR interface operates at 1333 Mb/s, the VCCPINT minimum is 0.97V and the VCCPINT maximum is 1.03V.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
PS Switching Characteristics
Clocks
Table 20: System Reference Clock Input Requirements
Symbol
Description
Min
Typ
Max
Units
TJTPSCLK
PS_CLK RMS clock jitter tolerance
–
–
±0.5
%
TDCPSCLK
PS_CLK duty cycle
40
–
60
%
TRFPSCLK
PS_CLK rise and fall time
–
4
–
ns
FPSCLK
PS_CLK frequency
30
–
60
MHz
Notes:
1.
Tested to commercial (C) and extended (E) temperature ranges only. See Temperature in Table 2.
Table 21: PS PLL Switching Characteristics
Symbol
Speed Grade
Description
Units
-3
-2
-1
60
60
60
µs
TLOCK_PSPLL
PLL maximum lock time
FPSPLL_MAX
PLL maximum output frequency
2000
1800
1600
MHz
FPSPLL_MIN
PLL minimum output frequency
780
780
780
MHz
Resets
Table 22: PS Reset Requirements
Symbol
Description
time(1)
TPSPOR
Required PS_POR_B assertion
TPSRST
Required PS_SRST_B assertion time
Min
Typ
Max
Units
100
–
–
µs
3
–
–
PS_CLK Clock Cycles
Notes:
1.
PS_POR_B needs to be asserted low until PS supply voltages reach minimum levels.
PS Configuration
Table 23: Processor Configuration Access Port Switching Characteristics
Symbol
FPCAPCK
Description
Min
Typ
Max
Units
Maximum processor configuration access port (PCAP) frequency
–
–
100
MHz
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
DDR Memory Interfaces
Table 24: DDR3 Interface Switching Characteristics (1333 Mb/s)(1)
Symbol
Description
Min
Max
Units
TDQVALID
Input data valid window
500
–
ps
TDQDS(2)
Output DQ to DQS skew
95
–
ps
TDQDH(3)
Output DQS to DQ skew
222
–
ps
TDQSS
Output clock to DQS skew
–0.11
0.08
TCK
TCACK(4)
Command/address output setup time with respect to CLK
465
–
ps
TCKCA(5)
Command/address output hold time with respect to CLK
528
–
ps
Notes:
1.
2.
3.
4.
5.
Recommended VCCO_DDR = 1.5V ±5%.
Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 25: DDR3 Interface Switching Characteristics (1066 Mb/s)(1)
Symbol
Description
Min
Max
Units
TDQVALID
Input data valid window
500
–
ps
TDQDS(2)
Output DQ to DQS skew
100
–
ps
TDQDH(3)
Output DQS to DQ skew
315
–
ps
TDQSS
Output clock to DQS skew
–0.10
0.10
TCK
TCACK(4)
Command/address output setup time with respect to CLK
560
–
ps
TCKCA(5)
Command/address output hold time with respect to CLK
658
–
ps
Notes:
1.
2.
3.
4.
5.
Recommended VCCO_DDR = 1.5V ±5%.
Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 26: DDR3L Interface Switching Characteristics (800 Mb/s)(1)
Symbol
Description
Min
Max
Units
TDQVALID
Input data valid window
500
–
ps
TDQDS(2)
Output DQ to DQS skew
321
–
ps
TDQDH(3)
Output DQS to DQ skew
380
–
ps
TDQSS
Output clock to DQS skew
–0.12
0.04
TCK
TCACK(4)
Command/address output setup time with respect to CLK
636
–
ps
TCKCA(5)
Command/address output hold time with respect to CLK
853
–
ps
Notes:
1.
2.
3.
4.
5.
Recommended VCCO_DDR = 1.35V ±5%.
Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 27: LPDDR2 Interface Switching Characteristics (800 Mb/s)(1)
Symbol
Description
Min
Max
Units
TDQVALID
Input data valid window
500
–
ps
TDQDS(2)
Output DQ to DQS skew
111
–
ps
TDQDH(3)
Output DQS to DQ skew
318
–
ps
TDQSS
Output clock to DQS skew
0.91
1.10
TCK
TCACK(4)
Command/address output setup time with respect to CLK
132
–
ps
TCKCA(5)
Command/address output hold time with respect to CLK
363
–
ps
Notes:
1.
2.
3.
4.
5.
Recommended VCCO_DDR = 1.2V ±5%.
Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses VIL(AC)
to VREF of CLK.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 28: LPDDR2 Interface Switching Characteristics (400 Mb/s)(1)
Symbol
Description
Min
Max
Units
TDQVALID
Input data valid window
500
–
ps
TDQDS(2)
Output DQ to DQS skew
561
–
ps
TDQDH(3)
Output DQS to DQ skew
852
–
ps
TDQSS
Output clock to DQS skew
0.91
1.08
TCK
TCACK(4)
Command/address output setup time with respect to CLK
617
–
ps
TCKCA(5)
Command/address output hold time with respect to CLK
918
–
ps
Notes:
1.
2.
3.
4.
5.
Recommended VCCO_DDR = 1.2V ±5%.
Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses VIL(AC)
to VREF of CLK.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 29: DDR2 Interface Switching Characteristics (800 Mb/s)(1)
Symbol
Description
Min
Max
Units
TDQVALID
Input data valid window
500
–
ps
TDQDS(2)
Output DQ to DQS skew
147
–
ps
TDQDH(3)
Output DQS to DQ skew
376
–
ps
TDQSS
Output clock to DQS skew
–0.07
0.08
TCK
TCACK(4)
Command/address output setup time with respect to CLK
732
–
ps
TCKCA(5)
Command/address output hold time with respect to CLK
938
–
ps
Notes:
1.
2.
3.
4.
5.
Recommended VCCO_DDR = 1.8V ±5%.
Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 30: DDR2 Interface Switching Characteristics (400 Mb/s)(1)
Symbol
Description
Min
Max
Units
TDQVALID
Input data valid window
500
–
ps
TDQDS(2)
Output DQ to DQS skew
385
–
ps
TDQDH(3)
Output DQS to DQ skew
662
–
ps
TDQSS
Output clock to DQS skew
–0.11
0.06
TCK
TCACK(4)
Command/address output setup time with respect to CLK
1760
–
ps
TCKCA(5)
Command/address output hold time with respect to CLK
1739
–
ps
Notes:
1.
2.
3.
4.
5.
Recommended VCCO_DDR = 1.8V ±5%.
Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
X-Ref Target - Figure 1
CLK
CLK
TCKCA
TCACK
Write
Command
NOP
NOP
NOP
NOP
TCKCA
TCACK
Address
Bank, Col n
TDQSS
DQS
DQS
TDQDH
TDQDH
TDQDS
DQ
TDQDS
D0
D1
D2
D3
DS191_01_012013
Figure 1: DDR Output Timing Diagram
X-Ref Target - Figure 2
CLK
CLK
DQS
DQS
DQ
TDQVALID
D0
D1
D2
D3
DS191_02_012213
Figure 2: DDR Input Timing Diagram
DS191 (v1.4) April 24, 2013
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Static Memory Controller
Table 31: SMC Interface Delay Characteristics(1)(2)
Symbol
Description
Min
Max
Units
TNANDDOUT
NAND_IO output delay from last register to pad
4.12
6.45
ns
TNANDALE
NAND_ALE output delay from last register to pad
5.08
6.33
ns
TNANDCLE
NAND_CLE output delay from last register to pad
4.87
6.40
ns
TNANDWE
NAND_WE_B output delay from last register to pad
4.69
5.89
ns
TNANDRE
NAND_RE_B output delay from last register to pad
5.12
6.44
ns
TNANDCE
NAND_CE_B output delay from last register to pad
4.68
5.89
ns
TNANDDIN
NAND_IO setup time and input delay from pad to first register
1.48
3.09
ns
TNANDBUSY
NAND_BUSY setup time and input delay from pad to first register
2.48
3.33
ns
TSRAMA
SRAM_A output delay from last register to pad
3.94
5.73
ns
TSRAMDOUT
SRAM_DQ output delay from last register to pad
4.66
6.45
ns
TSRAMCE
SRAM_CE output delay from last register to pad
4.57
5.95
ns
TSRAMOE
SRAM_OE_B output delay from last register to pad
4.79
6.13
ns
TSRAMBLS
SRAM_BLS_B output delay from last register to pad
5.25
6.74
ns
TSRAMWE
SRAM_WE_B output delay from last register to pad
5.12
6.48
ns
TSRAMDIN
SRAM_DQ setup time and input delay from pad to first register
1.93
3.05
ns
TSRAMWAIT
SRAM_WAIT setup time and input delay from pad to first register
2.26
3.15
ns
Notes:
1.
2.
All parameters do not include the package flight time and register controlled delays.
Refer to the ARM® PrimeCell® Static Memory Controller (PL350 series) Technical Reference Manual for more SMC timing details.
DS191 (v1.4) April 24, 2013
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Quad-SPI Interfaces
Table 32: Quad-SPI Interface Switching Characteristics
Symbol
Description
Load
Conditions
Min
Max
Units
All(1)(2)
Feedback Clock Enabled
TDCQSPICLK1
TQSPICKO1
TQSPIDCK1
TQSPICKD1
TQSPISSCLK1
TQSPICLKSS1
FQSPICLK1
Quad-SPI clock duty cycle
Data and slave select output delay
Input data setup time
Input data hold time
44
56
%
15
pF(1)
–0.10
3.40
ns
30
pF(2)
–1.00
3.80
15
pF(1)
2.00
–
30
pF(2)
3.30
–
15
pF(1)
1.30
–
30
pF(2)
ns
ns
1.50
–
Slave select asserted to next clock edge
All(1)(2)
1
–
FQSPI_REF_CLK cycle
Clock edge to slave select deasserted
All(1)(2)
1
–
FQSPI_REF_CLK cycle
MHz
Quad-SPI device clock frequency
15
pF(1)
–
100(3)
30
pF(2)
–
70(3)
All(1)(2)
Feedback Clock Disabled
TDCQSPICLK2
TQSPICKO2
Quad-SPI clock duty cycle
Data and slave select output delay
44
56
%
15
pF(1)
–0.10
3.80
ns
30
pF(2)
–1.00
3.80
ns
TQSPIDCK2
Input data setup time(4)
All(1)(2)
1
11 – ------------------------------------------F QSPI_REF_CLK
–
ns
TQSPICKD2
Input data hold time
All(1)(2)
1
---------------------------------------2 × F QSPICLK2
–
ns
TQSPISSCLK2
Slave select asserted to next clock edge
All(1)(2)
1
–
FQSPI_REF_CLK cycle
Clock edge to slave select deasserted
All(1)(2)
1
–
FQSPI_REF_CLK cycle
Quad-SPI device clock frequency
All(1)(2)
–
40
MHz
All(1)(2)
–
200
MHz
TQSPICLKSS2
FQSPICLK2
Feedback Clock Enabled or Disabled
FQSPI_REF_CLK
Quad-SPI reference clock frequency
Notes:
1.
2.
3.
4.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, feedback clock pin has no load. Quad-SPI single slave select
4-bit I/O mode.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 30 pF loads in 4-bit stacked I/O configuration, feedback clock pin has no
load. Quad-SPI single slave select 4-bit I/O mode.
Requires appropriate component selection/board design.
Use 0 ns as the input data setup time when the calculated TQSPIDCK2 value is negative.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
X-Ref Target - Figure 3
QSPI{1,0}_SS_B
TQSPICLKSS1
TQSPISSCLK1
QSPI_SCLK_OUT
CPOL = 0
TQSPICLKSS1
TQSPISSCLK1
QSPI_SCLK_OUT
CPOL = 1
TQSPICKD1
TQSPICKO1
QSPI{1,0}_IO_[3,0]
TQSPIDCK1
OUT0
OUT1
INn-2
INn-1
INn
ds191_03_022413
Figure 3: Quad-SPI Interface (Feedback Clock Enabled) Timing Diagram
X-Ref Target - Figure 4
QSPI{1,0}_SS_B
TQSPICLKSS2
TQSPISSCLK2
QSPI_SCLK_OUT
(CPOL = 0)
TQSPISSCLK2
TQSPICLKSS2
QSPI_SCLK_OUT
(CPOL = 1)
TQSPICKO2
QSPI{0,1}_IO_[3:0]
OUT0
TQSPICKD2
TQSPIDCK2
OUT1
INn-1
INn
DS191_04_022013
Figure 4: Quad-SPI Interface (Feedback Clock Disabled) Timing Diagram
ULPI Interfaces
Table 33: ULPI Interface Clock Receiving Mode Switching Characteristics(1)(2)
Symbol
Description
Min
Typ
Max
Units
TULPIDCK
Input setup to ULPI clock, all inputs
3.00
–
–
ns
TULPICKD
Input hold to ULPI clock, all inputs
1.00
–
–
ns
TULPICKO
ULPI clock to output valid, all outputs
1.70
–
8.86
ns
FULPICLK
ULPI device clock frequency
–
60
–
MHz
Notes:
1.
2.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, 60 MHz device clock frequency.
All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
X-Ref Target - Figure 5
USB{0,1}_ULPI_CLK
TULPIDCK
TULPICKD
TULPIDCK
TULPICKD
USB{0,1}_ULPI_DATA[7:0] (Input)
USB{0,1}_ULPI_DIR,
USB{0,1}_ULPI_NXT
TULPICKO
USB{0,1}_ULPI_STP
TULPICKO
USB{0,1}_ULPI_DATA[7:0] (Output)
DS191_05_022013
Figure 5: ULPI Interface Timing Diagram
DS191 (v1.4) April 24, 2013
Preliminary Product Specification
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
RGMII and MDIO Interfaces
Table 34: RGMII and MDIO Interface Switching Characteristics(1)(2)(3)
Symbol
Description
Min
Typ
Max
Units
45
–
55
%
TDCGETXCLK
Transmit clock duty cycle
TGEMTXCKO
RGMII_TX_D[3:0], RGMII_TX_CTL output clock to out time
–0.50
–
0.50
ns
TGEMRXDCK
RGMII_RX_D[3:0], RGMII_RX_CTL input setup time
0.80
–
–
ns
TGEMRXCKD
RGMII_RX_D[3:0], RGMII_RX_CTL input hold time
0.80
–
–
ns
TMDIOCLK
MDC output clock period
400
–
–
ns
TMDIOCKH
MDC clock High time
160
–
–
ns
TMDIOCKL
MDC clock Low time
160
–
–
ns
TMDIODCK
MDIO input data setup time
80
–
–
ns
TMDIOCKD
MDIO input data hold time
0
–
–
ns
TMDIOCKO
MDIO data output delay
–20
–
170
ns
FGETXCLK
RGMII_TX_CLK transmit clock frequency
–
125
–
MHz
FGERXCLK
RGMII_RX_CLK receive clock frequency
–
125
–
MHz
FENET_REF_CLK
Ethernet reference clock frequency
–
125
–
MHz
Notes:
1.
2.
3.
Test conditions: LVCMOS25, fast slew rate, 8 mA drive strength, 15 pF loads. Values in this table are specified during 1000 Mb/s operation.
LVCMOS25 slow slew rate and LVCMOS33 are not supported.
All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 6
RGMII_TX_CLK
TGEMTXCKO
RGMII_TX_D[3:0]
RGMII_TX_CTL
RGMII_RX_CLK
TGEMRXDCK
TGEMRXCKD
RGMII_RX_D[3:0]
RGMII_RX_CTL
TMDIOCKH
TMDIOCLK
TMDIOCKL
MDIO_CLK
TMDIODCK
TMDIOCKD
MDIO_IO (Input)
TMDIOCKO
MDIO_IO (Output)
DS191_06_022013
Figure 6: RGMII Interface Timing Diagram
DS191 (v1.4) April 24, 2013
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
SD/SDIO Interfaces
Table 35: SD/SDIO Interface High Speed Mode Switching Characteristics(1)
Symbol
Description
Min
Typ
Max
Units
–
50
–
%
TDCSDHSCLK
SD device clock duty cycle
TSDHSCKO
Clock to output delay, all outputs
2.00
–
12.00
ns
TSDHSDCK
Input setup time, all inputs
3.00
–
–
ns
TSDHSCKD
Input hold time, all inputs
1.05
–
–
ns
FSD_REF_CLK
SD reference clock frequency
–
–
125
MHz
FSDHSCLK
High speed mode SD device clock frequency
0
–
50
MHz
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 7
SD{0,1}_CLK
TSDHSDCK
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (input)
TSDHSCKD
TSDHSCKO
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (output)
DS191_07_022013
Figure 7: SD/SDIO Interface High Speed Mode Timing Diagram
Table 36: SD/SDIO Interface Switching Characteristics(1)
Symbol
Description
Min
Typ
Max
Units
–
50
–
%
TDCSDSCLK
SD device clock duty cycle
TSDSCKO
Clock to output delay, all outputs
2.00
–
12.00
ns
TSDSDCK
Input setup time, all inputs
4.00
–
–
ns
TSDSCKD
Input hold time, all inputs
3.00
–
–
ns
FSD_REF_CLK
SD reference clock frequency
–
–
125
MHz
FSDIDCLK
Clock frequency in identification mode
–
–
400
MHz
FSDSCLK
Standard mode SD device clock frequency
0
–
50
MHz
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 8
SD{0,1}_CLK
TSDSDCK
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (input)
TSDSCKD
TSDSCKO
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (output)
DS191_108_030113
Figure 8: SD/SDIO Interface Standard Mode Timing Diagram
DS191 (v1.4) April 24, 2013
Preliminary Product Specification
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
I2C Interfaces
Table 37: I2C Fast Mode Interface Switching Characteristics(1)
Symbol
Description
Min
Typ
Max
Units
TDCI2CFCLK
I2C{0,1}SCL duty cycle
–
50
–
%
TI2CFCKO
I2C{0,1}SDAO clock to out delay
–
–
900
ns
TI2CFDCK
I2C{0,1}SDAI setup time
100
–
–
ns
FI2CFCLK
I2C{0,1}SCL clock frequency
–
–
400
KHz
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 9
I2C{0,1}SCL
TI2CFDCK
I2C{0,1}SDAI
TI2CFCKO
I2C{0,1}SDAO
DS191_08_022013
Figure 9: I2C Fast Mode Interface Timing Diagram
Table 38: I2C Standard Mode Interface Switching Characteristics(1)
Symbol
Description
Min
Typ
Max
Units
TDCI2CSCLK
I2C{0,1}SCL duty cycle
–
50
–
%
TI2CSCKO
I2C{0,1}SDAO clock to out delay
–
–
3450
ns
TI2CSDCK
I2C{0,1}SDAI setup time
250
–
–
ns
FI2CSCLK
I2C{0,1}SCL clock frequency
–
–
100
KHz
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 10
I2C{0,1}SCL
TI2CSDCK
I2C{0,1}SDAI
TI2CSCKO
I2C{0,1}SDAO
DS191_09_022013
Figure 10: I2C Standard Mode Interface Timing Diagram
DS191 (v1.4) April 24, 2013
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
SPI Interfaces
Table 39: SPI Master Mode Interface Switching Characteristics(1)
Symbol
Description
Min
Typ
Max
Units
–
50
–
%
TDCMSPICLK
SPI master mode clock duty cycle
TMSPIDCK
Input setup time for SPI{0,1}_MISO
2.00
–
–
ns
TMSPICKD
Input hold time for SPI{0,1}_MISO
8.20
–
–
ns
TMSPICKO
Output delay for SPI{0,1}_MOSI and SPI{0,1}_SS
–3.10
–
3.90
ns
TMSPISSCLK
Slave select asserted to first active clock edge
1
–
–
FSPI_REF_CLK cycles
TMSPICLKSS
Last active clock edge to slave select deasserted
0.5
–
–
FSPI_REF_CLK cycles
FMSPICLK
SPI master mode device clock frequency
–
–
50.00
MHz
FSPI_REF_CLK
SPI reference clock frequency
–
–
200.00
MHz
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 11
SPI{0,1}_SS
TMSPISSCLK
SPI{0,1}_CLK (CPOL=0)
TMSPICLKSS
SPI{0,1}_CLK (CPOL=1)
TMSPICKO
Dn
SPI{0,1}_MOSI
Dn–1
Dn–2
Dn–3
D0
TMSPICKD
TMSPIDCK
Dn
SPI{0,1}_MISO
Dn–1
Dn–2
DS191_10_022013
Figure 11: SPI Master (CPHA = 0) Interface Timing Diagram
X-Ref Target - Figure 12
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
TMSPISSCLK
TMSPICLKSS
SPI{0,1}_CLK (CPOL=1)
TMSPICKO
SPI{0,1}_MOSI
Dn
Dn–1
Dn–2
Dn–3
D0
TMSPICKD
TMSPIDCK
SPI{0,1}_MISO
Dn
Dn–1
Dn–2
Dn–3
D0
DS191_11_022013
Figure 12: SPI Master (CPHA = 1) Interface Timing Diagram
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 40: SPI Slave Mode Interface Switching Characteristics(1)(2)
Symbol
Description
Min
Max
Units
TSSPIDCK
Input setup time for SPI{0,1}_MOSI and SPI{0,1}_SS
1
–
FSPI_REF_CLK cycles
TSSPICKD
Input hold time for SPI{0,1}_MOSI and SPI{0,1}_SS
1
–
FSPI_REF_CLK cycles
TSSPICKO
Output delay for SPI{0,1}_MISO
0
2.6
FSPI_REF_CLK cycles
TSSPISSCLK
Slave select asserted to first active clock edge
1
–
FSPI_REF_CLK cycles
TSSPICLKSS
Last active clock edge to slave select deasserted
1
–
FSPI_REF_CLK cycles
FSSPICLK
SPI slave mode device clock frequency
–
25
MHz
FSPI_REF_CLK
SPI reference clock frequency
–
200
MHz
Notes:
1.
2.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 13
SPI{0,1}_SS
TSSPISSCLK
SPI{0,1}_CLK (CPOL=0)
TSSPICLKSS
SPI{0,1}_CLK (CPOL=1)
TSSPICKD
TSSPIDCK
Dn
SPI{0,1}_MOSI
Dn–1
Dn–2
Dn–3
D0
TSSPICKO
Dn
SPI{0,1}_MISO
Dn–1
Dn–2
Dn–3
D0
DS191_12_022013
Figure 13: SPI Slave (CPHA = 0) Interface Timing Diagram
X-Ref Target - Figure 14
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
TSSPISSCLK
TSSPICLKSS
SPI{0,1}_CLK (CPOL=1)
TSSPICKD
TSSPIDCK
SPI{0,1}_MOSI
Dn
Dn–1
Dn–2
Dn–3
D0
TSSPICKO
SPI{0,1}_MISO
Dn
Dn–1
Dn–2
Dn–3
D0
DS191_13_021013
Figure 14: SPI Slave (CPHA = 1) Interface Timing Diagram
DS191 (v1.4) April 24, 2013
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
CAN Interfaces
Table 41: CAN Interface Switching Characteristics(1)
Symbol
Description
Min
Max
Units
TPWCANRX
Minimum receive pulse width
1
–
µs
TPWCANTX
Minimum transmit pulse width
1
–
µs
Internally sourced CAN reference clock frequency
–
100
MHz
Externally sourced CAN reference clock frequency
–
40
MHz
Min
Max
Units
FCAN_REF_CLK
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
PJTAG Interfaces
Table 42: PJTAG Interface(1)(2)
Symbol
Description
TPJTAGDCK
PJTAG input setup time
2.4
–
ns
TPJTAGCKD
PJTAG input hold time
2.0
–
ns
TPJTAGCKO
PJTAG clock to out delay
–
12.5
ns
TPJTAGCLK
PJTAG clock frequency
–
20
MHz
Notes:
1.
2.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 15
PJTAGCLK
TPJTAGDCK
TPJTAGCKD
PJTAGTMS, PJTAGTDI
TPJTAGCKO
PJTAGTDO
DS191_14_022013
Figure 15: PJTAG Interface Timing Diagram
UART Interfaces
Table 43: UART Interface Switching Characteristics(1)
Symbol
Description
Min
Max
Units
BAUDTXMAX
Maximum transmit baud rate
–
1
Mb/s
BAUDRXMAX
Maximum receive baud rate
–
1
Mb/s
FUART_REF_CLK
UART reference clock frequency
–
100
MHz
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
GPIO Interfaces
Table 44: GPIO Banks Switching Characteristics(1)
Symbol
Description
Min
Max
Units
TPWGPIOH
Input high pulse width
10 x 1/cpu1x
–
µs
TPWGPIOL
Input low pulse width
10 x 1/cpu1x
–
µs
Notes:
1.
Pulse width requirement for interrupt.
X-Ref Target - Figure 16
TPWGPIOH
TPWGPIOL
GPIO
DS191_15_022013
Figure 16: GPIO Interface Timing Diagram
Trace Interface
Table 45: Trace Interface Switching Characteristics(1)
Symbol
Description
Min
Max
Units
–1.4
1.5
ns
TTCECKO
Trace clock to output delay, all outputs
TDCTCECLK
Trace clock duty cycle
40
60
%
FTCECLK
Trace clock frequency
–
80
MHz
Notes:
1.
Test conditions: LVCMOS25, fast slew rate, 8 mA drive strength, 15 pF loads.
Triple Timer Counter Interface
Table 46: Triple Timer Counter interface Switching Characteristics(1)
Symbol
Description
Min
Max
Units
2 x 1/cpu1x
–
ns
–
cpu1x/4
MHz
TPWTTCOCLK
Triple time counter output clock pulse width
FTTCOCLK
Triple time counter output clock frequency
TTTCICLKH
Triple time counter input clock high pulse width
1.5 x 1/cpu1x
–
ns
TTTCICLKL
Triple time counter input clock low pulse width
1.5 x 1/cpu1x
–
ns
FTTCICLK
Triple time counter input clock frequency
–
cpu1x/3
MHz
Notes:
1.
All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
Watchdog Timer
Table 47: Watchdog Timer Switching Characteristics
Symbol
FWDTCLK
Description
Watchdog timer input clock frequency
DS191 (v1.4) April 24, 2013
Preliminary Product Specification
Min
Max
Units
–
10
MHz
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
PS-PL Interface
Table 48: PS-PL Interface Performance
Symbol
Description
Min
Typical
Max
Units
FEMIOGEMCLK
EMIO gigabit Ethernet controller maximum frequency
–
–
125
MHz
FEMIOSDCLK
EMIO SD controller maximum frequency
–
–
25
MHz
FEMIOSPICLK
EMIO SPI controller maximum frequency
–
–
25
MHz
FEMIOJTAGCLK
EMIO JTAG controller maximum frequency
–
–
20
MHz
FEMIOTRACECLK
EMIO trace controller maximum frequency
–
–
125
MHz
FFTMCLK
Fabric trace monitor maximum frequency
–
–
125
MHz
FEMIODMACLK
DMA maximum frequency
–
–
100
MHz
PL Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in the PL. The
numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same
guidelines as the AC Switching Characteristics, page 14. In each table, the I/O bank type is either High Performance (HP)
or High Range (HR).
Table 49: PL Networking Applications Interface Performances
Description
I/O Bank Type
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)
SDR LVDS receiver
(SFI-4.1)(1)
DDR LVDS receiver
(SPI-4.2)(1)
Speed Grade
Units
-3
-2
-1
HR
710
710
625
Mb/s
HP
710
710
625
Mb/s
HR
1250
1250
950
Mb/s
HP
1600
1400
1250
Mb/s
HR
710
710
625
Mb/s
HP
710
710
625
Mb/s
HR
1250
1250
950
Mb/s
HP
1600
1400
1250
Mb/s
Notes:
1.
LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 50: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FFG Packages)(1)(2)
Memory
Standard
I/O Bank Type
VCCAUX_IO
Speed Grade
-3
-2
-1
Units
4:1 Memory Controllers
DDR3
DDR3L
DDR2
RLDRAM III
HP
2.0V
1866
1866
1600
Mb/s
HP
1.8V
1600
1333
1066
Mb/s
HR
N/A
1066
1066
800
Mb/s
HP
2.0V
1600
1600
1333
Mb/s
HP
1.8V
1333
1066
800
Mb/s
HR
N/A
800
800
667
Mb/s
HP
2.0V
800
800
800
Mb/s
HP
1.8V
800
800
800
Mb/s
HR
N/A
800
800
800
Mb/s
HP
2.0V
800
667
667
MHz
HP
1.8V
550
500
450
MHz
HR
N/A
N/A
2:1 Memory Controllers
DDR3
DDR3L
DDR2
QDR II+(3)
RLDRAM II
LPDDR2
HP
2.0V
HP
1.8V
HR
N/A
HP
2.0V
HP
1.8V
HR
N/A
HP
2.0V
HP
1.8V
HR
N/A
HP
2.0V
HP
1.8V
HR
N/A
HP
2.0V
HP
1.8V
HR
N/A
HP
2.0V
HP
1.8V
HR
N/A
Mb/s
1066
1066
800
Mb/s
Mb/s
Mb/s
1066
1066
800
800
800
667
Mb/s
800
800
800
Mb/s
550
500
450
MHz
500
450
400
MHz
533
500
450
MHz
Mb/s
Mb/s
667
667
667
Mb/s
Mb/s
Notes:
1.
2.
3.
VREF tracking is required. For more information, see the 7 Series FPGAs Memory Interface Solutions User Guide (UG586).
When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations
are limited to 333 MHz for all speed grades and I/O bank types.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 51: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FBG Packages)(1)(2)
Memory
Standard
I/O Bank Type
VCCAUX_IO(3)
Speed Grade
-3
-2
-1
Units
4:1 Memory Controllers
DDR3
DDR3L
DDR2
RLDRAM III
HP
N/A
1333
1066
800
Mb/s
HR
N/A
1066
800
800
Mb/s
HP
N/A
1066
800
667
Mb/s
HR
N/A
800
800
667
Mb/s
HP
N/A
800
800
800
Mb/s
HR
N/A
800
667
667
Mb/s
HP
N/A
550
500
450
MHz
HR
N/A
N/A
2:1 Memory Controllers
DDR3
DDR3L
DDR2
QDR II+(4)
RLDRAM II
LPDDR2
HP
N/A
1066
1066
800
Mb/s
HR
N/A
1066
800
800
Mb/s
HP
N/A
1066
800
667
Mb/s
HR
N/A
800
800
667
Mb/s
HP
N/A
800
800
800
Mb/s
HR
N/A
800
667
667
Mb/s
HP
N/A
550
500
450
MHz
HR
N/A
450
400
350
MHz
HP
N/A
HR
N/A
533
500
450
MHz
HP
N/A
667
667
667
Mb/s
HR
N/A
667
667
533
Mb/s
Notes:
1.
2.
3.
4.
VREF tracking is required. For more information, see the 7 Series FPGAs Memory Interface Solutions User Guide (UG586).
When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
FBG packages do not have separate VCCAUX_IO supply pins to adjust the pre-driver voltage of the HP I/O banks.
The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations
are limited to 333 MHz for all speed grades and I/O bank types.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
PL Switching Characteristics
IOB Pad Input/Output/3-State
Table 52 (3.3V high-range IOB (HR)) and Table 53 (1.8V high-performance IOB (HP)) summarizes the values of standardspecific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.
•
TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
•
TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
depending on the capability of the SelectIO output buffer.
•
TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI
termination turn-on time is always faster than TIOTP when the DCITERMDISABLE pin is used. In HR I/O banks, the
IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used.
Table 52: 3.3V IOB High Range (HR) Switching Characteristics
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-3
-2
-1
-3
-2
-1
LVTTL_S4
1.31
1.42
1.64
3.77
3.90
4.00
4.53
4.76
4.99
ns
LVTTL_S8
1.31
1.42
1.64
3.50
3.64
3.73
4.26
4.50
4.72
ns
LVTTL_S12
1.31
1.42
1.64
3.49
3.62
3.72
4.25
4.48
4.71
ns
LVTTL_S16
1.31
1.42
1.64
3.03
3.17
3.26
3.79
4.03
4.25
ns
LVTTL_S24
1.31
1.42
1.64
3.25
3.39
3.48
4.01
4.25
4.47
ns
LVTTL_F4
1.31
1.42
1.64
3.22
3.36
3.45
3.98
4.22
4.44
ns
LVTTL_F8
1.31
1.42
1.64
2.71
2.84
2.93
3.47
3.70
3.92
ns
LVTTL_F12
1.31
1.42
1.64
2.69
2.82
2.92
3.45
3.68
3.91
ns
LVTTL_F16
1.31
1.42
1.64
2.57
2.85
3.15
3.33
3.71
4.14
ns
LVTTL_F24
1.31
1.42
1.64
2.41
2.64
2.89
3.17
3.50
3.88
ns
LVDS_25(1)
0.64
0.68
0.80
1.36
1.47
1.55
2.12
2.33
2.54
ns
MINI_LVDS_25
0.68
0.70
0.79
1.36
1.47
1.55
2.12
2.33
2.54
ns
BLVDS_25(1)
0.65
0.69
0.80
1.83
2.02
2.20
2.59
2.88
3.19
ns
RSDS_25(1)
0.63
0.68
0.79
1.36
1.48
1.55
2.12
2.34
2.54
ns
PPDS_25(1)
0.65
0.69
0.80
1.36
1.49
1.58
2.12
2.35
2.57
ns
TMDS_33(1)
0.72
0.76
0.86
1.43
1.54
1.60
2.19
2.40
2.59
ns
PCI33_3(1)
1.28
1.41
1.65
2.71
3.08
3.52
3.47
3.94
4.51
ns
HSUL_12
0.63
0.64
0.71
1.77
1.90
2.00
2.53
2.76
2.99
ns
DIFF_HSUL_12
0.58
0.61
0.70
1.55
1.68
1.78
2.31
2.54
2.77
ns
HSTL_I_S
0.61
0.64
0.73
1.55
1.69
1.80
2.31
2.55
2.79
ns
HSTL_II_S
0.61
0.64
0.73
1.21
1.34
1.43
1.97
2.20
2.42
ns
HSTL_I_18_S
0.64
0.67
0.76
1.28
1.39
1.45
2.04
2.25
2.44
ns
HSTL_II_18_S
0.64
0.67
0.76
1.18
1.31
1.40
1.94
2.17
2.39
ns
DIFF_HSTL_I_S
0.63
0.67
0.77
1.42
1.54
1.61
2.18
2.40
2.60
ns
DIFF_HSTL_II_S
0.63
0.67
0.77
1.15
1.24
1.27
1.91
2.10
2.26
ns
DIFF_HSTL_I_18_S
0.65
0.69
0.78
1.27
1.38
1.43
2.03
2.24
2.42
ns
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 52: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-3
-2
-1
-3
-2
-1
DIFF_HSTL_II_18_S
0.65
0.69
0.78
1.14
1.23
1.26
1.90
2.09
2.25
ns
HSTL_I_F
0.61
0.64
0.73
1.10
1.19
1.23
1.86
2.05
2.22
ns
HSTL_II_F
0.61
0.64
0.73
1.05
1.18
1.28
1.81
2.04
2.27
ns
HSTL_I_18_F
0.64
0.67
0.76
1.05
1.18
1.28
1.81
2.04
2.27
ns
HSTL_II_18_F
0.64
0.67
0.76
1.03
1.14
1.23
1.79
2.00
2.22
ns
DIFF_HSTL_I_F
0.63
0.67
0.77
1.09
1.18
1.22
1.85
2.04
2.21
ns
DIFF_HSTL_II_F
0.63
0.67
0.77
1.02
1.11
1.14
1.78
1.97
2.13
ns
DIFF_HSTL_I_18_F
0.65
0.69
0.78
1.08
1.17
1.21
1.84
2.03
2.20
ns
DIFF_HSTL_II_18_F
0.65
0.69
0.78
1.01
1.10
1.13
1.77
1.96
2.12
ns
LVCMOS33_S4
1.31
1.40
1.60
3.77
3.90
4.00
4.53
4.76
4.99
ns
LVCMOS33_S8
1.31
1.40
1.60
3.49
3.62
3.72
4.25
4.48
4.71
ns
LVCMOS33_S12
1.31
1.40
1.60
3.05
3.18
3.28
3.81
4.04
4.27
ns
LVCMOS33_S16
1.31
1.40
1.60
3.06
3.43
3.88
3.82
4.29
4.87
ns
LVCMOS33_F4
1.31
1.40
1.60
3.22
3.36
3.45
3.98
4.22
4.44
ns
LVCMOS33_F8
1.31
1.40
1.60
2.71
2.84
2.93
3.47
3.70
3.92
ns
LVCMOS33_F12
1.31
1.40
1.60
2.57
2.85
3.15
3.33
3.71
4.14
ns
LVCMOS33_F16
1.31
1.40
1.60
2.44
2.69
2.96
3.20
3.55
3.95
ns
LVCMOS25_S4
1.08
1.16
1.32
3.08
3.22
3.31
3.84
4.08
4.30
ns
LVCMOS25_S8
1.08
1.16
1.32
2.85
2.98
3.07
3.61
3.84
4.06
ns
LVCMOS25_S12
1.08
1.16
1.32
2.44
2.57
2.67
3.20
3.43
3.66
ns
LVCMOS25_S16
1.08
1.16
1.32
2.79
2.92
3.01
3.55
3.78
4.00
ns
LVCMOS25_F4
1.08
1.16
1.32
2.71
2.84
2.93
3.47
3.70
3.92
ns
LVCMOS25_F8
1.08
1.16
1.32
2.14
2.28
2.37
2.90
3.14
3.36
ns
LVCMOS25_F12
1.08
1.16
1.32
2.15
2.29
2.52
2.91
3.15
3.51
ns
LVCMOS25_F16
1.08
1.16
1.32
1.92
2.17
2.45
2.68
3.03
3.44
ns
LVCMOS18_S4
0.64
0.66
0.74
1.55
1.68
1.78
2.31
2.54
2.77
ns
LVCMOS18_S8
0.64
0.66
0.74
2.14
2.28
2.37
2.90
3.14
3.36
ns
LVCMOS18_S12
0.64
0.66
0.74
2.14
2.28
2.37
2.90
3.14
3.36
ns
LVCMOS18_S16
0.64
0.66
0.74
1.49
1.62
1.72
2.25
2.48
2.71
ns
LVCMOS18_S24(1)
0.64
0.66
0.74
1.74
1.92
2.08
2.50
2.78
3.07
ns
LVCMOS18_F4
0.64
0.66
0.74
1.38
1.51
1.61
2.14
2.37
2.60
ns
LVCMOS18_F8
0.64
0.66
0.74
1.64
1.78
1.87
2.40
2.64
2.86
ns
LVCMOS18_F12
0.64
0.66
0.74
1.64
1.78
1.87
2.40
2.64
2.86
ns
LVCMOS18_F16
0.64
0.66
0.74
1.52
1.68
1.81
2.28
2.54
2.80
ns
LVCMOS18_F24(1)
0.64
0.66
0.74
1.34
1.46
1.55
2.10
2.32
2.54
ns
LVCMOS15_S4
0.66
0.69
0.81
1.86
2.00
2.09
2.62
2.86
3.08
ns
LVCMOS15_S8
0.66
0.69
0.81
2.05
2.18
2.28
2.81
3.04
3.27
ns
LVCMOS15_S12
0.66
0.69
0.81
1.83
2.03
2.23
2.59
2.89
3.22
ns
DS191 (v1.4) April 24, 2013
Preliminary Product Specification
www.xilinx.com
36
Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 52: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-3
-2
-1
-3
-2
-1
LVCMOS15_S16
0.66
0.69
0.81
1.76
1.95
2.13
2.52
2.81
3.12
ns
LVCMOS15_F4
0.66
0.69
0.81
1.63
1.76
1.86
2.39
2.62
2.85
ns
LVCMOS15_F8
0.66
0.69
0.81
1.79
1.99
2.18
2.55
2.85
3.17
ns
LVCMOS15_F12
0.66
0.69
0.81
1.40
1.54
1.65
2.16
2.40
2.64
ns
LVCMOS15_F16
0.66
0.69
0.81
1.37
1.51
1.61
2.13
2.37
2.60
ns
LVCMOS12_S4
0.88
0.91
1.00
2.53
2.67
2.76
3.29
3.53
3.75
ns
LVCMOS12_S8
0.88
0.91
1.00
2.05
2.18
2.28
2.81
3.04
3.27
ns
LVCMOS12_S12(1)
0.88
0.91
1.00
1.75
1.89
1.98
2.51
2.75
2.97
ns
LVCMOS12_F4
0.88
0.91
1.00
1.94
2.07
2.17
2.70
2.93
3.16
ns
LVCMOS12_F8
0.88
0.91
1.00
1.50
1.64
1.73
2.26
2.50
2.72
ns
LVCMOS12_F12(1)
0.88
0.91
1.00
1.54
1.71
1.87
2.30
2.57
2.86
ns
SSTL135_S
0.61
0.64
0.73
1.27
1.40
1.50
2.03
2.26
2.49
ns
SSTL15_S
0.61
0.64
0.73
1.24
1.37
1.47
2.00
2.23
2.46
ns
SSTL18_I_S
0.64
0.67
0.76
1.59
1.74
1.85
2.35
2.60
2.84
ns
SSTL18_II_S
0.64
0.67
0.76
1.27
1.40
1.50
2.03
2.26
2.49
ns
DIFF_SSTL135_S
0.59
0.61
0.73
1.27
1.40
1.50
2.03
2.26
2.49
ns
DIFF_SSTL15_S
0.63
0.67
0.77
1.24
1.37
1.47
2.00
2.23
2.46
ns
DIFF_SSTL18_I_S
0.65
0.69
0.78
1.50
1.63
1.72
2.26
2.49
2.71
ns
DIFF_SSTL18_II_S
0.65
0.69
0.78
1.13
1.22
1.25
1.89
2.08
2.24
ns
SSTL135_F
0.61
0.64
0.73
1.04
1.17
1.26
1.80
2.03
2.25
ns
SSTL15_F
0.61
0.64
0.73
1.04
1.17
1.26
1.80
2.03
2.25
ns
SSTL18_I_F
0.64
0.67
0.76
1.12
1.22
1.26
1.88
2.08
2.25
ns
SSTL18_II_F
0.64
0.67
0.76
1.05
1.18
1.28
1.81
2.04
2.27
ns
DIFF_SSTL135_F
0.59
0.61
0.73
1.04
1.17
1.26
1.80
2.03
2.25
ns
DIFF_SSTL15_F
0.63
0.67
0.77
1.04
1.17
1.26
1.80
2.03
2.25
ns
DIFF_SSTL18_I_F
0.65
0.69
0.78
1.10
1.19
1.23
1.86
2.05
2.22
ns
DIFF_SSTL18_II_F
0.65
0.69
0.78
1.02
1.10
1.14
1.78
1.96
2.13
ns
Notes:
1.
This I/O standard is only available in the 3.3V high-range (HR) banks.
DS191 (v1.4) April 24, 2013
Preliminary Product Specification
www.xilinx.com
37
Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 53: 1.8V IOB High Performance (HP) Switching Characteristics
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-3
-2
-1
-3
-2
-1
LVDS
0.75
0.79
0.92
1.05
1.17
1.24
1.68
1.92
2.06
ns
HSUL_12
0.69
0.72
0.82
1.65
1.84
2.05
2.29
2.59
2.87
ns
DIFF_HSUL_12
0.69
0.72
0.82
1.65
1.84
2.05
2.29
2.59
2.87
ns
HSTL_I_S
0.68
0.72
0.82
1.15
1.28
1.38
1.79
2.03
2.20
ns
HSTL_II_S
0.68
0.72
0.82
1.05
1.17
1.26
1.69
1.93
2.08
ns
HSTL_I_18_S
0.70
0.72
0.82
1.12
1.24
1.34
1.75
2.00
2.16
ns
HSTL_II_18_S
0.70
0.72
0.82
1.06
1.18
1.26
1.70
1.94
2.08
ns
HSTL_I_12_S
0.68
0.72
0.82
1.14
1.27
1.37
1.78
2.02
2.20
ns
HSTL_I_DCI_S
0.68
0.72
0.82
1.11
1.23
1.33
1.74
1.99
2.15
ns
HSTL_II_DCI_S
0.68
0.72
0.82
1.05
1.17
1.26
1.69
1.93
2.08
ns
HSTL_II_T_DCI_S
0.70
0.72
0.82
1.15
1.28
1.38
1.78
2.03
2.20
ns
HSTL_I_DCI_18_S
0.70
0.72
0.82
1.11
1.23
1.33
1.74
1.99
2.15
ns
HSTL_II_DCI_18_S
0.70
0.72
0.82
1.05
1.16
1.24
1.69
1.92
2.06
ns
HSTL_II _T_DCI_18_S
0.70
0.72
0.82
1.11
1.23
1.33
1.74
1.99
2.15
ns
DIFF_HSTL_I_S
0.75
0.79
0.92
1.15
1.28
1.38
1.79
2.03
2.20
ns
DIFF_HSTL_II_S
0.75
0.79
0.92
1.05
1.17
1.26
1.69
1.93
2.08
ns
DIFF_HSTL_I_DCI_S
0.75
0.79
0.92
1.15
1.28
1.38
1.78
2.03
2.20
ns
DIFF_HSTL_II_DCI_S
0.75
0.79
0.92
1.05
1.17
1.26
1.69
1.93
2.08
ns
DIFF_HSTL_I_18_S
0.75
0.79
0.92
1.12
1.24
1.34
1.75
2.00
2.16
ns
DIFF_HSTL_II_18_S
0.75
0.79
0.92
1.06
1.18
1.26
1.70
1.94
2.08
ns
DIFF_HSTL_I_DCI_18_S
0.75
0.79
0.92
1.11
1.23
1.33
1.74
1.99
2.15
ns
DIFF_HSTL_II_DCI_18_S
0.75
0.79
0.92
1.05
1.16
1.24
1.69
1.92
2.06
ns
DIFF_HSTL_II _T_DCI_18_S
0.75
0.79
0.92
1.11
1.23
1.33
1.74
1.99
2.15
ns
HSTL_I_F
0.68
0.72
0.82
1.02
1.14
1.22
1.66
1.90
2.04
ns
HSTL_II_F
0.68
0.72
0.82
0.97
1.08
1.15
1.61
1.84
1.97
ns
HSTL_I_18_F
0.70
0.72
0.82
1.04
1.16
1.24
1.68
1.91
2.06
ns
HSTL_II_18_F
0.70
0.72
0.82
0.98
1.09
1.16
1.62
1.85
1.98
ns
HSTL_I_12_F
0.68
0.72
0.82
1.02
1.13
1.21
1.65
1.88
2.03
ns
HSTL_I_DCI_F
0.68
0.72
0.82
1.04
1.16
1.24
1.67
1.91
2.06
ns
HSTL_II_DCI_F
0.68
0.72
0.82
0.97
1.08
1.15
1.61
1.84
1.97
ns
HSTL_II_T_DCI_F
0.70
0.72
0.82
1.02
1.14
1.22
1.66
1.90
2.04
ns
HSTL_I_DCI_18_F
0.70
0.72
0.82
1.04
1.16
1.24
1.67
1.91
2.06
ns
HSTL_II_DCI_18_F
0.70
0.72
0.82
0.98
1.09
1.16
1.61
1.85
1.98
ns
HSTL_II _T_DCI_18_F
0.70
0.72
0.82
1.04
1.16
1.24
1.67
1.91
2.06
ns
DIFF_HSTL_I_F
0.75
0.79
0.92
1.02
1.14
1.22
1.66
1.90
2.04
ns
DIFF_HSTL_II_F
0.75
0.79
0.92
0.97
1.08
1.15
1.61
1.84
1.97
ns
DIFF_HSTL_I_DCI_F
0.75
0.79
0.92
1.02
1.14
1.22
1.66
1.90
2.04
ns
DIFF_HSTL_II_DCI_F
0.75
0.79
0.92
0.97
1.08
1.15
1.61
1.84
1.97
ns
DS191 (v1.4) April 24, 2013
Preliminary Product Specification
www.xilinx.com
38
Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 53: 1.8V IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-3
-2
-1
-3
-2
-1
DIFF_HSTL_I_18_F
0.75
0.79
0.92
1.04
1.16
1.24
1.68
1.91
2.06
ns
DIFF_HSTL_II_18_F
0.75
0.79
0.92
0.98
1.09
1.16
1.62
1.85
1.98
ns
DIFF_HSTL_I_DCI_18_F
0.75
0.79
0.92
1.04
1.16
1.24
1.67
1.91
2.06
ns
DIFF_HSTL_II_DCI_18_F
0.75
0.79
0.92
0.98
1.09
1.16
1.61
1.85
1.98
ns
DIFF_HSTL_II _T_DCI_18_F
0.75
0.79
0.92
1.04
1.16
1.24
1.67
1.91
2.06
ns
LVCMOS18_S2
0.47
0.50
0.60
3.95
4.28
4.85
4.59
5.04
5.67
ns
LVCMOS18_S4
0.47
0.50
0.60
2.67
2.98
3.43
3.31
3.73
4.26
ns
LVCMOS18_S6
0.47
0.50
0.60
2.14
2.38
2.72
2.77
3.14
3.54
ns
LVCMOS18_S8
0.47
0.50
0.60
1.98
2.21
2.52
2.61
2.97
3.35
ns
LVCMOS18_S12
0.47
0.50
0.60
1.70
1.91
2.17
2.34
2.67
2.99
ns
LVCMOS18_S16
0.47
0.50
0.60
1.57
1.75
1.97
2.20
2.51
2.79
ns
LVCMOS18_F2
0.47
0.50
0.60
3.50
3.87
4.48
4.14
4.63
5.30
ns
LVCMOS18_F4
0.47
0.50
0.60
2.23
2.50
2.87
2.87
3.25
3.69
ns
LVCMOS18_F6
0.47
0.50
0.60
1.80
2.00
2.26
2.43
2.76
3.08
ns
LVCMOS18_F8
0.47
0.50
0.60
1.46
1.72
2.04
2.10
2.47
2.86
ns
LVCMOS18_F12
0.47
0.50
0.60
1.26
1.40
1.53
1.89
2.16
2.35
ns
LVCMOS18_F16
0.47
0.50
0.60
1.19
1.33
1.44
1.83
2.08
2.26
ns
LVCMOS15_S2
0.59
0.62
0.73
3.55
3.89
4.45
4.19
4.65
5.27
ns
LVCMOS15_S4
0.59
0.62
0.73
2.45
2.70
3.06
3.08
3.45
3.89
ns
LVCMOS15_S6
0.59
0.62
0.73
2.24
2.51
2.88
2.88
3.26
3.71
ns
LVCMOS15_S8
0.59
0.62
0.73
1.91
2.16
2.49
2.55
2.91
3.31
ns
LVCMOS15_S12
0.59
0.62
0.73
1.77
1.98
2.23
2.41
2.73
3.05
ns
LVCMOS15_S16
0.59
0.62
0.73
1.62
1.81
2.02
2.26
2.56
2.84
ns
LVCMOS15_F2
0.59
0.62
0.73
3.38
3.69
4.18
4.02
4.44
5.00
ns
LVCMOS15_F4
0.59
0.62
0.73
2.04
2.21
2.44
2.68
2.97
3.26
ns
LVCMOS15_F6
0.59
0.62
0.73
1.47
1.74
2.09
2.10
2.50
2.91
ns
LVCMOS15_F8
0.59
0.62
0.73
1.31
1.46
1.61
1.95
2.22
2.43
ns
LVCMOS15_F12
0.59
0.62
0.73
1.21
1.34
1.45
1.84
2.10
2.27
ns
LVCMOS15_F16
0.59
0.62
0.73
1.18
1.31
1.41
1.82
2.07
2.23
ns
LVCMOS12_S2
0.64
0.67
0.78
3.38
3.80
4.48
4.02
4.55
5.30
ns
LVCMOS12_S4
0.64
0.67
0.78
2.62
2.94
3.43
3.26
3.70
4.25
ns
LVCMOS12_S6
0.64
0.67
0.78
2.05
2.33
2.72
2.69
3.08
3.54
ns
LVCMOS12_S8
0.64
0.67
0.78
1.94
2.18
2.51
2.58
2.94
3.33
ns
LVCMOS12_F2
0.64
0.67
0.78
2.84
3.15
3.62
3.48
3.90
4.44
ns
LVCMOS12_F4
0.64
0.67
0.78
1.97
2.18
2.44
2.61
2.93
3.26
ns
LVCMOS12_F6
0.64
0.67
0.78
1.33
1.51
1.70
1.96
2.26
2.52
ns
LVCMOS12_F8
0.64
0.67
0.78
1.27
1.42
1.55
1.91
2.18
2.37
ns
LVDCI_18
0.47
0.50
0.60
1.99
2.15
2.35
2.62
2.91
3.17
ns
DS191 (v1.4) April 24, 2013
Preliminary Product Specification
www.xilinx.com
39
Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 53: 1.8V IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-3
-2
-1
-3
-2
-1
LVDCI_15
0.59
0.62
0.73
1.98
2.23
2.58
2.62
2.99
3.40
ns
LVDCI_DV2_18
0.47
0.50
0.60
1.99
2.15
2.34
2.62
2.90
3.17
ns
LVDCI_DV2_15
0.59
0.62
0.73
1.98
2.23
2.58
2.62
2.99
3.40
ns
HSLVDCI_18
0.68
0.72
0.82
1.99
2.15
2.35
2.62
2.91
3.17
ns
HSLVDCI_15
0.68
0.72
0.82
1.98
2.23
2.58
2.62
2.99
3.40
ns
SSTL18_I_S
0.68
0.72
0.82
1.02
1.15
1.24
1.66
1.90
2.07
ns
SSTL18_II_S
0.68
0.72
0.82
1.17
1.29
1.37
1.81
2.05
2.19
ns
SSTL18_I_DCI_S
0.68
0.72
0.82
0.92
1.06
1.17
1.56
1.82
1.99
ns
SSTL18_II_DCI_S
0.68
0.72
0.82
0.88
0.98
1.08
1.51
1.74
1.90
ns
SSTL18_II_T_DCI_S
0.68
0.72
0.82
0.92
1.06
1.17
1.56
1.82
1.99
ns
SSTL15_S
0.68
0.72
0.82
0.94
1.06
1.15
1.58
1.82
1.97
ns
SSTL15_DCI_S
0.68
0.72
0.82
0.94
1.06
1.15
1.57
1.82
1.97
ns
SSTL15_T_DCI_S
0.68
0.72
0.82
0.94
1.06
1.15
1.57
1.82
1.97
ns
SSTL135_S
0.69
0.72
0.82
0.97
1.10
1.19
1.60
1.85
2.01
ns
SSTL135_DCI_S
0.69
0.72
0.82
0.97
1.09
1.19
1.60
1.85
2.01
ns
SSTL135_T_DCI_S
0.69
0.72
0.82
0.97
1.09
1.19
1.60
1.85
2.01
ns
SSTL12_S
0.69
0.72
0.82
0.96
1.09
1.18
1.60
1.84
2.00
ns
SSTL12_DCI_S
0.69
0.72
0.82
1.03
1.17
1.27
1.66
1.92
2.09
ns
SSTL12_T_DCI_S
0.69
0.72
0.82
1.03
1.17
1.27
1.66
1.92
2.09
ns
DIFF_SSTL18_I_S
0.75
0.79
0.92
1.02
1.15
1.24
1.66
1.90
2.07
ns
DIFF_SSTL18_II_S
0.75
0.79
0.92
1.17
1.29
1.37
1.81
2.05
2.19
ns
DIFF_SSTL18_I_DCI_S
0.75
0.79
0.92
0.92
1.06
1.17
1.56
1.82
1.99
ns
DIFF_SSTL18_II_DCI_S
0.75
0.79
0.92
0.88
0.98
1.08
1.51
1.74
1.90
ns
DIFF_SSTL18_II_T_DCI_S
0.75
0.79
0.92
0.92
1.06
1.17
1.56
1.82
1.99
ns
DIFF_SSTL15_S
0.68
0.72
0.82
0.94
1.06
1.15
1.58
1.82
1.97
ns
DIFF_SSTL15_DCI_S
0.68
0.72
0.82
0.94
1.06
1.15
1.57
1.82
1.97
ns
DIFF_SSTL15_T_DCI_S
0.68
0.72
0.82
0.94
1.06
1.15
1.57
1.82
1.97
ns
DIFF_SSTL135_S
0.69
0.72
0.82
0.97
1.10
1.19
1.60
1.85
2.01
ns
DIFF_SSTL135_DCI_S
0.69
0.72
0.82
0.97
1.09
1.19
1.60
1.85
2.01
ns
DIFF_SSTL135_T_DCI_S
0.69
0.72
0.82
0.97
1.09
1.19
1.60
1.85
2.01
ns
DIFF_SSTL12_S
0.69
0.72
0.82
0.96
1.09
1.18
1.60
1.84
2.00
ns
DIFF_SSTL12_DCI_S
0.69
0.72
0.82
1.03
1.17
1.27
1.66
1.92
2.09
ns
DIFF_SSTL12_T_DCI_S
0.69
0.72
0.82
1.03
1.17
1.27
1.66
1.92
2.09
ns
SSTL18_I_F
0.68
0.72
0.82
0.94
1.06
1.15
1.58
1.82
1.97
ns
SSTL18_II_F
0.68
0.72
0.82
0.97
1.09
1.16
1.61
1.84
1.99
ns
SSTL18_I_DCI_F
0.68
0.72
0.82
0.89
1.02
1.10
1.53
1.77
1.92
ns
SSTL18_II_DCI_F
0.68
0.72
0.82
0.89
1.02
1.10
1.53
1.77
1.92
ns
SSTL18_II_T_DCI_F
0.68
0.72
0.82
0.89
1.02
1.10
1.53
1.77
1.92
ns
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 53: 1.8V IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-3
-2
-1
-3
-2
-1
SSTL15_F
0.68
0.72
0.82
0.89
1.01
1.09
1.53
1.77
1.91
ns
SSTL15_DCI_F
0.68
0.72
0.82
0.89
1.01
1.09
1.53
1.77
1.91
ns
SSTL15_T_DCI_F
0.68
0.72
0.82
0.89
1.01
1.09
1.53
1.77
1.91
ns
SSTL135_F
0.69
0.72
0.82
0.88
1.00
1.08
1.52
1.76
1.90
ns
SSTL135_DCI_F
0.69
0.72
0.82
0.89
1.00
1.08
1.52
1.76
1.90
ns
SSTL135_T_DCI_F
0.69
0.72
0.82
0.89
1.00
1.08
1.52
1.76
1.90
ns
SSTL12_F
0.69
0.72
0.82
0.88
1.00
1.08
1.52
1.76
1.90
ns
SSTL12_DCI_F
0.69
0.72
0.82
0.91
1.03
1.11
1.54
1.79
1.93
ns
SSTL12_T_DCI_F
0.69
0.72
0.82
0.91
1.03
1.11
1.54
1.79
1.93
ns
DIFF_SSTL18_I_F
0.75
0.79
0.92
0.94
1.06
1.15
1.58
1.82
1.97
ns
DIFF_SSTL18_II_F
0.75
0.79
0.92
0.97
1.09
1.16
1.61
1.84
1.99
ns
DIFF_SSTL18_I_DCI_F
0.75
0.79
0.92
0.89
1.02
1.10
1.53
1.77
1.92
ns
DIFF_SSTL18_II_DCI_F
0.75
0.79
0.92
0.89
1.02
1.10
1.53
1.77
1.92
ns
DIFF_SSTL18_II_T_DCI_F
0.75
0.79
0.92
0.89
1.02
1.10
1.53
1.77
1.92
ns
DIFF_SSTL15_F
0.68
0.72
0.82
0.89
1.01
1.09
1.53
1.77
1.91
ns
DIFF_SSTL15_DCI_F
0.68
0.72
0.82
0.89
1.01
1.09
1.53
1.77
1.91
ns
DIFF_SSTL15_T_DCI_F
0.68
0.72
0.82
0.89
1.01
1.09
1.53
1.77
1.91
ns
DIFF_SSTL135_F
0.69
0.72
0.82
0.88
1.00
1.08
1.52
1.76
1.90
ns
DIFF_SSTL135_DCI_F
0.69
0.72
0.82
0.89
1.00
1.08
1.52
1.76
1.90
ns
DIFF_SSTL135_T_DCI_F
0.69
0.72
0.82
0.89
1.00
1.08
1.52
1.76
1.90
ns
DIFF_SSTL12_F
0.69
0.72
0.82
0.88
1.00
1.08
1.52
1.76
1.90
ns
DIFF_SSTL12_DCI_F
0.69
0.72
0.82
0.91
1.03
1.11
1.54
1.79
1.93
ns
DIFF_SSTL12_T_DCI_F
0.69
0.72
0.82
0.91
1.03
1.11
1.54
1.79
1.93
ns
Notes:
1.
This I/O standard is only available in the 1.8V high-performance (HP) banks.
Table 54 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described
as the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster
than TIOTPHZ when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is
always faster than TIOTPHZ when the INTERMDISABLE pin is used.
Table 54: IOB 3-state Output Switching Characteristics
Symbol
Speed Grade
Description
-3
-2
-1
Units
TIOTPHZ
T input to pad high-impedance
0.76
0.86
0.99
ns
TIOIBUFDISABLE_HR
IBUF turn-on time from IBUFDISABLE to O output for HR
I/O banks
1.72
1.89
2.14
ns
TIOIBUFDISABLE_HP
IBUF turn-on time from IBUFDISABLE to O output for HP
I/O banks
1.31
1.46
1.76
ns
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Input/Output Logic Switching Characteristics
Table 55: ILOGIC Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1
Units
Setup/Hold
TICE1CK/TICKCE1
CE1 pin setup/hold with respect to CLK
0.42/0.00
0.48/0.00
0.67/0.00
ns
TISRCK/TICKSR
SR pin setup/hold with respect to CLK
0.53/0.01
0.61/0.01
0.99/0.01
ns
TIDOCKE2/TIOCKDE2
D pin setup/hold with respect to CLK without delay
(HP I/O banks only)
0.01/0.27
0.01/0.29
0.01/0.34
ns
TIDOCKDE2/TIOCKDDE2 DDLY pin setup/hold with respect to CLK (using IDELAY)
(HP I/O banks only)
0.01/0.27
0.02/0.29
0.02/0.34
ns
TIDOCKE3/TIOCKDE3
0.01/0.27
0.01/0.29
0.01/0.34
ns
0.01/0.27
0.02/0.29
0.02/0.34
ns
D pin setup/hold with respect to CLK without delay
(HR I/O banks only)
TIDOCKDE3/TIOCKDDE3 DDLY pin setup/hold with respect to CLK (using IDELAY)
(HR I/O banks only)
Combinatorial
TIDIE2
D pin to O pin propagation delay, no delay
(HP I/O banks only)
0.09
0.10
0.12
ns
TIDIDE2
DDLY pin to O pin propagation delay (using IDELAY)
(HP I/O banks only)
0.10
0.11
0.13
ns
TIDIE3
D pin to O pin propagation delay, no delay
(HR I/O banks only)
0.09
0.10
0.12
ns
TIDIDE3
DDLY pin to O pin propagation delay (using IDELAY)
(HR I/O banks only)
0.10
0.11
0.13
ns
TIDLOE2
D pin to Q1 pin using flip-flop as a latch without delay
(HP I/O banks only)
0.36
0.39
0.45
ns
TIDLODE2
DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)
(HP I/O banks only)
0.36
0.39
0.45
ns
TIDLOE3
D pin to Q1 pin using flip-flop as a latch without delay
(HR I/O banks only)
0.36
0.39
0.45
ns
TIDLODE3
DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)
(HR I/O banks only)
0.36
0.39
0.45
ns
TICKQ
CLK to Q outputs
0.47
0.50
0.58
ns
TRQ_ILOGICE2
SR pin to OQ/TQ out (HP I/O banks only)
0.84
0.94
1.16
ns
TGSRQ_ILOGICE2
Global set/reset to Q outputs (HP I/O banks only)
7.60
7.60
10.51
ns
TRQ_ILOGICE3
SR pin to OQ/TQ out (HR I/O banks only)
0.84
0.94
1.16
ns
TGSRQ_ILOGICE3
Global set/reset to Q outputs (HR I/O banks only)
7.60
7.60
10.51
ns
TRPW_ILOGICE2
Minimum pulse width, SR inputs (HP I/O banks only)
0.54
0.63
0.63
ns, Min
TRPW_ILOGICE3
Minimum pulse width, SR inputs (HR I/O banks only)
0.54
0.63
0.63
ns, Min
Sequential Delays
Set/Reset
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 56: OLOGIC Switching Characteristics
Symbol
Speed Grade
Description
-3
-2
-1
Units
Setup/Hold
TODCK/TOCKD
D1/D2 pins setup/hold with respect to CLK
0.45/–0.13
0.50/–0.13
0.58/–0.13
ns
TOOCECK/TOCKOCE
OCE pin setup/hold with respect to CLK
0.28/0.03
0.29/0.03
0.45/0.03
ns
TOSRCK/TOCKSR
SR pin setup/hold with respect to CLK
0.32/0.18
0.38/0.18
0.70/0.18
ns
TOTCK/TOCKT
T1/T2 pins setup/hold with respect to CLK
0.49/–0.16
0.56/–0.16
0.68/–0.16
ns
TOTCECK/TOCKTCE
TCE pin setup/hold with respect to CLK
0.28/0.01
0.30/0.01
0.45/0.01
ns
D1 to OQ out or T1 to TQ out
0.73
0.81
0.97
ns
TOCKQ
CLK to OQ/TQ out
0.41
0.43
0.49
ns
TRQ_OLOGICE2
SR pin to OQ/TQ out (HP I/O banks only)
0.63
0.70
0.83
ns
TGSRQ_OLOGICE2
Global set/reset to Q outputs (HP I/O banks only)
7.60
7.60
10.51
ns
TRQ_OLOGICE3
SR pin to OQ/TQ out (HR I/O banks only)
0.63
0.70
0.83
ns
TGSRQ_OLOGICE3
Global set/reset to Q outputs (HR I/O banks only)
7.60
7.60
10.51
ns
TRPW_OLOGICE2
Minimum pulse width, SR inputs (HP I/O banks only)
0.54
0.54
0.63
ns, Min
TRPW_OLOGICE3
Minimum pulse width, SR inputs (HR I/O banks only)
0.54
0.54
0.63
ns, Min
Combinatorial
TODQ
Sequential Delays
Set/Reset
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 57: ISERDES Switching Characteristics
Symbol
Speed Grade
Description
Units
-3
-2
-1
BITSLIP pin setup/hold with respect to CLKDIV
0.01/0.12
0.02/0.13
0.02/0.15
ns
CE pin setup/hold with respect to CLK (for CE1)
0.39/–0.02
0.44/–0.02
0.63/–0.02
ns
CE pin setup/hold with respect to CLKDIV (for CE2)
–0.12/0.29
–0.12/0.31
–0.12/0.35
ns
TISDCK_D /TISCKD_D
D pin setup/hold with respect to CLK
–0.02/0.11
–0.02/0.12
–0.02/0.15
ns
TISDCK_DDLY /TISCKD_DDLY
DDLY pin setup/hold with respect to CLK (using
IDELAY)(1)
–0.02/0.11
–0.02/0.12
–0.02/0.15
ns
TISDCK_D_DDR /TISCKD_D_DDR
D pin setup/hold with respect to CLK at DDR mode
–0.02/0.11
–0.02/0.12
–0.02/0.15
ns
TISDCK_DDLY_DDR/
TISCKD_DDLY_DDR
D pin setup/hold with respect to CLK at DDR mode
(using IDELAY)(1)
0.11/0.11
0.12/0.12
0.15/0.15
ns
CLKDIV to out at Q pin
0.46
0.47
0.58
ns
D input to DO output pin
0.09
0.10
0.12
ns
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP
TISCCK_CE / TISCKC_CE
TISCCK_CE2 /
(2)
TISCKC_CE2(2)
Setup/Hold for Data Lines
Sequential Delays
TISCKO_Q
Propagation Delays
TISDO_DO
Notes:
1.
2.
Recorded at 0 tap value.
TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in the timing report.
Output Serializer/Deserializer Switching Characteristics
Table 58: OSERDES Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
D input setup/hold with respect to CLKDIV
0.37/0.02
0.40/0.02
0.55/0.02
ns
T input setup/hold with respect to CLK
0.49/–0.15
0.56/–0.15
0.68/–0.15
ns
T input setup/hold with respect to CLKDIV
0.27/–0.15
0.30/–0.15
0.34/–0.15
ns
TOSCCK_OCE/TOSCKC_OCE
OCE input setup/hold with respect to CLK
0.28/0.03
0.29/0.03
0.45/0.03
ns
TOSCCK_S
SR (reset) input setup with respect to CLKDIV
0.41
0.46
0.75
ns
TOSCCK_TCE/TOSCKC_TCE
TCE input setup/hold with respect to CLK
0.28/0.01
0.30/0.01
0.45/0.01
ns
Setup/Hold
TOSDCK_D/TOSCKD_D
TOSDCK_T/TOSCKD_T(1)
TOSDCK_T2/TOSCKD_T2
(1)
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
0.35
0.37
0.42
ns
TOSCKO_TQ
Clock to out from CLK to TQ
0.41
0.43
0.49
ns
T input to TQ out
0.73
0.81
0.97
ns
Combinatorial
TOSDO_TTQ
Notes:
1.
TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the timing report.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Input/Output Delay Switching Characteristics
Table 59: Input/Output Delay Switching Characteristics
Symbol
Speed Grade
Description
-3
-2
-1
Units
IDELAYCTRL
TDLYCCO_RDY
FIDELAYCTRL_REF
Reset to ready for IDELAYCTRL
3.22
3.22
3.22
µs
Attribute REFCLK frequency =
200.0(1)
200
200
200
MHz
Attribute REFCLK frequency =
300.0(1)
300
300
N/A
MHz
±10
±10
±10
MHz
52.00
52.00
52.00
ns
IDELAYCTRL_REF_PRECISION
REFCLK precision
TIDELAYCTRL_RPW
Minimum reset pulse width
IDELAY/ODELAY
TIDELAYRESOLUTION
IDELAY/ODELAY chain delay resolution
1/(32 x 2 x FREF)
ps
Pattern dependent period jitter in delay chain for
clock pattern.(2)
0
0
0
ps
per tap
Pattern dependent period jitter in delay chain for
random data pattern (PRBS 23)(3)
±5
±5
±5
ps
per tap
Pattern dependent period jitter in delay chain for
random data pattern (PRBS 23)(4)
±9
±9
±9
ps
per tap
TIDELAY_CLK_MAX/TODELAY_CLK_MAX
Maximum frequency of CLK input to
IDELAY/ODELAY
800
800
710
MHz
TIDCCK_CE / TIDCKC_CE
CE pin setup/hold with respect to C for IDELAY
0.11/0.10
0.14/0.12
0.18/0.14
ns
TODCCK_CE / TODCKC_CE
CE pin setup/hold with respect to C for ODELAY
0.14/0.03
0.16/0.04
0.19/0.05
ns
TIDCCK_INC/ TIDCKC_INC
INC pin setup/hold with respect to C for IDELAY
0.10/0.14
0.12/0.16
0.14/0.20
ns
TODCCK_INC/ TODCKC_INC
INC pin setup/hold with respect to C for ODELAY
0.10/0.07
0.12/0.08
0.13/0.09
ns
TIDCCK_RST/ TIDCKC_RST
RST pin setup/hold with respect to C for IDELAY
0.13/0.08
0.14/0.10
0.16/0.12
ns
TODCCK_RST/ TODCKC_RST
RST pin setup/hold with respect to C for ODELAY
0.16/0.04
0.19/0.06
0.24/0.08
ns
TIDDO_IDATAIN
Propagation delay through IDELAY
Note 5
Note 5
Note 5
ps
TODDO_ODATAIN
Propagation delay through ODELAY
Note 5
Note 5
Note 5
ps
TIDELAYPAT_JIT and TODELAYPAT_JIT
Notes:
1.
2.
3.
4.
5.
Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps.
When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
When HIGH_PERFORMANCE mode is set to TRUE.
When HIGH_PERFORMANCE mode is set to FALSE.
Delay depends on IDELAY/ODELAY tap setting. See the timing report for actual values.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 60: IO_FIFO Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1
Units
IO_FIFO Clock to Out Delays
TOFFCKO_DO
RDCLK to Q outputs
0.51
0.56
0.63
ns
TCKO_FLAGS
Clock to IO_FIFO flags
0.59
0.62
0.81
ns
Setup/Hold
TCCK_D/TCKC_D
D inputs to WRCLK
0.43/–0.01
0.47/–0.01
0.53/–0.01
ns
TIFFCCK_WREN /TIFFCKC_WREN
WREN to WRCLK
0.39/–0.01
0.43/–0.01
0.50/–0.01
ns
TOFFCCK_RDEN/TOFFCKC_RDEN
RDEN to RDCLK
0.49/0.01
0.53/0.02
0.61/0.02
ns
Minimum Pulse Width
TPWH_IO_FIFO
RESET, RDCLK, WRCLK
0.81
0.92
1.08
ns
TPWL_IO_FIFO
RESET, RDCLK, WRCLK
0.81
0.92
1.08
ns
533.05
470.37
400.00
MHz
Maximum Frequency
FMAX
RDCLK and WRCLK
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
CLB Switching Characteristics
Table 61: CLB Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1
Units
Combinatorial Delays
TILO
An – Dn LUT address to A
0.05
0.05
0.06
ns, Max
TILO_2
An – Dn LUT address to AMUX/CMUX
0.15
0.16
0.19
ns, Max
TILO_3
An – Dn LUT address to BMUX_A
0.24
0.25
0.30
ns, Max
TITO
An – Dn inputs to A – D Q outputs
0.58
0.61
0.74
ns, Max
TAXA
AX inputs to AMUX output
0.38
0.40
0.49
ns, Max
TAXB
AX inputs to BMUX output
0.40
0.42
0.52
ns, Max
TAXC
AX inputs to CMUX output
0.39
0.41
0.50
ns, Max
TAXD
AX inputs to DMUX output
0.43
0.44
0.52
ns, Max
TBXB
BX inputs to BMUX output
0.31
0.33
0.40
ns, Max
TBXD
BX inputs to DMUX output
0.38
0.39
0.47
ns, Max
TCXC
CX inputs to CMUX output
0.27
0.28
0.34
ns, Max
TCXD
CX inputs to DMUX output
0.33
0.34
0.41
ns, Max
TDXD
DX inputs to DMUX output
0.32
0.33
0.40
ns, Max
TCKO
Clock to AQ – DQ outputs
0.26
0.27
0.32
ns, Max
TSHCKO
Clock to AMUX – DMUX outputs
0.32
0.32
0.39
ns, Max
Sequential Delays
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TAS/TAH
AN – DN input to CLK on A – D flip-flops
0.01/0.12
0.02/0.13
0.03/0.18
ns, Min
TDICK/TCKDI
AX – DX input to CLK on A – D flip-flops
0.04/0.14
0.04/0.14
0.05/0.20
ns, Min
AX – DX input through MUXs and/or carry logic to CLK on
A – D flip-flops
0.36/0.10
0.37/0.11
0.46/0.16
ns, Min
TCECK_CLB/TCKCE_CLB
CE input to CLK on A – D flip-flops
0.19/0.05
0.20/0.05
0.25/0.05
ns, Min
TSRCK/TCKSR
SR input to CLK on A – D flip-flops
0.30/0.05
0.31/0.07
0.37/0.09
ns, Min
Set/Reset
TSRMIN
SR input minimum pulse width
0.52
0.78
1.04
ns, Min
TRQ
Delay from SR input to AQ – DQ flip-flops
0.38
0.38
0.46
ns, Max
TCEO
Delay from CE input to AQ – DQ flip-flops
0.34
0.35
0.43
ns, Max
FTOG
Toggle frequency (for export control)
1818
1818
1818
MHz
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 62: CLB Distributed RAM Switching Characteristics
Symbol
Speed Grade
Description
-3
-2
-1
Units
Sequential Delays
TSHCKO(1)
Clock to A – B outputs
0.68
0.70
0.85
ns, Max
TSHCKO_1
Clock to AMUX – BMUX outputs
0.91
0.95
1.15
ns, Max
Setup and Hold Times Before/After Clock CLK
TDS_LRAM/TDH_LRAM
A – D inputs to CLK
0.45/0.23
0.45/0.24
0.54/0.27
ns, Min
TAS_LRAM/TAH_LRAM
Address An inputs to clock
0.13/0.50
0.14/0.50
0.17/0.58
ns, Min
Address An inputs through MUXs and/or carry logic to clock 0.40/0.16
0.42/0.17
0.52/0.23
ns, Min
WE input to clock
0.29/0.09
0.30/0.09
0.36/0.09
ns, Min
0.29/0.09
0.30/0.09
0.37/0.09
ns, Min
TWS_LRAM/TWH_LRAM
TCECK_LRAM/TCKCE_LRAM CE input to CLK
Clock CLK
TMPW_LRAM
Minimum pulse width
0.68
0.77
0.91
ns, Min
TMCP
Minimum clock period
1.35
1.54
1.82
ns, Min
Notes:
1.
TSHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 63: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1
Units
Sequential Delays
TREG
Clock to A – D outputs
0.96
0.98
1.20
ns, Max
TREG_MUX
Clock to AMUX – DMUX output
1.19
1.23
1.50
ns, Max
TREG_M31
Clock to DMUX output via M31 output
0.89
0.91
1.10
ns, Max
Setup and Hold Times Before/After Clock CLK
TWS_SHFREG/TWH_SHFREG
WE input
0.26/0.09
0.27/0.09
0.33/0.09
ns, Min
TCECK_SHFREG/TCKCE_SHFREG
CE input to CLK
0.27/0.09
0.28/0.09
0.33/0.09
ns, Min
TDS_SHFREG/TDH_SHFREG
A – D inputs to CLK
0.28/0.26
0.28/0.26
0.33/0.30
ns, Min
Minimum pulse width
0.55
0.65
0.78
ns, Min
Clock CLK
TMPW_SHFREG
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 64: Block RAM and FIFO Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
Clock CLK to DOUT output (without output
register)(2)(3)
1.57
1.80
2.08
ns, Max
Clock CLK to DOUT output (with output
register)(4)(5)
0.54
0.63
0.75
ns, Max
Clock CLK to DOUT output with ECC (without
output register)(2)(3)
2.35
2.58
3.26
ns, Max
Clock CLK to DOUT output with ECC (with output
register)(4)(5)
0.62
0.69
0.80
ns, Max
Clock CLK to DOUT output with Cascade (without
output register)(2)
2.21
2.45
2.80
ns, Max
Clock CLK to DOUT output with Cascade (with
output register)(4)
0.98
1.08
1.24
ns, Max
Clock CLK to FIFO flags outputs(6)
0.65
0.74
0.89
ns, Max
0.79
0.87
0.98
ns, Max
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO and
TRCKO_DO_REG(1)
TRCKO_DO_ECC and
TRCKO_DO_ECC_REG
TRCKO_DO_CASCOUT and
TRCKO_DO_CASCOUT_REG
TRCKO_FLAGS
outputs(7)
TRCKO_POINTERS
Clock CLK to FIFO pointers
TRCKO_PARITY_ECC
Clock CLK to ECCPARITY in ECC encode only
mode
0.66
0.72
0.80
ns, Max
TRCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
Clock CLK to BITERR (without output register)
2.17
2.38
3.01
ns, Max
Clock CLK to BITERR (with output register)
0.57
0.65
0.76
ns, Max
TRCKO_RDADDR_ECC and
TRCKO_RDADDR_ECC_REG
Clock CLK to RDADDR output with ECC (without
output register)
0.64
0.74
0.90
ns, Max
Clock CLK to RDADDR output with ECC (with
output register)
0.71
0.79
0.92
ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDRA/TRCKC_ADDRA
ADDR inputs(8)
0.38/0.27
0.42/0.28
0.48/0.31
ns, Min
TRDCK_DI_WF_NC/
TRCKD_DI_WF_NC
Data input setup/hold time when block RAM is
configured in WRITE_FIRST or NO_CHANGE
mode(9)
0.49/0.51
0.55/0.53
0.63/0.57
ns, Min
TRDCK_DI_RF/TRCKD_DI_RF
Data input setup/hold time when block RAM is
configured in READ_FIRST mode(9)
0.17/0.25
0.19/0.29
0.21/0.35
ns, Min
TRDCK_DI_ECC/TRCKD_DI_ECC
DIN inputs with block RAM ECC in standard
mode(9)
0.42/0.37
0.47/0.39
0.53/0.43
ns, Min
TRDCK_DI_ECCW/TRCKD_DI_ECCW
DIN inputs with block RAM ECC encode only(9)
0.79/0.37
0.87/0.39
0.99/0.43
ns, Min
TRDCK_DI_ECC_FIFO/
TRCKD_DI_ECC_FIFO
DIN inputs with FIFO ECC in standard mode(9)
0.89/0.47
0.98/0.50
1.12/0.54
ns, Min
TRCCK_INJECTBITERR/
TRCKC_INJECTBITERR
Inject single/double bit error in ECC mode
0.49/0.30
0.55/0.31
0.63/0.34
ns, Min
TRCCK_EN/TRCKC_EN
Block RAM Enable (EN) input
0.30/0.17
0.33/0.18
0.38/0.20
ns, Min
TRCCK_REGCE/TRCKC_REGCE
CE input of output register
0.21/0.13
0.25/0.13
0.31/0.14
ns, Min
TRCCK_RSTREG/TRCKC_RSTREG
Synchronous RSTREG input
0.25/0.06
0.27/0.06
0.29/0.06
ns, Min
TRCCK_RSTRAM/TRCKC_RSTRAM
Synchronous RSTRAM input
0.27/0.35
0.29/0.37
0.31/0.39
ns, Min
TRCCK_WEA/TRCKC_WEA
Write Enable (WE) input (Block RAM only)
0.38/0.15
0.41/0.16
0.46/0.17
ns, Min
TRCCK_WREN/TRCKC_WREN
WREN FIFO inputs
0.39/0.25
0.39/0.30
0.40/0.37
ns, Min
TRCCK_RDEN/TRCKC_RDEN
RDEN FIFO inputs
0.36/0.26
0.36/0.30
0.37/0.37
ns, Min
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 64: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
-3
-2
-1
0.76
0.83
0.93
Units
Reset Delays
TRCO_FLAGS
Reset RST to FIFO flags/pointers(10)
TRREC_RST/TRREM_RST
FIFO reset recovery and removal timing(11)
1.59/–0.68 1.76/–0.68 2.01/–0.68
ns, Max
ns, Max
Maximum Frequency
FMAX_BRAM_WF_NC
Block RAM (Write first and No change modes)
When not in SDP RF mode
601.32
543.77
458.09
MHz
FMAX_BRAM_RF_PERFORMANCE
Block RAM (Read first, Performance mode)
When in SDP RF mode but no address overlap
between port A and port B
601.32
543.77
458.09
MHz
FMAX_BRAM_RF_DELAYED_WRITE
Block RAM (Read first, Delayed_write mode)
When in SDP RF mode and there is possibility of
overlap between port A and port B addresses
528.26
477.33
400.80
MHz
FMAX_CAS_WF_NC
Block RAM Cascade (Write first, No change
mode)
When cascade but not in RF mode
551.27
493.93
408.00
MHz
FMAX_CAS_RF_PERFORMANCE
Block RAM Cascade (Read first, Performance
mode)
When in cascade with RF mode and no possibility
of address overlap/one port is disabled
551.27
493.93
408.00
MHz
FMAX_CAS_RF_DELAYED_WRITE
When in cascade RF mode and there is a
possibility of address overlap between port A and
port B
478.24
427.35
350.88
MHz
FMAX_FIFO
FIFO in all modes without ECC
601.32
543.77
458.09
MHz
FMAX_ECC
Block RAM and FIFO in ECC configuration
484.26
430.85
351.12
MHz
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
The timing report shows all of these parameters as TRCKO_DO.
TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
These parameters also apply to synchronous FIFO with DO_REG = 0.
TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.
TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is
possible.
9. These parameters include both A and B inputs as well as the parity inputs of A and B.
10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
DSP48E1 Switching Characteristics
Table 65: DSP48E1 Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1
Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_A_AREG/ TDSPCKD_A_AREG
A input to A register CLK
0.24/0.12
0.27/0.14
0.31/0.16
ns
TDSPDCK_B_BREG/TDSPCKD_B_BREG
B input to B register CLK
0.28/0.13
0.32/0.14
0.39/0.15
ns
TDSPDCK_C_CREG/TDSPCKD_C_CREG
C input to C register CLK
0.15/0.15
0.17/0.17
0.20/0.20
ns
TDSPDCK_D_DREG/TDSPCKD_D_DREG
D input to D register CLK
0.21/0.19
0.27/0.22
0.35/0.26
ns
TDSPDCK_ACIN_AREG/TDSPCKD_ACIN_AREG
ACIN input to A register CLK
0.21/0.12
0.24/0.14
0.27/0.16
ns
TDSPDCK_BCIN_BREG/TDSPCKD_BCIN_BREG
BCIN input to B register CLK
0.22/0.13
0.25/0.14
0.30/0.15
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{A, B}_MREG_MULT/
TDSPCKD_B_MREG_MULT
{A, B,} input to M register CLK using
multiplier
2.04/–0.01 2.34/–0.01 2.79/–0.01
ns
TDSPDCK_{A, B}_ADREG/ TDSPCKD_ D_ADREG
{A, D} input to AD register CLK
1.09/–0.02 1.25/–0.02 1.49/–0.02
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, B}_PREG_MULT/
TDSPCKD_{A, B} _PREG_MULT
{A, B,} input to P register CLK using
multiplier
3.41/–0.24 3.90/–0.24 4.64/–0.24
ns
TDSPDCK_D_PREG_MULT/ TDSPCKD_D_PREG_MULT
D input to P register CLK using
multiplier
3.33/–0.62 3.81/–0.62 4.53/–0.62
ns
TDSPDCK_{A, B} _PREG/
TDSPCKD_{A, B} _PREG
A or B input to P register CLK not using 1.47/–0.24 1.68/–0.24 2.00/–0.24
multiplier
ns
TDSPDCK_C_PREG/ TDSPCKD_C_PREG
C input to P register CLK not using
multiplier
1.30/–0.22 1.49/–0.22 1.78/–0.22
ns
TDSPDCK_PCIN_PREG/ TDSPCKD_PCIN_PREG
PCIN input to P register CLK
1.12/–0.13 1.28/–0.13 1.52/–0.13
ns
Setup and Hold Times of the CE Pins
TDSPDCK_{CEA;CEB}_{AREG;BREG}/
TDSPCKD_{CEA;CEB}_{AREG;BREG}
{CEA; CEB} input to {A; B} register CLK 0.30/0.05
0.36/0.06
0.44/0.09
ns
TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG
CEC input to C register CLK
0.24/0.08
0.29/0.09
0.36/0.11
ns
TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG
CED input to D register CLK
0.31/–0.02 0.36/–0.02 0.44/–0.02
ns
TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG
CEM input to M register CLK
0.26/0.15
0.29/0.17
0.33/0.20
ns
TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG
CEP input to P register CLK
0.31/0.01
0.36/0.01
0.45/0.01
ns
TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/
TDSPCKD_{RSTA; RSTB}_{AREG; BREG}
{RSTA, RSTB} input to {A, B} register
CLK
0.34/0.10
0.39/0.11
0.47/0.13
ns
TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG
RSTC input to C register CLK
0.06/0.22
0.07/0.24
0.08/0.26
ns
TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG
RSTD input to D register CLK
0.37/0.06
0.42/0.06
0.50/0.07
ns
TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG
RSTM input to M register CLK
0.18/0.18
0.20/0.21
0.23/0.24
ns
TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG
RSTP input to P register CLK
0.24/0.01
0.26/0.01
0.30/0.01
ns
Setup and Hold Times of the RST Pins
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_A_CARRYOUT_MULT
A input to CARRYOUT output using
multiplier
3.21
3.69
4.39
ns
TDSPDO_D_P_MULT
D input to P output using multiplier
3.15
3.61
4.30
ns
TDSPDO_A_P
A input to P output not using multiplier
1.30
1.48
1.76
ns
TDSPDO_C_P
C input to P output
1.13
1.30
1.55
ns
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 65: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
-3
-2
-1
Units
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT}
{A, B} input to {ACOUT, BCOUT} output
0.47
0.53
0.63
ns
TDSPDO_{A, B}_CARRYCASCOUT_MULT
{A, B} input to CARRYCASCOUT
output using multiplier
3.44
3.94
4.69
ns
TDSPDO_D_CARRYCASCOUT_MULT
D input to CARRYCASCOUT output
using multiplier
3.36
3.85
4.58
ns
TDSPDO_{A, B}_CARRYCASCOUT
{A, B} input to CARRYCASCOUT
output not using multiplier
1.50
1.72
2.04
ns
TDSPDO_C_CARRYCASCOUT
C input to CARRYCASCOUT output
1.34
1.53
1.83
ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_ACIN_P_MULT
ACIN input to P output using multiplier
3.09
3.55
4.24
ns
TDSPDO_ACIN_P
ACIN input to P output not using
multiplier
1.16
1.33
1.59
ns
TDSPDO_ACIN_ACOUT
ACIN input to ACOUT output
0.32
0.37
0.45
ns
TDSPDO_ACIN_CARRYCASCOUT_MULT
ACIN input to CARRYCASCOUT output
using multiplier
3.30
3.79
4.52
ns
TDSPDO_ACIN_CARRYCASCOUT
ACIN input to CARRYCASCOUT output
not using multiplier
1.37
1.57
1.87
ns
TDSPDO_PCIN_P
PCIN input to P output
0.94
1.08
1.29
ns
TDSPDO_PCIN_CARRYCASCOUT
PCIN input to CARRYCASCOUT output
1.15
1.32
1.57
ns
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_P_PREG
CLK PREG to P output
0.33
0.35
0.39
ns
TDSPCKO_CARRYCASCOUT_PREG
CLK PREG to CARRYCASCOUT
output
0.44
0.50
0.59
ns
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG
CLK MREG to P output
1.42
1.64
1.96
ns
TDSPCKO_CARRYCASCOUT_MREG
CLK MREG to CARRYCASCOUT
output
1.63
1.87
2.24
ns
TDSPCKO_P_ADREG_MULT
CLK ADREG to P output using
multiplier
2.30
2.63
3.13
ns
TDSPCKO_CARRYCASCOUT_ADREG_MULT
CLK ADREG to CARRYCASCOUT
output using multiplier
2.51
2.87
3.41
ns
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_P_AREG_MULT
CLK AREG to P output using multiplier
3.34
3.83
4.55
ns
TDSPCKO_P_BREG
CLK BREG to P output not using
multiplier
1.39
1.59
1.88
ns
TDSPCKO_P_CREG
CLK CREG to P output not using
multiplier
1.43
1.64
1.95
ns
TDSPCKO_P_DREG_MULT
CLK DREG to P output using multiplier
3.32
3.80
4.51
ns
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 65: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
-3
-2
-1
Units
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG}
CLK (ACOUT, BCOUT) to {A,B} register
output
0.55
0.62
0.74
ns
TDSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output using
multiplier
3.55
4.06
4.84
ns
TDSPCKO_CARRYCASCOUT_ BREG
CLK BREG to CARRYCASCOUT
output not using multiplier
1.60
1.82
2.16
ns
TDSPCKO_CARRYCASCOUT_ DREG_MULT
CLK DREG to CARRYCASCOUT
output using multiplier
3.52
4.03
4.79
ns
TDSPCKO_CARRYCASCOUT_ CREG
CLK CREG to CARRYCASCOUT
output
1.64
1.88
2.23
ns
Maximum Frequency
FMAX
With all registers used
741.84
650.20
547.95
MHz
FMAX_PATDET
With pattern detector
627.35
549.75
463.61
MHz
FMAX_MULT_NOMREG
Two register multiply without MREG
412.20
360.75
303.77
MHz
FMAX_MULT_NOMREG_PATDET
Two register multiply without MREG
with pattern detect
374.25
327.65
276.01
MHz
FMAX_PREADD_MULT_NOADREG
Without ADREG
468.82
408.66
342.70
MHz
FMAX_PREADD_MULT_NOADREG_PATDET
Without ADREG with pattern detect
468.82
408.66
342.70
MHz
FMAX_NOPIPELINEREG
Without pipeline registers (MREG,
ADREG)
306.84
267.81
225.02
MHz
FMAX_NOPIPELINEREG_PATDET
Without pipeline registers (MREG,
ADREG) with pattern detect
285.23
249.13
209.38
MHz
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Clock Buffers and Networks
Table 66: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
Description
Speed Grade
-3
-2
-1
Units
TBCCCK_CE/TBCCKC_CE(1)
CE pins setup/hold
0.12/0.30 0.14/0.38 0.26/0.38
ns
TBCCCK_S/TBCCKC_S(1)
S pins setup/hold
0.12/0.30 0.14/0.38 0.26/0.38
ns
TBCCKO_O(2)
BUFGCTRL delay from I0/I1 to O
0.08
0.10
0.12
ns
741.00
710.00
625.00
MHz
Maximum Frequency
FMAX_BUFG
Global clock tree (BUFG)
Notes:
1.
2.
TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Table 67: Input/Output Clock Switching Characteristics (BUFIO)
Symbol
TBIOCKO_O
Description
Clock to out delay from I to O
Speed Grade
Units
-3
-2
-1
1.04
1.14
1.32
ns
800.00
800.00
710.00
MHz
Maximum Frequency
FMAX_BUFIO
I/O clock tree (BUFIO)
Table 68: Regional Clock Buffer Switching Characteristics (BUFR)
Symbol
Description
Speed Grade
-3
-2
-1
Units
TBRCKO_O
Clock to out delay from I to O
0.60
0.65
0.77
ns
TBRCKO_O_BYP
Clock to out delay from I to O with Divide Bypass attribute set
0.30
0.32
0.38
ns
TBRDO_O
Propagation delay from CLR to O
0.71
0.75
0.96
ns
600.00
540.00
450.00
MHz
Maximum Frequency
FMAX_BUFR(1)
Regional clock tree (BUFR)
Notes:
1.
The maximum input frequency to the BUFR and BUFMR is the BUFIO FMAX frequency.
Table 69: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol
Description
TBHCKO_O
BUFH delay from I to O
TBHCCK_CE/TBHCKC_CE
CE pin setup and hold
Speed Grade
-3
-2
-1
0.10
0.11
0.13
0.20/0.16 0.23/0.20 0.38/0.21
Units
ns
ns
Maximum Frequency
FMAX_BUFH
Horizontal clock buffer (BUFH)
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 70: Duty-Cycle Distortion and Clock-Tree Skew
Symbol
TDCD_CLK
TCKSKEW
Description
skew(2)
Units
-3
-2
-1
All
0.20
0.20
0.20
ns
XC7Z030
0.29
0.36
0.37
ns
XC7Z045
0.43
0.54
0.57
ns
XC7Z100
N/A
Global clock tree duty-cycle distortion(1)
Global clock tree
Speed Grade
Device
ns
TDCD_BUFIO
I/O clock tree duty-cycle distortion
All
0.12
0.12
0.12
ns
TBUFIOSKEW
I/O clock tree skew across one clock region
All
0.02
0.02
0.02
ns
TDCD_BUFR
Regional clock tree duty-cycle distortion
All
0.15
0.15
0.15
ns
Notes:
1.
2.
These parameters represent the worst-case duty-cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty-cycle distortion that might be caused by asymmetrical
rise/fall times.
The TCKSKEWvalue represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer
tools to evaluate application specific clock skew.
MMCM Switching Characteristics
Table 71: MMCM Specification
Symbol
Description
Speed Grade
-3
-2
-1
Units
MMCM_FINMAX
Maximum input clock frequency
1066.00
933.00
800.00
MHz
MMCM_FINMIN
Minimum input clock frequency
10.00
10.00
10.00
MHz
MMCM_FINJITTER
Maximum input clock period jitter
< 20% of clock input period or 1 ns Max
MMCM_FINDUTY
Allowable input duty cycle: 10—49 MHz
25.00
25.00
25.00
%
Allowable input duty cycle: 50—199 MHz
30.00
30.00
30.00
%
Allowable input duty cycle: 200—399 MHz
35.00
35.00
35.00
%
Allowable input duty cycle: 400—499 MHz
40.00
40.00
40.00
%
Allowable input duty cycle: >500 MHz
45.00
45.00
45.00
%
MMCM_FMIN_PSCLK
Minimum dynamic phase-shift clock frequency
0.01
0.01
0.01
MHz
MMCM_FMAX_PSCLK
Maximum dynamic phase-shift clock frequency
550.00
500.00
450.00
MHz
MMCM_FVCOMIN
Minimum MMCM VCO frequency
600.00
600.00
600.00
MHz
MMCM_FVCOMAX
Maximum MMCM VCO frequency
1600.00
1440.00
1200.00
MHz
MMCM_FBANDWIDTH
Low MMCM bandwidth at typical(1)
1.00
1.00
1.00
MHz
High MMCM bandwidth at typical(1)
4.00
4.00
4.00
MHz
0.12
0.12
0.12
ns
MMCM_TSTATPHAOFFSET Static phase offset of the MMCM outputs(2)
Note 3
MMCM_TOUTJITTER
MMCM output jitter
MMCM_TOUTDUTY
MMCM output clock duty-cycle precision(4)
MMCM_TLOCKMAX
0.20
0.20
0.20
ns
MMCM maximum lock time
100.00
100.00
100.00
µs
MMCM_FOUTMAX
MMCM maximum output frequency
1066.00
933.00
800.00
MHz
MMCM_FOUTMIN
MMCM minimum output frequency(5)(6)
4.69
4.69
4.69
MHz
MMCM_TEXTFDVAR
External clock feedback variation
< 20% of clock input period or 1 ns Max
MMCM_RSTMINPULSE
Minimum reset pulse width
5.00
5.00
5.00
ns
MMCM_FPFDMAX
Maximum frequency at the phase frequency detector
550.00
500.00
450.00
MHz
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 71: MMCM Specification (Cont’d)
Symbol
Description
MMCM_FPFDMIN
Minimum frequency at the phase frequency detector
MMCM_TFBDELAY
Maximum delay in the feedback path
Speed Grade
-3
-2
-1
10.00
10.00
10.00
Units
MHz
3 ns Max or one CLKIN cycle
MMCM Switching Characteristics Setup and Hold
TMMCMDCK_PSEN/
TMMCMCKD_PSEN
Setup and hold of phase-shift enable
1.04/0.00 1.04/0.00 1.04/0.00
ns
TMMCMDCK_PSINCDEC/
TMMCMCKD_PSINCDEC
Setup and hold of phase-shift increment/decrement
1.04/0.00 1.04/0.00 1.04/0.00
ns
TMMCMCKO_PSDONE
Phase shift clock-to-out of PSDONE
0.59
0.68
0.81
ns
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
TMMCMDCK_DADDR/
TMMCMCKD_DADDR
Setup and hold of D address
1.25/0.15 1.40/0.15 1.63/0.15
ns, Min
TMMCMDCK_DI/
TMMCMCKD_DI
Setup and hold of D input
1.25/0.15 1.40/0.15 1.63/0.15
ns, Min
TMMCMDCK_DEN/
TMMCMCKD_DEN
Setup and hold of D enable
1.76/0.00 1.97/0.00 2.29/0.00
ns, Min
TMMCMDCK_DWE/
TMMCMCKD_DWE
Setup and hold of D write enable
1.25/0.15 1.40/0.15 1.63/0.15
ns, Min
TMMCMCKO_DRDY
CLK to out of DRDY
FDCK
DCLK frequency
0.65
0.72
0.99
ns, Max
200.00
200.00
200.00
MHz, Max
Notes:
1.
2.
3.
4.
5.
6.
The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
The static offset is measured between any MMCM outputs with identical phase.
Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
Includes global clock buffer.
Calculated as FVCO/128 assuming output duty cycle is 50%.
When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
PLL Switching Characteristics
Table 72: PLL Specification
Symbol
Description
Speed Grade
-3
-2
-1
Units
PLL_FINMAX
Maximum input clock frequency
1066.00
933.00
800.00
MHz
PLL_FINMIN
Minimum input clock frequency
19.00
19.00
19.00
MHz
PLL_FINJITTER
Maximum input clock period jitter
< 20% of clock input period or 1 ns Max
PLL_FINDUTY
Allowable input duty cycle: 19—49 MHz
25.00
25.00
25.00
%
Allowable input duty cycle: 50—199 MHz
30.00
30.00
30.00
%
Allowable input duty cycle: 200—399 MHz
35.00
35.00
35.00
%
Allowable input duty cycle: 400—499 MHz
40.00
40.00
40.00
%
Allowable input duty cycle: >500 MHz
45.00
45.00
45.00
%
PLL_FVCOMIN
Minimum PLL VCO frequency
800.00
800.00
800.00
MHz
PLL_FVCOMAX
Maximum PLL VCO frequency
PLL_FBANDWIDTH
PLL_TSTATPHAOFFSET
PLL_TOUTJITTER
2133.00
1866.00
1600.00
MHz
Low PLL bandwidth at
typical(1)
1.00
1.00
1.00
MHz
High PLL bandwidth at
typical(1)
4.00
4.00
4.00
MHz
0.12
0.12
0.12
ns
Static phase offset of the PLL
PLL output
outputs(2)
jitter(3)
Note 1
PLL_TOUTDUTY
PLL output clock duty-cycle
PLL_TLOCKMAX
PLL_FOUTMAX
precision(4)
0.20
0.20
0.20
ns
PLL maximum lock time
100.00
100.00
100.00
µs
PLL maximum output frequency
1066.00
933.00
800.00
MHz
6.25
6.25
6.25
MHz
frequency(5)
PLL_FOUTMIN
PLL minimum output
PLL_TEXTFDVAR
External clock feedback variation
< 20% of clock input period or 1 ns Max
PLL_RSTMINPULSE
Minimum reset pulse width
5.00
5.00
5.00
ns
PLL_FPFDMAX
Maximum frequency at the phase frequency detector
550.00
500.00
450.00
MHz
PLL_FPFDMIN
Minimum frequency at the phase frequency detector
19.00
19.00
19.00
MHz
PLL_TFBDELAY
Maximum delay in the feedback path
3 ns Max or one CLKIN cycle
Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK
TPLLCCK_DADDR/
TPLLCKC_DADDR
Setup and hold of D address
1.25/0.15 1.40/0.15 1.63/0.15
ns, Min
TPLLCCK_DI/
TPLLCKC_DI
Setup and hold of D input
1.25/0.15 1.40/0.15 1.63/0.15
ns, Min
TPLLCCK_DEN/
TPLLCKC_DEN
Setup and hold of D enable
1.76/0.00 1.97/0.00 2.29/0.00
ns, Min
TPLLCCK_DWE/
TPLLCKC_DWE
Setup and hold of D write enable
1.25/0.15 1.40/0.15 1.63/0.15
ns, Min
TPLLCKO_DRDY
CLK to out of DRDY
FDCK
DCLK frequency
0.65
0.72
0.99
ns, Max
200.00
200.00
200.00
MHz, Max
Notes:
1.
2.
3.
4.
5.
The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
The static offset is measured between any PLL outputs with identical phase.
Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
Includes global clock buffer.
Calculated as FVCO/128 assuming output duty cycle is 50%.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Device Pin-to-Pin Output Parameter Guidelines
Table 73: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
Symbol
Description
Device
Speed Grade
-3
-2
-1
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL.
TICKOF
Clock-capable clock input and OUTFF without
MMCM/PLL (near clock region)
XC7Z030
5.32
5.85
6.55
ns
XC7Z045
5.27
5.78
6.48
ns
XC7Z100
N/A
ns
Notes:
1.
This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 74: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
Symbol
Description
Device
Speed Grade
-3
-2
-1
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL.
TICKOFFAR
Clock-capable clock input and OUTFF without
MMCM/PLL (far clock region)
XC7Z030
5.32
5.85
6.55
ns
XC7Z045
5.88
6.46
7.23
ns
XC7Z100
N/A
ns
Notes:
1.
This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 75: Clock-Capable Clock Input to Output Delay With MMCM
Symbol
Description
Device
Speed Grade
-3
-2
-1
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, with MMCM.
TICKOFMMCMCC
Clock-capable clock input and OUTFF with MMCM
XC7Z030
0.92
0.92
0.92
ns
XC7Z045
0.97
0.97
0.97
ns
XC7Z100
N/A
ns
Notes:
1.
2.
This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
MMCM output jitter is already included in the timing calculation.
Table 76: Clock-Capable Clock Input to Output Delay With PLL
Symbol
Description
Device
Speed Grade
-3
-2
-1
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, with PLL.
TICKOFPLLCC
Clock-capable clock input and OUTFF with PLL
XC7Z030
0.81
0.81
0.81
ns
XC7Z045
0.86
0.86
0.86
ns
XC7Z100
N/A
ns
Notes:
1.
2.
This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
PLL output jitter is already included in the timing calculation.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 77: Pin-to-Pin, Clock-to-Out using BUFIO
Symbol
TICKOFCS
Speed Grade
Description
Units
-3
-2
-1
Clock-to-out of I/O clock for HR I/O banks
4.93
5.52
6.20
ns
Clock-to-out of I/O clock for HP I/O banks
4.85
5.44
6.11
ns
Device Pin-to-Pin Input Parameter Guidelines
Table 78: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Symbol
Description
Device
Speed Grade
-3
-2
-1
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
TPSFD/ TPHFD
Full delay (legacy delay or default delay)
global clock input and IFF(2) without
MMCM/PLL with ZHOLD_DELAY on HR I/O
banks
XC7Z030
3.04/–0.34 3.16/–0.34 3.40/–0.34
ns
XC7Z045
3.50/–0.47 3.67/–0.47 3.97/–0.47
ns
XC7Z100
N/A
ns
Notes:
1.
2.
Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global
clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input
signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input flip-flop or latch.
Table 79: Clock-Capable Clock Input Setup and Hold With MMCM
Symbol
Description
Device
Speed Grade
-3
-2
-1
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
TPSMMCMCC/
TPHMMCMCC
No delay clock-capable clock input and IFF(2)
with MMCM
XC7Z030
2.41/–0.23 2.68/–0.23 2.95/–0.23
ns
XC7Z045
2.73/–0.09 3.00/–0.09 3.32/–0.09
ns
XC7Z100
N/A
ns
Notes:
1.
2.
3.
Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global
clock input signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input flip-flop or latch
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 80: Clock-Capable Clock Input Setup and Hold With PLL
Symbol
Description
Device
Speed Grade
-3
-2
-1
Units
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)
TPSPLLCC/
TPHPLLCC
No delay clock-capable clock input and IFF(2) with
PLL
XC7Z030
2.71/–0.34 3.02/–0.34 3.29/–0.34
ns
XC7Z045
2.91/–0.20 3.24/–0.20 3.53/–0.20
ns
XC7Z100
N/A
ns
Notes:
1.
2.
3.
Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global
clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input
signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input flip-flop or latch
Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 81: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Symbol
TPSCS/TPHCS
Speed Grade
Description
-3
-2
-1
Units
Setup/hold of I/O clock for HR I/O banks
–0.36/1.36 –0.36/1.50 –0.36/1.70
ns
Setup/hold of I/O clock for HP I/O banks
–0.34/1.39 –0.34/1.53 –0.34/1.73
ns
Table 82: Sample Window
Symbol
Speed Grade
Description
-3
-2
-1
Units
TSAMP
Sampling error at receiver pins(1)
0.51
0.56
0.61
ns
TSAMP_BUFIO
Sampling error at receiver pins using BUFIO(2)
0.30
0.35
0.40
ns
Notes:
1.
2.
This parameter indicates the total sampling error of the PL DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
This parameter indicates the total sampling error of the PL DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Additional Package Parameter Guidelines
The parameters in this section provide the necessary values for calculating timing budgets for PL clock transmitter and
receiver data-valid windows.
Table 83: Package Skew
Symbol
TPKGSKEW
Description
Package skew(1)
Device
XC7Z030
XC7Z045
XC7Z100
Package
Value
Units
FBG484
113
ps
FBG676
113
ps
FFG676
136
ps
FBG676
159
ps
FFG676
158
ps
FFG900
191
ps
FFG900
ps
FFG1156
ps
Notes:
1.
2.
These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die
pad to ball.
Package delay information is available for these device/package combinations. This information can be used to deskew the package.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
GTX Transceiver Specifications
GTX Transceiver DC Input and Output Levels
Table 84 summarizes the DC specifications of the GTX transceivers in Zynq-7000 devices. Consult the 7 Series FPGAs
GTX/GTH Transceivers User Guide (UG476) for further details.
Table 84: GTX Transceiver DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
–
–
1000
mV
DVPPOUT
Differential peak-to-peak output Transmitter output swing is set to
maximum setting
voltage (1)
VCMOUTDC
DC common mode output
voltage.
ROUT
Differential output resistance
–
100
–
Ω
TOSKEW
Transmitter output pair (TXP and TXN) intra-pair skew
–
2
12
ps
>10.3125 Gb/s
150
–
1250
mV
6.6 Gb/s to 10.3125 Gb/s
150
–
1250
mV
≤ 6.6 Gb/s
150
–
2000
mV
Differential peak-to-peak input
voltage (external AC coupled)
DVPPIN
Equation based
VMGTAVTT – DVPPOUT/4
mV
VIN
Absolute input voltage
DC coupled VMGTAVTT = 1.2V
–200
–
VMGTAVTT
mV
VCMIN
Common mode input voltage
DC coupled VMGTAVTT = 1.2V
–
2/3 VMGTAVTT
–
mV
RIN
Differential input resistance
–
100
–
Ω
–
100
–
nF
CEXT
Recommended external AC coupling
capacitor(2)
Notes:
1.
2.
The output swing and preemphasis levels are programmable using the attributes discussed in the 7 Series FPGAs GTX/GTH Transceivers
User Guide (UG476) and can result in values lower than reported in this table.
Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 17
+V
P
Single-Ended
Voltage
N
0
ds191_16_010213
Figure 17: Single-Ended Peak-to-Peak Voltage
X-Ref Target - Figure 18
+V
Differential
Voltage
0
–V
P–N
ds191_17_010213
Figure 18: Differential Peak-to-Peak Voltage
Table 85 summarizes the DC specifications of the clock input of the GTX transceiver. Consult the 7 Series FPGAs GTX/GTH
Transceivers User Guide (UG476) for further details.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 85: GTX Transceiver Clock DC Input Level Specification
Symbol
DC Parameter
Min
Typ
Max
Units
250
–
2000
mV
VIDIFF
Differential peak-to-peak input voltage
RIN
Differential input resistance
–
100
–
Ω
CEXT
Required external AC coupling capacitor
–
100
–
nF
GTX Transceiver Switching Characteristics
Consult the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) for further information.
Table 86: GTX Transceiver Performance
Speed Grade
Symbol
Description
-3
Output
Divider
-1(1)
-2
Units
Package Type
FF
FB
FF
FB
FF
FB
FGTXMAX(2)
Maximum GTX transceiver data rate
12.5
6.6
10.3125
6.6
8.0
6.6
Gb/s
FGTXMIN(2)
Minimum GTX transceiver data rate
0.500
0.500
0.500
0.500
0.500
0.500
Gb/s
FGTXCRANGE
CPLL line rate range
1
3.2–6.6
Gb/s
2
1.6–3.3
Gb/s
4
0.8–1.65
Gb/s
8
0.5–0.825
Gb/s
16
N/A
Gb/s
1
FGTXQRANGE1
QPLL line rate range 1
5.93–8.0
5.93–6.6
5.93–8.0
5.93–6.6
5.93–8.0
5.93–6.6
Gb/s
2
2.965–4.0
2.965–4.0
2.965–4.0
Gb/s
4
1.4825–2.0
1.4825–2.0
1.4825–2.0
Gb/s
8
0.74125–1.0
0.74125–1.0
0.74125–1.0
Gb/s
16
N/A
N/A
N/A
Gb/s
N/A
Gb/s
9.8–
12.5
1
N/A
9.8–
10.3125
N/A
2
4.9–6.25
4.9–5.15625
N/A
Gb/s
4
2.45–3.125
2.45–2.578125
N/A
Gb/s
8
1.225–1.5625
1.225–1.2890625
N/A
Gb/s
16
0.6125–0.78125
0.6125–0.64453125
N/A
Gb/s
1.6–3.3
1.6–3.3
1.6–3.3
GHz
FGQPLLRANGE1 GTX transceiver QPLL frequency range 1
5.93–8.0
5.93–8.0
5.93–8.0
GHz
FGQPLLRANGE2 GTX transceiver QPLL frequency range 2
9.8–12.5
9.8–10.3125
N/A
GHz
FGTXQRANGE2
FGCPLLRANGE
QPLL line rate range 2(3)
GTX transceiver CPLL frequency range
Notes:
1.
2.
3.
The -1 speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s.
Data rates between 8.0 Gb/s and 9.8 Gb/s are not available.
For QPLL line rate range 2, the maximum line rate with the divider N set to 66 is 10.3125Gb/s.
Table 87: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
FGTXDRPCLK
Description
GTXDRPCLK maximum frequency
DS191 (v1.4) April 24, 2013
Preliminary Product Specification
Speed Grade
-3
-2
-1
175.01
175.01
156.25
Units
MHz
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 88: GTX Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
All Speed Grades
Units
Min
Typ
Max
-3 speed grade
60
–
700
MHz
All other speed grades
60
–
670
MHz
FGCLK
Reference clock frequency range
TRCLK
Reference clock rise time
20% – 80%
–
200
–
ps
TFCLK
Reference clock fall time
80% – 20%
–
200
–
ps
TDCREF
Reference clock duty cycle
Transceiver PLL only
40
50
60
%
X-Ref Target - Figure 19
TRCLK
80%
20%
TFCLK
ds191_18_010213
Figure 19: Reference Clock Timing Parameters
Table 89: GTX Transceiver PLL/Lock Time Adaptation
Symbol
TLOCK
TDLOCK
Description
Conditions
Initial PLL lock
Clock recovery phase acquisition and
adaptation time for decision feedback
equalizer (DFE).
Clock recovery phase acquisition and
adaptation time for low-power mode
(LPM) when the DFE is disabled.
DS191 (v1.4) April 24, 2013
Preliminary Product Specification
After the PLL is locked to the
reference clock, this is the time it
takes to lock the clock data
recovery (CDR) to the data
present at the input.
All Speed Grades
Units
Min
Typ
Max
–
–
1
ms
x106
UI
UI
–
50,000
37
–
50,000
2.3 x106
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 90: GTX Transceiver User Clock Switching Characteristics(1)(2)
Symbol
Speed Grade (3)(4)
Data Width Conditions
Description
Internal Logic
Interconnect Logic
-3
-2
-1
Units
FTXOUT
TXOUTCLK maximum frequency
412.500
412.500
312.500
MHz
FRXOUT
RXOUTCLK maximum frequency
412.500
412.500
312.500
MHz
FTXIN
TXUSRCLK maximum frequency
FRXIN
RXUSRCLK maximum frequency
FTXIN2
TXUSRCLK2 maximum frequency
FRXIN2
RXUSRCLK2 maximum frequency
16-bit
16-bit and 32-bit
412.500
412.500
312.500
MHz
32-bit
32-bit
390.625
322.266
250.000
MHz
16-bit
16-bit and 32-bit
412.500
412.500
312.500
MHz
32-bit
32-bit
390.625
322.266
250.000
MHz
16-bit
16-bit
412.500
412.500
312.500
MHz
16-bit and 32-bit 32-bit
390.625
322.266
250.000
MHz
64-bit
64-bit
195.313
161.133
125.000
MHz
16-bit
16-bit
412.500
412.500
312.500
MHz
16-bit and 32-bit 32-bit
390.625
322.266
250.000
MHz
64-bit
195.313
161.133
125.000
MHz
64-bit
Notes:
1.
2.
3.
4.
Clocking must be implemented as described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
These frequencies are not supported for all possible transceiver configurations.
For speed grades -3 and -2, a 16-bit data path can only be used for speeds less than 6.6 Gb/s.
For speed grade -1, a 16-bit data path can only be used for speeds less than 5.0 Gb/s.
Table 91: GTX Transceiver Transmitter Switching Characteristics
Symbol
Description
Condition
Min
Typ
Max
Units
0.500
–
FGTXMAX
Gb/s
–
ps
FGTXTX
Serial data rate range
TRTX
TX rise time
20%–80%
–
40
80%–20%
TFTX
TX fall time
–
40
–
ps
TLLSKEW
TX lane-to-lane skew(1)
–
–
500
ps
VTXOOBVDPP
Electrical idle amplitude
–
–
15
mV
TTXOOBTRANSITION
Electrical idle transition time
–
–
140
ns
jitter(2)(4)
TJ12.5
Total
DJ12.5
Deterministic jitter(2)(4)
TJ11.18
Total jitter(2)(4)
DJ11.18
Deterministic
jitter(2)(4)
jitter(2)(4)
TJ10.3125
Total
DJ10.3125
Deterministic jitter(2)(4)
TJ9.953
DJ9.953
Total
jitter(2)(4)
Deterministic
jitter(2)(4)
jitter(2)(4)
TJ9.8
Total
DJ9.8
Deterministic jitter(2)(4)
TJ8.0
Total jitter(2)(4)
DJ8.0
Deterministic
jitter(2)(4)
jitter(2)(4)
TJ6.6_QPLL
Total
DJ6.6_QPLL
Deterministic jitter(2)(4)
DS191 (v1.4) April 24, 2013
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12.5 Gb/s
11.18 Gb/s
10.3125 Gb/s
9.953 Gb/s
9.8 Gb/s
8.0 Gb/s
6.6 Gb/s
–
–
0.28
UI
–
–
0.17
UI
–
–
0.28
UI
–
–
0.17
UI
–
–
0.28
UI
–
–
0.17
UI
–
–
0.28
UI
–
–
0.17
UI
–
–
0.28
UI
–
–
0.17
UI
–
–
0.33
UI
–
–
0.17
UI
–
–
0.28
UI
–
–
0.17
UI
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 91: GTX Transceiver Transmitter Switching Characteristics (Cont’d)
Symbol
TJ6.6_CPLL
Description
Total
jitter(3)(4)
jitter(3)(4)
DJ6.6_CPLL
Deterministic
TJ5.0
Total jitter(3)(4)
DJ5.0
TJ4.25
Deterministic
Total
jitter(3)(4)
jitter(3)(4)
jitter(3)(4)
DJ4.25
Deterministic
TJ3.75
Total jitter(3)(4)
DJ3.75
Deterministic jitter(3)(4)
TJ3.2
Total
jitter(3)(4)
jitter(3)(4)
DJ3.2
Deterministic
TJ3.2L
Total jitter(3)(4)
DJ3.2L
Deterministic jitter(3)(4)
TJ2.5
Total
jitter(3)(4)
jitter(3)(4)
DJ2.5
Deterministic
TJ1.25
Total jitter(3)(4)
DJ1.25
Deterministic jitter(3)(4)
TJ500
DJ500
Total
jitter(3)(4)
Deterministic
jitter(3)(4)
Condition
6.6 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.20 Gb/s(5)
3.20 Gb/s(6)
2.5 Gb/s(7)
1.25 Gb/s(8)
500 Mb/s
Min
Typ
Max
Units
–
–
0.30
UI
–
–
0.15
UI
–
–
0.33
UI
–
–
0.15
UI
–
–
0.33
UI
–
–
0.14
UI
–
–
0.34
UI
–
–
0.16
UI
–
–
0.2
UI
–
–
0.1
UI
–
–
0.35
UI
–
–
0.16
UI
–
–
0.20
UI
–
–
0.08
UI
–
–
0.15
UI
–
–
0.06
UI
–
–
0.1
UI
–
–
0.03
UI
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTX Quads).
Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
All jitter values are based on a bit-error ratio of 1e-12.
CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
CPLL frequency at 1.6 GHz and TXOUT_DIV = 1.
CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 92: GTX Transceiver Receiver Switching Characteristics
Symbol
Description
RX oversampler not enabled
Min
Typ
Max
Units
0.500
–
FGTXMAX
Gb/s
FGTXRX
Serial data rate
TRXELECIDLE
Time for RXELECIDLE to respond to loss or restoration of data
–
10
–
ns
RXOOBVDPP
OOB detect threshold peak-to-peak
60
–
150
mV
RXSST
Receiver spread-spectrum
tracking(1)
–5000
–
0
ppm
RXRL
Run length (CID)
–
–
512
UI
Bit rates ≤ 6.6 Gb/s
–1250
–
1250
ppm
Bit rates > 6.6 Gb/s and
≤ 8.0 Gb/s
–700
–
700
ppm
Bit rates > 8.0 Gb/s
–200
–
200
ppm
Data/REFCLK PPM offset
tolerance
RXPPMTOL
SJ Jitter
Modulated @ 33 KHz
Tolerance(2)
JT_SJ12.5
JT_SJ11.18
JT_SJ10.32
JT_SJ9.95
JT_SJ9.8
JT_SJ8.0
JT_SJ6.6_QPLL
JT_SJ6.6_CPLL
JT_SJ5.0
JT_SJ4.25
JT_SJ3.75
JT_SJ3.2
JT_SJ3.2L
JT_SJ2.5
JT_SJ1.25
JT_SJ500
Sinusoidal jitter (QPLL)(3)
12.5 Gb/s
0.3
–
–
UI
Sinusoidal jitter
(QPLL)(3)
11.18 Gb/s
0.3
–
–
UI
Sinusoidal jitter
(QPLL)(3)
10.32 Gb/s
0.3
–
–
UI
Sinusoidal jitter
(QPLL)(3)
9.95 Gb/s
0.3
–
–
UI
Sinusoidal jitter
(QPLL)(3)
9.8 Gb/s
0.3
–
–
UI
Sinusoidal jitter
(QPLL)(3)
8.0 Gb/s
0.44
–
–
UI
Sinusoidal jitter
(QPLL)(3)
6.6 Gb/s
0.48
–
–
UI
Sinusoidal jitter
(CPLL)(3)
6.6 Gb/s
0.44
–
–
UI
Sinusoidal jitter
(CPLL)(3)
5.0 Gb/s
0.44
–
–
UI
Sinusoidal jitter
(CPLL)(3)
4.25 Gb/s
0.44
–
–
UI
Sinusoidal jitter
(CPLL)(3)
3.75 Gb/s
Sinusoidal jitter
(CPLL)(3)
Sinusoidal jitter
(CPLL)(3)
Sinusoidal jitter
(CPLL)(3)
Sinusoidal jitter
(CPLL)(3)
1.25
Sinusoidal jitter
(CPLL)(3)
SJ Jitter Tolerance with Stressed
0.44
–
–
UI
3.2
Gb/s(4)
0.45
–
–
UI
3.2
Gb/s(5)
0.45
–
–
UI
2.5
Gb/s(6)
0.5
–
–
UI
0.5
–
–
UI
500 Mb/s
0.4
–
–
UI
3.2 Gb/s
0.70
–
–
UI
6.6 Gb/s
0.70
–
–
UI
3.2 Gb/s
0.1
–
–
UI
6.6 Gb/s
0.1
–
–
UI
Gb/s(7)
Eye(2)
JT_TJSE3.2
Total jitter with stressed eye(8)
JT_SJSE3.2
Sinusoidal jitter with stressed
eye(8)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Using RXOUT_DIV = 1, 2, and 4.
All jitter values are based on a bit error ratio of 1e–12.
The frequency of the injected sinusoidal jitter is 10 MHz.
CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
CPLL frequency at 1.6 GHz and RXOUT_DIV = 1.
CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
Composite jitter with RX and LPM or DFE mode.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
GTX Transceiver Protocol Jitter Characteristics
For Table 93 through Table 98, the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) contains recommended
settings for optimal usage of protocol specific characteristics.
Table 93: Gigabit Ethernet Protocol Characteristics
Description
Line Rate (Mb/s)
Min
Max
Units
1250
–
0.24
UI
1250
0.749
–
UI
Line Rate (Mb/s)
Min
Max
Units
3125
–
0.35
UI
3125
0.65
–
UI
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
Table 94: XAUI Protocol Characteristics
Description
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
Table 95: PCI Express Protocol Characteristics(1)
Standard
Description
Line Rate (Mb/s)
Min
Max
Units
PCI Express Transmitter Jitter Generation
PCI Express Gen 1
Total transmitter jitter
2500
–
0.25
UI
PCI Express Gen 2
Total transmitter jitter
5000
–
0.25
UI
–
31.25
ps
–
12
ps
0.65
–
UI
0.40
–
UI
0.30
–
UI
1.00
–
UI
Note 4
–
UI
0.10
–
UI
PCI Express Gen 3(2)
Total transmitter jitter uncorrelated
Deterministic transmitter jitter uncorrelated
8000
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1
PCI Express Gen 2(3)
Total receiver jitter tolerance
2500
Receiver inherent timing error
Receiver inherent deterministic timing error
5000
0.03 MHz–1.0 MHz
PCI Express Gen
3(2)
Receiver sinusoidal jitter
tolerance
1.0 MHz–10 MHz
8000
10 MHz–100 MHz
Notes:
1.
2.
3.
4.
Tested per card electromechanical (CEM) methodology.
PCI-SIG 3.0 certification and compliance test boards are currently not available.
Using common REFCLK.
Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20 dB/decade.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 96: CEI-6G and CEI-11G Protocol Characteristics
Description
Line Rate (Mb/s)
Interface
Min
Max
Units
CEI-6G-SR
–
0.3
UI
CEI-6G-LR
–
0.3
UI
CEI-6G-SR
0.6
–
UI
CEI-6G-LR
0.95
–
UI
CEI-11G-SR
–
0.3
UI
CEI-11G-LR/MR
–
0.3
UI
CEI-11G-SR
0.65
–
UI
CEI-11G-MR
0.65
–
UI
CEI-11G-LR
0.825
–
UI
CEI-6G Transmitter Jitter Generation
Total transmitter jitter(1)
4976–6375
CEI-6G Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance(1)
4976–6375
CEI-11G Transmitter Jitter Generation
Total transmitter jitter(2)
9950–11100
CEI-11G Receiver High Frequency Jitter Tolerance
Total receiver jitter
tolerance(2)
9950–11100
Notes:
1.
2.
Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.
Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock.
Table 97: SFP+ Protocol Characteristics
Description
Line Rate (Mb/s)
Min
Max
Units
–
0.28
UI
0.7
–
UI
SFP+ Transmitter Jitter Generation
9830.40(1)
9953.00
Total transmitter jitter
10312.50
10518.75
11100.00
SFP+ Receiver Frequency Jitter Tolerance
9830.40(1)
9953.00
Total receiver jitter tolerance
10312.50
10518.75
11100.00
Notes:
1.
Line rated used for CPRI over SFP+ applications.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 98: CPRI Protocol Characteristics
Description
Line Rate (Mb/s)
Min
Max
Units
614.4
–
0.35
UI
1228.8
–
0.35
UI
2457.6
–
0.35
UI
3072.0
–
0.35
UI
4915.2
–
0.3
UI
6144.0
–
0.3
UI
9830.4
–
Note 1
UI
614.4
0.65
–
UI
1228.8
0.65
–
UI
2457.6
0.65
–
UI
3072.0
0.65
–
UI
4915.2
0.95
–
UI
6144.0
0.95
–
UI
9830.4
Note 1
–
UI
CPRI Transmitter Jitter Generation
Total transmitter jitter
CPRI Receiver Frequency Jitter Tolerance
Total receiver jitter tolerance
Notes:
1.
Tested per SFP+ specification, see Table 97.
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm
Table 99: Maximum Performance for PCI Express Designs
Symbol
Speed Grade
Description
-3
-2
-1
Units
FPIPECLK
Pipe clock maximum frequency
250
250
250
MHz
FUSERCLK
User clock maximum frequency
500
500
250
MHz
FUSERCLK2
User clock 2 maximum frequency
250
250
250
MHz
FDRPCLK
DRP clock maximum frequency
250
250
250
MHz
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
XADC Specifications
Table 100: XADC Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
VCCADC = 1.8V ± 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, Tj = –40°C to 100°C, Typical values at Tj=+40°C
ADC Accuracy(1)
Resolution
12
–
–
Bits
–
–
±2
LSBs
No missing codes, guaranteed monotonic
–
–
±1
LSBs
Unipolar operation
–
–
±8
LSBs
Bipolar operation
–
–
±4
LSBs
Gain Error
–
–
±0.5
%
Offset Matching
–
–
4
LSBs
Gain Matching
–
–
0.3
%
0.1
–
1
MS/s
FSAMPLE = 500KS/s, FIN = 20KHz
60
–
–
dB
External 1.25V reference
–
–
2
LSBs
On-chip reference
–
3
–
LSBs
FSAMPLE = 500KS/s, FIN = 20KHz
70
–
–
dB
10
–
–
Bits
–
–
±1
No missing codes, guaranteed monotonic
–
–
±1
LSB
(at 10 bits)
Unipolar operation
0
–
1
V
–0.5
–
+0.5
V
Unipolar common mode range (FS input)
0
–
+0.5
V
Bipolar common mode range (FS input)
+0.5
–
+0.6
V
Adjacent analog channels set within these
ranges should not corrupt measurements on
adjacent channels
–0.1
–
VCCADC
V
250
–
–
KHz
Tj = –40°C to 100°C.
–
–
±4
°C
Tj = –55°C to +125°C
–
–
±6
°C
Measurement range of VCCAUX 1.8V ±5%
Tj = –40°C to +100°C
–
–
±1
%
Measurement range of VCCAUX 1.8V ±5%
Tj = –55°C to +125°C
–
–
±2
%
Integral
Nonlinearity(2)
Differential Nonlinearity
INL
DNL
Offset Error
Sample Rate
Signal to Noise
Ratio(2)
SNR
RMS Code Noise
Total Harmonic
Distortion(2)
THD
ADC Accuracy at Extended Temperatures (-55°C to 125°C)
Resolution
Integral
Nonlinearity(2)
Differential Nonlinearity
Analog
INL
DNL
Inputs(3)
ADC Input Ranges
Bipolar operation
Maximum External Channel Input Ranges
Auxiliary Channel Full
Resolution Bandwidth
FRBW
On-Chip Sensors
Temperature Sensor Error
Supply Sensor Error
Conversion Rate(4)
Conversion Time - Continuous
tCONV
Number of ADCCLK cycles
26
–
32
Cycles
Conversion Time - Event
tCONV
Number of CLK cycles
–
–
21
Cycles
DRP Clock Frequency
DCLK
DRP clock frequency
8
–
250
MHz
ADC Clock Frequency
ADCCLK
Derived from DCLK
1
–
26
MHz
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Table 100: XADC Specifications (Cont’d)
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
40
–
60
%
1.20
1.25
1.30
V
1.2375
1.25
1.2625
V
DCLK Duty Cycle
XADC Reference(5)
External Reference
VREFP
On-Chip Reference
Externally supplied reference voltage
Ground VREFP pin to AGND,
Tj = –40°C to 100°C
Notes:
1.
2.
3.
4.
5.
Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature
is enabled.
Only specified for the BitGen option XADCEnhancedLinearity = ON.
See the ADC chapter in the 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter
User Guide (UG480) for a detailed description.
See the Timing chapter in the 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital
Converter User Guide (UG480) for a detailed description.
Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by ±4% is permitted. On-chip reference variation is ±1%.
Configuration Switching Characteristics
Table 101: Configuration Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
50.00
50.00
50.00
ms, Max
3.00/2.00
3.00/2.00
3.00/2.00
ns, Min
Power-up Timing Characteristics
TPOR
Power-on reset
Boundary-Scan Port Timing Specifications
TTAPTCK/TTCKTAP
TMS and TDI setup/hold
TTCKTDO
TCK falling edge to TDO output
7.00
7.00
7.00
ns, Max
FTCK
TCK frequency
66.00
66.00
66.00
MHz, Max
100.00
100.00
100.00
MHz, Max
Internal Configuration Access Port
FICAPCK
Internal configuration access port (ICAPE2)
eFUSE Programming Conditions
Table 102 lists the programming conditions specifically for eFUSE. For more information, see the 7 Series FPGA
Configuration User Guide (UG470).
Table 102: eFUSE Programming Conditions(1)
Symbol
Description
Min
Typ
Max
Units
IFS
VCCAUX supply current
–
–
115
mA
tj
Temperature range
15
–
125
°C
Notes:
1.
The Zynq-7000 device must not be configured during eFUSE programming.
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Zynq-7000 AP SoC (XC7Z030, XC7Z045, and XC7Z100): DC and AC Switching Characteristics
Revision History
The following table shows the revision history for this document:
Date
Version
Description
08/23/2012
1.0
Initial Xilinx release.
08/31/2012
1.1
Updated Tj and added Note 3 to Table 2. Updated RIN_TERM in Table 3. Updated standards in Table 9.
Revised PS Performance Characteristics section introduction. Updated values in Table 18. Added
Note 3 to Table 32. Added notes to Table 34. Revised FMSPICLK in Table 39.
03/14/2013
1.2
Updated the AC Switching Characteristics based upon ISE 14.5 and Vivado 2013.1, both at v1.06 for
the -3, -2, and -1 speed specifications throughout the document. Updated Table 16 and Table 17 for
production release of the XC7Z045 in the -2 and -1 speed designations.
Added the XC7Z100 device throughout document.
Updated description in Introduction. Added Note 2 to Table 2. Updated VPIN in Table 1 and Table 2.
Clarified PS specifications for CPIN(2) and removed Note 3 on IRPD in Table 3. Updated Table 6.
Updated Table 9, including removal of LVTTL, notes 2 and 3, and adding SSTL135. Added Table 10.
Many enhancements and additions to the figures and tables in the PS Switching Characteristics
section including adding notes with test conditions where applicable. Replaced or updated Table 18
through Table 48. Removed AXI Interconnects section.
Updated Note 1 in Table 68. Updated Note 1 and Note 2 in Table 83. In Table 86, increased -1 speed
grade (FF package) FGTXMAX value from 6.6 Gb/s to 8.0 Gb/s.
Updated the rows on offset error and gain error and matching in Table 100. Added Internal
Configuration Access Port section to Table 101.
03/27/2013
1.3
In Table 7, changed ICCINTMIN value for the XC7Z030. Updated Table 16 and Table 17 for production
release of the XC7Z030 in the -2 and -1 speed designations. In Table 50, updated the table title,
LPDDR2 values, and removed Note 3. In Table 51, updated the table title and removed Note 4.
04/24/2013
1.4
Updated Table 16 and Table 17 for production release of the XC7Z030 and XC7Z045 in the -3 speed
designations. Removed the PS Power-on Reset section. Updated the PS—PL Power Sequencing
section. Clarified the load conditions in Table 32 by adding new data.
In Table 1, revised VIN (I/O input voltage) to match values in Table 4 and Table 5, and combined Note 4
with old Note 5 and then added new Note 6. Revised VIN description and added Note 8, and updated
Note 3 in Table 2. Updated first 3 rows in Table 4 and Table 5. Revised PCI33_3 voltage minimum in
Table 11 to match values in Table 1, Table 4, and Table 5. Added Note 1 to Table 14 and Table 15.
Added Note 2 to Table 19. Throughout the data sheet (Table 62, Table 63, and Table 78) removed the
obvious note “A Zero “0” Hold Time listing indicates no hold time or a negative hold time.” Updated and
clarified USRCLK data in Table 90.
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