User manual | UPD78052(A),78053(A),78054(A) Data Sheet

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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78052(A), 78053(A), 78054(A)
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
A stricter quality assurance program (called special grade in NEC’s grade classification) is applied to the
µPD78052(A), 78053(A), and 78054(A), compared to the µPD78052, 78053, and 78054, which are classified as
standard grade.
The µ PD78052(A), 78053(A), and 78054(A) belong to the µPD78054 Subseries products of the 78K/0 Series.
These microcontrollers include the rich peripheral hardware, such as 8-bit resolution A/D converter, 8-bit resolution
D/A converter, timer, serial interface, real-time output port, and interrupt functions.
Various development tools are also available.
Details of the function description, etc., are described in the following User’s Manuals. Be sure to read
the documents when designing.
µPD78054, 78054Y Subseries User's Manual : U11747E
78K/0 Series User’s Manual Instructions
: IEU-1372
FEATURES
• Large on-chip ROM and RAM
Item
Part
Number
•
•
•
•
•
•
•
•
Program Memory
(ROM)
Data Memory
Internal HighSpeed RAM
µPD78052(A)
16 Kbytes
512 bytes
µPD78053(A)
24 Kbytes
1024 bytes
µPD78054(A)
32 Kbytes
Buffer RAM
32 bytes
Package
• 80-pin plastic QFP (14 × 14 mm)
External memory expansion space: 64 Kbytes
Instruction execution time can be varied from high-speed (0.4 µs) to ultra-low-speed (122 µ s)
I/O ports: 69 (N-ch open-drain : 4)
8-bit resolution A/D converter : 8 channels
8-bit resolution D/A converter : 2 channels
Serial interface : 3 channels
Timer: 5 channels
Power supply voltage : VDD = 2.0 to 6.0 V
APPLICATIONS
Control devices of transport system, gas detector circuit-breakers, safety devices, etc.
The information in this document is subject to change without notice.
Document No. U12171EJ1V0DS00 (1st edition)
Date Published March 1997 N
Printed in Japan
©
1997
µPD78052(A), 78053(A), 78054(A)
ORDERING INFORMATION
Part Number
Package
µ PD78052GC(A)-×××-3B9
µ PD78053GC(A)-×××-3B9
µ PD78054GC(A)-×××-3B9
Remark
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
Quality Grade
Special
Special
Special
××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
DIFFERENCES BETWEEN µ PD78052(A), 78053(A), 78054(A) AND STANDARD PRODUCTS (µ PD78052,
78053, 78054)
Part Number
Item
Package
µPD78052(A), 78053(A), 78054(A)
• 80-pin plastic QFP (14 × 14 mm)
µPD78052, 78053, 78054
• 80-pin plastic QFP (14 × 14 mm)
• 80-pin plastic TQFP (fine pitch (12 × 12 mm))
Quality grade
2
Special
Standard
µPD78052(A), 78053(A), 78054(A)
78K/0 SERIES PRODUCT DEVELOPMENT
These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are
subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
µ PD78075BY
µPD78075B
100-pin
EMI noise reduction version of the µ PD78078
100-pin
µPD78078
µPD78078Y
A timer was added to the µPD78054, and external interface function was enhanced
100-pin
µPD78070A
µPD78070AY
ROM-less versions of the µ PD78078
100-pin
80-pin
80-pin
µPD780018Note
µPD780058
µPD78058F
µPD780018YNote
µPD780058YNote
µPD78058FY
Serial I/O of the µ PD78078 was enhanced, and only selected functions are provided
Serial I/O of the µ PD78054 was enhanced, EMI noise reduction version
EMI noise reduction version of the µPD78054
80-pin
µPD78054
µPD78054Y
UART and D/A converter were added to the µPD78014, and I/O was enhanced
64-pin
µPD780034
µPD780034Y
An A/D converter of the µ PD780024 was enhanced
64-pin
64-pin
µPD780024
µPD78014H
µPD780024Y
Serial I/O of the µ PD78018F was enhanced, EMI noise reduction version
64-pin
µPD78018F
µPD78018FY
Low-voltage (1.8 V) operation versions of the µ PD78014 with several ROM and RAM capacities are available
64-pin
64-pin
µPD78014
µPD780001
µPD78014Y
An A/D converter and 16-bit timer were added to the µPD78002
An A/D converter was added to the µPD78002
64-pin
µPD78002
µPD78002Y
Basic subseries for control
42/44-pin
µPD78083
EMI noise reduction version of the µ PD78018F
On-chip UART, capable of operating at a low voltage (1.8 V)
Inverter control
64-pin
µPD780964
An A/D converter of the µPD780924 was enhanced
64-pin
µPD780924
On-chip inverter control circuit and UART, EMI noise reduction version
FIPTM drive
78K/0
Series
100-pin
µPD780208
The I/O and FIP C/D of the µ PD78044F were enhanced, Display output total: 53
100-pin
µ PD780228
The I/O and FIP C/D of the µ PD78044H were enhanced, Display output total: 48
80-pin
µPD78044H
N-ch open-drain input/output was added to the µ PD78044F, Display output total: 34
80-pin
µPD78044F
Basic subseries for driving FIP, Display output total: 34
LCD drive
100-pin
µPD780308
100-pin
µPD78064B
100-pin
µPD78064
µPD780308Y
SIO of the µPD78064 was enhanced, and ROM and RAM were expanded
EMI noise reduction version of the µ PD78064
µPD78064Y
Subseries for driving LCDs, On-chip UART
IEBusTM supported
80-pin
µPD78098
The IEBus controller was added to the µPD78054
LV
64-pin
µPD78P0914
On-chip PWM output, LV digital code decoder, Hsync counter
Note Under planning
3
µPD78052(A), 78053(A), 78054(A)
The major functional differences among the subseries are shown below.
Function
Subseries Name
Control
Inverter
control
FIP
drive
LCD
drive
µPD78075B
µPD78078
µPD78070A
µPD780018
µPD780058
µPD78058F
µPD78054
µPD780034
µPD780024
µPD78014H
µPD78018F
µPD78014
µPD780001
µPD78002
µPD78083
µPD780964
µPD780924
µPD780208
µPD780228
µPD78044H
µPD78044F
µPD780308
µPD78064B
µPD78064
µPD78098
ROM
Capacity
8-bit
16-bit
32 K-40 K
48 K-60 K
–
48 K-60 K
24 K-60 K
48 K-60 K
16 K-60 K
8 K-32 K
4ch
1ch
8
8
8
8
4
8-bit 10-bit 8-bit
Watch WDT
1ch
1ch
A/D
8ch
–
8ch
–
1.8 V Available
8ch
–
61
2ch (time-division 3-wire:1ch) 88
3ch (time-division UART: 1ch) 68
3ch (UART: 1ch)
69
–
3ch (UART: 1ch,
51
time-division 3-wire: 1ch)
2ch
53
2.7 V
1.8
2.7
2.0
1.8
V
V
V
V
2.7 V
3ch
Note
32
48
32
16
48
32
16
32
2ch
3ch
2ch
1ch
–
1ch
1ch
–
1ch
1ch
2ch
1ch
1ch
1ch
8ch
–
–
2ch
1ch
1ch
1ch
8ch
–
2ch
6ch
–
–
1ch
8ch
–
–
10-bit timer: 1 channel
88
–
2ch
8 K-32 K
K
K
VDD External
MIN.
Value Expansion
3ch (UART: 1ch)
–
8ch
–
8ch
8ch
K
K
K
K
K
I/O
2ch
–
1ch
–
–
K-60
K-60
K-48
K-40
K-60
K
K-32
K-60
Serial Interface
A/D D/A
2ch
K-60 K
K-32 K
K
K-16 K
IEBus
supported
LV
µPD78P0914 32 K
Note
Timer
–
1ch
1ch
8ch
–
–
–
–
39
53
33
47
–
Available
1.8 V
–
2.7 V Available
74
72
68
2.7 V
4.5 V
2.7 V
–
2ch
3ch (time-division UART: 1ch) 57
2ch (UART: 1ch)
2.0 V
2.0 V
–
3ch (UART: 1ch)
69
2.7 V Available
2ch
54
4.5 V Available
1ch (UART: 1ch)
2ch (UART: 2ch)
2ch
1ch
µPD78052(A), 78053(A), 78054(A)
FUNCTION OVERVIEW
Part Number
µPD78052(A)
Item
Internal
memory
ROM
High-speed RAM
Buffer RAM
Memory space
General registers
Instruction cycle
When main system clock
selected
When subsystem clock
selected
µPD78053(A)
µPD78054(A)
16 Kbytes
24 Kbytes
32 Kbytes
512 bytes
1024 bytes
32 bytes
64 Kbytes
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
On-chip instruction execution time cycle modification function
0.4 µs/0.8 µ s/1.6 µs/3.2 µs/6.4 µ s/12.8 µs (at 5.0-MHz operation)
122 µ s (at 32.768-kHz operation)
Instruction set
•
•
•
•
I/O ports
Total
• CMOS input
• CMOS I/O
• N-ch open-drain I/O
A/D converter
D/A converter
Serial interface
8-bit resolution × 8 channels
8-bit resolution × 2 channels
• 3-wire serial I/O, SBI, or 2-wire serial I/O mode selectable: 1 channel
• 3-wire serial I/O mode (on-chip max. 32 bytes automatic transmit/receive
function): 1 channel
•
•
•
•
•
Timer
16-bit operation
Multiplication/division (8 bits × 8 bits,16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, boolean operation)
BCD adjustment, etc.
: 69
: 02
: 63
: 04
3-wire serial I/O or UART mode selectable: 1 channel
16-bit timer/event counter
: 1 channel
8-bit timer/event counter
: 2 channels
Watch timer
: 1 channel
Watchdog timer
: 1 channel
Timer output
3 (14-bit PWM output × 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,
5.0 MHz (at main system clock 5.0-MHz operation)
32.768 kHz (at subsystem clock 32.768-kHz operation)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 5.0-MHz operation)
Vectored
interrupt
Maskable
Internal : 13, external : 7
Non-maskable
Internal : 1
Software
1
source
Test input
Internal : 1, external : 1
Power supply voltage
VDD = 2.0 to 6.0 V
Operating ambient temperature
TA = –40 to +85 °C
Package
• 80-pin plastic QFP (14 × 14 mm)
5
µPD78052(A), 78053(A), 78054(A)
CONTENTS
1.
PIN CONFIGURATION (Top View) .................................................................................................................
7
2.
BLOCK DIAGRAM ..........................................................................................................................................
9
3
PIN FUNCTIONS .............................................................................................................................................
3.1 Port Pins .................................................................................................................................................
3.2 Non-port Pins ........................................................................................................................................
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................................
10
10
12
14
4.
MEMORY SPACE ............................................................................................................................................. 18
5.
PERIPHERAL HARDWARE FUNCTION FEATURES ...................................................................................
5.1 Ports ........................................................................................................................................................
5.2 Clock Generator ....................................................................................................................................
5.3 Timer/Event Counter .............................................................................................................................
5.4 Clock Output Control Circuit...............................................................................................................
5.5 Buzzer Output Control Circuit ............................................................................................................
5.6 A/D Converter ........................................................................................................................................
5.7 D/A Converter ........................................................................................................................................
5.8 Serial Interfaces ....................................................................................................................................
5.9 Real-Time Output Port ..........................................................................................................................
6.
INTERRUPT FUNCTIONS AND TEST FUNCTIONS ..................................................................................... 28
6.1 Interrupt Functions ............................................................................................................................... 28
6.2 Test Functions ....................................................................................................................................... 32
7.
EXTERNAL DEVICE EXPANSION FUNCTIONS ........................................................................................... 33
8.
STANDBY FUNCTION ..................................................................................................................................... 33
9.
RESET FUNCTION ........................................................................................................................................... 33
19
19
20
20
23
23
24
25
25
27
10. INSTRUCTION SET .......................................................................................................................................... 34
11. ELECTRICAL SPECIFICATIONS .................................................................................................................... 37
12. CHARACTERISTIC CURVES (FOR REFERENCE ONLY)............................................................................ 65
13. PACKAGE DRAWING ...................................................................................................................................... 67
14. RECOMMENDED SOLDERING CONDITIONS .............................................................................................. 68
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................................. 69
APPENDIX B.
6
RELATED DOCUMENTS ............................................................................................................ 71
µPD78052(A), 78053(A), 78054(A)
1. PIN CONFIGURATION (Top View)
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
VDD
X2
X1
IC
XT2
AVDD
XT1/P07
AVREF0
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
• 80-pin plastic QFP (14 × 14 mm)
µ PD78052GC(A)-×××-3B9
µ PD78053GC(A)-×××-3B9
µ PD78054GC(A)-×××-3B9
P15/ANI5
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
P16/ANI6
2
59
P127/RTP7
P17/ANI7
3
58
P126/RTP6
AVSS
4
57
P125/RTP5
P130/ANO0
5
56
P124/RTP4
P131/ANO1
6
55
P123/RTP3
RESET
AVREF1
7
54
P122/RTP2
P70/SI2/RxD
8
53
P121/RTP1
P71/SO2/TxD
9
52
P120/RTP0
P72/SCK2/ASCK
10
51
P37
P20/SI1
11
50
P36/BUZ
P21/SO1
12
49
P35/PCL
P22/SCK1
13
48
P34/TI2
P23/STB
14
47
P33/TI1
P24/BUSY
15
46
P32/TO2
P65/WR
P64/RD
P63
P62
P61
P60
P57/A15
P56/A14
VSS
P55/A13
P54/A12
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P53/A11
P66/WAIT
P41/AD1
P52/A10
P67/ASTB
42
P50/A8
43
19
P51/A9
18
P40/AD0
P47/AD7
P27/SCK0
P46/AD6
P30/TO0
P45/AD5
P31/TO1
44
P44/AD4
45
17
P43/AD3
16
P42/AD2
P25/SI0/SB0
P26/SO0/SB1
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS .
2. Connect the AV DD pin to VDD.
3. Connect the AV SS pin to VSS.
m
7
µPD78052(A), 78053(A), 78054(A)
A8-A15
AD0-AD7
ANI0-ANI7
ANO0, ANO1
ASCK
ASTB
AVDD
AVREF0 , AVREF1
AVSS
BUSY
BUZ
IC
INTP0-INTP6
P00-P07
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P72
P120-P127
P130, P131
8
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Address Bus
Address/Data Bus
Analog Input
Analog Output
Asynchronous Serial Clock
Address Strobe
Analog Power Supply
Analog Reference Voltage
Analog Ground
Busy
Buzzer Clock
Internally Connected
Interrupt from Peripherals
Port0
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Port12
Port13
PCL
RD
RESET
RTP0-RTP7
RxD
SB0, SB1
SCK0-SCK2
SI0-SI2
SO0-SO2
STB
TI00, TI01
TI1, TI2
TO0-TO2
TxD
V DD
V SS
WAIT
WR
X1, X2
XT1, XT2
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Programmable Clock
Read Strobe
Reset
Real-Time Output Port
Receive Data
Serial Bus
Serial Clock
Serial Input
Serial Output
Strobe
Timer Input
Timer Input
Timer Output
Transmit Data
Power Supply
Ground
Wait
Write Strobe
Crystal (Main System Clock)
Crystal (Subsystem Clock)
µPD78052(A), 78053(A), 78054(A)
2. BLOCK DIAGRAM
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
16-bit TIMER/
EVENT COUNTER
TO1/P31
TI1/P33
8-bit TIMER/
EVENT COUNTER 1
TO2/P32
TI2/P34
8-bit TIMER/
EVENT COUNTER 2
WATCHDOG TIMER
WATCH TIMER
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SERIAL
INTERFACE 0
78K/0
CPU CORE
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
SERIAL
INTERFACE 1
SI2/RxD/P70
SO2/TxD/P71
SCK2/ASCK/P72
SERIAL
INTERFACE 2
ROM
RAM
ANI0/P10ANI7/P17
AVDD
AVSS
AVREF0
A/D CONVERTER
ANO0/P130,
ANO1/P131
AVSS
AVREF1
D/A CONVERTER
INTP0/P00INTP6/P06
INTERRUPT
CONTROL
BUZ/P36
PCL/P35
PORT0
P00
P01-P06
P07
PORT1
P10-P17
PORT2
P20-P27
PORT3
P30-P37
PORT4
P40-P47
PORT5
P50-P57
PORT6
P60-P67
PORT7
P70-P72
PORT12
P120-P127
PORT13
P130, P131
REAL-TIME
OUTPUT PORT
RTP0/P120RTP7/P127
EXTERNAL
ACCESS
AD0/P40AD7/P47
A8/P50A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
SYSTEM
CONTROL
RESET
X1
X2
XT1/P07
XT2
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
VDD VSS IC
Remark The internal ROM and RAM capacity depends on the product.
9
µPD78052(A), 78053(A), 78054(A)
3. PIN FUNCTIONS
3.1
Port Pins (1/2)
Pin Name
P00
Input
P01
Input/
output
P02
Function
I/O
Port 0
8-bit I/O port
After
Reset
DualFunction Pin
Input only
Input
INTP0/TI00
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up
resistor can be used by software.
Input
INTP1/TI01
INTP2
P03
INTP3
P04
INTP4
P05
INTP5
P06
INTP6
P07
Note 1
Input
Input only
Input
XT1
P10 to P17
Input/
output
Port 1
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used
by software.Note 2
Input
ANI0 to ANI7
P20
Input/
output
Port 2
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used
by software.
Input
SI1
P21
P22
P23
SO1
SCK1
STB
P24
BUSY
P25
SI0/SB0
P26
SO0/SB1
P27
SCK0
P30
P31
Input/
output
P32
P33
Port 3
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used
by software.
Input
TO0
TO1
TO2
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
P40 to P47
Input/
output
Port 4
8-bit input/output port.
Input/output can be specified in 8-bit unit.
When used as an input port, on-chip pull-up resistor can be used
by software. Test input flag (KRIF) is set to 1 by falling edge detection.
Input
AD0 to AD7
Notes 1. When using the P07/XT1 pin as an input port, set 1 in the bit 6 (FRC) of the processor clock control register
(PCC). On-chip feedback resistor of the subsystem clock oscillator should not be used.
2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input pins, use of the pull-up resistor
is cancelled automatically.
10
µPD78052(A), 78053(A), 78054(A)
3.1
Port Pins (2/2)
Pin Name
I/O
Function
After
Reset
DualFunction Pin
P50 to P57
Input/
output
Port 5
8-bit input/output port.
LED can be driven directly.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used
by software.
Input
A8 to A15
P60
Input/
output
Port 6
8-bit input/outport port.
Input/output can be specified bit-wise.
Input
—
Input
RD
P61
P62
P63
P64
N-ch open-drain input/output
port. On-chip pull-up resistor
can be specified by mask
option. LED can be driven
directly.
When used as an input port,
on-chip pull-up resistor can be
used by software.
P65
P66
WR
WAIT
P67
P70
P71
ASTB
Input/
output
P72
Input
Input/
output
SI2/RxD
SO2/TxD
SCK2/ASCK
When used as an input port, on-chip pull-up resistor can be used by software.
P120 to P127 Input/
output
P130, P131
Port 7
3-bit input/output port.
Input/output can be specified bit-wise.
Port 12
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used
by software.
Input
RTP0 to RTP7
Port 13
2-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used
by software.
Input
ANO0, ANO1
11
µPD78052(A), 78053(A), 78054(A)
3.2
Non-port Pins (1/2)
Pin Name
INTP0
I/O
Input
INTP1
Function
External interrupt input by which the effective edge (rising edge, falling
edge, or both rising edge and falling edge) can be specified.
After
Reset
DualFunction Pin
Input
P00/TI00
P01/TI01
INTP2
P02
INTP3
P03
INTP4
P04
INTP5
P05
INTP6
P06
SI0
Input
Serial interface serial data input.
Input
P25/SB0
SI1
P20
SI2
P70/RxD
SO0
Output
Serial interface serial data output.
Input
P26/SB1
SO1
P21
SO2
P71/TxD
SB0
SB1
SCK0
SCK1
Input/
output
Serial interface serial data input/output.
Input/
output
Serial interface serial clock input/output.
Input
P25/SI0
P26/SO0
Input
P27
P22
P72/ASCK
SCK2
Output
Serial interface automatic transmit/receive strobe output.
Input
P23
BUSY
Input
Serial interface automatic transmit/receive busy input.
Input
P24
RxD
Input
Asynchronous serial interface serial data input.
Input
P70/SI2
TxD
Output
Asynchronous serial interface serial data output.
Input
P71/SO2
ASCK
Input
Asynchronous serial interface serial clock input.
Input
P72/SCK2
TI00
Input
External count clock input to 16-bit timer (TM0).
Input
P00/INTP0
STB
TI01
Capture trigger signal input to capture register (CR00).
TI1
External count clock input to 8-bit timer (TM1).
P33
TI2
External count clock input to 8-bit timer (TM2).
P34
TO0
Output
16-bit timer (TM0) output (dual-function as 14-bit PWM output).
P01/INTP1
Input
P30
TO1
8-bit timer (TM1) output.
P31
TO2
8-bit timer (TM2) output.
P32
PCL
Output
Clock output (for main system clock, subsystem clock trimming).
Input
P35
BUZ
Output
Buzzer output.
Input
P36
Real-time output port by which data is output in synchronization with a
Input
P120 to P127
RTP0 to RTP7 Output
trigger.
AD0 to AD7
Input/
output
Low-order address/data bus at external memory expansion.
Input
P40 to P47
A8 to A15
Output
High-order address bus at external memory expansion.
Input
P50 to P57
RD
Output
External memory read operation strobe signal output.
Input
P64
WR
12
External memory write operation strobe signal output.
P65
µPD78052(A), 78053(A), 78054(A)
3.2
Non-port Pins (2/2)
Pin Name
I/O
WAIT
Input
ASTB
Output
After
Reset
DualFunction Pin
Wait insertion at external memory access.
Input
P66
Strobe output which latches the address information output at port 4
Input
P67
A/D converter analog input.
Input
P10 to P17
D/A converter analog output.
Input
P130, P131
Function
and port 5 to access external memory.
ANI0 to ANI7
Input
ANO0, ANO1
Output
AVREF0
Input
A/D converter reference voltage input.
—
—
AVREF1
Input
D/A converter reference voltage input.
—
—
AVDD
—
A/D converter analog power supply. Connect to VDD.
—
—
AVSS
—
A/D and D/A converter ground potential. Connect to VSS .
—
—
RESET
Input
System reset input.
—
—
X1
Input
Main system clock oscillation crystal connection.
—
—
X2
—
—
—
XT1
Input
Input
P07
XT2
—
—
—
VDD
—
Positive power supply.
—
—
VSS
—
Ground potential.
—
—
IC
—
Internal connection. Connect to VSS directly.
—
—
Subsystem clock oscillation crystal connection.
13
µPD78052(A), 78053(A), 78054(A)
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Figure 3-1.
Table 3-1. Input/Output Circuit Type of Each Pin (1/2)
Pin Name
Input/output
Circuit Type
I/O
P00/INTP0/TI00
2
Input
P01/INTP1/TI01
8-A
Input/output
P07/XT1
16
Input
P10/ANI0 to P17/ANI7
11
Input/output
P20/SI1
8-A
P21/SO1
5-A
P22/SCK1
8-A
P23/STB
5-A
P24/BUSY
8-A
Recommended Connection when not Used
Connect to VSS.
Connect to VSS via a resistor individually.
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
P25/SI0/SB0
Connect to VDD.
Connect to VDD or VSS via a resistor individually.
10-A
P26/SO0/SB1
P27/SCK0
P30/TO0
5-A
P31/TO1
P32/TO2
P33/TI1
8-A
P34/TI2
P35/PCL
5-A
P36/BUZ
P37
P40/AD0 to P47/AD7
5-E
Connect to VDD via a resistor individually.
P50/A8 to P57/A15
5-A
Connect to VDD or VSS via a resistor individually.
P60 to P63
P64/RD
P65/WR
P66/WAIT
P67/ASTB
14
13-B
5-A
Connect to VDD via a resistor individually.
Connect to VDD or VSS via a resistor individually.
µPD78052(A), 78053(A), 78054(A)
Table 3-1. Input/Output Circuit Type of Each Pin (2/2)
Pin Name
P70/SI2/RxD
Input/output
Circuit Type
I/O
8-A
Input/
P71/SO2/TxD
5-A
output
P72/SCK2/ASCK
8-A
P120/RTP0 to
5-A
Recommended Connection when not Used
Connect to VDD or VSS via a resistor individually.
P127/RTP7
P130/ANO0,
12-A
Connect to VSS via a resistor individually.
P131/ANO1
RESET
2
Input
XT2
16
—
AVREF0
—
AVREF1
—
Leave open.
Connect to VSS .
Connect to VDD.
AVDD
AVSS
Connect to VSS .
IC
Connect to VSS directly.
15
µPD78052(A), 78053(A), 78054(A)
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 2
Type 8-A
VDD
pullup
enable
P-ch
IN
VDD
data
P-ch
IN/OUT
Schmitt-Triggered Input with Hysteresis Characteristic
VDD
Type 5-A
pullup
enable
output
disable
N-ch
VDD
Type 10-A
pullup
enable
P-ch
P-ch
VDD
VDD
data
data
P-ch
P-ch
IN/OUT
output
disable
IN/OUT
open drain
output disable
N-ch
N-ch
input
enable
Type 5-E
pullup
enable
pullup
enable
P-ch
P-ch
IN/OUT
P-ch
IN/OUT
output
disable
P-ch
VDD
data
VDD
data
VDD
Type 11
V DD
N-ch
output
disable
Comparator
N-ch
P-ch
+
-
N-ch
VREF (Threshold Voltage)
input
enable
16
µPD78052(A), 78053(A), 78054(A)
Figure 3-1. Pin Input/Output Circuits (2/2)
VDD
Type 12-A
pullup
enable
Type 16
feedback
P-ch
cut-off
VDD
data
P-ch
P-ch
IN/OUT
output
disable
input
enable
N-ch
P-ch
XT1
Analog Output
Voltage
XT2
N-ch
Type 13-B
V DD
Mask
Option
IN/OUT
data
output disable
N-ch
V DD
RD
P-ch
Middle-High Voltage Input Buffer
17
µPD78052(A), 78053(A), 78054(A)
4. MEMORY SPACE
Figure 4-1 shows the µ PD78052(A), 78053(A), 78054(A) memory map.
Figure 4-1. Memory Map
FFFFH
Special Function Registers
(SFR) 256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
General Registers
32 × 8 bits
Internal High-Speed
RAM Note
mmmmH
mmmmH – 1
Use Prohibited
Data Memory
Space
FAE0H
FADFH
nnnnH
Buffer RAM
32 × 8 bits
FAC0H
FABFH
Program Area
1000H
0FFFH
Use Prohibited
CALLF Entry Area
FA80H
FA7FH
0800H
07FFH
Program Area
External Memory
0080H
007FH
Program Memory
Space
nnnnH + 1
nnnnH
CALLT Table Area
Internal ROM
0040H
003FH
Note
Vector Table Area
0000H
0000H
Note The internal ROM capacity and internal high-speed RAM capacity depend on the products (see the following
table).
18
Relevant Product Name
Internal ROM Last Address
nnnnH
Internal High-Speed RAM Start Address
mmmmH
µPD78052(A)
3FFFH
FD00H
µPD78053(A)
5FFFH
FB00H
µPD78054(A)
7FFFH
µPD78052(A), 78053(A), 78054(A)
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports
The following 3 types of I/O ports are available.
• CMOS input (P00, P07)
• CMOS input/output (P01 to P06, port 1 to port 5, P64 to P67, port 7, port 12, port 13)
• N-channel open-drain input/output (P60 to P63)
Total
: 2
: 63
: 4
: 69
Table 5-1. Port Functions
Name
Port 0
Pin Name
Function
P00, P07
Dedicated input port pins
P01 to P06
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Port 1
P10 to P17
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Port 2
P20 to P27
Port 3
P30 to P37
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Port 4
P40 to P47
Input/output port pins. Input/output specifiable in 8-bit units.
When used as input port pins, on-chip pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Port 5
P50 to P57
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
LED direct drive capability.
Port 6
P60 to P63
N-channel open-drain input/output port pins. Input/output specifiable bit-wise.
On-chip pull-up resistor can be used by mask option.
LED direct drive capability.
P64 to P67
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Port 7
P70 to P72
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Port 12
P120 to P127
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Port 13
P130, P131
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
19
µPD78052(A), 78053(A), 78054(A)
5.2 Clock Generator
Two types of generators, a main system clock generator and a subsystem clock generator, are available.
The instruction execution time can also be changed.
• 0.4 µ s/0.8 µs/1.6 µ s/3.2 µ s/6.4 µs/12.8 µs (main system clock: at 5.0-MHz operation)
• 122 µ s (subsystem clock: at 32.768-kHz operation)
Figure 5-1. Clock Generator Block Diagram
XT1/P07
Subsystem
Clock
Oscillator
XT2
fXT
Watch Timer, Clock
Output Function
Prescaler
1
X1
X2
Main System fX
Clock
Oscillator
Selector
fXX fXX fXX
2 22 23
fX
2
STOP
Clock to Peripheral
Hardware
Prescaler
fXX
Divider
2
fXX fXT
24 2
Selector
Standby
Control
Circuit
Wait Control
Circuit
CPU Clock
(fCPU)
To INTP0
Sampling Clock
5.3 Timer/Event Counter
The µ PD78052(A), 78053(A), and 78054(A) incorporate 5 channels of the timer/event counter.
• 16-bit timer/event counter
: 1 channel
• 8-bit timer/event counter
: 2 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
Table 5-2. Types and Functions of Timer/Event Counter
16-Bit Timer/Event Counter 8-Bit Timer/Event Counter Watch Timer
Watchdog Timer
Type
Interval timer
1 channel
2 channels
External event counter
1 channel
2 channels
Timer output
1 output
2 outputs
PWM output
1 output
Pulse width measurement
2 inputs
Square wave output
1 output
One-shot pulse output
1 output
1 channel
1 channel
1
1
Function
Interrupt source
Test input
20
2
2 outputs
2
1 input
µPD78052(A), 78053(A), 78054(A)
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal Bus
INTP1
TI01/P01/INTP1
16-Bit Capture/
Compare Register
(CR00)
Selector
INTTM00
PWM Pulse
Output
Control
Circuit
Match
Watch Timer
Output
Output Control
Circuit
TO0/P30
2fXX
fXX
Selector
fXX/2
16-Bit Timer Register
(TM0)
fXX/2 2
TI00/P00/INTP0
Clear
Edge
Detector
Selector
Match
INTTM01
INTP0
16-Bit Capture/
Compare Register
(CR01)
Internal Bus
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal Bus
INTTM1
8-Bit Compare
Register (CR10)
8-Bit Compare
Register (CR20)
Selector
Match
Match
Output
Control
Circuit
INTTM2
fXX/2-fXX/29
fXX/211
Selector
8-Bit Timer
Register 1 (TM1)
Selector
TI1/P33
Clear
8-Bit Timer
Register 2 (TM2)
Clear
fXX/2-fXX/2 9
fXX/211
TO2/P32
Selector
Selector
TI2/P34
Output
Control
Circuit
TO1/P31
Internal Bus
21
µPD78052(A), 78053(A), 78054(A)
Figure 5-4. Watch Timer Block Diagram
fW
2 14
Selector
fXX/2 7
Selector
fW
5-Bit Counter
Selector
Prescaler
INTWT
fXT
fW
213
fW
24
fW
25
fW
26
fW
27
fW
28
fW
29
INTTM3
Selector
To 16-Bit Timer/
Event Counter
Figure 5-5. Watchdog Timer Block Diagram
fXX
23
Prescaler
fXX
24
f XX
25
fXX
26
fXX
27
fXX
28
fXX
29
fXX
211
INTWDT
Maskable
Interrupt Request
Selector
8-Bit Counter
Control
Circuit
RESET
INTWDT
Non-Maskable
Interrupt Request
22
µPD78052(A), 78053(A), 78054(A)
5.4 Clock Output Control Circuit
The clock with the following frequency can be output as a clock output.
• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (main system clock: at 5.0MHz operation)
• 32.768 kHz (subsystem clock: at 32.768-kHz operation)
Figure 5-6. Clock Output Control Circuit Block Diagram
f XX
fXX/2
fXX /2 2
f XX /2 3
Synchronization
Circuit
Selector
fXX /2 4
Output Control
Circuit
PCL/P35
f XX /2 5
fXX /2 6
fXX /2 7
f XT
5.5 Buzzer Output Control Circuit
The clock with the following frequency can be output as a buzzer output.
• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (main system clock: at 5.0-MHz operation)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
f XX /2 9
fXX /2 10
Selector
Output Control
Circuit
BUZ/P36
fXX /2 11
23
µPD78052(A), 78053(A), 78054(A)
5.6 A/D Converter
An A/D converter of 8-bit resolution × 8 channels is incorporated.
The following two types of the A/D conversion operation start-up methods are available.
• Hardware start
• Software start
Figure 5-8. A/D Converter Block Diagram
Series Resistor String
AVDD
Sample & Hold Circuit
ANI0/P10
AVREF0
ANI1/P11
Voltage Comparator
ANI2/P12
Tap
Selector
ANI3/P13
ANI4/P14
Selector
ANI5/P15
ANI6/P16
Succesive Approximation
Register (SAR)
ANI7/P17
INTP3/P03
Edge
Detection
Circuit
Control
Circuit
AVSS
INTAD
INTP3
A/D Conversion
Result Register (ADCR)
Internal Bus
24
µPD78052(A), 78053(A), 78054(A)
5.7 D/A Converter
A D/A converter of 8-bit resolution × 2 channels is incorporated.
Conversion method is R-2R resistor ladder method.
Figure 5-9. D/A Converter Block Diagram
AVREF1
ANOn
Selector
DACSn
Write
AVSS
INTTMX
D/A Conversion Value Set Register n
(DACSn)
DAMm
D/A Converter
Mode Register
Internal Bus
n = 0, 1
m = 4, 5
x = 1, 2
5.8 Serial Interfaces
3 channels of the clocked serial interface are incorporated.
• Serial interface channel 0
• Serial interface channel 1
• Serial interface channel 2
Table 5-3. Types and Functions of Serial Interface
Function
3-wire serial I/O mode
Serial Interface Channel 0
Serial Interface Channel 1
√ (MSB/LSB first switchable)
√ (MSB/LSB first switchable)
√ (MSB/LSB first switchable)
√ (MSB/LSB first switchable)
—
3-wire serial I/O mode with
—
Serial Interface Channel 2
automatic transmit/
receive function
SBI (serial bus interface) mode
√ (MSB first)
—
2-wire serial I/O mode
√ (MSB first)
—
Asynchronous serial interface
(UART) mode
—
—
—
—
√ (Dedicated baud rate
generator incorporated)
25
µPD78052(A), 78053(A), 78054(A)
Figure 5-10. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25
Selector
Serial I/O Shift
Register 0 (SIO0)
Output
Latch
SO0/SB1/P26
Selector
Bus Release/Command/
Acknowledge Detection
Circuit
Serial Clock Counter
SCK0/P27
Busy/Acknowledge
Output Circuit
Interrupt
Request
Signal
Generator
INTCSI0
fXX/2-fXX/28
Serial Clock
Control Circuit
Selector
TO2
Figure 5-11. Serial Interface Channel 1 Block Diagram
Internal Bus
Automatic Data Transmit/
Receive Address Pointer
(ADTP)
Buffer RAM
Automatic Data
Transmit/Receive
Interval Specification
Register (ADTI)
Match
SI1/P20
Serial I/O Shift Register 1 (SIO1)
SO1/P21
5-Bit Counter
STB/P23
BUSY/P24
SCK1/P22
Handshake
Control
Circuit
Serial Counter
Interrupt Request
Signal Generator
INTCSI1
8
fXX/2-fXX/2
Serial Clock Control Circuit
26
Selector
TO2
µPD78052(A), 78053(A), 78054(A)
Figure 5-12. Serial Interface Channel 2 Block Diagram
Internal Bus
RxD/SI2/P70
Receive Buffer Register
(RXB/SIO2)
Direction Control Circuit
Direction Control Circuit
Transmit Shift Register
(TXS/SIO2)
Receive Shift Register
(RXS)
Transmit Control Circuit
INTST
TxD/SO2/P71
INTSER
Receive Control Circuit
INTSR/INTCSI2
SCK Output
Control Circuit
ASCK/SCK2/P72
Baud Rate
Generator
fXX-fXX/210
5.9
Real-Time Output Port
Data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently
with timer interrupt or external interrupt generation in order to output to off-chip. This is real-time output function. And
pins to output to off-chip are called real-time output ports.
By using a real-time output port, a signal which has no jitter can be output. This is most applicable to control of
stepping motor, etc.
Figure 5-13. Real-Time Output Port Block Diagram
Internal Bus
INTP2
INTTM1
INTTM2
Output Trigger
Control Circuit
Real-Time Output Real-Time Output
Buffer Register
Buffer Register
Higher 4 Bits
Lower 4 Bits
(RTBH)
(RTBL)
Real-Time Output Port Mode
Register (RTPM)
Output Latch
P127
P120
27
µPD78052(A), 78053(A), 78054(A)
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 Interrupt Functions
There are 22 interrupt functions of three different kinds, as shown below.
• Non-maskable : 1
• Maskable : 20
• Software : 1
Table 6-1. Interrupt Source List (1/2)
Note 1
Kind of Interrupt
Non-maskable
Maskable
Default
Priority
Interrupt Source
Name
Trigger
–––
INTWDT
Watchdog timer overflow
(watchdog timer mode 1 selected)
0
INTWDT
Watchdog timer overflow
(interval timer mode selected)
1
INTP0
2
Internal
Vector Table
Address
0004H
Basic
Configuration
Type Note 2
(A)
(B)
0006H
(C)
INTP1
0008H
(D)
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTP6
0012H
8
INTCSI0
End of serial interface channel 0 transfer Internal
0014H
9
INTCSI1
End of serial interface channel 1 transfer
0016H
10
INTSER
0018H
11
INTSR
Generation of serial interface channel
2 UART receive error
End of serial interface channel 2 UART
reception
12
Pin input edge detection
Internal/
External
INTCSI2
End of serial interface channel 2 3-wire
transfer
INTST
End of serial interface channel 2 UART
transmission
External
(B)
001AH
001CH
Notes 1. The default priority is a priority order when two or more maskable interrupts are generated simultaneously.
0 is the highest order and 18, the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
28
µPD78052(A), 78053(A), 78054(A)
Table 6-1. Interrupt Source List (2/2)
Note 1
Kind of Interrupt
Maskable
Software
Default
Priority
Interrupt Source
Name
Trigger
Internal/ Vector Table
External Address
13
INTTM3
Reference time interval signal from watch
timer
14
INTTM00
Generation of match signal of 16-bit
timer register and capture/compare
register (CR00)
0020H
15
INTTM01
Generation of match signal of 16-bit
timer register and capture/compare
register (CR01)
0022H
16
INTTM1
Generation of match signal of 8-bit
timer/event counter 1
0024H
17
INTTM2
Generation of match signal of 8-bit timer/
event counter 2
0026H
18
INTAD
End of conversion by A/D converter
0028H
—
BRK
BRK instruction execution
Internal
—
001EH
003EH
Basic
Configuration
Type Note 2
(B)
(E)
Notes 1. The default priority is a priority order when two or more maskable interrupts are generated simultaneously.
0 is the highest order and 18, the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
29
µPD78052(A), 78053(A), 78054(A)
Figure 6-1. Interrupt Function Basic Configuration (1/2)
(A) Internal non-maskable interrupt
Internal Bus
Interrupt
Request
Vector Table
Address
Generator
Priority Control
Circuit
Standby Release
Signal
(B) Internal maskable interrupt
Internal Bus
MK
Interrupt
Request
PR
IE
ISP
Priority Control
Circuit
IF
Vector Table
Address
Generator
Standby Release
Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Sampling Clock
Select Register
(SCS)
Interrupt
Request
Sampling
Clock
External Interrupt
Mode Register
(INTM0)
Edge
Detection
Circuit
MK
IF
IE
PR
Priority Control
Circuit
ISP
Vector Table
Address
Generator
Standby Release
Signal
30
µPD78052(A), 78053(A), 78054(A)
Figure 6-1. Interrupt Function Basic Configuration (2/2)
(D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt
Mode Register
(INTM0, INTM1)
Interrupt
Request
Edge Detection
Circuit
MK
IE
PR
Priority Control
Circuit
IF
ISP
Vector Table
Address
Generator
Standby Release
Signal
(E) Software interrupt
Internal Bus
Interrupt
Request
IF
IE
ISP
MK
PR
:
:
:
:
:
Priority Control
Circuit
Vector Table
Address
Generator
Interrupt request flag
Interrupt enable flag
In-service priority flag
Interrupt mask flag
Priority specification flag
31
µPD78052(A), 78053(A), 78054(A)
6.2 Test Functions
There are two test functions as shown in Table 6-2.
Table 6-2. Test Input Source List
Test Input Source
Internal/External
Trigger
Name
INTWT
Watch timer overflow
Internal
INTPT4
Port 4 falling edge detection
External
Figure 6-2. Test Function Basic Configuration
Internal Bus
MK
Test Input
IF : Test input flag
MK : Test mask flag
32
IF
Standby Release
Signal
µPD78052(A), 78053(A), 78054(A)
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion functions connect external devices to areas other than the internal ROM, RAM and
SFR. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
There are the following two standby functions to reduce the consumption current.
• HALT mode
• STOP mode
: The CPU operating clock is stopped.
The average consumption current can be reduced by intermittent operation in combination with
the normal operating mode.
: The main system clock oscillation is stopped. The whole operation by the main system clock
is stopped, so that the system operates with ultra-low power consumption using only the
subsystem clock.
Figure 8-1. Standby Function
CSS = 1
Main System
Clock Operation
Interrupt
Request
STOP Mode
(Main system clock
oscillation stopped)
Note
CSS = 0
HALT
Instruction
STOP
Instruction
Interrupt
Request
HALT Mode
(Clock supply to CPU
is stopped, oscillation
maintained)
Subsystem Clock
Operation Note
Interrupt
Request
HALT
Instruction
HALT Mode Note
(Clock supply to CPU
is stopped, oscillation
maintained)
The consumption current can be reduced by stopping the main system clock. When the CPU is operating
on the subsystem clock, set bit 7 (MCC) in the processor clock control register (PCC) to stop the main system
clock. The STOP instruction cannot be used.
Caution
When the main system clock is stopped and the system is operated by the subsystem clock, the
subsystem clock should be switched again to the main system clock after the oscillation
stabilization time is secured by the program.
Remark
CSS : bit 4 in the PCC
9. RESET FUNCTION
There are the following two reset methods.
• External reset by RESET pin
• Internal reset by watchdog timer runaway time detection
33
µPD78052(A), 78053(A), 78054(A)
10. INSTRUCTION SET
(1) 8-bit instruction
MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second
operand
First
operand
A
r
[HL + byte]
#byte
A
r
Note
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B]
$addr16
1
None
[HL + C]
ADD
MOV
MOV
MOV
MOV
ADDC
XCH
XCH
XCH
XCH
MOV
MOV
MOV
MOV
ROR
XCH
XCH
XCH
ROL
SUB
ADD
ADD
ADD
SUBC
ADDC
ADDC
ADDC
ADD
ADD
RORC
ADDC
ADDC
AND
SUB
SUB
SUB
SUB
SUB
ROLC
OR
SUBC
SUBC
SUBC
SUBC
SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
INC
DEC
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
DBNZ
B, C
sfr
MOV
MOV
saddr
MOV
MOV
ADD
DBNZ
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
[HL]
MOV
ROR4
ROL4
[HL + byte]
MOV
[HL + B]
[HL + C]
X
MULU
C
DIVUW
Note Except r = A
34
µPD78052(A), 78053(A), 78054(A)
(2) 16-bit instruction
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second operand
First operand
rp Note
AX
#word
MOVW
ADDW
SUBW
CMPW
AX
MOVW
saddrp
!addr16
MOVW
MOVW
SP
None
MOVW
XCHW
rp
MOVW
MOVW Note
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
INCW, DECW
PUSH, POP
MOVW
MOVW
SP
sfrp
MOVW
Note Only when rp = BC, DE or HL
(3) Bit manipulation instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second operand
A.bit
First operand
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
A.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit
MOV1
BT
BF
SET1
CLR1
BTCLR
CY
MOV1
AND1
MOV1
AND1
MOV1
AND1
MOV1
AND1
MOV1
AND1
SET1
CLR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
NOT1
(4) Call instruction/branch instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second operand
First operand
Basic instruction
Compound
instruction
AX
BR
!addr16
CALL
BR
!addr11
CALLF
[addr5]
CALLT
$addr16
BR, BC, BNC
BZ, BNZ
BT, BF
BTCLR
DBNZ
35
µPD78052(A), 78053(A), 78054(A)
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
36
µPD78052(A), 78053(A), 78054(A)
11. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Parameter
Symbol
Supply voltage
VDD
Test Conditions
Rating
Unit
–0.3 to +7.0
V
AVDD
–0.3 to V DD+0.3
V
AVREF0
–0.3 to V DD+0.3
V
AVREF1
–0.3 to V DD+0.3
V
AVSS
Input voltage
VI1
–0.3 to +0.3
V
–0.3 to V DD+0.3
V
–0.3 to +16
V
–0.3 to V DD+0.3
V
AVSS–0.3 to AVREF0 +0.3
V
1 pin
–10
mA
P01 to P06, P30-P37, P56, P57, P60 to P67, P120 to P127 total
–15
mA
P10 to P17, P20 to P27, P40 to P47, P50 to P55,
–15
mA
Peak value
30
mA
Effective value
15
mA
Peak value
100
mA
Effective value
70
mA
Peak value
100
mA
Effective value
70
mA
P10 to P17, P20 to P27, P40 to P47,
Peak value
50
mA
P70 to P72, P130, P131 total
Effective value
20
mA
P01 to P06, P30 to P37, P64 to P67,
Peak value
50
mA
P120 to P127 total
Effective value
20
mA
P00 to P07, P10 to P17, P20 to P27, P30 toP37, P40 to P47,
P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130,
P131, X1, X2, XT2, RESET
VI2
Output voltage
N-ch open-drain
VO
Analog intput voltage VO
High level output
current
P60 to P63
I OH
P10 to P17
Analog input pin
P70 to P72, P130, P131 total
Low level output
current
I OL Note
1 pin
P50 to P55 total
P56, P57, P60 to P63 total
Operating ambient
temperature
TA
–40 to +85
°C
Storage
temperature
Tstg
–65 to +150
°C
Note
Effective value should be calculated as follows: [Effective value] = [Peak value] × √duty
Caution
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter
or even momentarily. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions which ensure that the absolute maximum ratings are not exceeded.
Remark The characteristics of dual-function pins and port pins are the same unless otherwise specified.
37
µPD78052(A), 78053(A), 78054(A)
MAIN SYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS (TA = –40 to 85 °C, VDD = 2.0 to 6.0 V)
Resonator
Recommended Circuit
X2
Ceramic
resonator
X1 IC
Test Conditions
Parameter
Oscillation
frequency (fX) Note 1
C2
C1
Oscillation
stabilization time
X2
Crystal
resonator
X1 IC
C1
X1
frequency (fX)
Unit
5.0
MHz
4
ms
5.0
MHz
ms
Note 2
Note 1
MAX.
10
VDD = 4.5 to 6.0 V
Oscillation
X1 input
X2
1.0
1.0
Note 1
stabilization time
External
clock
TYP.
After VDD reaches oscillation voltage range MIN.
Oscillation
frequency (fX)
C2
Note 2
VDD = Oscillation
voltage range
MIN.
30
1.0
5.0
MHz
85
500
ns
X1 input
µPD74HCU04
high-/low-level width
(tXH , t XL)
Notes 1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line
in the above figures should be carried out as follows to avoid an adverse effect from wiring
capacitance.
•
•
•
•
•
•
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as VSS.
Do not ground wiring to a ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock,
the subsystem clock should be switched again to the main system clock after the oscillation
stabilization time is secured by the program.
38
µPD78052(A), 78053(A), 78054(A)
SUBSYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS (TA = –40 to +85 °C, V DD = 2.0 to 6.0 V)
Resonator
Recommended Circuit
IC XT2
Crystal
resonator
XT1
R1
C4
External
clock
XT2
C3
XT1
Parameter
Test Conditions
Oscillation
frequency (fXT) Note 1
Oscillation
stabilization time Note 2
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
VDD = 4.5 to 6.0 V
s
10
XT1 input
frequency (fXT) Note 1
32
100
kHz
XT1 input
high-/low-level width
(tXTH , tXTL)
5
15
µs
Notes 1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage MIN.
Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line in
the above figure should be carried out as follows to avoid an adverse effect from wiring
capacitance.
•
•
•
•
•
•
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as V SS.
Do not ground wiring to a ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption
current, and is more prone to malfunction due to noise than the main system clock oscillator.
Particular care is therefore required with the wiring method when the subsystem clock is used.
39
µPD78052(A), 78053(A), 78054(A)
RECOMMENDED OSCILLATOR CONSTANT
MAIN SYSTEM CLOCK: CERAMIC RESONATOR (T A = –40 to +85 °C)
Manufacturer
Product Name
Recommended
Oscillator Constant
Frequency
(MHz)
C1 (pF)
C2 (pF)
Oscillation
Voltage Range
R1 (kΩ)
MIN. (V)
MAX. (V)
Remarks
Murata Mfg.
Co., Ltd.
CSA5.00MG
5.00
30
30
0
2.0
6.0
CST5.00MGW
5.00
On-chip
On-chip
0
2.0
6.0
Capacitor on-chip
Kyocera
Corp.
KBR-5.0MSA
5.00
33
33
0
2.0
6.0
Lead type
KBR-5.0MKS
5.00
On-chip
On-chip
0
2.0
6.0
Capacitor on-chip,
lead type
KBR-5.0MWS
5.00
On-chip
On-chip
0
2.0
6.0
Capacitor on-chip,
chip type
PBRC 5.00A
5.00
33
33
0
2.0
6.0
Chip type
CCR4.0MC3
4.00
On-chip
On-chip
0
2.0
6.0
Capacitor on-chip
CCR5.0MC3
5.00
On-chip
On-chip
0
2.0
6.0
Capacitor on-chip
TDK Corp.
MAIN SYSTEM CLOCK: CRYSTAL RESONATOR (T A = –10 to +70 °C)
Manufacturer
Daishinku
Product Name
SMD-49
Recommended
Oscillator Constant
Frequency
(MHz)
Oscillation
Voltage Range
C1 (pF)
C2 (pF)
R1 (kΩ)
MIN. (V)
MAX. (V)
27
27
1.5
2.0
6.0
3.579545
SUBSYSTEM CLOCK: CRYSTAL RESONATOR (T A = –10 to +70 °C)
Manufacturer
Daishinku
Product Name
DT-38
Recommended
Oscillator Constant
Frequency
(kHz)
Oscillation
Voltage Range
C3 (pF)
C4 (pF)
R2 (kΩ)
MIN. (V)
MAX. (V)
27
20
330
2.0
6.0
32.768
(1TA252E00)
CAPACITANCE (TA = 25 °C , V DD = VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input
capacitance
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
15
pF
Input/output
capacitance
CIO
f = 1 MHz
Unmeasured pins returned
to 0 V.
P01 to P06, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67, P70 to P72,
P120 to P127, P130, P131
15
pF
P60 to P63
20
pF
Remark
40
The characteristics of dual-function pins and port pins are the same unless otherwise specified.
µPD78052(A), 78053(A), 78054(A)
DC CHARACTERISTICS (TA = –40 to +85 °C, V DD = 2.0 to 6.0 V)
Parameter
Symbol
Input voltage
high
VIH1
VIH2
Test Conditions
MIN.
P10 to P17, P21, P23, P30 to P32,
P35 to P37, P40 to P47, P50 to P57,
P64 to P67, P71, P120 to P127,
P130, P131
VDD = 2.7 to 6.0 V
P00 to P06, P20, P22, P24 to P27,
VDD = 2.7 to 6.0 V
P33, P34, P70, P72, RESET
0.7VDD
VDD
V
0.8VDD
VDD
V
0.8VDD
VDD
V
0.85VDD
VDD
V
15
V
VDD = 2.7 to 6.0 V
0.7VDD
0.8VDD
15
V
VIH4
X1, X2
VDD = 2.7 to 6.0 V
VDD–0.5
VDD
V
VDD–0.2
VDD
V
4.5 V ≤ VDD ≤ 6.0 V
0.8VDD
VDD
V
2.7 V ≤ VDD < 4.5 V
0.9VDD
VDD
V
2.0 V ≤ VDD < 2.7 V
0.9VDD
VDD
V
0
0.3VDD
V
0
0.2VDD
V
0
0.2VDD
V
0
0.15VDD
V
4.5 V ≤ VDD ≤ 6.0 V
0
0.3VDD
V
2.7 V ≤ VDD < 4.5 V
0
0.2VDD
V
0
0.1VDD
V
VDD = 2.7 to 6.0 V
0
0.4
V
0
0.2
V
4.5 V ≤ VDD ≤ 6.0 V
0
0.2VDD
V
2.7 V ≤ VDD < 4.5 V
0
0.1VDD
V
2.0 V ≤ VDD < 2.7 V
0
0.1VDD
V
VIL1
XT1/P07, XT2
Note
P10 to P17, P21, P23, P30 to P32,
P35 to P37, P40 to P47, P50 to P57,
P64 to P67, P71, P120 to P127,
P130, P131
VDD = 2.7 to 6.0 V
P00 to P06, P20, P22, P24 to P27,
VDD = 2.7 to 6.0 V
P33, P34, P70, P72, RESET
VIL3
VIL4
VIL5
P60 to P63
X1, X2
XT1/P07, XT2
VOH
VDD = 4.5 to 6.0 V, IOH = –1 mA
VOL1
P50 to P57, P60 to P63
Note
VDD–1.0
I OH = –100 µ A
high
Output voltage
low
Unit
P60 to P63
(N-ch open-drain)
VIL2
Output voltage
MAX.
VIH3
VIH5
Input voltage
low
Remark
VOL2
SB0, SB1, SCK0
VOL3
I OL = 400 µ A
V
VDD–0.5
VDD = 4.5 to 6.0 V,
I OL = 15 mA
P01 to P06, P10 to P17, P20 to P27, VDD = 4.5 to 6.0 V,
P30 to P37, P40 to P47, P64 to P67, I OL = 1.6 mA
P70 to P72, P120 to P127, P130,
P131
Note
TYP.
VDD = 4.5 to 6.0 V,
open-drain,
pulled-up (R = 1 kΩ)
V
0.4
2.0
V
0.4
V
0.2VDD
V
0.5
V
For use as P07, use an inverter to input the inverted phase of P07 to the XT2 pin.
The characteristics of dual-function pins and port pins are the same unless otherwise specified.
41
µPD78052(A), 78053(A), 78054(A)
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V)
Parameter
Input leakage
current high
Symbol
I LIH1
Test Conditions
VIN = VDD
I LIH2
Input leakage
current low
MIN.
TYP.
MAX.
Unit
P00 to P06, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P72,
P120 to P127, P130, P131, RESET
3
µA
X1, X2, XT1/P07, XT2
20
µA
I LIH3
VIN = 15 V
P60 to P63
80
µA
I LIL1
VIN = 0 V
P00 to P06, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, P70 to P72,
P120 to P127, P130, P131, RESET
–3
µA
–20
µA
–3 Note 1
µA
I LIL2
X1, X2, XT1/P07, XT2
I LIL3
P60 to P63
Output leakage
current high
I LOH
VOUT = V DD
3
µA
Output leakage
current low
I LOL
VOUT = 0 V
–3
µA
Mask option pullup resistor
R1
VIN = 0 V, P60 to P63
20
40
90
kΩ
Software pullup resistor Note 2
R2
VIN = 0 V, P01 to P06, 4.5 V ≤ VDD ≤ 6.0 V
P10 to P17, P20 to P27,
P30 to P37, P40 to P47,
P50 to P57, P64 to P67, 2.7 V ≤ VDD < 4.5 V
P70 to P72, P120 to
P127, P130, P131
15
40
90
kΩ
500
kΩ
20
Notes 1. When the pull-up resistor is not included in P60 to P63 (specified by a mask option), the –200 µA (MAX.)
low-level input leakage current flows only at the 1.5-clock interval (no wait) when the read instruction to
the port 6 (P6) and port mode register 6 (PM6) is executed. Other than the 1.5-clock interval, –3 µ A (MAX.)
current flows.
2. A software pull-up resistor can be used only in the range of V DD = 2.7 to 6.0 V.
Remark
42
The characteristics of dual-function pins and port pins are the same unless otherwise specified.
µPD78052(A), 78053(A), 78054(A)
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V)
Parameter
Power supply
current Note 1
Symbol
IDD1
Test Conditions
5.0-MHz Crystal oscillation
operating mode
(fXX = 2.5 MHz) Note 2
5.0-MHz Crystal oscillation
operating mode
(fXX = 5.0 MHz) Note 3
IDD2
5.0-MHz Crystal oscillation
HALT mode
(fXX = 2.5 MHz) Note 2
5.0-MHz Crystal oscillation
HALT mode
(fXX = 5.0 MHz) Note 3
I DD3
I DD4
I DD5
I DD6
32.768-kHz Crystal oscillation
operating mode Note 4
32.768-kHz Crystal oscillation
HALT mode Note 4
XT1 = V DD
STOP mode
When feedback resistor is used
XT1 = V DD
STOP mode
When feedback resistor is unused
MIN.
VDD = 5.0 V ± 10 %
Note 5
VDD = 3.0 V ± 10 %
Note 6
VDD = 2.2 V ± 10 % Note 6
VDD = 5.0 V ± 10 %
Note 5
VDD = 3.0 V ± 10 %
Note 6
TYP.
MAX.
Unit
4
12
mA
0.6
1.8
mA
0.35
1.05
mA
6.5
19.5
mA
0.8
2.4
mA
VDD = 5.0 V ± 10 %
1.4
4.2
mA
VDD = 3.0 V ± 10 %
0.5
1.5
mA
VDD = 2.2 V ± 10 %
280
840
µA
VDD = 5.0 V ± 10 %
1.6
4.8
mA
VDD = 3.0 V ± 10 %
0.65
1.95
mA
VDD = 5.0 V ± 10 %
60
120
µA
VDD = 3.0 V ± 10 %
32
64
µA
VDD = 2.2 V ± 10 %
24
48
µA
VDD = 5.0 V ± 10 %
25
55
µA
VDD = 3.0 V ± 10 %
5
15
µA
VDD = 2.2 V ± 10 %
2.5
12.5
µA
VDD = 5.0 V ± 10 %
1
30
µA
VDD = 3.0 V ± 10 %
0.5
10
µA
VDD = 2.2 V ± 10 %
0.3
10
µA
VDD = 5.0 V ± 10 %
0.1
30
µA
VDD = 3.0 V ± 10 %
0.05
10
µA
VDD = 2.2 V ± 10 %
0.05
10
µA
Notes 1. The current flowing in the VDD pin. Not including the current flowing in the A/D converter, D/A converter,
and on-chip pull-up resistor.
2. fXX=fX /2 operation (when the oscillation mode selection register (OSMS) is set to 00H)
3. fXX = f X operation (when the OSMS is set to 01H)
4. When the main system clock is stopped
5. High-speed mode operation (when the processor clock control register (PCC) is set to 00H)
6. Low-speed mode operation (when the PCC is set to 04H)
Remark fXX : Main system clock frequency (fX or fX/2)
fX : Main system clock oscillation frequency
43
µPD78052(A), 78053(A), 78054(A)
AC CHARACTERISTICS
(1) BASIC OPERATION (TA = –40 to +85 °C, V DD = 2.0 to 6.0 V)
Parameter
Cycle time
(Min. instruction
Symbol
TCY
Test Conditions
Operating on main
fXX = fX/2
Note 1
MIN.
f XX = f X Note 2
f TI
TI00 input
high-/low-level width
t TIH ,
tTIL
TI01, TI1, TI2 input
t TIH ,
high-/low-level width
tTIL
Interrupt input
high-/low-level
64
µs
64
µs
4.5 V ≤ V DD ≤ 6.0 V
0.4
32
µs
2.7 V ≤ V DD < 4.5 V
0.8
32
µs
INTP0
t INTL
INTP1 to INTP6, KR0 to KR7
t RSL
0
0
VDD = 4.5 to 6.0 V
width
RESET
40
VDD = 4.5 to 6.0 V
t INTH,
VDD = 2.7 to 6.0 V
low-level width
Unit
0.8
Operating on subsystem clock
TI00, TI01, TI1, TI2
input frequency
MAX.
2.2
VDD = 2.7 to 6.0 V
system clock
execution time)
TYP.
125
µs
4
275
MHz
kHz
8/f sam Note 3
µs
100
ns
1.8
µs
8/fsam
VDD = 2.7 to 6.0 V
122
Note 3
µs
10
µs
20
µs
10
µs
20
µs
Notes 1. When oscillation mode selection register (OSMS) is set to 00H
2. When OSMS is set to 01H
3. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock selection register, f sam is selectable
between fXX/2N, fXX /32, fXX/64, and f XX/128 (when N = 0 to 4).
Remark fXX : Main system clock frequency (fX or f X/2)
fX : Main system clock oscillation frequency
44
µPD78052(A), 78053(A), 78054(A)
T CY vs VDD (At f XX = f X main system clock operation)
60
60
10
10
Cycle Time TCY [µs]
Cycle Time TCY [µ s]
TCY vs VDD (At fXX = fX/2 main system clock operation)
Operation Guaranteed
Range
2.0
Operation Guaranteed
Range
2.0
1.0
1.0
0.5
0.4
0.5
0.4
0
0
1
2
3
4
5
Supply Voltage VDD [V]
6
1
2
3
4
5
6
Supply Voltage VDD [V]
45
µPD78052(A), 78053(A), 78054(A)
(2) READ/WRITE OPERATION
(a) When MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85 °C, V DD = 4.5 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
t ASTH
0.85tCY–50
ns
Address setup time
t ADS
0.85tCY–50
ns
Address hold time
t ADH
50
ns
Data input time from address
t ADD1
(2.85+2n)t CY–80
ns
t ADD2
(4+2n)t CY–100
ns
t RDD1
(2+2n)t CY–100
ns
t RDD2
(2.85+2n)tCY–100
ns
Data input time from RD↓
Read data hold time
t RDH
0
ns
RD low-level width
t RDL1
(2+2n)t CY–60
ns
t RDL2
(2.85+2n)tCY –60
ns
t RDWT1
0.85tCY–50
ns
t RDWT2
2tCY–60
ns
WAIT↓ input time from WR↓
t WRWT
2tCY–60
ns
WAIT low-level width
t WTL
(1.15+2n)t CY
(2+2n)t CY
ns
Write data setup time
t WDS
(2.85+2n)t CY–100
ns
Write data hold time
t WDH
20
ns
WR low-level width
t WRL
(2.85+2n)tCY –60
ns
RD↓ delay time from ASTB↓
t ASTRD
25
ns
WR↓ delay time from ASTB↓
t ASTWR
0.85t CY+20
ns
ASTB↑ delay time from
RD↑ in external fetch
t RDAST
0.85tCY–10
1.15t CY+20
ns
Address hold time from
RD↑ in external fetch
t RDADH
0.85tCY–50
1.15t CY+50
ns
Write data output time from RD↑
t RDWD
40
Write data output time from WR↓
t WRWD
0
50
ns
Address hold time from WR↑
tWRADH
0.85tCY
1.15t CY+40
ns
RD↑ delay time from WAIT↑
t WTRD
1.15t CY+40
3.15t CY+40
ns
WR↑ delay time from WAIT↑
t WTWR
1.15t CY+30
3.15t CY+30
ns
WAIT↓ input time from RD↓
Remarks
46
1.
2.
3.
4.
MCS: Oscillation mode selection register (OSMS) bit 0
PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0
tCY = TCY/4
n indicates the number of waits.
ns
µPD78052(A), 78053(A), 78054(A)
(b) Except when MCS = 1, PCC2 to PCC0 = 000B (T A = –40 to +85 °C, VDD = 2.0 to 6.0 V) (1/2)
Parameter
Symbol
Test Conditions
MIN.
t CY–80
ASTB high-level width
tASTH
VDD = 2.7 to 6.0 V
Address setup time
tADS
VDD = 2.7 to 6.0 V
Address hold time
tADH
VDD = 2.7 to 6.0 V
Data input time from address
tADD1
VDD = 2.7 to 6.0 V
MAX.
ns
t CY–150
ns
t CY–80
ns
t CY–150
ns
0.4t CY–10
ns
0.37tCY–40
tADD2
Data input time from RD↓
VDD = 2.7 to 6.0 V
tRDD1
VDD = 2.7 to 6.0 V
tRDD2
VDD = 2.7 to 6.0 V
Read data hold time
tRDH
RD low-level width
tRDL1
ns
(3+2n)tCY –160
ns
(3+2n)tCY –320
ns
(4+2n)tCY –200
ns
(4+2n)tCY –300
ns
(1.4+2n)t CY–70
ns
(1.37+2n)t CY–120
ns
(2.4+2n)t CY–70
ns
(2.37+2n)t CY–120
ns
0
VDD = 2.7 to 6.0 V
tRDL2
VDD = 2.7 to 6.0 V
tRDWT1
VDD = 2.7 to 6.0 V
ns
(1.4+2n)tCY –20
ns
(1.37+2n)t CY–20
ns
(2.4+2n)tCY –20
ns
(2.37+2n)t CY–20
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
ns
tCY–200
ns
VDD = 2.7 to 6.0 V
2tCY–100
ns
2tCY–200
ns
tWRWT
VDD = 2.7 to 6.0 V
2tCY–100
ns
2tCY–200
ns
(2+2n)t CY
ns
tWTL
Write data setup time
tWDS
Write data hold time
tWDH
WR low-level width
tWRL
(1+2n)t CY
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
RD↓ delay time from ASTB↓
tASTRD
VDD = 2.7 to 6.0 V
WR↓ delay time from ASTB↓
tASTWR
VDD = 2.7 to 6.0 V
1.
2.
3.
4.
ns
tCY–100
tRDWT2
WAIT low-level width
Remarks
Unit
(2.4+2n)tCY –60
ns
(2.37+2n)tCY –100
ns
20
ns
(2.4+2n)tCY –20
ns
(2.37+2n)t CY–20
ns
0.4t CY–30
ns
0.37tCY–50
ns
1.4t CY–30
ns
1.37tCY–50
ns
MCS: Oscillation mode selection register (OSMS) bit 0
PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0
tCY = T CY/4
n indicates the number of waits.
47
µPD78052(A), 78053(A), 78054(A)
(b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85 °C, V DD = 2.0 to 6.0 V) (2/2)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB↑ delay time from
RD↑ in external fetch
t RDAST
tCY–10
t CY+20
ns
Address hold time from
RD↑ in external fetch
t RDADH
t CY–50
t CY+50
ns
Write data output time from RD↑
t RDWD
Write data output time from WR↓
Address hold time from WR↑
tWRWD
t WRADH
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
RD↑ delay time from WAIT↑
t WTRD
VDD = 2.7 to 6.0 V
WR↑ delay time from WAIT↑
t WTWR
VDD = 2.7 to 6.0 V
Remarks
48
1.
2.
3.
4.
0.4tCY –20
ns
0.37tCY–40
ns
0
60
ns
0
120
ns
t CY
t CY+60
ns
t CY
t CY+120
ns
0.6t CY+180
2.6t CY+180
ns
0.63t CY+350
2.63t CY+350
ns
0.6t CY+120
2.6t CY+120
ns
0.63t CY+240
2.63t CY+240
ns
MCS: Oscillation mode selection register (OSMS) bit 0
PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0
tCY = TCY/4
n indicates the number of waits.
µPD78052(A), 78053(A), 78054(A)
(3) SERIAL INTERFACE (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V)
(a) Serial interface channel 0
(i)
3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
t KCY1
SCK0 high-/low-level
width
t KH1, t KL1
SI0 setup time
tSIK1
(to SCK0↑)
SI0 hold time (from
SCK0↑)
SO0 output delay time
from SCK0↓
Note
Test Conditions
MIN.
MAX.
Unit
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
t KCY1/2–50
ns
tKCY1/2–100
ns
4.5 V ≤ VDD ≤ 6.0 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
300
ns
ns
400
ns
VDD = 4.5 to 6.0 V
tKSI1
tKSO1
TYP.
C = 100 pF Note
300
ns
MAX.
Unit
C is the load capacitance of SO0 output line.
(ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level
width
Symbol
t KCY2
t KH2, t KL2
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
400
ns
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
800
ns
1600
ns
SI0 setup time (to SCK0↑) tSIK2
100
ns
SI0 hold time (from
SCK0↑)
tKSI2
400
ns
SO0 output delay time
from SCK0↓
tKSO2
C = 100 pF Note
300
ns
SCK0 rise, fall time
tR2, tF2
When using external device
160
ns
1000
ns
expansion function
When not using external
device expansion function
Note
C is the load capacitance of SO0 output line.
49
µPD78052(A), 78053(A), 78054(A)
(iii) SBI mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY3
SCK0 high-/low-level
width
tKH3,
SB0, SB1 setup time
(to SCK0↑)
tSIK3
SB0, SB1 hold time
tKSI3
Test Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
t KL3
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
tKCY3/2–50
ns
t KCY3/2–150
ns
100
ns
300
ns
t KCY3/2
ns
(from SCK0↑)
SB0, SB1 output
tKSO3
VDD = 4.5 to 6.0 V
R = 1 kΩ,
delay time from SCK0↓
C = 100 pF
Note
0
250
ns
0
1000
ns
SB0, SB1↓ from SCK0↑
tKSB
t KCY3
ns
SCK0↓ from SB0, SB1↓
tSBK
t KCY3
ns
SB0, SB1 high-level
width
tSBH
t KCY3
ns
SB0, SB1 low-level
width
tSBL
tKCY3
ns
Note
50
R and C are the load resistance and load capacitance of the SCK0 and SB0, SB1 output lines.
µPD78052(A), 78053(A), 78054(A)
(iv) SBI mode (SCK0... External clock input)
Parameter
SCK0 cycle time
Symbol
tKCY4
SCK0 high-/low-level
width
tKH4,
SB0, SB1 setup time
(to SCK0↑)
tSIK4
Test Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
tKL4
SB0, SB1 hold time
(from SCK0↑)
tKSI4
SB0, SB1 output delay
time from SCK0↓
tKSO4
VDD = 4.5 to 6.0 V
R = 1 kΩ,
C = 100 pF
VDD = 4.5 to 6.0 V
Note
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
300
ns
t KCY4/2
ns
0
300
ns
0
1000
ns
SB0, SB1↓ from SCK0↑
tKSB
t KCY4
ns
SCK0↓ from SB0, SB1↓
tSBK
t KCY4
ns
SB0, SB1 high-level
width
tSBH
tKCY4
ns
SB0, SB1 low-level
width
tSBL
tKCY4
ns
SCK0 rise, fall time
tR4, t F4
When using external device
160
ns
1000
ns
expansion function
When not using external
device expansion function
Note
R and C are the load resistance and load capacitance of the SB0, SB1 output line.
51
µPD78052(A), 78053(A), 78054(A)
(v) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY5
Test Conditions
R = 1 kΩ,
C = 100 pF
SCK0 high-level width
SCK0 low-level width
SB0, SB1 setup time
VDD = 2.7 to 6.0 V
MIN.
(to SCK0↑)
ns
t KCY5/2–190
ns
tKCY5/2–50
ns
tKCY5 /2–100
ns
4.5 V ≤ VDD ≤ 6.0 V
300
ns
2.7 V ≤ VDD < 4.5 V
350
ns
400
ns
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI5
600
SB0, SB1 output delay
time from SCK0↓
tKSO5
0
Note
ns
t KCY5/2–160
VDD = 4.5 to 6.0 V
tSIK5
Unit
ns
3200
VDD = 2.7 to 6.0 V
tKL5
MAX.
1600
Note
tKH5
TYP.
300
ns
R and C are the load resistance and load capacitance of the SCK0 and SB0, SB1 output lines.
(vi) 2-wire serial I/O mode (SCK0... External clock input)
Parameter
SCK0 cycle time
Symbol
TYP.
MAX.
Unit
ns
3200
ns
650
ns
1300
ns
800
ns
1600
ns
tSIK6
100
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI6
t KCY6/2
ns
SB0, SB1 output delay
time from SCK0↓
tKSO6
SCK0 rise, fall time
tR6, t F6
SCK0 low-level width
SB0, SB1 setup time
tKH6
tKL6
VDD = 2.7 to 6.0 V
MIN.
1600
SCK0 high-level width
tKCY6
Test Conditions
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
(to SCK0↑)
R = 1 kΩ,
VDD = 4.5 to 6.0 V
C = 100 pF Note
0
300
ns
0
500
ns
160
ns
1000
ns
When using external device
expansion function
When not using external
device expansion function
Note
52
R and C are the load resistance and load capacitance of the SB0, SB1 output line.
µPD78052(A), 78053(A), 78054(A)
(b) Serial interface channel 1
(i) 3-wire serial I/O mode (SCK1... Internal clock output)
Parameter
SCK1 cycle time
Symbol
t KCY7
SCK1 high-/low-level
tKH7,
width
t KL7
SI1 setup time
tSIK7
(to SCK1↑)
SI1 hold time
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
tKCY7/2–50
ns
tKCY7/2–100
ns
4.5 V ≤ VDD ≤ 6.0 V
100
ns
2.7 V ≤ V DD < 4.5 V
150
ns
300
ns
400
ns
V DD = 4.5 to 6.0 V
tKSI7
(from SCK1↑)
SO1 output delay time
tKSO7
C = 100 pF
Note
300
ns
MAX.
Unit
from SCK1↓
Note
C is the load capacitance of the SO1 output line.
(ii) 3-wire serial I/O mode (SCK1... External clock input)
Parameter
SCK1 cycle time
Symbol
t KCY8
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
SCK1 high-/low-level
tKH8,
4.5 V ≤ VDD ≤ 6.0 V
400
ns
width
t KL8
2.7 V ≤ VDD < 4.5 V
800
ns
1600
ns
tSIK8
100
ns
tKSI8
400
ns
SI1 setup time
(to SCK1↑)
SI1 hold time
(from SCK1↑)
SO1 output delay
Note
tKSO8
C = 100 pF
t R8, tF8
When using external device
expansion function
300
ns
160
ns
1000
ns
time from SCK1↓
SCK1 rise, fall time
When not using external
device expansion function
Note
C is the load capacitance of the SO1 output line.
53
µPD78052(A), 78053(A), 78054(A)
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...Internal clock output)
Parameter
SCK1 cycle time
SCK1 high-/low-level width
SI1 setup time (to SCK1↑)
Symbol
t KCY9
Test Conditions
2.7 V ≤ VDD < 4.5 V
1600
ns
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
tKSO9
STB↑ from SCK1↑
tSBD
Strobe signal high-level width
t SBW
Busy signal setup time
(to busy signal detection timing)
tBYH
SCK1↓ from busy inactive
tSPS
Note
C = 100 pF
3200
ns
tKCY9/2–50
ns
t KCY9/2–100
ns
100
ns
150
ns
300
ns
400
ns
Note
VDD = 2.7 to 6.0 V
tBYS
Busy signal hold time
(from busy signal detection timing)
Unit
ns
tSIK9
tKSI9
MAX.
800
VDD = 4.5 to 6.0 V
SO1 output delay time from SCK1↓
TYP.
4.5 V ≤ VDD ≤ 6.0 V
t KH9,
t KL9
SI1 hold time (from SCK1↑)
MIN.
300
ns
t KCY9/2–100
tKCY9/2+100
ns
t KCY9–30
t KCY9+30
ns
t KCY9–60
t KCY9+60
ns
100
ns
4.5 V ≤ VDD ≤ 6.0 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
200
ns
2tKCY9
ns
C is the load capacitance of the SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...External clock input)
Parameter
SCK1 cycle time
SCK1 high-/low-level width
Symbol
t KCY10
t KH10 ,
t KL10
SI1 setup time (to SCK1↑)
t SIK10
SI1 hold time (from SCK1↑)
t KSI10
Test Conditions
MAX.
Unit
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
4.5 V ≤ VDD ≤ 6.0 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
1600
ns
100
ns
400
ns
Note
t KSO10
SCK1 rise, fall time
tR10, t F10 When using external device
expansion function
C = 100 pF
When not using external
device expansion function
54
TYP.
4.5 V ≤ VDD ≤ 6.0 V
SO1 output delay time from SCK1↓
Note
MIN.
C is the load capacitance of the SO1 output line.
300
ns
160
ns
1000
ns
µPD78052(A), 78053(A), 78054(A)
(c) Serial interface channel 2
(i) 3-wire serial I/O mode (SCK2... Internal clock output)
Parameter
SCK2 cycle time
Symbol
t KCY11
SCK2 high-/low-level
tKH11 ,
width
t KL11
SI2 setup time
tSIK11
(to SCK2↑)
SI2 hold time
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
tKCY11 /2–50
ns
t KCY11/2–100
ns
4.5 V ≤ VDD ≤ 6.0 V
100
ns
2.7 V ≤ V DD < 4.5 V
150
ns
300
ns
400
ns
V DD = 4.5 to 6.0 V
tKSI11
(from SCK2↑)
SO2 output delay time
tKSO11
C = 100 pF
Note
300
ns
MAX.
Unit
from SCK2↓
Note
C is the load capacitance of the SO2 output line.
(ii) 3-wire serial I/O mode (SCK2... External clock input)
Parameter
SCK2 cycle time
Symbol
t KCY12
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 6.0 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
SCK2 high-/low-level
tKH12 ,
4.5 V ≤ VDD ≤ 6.0 V
400
ns
width
t KL12
2.7 V ≤ VDD < 4.5 V
800
ns
1600
ns
tSIK12
100
ns
tKSI12
400
ns
SI2 setup time
(to SCK2↑)
SI2 hold time
(from SCK2↑)
SO2 output delay
tKSO12
C = 100 pF
t R12, t F12
Note
300
ns
When using external
device expansion function
160
ns
When not using external
device expansion function
1000
ns
time from SCK2↓
SCK2 rise, fall time
Note
C is the load capacitance of the SO2 output line.
55
µPD78052(A), 78053(A), 78054(A)
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Transfer rate
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 6.0 V
78125
bps
2.7 V ≤ VDD < 4.5 V
39063
bps
19531
bps
MAX.
Unit
(iv) UART mode (External clock input)
Parameter
ASCK cycle time
ASCK high-/low-level width
Symbol
Test Conditions
MIN.
t KCY13
4.5 V ≤ VDD ≤ 6.0 V
800
TYP.
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
3200
ns
t KH13 ,
4.5 V ≤ VDD ≤ 6.0 V
400
ns
t KL13
2.7 V ≤ VDD < 4.5 V
800
ns
1600
Transfer rate
ASCK rise, fall time
56
tR13,
tF13
ns
4.5 V ≤ VDD ≤ 6.0 V
39063
bps
2.7 V ≤ VDD < 4.5 V
19531
bps
9766
bps
1000
ns
160
ns
VDD = 4.5 to 6.0 V,
when not using
external device
expansion function
µPD78052(A), 78053(A), 78054(A)
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 Input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 Input
TI Timing
1/fTI
tTIL
tTIH
TI00, TI01, TI1, TI2
57
µPD78052(A), 78053(A), 78054(A)
Read/Write Operation
External Fetch (No Wait) :
A8 to A15
Upper 8-Bit Address
Lower 8-Bit
Address
tADD1
Hi-Z
AD0 to AD7
tADS
tASTH
Operation
Code
tRDADH
tRDD1
tADH
tRDAST
ASTB
RD
tRDL1
tASTRD
tRDH
External Fetch (Wait Insertion) :
A8 to A15
Upper 8-Bit Address
Lower 8-Bit
Address
tADD1
Hi-Z
AD0 to AD7
Operation
Code
tRDADH
tRDD1
tADS
tASTH
tADH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
58
tWTL
tWTRD
µPD78052(A), 78053(A), 78054(A)
External Data Access (No Wait) :
A8 to A15
Upper 8-Bit Address
Lower
8-Bit
Address
tADD2
Hi-Z
AD0 to AD7
Read Data
Hi-Z
Hi-Z
Write Data
tRDD2
tADS
tADH
tRDH
tASTH
ASTB
RD
tRDWD
tRDL2
tASTRD
tWDH
tWDS
tWRWD
WR
tASTWR
tWRL
tWRADH
External Data Access (Wait Insertion) :
A8 to A15
Upper 8-Bit Address
Lower
8-Bit
Address
tADD2
Hi-Z
AD0 to AD7
Read Data
Hi-Z
Hi-Z
Write Data
tRDD2
tADS
tADH
tRDH
tASTH
ASTB
tASTRD
RD
tRDWD
tRDL2
tWDH
tWDS
tWRWD
WR
tASTWR
tWRL
tWRADH
WAIT
tRDWT2
tWTRD
tWTL
tWRWT
tWTL
tWTWR
59
µPD78052(A), 78053(A), 78054(A)
Serial Transfer Timing
3-Wire Serial I/O Mode :
tKCYm
tKLm
tKHm
tFn
tRn
SCK0 to SCK2
tSIKm
SI0 to SI2
tKSIm
Input Data
tKSOm
SO0 to SO2
Output Data
m = 1, 2, 7, 8, 11, 12
n = 2, 8, 12
SBI Mode (Bus Release Signal Transfer) :
tKCY3,4
tKL3,4
tKH3,4
tF4
tR4
SCK0
tKSB
tSBL
tSBK
tSBH
tSIK3,4
SB0, SB1
tKSO3,4
SBI Mode (Command Signal Transfer) :
tKCY3,4
tKL3,4
tKH3,4
tF4
tR4
SCK0
tSIK3,4
tKSB
tSBK
SB0, SB1
tKSO3,4
60
tKSI3,4
tKSI3, 4
µPD78052(A), 78053(A), 78054(A)
2-Wire Serial I/O Mode :
tKCY5,6
tKL5,6
tKH5,6
tR6
tF6
SCK0
tSIK5,6
tKSI5,6
tKSO5,6
SB0, SB1
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function :
SO1
SI1
D2
D1
D2
D0
D1
D7
D0
D7
tKSI9,10
tSIK9,10
tKH9,10
tF10
tKSO9,10
SCK1
tR10
tKL9,10
STB
tSBD
tSBW
tKCY9,10
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy Processing) :
SCK1
7
8
9 Note
10 Note
tBYS
10+n Note
tBYH
1
tSPS
BUSY
(Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
61
µPD78052(A), 78053(A), 78054(A)
UART Mode (External Clock Input) :
t KCY13
t KL13
t KH13
tR13
tF13
ASCK
A/D CONVERTER CHARACTERISTICS (T A = –40 to +85 °C, AVDD = V DD = 2.0 to 6.0 V, AVSS = V SS = 0 V)
Parameter
Symbol
Test Conditions
Resolution
Overall error
Note
MIN.
TYP.
MAX.
Unit
8
8
8
bit
2.7 V ≤ AVREF0 ≤ AVDD
0.6
%
2.0 V ≤ AVREF0 < 2.7 V
1.4
%
200
µs
Conversion time
t CONV
19.1
Sampling time
t SAMP
12/fxx
Analog input voltage
VIAN
AVSS
AVREF0
V
Reference voltage
AVREF0
2.0
AVDD
V
Resistance between AV REF0 and AVSS
RAIREF0
4
Note
µs
kΩ
14
Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value.
Remark fXX : Main system clock frequency (fX or f X/2)
fx : Main system clock oscillation frequency
D/A CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V, AV SS = VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
Resolution
Overall error
8
bit
1.2
%
R = 4 MΩ Note 1
0.8
%
0.6
%
C = 30 pF 4.5 V ≤ AVREF1 ≤ 6.0 V
10
µs
2.7 V ≤ AVREF1 < 4.5 V
15
µs
2.0 V ≤ AVREF1 < 2.7 V
20
µs
R = 10 MΩ
Note 1
Output resistance
RO
Analog reference voltage
AVREF1
AVREF1 current
I REF1
Unit
Note 1
R = 2 MΩ
Settling time
MAX.
Note 1
DACS0, DACS1 = 55H
Note 2
10
2.0
Note 2
kΩ
VDD
V
1.5
mA
Notes 1. R and C denote D/A converter output pin load resistance and load capacitance, respectively.
2. Value for one D/A converter channel
Remark
62
DACS0, DACS1: D/A conversion value setting register 0, 1
µPD78052(A), 78053(A), 78054(A)
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (T A = –40 to +85 °C)
Parameter
Symbol
Data retention power
supply voltage
VDDDR
Data retention
power supply
current
IDDDR
Release signal set time
tSREL
Oscillation stabilization wait time
tWAIT
Note
Test Conditions
MIN.
TYP.
1.8
VDDDR = 1.8 V
Subsystem clock stop and
feedback resistor disconnected
MAX.
Unit
6.0
V
10
µA
0.1
µs
0
Release by RESET
217/fx
ms
Release by interrupt
Note
ms
In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection
of 212/fXX and 214/fXX to 217/fXX is possible.
Remark fXX : Main system clock frequency (fX or f X/2)
fX : Main system clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
63
µPD78052(A), 78053(A), 78054(A)
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP6
RESET Input Timing
tRSL
RESET
64
µPD78052(A), 78053(A), 78054(A)
12. CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
IDD vs VDD (fx = fxx = 5.0 MHz)
(TA = 25 ˚C)
10.0
PCC = 00H
PCC = 01H
5.0
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT (X1 oscillation, XT1 oscillation)
1.0
Supply Current IDD (mA)
0.5
0.1
PCC = B0H
0.05
HALT (X1 stop, XT1 oscillation)
0.01
0.005
0.001
0
2
3
4
5
6
7
8
9
Supply Voltage VDD (V)
65
µPD78052(A), 78053(A), 78054(A)
IDD vs VDD (fx = 5.0 MHz, fxx = 2.5 MHz)
(TA = 25 ˚C)
10.0
PCC = 00H
5.0
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT (X1 oscillation, XT1 oscillation)
1.0
Supply Current IDD (mA)
0.5
0.1
PCC = B0H
0.05
HALT (X1 Stop, XT1 oscillation)
0.01
0.005
0.001
0
2
3
4
5
6
Supply Voltage VDD (V)
66
7
8
9
µPD78052(A), 78053(A), 78054(A)
13. PACKAGE DRAWING
80 PIN PLASTIC QFP (14×14)
A
B
60
61
41
40
detail of lead end
C D
S
R
Q
21
20
80
1
F
J
G
I
H
M
K
P
M
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
17.2±0.4
0.677±0.016
B
14.0±0.2
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.2±0.4
0.677±0.016
F
0.825
0.032
G
0.825
0.032
H
0.30±0.10
0.012 +0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.6±0.2
L
0.8±0.2
0.063±0.008
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.1±0.1
0.004±0.004
R
5°±5°
5°±5°
S
3.0 MAX.
0.119 MAX.
S80GC-65-3B9-4
Remark Dimensions and materials of ES product are the same as those of mass-production products.
67
µPD78052(A), 78053(A), 78054(A)
14. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to the information document “Semiconductor Device
Mounting Technology Manual” (C10535E).
For soldering methods and conditions other than those recommended below, contact our sales representative.
Table 14-1. Surface Mounting Type Soldering Conditions
µ PD78052GC(A)-×××-3B9 : 80-pin plastic QFP (14 × 14 mm)
µ PD78053GC(A)-×××-3B9 : 80-pin plastic QFP (14 × 14 mm)
µ PD78054GC(A)-×××-3B9 : 80-pin plastic QFP (14 × 14 mm)
Soldering
Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235 °C, Reflow time: 30 seconds or below (at 210 °C or
higher), Number of reflow processes: 3 max.
IR35-00-3
VPS
Package peak temperature: 215 °C, Reflow time: 40 seconds or below (at 200 °C or
higher), Number of reflow processes: 3 max.
VP15-00-3
Wave soldering
Solder temperature: 260 °C or below, Flow time: 10 seconds or below, Number of
flow processes: once, Preheating temperature: 120 °C or below (package surface
temperature)
WS60-00-1
Pin partial heating Pin temperature: 300 °C or below, Time: 3 seconds or below (per device side)
Caution
68
—
Use of more than one soldering method should be avoided (except for the pin partial heating
method).
µPD78052(A), 78053(A), 78054(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78054 Subseries.
Language Processing Software
RA78K/0 Note 1, 2, 3, 4
Assembler package common to 78K/0 Series
CC78K/0 Note 1, 2, 3, 4
C compiler package common to 78K/0 Series
DF78054 Note 1, 2, 3, 4
Device file common to µPD78054 Subseries
CC78K/0-L Note 1, 2, 3, 4
C compiler library source file common to 78K/0 Series
Debugging Tools
IE-78000-R
In-circuit emulator common to 78K/0 Series
IE-78000-R-A
In-circuit emulator common to 78K/0 Series (for integrated debugger)
IE-78000-R-BK
Break board common to 78K/0 Series
IE-78064-R-EM
Emulation board common to µPD78064 Subseries
EP-78230GC-R
Emulation probe common to µPD78234 Subseries
EV-9200GC-80
Socket to be mounted on the target system board manufactured for 80-pin plastic QFP
SM78K0
ID78K0
Note 5, 6, 7
Note 4, 5, 6, 7
SD78K/0 Note 1, 2
DF78054
Note 1, 2, 4, 5, 6, 7
System simulator common to 78K/0 Series
Integrated debugger for IE-78000-R-A
Screen debugger for IE-78000-R
Device file for µPD78054 Subseries
PC-9800 Series (MS-DOSTM ) based
IBM PC/ATTM and its compatibles (PC DOSTM /IBM DOSTM/MS-DOS) based
HP9000 Series 300TM (HP-UX TM) based
HP9000 Series 700TM (HP-UX) based, SPARCstation TM (SunOSTM ) based, EWS4800 Series (EWS-UX/
V) based
5. PC-9800 Series (MS-DOS + WindowsTM ) based
6. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based
7. NEWSTM (NEWS-OSTM ) based
Notes 1.
2.
3.
4.
Remarks 1. For third party development tools, see the 78K/0 Series Selection Guide (U11126E).
2. RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0 are used in combination with DF78054.
69
µPD78052(A), 78053(A), 78054(A)
Real-Time OS
RX78K/0 Note 1, 2, 3, 4
Real-time OS for 78K/0 Series
MX78K0 Note 1, 2, 3, 4
OS for 78K/0 Series
Fuzzy Inference Development Support System
FE9000
Note 1/FE9200 Note 5
Fuzzy knowledge data input tool
FT9080
Note 1/FT9085 Note 2
Translator
FI78K0 Note 1, 2
Fuzzy inference module
FD78K0 Note 1, 2
Fuzzy inference debugger
Notes 1.
2.
3.
4.
PC-9800 Series (MS-DOS) based
IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS) based
HP9000 Series 300 (HP-UX ) based
HP9000 Series 700 (HP-UX) based, SPARCstation (SunOS) based, EWS4800 Series (EWS-UX/V)
based
5. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based
Remarks 1. For third party development tools, see the 78K/0 Series Selection Guide (U11126E).
2. RX78K/0 is used in combination with DF78054.
70
µPD78052(A), 78053(A), 78054(A)
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
Document No.
Document No.
(English)
(Japanese)
µPD78054, 78054Y Subseries User’s Manual
U11747E
U11747J
µPD78052(A), 78053(A), 78054(A) Data Sheet
This document
U12171J
78K/0 Series User’s Manual Instructions
IEU-1372
IEU-849
78K/0 Series Instruction Set
–
U10904J
78K/0 Series Instruction Table
–
U10903J
µPD78054 Subseries Special Function Register Table
–
U10102J
Fundamental (III)
U10182E
IEA-767
Floating-Point Arithmetic Programs
IEA-1289
IEA-718
78K/0 Series Application Note
Development Tool Related Documents (User’s Manual)
Document Name
RA78K Series Assembler Package
Document No.
Document No.
(English)
(Japanese)
Operation
EEU-1399
EEU-809
Language
EEU-1404
EEU-815
RA78K Series Structured Assembler Preprocessor
EEU-1402
EEU-817
RA78K0 Assembler Package
Operation
U11802E
U11802J
Assembly Language
U11801E
U11801J
Structured Assembly Language
U11789E
U11789J
Operation
EEU-1280
EEU-656
Language
EEU-1284
EEU-655
Operation
U11517E
U11517J
CC78K Series C Compiler
CC78K/0 C Compiler
CC78K/0 C Compiler Application Note
CC78K Series Library Source File
Language
U11518E
U11518J
Programming Know-how
EEA-1208
EEA-618
–
EEU-777
IE-78000-R
U11376E
EEU-810
IE-78000-R-A
U10057E
U10057J
IE-78000-R-BK
EEU-1427
EEU-867
IE-78064-R-EM
EEU-1443
EEU-905
EP-78230
EEU-1515
EEU-985
Caution
The above related documents are subject to change without notice. For design purpose, etc.,
be sure to use the latest documents.
71
µPD78052(A), 78053(A), 78054(A)
Document No.
(English)
Document No.
(Japanese)
Reference
U10181E
U10181J
External Part User Open
U10092E
U10092J
Document Name
SM78K0 System Simulator, Windows based
SM78K Series System Simulator
Interface Specifications
ID78K0 Integrated Debugger, EWS based
Reference
–
U11151J
ID78K0 Integrated Debugger, PC based
Reference
U11539E
U11539J
ID78K0 Integrated Debugger, Windows based
Guide
U11649E
U11649J
SD78K/0 Screen Debugger
Introduction
–
EEU-852
PC-9800 Series (MS-DOS) based
Reference
–
U10952J
SD78K/0 Screen Debugger
Introduction
EEU-1414
EEU-5024
IBM PC/AT (PC DOS) based
Reference
U11279E
U11279J
Embedded Software Documents (User’s Manual)
Document Name
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
Document No.
Document No.
(English)
(Japanese)
Basics
–
U11537J
Installation
–
U11536J
Technical
–
U11538J
–
EEU-5010
Fuzzy Knowledge Data Input Tools
Basics
EEU-1438
EEU-829
78K/0, 78K/II, 87AD Series
EEU-1444
EEU-862
EEU-1441
EEU-858
EEU-1458
EEU-921
Fuzzy Inference Development Support System Translator
78K/0 Series Fuzzy Inference Development Support System
Fuzzy Inference Module
78K/0 Series Fuzzy Inference Development Support System
Fuzzy Inference Knowledge Debugger
Other Documents
Document Name
IC Package Manual
Document No.
Document No.
(English)
(Japanese)
C10943X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Devices
C11531E
C11531J
NEC Semiconductor Device Reliability/Quality Control System
C10983E
C10983J
Electrostatic Discharge (ESD) Test
Guide to Quality Assurance for Semiconductor Devices
Microcomputer Product Series Guide
–
MEM-539
MEI-1202
C11893J
–
U11416J
Caution The above related documents are subject to change without notice. For design purpose, etc.,
be sure to use the latest documents.
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µPD78052(A), 78053(A), 78054(A)
[MEMO]
73
µPD78052(A), 78053(A), 78054(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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µPD78052(A), 78053(A), 78054(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
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µPD78052(A), 78053(A), 78054(A)
FIP and IEBus are trademarks of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5

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