datasheet for A29010 by AMIC Technology

datasheet for A29010 by AMIC Technology
A29010 Series
128K X 8 Bit CMOS 5.0 Volt-only,
Uniform Sector Flash Memory
Document Title
128K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Revision History
Rev. No.
0.0
0.1
History
Issue Date
Initial issue
December 8, 2000
Change ILIT from 50μA to 100μA
January 3, 2001
Remark
Preliminary
Change typical byte programming time from 7μs to 35μs
0.2
Erase VCC supply voltage for ± 5% devices in Operation Ranges
February 6, 2001
Add the time limit tWPH max. = 50μs of command cycle sequence
0.3
Correct the Continuation ID command to hexadecimal
August 21, 2001
1.0
Final version release
October 7, 2003
1.1
Add Pb-Free package type
August 9, 2004
1.2
Add industrial product (-U) that operating temperature during
December 2, 2004
Final
-40°C to +85°C for TSOP type
1.3
Add A29010L-70UF and -55UF and to delete all leaded device from the
July 13, 2010
ordering sheet
1.4
Page 1: Change from typical 100,000 cycles to minimum 100,000 cycles
November 25, 2010
1.5
Page 4: Output Short Circuit Current, change from
July 20, 2012
(July, 2012, Version 1.5)
00mA to 200mA
AMIC Technology, Corp.
A29010 Series
128K X 8 Bit CMOS 5.0 Volt-only,
Uniform Sector Flash Memory
Features
̈ 5.0V ± 10% for read and write operations
̈ Access times:
- 55/70/90 (max.)
̈ Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 μA typical CMOS standby
̈ Flexible sector architecture
- 32 KbyteX4 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within that
sector
̈ Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors
and verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies bytes at specified addresses
̈ Minimum 100,000 program/erase cycles per sector
̈ 20-year data retention at 125°C
- Reliable operation for the life of the system
̈ Compatible with JEDEC-standards
- Pinout and software compatible with single-powersupply Flash memory standard
- Superior inadvertent write protection
̈ Data Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
̈ Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
̈ Package options
- 32-pin P-DIP, PLCC, or TSOP(Forward type)
̈ Industrial operating temperature range:
-40°C to 85°C for -U
General Description
The A29010 is a 5.0 volt-only Flash memory organized as
131,072 bytes of 8 bits each. The 128 Kbytes of data are
further divided into four sectors for flexible sector erase
capability. The 8 bits of data appear on I/O0 - I/O7 while the
addresses are input on A0 to A16. The A29010 is offered in 32pin PLCC, TSOP, and PDIP packages. This device is designed
to be programmed in-system with the standard system 5.0 volt
VCC supply. Additional 12.0 volt VPP is not required for insystem write or erase operations. However, the A29010 can
also be programmed in standard EPROM programmers.
The A29010 has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it is
in the Erase Suspend. Besides the I/O6 toggle bit, the A29010
has a second toggle bit, I/O2, to indicate whether the addressed
sector is being selected for erase. The A29010 also offers the
ability to program in the Erase Suspend mode. The standard
A29010 offers access times of 55, 70 and 90 ns allowing highspeed microprocessors to operate without wait states. To
eliminate bus contention the device has separate chip enable
( CE ), write enable ( WE ) and output enable ( OE ) controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The A29010 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands
are written to the command register using standard
microprocessor write timings. Register contents serve as input
to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase
(July, 2012, Version 1.5)
1
operations. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically preprograms
the array (if it is not already programmed) before executing the
erase operation. During erase, the device automatically times
the erase pulse widths and verifies proper erase margin.
The host system can detect whether a program or erase
operation is complete by reading the I/O7 ( Data Polling) and
I/O6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The A29010 is fully erased when shipped from
the factory.
The hardware sector protection feature disables operations for
both program and erase in any combination of the sectors
of memory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any other sector that is not selected for erasure. True
background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
AMIC Technology, Corp.
A29010 Series
Pin Configurations
̈ DIP
̈ PLCC
A7
5
29
A14
27
A8
A6
6
28
A13
26
A9
A5
7
27
A8
8
26
A9
A6
6
A5
7
A4
8
A3
9
NC
A13
WE
5
30
A14
28
31
29
VCC
4
A7
32
A12
NC
NC
A16
WE
30
1
31
3
2
2
A15
A12
A16
A15
VCC
3
32
4
1
A29010
NC
25
A11
A4
24
OE
A3
9
25
A11
23
A10
A2
10
24
OE
A1
11
23
A10
A2
10
A1
11
22
CE
A0
A29010L
15
I/O4
VSS
16
17
I/O3
20
I/O5
18
I/O6
19
I/O5
14
I/O2
19
I/O1
18
I/O7
I/O4
21
17
13
16
CE
I/O3
22
13
VSS
12
I/O0
15
A0
I/O6
14
I/O7
20
I/O2
21
I/O1
12
I/O0
̈ TSOP (Forward type)
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
(July, 2012, Version 1.5)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A29010V
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
AMIC Technology, Corp.
A29010 Series
Block Diagram
I/O0 - I/O7
VCC
VSS
Input/Output
Buffers
Erase Voltage
Generator
State
Control
WE
PGM Voltage
Generator
Command
Register
Chip Enable
Output Enable
Logic
CE
OE
STB
Data Latch
STB
VCC Detector
Timer
A0-A16
Address Latch
Y-Decoder
Y-Gating
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
(July, 2012, Version 1.5)
Description
A0 - A16
Address Inputs
I/O0 - I/O7
Data Inputs/Outputs
CE
Chip Enable
WE
Write Enable
OE
Output Enable
VSS
Ground
VCC
Power Supply
3
AMIC Technology, Corp.
A29010 Series
Absolute Maximum Ratings*
*Comments
Ambient Operating Temperature . ……………..-55°C to + 125°C
Storage Temperature …………………………-65°C to + 125°C
Ground to VCC ……………………………………..-2.0V to 7.0V
Output Voltage (Note 1) ……………………………-2.0V to 7.0V
A9 & OE (Note 2) …………………………………..-2.0V to 12.5V
All other pins (Note 1)……………………………….. -2.0V to 7.0V
Output Short Circuit Current (Note 3) ……………………. 200mA
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to this device. These are stress
ratings only. Functional operation of this device at these or any
other conditions above those indicated in the operational
sections of these specification is not implied or intended.
Exposure to the absolute maximum rating conditions for
extended periods may affect device reliability.
Operating Ranges
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, inputs may undershoot VSS to -2.0V for
periods of up to 20ns. Maximum DC voltage on output and
I/O pins is VCC +0.5V. During voltage transitions, outputs
may overshoot to VCC +2.0V for periods up to 20ns.
2. Minimum DC input voltage on A9 pins is -0.5V. During
voltage transitions, A9 and OE may overshoot VSS to -2.0V
for periods of up to 20ns. Maximum DC input voltage on A9
and OE is +12.5V which may overshoot to 13.5V for
periods up to 20ns.
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
Commercial (C) Devices
Ambient Temperature (TA) . . . . ……... . . . . . . . . . 0°C to +70°C
Operating Ranges:
Extended Range Device
Ambient Temperature(TA)………………………..…-40°C to 85°C
VCC Supply Voltages
VCC for ± 10% devices . . . . . . . . . . ………. . . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the device
bus operations, which are initiated through the internal
command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the command.
The contents of the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of the
device. The appropriate device bus operations table lists the
inputs and control levels required, and the resulting output. The
following subsections describe each of these operations in
further detail.
Table 1. A29010 Device Bus Operations
Operation
CE
OE
WE
A0 – A16
I/O0 - I/O7
Read
L
L
H
AIN
DOUT
Write
L
H
L
AIN
DIN
VCC ± 0.5 V
X
X
X
High-Z
TTL Standby
H
X
X
X
High-Z
Output Disable
L
H
H
X
High-Z
CMOS Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
(July, 2012, Version 1.5)
4
AMIC Technology, Corp.
A29010 Series
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the
CE and OE pins to VIL. CE is the power control and selects
the device. OE is the output control and gates array data to the
output pins. WE should remain at VIH all the time during read
operation. The internal state machine is set for reading array
data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is necessary
in this mode to obtain array data. Standard microprocessor read
cycles that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device
remains enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to the AC
Read Operations table for timing specifications and to the Read
Operations Timings diagram for the timing waveforms, lCC1 in
the DC Characteristics table represents the active current
specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE to VIL, and OE
to VIH. An erase operation can erase one sector, multiple
sectors, or the entire device. The Sector Address Tables
indicate the address range that each sector occupies. A "sector
address" consists of the address inputs required to uniquely
select a sector. See the "Command Definitions" section for
details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate
from the memory array) on I/O7 - I/O0. Standard read cycle
timings apply in this mode. Refer to the "Autoselect Mode" and
"Autoselect Command Sequence" sections for more
information.
ICC2 in the Characteristics table represents the active current
specification for the write mode. The "AC Characteristics"
section contains timing specification tables and timing diagrams
for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check
the status of the operation by reading the status bits on I/O7 I/O0. Standard read cycle timings and ICC read specifications
apply. Refer to "Write Operation Status" for more information,
and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE input.
The device enters the CMOS standby mode when the CE is
held at VCC ± 0.5V. (Note that this is a more restricted voltage
range than VIH.) The device enters the TTL standby mode when
CE is held at VIH. The device requires the standard access
time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming, the
device draws active current until the operation is completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
Table 2. A29010 Block Sector Address Table
Sector
A16
A15
Sector Size (Kbytes)
Address Range
SA0
0
0
32
00000h - 07FFFh
SA1
0
1
32
08000h - 0FFFFh
SA2
1
0
32
10000h - 17FFFh
SA3
1
1
32
18000h - 1FFFFh
(July, 2012, Version 1.5)
5
AMIC Technology, Corp.
A29010 Series
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match a
device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed
in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pinA9. Address pins
A6, A1, and A0 must be as shown in Autoselect Codes (High
Voltage Method) table. In addition, when verifying sector
protection, the sector address must appear on the appropriate
highest order address bits. Refer to the corresponding Sector
Address Tables. The Command Definitions table shows the
remaining address bits that are don't care. When all necessary
bits have been set as required, the programming equipment
may then read the corresponding identifier code on I/O7 I/O0.To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register,
as shown in the Command Definitions table. This method does
not require VID. See "Command Definitions" for details on using
the autoselect mode.
Table 3. A29010 Autoselect Codes (High Voltage Method)
Description
A16 - A15 A14 - A10
A9
A8 - A7
A6
A5 - A2
A1
A0
Identifier Code on
I/O7 - I/O0
Manufacturer ID: AMIC
X
X
VID
X
VIL
X
VIL
VIL
37h
Device ID: A29010
X
X
VID
X
VIL
X
VIL
VIH
A4h
Sector
X
VID
X
VIL
X
VIH
VIL
01h (protected)
Sector Protection
Verification
Continuation ID
Address
X
00h (unprotected)
X
VID
X
VIL
X
VIH
VIH
7Fh
Note: CE =VIL, OE =VIL and WE =VIH when Autoselect Mode
(July, 2012, Version 1.5)
6
AMIC Technology, Corp.
A29010 Series
an address within erase-suspended sectors, the device
outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array data
with the same exception. See "Erase Suspend/Erase Resume
Commands" for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
Sector Protection/Unprotection
The hardware sector protection feature disables both program
and erase operations in any sector. The hardware sector
unprotection feature re-enables both program and erase
operations in previously protected sectors.
Sector protection/unprotection must be implemented using
programming equipment. The procedure requires a high
voltage (VID) on address pin A9 and the control pins.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
Hardware Data Protection
Reset Command
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table). In
addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device is
powered up to read array data to avoid accidentally writing
data to the array.
Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data (also
applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to return
to reading array data (also applies to autoselect during Erase
Suspend).
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE , CE or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE =VIL, CE
= VIH or WE = VIH. To initiate a write cycle, CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power up, the device
Autoselect Command Sequence
does not accept commands on the rising edge of WE . The
internal state machine is automatically reset to reading array
data on the initial power-up.
The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
Command Definitions
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
All addresses are latched on the falling edge of WE or CE ,
whichever happens later. All data is latched on the rising edge
of WE or CE , whichever happens first. Refer to the
appropriate timing diagrams in the "AC Characteristics"
section.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated program pulses
and verify the programmed cell margin. The Command
Definitions table shows the address and data requirements for
the byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing
an Embedded Program or Embedded Erase algorithm. After
the device accepts an Erase Suspend command, the device
enters the Erase Suspend mode. The system can read array
data using the standard read timings, except that if it reads at
(July, 2012, Version 1.5)
7
AMIC Technology, Corp.
A29010 Series
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 2 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
no longer latched. The system can determine the status of the
program operation by using I/O7 or I/O6. See "Write Operation
Status" for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Programming is allowed in
any sequence and across sector boundaries. A bit cannot be
programmed from a "0" back to a "1 ". Attempting to do so
may halt the operation and set I/O5 to "1", or cause the Data
Polling algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is still "0".
Only erase operations can convert a "0" to a "1".
START
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements for
the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase timeout of 50μs begins. During the time-out period, additional
sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50μs, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase commands
can be assumed to be less than 50μs, the system need not
monitor I/O3. Any command other than Sector Erase or Erase
Suspend during the time-out period resets the device to
reading array data. The system must rewrite the command
sequence and any additional sector addresses and
commands.
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
WE pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, or I/O2. Refer to "Write Operation
Status" for information on these status bits.
Figure 2 illustrates the algorithm for the erase operation. Refer
to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
Write Program
Command
Sequence
Embedded
Program
algorithm in
progress
Data Poll
from System
Verify Data ?
No
Yes
Increment Address
Last Address ?
Yes
Programming
Completed
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 1. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which in
turn invokes the Embedded Erase algorithm. The device does
not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
(July, 2012, Version 1.5)
8
AMIC Technology, Corp.
A29010 Series
When the device exits the autoselect mode, the device reverts
to the Erase Suspend mode, and is ready for another valid
operation. See "Autoselect Command Sequence" for more
information.
The system must write the Erase Resume command (address
bits are "don't care") to exit the erase suspend mode and
continue the sector erase operation. Further writes of the
Resume command are ignored. Another Erase Suspend
command can be written after the device has resumed
erasing.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a
sector erase operation and then read data from, or program
data to, any sector not selected for erasure. This command is
valid only during the sector erase operation, including the
50μs time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if written
during the chip erase operation or Embedded Program
algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are
"don't cares" when writing the Erase Suspend command.
When the Erase Suspend command is written during a sector
erase operation, the device requires a maximum of 20μs to
suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-out,
the device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all sectors
selected for erasure.) Normal read and write timings and
command definitions apply. Reading at any address within
erase-suspended sectors produces status data on I/O7 - I/O0.
The system can use I/O7, or I/O6 and I/O2 together, to
determine if a sector is actively erasing or is erasesuspended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete, the
system can once again read array data within non-suspended
sectors. The system can determine the status of the program
operation using the I/O7 or I/O6 status bits, just as in the
standard program operation. See "Write Operation Status" for
more information.
The system may also write the autoselect command sequence
when the device is in the Erase Suspend mode. The device
allows reading autoselect codes even at addresses within
erasing sectors, since the codes are not stored in the memory
array.
START
Write Erase
Command
Sequence
Data Poll
from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
Yes
Erasure Completed
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O3 : Sector Erase Timer" for more information.
Figure 2. Erase Operation
(July, 2012, Version 1.5)
9
AMIC Technology, Corp.
A29010 Series
Table 4. A29010 Command Definitions
Sequence
(Note 1)
Bus Cycles (Notes 2 - 4)
Cycles
Command
First
Addr Data
Second
Third
Addr
Data
Addr
Fourth
Data Addr
Fifth
Data
Read (Note 5)
1
RA
RD
Reset (Note 6)
1
XXX
F0
Auto select
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
37
Device ID
4
555
AA
2AA
55
555
90
X01
A4
Continuation ID
4
555
AA
2AA
55
555
90
X03
7F
Sector Protect Verify
4
555
AA
2AA
55
555
90
(Note 7)
(Note 8)
SA
00
X02
01
Sixth
Addr Data
Addr
Data
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (Note 9)
1
XXX
B0
Erase Resume (Note 10)
1
XXX
30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A16 - A15 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A16 - A12 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high (while
the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
10. The Erase Resume command is valid only during the Erase Suspend mode.
11. The time between each command cycle has to be less than 50μs
(July, 2012, Version 1.5)
10
AMIC Technology, Corp.
A29010 Series
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, and I/O7, are provided in the
A29010 to determine the status of a write operation. Table 5
and the following subsections describe the functions of these
status bits. I/O7, I/O6 and I/O2 each offer a method for
determining whether a program or erase operation is complete
or in progress. These three bits are discussed first.
START
Read I/O7-I/O0
Address = VA
I/O7: Data Polling
The Data Polling bit, I/O7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data Polling is
valid after the rising edge of the final WE pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
protected sector, Data Polling on I/O7 is active for
approximately 2μs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data Polling
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data Polling produces a "1" on I/O7.This is analogous to the
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in a
sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on I/O7 is
active for approximately 100μs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0 on
the following read cycles. This is because I/O7 may change
asynchronously with I/O0 - I/O6 while Output Enable ( OE ) is
asserted low. The Data Polling Timings (During Embedded
Algorithms) figure in the "AC Characteristics" section
illustrates this. Table 5 shows the outputs for Data Polling on
I/O7. Figure 3 shows the Data Polling algorithm.
Yes
I/O7 = Data ?
No
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Address = VA
Yes
I/O7 = Data ?
No
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.
Figure 3. Data Polling Algorithm
(July, 2012, Version 1.5)
11
AMIC Technology, Corp.
A29010 Series
I/O6: Toggle Bit I
Reading Toggle Bits I/O6, I/O2
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final WE pulse in the command sequence (prior to the
program or erase operation), and during the sector erase timeout.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
(The system may use either OE or CE to control the read
cycles.) When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100μs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the device
enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O7 (see the subsection on " I/O7 : Data
Polling").
If a program address falls within a protected sector, I/O6
toggles for approximately 2μs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for Toggle
Bit I on I/O6. Refer to Figure 4 for the toggle bit algorithm, and
to the Toggle Bit Timings figure in the "AC Characteristics"
section for the timing diagram. The I/O2 vs. I/O6 figure shows
the differences between I/O2 and I/O6 in graphical form. See
also the subsection on " I/O2: Toggle Bit II".
Refer to Figure 4 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7 - I/O0 at least twice in a row to determine whether a toggle
bit is toggling. Typically, a system would note and store the
value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7 - I/O0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit is
no longer toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the device did
not complete the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5 through
successive read cycles, determining the status as described in
the previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 4).
I/O2: Toggle Bit II
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE pulse in the command sequence.
I/O2 toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may
use either OE or CE to control the read cycles.) But I/O2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer
to Table 6 to compare outputs for I/O2 and I/O6.
Figure 4 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle Bit
Timings figure for the toggle bit timing diagram. The I/O2 vs.
I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form.
(July, 2012, Version 1.5)
12
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and when
the operation has exceeded the timing limits, I/O5 produces a
"1."
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase operation
has begun. (The sector erase timer does not apply to the chip
erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector
erase command. When the time-out is complete, I/O3 switches
from "0" to "1." The system may ignore I/O3 if the system can
guarantee that the time between additional sector erase
commands will always be less than 50μs. See also the "Sector
Erase Command Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O7 ( Data Polling) or I/O6
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
AMIC Technology, Corp.
A29010 Series
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each subsequent
sector erase command. If I/O3 is high on the second status
check, the last command might not have been accepted.
Table 5 shows the outputs for I/O3.
START
Read I/O7-I/O0
Read I/O7-I/O0
Toggle Bit
= Toggle ?
(Note 1)
No
Yes
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Twice
Toggle Bit
= Toggle ?
(Notes 1,2)
No
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O5
changes to "1". See text.
Figure 4. Toggle Bit Algorithm
(July, 2012, Version 1.5)
13
AMIC Technology, Corp.
A29010 Series
Table 5. Write Operation Status
Operation
I/O7
I/O6
I/O5
(Note 1)
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
I/O7
I/O3
(Note 2)
I/O2
(Note 1)
Toggle
0
N/A
No toggle
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Data
Data
Data
Data
Data
Toggle
0
N/A
N/A
Reading within Non-Erase
Suspend Sector
Erase-Suspend-Program
I/O7
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See
“I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
(July, 2012, Version 1.5)
20ns
14
AMIC Technology, Corp.
A29010 Series
DC Characteristics
TTL/NMOS Compatible
Parameter
Parameter Description
Test Description
Min.
Typ.
Max.
Unit
Symbol
ILI
ILIT
Input Load Current
VIN = VSS to VCC. VCC = VCC Max
±1.0
μA
A9 & OE Input Load Current
VCC = VCC Max,
100
μA
±1.0
μA
A9 & OE = 12.5V
ILO
ICC1
Output Leakage Current
VOUT = VSS to VCC. VCC = VCC Max
VCC Active Read Current
CE = VIL, OE = VIH
20
30
mA
CE = VIL, OE =VIH
30
40
mA
CE = VIH
0.4
1.0
mA
-0.5
0.8
V
2.0
VCC+0.5
V
10.5
12.5
V
0.45
V
(Notes 1, 2)
ICC2
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)
ICC3
VCC Standby Current (Note 2)
VIL
Input Low Level
VIH
Input High Level
VID
Voltage for Autoselect
VCC = 5.25 V
VOL
Output Low Voltage
IOL = 12mA, VCC = VCC Min
VOH
Output High Voltage
IOH = -2.5 mA, VCC = VCC Min
2.4
V
CMOS Compatible
Parameter
Parameter Description
Test Description
Min.
Typ.
Max.
Unit
μA
Symbol
ILI
ILIT
Input Load Current
VIN = VSS to VCC, VCC = VCC Max
±1.0
A9 & OE Input Load Current
VCC = VCC Max,
100
A9 & OE = 12.5V
ILO
Output Leakage Current
ICC1
VCC Active Read Current
±1.0
VOUT = VSS to VCC, VCC = VCC Max
CE = VIL, OE = VIH
20
30
CE = VIL, OE = VIH
30
40
CE = VCC ± 0.5 V
1
5
(Notes 1,2)
ICC2
VCC Active Program/Erase Current
(Notes 2,3,4)
μA
μA
mA
mA
μA
ICC3
VCC Standby Current (Notes 2, 5)
VIL
Input Low Level
VIH
Input High Level
VID
Voltage for Autoselect
VCC = 5.25 V
VOL
Output Low Voltage
IOL = 12.0 mA, VCC = VCC Min
VOH1
Output High Voltage
IOH = -2.5 mA, VCC = VCC Min
0.85 x
VCC
V
IOH = -100 μA. VCC = VCC Min
VCC-0.4
V
VOH2
-0.5
0.8
V
0.7 x VCC
VCC+0.3
V
10.5
12.5
V
0.45
V
Notes for DC characteristics (both tables):
1. The ICC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Not 100% tested.
5. For CMOS mode only, ICC3 = 20μA max at extended temperatures (> +85°C).
(July, 2012, Version 1.5)
15
AMIC Technology, Corp.
A29010 Series
AC Characteristics
Read Only Operations
Parameter Symbols
Description
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 2)
tAVQV
tACC
Address to Output Delay
Speed
Test Setup
CE = VIL
Unit
-55
-70
-90
Min.
55
70
90
ns
Max.
55
70
90
ns
Max.
55
70
90
ns
OE = VIL
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
Output Enable to Output Delay
Max.
30
30
35
ns
tOEH
Output Enable Hold
Read
Min.
0
0
0
ns
Toggle and
Min.
10
10
10
ns
Max.
18
20
20
ns
18
20
20
ns
0
0
0
ns
Time (Note 2)
OE = VIL
Data Polling
tEHQZ
tDF
Chip Enable to Output High Z
tGHQZ
tDF
Output Enable to Output High Z
tAXQX
tOH
Output Hold Time from Addresses,
CE or OE , Whichever Occurs First
Min.
Notes:
1. Output driver disable time.
2. Not 100% tested.
Timing Waveforms for Read Only Operation
tRC
Addresses
Addresses Stable
tACC
CE
tDF
tOE
OE
tOEH
WE
tCE
tOH
High-Z
Output
Output Valid
High-Z
0V
(July, 2012, Version 1.5)
16
AMIC Technology, Corp.
A29010 Series
AC Characteristics
Erase and Program Operations
Description
Parameter
Symbols
Unit
Speed
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
tAVWL
tAS
Address Setup Time
Min.
tWLAX
tAH
Address Hold Time
Min.
40
45
45
ns
tDVWH
tDS
Data Setup Time
Min.
25
30
45
ns
tWHDX
tDH
Data Hold Time
Min.
0
ns
tOES
Output Enable Setup Time
Min.
0
ns
Read Recover Time Before Write
Min.
0
ns
tGHWL
tGHWL
-55
-70
-90
55
70
90
0
ns
ns
( OE high to WE low)
tELWL
tCS
CE Setup Time
Min.
0
ns
tWHEH
tCH
CE Hold Time
Min.
0
ns
tWLWH
tWP
Write Pulse Width
Min.
tWHWL
tWPH
Write Pulse Width High
30
35
45
ns
Min.
20
ns
Max.
50
μs
tWHWH1
tWHWH1
Byte Programming Operation
(Note 2)
Typ.
7
μs
tWHWH2
tWHWH2
Sector Erase Operation
(Note 2)
Typ.
1
sec
VCC Set Up Time (Note 1)
Min.
50
μs
tVCS
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
(July, 2012, Version 1.5)
17
AMIC Technology, Corp.
A29010 Series
Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
PA
555h
PA
tAH
PA
~
~ ~
~
Addresses
tAS
~
~
tWC
Read Status Data (last two cycles)
CE
tCH
~
~
tGHWL
OE
tWP
~
~
tWHWH1
WE
tCS
tWPH
A0h
Data
tDH
PD
~
~
tDS
Status
DOUT
~
~
tVCS
VCC
Note : PA = program addrss, PD = program data, Dout is the true data at the program address.
(July, 2012, Version 1.5)
18
AMIC Technology, Corp.
A29010 Series
Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
tAS
~
~
tWC
SA
2AAh
VA
555h for chip erase
tAH
VA
~
~ ~
~
Addresses
Read Status Data
CE
~
~
tGHWL
tCH
OE
~
~
tWP
WE
tWPH
tWHWH2
tCS
tDH
55h
Data
In
Progress
Complete
10h for chip erase
~
~
tVCS
30h
~
~
tDS
VCC
Note : SA = Sector Address. VA = Valid Address for reading status data.
(July, 2012, Version 1.5)
19
AMIC Technology, Corp.
A29010 Series
Timing Waveforms for Data Polling (During Embedded Algorithms)
Addresses
~
~
tRC
VA
~
~ ~
~
tAC
C
CE
VA
VA
tCE
tCH
~
~
tOE
OE
tDF
~
~
tOEH
WE
tOH
I/O0 - I/O6
Status Data
High-Z
~
~
Complement
Complement
True
Valid Data
~
~
I/O7
Status Data
True
Valid Data
High-Z
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
Addresses
~
~
tRC
VA
VA
~
~ ~
~
tACC
CE
VA
VA
tCE
tCH
tOE
tOEH
~
~ ~
~
OE
tDF
WE
I/O6 , I/O2
Valid Status
Valid Status
(first read)
(second read)
~
~
tOH
Valid Status
Valid Status
(stop togging)
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
(July, 2012, Version 1.5)
20
AMIC Technology, Corp.
A29010 Series
Timing Waveforms for I/O2 vs. I/O6
~
~
~
~
~
~
~
~
~
~
~
~
Erase
Complete
~
~
~
~
Erase
~
~
I/O2
Erase Suspend
Read
~
~
I/O6
Erase
Suspend
Program
Erase Suspend
Read
~
~
Erase
Erase
Resume
~
~
WE
Enter Erase
Suspend Program
~
~
~
~
Erase
Suspend
~
~
Enter
Embedded
Erasing
I/O2 and I/O6 toggle with OE and CE
Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Statue" for
more information.
AC Characteristics
Erase and Program Operations
Alternate CE Controlled Writes
Description
Parameter Symbols
Unit
Speed
JEDEC
Std
-55
-70
-90
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
tAVEL
tAS
Address Setup Time
Min.
55
70
90
tELAX
tAH
Address Hold Time
Min.
40
45
45
ns
tDVEH
tDS
Data Setup Time
Min.
25
30
45
ns
tEHDX
tDH
Data Hold Time
Min.
0
ns
ns
0
ns
tGHEL
tGHEL
Read Recover Time Before Write
Min.
0
ns
tWLEL
tWS
WE Setup Time
Min.
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
ns
tELEH
tCP
Write Pulse Width
Min.
30
35
45
ns
tEHEL
tCPH
Write Pulse Width High
Min.
20
20
20
ns
tWHWH1
tWHWH1
Byte Programming Operation (Note 2)
Typ.
7
μs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ.
1
sec
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
(July, 2012, Version 1.5)
21
AMIC Technology, Corp.
A29010 Series
Timing Waveforms for Alternate CE Controlled Write Operation
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
~
~
Data Polling
PA
~
~
Addresses
tWC
tAS
tAH
~
~
tWH
WE
~
~
tGHEL
OE
tWHWH1 or 2
~
~
tCP
tBUSY
tCPH
CE
tWS
tDS
~
~
tDH
Data
I/O7
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Typ. (Note 1)
Max. (Note 2)
Unit
Comments
Sector Erase Time
1
8
sec
Chip Erase Time
8
64
sec
Excludes 00h programming prior to
erasure (Note 4)
Byte Programming Time
35
300
μs
Chip Programming Time (Note 3)
3.6
10.8
sec
Excludes system-level overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5V (4.75V for -55), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program
faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device
set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4 for
further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
(July, 2012, Version 1.5)
22
AMIC Technology, Corp.
A29010 Series
Latch-up Characteristics
Description
Input Voltage with respect to VSS on all I/O pins
VCC Current
Input voltage with respect to VSS on all pins except I/O pins
(including A9 and OE )
Min.
Max.
-1.0V
VCC+1.0V
-100 mA
+100 mA
-1.0V
12.5V
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.
TSOP Pin Capacitance
Parameter Symbol
CIN
Parameter Description
Test Setup
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Typ.
Max.
Unit
VIN=0
6
7.5
pF
VOUT=0
8.5
12
pF
VIN=0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
PLCC and P-DIP Pin Capacitance
Parameter Symbol
CIN
Parameter Description
Test Setup
Input Capacitance
Typ.
Max.
Unit
VIN=0
4
6
pF
COUT
Output Capacitance
VOUT=0
8
12
pF
CIN2
Control Pin Capacitance
VPP=0
8
12
pF
Notes:
3. Sampled, not 100% tested.
4. Test conditions TA = 25°C, f = 1.0MHz
Data Retention
Parameter
Minimum Pattern Data Retention Time
(July, 2012, Version 1.5)
23
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
AMIC Technology, Corp.
A29010 Series
Test Conditions
Test Specifications
Test Condition
-55
All others
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
20
ns
Input Pulse Levels
0.0 - 3.0
0.45 - 2.4
V
Input timing measurement reference levels
1.5
0.8, 2.0
V
Output timing measurement reference levels
1.5
0.8, 2.0
V
Test Setup
5.0 V
2.7 KΩ
Device
Under
Test
CL
(July, 2012, Version 1.5)
Diodes = IN3064 or Equivalent
6.2 KΩ
24
AMIC Technology, Corp.
A29010 Series
Ordering Information
Part No.
Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (μA)
Package
A29010-55F
32Pin Pb-Free DIP
A29010L-55UF
32Pin Pb-Free PLCC
A29010L-55F
55
20
30
1
32Pin Pb-Free PLCC
A29010V-55UF
32Pin Pb-Free TSOP
A29010V-55F
32Pin Pb-Free TSOP
A29010-70F
32Pin Pb-Free DIP
A29010L-70UF
32Pin Pb-Free PLCC
A29010L-70F
70
20
30
1
32Pin Pb-Free PLCC
A29010V-70UF
32Pin Pb-Free TSOP
A29010V-70F
32Pin Pb-Free TSOP
A29010-90F
32Pin Pb-Free DIP
A29010L-90UF
32Pin Pb-Free PLCC
A29010L-90F
90
20
30
1
32Pin Pb-Free PLCC
A29010V-90UF
32Pin Pb-Free TSOP
A29010V-90F
32Pin Pb-Free TSOP
Note: -U is for industrial operating temperature range.
(July, 2012, Version 1.5)
25
AMIC Technology, Corp.
A29010 Series
Package Information
P-DIP 32L Outline Dimensions
unit: inches/mm
D
17
1
16
E
32
A1
A2
Base Plane
Seating Plane
L
A
C
E1
B
θ
e
B1
Symbol
Dimensions in inches
Min
Nom
Max
EA
Dimensions in mm
Min
Nom
Max
A
-
-
0.210
-
-
5.334
A1
0.015
-
-
0.381
-
-
A2
0.149
0.154
0.159
3.785
3.912
4.039
B
-
0.018
-
-
0.457
-
B1
-
0.050
-
-
1.270
-
C
-
0.010
-
-
0.254
-
D
1.645
1.650
1.655
41.783
41.91
42.037
E
0.537
0.542
0.547
13.64
13.767
13.894
E1
0.590
0.600
0.610
14.986
15.240
15.494
EA
0.630
0.650
0.670
16.002
16.510
17.018
e
-
0.100
-
-
2.540
-
L
0.120
0.130
0.140
3.048
3.302
3.556
0°
-
0°
-
15°
θ
15°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
(July, 2012, Version 1.5)
26
AMIC Technology, Corp.
A29010 Series
Package Information
PLCC 32L Outline Dimension
unit: inches/mm
θ
Symbol
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.134
-
-
3.40
A1
0.0185
-
-
0.47
-
-
A2
0.105
0.110
0.115
2.67
2.80
2.93
b1
0.026
0.028
0.032
0.66
0.71
0.81
b
0.016
0.018
0.021
0.41
0.46
0.54
C
0.008
0.010
0.014
0.20
0.254
0.35
D
0.547
0.550
0.553
13.89
13.97
14.05
E
0.447
0.450
0.453
11.35
11.43
11.51
e
0.044
0.050
0.056
1.12
1.27
1.42
GD
0.490
0.510
0.530
12.45
12.95
13.46
GE
0.390
0.410
0.430
9.91
10.41
10.92
HD
0.585
0.590
0.595
14.86
14.99
15.11
HE
0.485
0.490
0.495
12.32
12.45
12.57
L
0.075
0.090
0.095
1.91
2.29
2.41
y
-
-
0.003
-
-
0.075
0°
-
0°
-
10°
θ
10°
Notes:
1. Dimensions D and E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
(July, 2012, Version 1.5)
27
AMIC Technology, Corp.
A29010 Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
A
A1
c
E
A2
e
D
θ
L
LE
HD
Detail "A"
D
Detail "A"
y
S
Symbol
Dimensions in inches
Min
Nom
Max
b
Dimensions in mm
Min
Nom
Max
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.041
0.95
1.00
1.05
b
0.007
0.009
0.011
0.18
0.22
0.27
c
0.004
-
0.008
0.11
-
0.20
D
0.720
0.724
0.728
18.30
18.40
18.50
E
-
0.315
0.319
-
8.00
8.10
e
0.020 BSC
0.50 BSC
HD
0.779
0.787
0.795
19.80
20.00
20.20
L
0.016
0.020
0.024
0.40
0.50
0.60
LE
-
0.032
-
-
0.80
-
S
-
-
0.020
-
-
0.50
y
-
-
0.003
-
-
0.08
θ
0°
-
5°
0°
-
5°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(July, 2012, Version 1.5)
28
AMIC Technology, Corp.
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement