Fully Integrated Ballast Controller with Digital

Fully Integrated Ballast Controller with Digital
Fully Integrated Ballast Controller with
Digital Phase Control
Yan Yin, Mariko Shirazi, Regan Zane
Colorado Power Electronics Center
University of Colorado at Boulder
Boulder, CO 80309-0425
[email protected]
Abshuct - An integrated b a h t controller fabricated in P
0.8 um CMOS process is presented that includes digital phase
control, current regulation and soft-start ignition. The primarily
digital approach provides programmability for broad
application, insensitivity to process and temperature variations,
and few external components. Experimental results are provided
for a 500 W HID electronic ballast.
Key words: electronic ballast, digital, phase control, integrated
circuit, current regnbtion, over voltageprotecfion
I. INTRODUCTION
High frequency electronic ballasts are used to provide
stable ac drive to a variety of discharge lamps. In many cases,
different lamp technologies and applications require unique
operating modes and conditions for lamp ignition, normal
operation, dimming, and protection [l-51. In this paper we
present a fully integrated ballast controller developed to
provide the most c o m o n control features in a single low-cost
CMOS IC, including programmable ignition and transition to
n o m 1 operation, ac lamp current regulation, over-voltage
protection and dimming control. The controller is designed to
operate independently for many applications (e.g. standard and
dimming linear and compact fluorescent lamps (LFL and
CFL)). In addition, the IC provides a simple digital interface
for communication with a lamp controller for more specialized
applications (e.g. high intensity discharge (HID)lamp control
with hot re-strike protection and outer-loop power regulation).
The custom IC can interface with any standard low-cost IC
(e.g. micro-controller or programmable logic (CPLD or
FPGA)) for specialized lamp control functions. The digital
interface provides the external controller with sampled
information on the ac lamp current and voltage and receives
current reference and startup setting commands. The overall IC
architecture was designed for application to a broad range of
lamp technologies in order to leverage high volumes for low
cost CMOS processing, while limiting the overhead associated
with more specialized requirements.
phase control have been discussed in [5-8],and the approach
for direct digital phase control was presented in [9,10]. The
controller provides self-tuning to the ballast resonant
frequency, guaranteed operation above resonance, and
simplified dynamics for current regdation [ll]. The design is
capable of phase regulation over a frequency range from
30 kHz to 300 kHz, which allows the same controller and
settings to work properly with a wide range of ballast designs
and lamp technologies. The outer control loop provides ac
lamp current sensing and regulation for lamp ignition and
dimming control. Buffered ac sensing of phase and lamp
current and voltage facilitate fast detection, improved
efficiency and lower cost by removing external rectifying
diodes and filtering. The primarily digital approach provides
programmability for broader application, insensitivity to
process and temperature variations, few external components,
and ease of re-use and adaptation to other platforms and IC
technologies.
The core of the controller is based on two control loops,
with a simplified diagram shown in Fig. 1. The inner loop is
based on a direct digital phase controller that provides near
cycle-by-cycle phase regulation. Benefits and approaches for
This work is co-sponsored by the National Science Foundation (under Grant
No. 0348772), General Electric Global Research (through CoPEC) and the
Department of Energy's National Energy Technology Laboratory (under
Cooperative Agreement DE-FC26-02NT41252).
0-7803-8975-1/05/$20.00
92005 IEEE.
1065
T
id
J
-I
I
shase
ntroller
-
I I
I
I
zero-crossin
detector
envelope
detector
compensator
Figure 1. Simplified block diagram of the two primary control loops in
the ballast IC: ( I ) inner phase control and (2) outer lamp current
regulation.
Section I1 of the paper provides a detailed description of
the custom IC architecture and design. Experimental results are
presented in Section 111 demonstrating the performance
capabilities and limitations of the IC hnctional blocks together
with an application example for a 400 W HID ballast. Our
conclusions arc sumniarized in Section IV.
11. INTEGRATED BALLASTCONTROLLER ARCHITECTURE
AND
DESIGN
Figure 2 shows a simprified block diagram of the core
blocks in the integrated ballast controller. The inner dashed
box contains the core digital controller while the outer dashed
box contains the analog interface functions.
A . Digital Control Blocks
The core digital controller of the IC receives zero crossing
information on the inductor current, samples of the ac lamp
current and voltage, low side gate drive feedback, and a digital
reference current command, and outputs the high and low side
gate drive signals and a shutdown signal for protection. The
ballast control can be considered to operate in two modes:
Lamp Ignition and Lamp Current Regulation. During lamp
ignition, the digitally controlled oscillator (DCO) module
guarantees initial operation to enable phase detection and
regulation. The stariup module then sweeps the phase from a
high to a low value until the lamp ignites. Once the lamp
ignites, the peak detector and compensator modules implement
the digital current regulation loop. The over-voltage protection
module monitors lamp voltage and shuts down the lamp should
the voltage exceed a programmable limit. Although this
module is active at all times, it is particularly relevant during
lamp ignition and in the event of a lamp failure.
The phase controller is active during both lamp ignition
and lamp current regulation, regulating the phase angle
between inductor current and midpoint voltage and providing
supervisory timing functions for synchronization of analog-todigital ( A D ) conversion sampling, lamp current peak
detection, and lamp current compensation. The phase
command for the phase controller is provided by the startup
module during lamp ignition @hase sweep) and by the
compensator during lamp current regulation. Each of the core
blocks active during lamp ignition and current regulation are
described in more detail below.
A . I : Digital Phase Controller
The direct digital phase control concept, strategy and
discrete hardware verification were presented in [9,10]. The
key concept and control algorithm for realization are briefly
reviewed here.
t
I
I
I
I
I
I
I
DIGITAL CONTROL
;
ANALOG INTERFACE
Figure 2. Black diagram for the custom IC ballast controller.
1066
1
I
I
The control algorithm based on Fig. 2 i s implemented in the
state machine of Fig. 4. The phase controller provides a onceper-cycle pulse based on inductor current positive zero crossing
detection to synchronize the peak detector and compensator
and a higher frequency synchronized clock for the A D
converter.
When the LCC resonant inverter of Fig. 1 is operated above
resonance, the resonant inductor dominates the resonant tank
and thus the inductor current iL lags the mid-point voltage v,
from 0" to 90" as the switching frequency shifts away from
resonance. The output power decreases as the frequency
increases above the resonant frequency and the phase angle
between mid-point voltage and inductor current increases from
0" to 90". Thus the output power can be regulated by
controlling the phase angle between the mid-point voltage and
the inductor current. The benefits of phase control over
frequency controi have been described in [5-8,111. By
controlling the inductor current phase angle to be greater than
0", the system will be forced to operate above resonance,
resulting in zero voltage switching (ZVS) operation for
appropriately designed resonant tanks. Furthermore, if the
resonant frequency shifts due to variations of the tank elements
and load, the phase controller will self-tune to the resonant
frequency on a near cycle-by-cycle basis and the operating
point will not be affected. Finally, phase control simplifies the
lamp current regulation dynamics by converting the 2-pole
response obtained using frequency control into a single-pole
response [ 113.
n
A
Figure 4 . State machine for phase controller
hrrn offHSgate
ram on LS gate
Figure 3. Phase control using inductor current and mid-point voltage in a
half-bridge LCC resonant inverter
The basic strategy to directly control the inductor current
phase is illustrated in Fig. 3. The essence of the control is to
time the period by detecting the inductor current zero crossing,
then compute the required time delays from the zero crossing
to determine when to him on or off the high and low side gate
drives to achieve the desired phase. Given a phase command,
the time delay from the zero crossing of the inductor current to
the falling edge of the mid-point voltage can be computed as
-
T,, [n- 11
9
(1)
where 0 5 al[n]_< 2"-1, m is the number of bits of the digital
phase command, al[nJ = 0 corresponds to -0" while
a,[n]= 2m - 1 corresponds to -go", and Tgdn-l] is the gate
drive delay of the previous cycle (used to compensate phase
errors due to gate drive delay [lo]).
A . 2 : Lamp Ignition
The DCO, startup, and over-voltage protection modules are
active during lamp ignition. When the controller is first
powered up, it will operate in DCO at a programmable
frequency for 10 ms. This is followed by the phase sweep.
Once the peak lamp current exceeds a specified threshold
(ipk> i,,), the lamp current compensator takes over, The start
phase, minimum phase, sweep rate, and threshold current are
all programmable. The minimum phase setting is used to
protect the ballast (in addition to over-voltage protection) and
avoid zero voltage switching. Figure 5 shows a block diagram
of the startup module which performs the phase sweep. The
start phase and minimum phase parameters, which define start
and end values for the phase sweep, are not shown in the
figure. The startup controller also includes the multiplexer
which determines whether the phase command is to be
provided from the phase sweep or the compensator.
Should the startup module reach minimum phase without
lamp current exceeding the threshold, the ballast controller will
drop back into DCO and repeat the ignition sequence. In the
case of an over-voltage, the controller will likewise drop back
into DCO and repeat the ignition sequence, as well as send a
shutdown signal to the gate driver. Thus high voltage ignitions
are avoided - the sweep is repeated multiple times until the
lamp ignites at a sufficiently IOW voltage.
1067
Figure 5. Block diagram ofthe startup conlroller,which sweeps phase
from 90a toward 0"
Figure 8. Block diagram of the startup controller combined with the
compensator for smooth transitions between operating modes
larch
This solution achieves a smooth transfer from phase sweep
ignition to lamp current regulation modes by forcing the output
of the compensator to be the same as the output of the phase
sweep during startup.
cycle-elk
B. Analog Interface Blocks
The core analog interface blocks are the current-mode ac
buffer, current-mode comparator, and current-mode AID
converter. The current-mode ac buffer was used to provide
direct sensing of both positive and negative voltages (either
single-ended or differential) with only one or two extemal
resistors, eliminating off-chip rectifying diodes and filtering
circuitry. The basic buffer structure is shown in Fig. 9,
configured for a single-ended input. The buffer provides an
output current proportional to the driving voltage and matched
extemal resistors R (based on two operational transconductance
Figure 6. Block diagram of the peak detector, which latches the peak
lamp current in each switching cycle
1.1
truncal
(~51I7:01,
amplifiers (OTAs)). The OTAs were implemented using folded
cycle-clk
cascode techniques. For the single-ended input configuration,
the relationship for ideal OTAs is
1,"* -I,
Figure 7. B[ock diagram of the compensator block, which provides integral
compensation to the lamp current regulation loop
A.3: Lamp Current Regulation
Figures 6 and 7 show block diagrams of the peak detector
and compensator, respectively. The compensator is a simple
integral only compensator with programmable gain. Both the
peak detector output and compensator delay are latched by the
once-per-cycle pulsr:, cycle-ck, from the phase controller.
Although not shown in Fig. 7, the programmable minimum
phase parameter is used by the compensator as well as the startup module. Should the phase error be sufficient to cause the
output of the compensator to reach minimum phase, the phase
command will remain at minimum phase until the phase error
decreases again.
.
-1,
.
=--.v,
R
For inductor current zero-crossing detection, a simple
current-mode comparator follows the buffer. This comparator
One problem with implementing the compensator of Fig. 7
separately from the startup controller (including multiplexer) o f
Fig. 5 is the potential for large steps in phase command when
switching from the start-up phase sweep to current regulation.
To address this problem, the start-up controller and
compensator were combined into one module shown in Fig. 8.
1068
I
R
Figure 9. Analog ac buffer block diagram
&biz I-mode
hold
Figure IO. Block diagram for current-modeAID conversion
is based on the high speed current-mode approach proposed in
[12]. The output of the comparator is a square wave with a
rising edge synchronous to the positive zero crossing of the
inductor current waveform. This signal is used by the phase
controller to determine the switching period.
For lamp current and voltage A/I) conversion, the output
current is piped through a channel including analog current
mode rectification (to simplify A/D), sample & hold, and an
asynchronous pipelincd A/D converter, as shown in Fig. 10.
I
Currenr Mirror
I
Figure 12. First two MSBs of the asynchronous pipe-tined A/D converter
111. EXPERIMENTAL RESULTS AND HID APPLICATION
EXAMPLE
The complete ballast controller IC of Fig. 3 was fabricated
in a low-cost 0.8 p n CMOS process, with the IC layout shown
in Fig. 13. The controller performance was evaluated on an
experimental 400 W HID ballast with a startup frequency of
200 ldlz and fill power operation at 140kHz. The
experimental setup is shown in Fig. 14.
Dlgitd
r---t--1
COUb1
Functions
P
An&
Inreflace
Figure 13. Photograph of the integrated ballast controller,
measuring 4 m m x 3 m m
Figure 1 I . Simplified conceptual diagram of the current-mode rectifier
A conceptual block diagram of the current-mode rectifier is
shown in Fig. 11. The current-mode sample & hold circuit is
based on a comp tete clock-feedthrough (CFT) cancellation
approach as described in [13]. The S%H block samples the
full-wave rectified current with a sampling frequency of 16 or
32 times ballast frequency, based on the synchronized clock
ARC-clk from the phase controller. This ensures that exactly
l 6 or 32 samples o f output waveforms are taken in each
switching period, despite variations in switching frequency.
Thc 6-bit current-mode A/D is realized using an
asynchronous pipelined structure, as shown in Fig. 12 for the
first two MSBs. The input current to each stage is compared to
% the reference current to get the digital output for that bit. If
the input current is greater than Yi the reference current, the bit
will be on, and X the reference current is subtracted from the
input current, the result i s multiplied by two, and then passed to
the next stage. If the input current is less than !4 the reference
current, the bit will be off, and the input current is directly
multiplied by two and then passed to the next stage.
1069
Figure 14. Experimental setup for 400 W HID ballast demonstratlon
Lamp Current AIO Conversion
16X rampling (2.7 MHz)
TO
I
I
I
1
Lamp Current
I
I
1.
I
0
a
2
4
0
8
Actual C u r "
io
I2
[A]
Figure 15. Digital output vs. analog input for the lamp current A/D
converter clocked at 16 times the ballast frequency
A . IC Limitations
Testing of the integrated ballast controller verified all
digital functions. However, it also revealed limitations in the
analog interface. One is that the ac buffer introduces an offset
into the current output. This problem was overcome by
injecting current into the ac buffer to compensate for the offset.
The second limitation is that the A/D converter contains a "flat
spot" - i.e. a range over which the digital output remains
constant as the anatog input changes. This is shown in Fig. 15
for the lamp current N D converter. When the analog input
reaches a value suflicient to produce a raw digital output of
31d= 1Fh (d: decimal, h:hex), the output will remain at 1Fh
until the input is increased to a value sufficient to produce a
raw digital output of 23h, at which point the digital output will
then jump to this value. The data for this plot was collected
with the S&H sampling at 16 times the ballast frequency
(approximately 2.7 MHz in this case). The same results were
obtained when the A/D converter was clocked externally using
a 10 kHz clock, verifying that this problem is sample-rate
independent. Fortunately, this has no effect unless operating in
this region, which, for lamp current, is above rated power.
The final limitation is that some noise is present in the
current-mode A/D converter, resulting in occasional spikes in
the digital output word. These spikes do not significantly
affect lamp current regulation since they happen infrequently
(on the order of 1 in lOOO), however they do adversely effect
over-voltage protection. Spikes introduced by the lamp voltage
AID converter caused the control chip to send one-clock-cycle
shutdown pulses to the gate driver chip. Therefore, it was
necessaIy to use an extemal comparator, as shown in Fig. 14,
to provide over-voltage protection.
Future versions of the IC will address any A/D converter
layout issues which may be causing the non-linearity and noise
problems of the converter. IR addition, digital averaging or
logic will be used to remove outliers from the latched values.
B. Experimental Waveforms
Figure 16 shows steady-state operation of the lamp at near
rated power. The phase error between commanded phase and
actual phase is approximately 3". Figure 17 shows an ignition
sequence with operating modes labeled. Once the lamp ignites,
it goes through a very short glow-to-arc phase, followed by a
I
loductor Curront
7
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.
Lamp Current Regulation
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. M#ms5owb: 2wru&i
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".
Figure 17. HID lamp ignition sequence with operating modes labeled
VM = 300 V, Current Reference = 4.8 A
warm-up period. During warm-up, the regulator maintains
near constant current despite changes to the lamp impedance.
Figure 18 shows a detail view of the challenging lamp
dynamics during the glow-to-arc phase. The lamp current
initially contains higher order harmonics and oscillates between
rectifying behavior prior to stable arc operation. The phase
controller is unaffected by these dynamics as it tracks constant
phase despite variations in the tank input impedance. Changes
in the frequency of the midpoint voltage are observed as the
phase controller maintains an approximately constant phase
(due to the small compensator gain used, the phase command is
held approximately constant over the several cycles shown). It
should be noted that during the glow-to-arc operating
conditions, the lamp current peaks are not a good
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Lamp Current
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F i p 18 HID lamp glow-to-arc dynamics In the first
few cycles after ignitlon
representation of the lamp R M S current.
A simple
improvement would be to perform a cycle-by-cycle average of
the rectified current waveform as a closer approximation to the
RMS value with relatively little processing overhead. This
would provide higher currents during initial operation and
could help to force the lamp out of the glow-to-arc mode more
quickly. Finally, Fig. 19 demonstrates over-voltage protection
operation with the over-voltage limit set near 3,500 V As
shown, the ballast controller repeats ignition sequence
indefinitely until the lamp can ignite below the over-voltage
limit.
Figure 19. Repeated ignition attempts of HID lamp
with over-voltage protection near 3,500 V
[4]
IV. CONCLUS[ONS
We have presented design details and expenmental results
for a fully integrated ballast controller based on digital phase
control. Functional blocks of the custom IC include
programmable ignition and transition to normal operation, ac
lamp current regulation, over-voltage protection and dimming
control. Phase controt provides self-tuning to the ballast
resonant frequency, guaranteed operation above resonance, and
simplified dynamics for current regulation. The primarily
digital approach provides programmability for broader
application, insensitivity to process and temperature vmations,
few external components, and ease of re-use and adaptation to
other platforms and IC technologies. Experimental results are
provided demonstrating IC operation in a 400 W HID ballast
application.
[5]
[6]
[7]
[SI
[9]
[IO]
[I I ]
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