DS821

DS821
LogiCORE IP 7 Series FPGAs
Integrated Block v1.2
for PCI Express
DS821 October 19, 2011
Product Specification
Introduction
LogiCORE IP Facts Table
The LogiCORE™ IP 7 Series FPGAs Integrated Block
for PCI Express® core is a high-bandwidth, scalable,
and reliable serial interconnect building block for use
with Xilinx® 7 Series FPGA families. The Integrated
Block for PCI Express (PCIe®) solution supports 1-lane,
2-lane, 4-lane, and 8-lane Endpoint configurations at up
to 5 Gb/s (Gen2) speeds, all of which are compliant
with the PCI Express Base Specification, rev. 2.1. This
solution supports the AXI4-Stream interface for the
customer user interface.
PCI Express offers a serial architecture that alleviates
many of the limitations of parallel bus architectures by
using clock data recovery (CDR) and differential
signaling. Using CDR (as opposed to source
synchronous clocking) lowers pin count, enables
superior frequency scalability, and makes data
synchronization easier. The layered architecture of PCI
Express provides for future attachment to copper,
optical, or emerging physical signaling media. PCI
Express technology, adopted by the PCI-SIG® as the
next generation PCI, is backward-compatible to the
existing PCI software model.
With higher bandwidth per pin, low overhead, low
latency, reduced signal integrity issues, and CDR
architecture, the Integrated Block for PCIe sets the
industry
standard
for
a
high-performance,
cost-efficient, third-generation I/O solution.
The Integrated Block for PCI Express solution is
compatible with industry-standard application form
factors such as the PCI Express Card Electromechanical
(CEM) v2.0 and the PCI Industrial Computer
Manufacturers Group (PICMG) 3.4 specifications.
Core Specifics
Supported
Device Family (1)
Virtex-7, Kintex-7
Minimum
Device
XC7K30T-1 (2)
Supported User
Interfaces
AXI4-Stream
Resources
Special
Features
See Table 1
GTXE2 Transceivers,
7 Series FPGA Integrated Block for PCI Express,
Virtex-7/Kintex-7 FPGA Mixed-Mode Clock
Manager (MMCM), Block RAM
Provided with Core
Product Specification
User Guide
Instantiation Template
Documentation
Design Files
Verilog/VHDL (3) RTL Source and Simulation
Models
Verilog/VHDL Test Bench,
Verilog/VHDL Example Design
Example Design
Verilog, VHDL
Test Bench
Verilog, VHDL
Constraints File
User Constraints File (UCF)
Simulation
Model
Verilog, VHDL
Tested Design Tools
Design Entry
Tools
ISE 13.3
Simulation (4)
Cadence Incisive Enterprise Simulator (IES)
Synopsys VCS and VCS MX
Mentor Graphics ModelSim
Synthesis Tools
XST 13.3
Support
Provided by Xilinx @ www.xilinx.com/support
1. For a complete listing of supported devices, see the release notes
for this core.
2. Designs needing 8-lane operation with 5 Gb/s (Gen2) speeds must
use the 128-bit version of the product and a -2 or -3 speed grade
device.
3. RTL source for the GTX wrapper is Verilog only. VHDL projects
require mixed language mode simulators.
4. For a listing of the supported tool versions, see the ISE Design
Suite 13: Release Note Guide.
© Copyright 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in
the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective
owners.
DS821 October 19, 2011
Product Specification
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1
LogiCORE IP 7 Series FPGAs Integrated Block v1.2 for PCI Express
Table 1: Resources Used
Interface
Width
GTXE1
LUT (1)
FF (2)
1-lane
Gen1/Gen2 (3)
64-bit
1
400
575
2-lane Gen1/Gen2
64-bit
2
525
750
4-lane Gen1
64-bit
4
800
1100
4-lane Gen2
64-bit,
128-bit
4
800
1300
8-lane, Gen1
64-bit,
128-bit
8
1350
2275
8-lane, Gen2
128-bit
8
1450
2600
Product
RX Buffers
Size (KB)
TX
Buffers
Size (KB)
CMPS (2)
(Bytes)
Block
RAM
MMCMs
Clock
Buffers
8 or 16
4-32
128-1024
2-16
1
5
1. Numbers are for the default core configuration. Actual LUT and FF utilization values vary based on specific configurations.
2. Capability Maximum Payload Size (CMPS).
3. Gen1 speeds are 2.5 Gb/s. Gen2 speeds are 5.0 Gb/s.
Features
•
High-performance, highly flexible, scalable, and reliable, general-purpose I/O core
•
Compliant with the PCI Express Base Specification, rev. 2.1
•
Compatible with conventional PCI software model
•
Incorporates Xilinx Smart-IP technology to guarantee critical timing
•
Uses GTXE2 transceivers for 7 Series FPGA families
•
2.5 GT/s and 5.0 GT/s line speed
•
Supports 1-lane, 2-lane, 4-lane, and 8-lane operation
•
Elastic buffers and clock compensation
•
Automatic clock data recovery
•
Supports Endpoint configurations
•
8B/10B encode and decode
•
Supports Lane Reversal and Lane Polarity Inversion per PCI Express specification requirements
•
Standardized user interface
•
Supports AXI4-Stream interface
•
Easy-to-use packet-based protocol
•
Full-duplex communication
•
Back-to-back transactions enable greater link bandwidth utilization
•
Supports flow control of data and discontinuation of an in-process transaction in transmit direction
•
Supports flow control of data in receive direction
•
Compliant with PCI/PCI Express power management functions
•
Supports a maximum transaction payload of up to 1024 bytes
•
Supports Multi-Vector MSI for up to 32 vectors and MSI-X
•
Up-configure capability enables application driven bandwidth scalability
•
Compliant with PCI Express transaction ordering rules
DS821 October 19, 2011
Product Specification
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2
LogiCORE IP 7 Series FPGAs Integrated Block v1.2 for PCI Express
Applications
The 7 series Integrated Block for PCI Express architecture enables a broad range of computing and communications
target applications, emphasizing performance, cost, scalability, feature extensibility and mission-critical reliability.
Typical applications include:
•
Data communications networks
•
Telecommunications networks
•
Broadband wired and wireless applications
•
Cross-connects
•
Network interface cards
•
Chip-to-chip and backplane interconnect
•
Crossbar switches
•
Wireless base stations
Functional Description
For information about the internal architecture and detailed descriptions of the interfaces of the integrated block in
Virtex®-7 and Kintex™-7 FPGAs, see the LogiCORE IP 7 Series FPGAs Integrated Block for PCI Express User Guide.
Figure 1 illustrates the interfaces to the core.
•
System (SYS) Interface
•
PCI Express (PCI EXP) Interface
•
Physical Layer Control and Status (PL) Interface
•
Configuration (CFG) Interface
•
AXI4-Stream Interface
X-Ref Target - Figure 1
LogiCORE IP 7 Series FPGAs
Integrated Block for PCI Express
TX
Block RAM
User
Logic
AXI4-Stream
Interface
Physical Layer
Control and Status
Host
Interface
User
Logic
RX
Block RAM
Physical
(PL)
7 Series FPGAs
Integrated Block for
PCI Express
(PCIE_2_1)
PCI Express
(PCI_EXP)
Transceivers
Configuration
(CFG)
Optional Debug
Optional Debug
(DRP)
System
(SYS)
PCI
Express
Fabric
User Logic
Clock
and
Reset
Figure 1: Integrated Block for PCI Express Top-Level Functional Blocks and Interfaces
DS821 October 19, 2011
Product Specification
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LogiCORE IP 7 Series FPGAs Integrated Block v1.2 for PCI Express
Protocol Layers
The integrated block follows the PCI Express Base Specification, rev. 2.1 layering model, which consists of the
Physical, Data Link, and Transaction Layers. The protocol uses packets to exchange information between layers.
Packets are formed in the Transaction and Data Link Layers to carry information from the transmitting component
to the receiving component. Necessary information is added to the packet being transmitted, which is required to
handle the packet at specific layers.
At the receiving end, each layer of the receiving element processes the incoming packet, strips the relevant
information and forwards the packet to the next layer. As a result, the received packets are transformed from their
Physical Layer representation to their Data Link Layer representation and Transaction Layer representation.
The functions of the protocol layers include:
•
Generating and processing of TLPs
•
Flow-control management
•
Initialization and power management functions
•
Data protection
•
Error checking and retry functions
•
Physical link interface initialization
•
Maintenance and status tracking
•
Serialization, deserialization and other circuitry for interface operation
Each of the protocol layers are defined in the sections that follow.
Physical Layer
The Physical Layer exchanges information with the Data Link Layer in an implementation-specific format. This
layer is responsible for converting information received from the Data Link Layer into an appropriate serialized
format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device.
Data Link Layer
The Data Link Layer acts as an intermediate stage between the Transaction Layer and the Physical Layer. Its
primary responsibility is to provide a reliable mechanism for the exchange of Transaction Layer Packets (TLPs)
between the two Components on a Link.
Services provided by the Data Link Layer include data exchange (TLPs), error detection and recovery, initialization
services and the generation and consumption of Data Link Layer Packets (DLLPs). DLLPs are the mechanism used
to transfer information between Data Link Layers of two directly connected components on the Link. DLLPs are
used for conveying information such as Flow Control and TLP acknowledgments.
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The primary function of the Transaction
Layer is the assembly and disassembly of Transaction Layer Packets (TLPs). Packets are formed in the Transaction
and Data Link Layers to carry the information from the transmitting component to the receiving component. TLPs
are used to communicate transactions, such as read and write, as well as certain types of events. To maximize the
efficiency of communication between devices, the Transaction Layer implements a pipelined, full split-transaction
protocol and manages credit-based flow control of TLPs.
DS821 October 19, 2011
Product Specification
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LogiCORE IP 7 Series FPGAs Integrated Block v1.2 for PCI Express
Configuration Management
The Configuration Management Layer supports generation and reception of System Management Messages by
communicating with the other layers and the user application. This layer contains the device configuration space
and other system functions. The Configuration layer implements PCI and PCI Express power management
capabilities, and facilitates exchange of power management messages, including support for PME event generation.
Also implemented are user-triggered error message generation, and user-read access to the device configuration
space.
PCI Configuration Space
The configuration space consists of three primary parts. These include the following:
•
•
•
Legacy PCI v3.0 Type 0/1 Configuration Space Header
•
Type 0 Configuration Space Header, used by Endpoint applications
•
Type 1 Configuration Space Header, used by Root Port applications
Legacy Extended Capability Items
•
PCIe Capability Item
•
Power Management Capability Item
•
Message Signaled Interrupt (MSI) Capability Item
•
MSI-X Capability Item (optional)
PCIe Extended Capabilities
•
Device Serial Number Extended Capability (optional)
•
Virtual Channel Extended Capability (optional)
•
Vendor Specific Extended Capability (optional)
•
Advanced Error Reporting Extended Capability (optional)
•
Resizeable BAR Extended Capability (optional)
These capabilities, together with the standard Type 0/1 header, support software driven Plug and Play initialization
and configuration.
Support
Xilinx provides technical support for this LogiCORE IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
The Xilinx 7 Series FPGAs Integrated Block for PCI Express is included with the CORE Generator™ software. No
license key is required.
DS821 October 19, 2011
Product Specification
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5
LogiCORE IP 7 Series FPGAs Integrated Block v1.2 for PCI Express
References
The following list provides supplemental information useful with this data sheet:
•
UG761, Xilinx AXI Reference Guide
•
AMBA AXI4-Stream Protocol Specification
•
UG477, 7 Series FPGAs Integrated Endpoint Block for PCI Express User Guide
•
Xilinx Solution Center for PCI Express
Revision History
The following table shows the revision history for this document:
Date
Version
Description of Revisions
03/01/11
1.0
Initial Xilinx release. This release is for ISE 13.1 software and core release v1.1.
10/19/11
1.1
ISE 13.3 software release for core v1.2.
• Updated the LogiCORE IP Facts table and added table note 3.
• Updated Table 1 and added MMCM and Clock Buffer columns.
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Product Specification
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