DATA SHEET PIC Microcontrollers

DATA SHEET PIC Microcontrollers
DATA SHEET
PIC Microcontrollers
Order code
73-3218
Manufacturer code
PIC16C505-04I/P
Description
PIC16C505-04I/P MICRO (RC)
PIC Microcontrollers
Page 1 of 86
The enclosed information is believed to be correct, Information may change ‘without notice’ due to
product improvement. Users should ensure that the product is suitable for their use. E. & O. E.
Sales: 01206 751166
[email protected]
Technical: 01206 835555
[email protected]
Revision A
20/02/2007
Fax: 01206 751188
www.rapidonline.com
PIC16C505
14-Pin, 8-Bit CMOS Microcontroller
Device included in this Data Sheet:
Special Microcontroller Features:
PIC16C505
•
•
•
•
High-Performance RISC CPU:
• Only 33 instructions to learn
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
Memory
Device
PIC16C505
Program
Data
1024 x 12
72 x 8
• Direct, indirect and relative addressing modes for
data and instructions
• 12-bit wide instructions
• 8-bit wide data path
• 2-level deep hardware stack
• Eight special function hardware registers
• Direct, indirect and relative addressing modes for
data and instructions
• All single cycle instructions (200 ns) except for
program branches which are two-cycle
Peripheral Features:
•
•
•
•
11 I/O pins with individual direction control
1 input pin
High current sink/source for direct LED drive
Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
Pin Diagram:
PDIP, SOIC, Ceramic Side Brazed
1
2
3
4
5
6
14
PIC16C505
VDD
RB5/OSC1/CLKIN
RB4/OSC2/CLKOUT
RB3/MCLR/VPP
RC5/T0CKI
RC4
RC3
7
 1999 Microchip Technology Inc.
13
12
11
10
9
8
•
•
•
•
•
In-Circuit Serial Programming (ICSP™)
Power-on Reset (POR)
Device Reset Timer (DRT)
Watchdog Timer (WDT) with dedicated on-chip
RC oscillator for reliable operation
Programmable Code Protection
Internal weak pull-ups on I/O pins
Wake-up from Sleep on pin change
Power-saving Sleep mode
Selectable oscillator options:
- INTRC: Precision internal 4 MHz oscillator
- EXTRC: External low-cost RC oscillator
- XT:
Standard crystal/resonator
- HS:
High speed crystal/resonator
- LP:
Power saving, low frequency
crystal
CMOS Technology:
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• Wide operating voltage range (2.5V to 5.5V)
• Wide temperature ranges
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
- < 1.0 µA typical standby current @ 5V
• Low power consumption
- < 2.0 mA @ 5V, 4 MHz
- 15 µA typical @ 3.0V, 32 kHz for TMR0
running in SLEEP mode
- < 1.0 µA typical standby current @ 5V
VSS
RB0
RB1
RB2
RC0
RC1
RC2
DS40192C-page 1
PIC16C505
TABLE OF CONTENTS
1.0
General Description..................................................................................................................................................................... 3
2.0
PIC16C505 Device Varieties ....................................................................................................................................................... 5
3.0
Architectural Overview ................................................................................................................................................................ 7
4.0
Memory Organization ................................................................................................................................................................ 11
5.0
I/O Port ...................................................................................................................................................................................... 19
6.0
Timer0 Module and TMR0 Register .......................................................................................................................................... 23
7.0
Special Features of the CPU ..................................................................................................................................................... 27
8.0
Instruction Set Summary ........................................................................................................................................................... 39
9.0
Development Support................................................................................................................................................................ 51
10.0 Electrical Characteristics - PIC16C505 ..................................................................................................................................... 57
11.0 DC and AC Characteristics - PIC16C505.................................................................................................................................. 71
11.0 Packaging Information............................................................................................................................................................... 75
Index .................................................................................................................................................................................................... 79
On-Line Support................................................................................................................................................................................... 81
Reader Response ................................................................................................................................................................................ 82
PIC16C505 Product Identification System .......................................................................................................................................... 83
To Our Valued Customers
Most Current Data Sheet
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Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet.
• E-mail us at [email protected]
We appreciate your assistance in making this a better document.
DS40192C-page 2
 1999 Microchip Technology Inc.
PIC16C505
1.0
GENERAL DESCRIPTION
The PIC16C505 from Microchip Technology is a lowcost, high-performance, 8-bit, fully static, EPROM/
ROM-based CMOS microcontroller. It employs a RISC
architecture with only 33 single word/single cycle
instructions. All instructions are single cycle (200 µs)
except for program branches, which take two cycles.
The PIC16C505 delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly
symmetrical resulting in a typical 2:1 code compression
over other 8-bit microcontrollers in its class. The easy
to use and easy to remember instruction set reduces
development time significantly.
The PIC16C505 product is equipped with special features that reduce system cost and power requirements.
The Power-On Reset (POR) and Device Reset Timer
(DRT) eliminate the need for external reset circuitry.
There are five oscillator configurations to choose from,
including INTRC internal oscillator mode and the
power-saving LP (Low Power) oscillator mode. Power
saving SLEEP mode, Watchdog Timer and code
protection features improve system cost, power and
reliability.
1.1
Applications
The PIC16C505 fits in applications ranging from personal care appliances and security systems to lowpower remote transmitters/receivers. The EPROM
technology makes customizing application programs
(transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The
small footprint packages, for through hole or surface
mounting, make this microcontroller perfect for applications with space limitations. Low-cost, low-power, highperformance, ease of use and I/O flexibility make the
PIC16C505 very versatile even in areas where no
microcontroller use has been considered before (e.g.,
timer functions, replacement of “glue” logic and PLD’s
in larger systems, and coprocessor applications).
The PIC16C505 is available in the cost-effective OneTime-Programmable (OTP) version, which is suitable
for production in any volume. The customer can take
full advantage of Microchip’s price leadership in OTP
microcontrollers, while benefiting from the OTP’s
flexibility.
The PIC16C505 product is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a ‘C’ compiler, a low-cost development programmer and a full featured programmer. All the tools
are supported on IBM PC and compatible machines.
 1999 Microchip Technology Inc.
DS40192C-page 3
PIC16C505
TABLE 1-1:
PIC16C505 DEVICE
PIC16C505
Clock
Memory
Peripherals
Features
Maximum Frequency
of Operation (MHz)
20
EPROM Program Memory
1024
Data Memory (bytes)
72
Timer Module(s)
TMR0
Wake-up from SLEEP on
pin change
Yes
I/O Pins
11
Input Pins
1
Internal Pull-ups
Yes
In-Circuit Serial Programming
Yes
Number of Instructions
33
Packages
14-pin DIP, SOIC, JW
The PIC16C505 device has Power-on Reset, selectable Watchdog Timer, selectable code protect, high I/O current capability and
precision internal oscillator.
The PIC16C505 device uses serial programming with data pin RB0 and clock pin RB1.
DS40192C-page 4
 1999 Microchip Technology Inc.
PIC16C505
2.0
PIC16C505 DEVICE VARIETIES
A variety of packaging options are available.
Depending
on
application
and
production
requirements, the proper device option can be
selected using the information in this section. When
placing orders, please use the PIC16C505 Product
Identification System at the back of this data sheet to
specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in a ceramic windowed package, is optimal for prototype development
and pilot programs.
The UV erasable version can be erased and
reprogrammed to any of the configuration modes.
Note:
Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
Microchip’s PICSTART PLUS and PRO MATE II programmers all support programming of the PIC16C505.
Third party programmers also are available; refer to the
Microchip Third Party Guide, (DS00104), for a list of
sources.
2.2
2.3
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program medium
to high quantity units and whose code patterns have
stabilized. The devices are identical to the OTP devices
but with all EPROM locations and fuse options already
programmed by the factory. Certain code and prototype
verification procedures do apply before production
shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service, where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility of frequent code
updates or small volume applications.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
 1999 Microchip Technology Inc.
DS40192C-page 5
PIC16C505
NOTES:
DS40192C-page 6
 1999 Microchip Technology Inc.
PIC16C505
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C505 can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C505 uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12 bits wide, making it possible to have
all single word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions
(33) execute in a single cycle (200ns @ 20MHz)
except for program branches.
The Table below lists program memory (EPROM) and
data memory (RAM) for the PIC16C505.
Memory
Device
PIC16C505
Program
Data
1024 x 12
72 x 8
The PIC16C505 device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
one operand is typically the W (working) register. The
other operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.
The PIC16C505 can directly or indirectly address its
register files and data memory. All special function
registers, including the program counter, are mapped
in the data memory. The PIC16C505 has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC16C505 simple yet efficient.
In addition, the learning curve is reduced significantly.
 1999 Microchip Technology Inc.
DS40192C-page 7
PIC16C505
FIGURE 3-1:
PIC16C505 BLOCK DIAGRAM
12
Program
Bus
Data Bus
Program Counter
EPROM
1K x 12
Program
Memory
8
12
RAM Addr
9
Addr MUX
Instruction reg
Indirect
5-7 Addr
5
FSR reg
STATUS reg
8
3
Device Reset
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2
Timing
Generation
RB0
RB1
RB2
RB3/MCLR/VPP
RB4/OSC2/CLKOUT
RB5/OSC1/CLKIN
RAM
72 bytes
File
Registers
STACK1
STACK2
Direct Addr
PORTB
Power-on
Reset
PORTC
RC0
RC1
RC2
RC3
RC4
RC5/T0CKI
MUX
ALU
8
Watchdog
Timer
W reg
Internal RC
OSC
Timer0
MCLR
VDD, VSS
DS40192C-page 8
 1999 Microchip Technology Inc.
PIC16C505
TABLE 3-1:
PIC16C505 PINOUT DESCRIPTION
DIP
Pin #
SOIC
Pin #
I/O/P
Type
RB0
13
13
I/O
TTL/ST Bi-directional I/O port/ serial programming data. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
RB1
12
12
I/O
TTL/ST Bi-directional I/O port/ serial programming clock. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
RB2
11
11
I/O
RB3/MCLR/VPP
4
4
I
RB4/OSC2/CLKOUT
3
3
I/O
RB5/OSC1/CLKIN
2
2
I/O
RC0
10
10
I/O
TTL
Bi-directional I/O port.
RC1
9
9
I/O
TTL
Bi-directional I/O port.
RC2
8
8
I/O
TTL
Bi-directional I/O port.
RC3
7
7
I/O
TTL
Bi-directional I/O port.
RC4
6
6
I/O
TTL
Bi-directional I/O port.
RC5/T0CKI
5
5
I/O
ST
Bi-directional I/O port. Can be configured as T0CKI.
VDD
1
1
P
—
Positive supply for logic and I/O pins
VSS
14
14
P
—
Ground reference for logic and I/O pins
Name
Buffer
Type
TTL
Description
Bi-directional I/O port.
TTL/ST Input port/master clear (reset) input/programming voltage input. When configured as MCLR, this pin is an
active low reset to the device. Voltage on MCLR/VPP
must not exceed VDD during normal device operation.
Can be software programmed for internal weak pull-up
and wake-up from SLEEP on pin change. Weak pullup only when configured as RB3. ST when configured
as MCLR.
TTL
Bi-directional I/O port/oscillator crystal output. Connections to crystal or resonator in crystal oscillator
mode (XT and LP modes only, RB4 in other modes).
Can be software programmed for internal weak pull-up
and wake-up from SLEEP on pin change. In EXTRC
and INTRC modes, the pin output can be configured to
CLKOUT, which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
TTL/ST Bidirectional IO port/oscillator crystal input/external
clock source input (RB5 in Internal RC mode only,
OSC1 in all other oscillator modes). TTL input when
RB5, ST input in external RC oscillator mode.
Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,
ST = Schmitt Trigger input
 1999 Microchip Technology Inc.
DS40192C-page 9
PIC16C505
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into the instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
Instruction Flow/Pipelining
An Instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the
instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3 and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
EXAMPLE 3-1:
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTB, BIT1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch
instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS40192C-page 10
 1999 Microchip Technology Inc.
PIC16C505
4.0
MEMORY ORGANIZATION
PIC16C505 memory is organized into program memory and data memory. For the PIC16C505, a paging
scheme is used.
Program memory pages are
accessed using one STATUS register bit. Data memory banks are accessed using the File Select Register
(FSR).
4.1
FIGURE 4-1:
PC<11:0>
12
CALL, RETLW
Stack Level 1
Stack Level 2
Program Memory Organization
The PIC16C505 devices have a 12-bit Program
Counter (PC).
Reset Vector (note 1)
User Memory
Space
The 1K x 12 (0000h-03FFh) for the PIC16C505 are
physically implemented. Refer to Figure 4-1.
Accessing a location above this boundary will cause a
wrap-around within the first 1K x 12 space. The
effective reset vector is at 0000h, (see Figure 4-1).
Location 03FFh contains the internal clock oscillator
calibration value. This value should never be
overwritten.
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C505
0000h
01FFh
0200h
On-chip Program
Memory
1024 Words
03FFh
0400h
7FFh
Note 1:
 1999 Microchip Technology Inc.
Address 0000h becomes the
effective reset vector. Location 03FFh
contains the MOVLW XX INTERNAL RC
oscillator calibration value.
DS40192C-page 11
PIC16C505
4.2
Data Memory Organization
For the PIC16C505, the register file is composed of 8
Special Function Registers, 24 General Purpose
Registers and 48 General Purpose Registers that may
be addressed using a banking scheme (Figure 4-2).
Data memory is composed of registers or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers and
General Purpose Registers.
4.2.1
GENERAL PURPOSE REGISTER FILE
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
FSR (Section 4.8).
The Special Function Registers include the TMR0
register, the Program Counter (PCL), the Status
Register, the I/O registers (ports) and the File Select
Register (FSR). In addition, Special Function
Registers are used to control the I/O port configuration
and prescaler options.
The General Purpose Registers are used for data and
control information under command of the instructions.
FIGURE 4-2:
PIC16C505 REGISTER FILE MAP
FSR<6:5>
00
File Address
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
OSCCAL
06h
PORTB
07h
PORTC
08h
General
Purpose
Registers
0Fh
01
20h
40h
2Fh
DS40192C-page 12
6Fh
50h
3Fh
Bank 0
Note 1:
60h
4Fh
General
Purpose
Registers
General
Purpose
Registers
1Fh
11
Addresses map back to
addresses in Bank 0.
30h
10h
10
70h
General
Purpose
Registers
5Fh
Bank 1
General
Purpose
Registers
7Fh
Bank 2
Bank 3
Not a physical register.
 1999 Microchip Technology Inc.
PIC16C505
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control
the operation of the device (Table 4-1).
TABLE 4-1:
Address
00h
SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Name
INDF
Value on
Power-On
Reset
Value on
All Other
Resets(2)
Uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
uuuu uuuu
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
02h(1)
PCL
Low order 8 bits of PC
1111 1111
1111 1111
03h
STATUS
0001 1xxx
q00q quuu(1)
04h
FSR
110x xxxx
11uu uuuu
05h
OSCCAL
1000 00--
uuuu uu--
N/A
N/A
RBWUF
—
PAO
TO
PD
Z
DC
C
CAL1
CAL0
—
—
Indirect data memory address pointer
CAL5
CAL4
CAL3
CAL2
TRISB
—
—
I/O control registers
--11 1111
--11 1111
TRISC
—
—
I/O control registers
--11 1111
--11 1111
N/A
OPTION
RBWU
RBPU
TOCS
TOSE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
06h
PORTB
—
—
RB5
RB4
RB3
RB2
RB1
RB0
--xx xxxx
--uu uuuu
07h
PORTC
—
—
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
--uu uuuu
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged,
q = depends on condition.
Note 1: If reset was due to wake-up on pin change, then bit 7 = 1. All other rests will cause bit 7 = 0.
Note 2: Other (non-power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset.
 1999 Microchip Technology Inc.
DS40192C-page 13
PIC16C505
4.3
STATUS Register
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
This register contains the arithmetic status of the ALU,
the RESET status and the page preselect bit.
It is recommended, therefore, that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register, because these instructions do not affect the
Z, DC or C bits from the STATUS register. For other
instructions, which do affect STATUS bits, see
Instruction Set Summary.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.
REGISTER 4-1:
R/W-0
RBWUF
bit7
R/W-0
STATUS REGISTER (ADDRESS:03h)
—
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
6
5
4
3
2
1
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
RBWUF: I/O reset bit
1 = Reset due to wake-up from SLEEP on pin change
0 = After power up or other reset
bit 6:
Unimplemented
bit 5:
PA0: Program page preselect bits
1 = Page 1 (200h - 3FFh)
0 = Page 0 (000h - 1FFh)
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program
page preselect is not recommended, since this may affect upward compatibility with future products.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF
SUBWF
1 = A carry occurred
1 = A borrow did not occur
0 = A carry did not occur
0 = A borrow occurred
DS40192C-page 14
RRF or RLF
Load bit with LSB or MSB, respectively
 1999 Microchip Technology Inc.
PIC16C505
4.4
OPTION Register
Note:
The OPTION register is a 8-bit wide, write-only
register, which contains various control bits to
configure the Timer0/WDT prescaler and Timer0.
If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin (i.e., note that TRIS overrides
OPTION control of RBPU and RBWU).
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A RESET sets the OPTION<7:0> bits.
REGISTER 4-2:
OPTION REGISTER
W-1
W-1
W-1
W-1
W-1
W-1
W-1
W-1
RBWU
RBPU
T0CS
T0SE
PSA
PS2
PS1
PS0
6
5
4
3
2
1
bit7
bit 7:
RBWU: Enable wake-up on pin change (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
bit 6:
RBPU: Enable weak pull-ups (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
bit 5:
T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin (overrides TRIS <RC57>
0 = Transition on internal instruction cycle clock, Fosc/4
bit 4:
T0SE: Timer0 source edge select bit
1 = Increment on high to low transition on the T0CKI pin
0 = Increment on low to high transition on the T0CKI pin
bit 3:
PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0:
PS<2:0>: Prescaler rate select bits
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
 1999 Microchip Technology Inc.
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
DS40192C-page 15
PIC16C505
4.5
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal 4 MHz oscillator. It contains six
bits for calibration
Note:
Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be read prior to
erasing the part, so it can be reprogrammed correctly later.
After you move in the calibration constant, do not
change the value. See Section 7.2.5
REGISTER 4-3:
OSCCAL REGISTER (ADDRESS 05h) PIC16C505
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: CAL<5:0>: Calibration
bit 1-0: Unimplemented read as ‘0’
DS40192C-page 16
 1999 Microchip Technology Inc.
PIC16C505
4.6
Program Counter
4.6.1
EFFECTS OF RESET
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page (i.e., the oscillator calibration instruction.)
After executing MOVLW XX, the PC will roll over to
location 00h and begin executing user code.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0>. Bit 5 of the STATUS register
provides page information to bit 9 of the PC
(Figure 4-3).
The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is preselected.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-3).
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC, and BSF PC,5.
Note:
Because PC<8> is cleared in the CALL
instruction or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any program memory page (512 words long).
FIGURE 4-3:
LOADING OF PC
BRANCH INSTRUCTIONS PIC16C505
GOTO Instruction
11 10
9
8 7
Therefore, upon a RESET, a GOTO instruction will
automatically cause the program to jump to page 0
until the value of the page bits is altered.
4.7
Stack
PIC16C505 devices have a 12-bit wide hardware
push/pop stack.
A CALL instruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
0
PC
PCL
Note 1: There are no STATUS bits to indicate
stack overflows or stack underflow conditions.
Instruction Word
PA0
7
Note 2: There are no instructions mnemonics
called PUSH or POP. These are actions that
occur from the execution of the CALL,
RETLW, and instructions.
0
STATUS
CALL or Modify PCL Instruction
11 10
9
8 7
0
PC
PCL
Instruction Word
Reset to ‘0’
PA0
7
0
STATUS
 1999 Microchip Technology Inc.
DS40192C-page 17
PIC16C505
4.8
Indirect Data Addressing; INDF and
FSR Registers
EXAMPLE 4-2:
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
EXAMPLE 4-1:
INDIRECT ADDRESSING
movlw
movwf
clrf
incf
btfsc
goto
NEXT
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x10
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
• Register file 07 contains the value 10h
:
:
• Register file 08 contains the value 0Ah
;YES, continue
The FSR is a 5-bit wide register. It is used in
conjunction with the INDF register to indirectly address
the data memory area.
• Load the value 07 into the FSR register
• A read of the INDF register will return the value
of 10h
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
• Increment the value of the FSR register by one
(FSR = 08)
The device uses FSR<6:5> to select between banks
0:3.
• A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
(FSR)
6 5
bank select
4
Indirect Addressing
(opcode)
0
6
5
4
bank
location select
00
01
10
(FSR)
0
location select
11
00h
Addresses
map back to
addresses
in Bank 0.
Data
Memory(1)
0Fh
10h
1Fh
Bank 0
3Fh
Bank 1
5Fh
Bank 2
7Fh
Bank 3
Note 1: For register map detail see Section 4.2.
DS40192C-page 18
 1999 Microchip Technology Inc.
PIC16C505
5.0
I/O PORT
As with any other register, the I/O register can be
written and read under program control. However,
read instructions (e.g., MOVF PORTB,W) always read
the I/O pins independent of the pin’s input/output
modes. On RESET, all I/O ports are defined as input
(inputs are at hi-impedance) since the I/O control
registers are all set.
5.1
PORTB
PORTB is an 8-bit I/O register. Only the low order 6
bits are used (RB<5:0>). Bits 7 and 6 are
unimplemented and read as '0's. Please note that RB3
is an input only pin. The configuration word can set
several I/O’s to alternate functions. When acting as
alternate functions, the pins will read as ‘0’ during port
read. Pins RB0, RB1, RB3 and RB4 can be configured
with weak pull-ups and also with wake-up on change.
The wake-up on change and weak pull-up functions
are not pin selectable. If pin 4 is configured as MCLR,
weak pull-up is always off and wake-up on change for
this pin is not enabled.
5.2
TRIS Registers
The output driver control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. The
exceptions are RB3, which is input only, and RC5,
which may be controlled by the option register. See
Register 4-2.
Note:
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins except RB3, which is input
only, may be used for both input and output operations.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF PORTB,W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except RB3) can be programmed individually as
input or output.
FIGURE 5-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
Q
Data
Latch
WR
Port
CK
VDD
Q
P
PORTC
PORTC is an 8-bit I/O register. Only the low order 6 bits
are used (RC<5:0>). Bits 7 and 6 are unimplemented
and read as ‘0’s.
5.3
5.4
W
Reg
N
D
Q
TRIS
Latch
TRIS ‘f’
CK
Reset
I/O
pin(1)
VSS
Q
(2)
RD Port
Note 1:
I/O pins have protection diodes to VDD and VSS.
Note 2:
See Table 3-1 for buffer type.
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
 1999 Microchip Technology Inc.
DS40192C-page 19
PIC16C505
TABLE 5-1:
Address
SUMMARY OF PORT REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other Resets
N/A
TRISB
—
—
I/O control registers
--11 1111
--11 1111
N/A
TRISC
—
—
I/O control registers
--11 1111
--11 1111
N/A
OPTION
RBWU
RBPU
TOCS
TOSE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
03h
STATUS
RBWUF
—
PAO
TO
PD
Z
DC
C
0001 1xxx
q00q quuu(1)
06h
PORTB
—
—
RB5
RB4
RB3
RB2
RB1
RB0
--xx xxxx
--uu uuuu
07h
PORTC
—
—
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
--uu uuuu
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged,
q = depends on condition.
Note 1: If reset was due to wake-up on pin change, then bit 7 = 1. All other rests will cause bit 7 = 0.
5.5
I/O Programming Considerations
5.5.1
BI-DIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a bidirectional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.
Example 5-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wiredand”). The resulting high output currents may damage
the chip.
DS40192C-page 20
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial PORTB Settings
; PORTB<5:3> Inputs
; PORTB<2:0> Outputs
;
;
PORTB latch PORTB pins
;
---------- ---------BCF
PORTB, 5
;--01 -ppp
--11 pppp
BCF
PORTB, 4
;--10 -ppp
--11 pppp
MOVLW 007h
;
TRIS PORTB
;--10 -ppp
--11 pppp
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;RB5 to be latched as the pin value (High).
5.5.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction causes that file to be read
into the CPU. Otherwise, the previous state of that pin
may be read into the CPU rather than the new state.
When in doubt, it is better to separate these
instructions with a NOP or another instruction not
accessing this I/O port.
 1999 Microchip Technology Inc.
PIC16C505
FIGURE 5-2:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
MOVWF PORTB
PC + 1
MOVF PORTB,W
Q1 Q2 Q3 Q4
PC + 2
PC + 3
NOP
NOP
This example shows a write to PORTB
followed by a read from PORTB.
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
RB<5:0>
TPD = propagation delay
Port pin
written here
Instruction
executed
MOVWF PORTB
(Write to PORTB)
 1999 Microchip Technology Inc.
Port pin
sampled here
MOVF PORTB,W
(Read PORTB)
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
NOP
DS40192C-page 21
PIC16C505
NOTES:
DS40192C-page 22
 1999 Microchip Technology Inc.
PIC16C505
6.0
TIMER0 MODULE AND TMR0
REGISTER
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input are discussed
in detail in Section 6.1.
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 6-1:
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 6.2 details the
operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
TIMER0 BLOCK DIAGRAM
Data Bus
RC5/T0CKI
Pin
FOSC/4
0
PSout
1
1
Programmable
Prescaler(2)
0
T0SE
8
Sync with
Internal
Clocks
TMR0 reg
PSout
(2 TCY delay) Sync
3
T0CS(1)
PS2, PS1, PS0(1)
PSA(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
 1999 Microchip Technology Inc.
DS40192C-page 23
PIC16C505
FIGURE 6-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC-1
T0
Timer0
PC
PC+1
T0+1
PC+3
T0+2
Instruction
Executed
Write TMR0
executed
FIGURE 6-3:
PC+2
PC+4
PC+5
NT0+1
NT0
Read TMR0 Read TMR0
reads NT0
reads NT0
Read TMR0
reads NT0
PC+6
NT0+2
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC-1
PC
T0
Timer0
PC+1
Address
PC+3
T0+1
PC+4
PC+5
Write TMR0
executed
Read TMR0
reads NT0
PC+6
NT0+1
NT0
Instruction
Execute
TABLE 6-1:
PC+2
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
T0
Read TMR0
reads NT0 + 1
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
01h
TMR0
Timer0 - 8-bit real-time clock/counter
N/A
OPTION
RBWU
RBPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
N/A
TRISC
—
—
RC5
RC4
RC3
RC2
RC1
RC0
--11 1111 --11 1111
xxxx xxxx uuuu uuuu
Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged.
DS40192C-page 24
 1999 Microchip Technology Inc.
PIC16C505
6.1
Using Timer0 with an External Clock
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-4). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
FIGURE 6-4:
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler Output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
 1999 Microchip Technology Inc.
DS40192C-page 25
PIC16C505
6.2
Prescaler
RESET,
the
following
instruction
sequence
(Example 6-1) must be executed when changing the
prescaler assignment from Timer0 to the WDT.
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 7.6). For simplicity,
this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler
may be used by either the Timer0 module or the WDT,
but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for
the WDT, and vice-versa.
EXAMPLE 6-1:
1.CLRWDT
2.CLRF
TMR0
3.MOVLW '00xx1111’b
4.OPTION
;Clear WDT
;Clear TMR0 & Prescaler
;These 3 lines (5, 6, 7)
; are required only if
; desired
5.CLRWDT
;PS<2:0> are 000 or 001
6.MOVLW '00xx1xxx’b ;Set Postscaler to
7.OPTION
; desired WDT rate
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1,x, etc.) will clear the prescaler.
When assigned to WDT, a CLRWDT instruction will
clear the prescaler along with the WDT. The prescaler
is neither readable nor writable. On a RESET, the
prescaler contains all '0's.
6.2.1
CHANGING PRESCALER
(TIMER0→WDT)
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2.
This sequence must be used even if the WDT is
disabled. A CLRWDT instruction should be executed
before switching the prescaler.
EXAMPLE 6-2:
SWITCHING PRESCALER ASSIGNMENT
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). To avoid an unintended device
MOVLW
'xxxx0xxx'
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
OPTION
FIGURE 6-5:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = Fosc/4)
Data Bus
0
RC5/T0CKI
Pin
1
8
M
U
X
1
M
U
X
0
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Sync
2
Cycles
TMR0 reg
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS<2:0>
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
DS40192C-page 26
 1999 Microchip Technology Inc.
PIC16C505
7.0
SPECIAL FEATURES OF THE
CPU
The PIC16C505 has a Watchdog Timer, which can be
shut off only through configuration bit WDTE. It runs
off of its own RC oscillator for added reliability. If using
HS, XT or LP selectable oscillator options, there is
always an 18 ms (nominal) delay provided by the
Device Reset Timer (DRT), intended to keep the chip
in reset until the crystal oscillator is stable. If using
INTRC or EXTRC, there is an 18 ms delay only on VDD
power-up. With this timer on-chip, most applications
need no external reset circuitry.
What sets a microcontroller apart from other
processors are special circuits to deal with the needs
of
real-time
applications.
The
PIC16C505
microcontroller has a host of such features intended to
maximize system reliability, minimize cost through
elimination of external components, provide power
saving operating modes and offer code protection.
These features are:
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up
from SLEEP through a change on input pins or
through a Watchdog Timer time-out. Several oscillator
options are also made available to allow the part to fit
the application, including an internal 4 MHz oscillator.
The EXTRC oscillator option saves system cost while
the LP crystal option saves power. A set of
configuration bits are used to select various options.
• Oscillator selection
• Reset
- Power-On Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from SLEEP on pin change
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit Serial Programming
• Clock Out
REGISTER 7-1:
7.1
Configuration Bits
The PIC16C505 configuration word consists of 12 bits.
Configuration bits can be programmed to select
various device configurations. Three bits are for the
selection of the oscillator type, one bit is the Watchdog
Timer enable bit, and one bit is the MCLR enable bit.
Seven bits are for code protection (Register 7-1).
CONFIGURATION WORD FOR PIC16C505
CP
CP
CP
CP
CP
CP
MCLRE
CP
bit11
10
9
8
7
6
5
4
WDTE FOSC2 FOSC1 FOSC0
3
2
1
bit0
Register: CONFIG
Address(2): 0FFFh
bit 11-6, 4: CP Code Protection bits (1)(2)(3)
bit 5:
MCLRE: RB3/MCLR pin function select
1 = RB3/MCLR pin function is MCLR
0 = RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD
bit 3:
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0:
FOSC<1:0>: Oscillator Selection bits
111 = external RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
110 = external RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
101 = internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
100 = internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
011 = invalid selection
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
03FFh is always uncode protected on the PIC16C505. This location contains the
MOVLWxx calibration instruction for the INTRC.
Refer to the PIC16C505 Programming Specifications to determine how to access the configuration word. This register is not user addressable during device operation.
All code protect bits must be written to the same value.
Note 1:
2:
3:
 1999 Microchip Technology Inc.
DS40192C-page 27
PIC16C505
7.2
Oscillator Configurations
7.2.1
OSCILLATOR TYPES
TABLE 7-1:
The PIC16C505 can be operated in four different
oscillator modes. The user can program three
configuration bits (FOSC<2:0>) to select one of these
four modes:
•
•
•
•
•
LP:
XT:
HS:
INTRC:
EXTRC:
7.2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Internal 4 MHz Oscillator
External Resistor/Capacitor
Osc
Type
CRYSTAL OPERATION (OR
CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
C1(1)
OSC1
Cap. Range
C1
Cap. Range
C2
XT
4.0 MHz
30 pF
30 pF
HS
16 MHz
10-47 pF
10-47 pF
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
FIGURE 7-1:
Resonator
Freq
TABLE 7-2:
In HS, XT or LP modes, a crystal or ceramic resonator
is connected to the RB5/OSC1/CLKIN and RB4/
OSC2/CLKOUT
pins
to
establish
oscillation
(Figure 7-1). The PIC16C505 oscillator design
requires the use of a parallel cut crystal. Use of a
series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in HS, XT
or LP modes, the device can have an external clock
source drive the RB5/OSC1/CLKIN pin (Figure 7-2).
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC16C505
Osc
Type
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR PIC16C505
Resonator
Freq
Cap.Range
C1
Cap. Range
C2
15 pF
15 pF
32 kHz(1)
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
HS
20 MHz
15-47 pF
15-47 pF
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
These values are for design guidance only. Rs may
be required to avoid overdriving crystals with low
drive level specification. Since each crystal has its
own characteristics, the user should consult the crystal manufacturer for appropriate values of external
components.
LP
XT
PIC16C505
SLEEP
XTAL
RS(2)
RF(3)
OSC2
To internal
logic
C2(1)
Note 1:
2:
3:
See Capacitor Selection tables for
recommended values of C1 and C2.
A series resistor (RS) may be required for AT
strip cut crystals.
RF approx. value = 10 MΩ.
FIGURE 7-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
PIC16C505
Clock from
ext. system
Open
DS40192C-page 28
OSC2
 1999 Microchip Technology Inc.
PIC16C505
7.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 7-3 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
FIGURE 7-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
74AS04
PIC16C505
CLKIN
10k
XTAL
10k
20 pF
20 pF
Figure 7-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
7.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
Figure 7-5 shows how the R/C combination is
connected to the PIC16C505. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
The Electrical Specifications section shows RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger
values of R (since leakage current variation will affect
RC frequency more for large R) and for smaller values
of C (since variation of input capacitance will affect RC
frequency more).
Also, see the Electrical Specifications section for
variation of oscillator frequency due to VDD for given
Rext/Cext values, as well as frequency variation due to
operating temperature for given R, C and VDD values.
FIGURE 7-5:
EXTERNAL RC OSCILLATOR
MODE
VDD
Rext
FIGURE 7-4:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
330
To Other
Devices
330
74AS04
74AS04
74AS04
PIC16C505
Internal
clock
OSC1
N
Cext
PIC16C505
VSS
FOSC/4
OSC2/CLKOUT
CLKIN
0.1 mF
XTAL
 1999 Microchip Technology Inc.
DS40192C-page 29
PIC16C505
7.2.5
INTERNAL 4 MHz RC OSCILLATOR
The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25°C, see Electrical
Specifications section for information on variation over
voltage and temperature.
In addition, a calibration instruction is programmed into
the last address of memory, which contains the calibration value for the internal RC oscillator. This location is
always protected, regardless of the code protect settings. This value is programmed as a MOVLW XX
instruction where XX is the calibration value, and is
placed at the reset vector. This will load the W register
with the calibration value upon reset and the PC will
then roll over to the users program at address 0x000.
The user then has the option of writing the value to the
OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency.
Note:
Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be read prior
to erasing the part so it can be reprogrammed correctly later.
For the PIC16C505, only bits <7:2> of OSCCAL are
implemented.
7.3
RESET
The device differentiates between various kinds of
reset:
a) Power on reset (POR)
b) MCLR reset during normal operation
c) MCLR reset during SLEEP
d) WDT time-out reset during normal operation
e) WDT time-out reset during SLEEP
f) Wake-up from SLEEP on pin change
Some registers are not reset in any way, they are
unknown on POR and unchanged in any other reset.
Most other registers are reset to “reset state” on poweron reset (POR), MCLR, WDT or wake-up on pin
change reset during normal operation. They are not
affected by a WDT reset during SLEEP or MCLR reset
during SLEEP, since these resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD and RBWUF bits. They are set or cleared
differently in different reset situations. These bits are
used in software to determine the nature of reset. See
Table 7-3 for a full description of reset states of all
registers.
DS40192C-page 30
 1999 Microchip Technology Inc.
PIC16C505
TABLE 7-3:
RESET CONDITIONS FOR REGISTERS
Address
Power-on Reset
MCLR Reset
WDT time-out
Wake-up on Pin Change
—
qqqq qqqq(1)
qqqq qqqq(1)
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PC
02h
1111 1111
1111 1111
STATUS
03h
0001 1xxx
q00q quuu(2,3)
FSR
04h
110x xxxx
11uu uuuu
OSCCAL
05h
1000 00--
uuuu uu--
PORTB
06h
--xx xxxxx
--uu uuuu
PORTC
07h
--xx xxxxx
--uu uuuu
OPTION
—
1111 1111
1111 1111
TRISB
—
--11 1111
--11 1111
TRISC
—
--11 1111
--11 1111
Register
W
INDF
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1:
Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of
memory.
Note 2:
See Table 7-7 for reset value for specific conditions.
Note 3:
If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0.
TABLE 7-4:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
Power on reset
0001 1xxx
1111 1111
MCLR reset during normal operation
000u uuuu
1111 1111
MCLR reset during SLEEP
0001 0uuu
1111 1111
WDT reset during SLEEP
0000 0uuu
1111 1111
WDT reset normal operation
0000 uuuu
1111 1111
Wake-up from SLEEP on pin change
1001 0uuu
1111 1111
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’.
 1999 Microchip Technology Inc.
DS40192C-page 31
PIC16C505
7.3.1
MCLR ENABLE
This configuration bit when unprogrammed (left in the
‘1’ state) enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD, and the pin is assigned to be a I/O. See
Figure 7-6.
FIGURE 7-6:
MCLR SELECT
RBWU
MCLRE
WEAK
PULL-UP
INTERNAL MCLR
RB3/MCLR/VPP
7.4
Power-On Reset (POR)
The PIC16C505 family incorporates on-chip Power-On
Reset (POR) circuitry, which provides an internal chip
reset for most power-up situations.
The on chip POR circuit holds the chip in reset until VDD
has reached a high enough level for proper operation.
To take advantage of the internal POR, program the
RB3/MCLR/VPP pin as MCLR and tie through a resistor
to VDD or program the pin as RB3. An internal weak
pull-up resistor is implemented using a transistor. Refer
to Table 10-1 for the pull-up resistor ranges. This will
eliminate external RC components usually needed to
create a Power-on Reset. A maximum rise time for VDD
is specified. See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the onchip reset signal.
A power-up example where MCLR is held low is
shown in Figure 7-8. VDD is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset TDRT msec after MCLR
goes high.
In Figure 7-9, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together or the
pin is programmed to be RB3.). The VDD is stable
before the start-up timer times out and there is no
problem in getting a proper reset. However,
Figure 7-10 depicts a problem situation where VDD
rises too slowly. The time between when the DRT
senses that MCLR is high and when MCLR and VDD
actually reach their full value, is too long. In this
situation, when the start-up timer times out, VDD has
not reached the VDD (min) value and the chip may not
function correctly. For such situations, we recommend
that external RC circuits be used to achieve longer
POR delay times (Figure 7-9).
Note:
When the device starts normal operation
(exits the reset condition), device operating
parameters (voltage, frequency, temperature, etc.) must be met to ensure operation.
If these conditions are not met, the device
must be held in reset until the operating
conditions are met.
For additional information refer to Application Notes
“Power-Up Considerations” - AN522 and “Power-up
Trouble Shooting” - AN607.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 7-7.
DS40192C-page 32
 1999 Microchip Technology Inc.
PIC16C505
FIGURE 7-7:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
POR (Power-On Reset)
VDD
Pin Change
Wake-up on
pin change
SLEEP
RB3/MCLR/VPP
WDT Time-out
MCLRE
RESET
8-bit Asynch
On-Chip
DRT OSC
S
Q
R
Q
Ripple Counter
(Start-Up Timer)
CHIP RESET
FIGURE 7-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
 1999 Microchip Technology Inc.
DS40192C-page 33
PIC16C505
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
Note:
7.5
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
Device Reset Timer (DRT)
In the PIC16C505, the DRT runs any time the device is
powered up. DRT runs from RESET and varies based
on oscillator selection and reset type (see Table 7-5).
The DRT operates on an internal RC oscillator. The
processor is kept in RESET as long as the DRT is
active. The DRT delay allows VDD to rise above VDD
min. and for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after MCLR has reached a logic high (VIHMCLR)
level. Thus, programming RB3/MCLR/VPP as MCLR
and using an external RC network connected to the
MCLR input is not required in most cases, allowing for
savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the RB3/
MCLR/VPP pin as a general purpose input.
The Device Reset time delay will vary from chip to chip
due to VDD, temperature and process variation. See
AC parameters for details.
The DRT will also be triggered upon a Watchdog
Timer time-out. This is particularly important for
applications using the WDT to wake from SLEEP
mode automatically.
7.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the RB5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or SLEEP, a WDT
reset or wake-up reset generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
The WDT can be permanently disabled by
programming the configuration bit WDTE as a ’0’
(Section 7.1). Refer to the PIC16C505 Programming
Specifications to determine how to access the
configuration word.
TABLE 7-5:
Oscillator
Configuration
DRT (DEVICE RESET TIMER
PERIOD)
POR Reset
Subsequent
Resets
IntRC &
ExtRC
18 ms (typical)
300 µs
(typical)
HS, XT & LP
18 ms (typical)
18 ms (typical)
Reset sources are POR, MCLR, WDT time-out and
Wake-up on pin change. (See Section 7.9.2, Notes 1,
2, and 3, page 37.)
DS40192C-page 34
 1999 Microchip Technology Inc.
PIC16C505
7.6.1
WDT PERIOD
7.6.2
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, a time-out
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, VDD and part-topart process variations (see DC specs).
WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
FIGURE 7-11: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
0
1
Watchdog
Timer
M
Postscaler
Postscaler
U
X
8 - to - 1 MUX
PS<2:0>
PSA
WDT Enable
Configuration Bit
To Timer0 (Figure 6-4)
1
0
PSA
MUX
Note: T0CS, T0SE, PSA, PS<2:0>
are bits in the OPTION register.
WDT
Time-out
TABLE 7-6:
Address
N/A
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
RBWU
RBPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Value on
All Other
Resets
1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as '0', u = unchanged.
 1999 Microchip Technology Inc.
DS40192C-page 35
PIC16C505
7.7
Time-Out Sequence, Power Down,
and Wake-up from SLEEP Status Bits
(TO/PD/RBWUF)
FIGURE 7-13: BROWN-OUT PROTECTION
CIRCUIT 2
VDD
The TO, PD, and RBWUF bits in the STATUS register
can be tested to determine if a RESET condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) reset.
R1
TABLE 7-7:
R2
RBWUF TO
PD
0
0
0
0
0
u
0
1
0
0
1
1
0
u
u
1
1
0
PIC16C505
Q1 MCLR(1)
TO/PD/RBWUF STATUS
AFTER RESET
40k*
RESET caused by
WDT wake-up from
SLEEP
WDT time-out (not from
SLEEP)
MCLR wake-up from
SLEEP
Power-up
MCLR not during SLEEP
Wake-up from SLEEP on
pin change
Legend: u = unchanged
Note 1: The TO, PD, and RBWUF bits maintain their
status (u) until a reset occurs. A low-pulse on the
MCLR input does not change the TO, PD, and
RBWUF status bits.
7.8
VDD
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
VDD •
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
To reset PIC16C505 devices when a brown-out
occurs, external brown-out protection circuits may be
built, as shown in Figure 7-12 and Figure 7-13.
FIGURE 7-12: BROWN-OUT PROTECTION
CIRCUIT 1
= 0.7V
Note 1: Pin must be confirmed as MCLR.
FIGURE 7-14: BROWN-OUT PROTECTION
CIRCUIT 3
VDD
MCP809
Reset on Brown-Out
R1
R1 + R2
VSS
bypass
capacitor
VDD
VDD
RST
MCLR
PIC12C5XX
This brown-out protection circuit employs Microchip
Technology’s MCP809 microcontroller supervisor.
There are 7 different trip point selections to
accommodate 5V to 3V systems.
VDD
VDD
33k
PIC16C505
10k
Q1
MCLR(1)
40k*
This circuit will activate reset when VDD goes below
Vz + 0.7V (where Vz = Zener voltage).
Note 1: Pin must be confirmed as MCLR.
DS40192C-page 36
 1999 Microchip Technology Inc.
PIC16C505
7.9
Power-Down Mode (SLEEP)
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
7.9.1
SLEEP
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the RB3/
MCLR/VPP pin must be at a logic high level (VIHMC) if
MCLR is enabled.
7.9.2
7.10
Program Verification/Code Protection
If the code protection bit has not been programmed,
the on-chip program memory can be read out for
verification purposes.
The first 64 locations and the last location (OSCCAL)
can be read, regardless of the code protection bit
setting.
7.11
ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other codeidentification numbers. These locations are not
accessible during normal execution, but are readable
and writable during program/verify.
Use only the lower 4 bits of the ID locations and
always program the upper 8 bits as ’0’s.
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
An external reset input on RB3/MCLR/VPP pin,
when configured as MCLR.
A Watchdog Timer time-out reset (if WDT was
enabled).
A change on input pin RB0, RB1, RB3 or RB4
when wake-up on change is enabled.
These events cause a device reset. The TO, PD, and
RBWUF bits can be used to determine the cause of
device reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The RBWUF bit indicates a change in state while in
SLEEP at pins RB0, RB1, RB3 or RB4 (since the last
file or bit operation on RB port).
Caution: Right before entering SLEEP, read the
input pins. When in SLEEP, wake up
occurs when the values at the pins change
from the state they were in at the last
reading. If a wake-up on change occurs
and the pins are not read before reentering
SLEEP, a wake-up will occur immediately
even if no pins change while in SLEEP
mode.
The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.
 1999 Microchip Technology Inc.
DS40192C-page 37
PIC16C505
7.12
In-Circuit Serial Programming
The PIC16C505 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
The device is placed into a program/verify mode by
holding the RB1 and RB0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB1 becomes the programming clock
and RB0 becomes the programming data. Both RB1
and RB0 are Schmitt Trigger inputs in this mode.
After reset, a 6-bit command is then supplied to the
device. Depending on the command, 14 bits of program
data are then supplied to or from the device, depending
if the command was a load or a read. For complete
details of serial programming, please refer to the
PIC16C505 Programming Specifications.
FIGURE 7-15: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
PIC16C505
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB1
Data I/O
RB0
VDD
To Normal
Connections
A typical in-circuit serial programming connection is
shown in Figure 7-15.
DS40192C-page 38
 1999 Microchip Technology Inc.
PIC16C505
8.0
INSTRUCTION SET SUMMARY
Each PIC16C505 instruction is a 12-bit word divided
into an OPCODE, which specifies the instruction type,
and one or more operands which further specify the
operation of the instruction. The PIC16C505
instruction set summary in Table 8-2 groups the
instructions into byte-oriented, bit-oriented, and literal
and control operations. Table 8-1 shows the opcode
field descriptions.
For byte-oriented instructions, ’f’ represents a file
register designator and ’d’ represents a destination
designator. The file register designator is used to
specify which one of the 32 file registers is to be used
by the instruction.
The destination designator specifies where the result
of the operation is to be placed. If ’d’ is ’0’, the result is
placed in the W register. If ’d’ is ’1’, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
For literal and control operations, ’k’ represents an
8 or 9-bit constant or literal value.
TABLE 8-1:
OPCODE FIELD
DESCRIPTIONS
Field
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.
d
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register ’f’)
Default is d = 1
label
Label name
TOS
Top of Stack
WDT
PD
Power-Down bit
FIGURE 8-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
11
6
OPCODE
5
d
4
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
11
OPCODE
8 7
5 4
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Literal and control operations - GOTO instruction
11
9
8
OPCODE
0
k (literal)
k = 9-bit immediate value
Destination, either the W register or the specified
register file location
[ ]
Options
( )
Contents
→
Assigned to
<>
Register bit field
∈
where ’h’ signifies a hexadecimal digit.
Watchdog Timer Counter
Time-Out bit
italics
0xhhh
Program Counter
TO
dest
Figure 8-1 shows the three general formats that the
instructions can have. All examples in the figure use the
following format to represent a hexadecimal number:
Description
f
PC
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
In the set of
User defined term (font is courier)
 1999 Microchip Technology Inc.
DS40192C-page 39
PIC16C505
TABLE 8-2:
INSTRUCTION SET SUMMARY
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f,d
f,d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
12-Bit Opcode
Description
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
LSb
Status
Affected Notes
Cycles
MSb
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C,DC,Z
None
Z
1,2,4
2,4
4
1
1
1 (2)
1 (2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2,4
2,4
1
2
1
2
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
TO, PD
None
Z
2,4
2,4
2,4
2,4
2,4
2,4
1,4
2,4
2,4
1,2,4
2,4
2,4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW
k
k
k
k
k
k
–
k
–
f
k
AND literal with W
Call subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
Exclusive OR Literal to W
1
3
Note 1: The 9th bit of the program counter will be forced to a ’0’ by any instruction that writes to the PC except for GOTO.
(Section 4.6)
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven
low by an external device, the data will be written back with a ’0’.
3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of
PORTB. A ’1’ forces the pin to a hi-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
(if assigned to TMR0).
DS40192C-page 40
 1999 Microchip Technology Inc.
PIC16C505
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
f,d
Status Affected: C, DC, Z
Encoding:
0001
Description:
Status Affected: Z
11df
ffff
Encoding:
0001
Add the contents of the W register
and register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
’1’, the result is stored back in register ’f’.
Description:
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example:
ADDWF
Example:
ANDWF
FSR, 0
Before Instruction
W
=
FSR =
W =
FSR =
After Instruction
W
=
FSR =
0xD9
0xC2
ANDLW
And literal with W
Syntax:
[ label ] ANDLW
Operands:
0 ≤ k ≤ 255
Operation:
(W).AND. (k) → (W)
k
Status Affected: Z
kkkk
1
Cycles:
1
Example:
ANDLW
0x5F
Before Instruction
W
kkkk
The contents of the W register are
AND’ed with the eight-bit literal 'k'.
The result is placed in the W register.
Words:
=
FSR,
1
0x17
0xC2
W
=
FSR =
Description:
ffff
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0, the
result is stored in the W register. If
'd' is '1', the result is stored back in
register 'f'.
After Instruction
1110
01df
Before Instruction
0x17
0xC2
Encoding:
f,d
0xA3
0x17
0x02
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 31
0≤b≤7
Operation:
0 → (f<b>)
f,b
Status Affected: None
Encoding:
0100
bbbf
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Example:
BCF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
After Instruction
W
=
0x03
 1999 Microchip Technology Inc.
DS40192C-page 41
PIC16C505
BSF
Bit Set f
Syntax:
[ label ] BSF
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BTFSS f,b
Operands:
0 ≤ f ≤ 31
0≤b≤7
Operands:
0 ≤ f ≤ 31
0≤b<7
Operation:
1 → (f<b>)
Operation:
skip if (f<b>) = 1
f,b
Status Affected: None
Encoding:
Status Affected: None
0101
bbbf
ffff
Description:
Bit ’b’ in register ’f’ is set.
Words:
1
Cycles:
1
Example:
BSF
FLAG_REG,
Encoding:
Description:
7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
0≤b≤7
Operation:
skip if (f<b>) = 0
0110
bbbf
ffff
If bit ’b’ in register ’f’ is ’1’, then the
next instruction is skipped.
If bit ’b’ is ’1’, then the next instruction fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a 2 cycle instruction.
Words:
1
Cycles:
1(2)
Example:
HERE
FALSE
TRUE
•
•
BTFSS
GOTO
•
FLAG,1
PROCESS_CODE
Before Instruction
PC
bbbf
ffff
Description:
If bit ’b’ in register ’f’ is 0, then the
next instruction is skipped.
If bit ’b’ is 0, then the next instruction fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a 2 cycle instruction.
Words:
1
Cycles:
1(2)
Example:
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
=
address (HERE)
=
=
=
=
0,
address (FALSE);
1,
address (TRUE)
After Instruction
Status Affected: None
Encoding:
0111
If FLAG<1>
PC
if FLAG<1>
PC
FLAG,1
PROCESS_CODE
Before Instruction
PC
=
address (HERE)
=
=
=
=
0,
address (TRUE);
1,
address(FALSE)
After Instruction
if FLAG<1>
PC
if FLAG<1>
PC
DS40192C-page 42
 1999 Microchip Technology Inc.
PIC16C505
CALL
Subroutine Call
CLRW
Clear W
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRW
Operands:
0 ≤ k ≤ 255
Operands:
None
Operation:
(PC) + 1→ Top of Stack;
k → PC<7:0>;
(STATUS<6:5>) → PC<10:9>;
0 → PC<8>
Operation:
00h → (W);
1→Z
Status Affected: None
Encoding:
Description:
1001
kkkk
kkkk
Subroutine call. First, return
address (PC+1) is pushed onto the
stack. The eight bit immediate
address is loaded into PC bits
<7:0>. The upper bits PC<10:9>
are loaded from STATUS<6:5>,
PC<8> is cleared. CALL is a two
cycle instruction.
Words:
1
Cycles:
2
Example:
HERE
CALL
THERE
Status Affected: Z
Encoding:
0000
0100
0000
Description:
The W register is cleared. Zero bit
(Z) is set.
Words:
1
Cycles:
1
Example:
CLRW
Before Instruction
W
=
0x5A
After Instruction
W
Z
=
=
0x00
1
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
After Instruction
Operands:
None
PC =
TOS =
Operation:
00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
Before Instruction
PC =
address (HERE)
address (THERE)
address (HERE + 1)
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 ≤ f ≤ 31
Operation:
00h → (f);
1→Z
Status Affected: TO, PD
f
Encoding:
Description:
0000
011f
Words:
1
Cycles:
1
Example:
CLRF
Words:
1
Cycles:
1
Example:
CLRWDT
Before Instruction
WDT counter =
FLAG_REG
Before Instruction
FLAG_REG
=
0x5A
=
=
0x00
1
After Instruction
FLAG_REG
Z
0100
The CLRWDT instruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
ffff
The contents of register ’f’ are
cleared and the Z bit is set.
0000
Description:
Status Affected: Z
Encoding:
0000
 1999 Microchip Technology Inc.
?
After Instruction
WDT counter
WDT prescale
TO
PD
=
=
=
=
0x00
0
1
1
DS40192C-page 43
PIC16C505
COMF
Complement f
Syntax:
[ label ] COMF
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) → (dest)
Operation:
(f) – 1 → d;
f,d
Status Affected: Z
Encoding:
Description:
Status Affected: None
0010
01df
ffff
The contents of register ’f’ are
complemented. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in register ’f’.
Words:
1
Cycles:
1
Example:
COMF
Encoding:
=
After Instruction
REG1
W
=
=
0x13
0xEC
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
1
Cycles:
1(2)
Example:
HERE
Description:
PC
1
Cycles:
1
Example:
DECF
Before Instruction
CNT
Z
=
=
0x01
0
After Instruction
CNT
Z
=
=
CNT, 1
LOOP
=
address (HERE)
After Instruction
11df
CNT
if CNT
PC
if CNT
PC
ffff
Decrement register 'f'. If 'd' is 0, the
result is stored in the W register. If
'd' is 1, the result is stored back in
register 'f'.
Words:
DECFSZ
GOTO
CONTINUE •
•
•
Before Instruction
Status Affected: Z
0000
ffff
Words:
(f) – 1 → (dest)
Encoding:
11df
The contents of register 'f' are decremented. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in register
'f'.
If the result is 0, the next instruction, which is already fetched, is
discarded and a NOP is executed
instead making it a two cycle
instruction.
REG1,0
0x13
0010
Description:
Before Instruction
REG1
skip if result = 0
CNT,
=
=
=
≠
=
CNT - 1;
0,
address (CONTINUE);
0,
address (HERE+1)
GOTO
Unconditional Branch
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 511
Operation:
k → PC<8:0>;
STATUS<6:5> → PC<10:9>
1
GOTO k
Status Affected: None
Encoding:
101k
kkkk
kkkk
Description:
GOTO is an unconditional branch.
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
STATUS<6:5>. GOTO is a two cycle
instruction.
Words:
1
Cycles:
2
Example:
GOTO THERE
0x00
1
After Instruction
PC =
DS40192C-page 44
address (THERE)
 1999 Microchip Technology Inc.
PIC16C505
INCF
Increment f
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) + 1 → (dest)
Operation:
(f) + 1 → (dest), skip if result = 0
INCF f,d
Status Affected: Z
Encoding:
Description:
Status Affected: None
0010
10df
ffff
The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in register
’f’.
Words:
1
Cycles:
1
Example:
INCF
CNT,
Encoding:
=
=
0xFF
0
After Instruction
CNT
Z
=
=
0x00
1
0011
11df
ffff
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in register
’f’.
If the result is 0, then the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead making it a two
cycle instruction.
Words:
1
Cycles:
1(2)
Example:
HERE
1
Before Instruction
CNT
Z
INCFSZ f,d
INCFSZ
GOTO
CONTINUE •
•
•
CNT,
LOOP
1
Before Instruction
PC
=
address (HERE)
After Instruction
CNT
if CNT
PC
if CNT
PC
 1999 Microchip Technology Inc.
=
=
=
≠
=
CNT + 1;
0,
address (CONTINUE);
0,
address (HERE +1)
DS40192C-page 45
PIC16C505
IORLW
Inclusive OR literal with W
MOVF
Move f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
(W) .OR. (k) → (W)
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) → (dest)
IORLW k
Status Affected: Z
Encoding:
1101
Description:
kkkk
kkkk
The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W register.
Words:
1
Cycles:
1
Example:
IORLW
W
=
0x9A
After Instruction
W
Z
=
=
Status Affected: Z
Encoding:
0xBF
0
Inclusive OR W with f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(W).OR. (f) → (dest)
IORWF
f,d
Status Affected: Z
00df
ffff
Description:
Inclusive OR the W register with
register 'f'. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in register
'f'.
Words:
1
Cycles:
1
Example:
IORWF
The contents of register 'f' are
moved to destination 'd'. If 'd' is 0,
destination is the W register. If 'd'
is 1, the destination is file register
'f'. 'd' = 1 is useful as a test of a file
register since status flag Z is
affected.
Words:
1
Cycles:
1
Example:
MOVF
RESULT =
W
=
FSR,
0
RESULT, 0
=
value in FSR register
MOVLW
Move Literal to W
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operation:
k → (W)
MOVLW k
Status Affected: None
Encoding:
1100
kkkk
kkkk
Description:
The eight bit literal 'k' is loaded into
the W register. The don’t cares
will assembled as 0s.
Words:
1
Cycles:
1
Example:
MOVLW
0x5A
After Instruction
W
Before Instruction
ffff
After Instruction
IORWF
0001
00df
Description:
W
Encoding:
0010
0x35
Before Instruction
MOVF f,d
=
0x5A
0x13
0x91
After Instruction
RESULT =
W
=
Z
=
DS40192C-page 46
0x13
0x93
0
 1999 Microchip Technology Inc.
PIC16C505
MOVWF
Move W to f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
Operands:
None
(W) → (f)
Operation:
(W) → OPTION
Operation:
MOVWF
f
0000
Load OPTION Register
Syntax:
[ label ]
001f
ffff
Description:
Move data from the W register to
register ’f’.
Words:
1
Cycles:
1
Example:
MOVWF
Encoding:
0000
Description:
TEMP_REG
Words:
1
Cycles:
1
OPTION
W
0xFF
0x4F
=
=
0x4F
0x4F
0010
Before Instruction
Before Instruction
=
=
0000
The content of the W register is
loaded into the OPTION register.
Example
TEMP_REG
W
OPTION
Status Affected: None
Status Affected: None
Encoding:
OPTION
=
0x07
After Instruction
OPTION =
0x07
After Instruction
TEMP_REG
W
RETLW
Return with Literal in W
Syntax:
[ label ]
RETLW k
NOP
No Operation
Operands:
0 ≤ k ≤ 255
Syntax:
[ label ]
Operation:
k → (W);
TOS → PC
NOP
Operands:
None
Operation:
No operation
Status Affected: None
Encoding:
Status Affected: None
Encoding:
0000
0000
Description:
No operation.
Words:
1
Cycles:
1
Example:
NOP
0000
1000
kkkk
kkkk
Description:
The W register is loaded with the
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
Words:
1
Cycles:
2
Example:
CALL TABLE ;W contains
;table offset
;value.
;W now has table
•
;value.
•
•
ADDWF PC
;W = offset
RETLW k1
;Begin table
RETLW k2
;
•
•
•
RETLW kn
; End of table
TABLE
Before Instruction
W
=
0x07
After Instruction
W
 1999 Microchip Technology Inc.
=
value of k8
DS40192C-page 47
PIC16C505
RLF
Rotate Left f through Carry
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
See description below
Operation:
See description below
RLF
f,d
Status Affected: C
Encoding:
Description:
Status Affected: C
0011
01df
C
1
Cycles:
1
Example:
RLF
=
=
REG1,0
DS40192C-page 48
=
=
=
Description:
0011
00df
ffff
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in register ’f’.
C
Words:
1
Cycles:
1
Example:
RRF
register ’f’
REG1,0
Before Instruction
1110 0110
0
After Instruction
REG1
W
C
Encoding:
register ’f’
Before Instruction
REG1
C
ffff
The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is stored back in register ’f’.
Words:
RRF f,d
REG1
C
=
=
1110 0110
0
After Instruction
1110 0110
1100 1100
1
REG1
W
C
=
=
=
1110 0110
0111 0011
0
 1999 Microchip Technology Inc.
PIC16C505
SLEEP
Syntax:
Enter SLEEP Mode
SUBWF
Subtract W from f
[label]
Syntax:
[label]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(f) – (W) → (dest)
SLEEP
Operands:
None
Operation:
00h → WDT;
0 → WDT prescaler;
1 → TO;
0 → PD
Status Affected: TO, PD, RBWUF
Encoding:
Description:
0000
0000
Words:
1
Cycles:
1
Example:
SLEEP
Status Affected: C, DC, Z
Encoding:
0000
10df
ffff
Description:
Subtract (2’s complement method)
the W register from register 'f'. If 'd'
is 0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
Words:
1
Cycles:
1
Example 1:
SUBWF
0011
Time-out status bit (TO) is set. The
power down status bit (PD) is
cleared.
RBWUF is unaffected.
The WDT and its prescaler are
cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See section on SLEEP for more
details.
SUBWF f,d
REG1, 1
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
REG1
W
C
=
=
=
1
2
1
; result is positive
Example 2:
Before Instruction
REG1
W
C
=
=
=
2
2
?
After Instruction
REG1
W
C
=
=
=
0
2
1
; result is zero
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
 1999 Microchip Technology Inc.
=
=
=
FF
2
0
; result is negative
DS40192C-page 49
PIC16C505
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[label]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Operation:
Operation:
(W) .XOR. k → (W)
Status Affected: Z
Encoding:
Status Affected: None
Encoding:
Description:
0011
10df
ffff
The upper and lower nibbles of
register ’f’ are exchanged. If ’d’ is
0, the result is placed in W register. If ’d’ is 1, the result is placed in
register ’f’.
Words:
1
Cycles:
1
Example
SWAPF
1111
kkkk
kkkk
Description:
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W register.
Words:
1
Cycles:
1
Example:
XORLW
0xAF
Before Instruction
REG1,
W
0
=
=
0xB5
After Instruction
Before Instruction
REG1
XORLW k
W
0xA5
=
0x1A
After Instruction
REG1
W
=
=
0xA5
0X5A
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS
Operands:
f=6
Operation:
(W) → TRIS register f
f
0000
0000
TRIS register ’f’ (f = 6 or 7) is
loaded with the contents of the W
register
Words:
1
Cycles:
1
TRIS
Before Instruction
W
=
=
[ label ] XORWF
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(W) .XOR. (f) → (dest)
PORTB
Encoding:
0001
10df
ffff
Description:
Exclusive OR the contents of the
W register with register 'f'. If 'd' is 0,
the result is stored in the W register. If 'd' is 1, the result is stored
back in register 'f'.
Words:
1
Cycles:
1
Example
XORWF
0XA5
REG
W
REG,1
=
=
0xAF
0xB5
After Instruction
REG
W
DS40192C-page 50
f,d
Before Instruction
0XA5
After Instruction
TRIS
Syntax:
0fff
Description:
Example
Exclusive OR W with f
Status Affected: Z
Status Affected: None
Encoding:
XORWF
=
=
0x1A
0xB5
 1999 Microchip Technology Inc.
PIC16C505
9.0
DEVELOPMENT SUPPORT
®
The PICmicro microcontrollers are supported with a
full range of hardware and software development tools:
• Integrated Development Environment
- MPLAB™ IDE Software
• Assemblers/Compilers/Linkers
- MPASM Assembler
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circuit
Emulator
- ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
- SEEVAL
- KEELOQ
9.1
MPLAB Integrated Development
Environment Software
• The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit
microcontroller market. MPLAB is a Windowsbased application which contains:
• Multiple functionality
- editor
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
• On-line help
 1999 Microchip Technology Inc.
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
- object code
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the ability to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
9.2
MPASM Assembler
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device programmers, or it can generate relocatable objects for
MPLINK.
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and generated machine code, and a COD file for MPLAB
debugging.
MPASM features include:
• MPASM and MPLINK are integrated into MPLAB
projects.
• MPASM allows user defined macros to be created
for streamlined assembly.
• MPASM allows conditional assembly for multi purpose source files.
• MPASM directives allow complete control over the
assembly process.
9.3
MPLAB-C17 and MPLAB-C18
C Compilers
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and integrated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compilers provide symbol information that is compatible with the
MPLAB IDE memory display.
DS40192C-page 51
PIC16C505
9.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with precompiled libraries using directives from a linker script.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many different applications. MPLIB manages the creation and
modification of library files.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
MPLIB features include:
• MPLIB makes linking easier because single libraries can be included instead of many smaller files.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
9.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Software Simulator offers the flexibility to develop and
debug code outside of the laboratory environment making it an excellent multi-project software development
tool.
9.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS40192C-page 52
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcontrollers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring features. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
9.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER systems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
9.8
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX families of 8-bit one-timeprogrammable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeable personality modules or daughter
boards. The emulator is capable of emulating without
target application circuitry being present.
9.9
MPLAB-ICD In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a powerful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F87X. This feature, along with Microchip’s In-Circuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
 1999 Microchip Technology Inc.
PIC16C505
9.10
PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
9.11
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
9.12
SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development system designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware simulation for Microchip’s PIC12C5XX, PIC12CE5XX, and
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system. In addition, the target system can provide input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entry-level system development.
9.13
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
 1999 Microchip Technology Inc.
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
9.14
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
9.15
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
DS40192C-page 53
PIC16C505
9.16
PICDEM-17
The PICDEM-17 is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 supports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emulator, and all of the sample programs can be run and
modified using either emulator. Additionally, a generous prototype area is available for user hardware.
9.17
SEEVAL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
9.18
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
DS40192C-page 54
 1999 Microchip Technology Inc.
 1999 Microchip Technology Inc.
Software Tools
Emulators
Programmers Debugger
á
á
á
PIC16C5X
á
á á á á
á
á
PIC14000
á
á á á
á
á
PIC12CXXX
á
á á á á
á
á
PICSTARTPlus
Low-Cost Universal Dev. Kit
PRO MATE II
Universal Programmer
á á
á
á
PIC16C8X
á
á á á á
á
á
PIC16C7XX
á
á á á á
á
á
PIC16C7X
á
á á á á
á
á
PIC16F62X
á
á á
PIC16CXXX
á
á á á á
PIC16C6X
á
á á á á
á
á
á
á
á á
á
á
á
á
á
á á
á
á
á
á á
á
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
† Development tool is available on select devices.
†
á
MCP2510 CAN Developer’s Kit
PIC16F8XX
á
†
MCRFXXX
á á á
13.56 MHz Anticollision microID
Developer’s Kit
á
125 kHz Anticollision microID
Developer’s Kit
á
125 kHz microID Developer’s Kit
á á á á
microID™ Programmer’s Kit
PIC16C9XX
á
KEELOQ Transponder Kit
á
KEELOQ® Evaluation Kit
á
PICDEM-17
á á á
á
PICDEM-14A
PIC17C4X
á á
á
†
á
PICDEM-3
á
á á á
**
24CXX/
25CXX/
93CXX
á
PICDEM-2
á
**
á
PICDEM-1
á á á
*
PIC17C7XX
á á
**
HCSXXX
á
SIMICE
MPLAB-ICD In-Circuit Debugger
ICEPIC Low-Cost
In-Circuit Emulator
PICMASTER/PICMASTER-CE
MPLAB™-ICE
MPASM/MPLINK
MPLAB C18 Compiler
PIC18CXX2
á
*
á
MPLAB C17 Compiler
TABLE 9-1:
Demo Boards and Eval Kits
MPLAB Integrated
Development Environment
PIC16C505
DEVELOPMENT TOOLS FROM MICROCHIP
MCP2510
á
DS40192C-page 55
PIC16C505
NOTES:
DS40192C-page 56
 1999 Microchip Technology Inc.
PIC16C505
10.0
ELECTRICAL CHARACTERISTICS - PIC16C505
Absolute Maximum Ratings†
Ambient Temperature under bias ........................................................................................................... –40°C to +125°C
Storage Temperature ............................................................................................................................. –65°C to +150°C
Voltage on VDD with respect to VSS ....................................................................................................................0 to +7 V
Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V
Voltage on all other pins with respect to VSS ............................................................................... –0.6 V to (VDD + 0.6 V)
Total Power Dissipation(1) ....................................................................................................................................700 mW
Max. Current out of VSS pin ..................................................................................................................................150 mA
Max. Current into VDD pin .....................................................................................................................................125 mA
Input Clamp Current, IIK (VI < 0 or VI > VDD).................................................................................................................... ±20 mA
Output Clamp Current, IOK (VO < 0 or VO > VDD)............................................................................................................. ±20 mA
Max. Output Current sunk by any I/O pin................................................................................................................25 mA
Max. Output Current sourced by any I/O pin...........................................................................................................25 mA
Max. Output Current sourced by I/O port .............................................................................................................100 mA
Max. Output Current sunk by I/O port ..................................................................................................................100 mA
Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
†NOTICE:
Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
 1999 Microchip Technology Inc.
DS40192C-page 57
PIC16C505
FIGURE 10-1: PIC16C505 VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 10-2: PIC16C505 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ 0°C, +70°C ≤ TA ≤ +125°C
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
DS40192C-page 58
 1999 Microchip Technology Inc.
PIC16C505
FIGURE 10-3: PIC16LC505 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
 1999 Microchip Technology Inc.
DS40192C-page 59
PIC16C505
10.1
DC CHARACTERISTICS:
PIC16C505-04 (Commercial, Industrial, Extended)
PIC16C505-20(Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
Power Supply Pins
Parm.
No.
Characteristic
Sym
Min
Typ(1)
Max
Units
Conditions
D001
Supply Voltage
VDD
3.0
5.5
V
See Figure 10-1 through Figure 10-3
D002
RAM Data Retention
Voltage(2)
VDR
—
1.5*
—
V
Device in SLEEP mode
D003
VDD Start Voltage to ensure
Power-on Reset
VPOR
—
VSS
—
V
See section on Power-on Reset for details
D004
VDD Rise Rate to ensure
Power-on Reset
SVDD
0.05*
—
—
V/ms
See section on Power-on Reset for details
D010
Supply Current(3)
IDD
—
—
—
—
—
—
0.8
0.6
3
4
4.5
19
1.4
1.0
7
12
16
27
mA
mA
mA
mA
mA
µA
FOSC = 4MHz, VDD = 5.5V, WDT disabled (Note 4)*
FOSC = 4MHz, VDD = 3.0V, WDT disabled (Note 4)
FOSC = 10MHz, VDD = 3.0V, WDT disabled (Note 6)
FOSC = 20MHz, VDD = 4.5V, WDT disabled
FOSC = 20MHz, VDD = 5.5V, WDT disabled*
FOSC = 32kHz, VDD = 3.0V, WDT disabled (Note 6)
D020
Power-Down Current (5)
IPD
—
—
—
—
0.25
0.4
3
5
4
5.5
8
14
µA
µA
µA
µA
VDD = 3.0V (Note 6)
VDD = 4.5V* (Note 6)
VDD = 5.5V, Industrial
VDD = 5.5V, Extended Temp.
D022
WDT Current(5)
∆IWDT
—
2.2
5
µA
VDD = 3.0V (Note 6)
1A
LP Oscillator Operating
Frequency
RC Oscillator Operating
Frequency
XT Oscillator Operating
Frequency
HS Oscillator Operating
Frequency
0
—
200
kHz
All temperatures
0
—
4
MHz
All temperatures
0
—
4
MHz
All temperatures
0
—
20
MHz
All temperatures
Fosc
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus
rate, internal code execution pattern and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD;
WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
4: Does not include current through Rext. The current through the resistor can be estimated by the formula:
IR = VDD/2Rext (mA) with Rext in kOhm.
5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in
SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
6: Commercial temperature range only.
DS40192C-page 60
 1999 Microchip Technology Inc.
PIC16C505
10.2
DC CHARACTERISTICS:
PIC16LC505-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
DC Characteristics
Power Supply Pins
Parm.
No.
Characteristic
Sym
Min
Typ(1)
Max
Units
Conditions
D001
Supply Voltage
VDD
2.5
—
5.5
V
See Figure 10-1 through Figure 10-3
D002
RAM Data Retention
Voltage(2)
VDR
—
1.5*
—
V
Device in SLEEP mode
D003
VDD Start Voltage to ensure
Power-on Reset
VPOR
—
VSS
—
V
See section on Power-on Reset for details
D004
VDD Rise Rate to ensure
Power-on Reset
SVDD
0.05*
—
—
V/ms
See section on Power-on Reset for details
D010
Supply Current(3)
IDD
—
0.8
1.4
mA
—
0.4
0.8
mA
—
15
23
µA
FOSC = 4MHz, VDD = 5.5V, WDT disabled
(Note 4)*
FOSC = 4MHz, VDD = 2.5V, WDT disabled
(Note 4)
FOSC = 32kHz, VDD = 2.5V, WDT disabled
(Note 6)
IPD
—
—
—
0.25
0.25
3
3
4
8
µA
µA
µA
VDD = 2.5V (Note 6)
VDD = 3.0V * (Note 6)
VDD = 5.5V Industrial
—
2.0
4
µA
VDD = 2.5V (Note 6)
0
—
200
kHz
All temperatures
0
—
4
MHz
All temperatures
0
—
4
MHz
All temperatures
0
—
4
MHz
All temperatures
D020
Power-Down Current (5)
D022
WDT Current(5)
∆IWDT
1A
LP Oscillator Operating
Frequency
RC Oscillator Operating
Frequency
XT Oscillator Operating
Frequency
HS Oscillator Operating
Frequency
FOSC
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type,
bus rate, internal code execution pattern and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD;
WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
4: Does not include current through Rext. The current through the resistor can be estimated by the formula:
IR = VDD/2Rext (mA) with Rext in kOhm.
5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
6: Commercial temperature range only.
 1999 Microchip Technology Inc.
DS40192C-page 61
PIC16C505
10.3
DC CHARACTERISTICS:
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
with Schmitt Trigger buffer
D032
MCLR, RC5/T0CKI
(in EXTRC mode)
D033
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
D040
with TTL buffer
D040A
D041
D042
D042A
D043
D070
D060
with Schmitt Trigger buffer
MCLR, RC5/T0CKI
OSC1 (XT, HS and LP)
OSC1 (in EXTRC mode)
GPIO weak pull-up current (Note 4)
Input Leakage Current (Notes 2, 3)
I/O ports
PIC16C505-04 (Commercial, Industrial, Extended)
PIC16C505-20(Commercial, Industrial, Extended)
PIC16LC505-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating voltage VDD range as described in DC spec Section 10.1 and
Section 10.3.
Sym
Min
Typ† Max Units
Conditions
VIL
Output Low Voltage
I/O ports/CLKOUT
D080A
D083
OSC2
D083A
†
Note 1:
2:
3:
4:
5:
6:
—
—
—
—
0.8V
0.15VDD
0.2VDD
0.2VDD
V
V
V
V
For all 4.5 ≤ VDD ≤ 5.5V
otherwise
VSS
—
0.3VDD
V
Note1
—
—
—
VDD
VDD
V
V
4.5 ≤ VDD ≤ 5.5V
VDD
VDD
VDD
VDD
400
otherwise
V For entire VDD range
V
V Note1
V
µA VDD = 5V, VPIN = VSS
VIH
IPUR
IIL
D061
GP3/MCLRI (Note 5)
D061A GP3/MCLRI (Note 6)
D063
OSC1
D080
VSS
VSS
VSS
VSS
VOL
2.0
0.25VDD
+ 0.8VDD
—
0.8VDD
—
0.8VDD
—
0.7VDD
—
0.9VDD
50
250
µA Vss ≤ VPIN ≤ VDD, Pin at
hi-impedance
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
—
—
±1
—
—
—
—
—
—
±30
±5
±5
—
—
0.6
V
—
—
0.6
V
—
—
0.6
V
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V,
–40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
–40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
–40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
–40°C to +125°C
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C505
be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
Does not include GP3. For GP3 see parameters D061 and D061A.
This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit
is higher than the standard I/O logic.
DS40192C-page 62
 1999 Microchip Technology Inc.
PIC16C505
DC CHARACTERISTICS
Param
No.
Characteristic
Output High Voltage
I/O ports/CLKOUT (Note 3)
D090
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating voltage VDD range as described in DC spec Section 10.1 and
Section 10.3.
Sym
Min
Typ† Max Units
Conditions
VOH
VDD - 0.7
—
—
V
VDD - 0.7
—
—
V
VDD - 0.7
—
—
V
VDD - 0.7
—
—
V
COSC2
—
—
15
pF
CIO
—
—
50
pF
D090A
D092
OSC2
D092A
D100
Capacitive Loading Specs on
Output Pins
OSC2 pin
D101
All I/O pins and OSC2
†
Note 1:
2:
3:
4:
5:
6:
IOH = -3.0 mA, VDD = 4.5V,
–40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
–40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
–40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
–40°C to +125°C
In XT, HS and LP modes when
external clock is used to drive
OSC1.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C505
be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
Does not include GP3. For GP3 see parameters D061 and D061A.
This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit
is higher than the standard I/O logic.
 1999 Microchip Technology Inc.
DS40192C-page 63
PIC16C505
TABLE 10-1:
VDD (Volts)
PULL-UP RESISTOR RANGES - PIC16C505
Temperature (°C)
Min
–40
25
85
125
–40
25
85
125
38K
42K
42K
50K
15K
18K
19K
22K
–40
25
85
125
–40
25
85
125
285K
343K
368K
431K
247K
288K
306K
351K
Typ
Max
Units
42K
48K
49K
55K
17K
20K
22K
24K
63K
63K
63K
63K
20K
23K
25K
28K
W
W
W
W
W
W
W
W
346K
414K
457K
504K
292K
341K
371K
407K
417K
532K
532K
593K
360K
437K
448K
500K
W
W
W
W
W
W
W
W
RB0/RB1/RB4
2.5
5.5
RB3
2.5
5.5
*
These parameters are characterized but not tested.
DS40192C-page 64
 1999 Microchip Technology Inc.
PIC16C505
10.4
Timing Parameter Symbology and Load Conditions - PIC16C505
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase subscripts (pp) and their meanings:
pp
2
to
mc
MCLR
ck
CLKOUT
osc
oscillator
cy
cycle time
os
OSC1
drt
device reset timer
t0
T0CKI
io
I/O port
wdt
watchdog timer
Uppercase letters and their meanings:
S
F
Fall
P
Period
H
High
R
Rise
I
Invalid (Hi-impedance)
V
Valid
L
Low
Z
Hi-impedance
FIGURE 10-4: LOAD CONDITIONS - PIC16C505
Pin
CL = 50 pF for all pins except OSC2
CL
VSS
 1999 Microchip Technology Inc.
15 pF for OSC2 in XT, HS or LP
modes when external clock
is used to drive OSC1
DS40192C-page 65
PIC16C505
10.5
Timing Diagrams and Specifications
FIGURE 10-5: EXTERNAL CLOCK TIMING - PIC16C505
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
TABLE 10-2:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505
AC Characteristics
Parameter
No.
1A
Sym
FOSC
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Characteristic
External CLKIN Frequency(2)
Oscillator Frequency(2)
1
TOSC
External CLKIN Period(2)
Oscillator Period
2
TCY
(2)
Instruction Cycle Time
Min
Typ(1)
Max
DC
—
4
MHz XT osc mode
DC
—
4
MHz HS osc mode
(PIC16C505-04)
DC
—
20
MHz HS osc mode
(PIC16C505-20)
DC
—
200
DC
—
4
Units
kHz
Conditions
LP osc mode
MHz EXTRC osc mode
0.1
—
4
MHz XT osc mode
4
—
4
MHz HS osc mode
(PIC16C505-04)
DC
—
200
kHz
LP osc mode
250
—
—
ns
XT osc mode
50
—
—
ns
HS osc mode
(PIC16C505-20)
—
—
µs
LP osc mode
250
—
—
ns
EXTRC osc mode
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS ocs mode
(PIC16C505-04)
50
—
250
ns
HS ocs mode
(PIC16C505-20)
LP osc mode
5
—
—
µs
—
4/FOSC
DC
ns
200
—
ns
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
DS40192C-page 66
 1999 Microchip Technology Inc.
PIC16C505
TABLE 10-2:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505 (CONTINUED)
AC Characteristics
Parameter
No.
3
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Sym
TosL, TosH
Characteristic
Clock in (OSC1) Low or High Time
Min
Typ(1)
Max
Units
50*
—
—
ns
XT oscillator
2*
—
—
µs
LP oscillator
ns
HS oscillator
10
4
TosR, TosF
Clock in (OSC1) Rise or Fall Time
Conditions
—
—
25*
ns
XT oscillator
—
—
50*
ns
LP oscillator
—
—
15
ns
HS oscillator
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
TABLE 10-3:
CALIBRATED INTERNAL RC FREQUENCIES - PIC16C505
AC Characteristics
Parameter
No.
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Min*
Typ(1)
Internal Calibrated RC Frequency
3.65
4.00
4.28
MHz VDD = 5.0V
Internal Calibrated RC Frequency
3.55
4.00
4.31
MHz VDD = 2.5V
Sym
Characteristic
Max* Units
Conditions
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
 1999 Microchip Technology Inc.
DS40192C-page 67
PIC16C505
FIGURE 10-6:
I/O TIMING - PIC16C505
Q1
Q4
Q2
Q3
OSC1
I/O Pin
(input)
17
I/O Pin
(output)
19
18
New Value
Old Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 10-4:
TIMING REQUIREMENTS - PIC16C505
AC Characteristics
Parameter
No.
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Sym
Characteristic
valid(2,3)
Min
Typ(1)
Max
Units
—
—
100*
ns
17
TosH2ioV
OSC1↑ (Q1 cycle) to Port out
18
TosH2ioI
OSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time)(2)
TBD
—
—
ns
19
TioV2osH
Port input valid to OSC1↑
(I/O in setup time)
TBD
—
—
ns
20
TioR
Port output rise time(3)
—
10
25**
ns
—
10
25**
ns
21
TioF
Port output fall
time(3)
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 10-4 for loading conditions.
DS40192C-page 68
 1999 Microchip Technology Inc.
PIC16C505
FIGURE 10-7: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C505
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Timeout
(Note 2)
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1:
I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
Runs in MCLR or WDT reset only in XT, LP and HS modes.
2:
TABLE 10-5:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C505
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Parameter
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
2000*
—
—
ns
VDD = 5.0 V
Conditions
30
TmcL
MCLR Pulse Width (low)
31
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
9*
18*
30*
ms
VDD = 5.0 V (Commercial)
32
TDRT
Device Reset Timer Period(2)
9*
18*
30*
ms
VDD = 5.0 V (Commercial)
34
TioZ
I/O Hi-impedance from MCLR Low
—
—
2000*
ns
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
TABLE 10-6:
DRT (DEVICE RESET TIMER PERIOD - PIC16C505
Oscillator Configuration
POR Reset
Subsequent Resets
IntRC & ExtRC
18 ms (typical)
300 µs (typical)
XT, HS & LP
18 ms (typical)
18 ms (typical)
 1999 Microchip Technology Inc.
DS40192C-page 69
PIC16C505
FIGURE 10-8: TIMER0 CLOCK TIMINGS - PIC16C505
T0CKI
40
41
42
TABLE 10-7:
TIMER0 CLOCK REQUIREMENTS - PIC16C505
AC Characteristics
Parm
Sym
No.
40
Tt0H
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1.
Characteristic
T0CKI High Pulse Width
No Prescaler
With Prescaler
41
Tt0L
T0CKI Low Pulse Width
No Prescaler
With Prescaler
42
Tt0P
T0CKI Period
Min
Typ(1) Max Units
0.5 TCY + 20*
—
—
ns
10*
—
—
ns
0.5 TCY + 20*
—
—
ns
10*
—
—
ns
20 or TCY + 40* N
—
—
ns
Conditions
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS40192C-page 70
 1999 Microchip Technology Inc.
PIC16C505
DC AND AC
CHARACTERISTICS PIC16C505
The graphs and tables provided in this section are for
design guidance and are not tested. In some graphs or
tables the data presented are outside specified
operating range (e.g., outside specified VDD range).
This is for information only and devices will operate
properly only within the specified range.
The data presented in this section is a statistical
summary of data collected on units from different lots
over a period of time. “Typical” represents the mean of
the distribution while “max” or “min” represents (mean
+ 3σ) and (mean – 3σ) respectively, where σ is
standard deviation.
FIGURE 11-1: CALIBRATED INTERNAL RC
FREQUENCY RANGE VS.
TEMPERATURE (VDD = 5.0V)
(INTERNAL RC IS
CALIBRATED TO 25°C, 5.0V)
4.50
4.50
4.40
4.30
Max.
4.20
4.10
4.00
3.90
3.80
3.70
4.40
3.60
4.30
3.50
-40
4.20
Frequency (MHz)
FIGURE 11-2: CALIBRATED INTERNAL RC
FREQUENCY RANGE VS.
TEMPERATURE (VDD = 2.5V)
(INTERNAL RC IS
CALIBRATED TO 25°C, 5.0V)
Frequency (MHz)
11.0
Min.
0
25
85
125
Temperature (Deg.C)
Max.
4.10
4.00
3.90
3.80
Min.
3.70
3.60
3.50
-40
0
25
85
125
Temperature (Deg.C)
 1999 Microchip Technology Inc.
DS40192C-page 71
PIC16C505
TABLE 11-1:
DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C
Oscillator
External RC
Internal RC
XT
LP
HS
Note 1:
2:
Frequency
VDD = 3.0V(1)
VDD = 5.5V
4 MHz
4 MHz
4 MHz
32 kHz
20 MHz
240 µA(2)
320 µA
300 µA
19 µA
N/A
800 µA(2)
800 µA
800 µA
50 µA
4.5 mA
LP oscillator based on VDD = 2.5V
Does not include current through external R&C.
FIGURE 11-4: SHORT DRT PERIOD VS. VDD
FIGURE 11-3: WDT TIMER TIME-OUT
PERIOD vs. VDD
950
55
850
50
750
45
WDT period (µS)
35
Max +125°C
30
Max +85°C
WDT period (µs)
650
40
550
Max +125°C
450
Max +85°C
350
Typ +25°C
25
250
20
MIn –40°C
Typ +25°C
150
15
MIn –40°C
0
0
10
0
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VDD (Volts)
VDD (Volts)
DS40192C-page 72
 1999 Microchip Technology Inc.
PIC16C505
FIGURE 11-5: IOH vs. VOH, VDD = 2.5 V
FIGURE 11-7: IOL vs. VOL, VDD = 2.5 V
25
0
-1
20
Max –40°C
15
-3
IOL (mA)
IOH (mA)
-2
-4
10
125°C
Min +
-5
-6
Typ +25°C
Min +85°C
85°C
Min +
Min +125°C
5
Typ +25°C
C
Max –40°
-7
500m
1.0
1.5
2.0
2.5
0
VOH (Volts)
0
250.0m
500.0m
1.0
VOL (Volts)
FIGURE 11-6: IOH vs. VOH, VDD = 5.5 V
FIGURE 11-8: IOL vs. VOL, VDD = 5.5 V
0
50
-5
Max –40°C
40
30
-20
in
°C
25
+1
Min +85°C
20
Min +125°C
10
M
ax
-25
–4
0°
C
Ty
p
+2
5
M
°C
in
M
Typ +25°C
IOL (mA)
-15
+8
5°
C
IOH (mA)
-10
-30
3.5
4.0
4.5
VOH (Volts)
5.0
5.5
0
250.0m
500.0m
750.0m
1.0
VOL (Volts)
 1999 Microchip Technology Inc.
DS40192C-page 73
PIC16C505
NOTES:
DS40192C-page 74
 1999 Microchip Technology Inc.
PIC16C505
11.0
PACKAGING INFORMATION
11.1
Package Marking Information
14-Lead PDIP (300 mil)
Example
16C505-04I/P
BUILT 4 SPEED
9904SAZ
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
AABBCDE
Example
14-Lead SOIC (150 mil)
16C505-04I
9904SAZ
XXXXXXXXXX
AABBCDE
14-Lead Windowed Ceramic (300 mil)
JW
XXX
16C505
XXXXXX
Legend: MM...M
XX...X
AA
BB
C
D
E
Note:
*
Example
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
 1999 Microchip Technology Inc.
DS40192C-page 75
PIC16C505
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
eB
p
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.740
.750
.760
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
eB
Overall Row Spacing
.310
.370
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS40192C-page 76
MAX
4.32
3.68
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
15
 1999 Microchip Technology Inc.
PIC16C505
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
L
β
Units
Dimension Limits
n
p
MIN
A1
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MIN
Number of Pins
Pitch
Overall Height
A
.053
.069
Molded Package Thickness
A2
.052
.061
Standoff
A1
.004
.010
Overall Width
E
.228
.244
Molded Package Width
E1
.150
.157
Overall Length
D
.337
.347
Chamfer Distance
h
.010
.020
Foot Length
L
.016
.050
φ
Foot Angle
0
8
c
Lead Thickness
.008
.010
Lead Width
B
.014
.020
α
Mold Draft Angle Top
0
15
β
Mold Draft Angle Bottom
0
15
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
 1999 Microchip Technology Inc.
MAX
1.75
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
0.25
0.51
15
15
DS40192C-page 77
PIC16C505
14-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil
E1
W
T
D
2
n
1
U
A
A2
L
A1
c
B1
eB
p
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Top of Body to Seating Plane
Standoff
Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Diameter
Lid Length
Lid Width
*Controlling Parameter
A
A2
A1
E1
D
L
c
B1
B
eB
W
T
U
INCHES*
NOM
14
.100
.142
.162
.100
.120
.025
.035
.280
.290
.693
.700
.130
.140
.008
.010
.052
.054
.016
.018
.296
.310
.161
.166
.440
.450
.260
.270
MIN
MAX
.182
.140
.045
.300
.707
.150
.012
.056
.020
.324
.171
.460
.280
MILLIMETERS
NOM
14
2.54
3.61
4.11
2.54
3.05
0.64
0.89
7.11
7.37
17.60
17.78
3.30
3.56
0.20
0.25
1.32
1.37
0.41
0.46
7.52
7.87
4.09
4.22
11.18
11.43
6.60
6.86
MIN
MAX
4.62
3.56
1.14
7.62
17.96
3.81
0.30
1.42
0.51
8.23
4.34
11.68
7.11
JEDEC Equivalent: MS-015
Drawing No. C04-107
DS40192C-page 78
 1999 Microchip Technology Inc.
PIC16C505
INDEX
A
ALU ....................................................................................... 7
Applications........................................................................... 3
Architectural Overview .......................................................... 7
Assembler
MPASM Assembler..................................................... 51
B
Block Diagram
On-Chip Reset Circuit ................................................. 33
Timer0......................................................................... 23
TMR0/WDT Prescaler................................................. 26
Watchdog Timer.......................................................... 35
Brown-Out Protection Circuit .............................................. 36
C
CAL0 bit .............................................................................. 16
CAL1 bit .............................................................................. 16
CAL2 bit .............................................................................. 16
CAL3 bit .............................................................................. 16
CALFST bit ......................................................................... 16
CALSLW bit ........................................................................ 16
Carry ..................................................................................... 7
Clocking Scheme ................................................................ 10
Code Protection ............................................................ 27, 37
Configuration Bits................................................................ 27
Configuration Word ............................................................. 27
Oscillator Types
HS............................................................................... 28
LP ............................................................................... 28
RC .............................................................................. 28
XT ............................................................................... 28
P
Package Marking Information ............................................. 75
Packaging Information ........................................................ 75
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 53
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 53
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 53
PICSTART Plus Entry Level Development System ......... 53
POR
Device Reset Timer (DRT) ................................... 27, 34
PD............................................................................... 36
Power-On Reset (POR) .............................................. 27
TO............................................................................... 36
PORTB ............................................................................... 19
Power-Down Mode ............................................................. 37
Prescaler ............................................................................ 26
PRO MATE II Universal Programmer .............................. 53
Program Counter ................................................................ 17
Q
Q cycles .............................................................................. 10
R
DC and AC Characteristics ................................................. 71
Development Support ......................................................... 51
Device Varieties .................................................................... 5
Digit Carry ............................................................................. 7
RC Oscillator....................................................................... 29
Read Modify Write .............................................................. 20
Register File Map................................................................ 12
Registers
Special Function ......................................................... 13
Reset .................................................................................. 27
Reset on Brown-Out ........................................................... 36
E
S
Errata .................................................................................... 2
SEEVAL Evaluation and Programming System .............. 54
SLEEP .......................................................................... 27, 37
Software Simulator (MPLAB-SIM) ...................................... 52
Special Features of the CPU .............................................. 27
Special Function Registers ................................................. 13
Stack................................................................................... 17
STATUS ............................................................................... 7
STATUS Register ............................................................... 14
D
F
Family of Devices
PIC16C505 ................................................................... 4
FSR ..................................................................................... 18
I
I/O Interfacing ..................................................................... 19
I/O Ports .............................................................................. 19
I/O Programming Considerations........................................ 20
ID Locations .................................................................. 27, 37
INDF.................................................................................... 18
Indirect Data Addressing..................................................... 18
Instruction Cycle ................................................................. 10
Instruction Flow/Pipelining .................................................. 10
Instruction Set Summary..................................................... 40
K
KeeLoq Evaluation and Programming Tools.................... 54
L
Loading of PC ..................................................................... 17
M
Memory Organization.......................................................... 11
Data Memory .............................................................. 12
Program Memory ........................................................ 11
MPLAB Integrated Development Environment Software .... 51
T
Timer0
Switching Prescaler Assignment ................................ 26
Timer0 ........................................................................ 23
Timer0 (TMR0) Module .............................................. 23
TMR0 with External Clock .......................................... 25
Timing Diagrams and Specifications .................................. 66
Timing Parameter Symbology and Load Conditions .......... 65
TRIS Registers ................................................................... 19
W
Wake-up from SLEEP......................................................... 37
Watchdog Timer (WDT)................................................ 27, 34
Period ......................................................................... 35
Programming Considerations ..................................... 35
WWW, On-Line Support ....................................................... 2
Z
Zero bit ................................................................................. 7
O
OPTION Register ................................................................ 15
OSC selection ..................................................................... 27
OSCCAL Register ............................................................... 16
Oscillator Configurations ..................................................... 28
 1999 Microchip Technology Inc.
DS40192B-page 79
PIC16C505
NOTES:
DS40192B-page 80
 1999 Microchip Technology Inc.
PIC16C505
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
981103
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems, technical information and more
• Listing of seminars and events
 1999 Microchip Technology Inc.
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER and PRO MATE are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of
Microchip in the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
DS40192C-page 81
PIC16C505
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC16C505
Y
N
Literature Number: DS40192C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40192C-page 82
 1999 Microchip Technology Inc.
PIC16C505
PIC16C505 Product Identification System
Examples
PART NO. -XX X /XX XXX
Pattern:
Special Requirements
Package:
SL
P
JW
= 150 mil SOIC
= 300 mil PDIP
= 300 mil Windowed Ceramic Side Brazed
Temperature
Range:
I
E
= 0°C to +70°C
= -40°C to +85°C
= -40°C to +125°C
Frequency
Range:
04
20
= 4 MHz (XT, INTRC, EXTRC OSC)
= 20 MHz (HS OSC)
Device
PIC16C505
PIC16LC505
PIC16C505T (Tape & reel for SOIC only)
PIC16LC505T (Tape & reel for SOIC only)
a)
PIC16C505-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
b)
PIC16C505-04I/SL
Industrial Temp., SOIC
package, 4 MHz, normal
VDD limits
c)
PIC16C505-04I/P
Industrial Temp.,
PDIP package, 4 MHz,
normal VDD limits
Please contact your local sales office for exact ordering procedures.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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 1999 Microchip Technology Inc.
DS40192C-page 83
Note the following details of the code protection feature on PICmicro® MCUs.
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•
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The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
 2002 Microchip Technology Inc.
M
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Japan
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Microchip Technology Japan K.K.
Benex S-1 6F
3-18-20, Shinyokohama
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Rocky Mountain
China - Beijing
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
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Tel: 248-538-2250 Fax: 248-538-2260
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Los Angeles
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Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
China - Chengdu
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-6766200 Fax: 86-28-6766599
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd., Fuzhou Liaison Office
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
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Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Rm. 1315, 13/F, Shenzhen Kerry Centre,
Renminnan Lu
Shenzhen 518001, China
Tel: 86-755-2350361 Fax: 86-755-2366086
San Jose
Hong Kong
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
New York
Toronto
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Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc.
India Liaison Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Korea
Microchip Technology Korea
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Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan
Microchip Technology Taiwan
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Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Microchip Technology SRL
Centro Direzionale Colleoni
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Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
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Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02
 2002 Microchip Technology Inc.
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