AOZ8802A Ultra-Low Capacitance TVS Diode Array General Description

AOZ8802A Ultra-Low Capacitance TVS Diode Array  General Description
AOZ8802A
Ultra-Low Capacitance TVS Diode Array
General Description
Features
The AOZ8802A is a transient voltage suppressor array
designed to protect high speed data lines such as HDMI,
MDDI, USB, SATA, and Gigabit Ethernet from damaging
ESD events.
z ESD protection for high-speed data lines:
This device incorporates four surge rated, low
capacitance steering diodes and a TVS in a single
package. During transient conditions, the steering diodes
direct the transient to either the positive side of the power
supply line or to ground.
The AOZ8802A provides a typical line to line capacitance
of 0.3pF and low insertion loss up to 6GHz providing
greater signal integrity making it ideally suited for HDMI
1.3 applications, such as Digital TVs, DVD players,
set-top boxes and USB applications in mobile
computing devices.
The AOZ8802A comes in a RoHS compliant and Halogen
Free 1.6mm x 1.0mm x 0.55mm DFN-6 package and is
rated -40°C to +85°C junction temperature range.
– IEC 61000-4-2, level 4 (ESD) immunity test
– Air discharge: ±15kV; Contact discharge: ±15kV
– IEC61000-4-4 (EFT) 40A (5/50nS)
– IEC61000-4-5 (Lightning) 2.5A (8/20µS)
– Human Body Model (HBM) ±24kV
z Array of surge rated diodes with internal TVS diode
z Small package saves board space
z Protects two I/O lines
z Low capacitance between I/O lines: 0.3pF
z Low clamping voltage
z Low operating voltage: 5.0V
Applications
z USB, MDDI, SATA ports
z Monitors and flat panel displays
z Set-top box
z Video graphics cards
z Digital Video Interface (DVI)
z Notebook computers
Typical Application
Vbus
+5V
USB 2.0
Controller
D+
D+
D-
D-
AOZ8802A
USB 2.0
Port
GND
Figure 1. USB Port
Rev. 1.0 October 2010
www.aosmd.com
Page 1 of 9
AOZ8802A
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ8802ADI
-40°C to +85°C
DFN-6
Green Product
RoHS Compliant
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
CH1
1
6
NC
CH2
2
5
NC
VN
3
4
VN
DFN-6
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
Storage Temperature (TS)
-65°C to +150°C
ESD Rating per IEC61000-4-2, contact
(1)
±15kV
ESD Rating per IEC61000-4-2, air(1)
ESD Rating per Human Body Model
±15kV
(2)
±24kV
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ.
Maximum Operating Ratings
Parameter
Rating
Junction Temperature (TJ)
Rev. 1.0 October 2010
-40°C to +125°C
www.aosmd.com
Page 2 of 9
AOZ8802A
Electrical Characteristics
TA = 25°C unless otherwise specified.
Symbol
Parameter
Diagram
IPP
Maximum Reverse Peak Pulse Current
VCL
Clamping Voltage @ IPP
VRWM
IR
VBR
IF
Working Peak Reverse Voltage
Maximum Reverse Leakage Current
Breakdown Voltage
IF
Forward Current
VF
Forward Voltage
PPK
Peak Power Dissipation
CJ
I
VCL VBR VRWM
V
IR VF
IT
IPP
Max. Capacitance @ VR = 0 and f = 1MHz
Specifications in BOLD indicate a temperature range of -40°C to +85°C.
Symbol
VRWM
VBR
Parameter
Reverse Working Voltage
Conditions
VN(4)
IT = 1mA, between I/O and
IR
Reverse Leakage Current
VRWM = 5V, between I/O and VN
VF
Diode Forward Voltage
IF = 15mA
Cj
Typ.
Max.
Units
5.0
V
Between I/O and VN(3)
Reverse Breakdown Voltage
VCL
Min.
6.0
0.70
V
0.85
1
µA
1
V
12
-3
V
V
14
-5
V
V
16.5
-7
V
V
Ground(5)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 1A, tp = 100ns, any I/O pin to
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 5A, tp = 100ns, any I/O pin to Ground(5)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 12A, tp = 100ns, any I/O pin to Ground(5)
Channel Input Capacitance
VR = 0V, f = 1MHz, between I/O pins
0.30
0.35
pF
VR = 0V, f = 1MHz, any I/O pin to Ground
0.60
0.75
pF
Notes:
3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
4. VBR is measured at the pulse test current IT.
5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.
Rev. 1.0 October 2010
www.aosmd.com
Page 3 of 9
AOZ8802A
Typical Performance Characteristics
Forward Voltage vs. Forward Peak Pulse Current
I/O – Gnd Insertion Loss (S21) vs. Frequency
(tperiod = 100ns, tr = 1ns)
8
0.00E+00
-5.00E+00
6
5
S21 (dB)
Forward Voltage (V)
7
4
3
-1.00E+01
-1.50E+01
-2.00E+01
2
-2.50E+01
1
-3.00E+01
0
0
2
4
6
8
10
Forward Current, IPP (A)
12
14
1
1000
10000
Analog Crosstalk (I/O–I/O) vs. Frequency
(tperiod = 100ns, tr = 1ns)
0
16
-20
Insertion Loss (dB)
Clamping Voltage, VCL (V)
100
Frequency (MHz)
Clamping Voltage vs. Peak Pulse Current
18
10
14
12
10
8
6
-40
-60
-80
-100
4
-120
2
0
2
4
6
8
10
Peak Puse Current, IPP (A)
Rev. 1.0 October 2010
12
14
1
10
100
1000
10000
Frequency (MHz)
www.aosmd.com
Page 4 of 9
AOZ8802A
Protecting USB Ports from ESD
Because electrostatic discharge (ESD) is common in
electronic systems, a device that provides protection
from the undesirable effects of ESD must be included in
the system design. Designing ESD protection structures
is becoming more and more challenging with the system
bus and I/O operating more often at high-speed data
rates. An Integrated Circuit (IC) connected to external
ports can be damaged by ESD from the operating
environment. The result of ever-shrinking IC process
technology is the decrease of ESD robustness because
of the smaller geometry of the silicon die.
Since USB is a hot insertion and removal system, the
USB components are subjected to ESD and cable
discharge event more frequently. Traditional methods of
ESD protection include metal oxide varistors (MOVs),
and regular CMOS or bipolar clamping diodes. At higher
data rates the parasitic characteristics of those devices
can cause distortion, deterioration and data loss of the
signal integrity. AOZ8802A offers ESD protection for
high-speed data rates and for diode array chips for ease
of design.
The very low 0.6pF (typical) line capacitance of the
AOZ8802A ensures less distortion of the 480 Mbit/s
USB 2.0 signal; the chips also protect against
electrostatic discharge up to the stringent IEC61000-4-2
level 4, 8kV (Contact Discharge) and 15kV standard
(Air Discharge). They also provide ultra low matching
capacitance to help improve the signal quality of
differential data lines. Monolithic integration provides
high device reliability, and an optimized pin-out allows
EMI-free board layouts. Figure 2 illustrates the flow
through design of the PCB layout with the AOZ8802A
package design. The pinout of the AOZ8802A is
designed to simply drop onto the IO lines of a USB 2.0
design without having to divert the signal lines that may
add more parasitic inductance. Pins 1, 2 & 3 is connected
to the internal TVS devices and ground. and pins 4, 5, 6
are no connects. The no connects is in place so the
package can be securely soldered onto the PCB surface.
D+
D+
D-
D-
Ground
Ground
Figure 2. Flow-through Layout
Rev. 1.0 October 2010
www.aosmd.com
Page 5 of 9
AOZ8802A
USB 2.0 PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8802A devices should be located as close as
possible to the noise source. The placement of the
AOZ8802A devices should be used on all data and
power lines that enter or exit the PCB at the I/O
connector. In most systems, surge pulses occur on data
and power lines that enter the PCB through the I/O
connector. Placing the AOZ8802A devices as close as
possible to the noise source ensures that a surge voltage
will be clamped before the pulse can be coupled into
adjacent PCB traces. In addition, the PCB should use the
shortest possible traces. A short trace length equates to
low impedance, which ensures that the surge energy will
be dissipated by the AOZ8802A device. Long signal
traces will act as antennas to receive energy from fields
Rev. 1.0 October 2010
that are produced by the ESD pulse. By keeping line
lengths as short as possible, the efficiency of the line to
act as an antenna for ESD related fields is reduced.
Minimize interconnecting line lengths by placing devices
with the most interconnect as close together as possible.
The protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design.
www.aosmd.com
Page 6 of 9
AOZ8802A
Package Dimensions, DFN-6 1.6mm x 1.0mm x 0.55mm
e
D
b
b1
L
E
3
Pin #1 Dot
by Marking
TOP VIEW
Pin #3 Identification R 0.130
2
1
e
BOTTOM VIEW
A
c
A1
Dimensions in millimeters
SIDE VIEW
RECOMMENDED LAND PATTERN
0.40
0.20
0.50
0.36
Symbols
A
A1
b
b1
c
D
E
e
L
Min.
0.50
0.00
0.15
Nom.
0.55
—
0.20
0.40
0.152 Ref.
1.55
1.60
0.95
1.00
0.50 BSC
0.33
0.38
Max.
0.60
0.05
0.25
1.65
1.05
0.43
Dimensions in inches
Symbols
A
A1
b
b1
c
D
E
e
L
Min.
0.020
0.000
0.006
Nom. Max.
0.022 0.024
—
0.002
0.008 0.010
0.016
0.006 Ref.
0.061 0.063 0.065
0.037 0.039 0.041
0.020 BSC
0.013 0.015 0.017
1.20
0.72
0.24
0.48
0.50
0.30
0.10
UNIT: mm
0.15
Note:
1. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
Rev. 1.0 October 2010
www.aosmd.com
Page 7 of 9
AOZ8802A
Tape and Reel Dimensions, DFN-6 1.6mm x 1.0mm x 0.55mm
Carrier Tape
P1
D1
T
P2
E1
E2
E
B0
K0
A0
P0
D0
Feeding Direction
UNIT: mm
Package
DFN 1.6 x 1.0
(8 mm)
A0
1.12
±0.05
B0
1.72
±0.05
K0
0.70
±0.05
D0
0.55
±0.05
D1
E
1.55
8.00
±0.10 +0.30/-0.10
E1
1.75
±0.10
E2
3.50
±0.05
P0
4.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.10
T
0.25
±0.05
Reel
W1
S
G
N
M
K
V
R
H
W
UNIT: mm
Tape Size Reel Size
8mm
ø178
M
N
W
W1
H
ø178.0
±0.50
ø60.0
±1
9.0
±0.5
N/A
ø13.0
+0.5/-0.2
K
S
10.25 2.40
±0.2 ±0.10
G
R
V
ø9.8
N/A
N/A
Leader / Trailer & Orientation
Trailer Tape
300mm Min.
75 Empty Pockets
Rev. 1.0 October 2010
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm Min.
125 Empty Pockets
Page 8 of 9
AOZ8802A
Part Marking
AOZ8802ADI
(1.6 x 1.0 DFN)
BB3
Product Number Code
Assembly Lot Code
Week Code
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.0 October 2010
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
www.aosmd.com
Page 9 of 9
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement