Migrate S29NS-P to S29VS

Migration from Spansion® S29NS-P to
S29VS-R
Application Note
By: Yong Qin and Gary Swalling
1. Introduction
The S29VS-R MirrorBit® Flash family offers a line of 1.8-Volt, burst mode, simultaneous read and write,
Address and Data Multiplexed (ADM) products. This guide discusses the new features of S29VS-R and the
considerations the designer should make when migrating from S29NS-P. In this migration guide, S29VS-R
and VS-R refer to the 128 Mb and 256 Mb densities only. For migration from S29NS-R, please also see the
application note, Migrating from S29NS-R to S29VS-R (Migrate_S29NS-R_to_S29VS-R_AN).
2. Feature Comparisons Summary
The following lists the items to consider when migrating from NS-P to VS-R:
 VS-R supports a new software sector protection method, compared with the Advanced Sector Protection
features in NS-P
 VS-R features a Status Register, instead of DQ Polling on the NS-P
 Command Set Changes
– Unlock cycles removed for all commands
– Separate commands to suspend and resume program vs. erase operations
– Single word program command removed
 VS-R is an 8-bank device, compared with the 16 banks of the NS-P
 VS-R has different Device ID values than the NS-P
 VS-R has significant changes in synchronous burst read
– Only supports modes 8 or 16 word with wrap-around or continuous
– Single Configuration Register, instead of two Configuration Registers in the NS-P
 VS-R has differences in Electrical Specifications
 Hardware Migration Considerations
– VS-R has no WP# pin
– Package pin-outs for 128 Mb and 256 Mb densities only differ by WP#
Publication Number Migrate_S29NS-P_to_S29VS-R_AN
Revision 01
Issue Date September 14, 2010
A pplication
Note
Table 2.1 Feature Comparisons
Key Features
NS-P
VS-R
Technology
MirrorBit
MirrorBit
Process Node
90 nm
65 nm
Densities
128 to 512 Mb
128 and 256 Mb
Data Bus Width
16-bit (Word)
16-bit (Word)
Bus Interface
ADM
ADM
VCC
1.70V to 1.95V
1.70V to 1.95V
Temperature Range
Wireless (-25°C to +85°C)
Wireless (-25°C to +85°C)
Industrial (-40°C to +85°C)
Common Flash Interface (CFI)
Yes
Yes
Burst Frequency Order Options
66 / 83 MHz
83 / 104 / 108 MHz
Burst Length (linear, words)
8 / 16 / 32 with or without wrap-around /
continuous
8 / 16 with wrap-around / continuous
Burst mode can be automatically activated
Yes
No
Data Transfer Flow Control
Yes (RDY)
Yes (RDY)
Sector Erase Architecture
32 KB small sectors, 128 KB large sectors
32 KB small sectors, 128 KB large sectors
NS128P/NS256P: top
VS128/256RxxBHW00: top
Boot Sector Architecture
Banks
NS512P: uniform
VS128/256RxxBHW01: bottom
16
8
Command Set
Unlock cycles
Reduced (no unlock cycles)
DQ Polling
Yes
No
Status Register
No
Yes
Write Buffer Programming
64-Byte Write Buffer
64-Byte Write Buffer
Single Word Programming
Yes
No
Program Suspend / Resume
Yes
Yes
Erase Suspend / Resume
Yes
Yes
Low VCC Write Inhibit
Yes
Yes
Hardware Sector Protection
WP# and VPP pins
VPP pin
Software Sector Protection
Advanced Sector Protection (PPB, DYB,
password)
Sector Lock Range, Sector Lock/Unlock
256 Bytes factory locked
256 Bytes factory locked
Secure Silicon Region
256 Bytes customer lockable
256 Bytes customer lockable
Program-Erase Endurance
100,000 cycles per sector (typical)
100,000 cycles per sector (typical)
Data Retention
20-year (typical)
10-year (typical)
NS128P/NS256P: 44-ball, 0.50 mm pitch
FBGA (Pb-free)
Discrete Packages
NS512P: 64-ball, 0.50 mm pitch FBGA (Pbfree)
Discrete Package Sizes (mm)
8.0 x 9.2, 6.2 x 7.7
44-ball, 0.50 mm pitch FBGA (LowHalogen, Pb-free)
6.2 x 7.7
3. Software Sector Protection
The VS-R family features a new method for software sector protection. The NS-P family supports Advanced
Sector Protection (ASP), including Persistent Protection Bits (PPBs), Dynamic Protection Bits (DYBs), and
Password Protection. Instead of ASP, VS-R supports new commands Sector Lock, Sector Unlock, and
Sector Lock Range.
When the VS-R is first powered up, all sectors are unlocked. Issuing the Sector Lock command will lock all
sectors in the device. Until power is cycled, only one sector at a time can be unlocked using the Sector
Unlock command. Issuing the Sector Lock Range command will protect the selected sectors from being
unlocked with the Sector Unlock command until power is cycled.
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Table 3.1 New VS-R Sector Protection Commands
First
Command
Sequence
Cycles
Sector Lock
Second
Data
Data
2AAh
60h
SLA
(A6 = 0)
60h
60h
2AAh
60h
SLA
(A6 = 1)
60h
60h
2AAh
60h
SLA
61h
Data
555h
60h
3
555h
4
555h
3
Sector
Unlock
Sector Lock
Range
Third
Word
Address
Word
Address
Word
Address
Fourth
Word
Address
Data
SLA
61h
Legend
SLA = Sector Lock Address
The NS-P Autoselect command can be used to check whether a particular sector is locked. VS-R does not
provide this information in the ID / CFI address space. Refer to the VS-R data sheet for a full explanation of
this feature.
4. Status Register
The NS-P family supports DQ Polling for software to detect the status of embedded operations. Instead of DQ
Polling, VS-R supports a Status Register. The Status Register content overlays the sector selected by the
Status Register Read command.
The Status Register contents are available for a single asynchronous read, or a single synchronous burst,
after the Status Register Read command is issued. This command must be issued before each read of the
status. Refer to the VS-R data sheet for a full explanation of this feature.
The Spansion Low Level Driver (LLD) provides software examples for both DQ Polling and Status Register
polling. The LLD can be downloaded from the Spansion web site (www.spansion.com). Select the “Drivers &
Software” page from the “Support” menu.
Table 4.1 VS-R Status Register
Bit 7
Overall Device
Ready Bit
Bit 6
Erase Suspend
Status Bit
Bit 5
Erase Status
Bit
Bit 4
Program
Status Bit
Bit 3
Bit 2
Bit 1
Bit 0
Reserve
Program
Suspend
Status Bit
Sector Lock
Status Bit
Bank Status Bit
0
Op. in
addressed
bank
0
Device Busy
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
1
No op. in
addressed
bank
0
Device Busy
September 14, 2010
1
Device Ready
0
No erase in
suspend
0
Erase
Successful
0
Program
Successful
x
0
No program in
suspend
0
Sector not
locked during
op.
0
No active op.
1
Device Ready
1
Erase in
Suspend
1
Erase Error
1
Program fail
x
1
Program in
suspend
1
Sec locked
error
1
Invalid
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A pplication
Note
Figure 4.1 VS-R Status Register Polling
Issue Commands for
Embedded Operation
Read Status
Bit 7 = 0?
(busy)
Yes
No
Erase/
Program
Error?
Yes
Operation Failed
No
Sector
Locked?
Yes
No
Suspended?
Operation Suspended
Yes
No
Operation Complete
5. Command Set Changes
The VS-R family has significant command set changes from the NS-P family. Where the NS-P requires
unlock cycles for most commands, these are removed from the VS-R commands. The VS-R does not support
the Unlock Bypass Mode and the Single Word Program command. The Write Buffer Program command can
be used to program individual words, as needed.
The NS-P provides a single Suspend command for both program and erase operations. To avoid confusion
about the state of the device, the VS-R provides separate Program Suspend and Erase Suspend commands.
Likewise, the Resume command was separated for program and erase. Refer to the VS-R data sheet for a
full explanation of the available commands.
The Spansion Low Level Driver (LLD) provides software examples for both command sets. The LLD can be
downloaded from the Spansion web site (www.spansion.com). Select the “Drivers & Software” page from the
“Support” menu.
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Table 5.1 VS-R Suspend/Resume Commands
Command Sequence
Cycles
Address
Data
Program Suspend
1
X
51h
Program Resume
1
SA
50h
Erase Suspend
1
X
B0h
Erase Resume
1
SA
30h
Legend
X = Don't care
SA = Address bits sufficient to select a sector
6. Flash Memory Array
The VS-R is an 8-bank device, compared with the 16 banks of the NS-P. The sector sizes are the same for
both families. The NS512P has uniform sector sizes, while the NS128P and NS256P have top boot sectors.
The VS128R and VS256R are both available with top or bottom boot sectors. These differences in bank and
sector architecture may require software changes. Refer to the device data sheets for memory address maps.
Table 6.1 NS256P to VS256R Bank/Sector Example
NS256P
Format of Flash
Image
VS256R (Top Boot)
Bank
Sector Size
Number of
Sectors
0
128 KB
16
1
128 KB
16
2
128 KB
16
3
128 KB
16
…
128 KB
16
…
128 KB
16
12
128 KB
16
13
128 KB
16
14
128 KB
16
15
128 KB
15
32 KB
4
OS Image
File System
Volume
Bootloader
Bank
Sector Size
Number of
Sectors
0
128 KB
32
1
128 KB
32
…
128 KB
32
6
128 KB
32
128 KB
31
32 KB
4
7
In the example from Table 6.1, a product can be populated with either NS256P or VS256R. This Operating
System image requires 2 MB of flash space, and fits into bank 0 on NS256P, but on VS256R, it requires a
separate bank to enable Simultaneous Read/Write. In order to maintain a single flash image, 4 MB of space
is set aside for the OS on both devices.
7. Device ID
The VS-R has a combined ID and Common Flash Interface (CFI) memory map. Access to Autoselect ID
values and CFI information is enabled by two different commands:
 CFI Query (command 98h)
 Autoselect (command 90h)
Commands 90h and 98h are both called ID/CFI Entry in the VS-R data sheet since they enable a combined
memory space. Just like NS-P, the VS-R requires the ID/CFI Exit command (F0h) to exit this memory space
and access the Flash memory array. Autoselect with unlock cycles can be used with VS-R to check the
Device ID, but it is not backwards compatible. The NS-P Autoselect command can be used to check whether
a particular sector is locked. VS-R does not provide this information in the ID / CFI address space.
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A pplication
Note
Table 7.1 Autoselect Entry with Unlock Cycles
Cycle
Operation
Byte Address
Word Address
Data
Unlock Cycle1
Write
BA+AAAh
BA+555h
AAh
Unlock Cycle2
Write
BA+555h
BA+2AAh
55h
Autoselect Command
Write
BA+AAAh
BA+555h
90h
Legend
BA = Address bits sufficient to select a bank
Table 7.2 VS-R ID/CFI Entry Command
Cycle
Operation
Byte Address
Word Address
Data
ID/CFI Entry Command
Write
SA+XAAh
SA+X55h
90h or 98h
Legend
X = Don't care
SA = Address bits sufficient to select a sector
Table 7.3 Autoselect ID Codes
NS256/128P
VS256/128R
Description
Word Offset
Data
Word Offset
Data
Manufacturer ID
(BA) + 00h
0001h
(SA) + 00h
0001h
Device ID, Word 1
(BA) + 01h
317Eh (NS256P)
327Eh (NS128P)
(SA) + 01h
007Eh (VS256R)
007Eh (VS128R)
Device ID, Word 2
BA + 0Eh
3141h (NS256P)
3243h (NS128P)
SA + 0Eh
0064h (VS256R Top)
0066h (VS256R Bottom)
0063h (VS128R Top)
0065h (VS128R Bottom)
Device ID, Word 3
BA + 0Fh
3100h (NS256P)
3200h (NS128P)
SA + 0Fh
0001h (VS256R)
0001h (VS128R)
DQ15 - DQ8 = Reserved
DQ7 - Factory Lock Bit:
1 = Locked,
DQ15 - DQ8 = Reserved
DQ7 - Factory Lock Bit:
1 = Locked,
0 = Not Locked
0 = Not Locked
DQ6 - Customer Lock Bit:
1 = Locked,
DQ6 - Customer Lock Bit:
1 = Locked,
Indicator Bits
BA + 07h
0 = Not Locked
DQ5 - Handshake Bit:
1 = Reserved,
SA + 07h
0 = Not Locked
DQ5 - DQ0 = Reserved
0 = Std Handshake
DQ4 & DQ3 - WP#
Protection Boot Code:
01 = WP# protects the top boot sectors
DQ2 - DQ0 = Reserved
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8.
No t e
Synchronous Burst Read
The VS-R supports synchronous burst read, but it does not support as many burst read modes as the NS-P.
Table 8.1 highlights the modes supported. Refer to the VS-R data sheet for a full explanation of the
synchronous burst read mode.
Table 8.1 Synchronous Burst Read Mode
Supported in NS-P?
Supported in VS-R?
Continuous
Burst Read Mode
Yes
Yes
8-word with wrap-around
Yes
Yes
16-word with wrap-around
Yes
Yes
32-word with wrap-around
Yes
No
8-word without wrap-around
Yes
No
16-word without wrap-around
Yes
No
32-word without wrap-around
Yes
No
Burst mode can be automatically activated
Yes
No
The VS-R has a single 16-bit Configuration Register. The NS-P has two 16-bit Configuration Registers. The
VS-R Configuration Register must be programmed with the Write Buffer Program command, while the NS-P
Configuration Register must be programmed with the Word Program Command. Refer to the VS-R data
sheet for a full explanation of the Configuration Register.
Table 8.2 Program NS-P Configuration Register
Address
Data
SA+555h
AAh
Unlock Cycle 1
Description
SA+2AAh
55h
Unlock Cycle 2
SA+555h
D0h
Configuration Register Entry
SA+X00h
CR
Set CR0
SA+X01h
CR
Set CR1
X
F0h
Configuration Register Exit
Legend
X = Don't care
SA = Address bits sufficient to select a sector
CR = Configuration Register Data
Table 8.3 Program VS-R Configuration Register
Address
Data
SA+555h
D0h
Configuration Register Entry
Description
SA+555h
25h
Write Buffer Load
SA+2AAh
0
SA
CR
One Word
SA+555h
29h
Buffer to Flash
X
F0h
Configuration Register Exit
Configuration Register Data
Legend
X = Don't care
SA = Address bits sufficient to select a sector
CR = Configuration Register Data
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Note
Table 8.4 Configuration Register Differences Between NS-P and VS-R
Function
Setting
CR Bit
CR1.15 - CR1.5
CR1.4
CR1.3 - CR1.1
NS-P
VS-R
Reserved
N/A
1 = Default
NS-P
N/A
VS-R
Output Drive
Strength
N/A
0 = Full Drive (Default)
1 = Half Drive
N/A
Reserved
N/A
1 = Default
N/A
CR1.0
Wait State
(with CR0.13-11)
N/A
Detail see data sheet
N/A
CR0.15
Reserved
Device Read Mode
0 = Reserved (Default)
1 = Reserved
0 = Synchronous Read Mode
1 = Asynchronous Read Mode
(Default)
CR0.14
Reserved
Wait State
0 = Reserved (Default)
1 = Reserved
Detail see data sheet
Wait State
(with CR1.0)
Wait State
Detail see data sheet
Detail see data sheet
CR0.7
Reserved
Output Drive
Strength
0 = Reserved
1 = Reserved (Default)
0 = Full Drive (Default)
1 = Half Drive
CR0.4
RDY Function
Reserved
0 = RDY (Default)
1 = Reserved
0 = Reserved (Default)
1 = Reserved
CR0.3
Burst Wrap Around
Reserved
0 = No Wrap Around Burst
1 = Wrap Around Burst (Default)
0 = Reserved
1 = Reserved (Default)
Burst Length
000 = Continuous (Default)
010 = 8-Word Linear burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
All other bit settings are reserved
000 = Continuous (Default)
010 = 8-Word Linear Burst Wrap
Around
011 = 16-Word Linear Burst Wrap
Around
All other bit settings are reserved
CR0.13 CR0.11
CR0.2-CR0.0
Burst Length
9. Hardware Sector Protection
The VS-R does not have a WP# pin, which can be used to lock specific sectors for the NS-P. The VS-R can
lock all sectors with the VPP pin, similar to NS-P. Refer to device data sheets for a full explanation of the
hardware data protection methods.
10. Electrical Specification Differences
Electrical considerations for porting from NS-P to VS-R are described below. Since there are several
differences between burst read on the NS-P and the VS-R, burst read current and timings are not discussed
here. Please refer to the device data sheets for a detailed description of electrical specifications.
Table 10.1 DC Characteristics
Parameter
Description
Source
Min / Typ / Max
NS-P
VS-R
ICC1
VCC Active Asynchronous Read Current (tested
at 10 MHz)
VCC
Max
80 mA
60 mA
ICC2
VCC Active Write Current
VCC
Typ
<20 mA
30 mA
Typ
20 µA
30 µA
Max
70 µA
40 µA
Typ
5 µA
20 µA
Typ
<15 mA
25 mA
Max
20 mA
28 mA
ICC3
VCC Standby Current
VCC
ICC6
VCC Sleep Current
VCC
IPP
Accelerated Program Current
VCC
VLKO
Low VCC Lock-out Voltage
Min
–
1.0V
Max
1.4V
1.1V
–
VS-R has a higher current draw from VCC in some situations. This change in current should be noted, but the
overall system impact is expected to be minimal.
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VS-R has a slightly lower lockout voltage than NS-P. Since systems should be designed for a minimum
operating VCC of 1.7V with either flash family, this change in lockout voltage should have no negative impact.
Table 10.2 Capacitance, Single Die and Package
Parameter
CIN
COUT
Description
Min or Max
NS-P
VS-R
Min
1.05 pF
2.0 pF
Max
1.75 pF
6.0 pF
Min
1.50 pF
2.0 pF
Max
2.50 pF
6.0 pF
Input Capacitance
Output Capacitance
VS-R has higher capacitance values than the NS-P. This increased capacitance can affect the slope of
signals for read and write cycles, as well as VCC ramp to the device. When changing from NS-P to VS-R
devices, these waveforms should be checked to ensure the timing specifications are satisfied. Signal integrity
simulations can be run with IBIS models, which are available at www.spansion.com.
Table 10.3 VCC Power-up
Parameter
Description
Min or Max
NS-P
VS-R
tVCS
VCC Setup Time
Min
30 µs
300 µs
tVIOS
VIO Setup Time
Min
–
300 µs
The VS-R requires that RESET# is held low significantly longer after VCC ramps up. When moving from
NS-P to VS-R, the power-up waveforms should be checked. If the RESET# pin is not held low for at least
300 µs after VCC ramps up, circuit changes may be needed to accommodate the new specification.
Table 10.4 AC Characteristics
10.1
Parameter
Description
Min or Max
NS-P
VS-R
tRC
Read Cycle Time
Min
–
80 ns
tOE
Output Enable to Output Valid
Max
9 ns
15 ns
tAVDO
AVD# High to OE# Low
Min
–
4 ns
tWEA
WE# Disable to AVD# Enable
Min
–
9.6 ns
tOEH (data reads)
WE# Disable to OE# Enable
Min
0 ns
4 ns
tVLWH
AVD# Disable to WE# Disable
Min
–
23.5 ns
10 ns
tCR
CE# Low to RDY Valid
Max
–
tWEH
OE# Disable to WE# Enable
Min
–
4 ns
tESL
Erase Suspend Latency
Min
20 µs
30 µs
tPSL
Program Suspend Latency
Min
20 µs
30 µs
Read Cycle Time (tRC)
VS-R requires a minimum asynchronous read cycle of 80 ns. NS-P does not specify this requirement. When
moving from NS-P to VS-R, the timing of back to back cycles should be checked to ensure this requirement is
satisfied. The memory controller may need adjustment.
10.2
Output Enable to Output Valid (tOE)
VS-R provides read cycle output within 15 ns of OE# going low. NS-P provides valid output within 9 ns. When
changing from NS-P to VS-R, devices and components reading from flash must now wait at least 15 ns
before latching the data.
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10.3
Note
AVD# High to OE# Low (tAVDO)
For asynchronous reads, VS-R requires AVD# is driven high at least 4 ns before OE# goes low. Since NS-P
does not have this requirement, it must be checked when moving to VS-R. The memory controller may need
adjustment.
10.4
WE# Disable to AVD# Enable (tWEA)
VS-R requires AVD# is driven low at least 9.6 ns after a write cycle. NS-P does not specify this requirement.
When moving from NS-P to VS-R, the timing of back to back cycles should be checked to ensure this
requirement is satisfied. The memory controller may need adjustment.
10.5
WE# Disable to OE# Enable (tOEH)
For asynchronous data reads, VS-R requires OE# is driven low at least 4 ns after a write cycle. NS-P
specifies 0ns for this parameter. When changing from NS-P to VS-R, the timing of back to back cycles should
be checked to ensure this new requirement is satisfied. The memory controller may need adjustment.
10.6
AVD# Disable to WE# Disable (tVLWH)
For flash write cycles, VS-R requires WE# is driven high at least 23.5 ns after AVD# goes high. NS-P does
not specify this requirement. When moving from NS-P to VS-R, the timing of write cycles should be checked
to ensure this requirement is satisfied. The memory controller may need adjustment.
10.7
CE# Low to RDY Valid (tCR)
When the flash device is not chip selected, the RDY pin is tri-stated to High-Z. Once the device is selected for
read or write, VS-R provides valid output on RDY within 10 ns of CE# going low. NS-P does not specify this
parameter. When using VS-R, devices and components reading from the flash RDY pin must wait at least
10 ns before latching the value.
10.8
OE# Disable to WE# Enable (tWEH)
For flash write cycles, VS-R requires WE# is driven low at least 4 ns after OE# goes high. NS-P does not
specify this requirement. When moving from NS-P to VS-R, the timing of back to back cycles should be
checked to ensure this requirement is satisfied. The memory controller may need adjustment.
10.9
Erase Suspend Latency (tESL)
After issuing an Erase Suspend Command, system software can read the device status to check if the erase
operation was suspended or completed. VS-R requires a delay of at least 30us before reading the Status
Register. NS-P requires a delay of only 20 µs before checking device status. When moving from NS-P to
VS-R, a longer delay must be implemented.
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10.10 Program Suspend Latency (tPSL)
After issuing an Program Suspend Command, system software can read the device status to check if the
erase operation was suspended or completed. VS-R requires a delay of at least 30 µs before reading the
Status Register. NS-P requires a delay of only 20 µs before checking device status. When moving from
NS-P to VS-R, a longer delay must be implemented.
Table 10.5 Erase and Programming Performance
Parameter
Voltage
VCC
128 KB Sector Erase Time With
Pre-programming Included
Typ or Max
NS-P
VS-R
Typ
0.9s
1.3s
Max
5.0s
5.5s
Typ
0.7s
1.3s
Max
3.75s
5.5s
VPP
VCC
128 KB Sector Erase Time With
Pre-programming Excluded
VPP
VCC
32 KB Sector Erase Time With
Pre-programming Included
VPP
VCC
32 KB Sector Erase Time With
Pre-programming Excluded
VPP
VCC
Typ
0.8s
0.8s
Max
3.5s
3.5s
Typ
0.8s
0.8s
Max
3.5s
3.5s
0.6s
Typ
0.45s
Max
1.85s
3.5s
Typ
0.35s
0.6s
Max
1.4s
3.5s
0.35s
Typ
0.15s
Max
2.0s
2.0s
Typ
0.15s
0.35s
Max
2.0s
2.0s
Typ
300 µs
450 µs
Max
3000 µs
3000 µs
Total 32-word Buffer Programming Time
VPP
Typ
192 µs
288 µs
Max
1920 µs
1540 µs
VS-R could take longer to program and erase in certain cases, as shown in Table 10.5. Software time outs
should be checked to ensure they allow the applicable maximum time.
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Note
11. Packaging
The VS-R and NS-P (128 Mb and 256 Mb densities) are available in 44-ball, 0.50 mm pitch FBGA packages.
The difference is that the VS-R package has NC instead of WP# for ball D9.
Figure 11.1 VS-R Ball Out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
NC
NC
B
C
RDY
A21
VSS
CLK
VCC
WE#
VPP
A19
A17
A22
VCCQ
A16
A20
AVD#
A23
RESET#
NC
A18
CE#
VSSQ
VSS
A/DQ7
A/DQ6
A/DQ13 A/DQ12
A/DQ3
A/DQ2
A/DQ9
A/DQ8
OE#
A/DQ15 A/DQ14
VSSQ
A/DQ5
A/DQ11 A/DQ10
VCCQ
A/DQ1
A/DQ0
D
E
F
A/DQ4
G
H
NC
NC
12. Conclusion
The VS-R family offers several improvements over the NS-P family, specifically targeting customer usage.
 Simplified operation status
 Simplified command set
 Simplified sector protection
13. References
 S29NS-P MirrorBit Flash Family Data Sheet
 S29VS/XS-R MirrorBit Flash Family Data Sheet
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App l ic atio n
No t e
14. Revision History
Section
Description
Revision 01 (September 14, 2010)
Initial release
September 14, 2010
Migrate_S29NS-P_to_S29VS-R_AN_01
13
A pplication
Note
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2010 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and
combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used
are for informational purposes only and may be trademarks of their respective owners.
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