1 STM32L0 architecture

1 STM32L0 architecture
STM32L0 architecture
OBJECTIVES
• Introduce STM32L0 internal structure
• Briefly describe each internal component
• some of them will be explained more in detail later
• Highlight the main features of each peripheral
After this presentation you will know what
you can find inside STM32L0 today.
2
3
Introduction
Flash I/F
STM32L06x – 64kB Block Diagram
CORTEXTM-M0+
M0+
CPU
32 MHz
With MPU
37/51 I/Os
NVIC
SysTick
ARM ® Lite Hi-Speed Bus
Matrix / Arbiter (max 32MHz)
SW Debug
64KB
Flash Memory
Power Supply
Reg 1.8V/1.5V/1.2V
POR/PDR/BOR/PVD
2KB
Data EEPROM
Int. RC 16 MHz
8KB SRAM
20B
Backup Reg.
TSC
RNG
RCC
DMA
7 Channels
Xtal 1-24MHz
Int. RC 37 kHz
Xtal 32,768 kHz
Int. RC 65K..4.2MHz
PLL
RTC / WUT
AES Tiny
4 x 16-bit Timer
EXTI
2 x Watchdog
2 x SPI
2 x COMP
(ind. & window)
1x LPTIM
Glass LCD Control.
(up to 8x24)
USB 2.0 FS
1 x 12-bit DAC
2 x USART
1 x 12-bit ADC
19 channels / 1Msps
1 x LPUART
Temp Sensor
2 x I2C
4
System Architecture
CORTEX-M0+
SLAVES
Flash I/F
MASTERS
System
FLASH and
Data EEPROM
SRAM
GPIOx
BusMatrix
IOPort
AHB
RCC – CRC – AES – DMA1 regs – TSC
APB1
AHB-APB1
APB1 peripherals
APB2
AHB-APB2
DMA1
APB2 peripherals
Bridges
Arbiter
Buses are not overloaded with data movement tasks !
5
6
System blocks
7
System blocks
Core
Cortex-M0+ Processor Overview
ARMv6-M Architecture
von Neumann architecture, 2-stage pipeline
Integrated Nested Vectored Interrupt Controller
(NVIC) for low latency interrupt processing
Designed to be fully programmed in C-language
Vector Table is a simple list of addresses
Full Thumb Instruction Set and subset of Thumb-2
Single cycle multiply (optional)
IOPort
Memory Protection Unit (MPU)* (optional) , privileged / unprivileged mode*
Integrated 24-bit System Timer (SysTick) for RTOS (optional)
+ interrupt vector table relocation
8
Cortex-M0+ instruction set
M0+
9
Cortex-M0+ pipeline
10
HRDATA HADDR
CLOCK
• Only two stage pipeline for maximum energy efficiency
a4
a6
i4
i5
i6
CPU PIPELINE
i3
Fetch
Decode
Execute
a8
i7
i5
Decode
Execute
Fetch
Fetch
Decode
Execute
Decode
Execute
Fetch
i4
1x 32-bit word = 2x 16-bit wide instructions
Fetch
Decode
i6
Execute
Decode
Cortex-M0+ Higher dynamic efficiency
• In pipelined processors, subsequent instructions are fetched while
executing current instructions
3-stage
pipeline
instructions fetched/decoded
but not used
2-stage
pipeline
• In 2-stage pipeline:
•
•
Branch shadow is reduced and energy is saved!
Branch turn-around is 1 cycle faster!
11
Debug Capabilities
12
Serial Wire Debug interface
SWD
VDD
Breakpoint and Watchpoint units
4 hardware breakpoints
(besides BKPT instruction)
SWDIO
SWCLK
2 hardware watchpoints
VSS
Additional debug features covered by DBGMCU
peripheral
13
System blocks
DMA
DMA Controller Features
• Up to 7 independently configurable channels (requests)
• 4 configurable levels of priority
• Independent source and destination transfer size (byte / half word / word)
• Support for circular buffer management
• Half-Transfer and Transfer complete events
• Programmable number of data to be transferred: up to 65536 (16-bit counter)
2
DMA
Flash
BusMatrix
Cortex
M0+
Cortex
M0+
RAM
Periph.
DMA
Flash
BusMatrix
1
RAM
Periph.
14
15
System blocks
Internal Memories
Memory Mapping and Boot Modes
Addressable memory space of 4 Gbytes
RAM : up to 8 Kbytes
FLASH : up to 64 Kbytes
Data EEPROM: up to 2 Kbytes
0xFFFF FFFF
0xE010 0000
0xE000 0000
BOOT Mode
Selection
Reserved
Reserved
User/Factory
Option Bytes
System Memory
0x5000 0000
I/O Port
Reserved
0x4000 0000
Boot modes
Depending on the Boot configuration, Embedded Flash
Memory, System Memory or Embedded SRAM Memory
is aliased at @0x00. The System Memory and Embedded
SRAM memory can be remapped also at @0x0
using a dedicated software bits.
BOOT0 is read on dedicated pin BOOT0
BOOT1 is an option register bit
Reserved
Cortex-M0+
internal
peripherals
0x1FF8 0000
EEPROM
0x0808 0000
Peripherals
Reserved
Boot Mode
Aliasing
nBOOT1
BOOT0
x
0
User Flash
User Flash is selected as
boot space
0
1
SystemMemory
SystemMemory is
selected as boot space
1
1
Embedded SRAM
Embedded SRAM is
selected as boot space
0x1FF0 0000
Reserved
SystemMemory: contains the Bootloader used to
re-program the FLASH through USART1/2 or SPI1/2
Flash
0x0800 0000
0x2000 0000
SRAM up to 8KB
Reserved
0x0000 0000
CODE
16
Boot from SRAM In the application initialization
code you have to Relocate the Vector Table in
SRAM using the NVIC Exception Table and Offset
register.
17
System blocks
Reset and Clock Control (RCC)
The Gear Box
• clock tree consists of 6 clock sources + 1xPLL
• Dynamic Internal Voltage Scaling: optimize consumption according to speed you need!
• Consumption down to few µA only with still running CPU !
MSI
Multi-Speed Internal clock : Default RUN mode
Internal 65kHz to 4.2MHz
- Low to Medium frequency, Ultra-Low consumption
- Default Clock Source (2.1MHz after reset)
HSI16
High-Speed Internal 16MHz clock : Performance mode
Internal @ 16MHz
+/-0.5%
- Up to 32MHz (PLL): 33.3 DMIPS
High-Speed External clock : Crystal / ext. signal
HSE
External 1-24MHz
HSI48
- USB 48MHz clk with single 16MHz crystal + PLL.
PLL
Up to 32MHz
High-Speed Internal 48MHz clock : USB and RNG
Internal 48MHz
LSI
Internal @ 37kHz
- “Synchronizable” 48MHz oscillator for USB enabling crystal less operation
- RNG seed clock source
Low Speed Internal clock : Security clock
- Used for Independent Watchdog security and RTC
LSE
Low Speed External clock (32.768KHz)
External @ 32kHz
- Mainly used for precise RTC
- Could be used to calibrate HSI & MSI
Configurable drive level
18
Internal Reset Circuitries
VDD /VDDA
Pull-up is disabled when
pin forced low
RPU
External
RESET
SYSTEM RESET
Filter
NRST
PULSE
GENERATOR
(min 20µs)
WWDG RESET
IWDG RESET
Software RESET
Power RESET
Low power
management RESET
Firewall RESET
POR/PDR
RESET
BOR
RESET
Power-on-Reset / Power-down-Reset circuitry (POR/PDR):
For devices operating from 1.65 to 3.6 V, there is no BOR and the reset is
released when VDD goes above POR level (1.5V) and asserted when VDD goes
below PDR (1.5V) level (no hysteresis)
Brown-out-Reset circuitry (BOR): (enabled by default, can be disabled)
Configurable level from 1.8V up to 2.9V (100mV hysteresis), if enabled →
POR/PDR have no effect
Programmable Voltage Detector (PVD)
Configurable level from 1.9V up to 3.1V (100mV step), no reset, can generate interrupt
19
20
System blocks
Power Control (PWR)
Power Supply Domains
on big packages only
(TBGA64)
VDDA domain
VREF-
1.65V ~ 3.6V
VDD = VDDA
VREF+
VDDA
Temp. sensor
VSSA
PLL
VDD domain
I/O Ring, Clock Sources
1.65V ~ 3.6V
(2.5V ~ 3.6V)
VSS
VDD
VLCD
STM32L0
Reset Circuitries
A/D, D/A converters
1.8V at power-on
(BOR)
21
USB
transceiver
3.0V ~ 3.6V
(1.65V ~ 3.6V)
VCore domain
Cortex-M0+ Core
Memories
BACKUP domain
(FLASH, SRAM)
Voltage Regulator
Digital
peripherals
( LCD Controller )
VDD_USB
For Battery Powered Application
• Functional down to 1.65V
• What for?
• Battery powered radio, fire alarms, motion detectors, other sensors…
• Extend application life time vs. 1.8V standard VDD Range
• 1.65V but no compromise on performance
• @ VDD = 1.65V freq. running still @ 16MHz
• …But what is functional @1.65V?
•
•
•
•
•
•
Memories and Core (even Flash/EEPROM can be programmed)
GPIOs
Comparators
Communication peripherals (USART, SPI, I2C)
Timers, RTC
Capacitive touch…
• (Only some high-speed peripherals and some analog peripherals need higher voltage)
22
23
System blocks
GPIO
General-Purpose I/Os (GPIO)
NO
CONFLICTS
24
Not on AHB → IOPort
EMC
TO / FROM
PERIPHERALS
FLEXIBLITY
16mA max
.....
...................
up to 16
400kHz
Push-Pull
OUTPUT
Open drain
10MHz
(Pull-up, Pull-down)
50MHz
ESD
(5VT)
Floating
INPUT
(Pull-up, Pull-down)
Analog
standard / 5V tolerant
IDR
ANALOG
PERIPHERALS
PIN
2MHz
ODR
B(S)RR
GPIO READ / WRITE
Fast toggle capable of changing
every SINGLE clock cycle (IOPort)
Locking mechanism provided to
freeze the port I/O configuration
Bitwise write access
All the GPIO’s can be configured to generate interrupt on external event (up to 16
lines at time)
16MHz SW I/O toggling
25
PA8_MCO
32MHz SYSCLK
(HSI16 + PLL)
PA5 as Push-Pull
output
16MHz toggling
generated by
consecutive writes to
BRR and BSRR
16MHz I/O toggling
26
Compiler optimizations to be enabled for SPEED
1 toggle
Example can be found in the STM32CubeL0 package.
(…STM32L053R8-Nucleo\Examples\GPIO\GPIO_IOToggle_MaxFrequency)
27
System blocks
Watchdogs
Watchdogs
• Independent Watchdog (IWDG) → IWWDG
• Dedicated low speed clock (LSI)
• HW and SW way of enabling
• IWDG clock still active if main clock source fails
• Timeout values @37kHz: 108us …28s
• Window Functionality
• Window Watchdog (WWDG)
• Configurable Time Window
• Can detect abnormally early or late application
behavior
• Conditional Reset
• WWDG Reset flag
• Timeout value @32MHz: 128us … 65.54ms
28
29
Analog peripherals
Analog to Digital Converter (ADC)
ADC conversion rate 1.14 MSPS and 12-bit resolution (0.87us @16MHz)
Up to 16-bit resolution with internal HW oversampler
Available in Performance and Low-power Run with CPU clk @ 32kHz
ADC supply requirement: 1.8V to 3.6 V (from 2.4V full speed available)
Up to 19 multiplexed channels (16 external + 3 internal)
DMA
Single and continuous conversion modes
Programmable sampling time
Hardware Delay insertion between conversions
Programmable Conversion resolution : 12, 10, 8 or 6-bit
Analog Watchdog on high and low thresholds
HW/SW Trigger
ADC State
Normal
Power Save
1
Delay
2
Delay
1
ON
OFF ON
OFF
ADC Waiting for
Trigger
ON
OFF
Startup Time
OFF
N
ON
Regular
conversion #N
30
Digital to Analog Converter (DAC)
• One DAC converter
• 8-bit or 12-bit monotonic output (left or right data alignment)
• Independent or simultaneous conversions
• External triggers for conversion (Timers)
• Conversion range: 0.5mV (0.2V) to VDDA-1LSB (VDDA-0.2V)
• Noise-wave and Triangular-wave generator
• Integrated buffer to reduce the output impedance
MAMPx[3:0]: Max amplitude
DAC_DHRx: Base value
DMA
31
Analog Comparators (COMPx)
32
• two zero-crossing comparators COMP1 and COMP2 sharing the same current bias
• COMP1 with fixed internal reference voltage / external threshold
• COMP2 has Rail-to-Rail inputs with selectable threshold
• Can be combined into a window comparator
Non inverting input
External Input
+
Inverting input
Window comparator
Configuration switch
External Input
-
1.22V
Bias from
VREFINT
COMP2
Non inverting input
Inverting input
COMP1
+
External Input
DAC OUTx
Rail to rail
COMP1 and COMP2 inputs and outputs are available on GPIO
LCD Main features
• High Flexibility Frame Rates
• Drive up to 224 (8x28) or 128 (4x32) picture elements (pixels)
• Programmable duty and bias
• Duty: Static, 1/2, 1/3, 1/4, 1/8
• Bias: Static, 1/2, 1/3, 1/4
• Low Power Waveform to reduce consumption
• External (VLCD) or internal (STEP-UP) voltage source
• Double buffer memory
• Contrast Control whatever power supply voltage source
• Blinking programmable pixels and frequency
• 1, 2, 3, 4, 8 or all pixels at programmable frequency
• Adjustable blink frequency: 0.5 Hz, 1 Hz, 2 Hz or 4 Hz
• Unused segments and common pins can be used as I/O
Frame ~30 Hz to
~100 Hz
33
Touch Sensing Controller
• Proven and robust surface charge transfer acquisition principle
• One sampling capacitor for up to 3 capacitive sensing channels to
reduce the system components
• Supports up to 24 capacitive sensing channels split over 8 analog I/O
groups
• Up to 8 capacitive sensing channels can be acquired in parallel offering a
very good response time
• 1 counter per analog I/O group to store the current acquisition result
• Full hardware management of the charge transfer acquisition sequence
• No CPU load during acquisition
• Spread spectrum feature to improve system robustness in noisy
environments (minimum step of 20.8ns)
34
35
Timers
Real-Time Clocks (RTC)
• Daylight saving compensation programmable by software
• (Smooth – 0.954ppm resolution)
• The RTC clock source can be any of the following:
• LSE oscillator clock
• LSI oscillator clock
• HSE 1MHz max (HSE divided by /32 in clock controller).
• Up to 2 TAMPERs
Alarm A
Date/hh:mm:ss:subs
Calendar
Alarm B
Day/month/year
hh:mm:ss:subs
(12/24 format)
Date/hh:mm:ss:subs
Wake-Up
16-bit autoreload
Timer
36
General Purporse Timers
37
• 3 x 16-bit timer
• with autoreload
• 8 CAPCOM units
ETR
Clock
ITR 1
Trigger/Clock
ITR 2
ITR 3
Controller
Trigger
Output
ITR 4
Output Compare / Input Capture
16-Bit Prescaler
PWM Output / Input
One Pulse Mode
Auto Reload Reg.
Encoder interface
+/- 16-Bit Counter
Synchronization
(Master/Slave, with external trigger)
CH1
• 1 x 16-bit basic timer
CH2
• with autoreload (DAC support)
• 1 x 16-bit Low-Power timer
(LPTIM)
CH3
CH4
CH1
Capture Compare
Capture Compare
Capture Compare
Capture Compare
CH2
CH3
CH4
Low-Power Timer
• Asynchronous running capability
• Ultra low power-consumption
• Timeout function for wakeup from
low power modes
38
39
Communication Peripherals
USART
Frame
•
•
•
•
7, 8, 9 DATA bits
0.5, 1, 1.5, 2 STOP bits
Even, odd, none PARITY
Oversampling /8 and /16 (default)
Modes • Asynchronous
LIN
SmartCard (T=0, T=1)
IrDA SIR ENDEC
Multiprocessor communication
Half duplex
Basic MODBUS
• Synchronous (CLK line)
Other
•
•
•
•
•
2x USARTs + 1x LPUART
4Mbps
DMA support
HW flow control (RTS, CTS lines)
Programmable data order (MSB/LSB)
Wake-Up from STOP mode
Swappable Tx/Rx pin, Driver Enable (for RS-485)
DMA
40
I2C
• I2C Version 3.0 compatibility
• Standard-Mode, Fast-Mode (up to 400 kHz), Fast-Mode+ (up to 1 MHz)
• Slave and master modes with multi-master capability
• 7-bit and 10-bit addressing mode, dual addressing capability
• Programmable timing, optional clock stretching
• Easy to use event management, 1-byte buffer with DMA capability
• SMBus ver. 2.0 and PMBus ver 1.1 standards compatibility
• Programmable analog and digital noise filters
• Wakeup from STOP on address match
DMA
41
SPI / I2S
• SPI
• Speed up to 16 MHz bitrate
• Full-duplex (3 wires), half-duplex (2 wires) or simplex synchronous transfers (2
wires, unidirectional data line)
• 8-bit or 16-bit data size selection
• MASTER or SLAVE operation, Multi-master mode capability
• NSS management by HW or SW for both MASTER and SLAVE modes
• CRC calculation and check for reliable communication
• I2S
I2C controls *
Audio Codec
2
CK
CK
SD
SD
WS
WS
MCLK**
MCLK
• Left-Justified / Right-Justified
• PCM standard
DMA
STM32L0xx
Digital Interface
• I S Philips
Analog Interface
• Up to 192kHz, 32-bit
42
USB Interface
43
• Crystal-less* USB 2.0 FS interface (12Mbit/s) with D+/D- resistors
* Integrated on-chip 48 MHz oscillator with clock recovery system (CRS)
No external resonator/crystal needed (cost saving is in range of 0.10$)
• Link Power Management (LPM) and Battery Charger Detection (BCD)
V1.2 compliant
• USB FS Device Library with intuitive USB device class drivers API
• Examples and demo based on a set of 6 classes (Audio, CCID, CDC, HID, VCP, MSC)
• Easy development of applications using USB full speed transfer types (control,
interrupt, bulk and isochronous)
• Device Firmware Upgrade on the field over USB (internal bootloader)
• USB VID/PID sublicensing service for free
44
Security peripherals
Safety and Security features Summary
• True EEPROM embedded → guaranteed robustness:
• Derived from Automotive
• ECC for Flash, EEPROM and Backup registers
• Working temp -40°C to 105°C
• Cycling: 10K on Flash / 300K on EEPROM (each block of 128-bit)
• Data retention: 30 years at 85°C / 10 years at 105°C
• Flash operation and programming capability down to 1.65V
• Read-Out Protection: SWD fuse memory protection
• Sector protection (4kb): Read (PcROP) or Write
• Firewall internal memory interface to secure selected Code/Data
• MPU, privilege/unprivilege modes, Watchdogs, Registers locking
• Clock Security System (CSS) for both HSE and LSE, if enabled:
• In case of HSE failure Clock Security System (CSS) will switch to MSI
• In case of LSE failure, wakeup from low-power mode is generated
(Interrupt request can be generated)
45
CRC – Features
CRC-based techniques are used to verify data transmission or storage integrity
• Fully programmable polynomial with programmable size (7, 8, 16, 32 bits)
• Alternatively, you can use default CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32+ X26+ X23 + X22 + X16+ X12 + X11+ X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Single input/output 32-bit data register (8, 16 or 32-bit data)
CRC computation done in 4 AHB clock cycles (HCLK) (for 32-bit data)
General-purpose 8-bit register (can be used for temporary storage)
AHB Bus
32-bit (read access)
Data register (Output)
CRC computation (default polynomial: 0x4C11DB7)
32-bit (write access)
Data register (Input)
46
Advanced Encryption AES
• Supports encryption and decryption using:
• 128-bit key
• 128-bit data blocks
• Supported modes:
•
Electronic CodeBook mode (ECB) – default
•
Cipher block chaining (CBC)
•
Counter (CTR) mode
• Dedicated 2 DMA channels:
• AES_IN – channel 1 or channel 5
• AES_OUT – channel 2 or channel 3
213 clock cycles for one 128-bit data block
47
Random Number Generator (RNG)
• Based on a continuous analog noise (True RNG)
• Generates 32-bit random numbers
• Clocked by a dedicated clock (PLL48CLK or HSI48)
• 40 periods of the clock signal between two consecutive random numbers
• Can be disabled to reduce power-consumption
• Provide a success ratio of more than 85% to FIPS 140-2 (Federal
Information Processing Standards Publication 140-2) tests for a
sequence of 20 000 bits
Firewall
Cortex-M
DMA
• To secure selected region of
memory against Read-Out
Bus matrix
SRAM
AHB/APB bridge
• Separation of the Main
application and some TOP
security library/stack
FLASH /
EEPROM
NVM code/data
Volatile Data
FIREWALL
FIREWALL_CR_FPA = 1
Entry
Start
address
RESET
49
Length
Segment
FIREWALL_CR_FPA = 0
Memory map
Thank you
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