Interfacing an External Processor to an Altera FPGA

Interfacing an External Processor to an Altera FPGA
10. Interfacing an External Processor to
an Altera FPGA
July 2011
ED51011-1.1
ED51011-1.1
This chapter provides an overview of the options Altera® provides to connect an
external processor to an Altera FPGA or Hardcopy® device. These interface options
include the PCI Express, PCI, RapidIO®, serial peripheral interface (SPI) interface or a
simple custom bridge that you can design yourself.
By including both an FPGA and a commercially available processor in your system,
you can partition your design to optimize performance and cost in the following
ways:
■
Offload pre- or post- processing of data to the external processor
■
Create dedicated FPGA resources for co-processing data
■
Reduce design time by using IP from Altera’s library of components to implement
peripheral expansion for industry standard functionality
■
Expand the I/O capability of your external processor
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
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Embedded Design Handbook
July 2011
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10–2
Chapter 10: Interfacing an External Processor to an Altera FPGA
You can instantiate the PCI Express, PCI, and RapidIO MegaCore functions using
either the MegaWizardTM Plug-In Manager or SOPC Builder design flow. The PCI Lite
and SPI cores are only available in the SOPC Builder design flow. SOPC Builder
automatically generates the HDL design files that include all of the specified
components and system connectivity. Alternatively, you can use the MegaWizard
Plug-In Manager to generate a stand-alone component outside of SOPC Builder.
Figure 10–1 shows the steps you take to instantiate a component in both design flows.
Figure 10–1. SOPC Builder and MegaWizard Plug-In Manager Design Flows
Select Design Flow
SOPC Builder
Flow
MegaWizard Plug-in
Manager Flow
Specify Parameters
Specify Parameters
Simulate with
Testbench
Complete SOPC
Builder System
Instantiate MegaCore
Function in Design
Simulate System
Specify Constraints
Compile Design
Program Device
The remainder of this chapter provides an overview of the MegaCore functions that
you can use to interface an Altera FPGA to an external processor. It covers the
following topics:
■
Configuration Options
■
RapidIO Interface
■
PCI Express Interface
■
PCI Interface
■
PCI Lite Interface
■
Serial Protocol Interface (SPI)
■
Custom Bridge Interfaces
Embedded Design Handbook
July 2011 Altera Corporation
Chapter 10: Interfacing an External Processor to an Altera FPGA
Configuration Options
10–3
Configuration Options
Figure 10–2 illustrates an SOPC Builder system design that includes a
high-performance external bus or switch to connect an industry-standard processor to
an external interface of a MegaCore function inside the FPGA. This MegaCore
function also includes an Avalon-MM master port that connects to the SOPC Builder
system interconnect fabric. As Figure 10–2 illustrates, Altera provides a library of
components, typically Avalon-MM slave devices, that connect seamlessly to the
Avalon system interconnect fabric.
Figure 10–2. FPGA with a Bus or Switch Interface Bridge for Peripheral Expansion
Altera FPGA or Hardcopy Device
Processor
Bus or Switch
Interface
Component
(PCIe or RIO)
M
DMA
On-Chip
Memory
M
S
System Interconnect Fabric
M
S
July 2011
Avalon-MM Master
Avalon-MM Slave
Altera Corporation
S
Memory
Controller
S
S
S
S
UART
User I/O
USB
Timer
Embedded Design Handbook
10–4
Chapter 10: Interfacing an External Processor to an Altera FPGA
Configuration Options
Figure 10–3 illustrates a design that includes an external processor that interfaces to a
PCI Express endpoint inside the FPGA. The system interconnect fabric inside the
implements a partial crossbar switch between the endpoint that connects to the
external processor and two additional PCI Express root ports that interface to an
Ethernet card and a marking engine. In addition, the system includes some custom
logic, a memory controller to interface to external DDR SDRAM memory, a USB
interface port, and an interface to external flash memory. SOPC Builder automatically
generates the system interconnect fabric to connect the components in the system.
Figure 10–3. FPGA with a Processor Bus or SPI for Peripheral Expansion
Stratix IV GX Device
PCIe
Hard IP
Custom
Logic
M
M
RP
PCIe
Hard IP
PCIe
Hard IP
PCI Link
Processor
RP
EP
System
Interconnect
Fabric
M
BAR0-1
PCIe
Hard IP
S
M
BAR0-1
BAR2
BAR3
M
S
Avalon-MM Master
Avalon-MM Slave
Ethernet
S
S
RP
S
S
BAR3
Memory
Controller
Marking
Engine
BAR2
S
S
USB
Flash
Cntl
Flash
DDR
SDRAM
Embedded Design Handbook
July 2011 Altera Corporation
Chapter 10: Interfacing an External Processor to an Altera FPGA
Configuration Options
10–5
Alternatively, you can also implement your logic in Verilog HDL or VHDL without
using SOPC Builder. Figure 10–4 illustrates a modular design that uses the FPGA for
co-processing with a second module to implement the interface to the processor. If
you choose this option, you must write all of the HDL to connect the modules in your
system.
Figure 10–4. FPGA Performs Co-Processing
Altera FPGA or HardCopy Device
Direct
I/F
Processor
Co-Processing
Implemented in
Verilog HDL or
VHDL
Table 10–1 summarizes the components Altera provides to connect an Altera FPGA or
HardCopy device to an external processor. As this table indicates, three of the
components are also available for use in the MegaWizard Plug-In Manager design
flow in addition to the SOPC Builder. Alternative implementations of these
components are also available through the Altera Megafunction Partners Program
(AMPPSM) partners. The AMPP partners offer a broad portfolio of megafunctions
optimized for Altera devices.
f For a complete list of third-party IP for Altera FPGAs, refer to the Intellectual Property
& Reference Designs web page of the Altera website. For SOPC Builder components,
search for sopc_builder_ready in the IP MegaStore megafunction search function.
.
Table 10–1. Processor Interface Solutions Available from an Altera Device
Available in
SOPC Builder
Available In
MegaWizard
Plug-In Manager
Third-Party
Solution
OpenCore Plus
Evaluation
Available
RapidIO
v
v
v
v
PCI Express
v
v
v
v
PCI
v
v
v
v
PCI Lite
v
—
—
SPI
v
—
—
License not
required
Protocol
July 2011
Altera Corporation
Embedded Design Handbook
10–6
Chapter 10: Interfacing an External Processor to an Altera FPGA
RapidIO Interface
Table 10–2 summarizes the most popular options for peripheral expansion in SOPC
Builder systems that include an industry-standard processor. All of these are available
in SOPC Builder. Some are also available using the MegaWizard Plug-In Manager.
Table 10–2. Partial list of peripheral interfaces available for SOPC Builder
Available in
SOPC Builder
Available In
MegaWizard
Plug-In Manager
Third-Party Solution
OpenCore Plus
Evaluation Available
CAN
v
—
v
v
I2C
v
—
v
v
Ethernet
v
v
v
v
PIO
v
—
—
Not required
POS-PHY Level 4 (SPI 4.2)
—
v
—
v
SPI
v
—
v
Not required
UART
v
—
v
v
USB
v
—
v
v
Protocol
f For detailed information about the components available in SOPC builder refer to the
Embedded Peripherals IP User Guide.
1
In some cases, you must download third-party IP solutions from the AMPP vendor
website, before you can evaluate the peripheral using the OpenCore Plus.
f For more information about the AMPP program and OpenCore Plus refer to
AN343: OpenCore Evaluation of AMPP Megafunctions and AN320: OpenCore Plus
Evaluation of Megafunctions.
The following sections discuss the high-performance interfaces that you can use to
interface to an external processor.
RapidIO Interface
RapidIO is a high-performance packet-switched protocol that transports data and
control information between processors, memories, and peripheral devices. The
RapidIO MegaCore function is available in SOPC Builder includes Avalon-MM ports
that translate Serial RapidIO transactions into Avalon-MM transactions. The
MegaCore function also includes an optional Avalon Streaming (Avalon-ST) interface
that you can use to send transactions directly from the transport layer to the system
interconnect fabric. When you select all optional features, the core includes the
following ports:
■
Avalon-MM I/O write master
■
Avalon-MM I/O read master
■
Avalon-MM I/O write slave
■
Avalon-MM I/O read slave
■
Avalon-MM maintenance master
■
Avalon-MM system maintenance slave
Embedded Design Handbook
July 2011 Altera Corporation
Chapter 10: Interfacing an External Processor to an Altera FPGA
RapidIO Interface
10–7
■
Avalon Streaming sink pass-through TX
■
Avalon-ST source pass-through RX
Using the SOPC Builder design flow, you can integrate a RapidIO endpoint in an
SOPC Builder system. You connect the ports using the SOPC Builder System
Contents tab and SOPC Builder automatically generates the system interconnect
fabric. Figure 10–5 illustrates an SOPC Builder system that includes a processor and a
RapidIO MegaCore function.
Figure 10–5. Example system with RapidIO Interface
Processor
Serial RapidIO Switch
FPGA
RapidIO MegaCore Function
Physical Layer
Transport Layer
Logical Layer
Src
M
Snk
S
M
S
M
S
System Interconnect Fabric
M
Avalon-MM Master I/F
M
Avalon-MM Slave I/F
Src
Avalon Streaming Source I/F
Snk
Avalon Streaming Sink I/F
Memory
Controller
S
Flash
Cntl
S
S
S
UART
USB
User I/O
f Refer to the RapidIO trade association web site's product list at www.rapidio.org for a
list of processors that support a Rapid IO interface.
July 2011
Altera Corporation
Embedded Design Handbook
10–8
Chapter 10: Interfacing an External Processor to an Altera FPGA
PCI Express Interface
f Refer to the following documents for a complete description of the RapidIO
MegaCore function:
■
RapidIO MegaCore Function User Guide
■
AN513: RapidIO Interoperability With TI 6482 DSP Reference Design
PCI Express Interface
The Altera IP Compiler for PCI Express configured using the SOPC Builder design
flow uses the IP Compiler for PCI Express's Avalon-MM bridge module to connect the
IP Compiler for PCI Express component to the system interconnect fabric. The bridge
facilitates the design of PCI Express systems that use the Avalon-MM interface to
access SOPC Builder components. Figure 10–6 illustrates a design that links an
external processor to an SOPC Builder system using the IP Compiler for PCI Express.
You can also implement the IP Compiler for PCI Express using the MegaWizard
Plug-In Manager design flow. The configuration options for the two design flows are
different. The IP Compiler for PCI Express is available in Stratix IV and Arria II GX
devices as a hard IP implementation and can be used as a root port or end point. In
Stratix V devices, Altera provides the Stratix V Hard IP for PCI Express.
f For more information about using the IP Compiler for PCI Express refer to the
following documents:
■
IP Compiler for PCI Express User Guide
■
AN532: An SOPC Builder PCI Express Design with GUI Interface
■
AN456: PCI Express High Performance Reference Design
■
AN443: External PHY Support in PCI Express MegaCore Functions
■
AN431: PCI Express to External Memory Reference Design
Embedded Design Handbook
July 2011 Altera Corporation
Chapter 10: Interfacing an External Processor to an Altera FPGA
PCI Interface
10–9
Figure 10–6 shows an example system in which an external processor communicates
with an Altera FPGA through a PCI Express link.
Figure 10–6. Example system with PCI Express interface
Processor
PCI Express Link
FPGA
PCI Express MegaCore Function
Physical Layer
Data Link Layer
Transaction Layer
Avalon-MM Adapter
S
M
System Interconnect Fabric
M
Avalon-MM Master I/F
M
Avalon-MM Slave I/F
Memory
Controller
S
S
S
S
Flash
Cntl
UART
USB
User I/O
PCI Interface
Altera offers a wide range of PCI local bus solutions that you can use to connect a host
processor to an FPGA. You can implement the PCI MegaCore function using the
MegaWizard Plug-In Manager or SOPC Builder design flow.
July 2011
Altera Corporation
Embedded Design Handbook
10–10
Chapter 10: Interfacing an External Processor to an Altera FPGA
PCI Lite Interface
The PCI SOPC Builder flow is an easy way to implement a complete Avalon-MM
system which includes peripherals to expand system functionality without having to
be well-acquainted with the Avalon-MM protocol. Figure 10–7 illustrates an SOPC
Builder system using the PCI MegaCore function. You can parameterize the PCI
MegaCore function with a 32- or 64-bit interface.
Figure 10–7. PCI MegaCore Function in an SOPC Builder System
Altera FPGA or HardCopy Device
PCI Master/Target
Component
DDR2
SDRAM
MegaCore
Function
PCI
Bus
PCI
MegaCore
Function
PCI-Avalon
Bridge
Logic
DDR2
SDRAM
Memory
Module
System
Interconnect
Fabric
DMA
Engine
f For more information refer to the PCI Compiler User Guide.
PCI Lite Interface
The PCI Lite component is optimized for low-latency and high throughput designs. It
is available only in the SOPC Builder design flow. The PCI Lite core provides a subset
of the PCI MegaCore function feature set to obtain a low-latency path that interfaces
to a processor and other peripherals connected to the system interconnect fabric in an
FPGA. This component translates PCI transactions to Avalon-MM transactions. The
PCI Lite core uses the PCI-Avalon bridge to connect the PCI bus to the system
interconnect fabric, allowing you to easily create simple PCI systems that include one
or more SOPC Builder components.
f For more information refer to the PCI Lite Core chapter in the Embedded Peripherals IP
User Guide.
You can also implement the original PCI master/target and target MegaCore
functions without an Avalon-MM bridge module using the MegaWizard Plug-In
Manager design flow.
f For more information, refer to AN223: PCI-to-DDR SDRAM Reference Design.
Embedded Design Handbook
July 2011 Altera Corporation
Chapter 10: Interfacing an External Processor to an Altera FPGA
Serial Protocol Interface (SPI)
10–11
Serial Protocol Interface (SPI)
The SPI Slave to Avalon Master Bridge component provides a simple connection
between processors and SOPC Builder systems through a four-wire industry standard
serial interface. Host systems can initiate Avalon-MM transactions by sending
encoded streams of bytes through the core's serial interface. The core supports read
and write transactions to the SOPC Builder system for memory access and peripheral
expansion.
The SPI Slave to Avalon Master Bridge is an SOPC Builder-ready component that
integrates easily into any SOPC Builder system. Processors that include an SPI
interface can easily encapsulate Avalon-MM transactions for reads and writes using
the protocols outlined in the SPI Slave/JTAG to Avalon Master Bridge Cores chapter of
the Embedded Peripherals IP User Guide.
Figure 10–8. Example System with SPI to Avalon-MM Interface Component
Altera FPGA
Processor
MOSI
SPI
MISO
SPI to
Avalon-MM
SPI IF Component
M
DMA
On-Chip
Memory
M
S
System Interconnect Fabric
M
S
Avalon-MM Master
Avalon-MM Slave
Memory
Controller
S
S
S
S
UART
UART
USB
User I/O
f Details of each protocol layer can be found in the following chapters of the Embedded
Peripherals IP User Guide:
SPI Slave/JTAG to Avalon Master Bridge Cores—Provide a connection from an external
host system to an SOPC Builder system. Allow an SPI master to initiate Avalon-MM
transactions.
Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores—Provide a connection
from an external host system to an SOPC Builder system. Allow an SPI master to
initiate Avalon-ST transactions.
Avalon Packets to Transactions Converter Core—Receives streaming data from upstream
components and initiates Avalon-MM transactions. Returns Avalon-MM transaction
responses to requesting components.
July 2011
Altera Corporation
Embedded Design Handbook
10–12
Chapter 10: Interfacing an External Processor to an Altera FPGA
Custom Bridge Interfaces
f The SPI Slave to Avalon Master Bridge Design Example demonstrates SPI transactions
between an Avalon-MM host system and a remote SPI system.
Custom Bridge Interfaces
Many bus protocols can be mapped to the system interconnect fabric either directly or
with some custom bridge interface logic to compensate for differences between the
interface standards. The Avalon-MM interface standard, which SOPC Builder
supports, is a synchronous, memory-mapped interface that is easy to create custom
bridges for.
If required, you can use the component editor available in SOPC Builder to quickly
define a custom bridge component to adapt the external processor bus to the
Avalon-MM interface or any other standard interface that is defined in the Avalon
Interfaces Specifications. The Templates menu available in the component editor
includes menu items to add any of the standard Avalon interfaces to your custom
bridge. You can then use the Interfaces tab of the component editor to modify timing
parameters including: Setup, Read Wait, Write Wait, and Hold timing parameters, if
required.
f For more information about the component editor, refer to the Component Editor
chapter in the SOPC Builder User Guide.
1
The Avalon-MM protocol requires that all masters provide byte addresses.
Consequently, it may be necessary for your custom bridge component to add address
wires when translating from the external processor bus interface to the Avalon-MM
interface. For example, if your processor bus has a 16-bit word address, you must add
one additional low-order address bit. If processor bus drives 32-bit word addresses,
you must add two additional, low-order address bits. In both cases, the extra bits
should be tied to 0. The external processor accesses individual byte lanes using the
byte enable signals.
Consider the following points when designing a custom bridge to interface between
an external processor and the Avalon-MM interface:
■
The processor bus signals must comply or be adapted with logic to comply with
the signals used for transactions, as described in the Avalon Interfaces Specifications.
■
The external processor must support the Avalon waitrequest signal that inserts
wait-state cycles for slave components
■
The system bus must have a bus reference clock to drive SOPC Builder interface
logic in the FPGA.
■
No time-out mechanism is available if you are using the Avalon-MM interface.
Embedded Design Handbook
July 2011 Altera Corporation
Chapter 10: Interfacing an External Processor to an Altera FPGA
Custom Bridge Interfaces
■
10–13
You must analyze the timing requirements of the system. You should perform a
timing analysis to guarantee that all synchronous timing requirements for the
external processor and Avalon-MM interface are met. Examine the following
timing characteristics:
■
Data tSU, tH , and tCO times to the bus reference clock
■
fMAX of the system matches the performance of the bus reference clock
■
Turn-around time for a read-to-write transfer or a write-to-read transfer for the
processor is well understood
If your processor has dedicated read and write buses, you can map them to the
Avalon-MM readdata and writedata signals. If your processor uses a bidirectional
data bus, the bridge component can implement the tristate logic controlled by the
processor’s output enable signal to merge the readdata and writedata signals into a
bidirectional data bus at the pins of the FPGA. Most of the other processor signals can
pass through the bridge component if they adhere to the Avalon-MM protocol.
Figure 10–9 illustrates the use of a bridge component with a 32-bit external processor.
Figure 10–9. Custom Bridge to Adapt an External Processor to an Avalon-MM Slave Interface
Altera FPGA or HardCopy Device
Custom Bridge
Custom Component
Avalon-MM Slave
ready
waitrequest_n
Wr_n & chipselect
write_n
Rd_n & chipselect
read_n
chipselect
External
Processor
(32-bit)
Wr_n
Rd_n
address[n:2]
BE[3:0]
data[31:0]
address[n:2 || 2b’00]
BE[3:0]
address [n:0]
byteenable[3:0]
writedata[31:0]
readdata[31:0]
OE_n
f For more information about designing with the Avalon-MM interface refer to the
Avalon Interfaces Specifications.
July 2011
Altera Corporation
Embedded Design Handbook
10–14
Chapter 10: Interfacing an External Processor to an Altera FPGA
Conclusion
Conclusion
Altera offers a variety of components that you can use to connect an FPGA to an
external processor. With most of these components, you can choose either the SOPC
Builder or MegaWizard Plug-In Manager design flow. You can also build your own
custom interface to an external processor. By using the Avalon-MM interface in SOPC
Builder, you can easily extend system capabilities for processors by taking advantage
of the SOPC Builder library of components.
Document Revision History
Table 10–3 shows the revision history for this document.
Table 10–3. Document Revision History
Date
Version
Changes
July 2011
1.1
Updated references.
February 2009
1.0
Initial release.
Embedded Design Handbook
July 2011 Altera Corporation
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